1352 files changed, 108381 insertions, 19692 deletions

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 2dbe6325f33..0f27e67abb9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -565,7 +565,7 @@ coreboot test.py:
     - export USE_LABGRID_SJG=1
     # export verbose="-v"
     - ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
-        --capture=tee-sys -k "not bootstd" || ret=$?
+        --capture=tee-sys -k "not bootstd ${TEST_PY_TEST_SPEC}" || ret=$?
     - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
     - if [[ $ret -ne 0 ]]; then
         exit $ret;
@@ -702,3 +702,9 @@ vf2:
   variables:
     ROLE: vf2
   <<: *lab_dfn
+
+qemu-x86_64:
+  variables:
+    ROLE: qemu-x86_64
+    TEST_PY_TEST_SPEC: "and not sleep"
+  <<: *lab_dfn
diff --git a/.mailmap b/.mailmap
index ff85151702f..85086602cd5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -76,6 +76,7 @@ Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
 Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
 Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
+Mattijs Korpershoek <mkorpershoek@kernel.org> <mkorpershoek@baylibre.com>
 Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
 Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
 Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
diff --git a/Kconfig b/Kconfig
index 70dc385dd2f..a508c5430f0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -748,7 +748,7 @@ source "dts/Kconfig"
 
 source "env/Kconfig"
 
-menu Networking
+menu "Networking"
 
 choice
 	prompt "Networking stack"
diff --git a/MAINTAINERS b/MAINTAINERS
index 92d4a158fd0..a0b06e9ee24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -66,7 +66,7 @@ F:	lib/alist.c
 F:	test/lib/alist.c
 
 ANDROID AB
-M:	Mattijs Korpershoek <mkorpershoek@baylibre.com>
+M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 R:	Igor Opaniuk <igor.opaniuk@gmail.com>
 R:	Sam Protsenko <semen.protsenko@linaro.org>
 S:	Maintained
@@ -77,7 +77,7 @@ F:	include/android_ab.h
 F:	test/py/tests/test_android/test_ab.py
 
 ANDROID AVB
-M:	Mattijs Korpershoek <mkorpershoek@baylibre.com>
+M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 R:	Igor Opaniuk <igor.opaniuk@gmail.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
@@ -987,7 +987,7 @@ F:	net/eth_bootdevice.c
 F:	test/boot/
 
 BOOTMETH_ANDROID
-M:	Mattijs Korpershoek <mkorpershoek@baylibre.com>
+M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
 F:	boot/bootmeth_android.c
@@ -1066,7 +1066,7 @@ N:	OF_UPSTREAM
 
 DFU
 M:	Lukasz Majewski <lukma@denx.de>
-M:	Mattijs Korpershoek <mkorpershoek@baylibre.com>
+M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
 F:	cmd/dfu.c
@@ -1178,7 +1178,7 @@ F:	test/common/event.c
 F:	test/py/tests/test_event_dump.py
 
 FASTBOOT
-M:	Mattijs Korpershoek <mkorpershoek@baylibre.com>
+M:	Mattijs Korpershoek <mkorpershoek@kernel.org>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
 F:	cmd/fastboot.c
@@ -1281,6 +1281,13 @@ T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/video/mali_dp.c
 F:	drivers/i2c/i2c-versatile.c
 
+MEMBUF
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/u-boot.git
+F:	include/membuf.h
+F:	lib/membuf.c
+
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
diff --git a/Makefile b/Makefile
index ea6ca427496..e83672b1823 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -406,6 +406,7 @@ LDR		= $(CROSS_COMPILE)ldr
 STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
+READELF		= $(CROSS_COMPILE)readelf
 LEX		= flex
 YACC		= bison
 AWK		= awk
@@ -820,6 +821,7 @@ KBUILD_AFLAGS += $(KAFLAGS)
 KBUILD_CFLAGS += $(KCFLAGS)
 
 KBUILD_LDFLAGS  += -z noexecstack
+KBUILD_LDFLAGS  += -z norelro
 KBUILD_LDFLAGS  += $(call ld-option,--no-warn-rwx-segments)
 
 KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
@@ -1065,7 +1067,7 @@ quiet_cmd_objcopy = OBJCOPY $@
 cmd_objcopy = $(OBJCOPY) --gap-fill=0xff $(OBJCOPYFLAGS) \
 	$(OBJCOPYFLAGS_$(@F)) $< $@
 
-# Provide a version which does not do this, for use by EFI
+# Provide a version which does not do this, for use by EFI and hex/srec
 quiet_cmd_zobjcopy = OBJCOPY $@
 cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 
@@ -1280,7 +1282,7 @@ OBJCOPYFLAGS_u-boot.hex := -O ihex
 OBJCOPYFLAGS_u-boot.srec := -O srec
 
 u-boot.hex u-boot.srec: u-boot FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 OBJCOPYFLAGS_u-boot-elf.srec := $(OBJCOPYFLAGS_u-boot.srec)
 
@@ -1294,12 +1296,12 @@ OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000
 endif
 
 u-boot-elf.srec: u-boot.elf FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 OBJCOPYFLAGS_u-boot-spl.srec = $(OBJCOPYFLAGS_u-boot.srec)
 
 spl/u-boot-spl.srec: spl/u-boot-spl FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 %.scif: %.srec
 	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
@@ -1434,7 +1436,7 @@ OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
 
 u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
@@ -2175,7 +2177,7 @@ System.map:	u-boot
 # ARM relocations should all be R_ARM_RELATIVE (32-bit) or
 # R_AARCH64_RELATIVE (64-bit).
 checkarmreloc: u-boot
-	@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
+	@RELOC="`$(READELF) -r -W $< | cut -d ' ' -f 4 | \
 		grep R_A | sort -u`"; \
 	if test "$$RELOC" != "R_ARM_RELATIVE" -a \
 		 "$$RELOC" != "R_AARCH64_RELATIVE"; then \
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf08fe63f1e..b7311d3b754 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -600,6 +600,13 @@ choice
 	prompt "Target select"
 	default TARGET_HIKEY
 
+config ARCH_AIROHA
+	bool "Airoha SoCs"
+	select DM
+	select OF_CONTROL
+	help
+	  Support for the Airoha soc.
+
 config ARCH_AT91
 	bool "Atmel AT91"
 	select GPIO_EXTRA_HEADER
@@ -648,7 +655,6 @@ config ARCH_MVEBU
 	select SPL_TIMER if SPL
 	select TIMER if !ARM64
 	select OF_CONTROL
-	select OF_SEPARATE
 	select SPI
 	imply CMD_DM
 
@@ -1110,13 +1116,14 @@ config ARCH_SNAPDRAGON
 	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select OF_CONTROL
-	select OF_SEPARATE
 	select SMEM
 	select SPMI
 	select BOARD_LATE_INIT
 	select OF_BOARD
 	select SAVE_PREV_BL_FDT_ADDR
 	select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
+	select SYSRESET
+	select SYSRESET_PSCI
 	imply OF_UPSTREAM
 	imply CMD_DM
 
@@ -1185,7 +1192,6 @@ config ARCH_SUNXI
 	select DM_SERIAL
 	select OF_BOARD_SETUP
 	select OF_CONTROL
-	select OF_SEPARATE
 	select PINCTRL
 	select SPECIFY_CONSOLE_INDEX
 	select SPL_SEPARATE_BSS if SPL
@@ -2251,6 +2257,8 @@ config SYS_KWD_CONFIG
 	  Path within the source directory to the kwbimage.cfg file to use
 	  when packaging the U-Boot image for use.
 
+source "arch/arm/mach-airoha/Kconfig"
+
 source "arch/arm/mach-apple/Kconfig"
 
 source "arch/arm/mach-aspeed/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7334e79965f..5ecadb2ef1b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -51,6 +51,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_AIROHA)		+= airoha
 machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 12ae9bd0603..1c1e33bec24 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -575,8 +575,12 @@ static void pretty_print_block_attrs(u64 pte)
 
 	if (perm_attrs & PTE_BLOCK_PXN)
 		cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN ");
-	if (perm_attrs & PTE_BLOCK_UXN)
-		cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN ");
+	if (perm_attrs & PTE_BLOCK_UXN) {
+		if (get_effective_el() == 1)
+			cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN ");
+		else
+			cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "XN ");
+	}
 	if (perm_attrs & PTE_BLOCK_RO)
 		cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO");
 	if (!mem_attrs[0])
@@ -1039,13 +1043,29 @@ int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
 
 	switch (perm) {
 	case MMU_ATTR_RO:
-		attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO;
+		/*
+		 * get_effective_el() will return 1 if
+		 * - Running in EL1 so we assume an EL1 translation regime
+		 *   with HCR_EL2.{NV, NV1} != {1,1}
+		 * - Running in EL2 with HCR_EL2.E2H = 1 so we assume an
+		 *   EL2&0 translation regime. Since we don't have accesses
+		 *   from EL0 we don't have to check HCR_EL2.TGE
+		 *
+		 * Both of these requires PXN to be set
+		 */
+		if (get_effective_el() == 1)
+			attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO;
+		else
+			attrs |= PTE_BLOCK_UXN | PTE_BLOCK_RO;
 		break;
 	case MMU_ATTR_RX:
 		attrs |= PTE_BLOCK_RO;
 		break;
 	case MMU_ATTR_RW:
-		attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+		if (get_effective_el() == 1)
+			attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+		else
+			attrs |= PTE_BLOCK_UXN;
 		break;
 	default:
 		log_err("Unknown attribute %d\n", perm);
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 939869b9ffa..f7707acdf1a 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -63,9 +63,12 @@ ENTRY(return_to_fel)
 1:	wfi
 	b	1b
 
+fel_stash_addr:			// must immediately precede back_in_32:
+	.word   0x00000000	// receives fel_stash addr, by AA64 code above
+
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe51f000c	// ldr	r0, [pc, #-12]  ; load fel_stash address
 	.word	0xe5901008	// ldr	r1, [r0, #8]
 	.word	0xe129f001	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
@@ -77,6 +80,4 @@ back_in_32:
 	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
 	.word	0xe12fff1e	// bx	lr		; return to FEL
-fel_stash_addr:
-	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 2f50087f57a..817e7a983ae 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -169,15 +169,6 @@ SECTIONS
 	_end = .;
 	_image_binary_end = .;
 
-	/*
-	 * Deprecated: this MMU section is used by pxa at present but
-	 * should not be used by new boards/CPUs.
-	 */
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
 /*
  * These sections occupy the same memory, but their lifetimes do
  * not overlap: U-Boot initializes .bss only after applying dynamic
@@ -190,14 +181,14 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	.dynsym _image_binary_end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu.hash : { *(.gnu.hash) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu.hash) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2ef8f838af7..080ea522ed5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra30-lg-p880.dtb \
 	tegra30-lg-p895.dtb \
 	tegra30-microsoft-surface-rt.dtb \
+	tegra30-ouya.dtb \
 	tegra30-tec-ng.dtb \
 	tegra30-wexler-qc750.dtb \
 	tegra114-dalmore.dtb \
@@ -1102,10 +1103,11 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
 	k3-am654-r5-base-board.dtb
 
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
-			      k3-j7200-r5-common-proc-board.dtb \
 			      k3-j721e-r5-sk.dtb \
 			      k3-j721e-r5-beagleboneai64.dtb
 
+dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
+
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb
 
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
new file mode 100644
index 00000000000..0316b73f3a5
--- /dev/null
+++ b/arch/arm/dts/an7581-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		atf-reserved-memory@80000000 {
+			no-map;
+			reg = <0x0 0x80000000 0x0 0x40000>;
+		};
+	};
+};
+
+&uart1 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/en7581-evb-u-boot.dtsi b/arch/arm/dts/en7581-evb-u-boot.dtsi
new file mode 100644
index 00000000000..ebd3b8b4958
--- /dev/null
+++ b/arch/arm/dts/en7581-evb-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	/* When running as a first-stage bootloader this isn't filled in automatically */
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x20000000>;
+	};
+};
+
+#include "an7581-u-boot.dtsi"
diff --git a/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
new file mode 100644
index 00000000000..390e2338d65
--- /dev/null
+++ b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	/* Will be removed when SMEM parsing is updated */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x40000000>,
+		      <0x0 0x4a500000 0x0 0x00100000>;
+	};
+};
+
+&sdhc_1 {
+	sdhci-caps-mask = <0x0 0x04000000>;
+	sdhci-caps = <0x0 0x04000000>;	/* SDHCI_CAN_VDD_180 */
+
+	/*
+	 * This reset is needed to clear out the settings done by
+	 * previous boot loader. Without this the SDHCI_RESET_ALL
+	 * reset done sdhci_init() times out.
+	 */
+	resets = <&gcc GCC_SDCC_BCR>;
+};
diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
deleted file mode 100644
index f86a23404e6..00000000000
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A7 SoC family in Quad core configuration
- *
- * TRM: https://www.ti.com/lit/zip/spruj16
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62a.dtsi"
-
-/ {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0: cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-
-				core1 {
-					cpu = <&cpu1>;
-				};
-
-				core2 {
-					cpu = <&cpu2>;
-				};
-
-				core3 {
-					cpu = <&cpu3>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53";
-			reg = <0x000>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53";
-			reg = <0x001>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53";
-			reg = <0x002>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53";
-			reg = <0x003>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-	};
-
-	L2_0: l2-cache0 {
-		compatible = "cache";
-		cache-unified;
-		cache-level = <2>;
-		cache-size = <0x80000>;
-		cache-line-size = <64>;
-		cache-sets = <512>;
-	};
-};
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
index 4a82d2fd222..2f119508e18 100644
--- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -1,10 +1,109 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-sk.dtb"
+#define BOARD_DESCRIPTION "k3-am69-sk"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 board"
+
 #include "k3-j784s4-binman.dtsi"
 
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-am69-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j784s4-hs-evm.bin";
+	};
+
+	tiboot3-am69-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j784s4-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form.  See j784s4_evm.h
+#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
+
+&capsule_tiboot3 {
+	efi-capsule {
+		image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
+
+		blob {
+			filename = "tiboot3-j784s4-hs-fs-evm.bin";
+		};
+	};
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form.  See j784s4_evm.h
+#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
+#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
+
+&capsule_tispl {
+	efi-capsule {
+		image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
+	};
+};
+
+&capsule_uboot {
+	efi-capsule {
+		image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
+	};
+};
+
+#endif
+
 / {
 	memory@80000000 {
 		bootph-all;
@@ -23,25 +122,3 @@
 	bootph-pre-ram;
 };
 
-#ifdef CONFIG_TARGET_J784S4_A72_EVM
-
-#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb"
-#define AM69_SK_DTB "u-boot.dtb"
-
-&spl_j784s4_evm_dtb {
-	filename = SPL_AM69_SK_DTB;
-};
-
-&j784s4_evm_dtb {
-	filename = AM69_SK_DTB;
-};
-
-&spl_j784s4_evm_dtb_unsigned {
-	filename = SPL_AM69_SK_DTB;
-};
-
-&j784s4_evm_dtb_unsigned {
-	filename = AM69_SK_DTB;
-};
-
-#endif
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index ef7d4594f69..423badd7cb5 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -7,46 +7,6 @@
 
 #ifdef CONFIG_TARGET_J7200_R5_EVM
 
-&bcfg_yaml {
-	config = "board-cfg_j7200.yaml";
-};
-
-&rcfg_yaml {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml {
-	config = "pm-cfg_j7200.yaml";
-};
-
-&scfg_yaml {
-	config = "sec-cfg_j7200.yaml";
-};
-
-&bcfg_yaml_tifs {
-	config = "board-cfg_j7200.yaml";
-};
-
-&rcfg_yaml_tifs {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml_tifs {
-	config = "pm-cfg_j7200.yaml";
-};
-
-&scfg_yaml_tifs {
-	config = "sec-cfg_j7200.yaml";
-};
-
-&rcfg_yaml_dm {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml_dm {
-	config = "pm-cfg_j7200.yaml";
-};
-
 &binman {
 	tiboot3-j7200-hs-evm.bin {
 		filename = "tiboot3-j7200-hs-evm.bin";
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index ecb1dd49c64..9ac29110324 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -120,3 +120,10 @@
 	vdd-supply-2 = <&buckb1>;
 	bootph-pre-ram;
 };
+
+&tps659414 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
new file mode 100644
index 00000000000..a64d19b05f3
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
@@ -0,0 +1,8756 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0
+ */
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 0
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
+
+#define DDRSS0_CTL_00_DATA 0x00000B00
+#define DDRSS0_CTL_01_DATA 0x00000000
+#define DDRSS0_CTL_02_DATA 0x00000000
+#define DDRSS0_CTL_03_DATA 0x00000000
+#define DDRSS0_CTL_04_DATA 0x00000000
+#define DDRSS0_CTL_05_DATA 0x00000000
+#define DDRSS0_CTL_06_DATA 0x00000000
+#define DDRSS0_CTL_07_DATA 0x00002AF8
+#define DDRSS0_CTL_08_DATA 0x0001ADAF
+#define DDRSS0_CTL_09_DATA 0x00000005
+#define DDRSS0_CTL_10_DATA 0x0000006E
+#define DDRSS0_CTL_11_DATA 0x000681C8
+#define DDRSS0_CTL_12_DATA 0x004111C9
+#define DDRSS0_CTL_13_DATA 0x00000005
+#define DDRSS0_CTL_14_DATA 0x000010A9
+#define DDRSS0_CTL_15_DATA 0x000681C8
+#define DDRSS0_CTL_16_DATA 0x004111C9
+#define DDRSS0_CTL_17_DATA 0x00000005
+#define DDRSS0_CTL_18_DATA 0x000010A9
+#define DDRSS0_CTL_19_DATA 0x01010000
+#define DDRSS0_CTL_20_DATA 0x02011001
+#define DDRSS0_CTL_21_DATA 0x02010000
+#define DDRSS0_CTL_22_DATA 0x00020100
+#define DDRSS0_CTL_23_DATA 0x0000000B
+#define DDRSS0_CTL_24_DATA 0x0000001C
+#define DDRSS0_CTL_25_DATA 0x00000000
+#define DDRSS0_CTL_26_DATA 0x00000000
+#define DDRSS0_CTL_27_DATA 0x03020200
+#define DDRSS0_CTL_28_DATA 0x00005656
+#define DDRSS0_CTL_29_DATA 0x00100000
+#define DDRSS0_CTL_30_DATA 0x00000000
+#define DDRSS0_CTL_31_DATA 0x00000000
+#define DDRSS0_CTL_32_DATA 0x00000000
+#define DDRSS0_CTL_33_DATA 0x00000000
+#define DDRSS0_CTL_34_DATA 0x040C0000
+#define DDRSS0_CTL_35_DATA 0x12481248
+#define DDRSS0_CTL_36_DATA 0x00050804
+#define DDRSS0_CTL_37_DATA 0x09040008
+#define DDRSS0_CTL_38_DATA 0x15000204
+#define DDRSS0_CTL_39_DATA 0x1760008B
+#define DDRSS0_CTL_40_DATA 0x1500422B
+#define DDRSS0_CTL_41_DATA 0x1760008B
+#define DDRSS0_CTL_42_DATA 0x2000422B
+#define DDRSS0_CTL_43_DATA 0x000A0A09
+#define DDRSS0_CTL_44_DATA 0x0400078A
+#define DDRSS0_CTL_45_DATA 0x1E161104
+#define DDRSS0_CTL_46_DATA 0x10012458
+#define DDRSS0_CTL_47_DATA 0x1E161110
+#define DDRSS0_CTL_48_DATA 0x10012458
+#define DDRSS0_CTL_49_DATA 0x02030410
+#define DDRSS0_CTL_50_DATA 0x2C040500
+#define DDRSS0_CTL_51_DATA 0x08292C29
+#define DDRSS0_CTL_52_DATA 0x14000E0A
+#define DDRSS0_CTL_53_DATA 0x04010A0A
+#define DDRSS0_CTL_54_DATA 0x01010004
+#define DDRSS0_CTL_55_DATA 0x04545408
+#define DDRSS0_CTL_56_DATA 0x04313104
+#define DDRSS0_CTL_57_DATA 0x00003131
+#define DDRSS0_CTL_58_DATA 0x00010100
+#define DDRSS0_CTL_59_DATA 0x03010000
+#define DDRSS0_CTL_60_DATA 0x00001508
+#define DDRSS0_CTL_61_DATA 0x000000CE
+#define DDRSS0_CTL_62_DATA 0x0000032B
+#define DDRSS0_CTL_63_DATA 0x00002073
+#define DDRSS0_CTL_64_DATA 0x0000032B
+#define DDRSS0_CTL_65_DATA 0x00002073
+#define DDRSS0_CTL_66_DATA 0x00000005
+#define DDRSS0_CTL_67_DATA 0x00050000
+#define DDRSS0_CTL_68_DATA 0x00CB0012
+#define DDRSS0_CTL_69_DATA 0x00CB0408
+#define DDRSS0_CTL_70_DATA 0x00400408
+#define DDRSS0_CTL_71_DATA 0x00120103
+#define DDRSS0_CTL_72_DATA 0x00100005
+#define DDRSS0_CTL_73_DATA 0x2F080010
+#define DDRSS0_CTL_74_DATA 0x0505012F
+#define DDRSS0_CTL_75_DATA 0x0401030A
+#define DDRSS0_CTL_76_DATA 0x041E100B
+#define DDRSS0_CTL_77_DATA 0x100B0401
+#define DDRSS0_CTL_78_DATA 0x0001041E
+#define DDRSS0_CTL_79_DATA 0x00160016
+#define DDRSS0_CTL_80_DATA 0x033B033B
+#define DDRSS0_CTL_81_DATA 0x033B033B
+#define DDRSS0_CTL_82_DATA 0x03050505
+#define DDRSS0_CTL_83_DATA 0x03010303
+#define DDRSS0_CTL_84_DATA 0x200B100B
+#define DDRSS0_CTL_85_DATA 0x04041004
+#define DDRSS0_CTL_86_DATA 0x200B100B
+#define DDRSS0_CTL_87_DATA 0x04041004
+#define DDRSS0_CTL_88_DATA 0x03010000
+#define DDRSS0_CTL_89_DATA 0x00010000
+#define DDRSS0_CTL_90_DATA 0x00000000
+#define DDRSS0_CTL_91_DATA 0x00000000
+#define DDRSS0_CTL_92_DATA 0x01000000
+#define DDRSS0_CTL_93_DATA 0x80104002
+#define DDRSS0_CTL_94_DATA 0x00000000
+#define DDRSS0_CTL_95_DATA 0x00040005
+#define DDRSS0_CTL_96_DATA 0x00000000
+#define DDRSS0_CTL_97_DATA 0x00050000
+#define DDRSS0_CTL_98_DATA 0x00000004
+#define DDRSS0_CTL_99_DATA 0x00000000
+#define DDRSS0_CTL_100_DATA 0x00040005
+#define DDRSS0_CTL_101_DATA 0x00000000
+#define DDRSS0_CTL_102_DATA 0x00003380
+#define DDRSS0_CTL_103_DATA 0x00003380
+#define DDRSS0_CTL_104_DATA 0x00003380
+#define DDRSS0_CTL_105_DATA 0x00003380
+#define DDRSS0_CTL_106_DATA 0x00003380
+#define DDRSS0_CTL_107_DATA 0x00000000
+#define DDRSS0_CTL_108_DATA 0x000005A2
+#define DDRSS0_CTL_109_DATA 0x00081CC0
+#define DDRSS0_CTL_110_DATA 0x00081CC0
+#define DDRSS0_CTL_111_DATA 0x00081CC0
+#define DDRSS0_CTL_112_DATA 0x00081CC0
+#define DDRSS0_CTL_113_DATA 0x00081CC0
+#define DDRSS0_CTL_114_DATA 0x00000000
+#define DDRSS0_CTL_115_DATA 0x0000E325
+#define DDRSS0_CTL_116_DATA 0x00081CC0
+#define DDRSS0_CTL_117_DATA 0x00081CC0
+#define DDRSS0_CTL_118_DATA 0x00081CC0
+#define DDRSS0_CTL_119_DATA 0x00081CC0
+#define DDRSS0_CTL_120_DATA 0x00081CC0
+#define DDRSS0_CTL_121_DATA 0x00000000
+#define DDRSS0_CTL_122_DATA 0x0000E325
+#define DDRSS0_CTL_123_DATA 0x00000000
+#define DDRSS0_CTL_124_DATA 0x00000000
+#define DDRSS0_CTL_125_DATA 0x00000000
+#define DDRSS0_CTL_126_DATA 0x00000000
+#define DDRSS0_CTL_127_DATA 0x00000000
+#define DDRSS0_CTL_128_DATA 0x00000000
+#define DDRSS0_CTL_129_DATA 0x00000000
+#define DDRSS0_CTL_130_DATA 0x00000000
+#define DDRSS0_CTL_131_DATA 0x0B030500
+#define DDRSS0_CTL_132_DATA 0x00040B04
+#define DDRSS0_CTL_133_DATA 0x0A090000
+#define DDRSS0_CTL_134_DATA 0x0A090701
+#define DDRSS0_CTL_135_DATA 0x0900000E
+#define DDRSS0_CTL_136_DATA 0x0907010A
+#define DDRSS0_CTL_137_DATA 0x00000E0A
+#define DDRSS0_CTL_138_DATA 0x07010A09
+#define DDRSS0_CTL_139_DATA 0x000E0A09
+#define DDRSS0_CTL_140_DATA 0x07000401
+#define DDRSS0_CTL_141_DATA 0x00000000
+#define DDRSS0_CTL_142_DATA 0x00000000
+#define DDRSS0_CTL_143_DATA 0x00000000
+#define DDRSS0_CTL_144_DATA 0x00000000
+#define DDRSS0_CTL_145_DATA 0x00000000
+#define DDRSS0_CTL_146_DATA 0x00000000
+#define DDRSS0_CTL_147_DATA 0x00000000
+#define DDRSS0_CTL_148_DATA 0x08080000
+#define DDRSS0_CTL_149_DATA 0x01000000
+#define DDRSS0_CTL_150_DATA 0x800000C0
+#define DDRSS0_CTL_151_DATA 0x800000C0
+#define DDRSS0_CTL_152_DATA 0x800000C0
+#define DDRSS0_CTL_153_DATA 0x00000000
+#define DDRSS0_CTL_154_DATA 0x00001500
+#define DDRSS0_CTL_155_DATA 0x00000000
+#define DDRSS0_CTL_156_DATA 0x00000001
+#define DDRSS0_CTL_157_DATA 0x00000002
+#define DDRSS0_CTL_158_DATA 0x0000100E
+#define DDRSS0_CTL_159_DATA 0x00000000
+#define DDRSS0_CTL_160_DATA 0x00000000
+#define DDRSS0_CTL_161_DATA 0x00000000
+#define DDRSS0_CTL_162_DATA 0x00000000
+#define DDRSS0_CTL_163_DATA 0x00000000
+#define DDRSS0_CTL_164_DATA 0x000B0000
+#define DDRSS0_CTL_165_DATA 0x000E0006
+#define DDRSS0_CTL_166_DATA 0x000E0404
+#define DDRSS0_CTL_167_DATA 0x00D601AB
+#define DDRSS0_CTL_168_DATA 0x10100216
+#define DDRSS0_CTL_169_DATA 0x01AB0216
+#define DDRSS0_CTL_170_DATA 0x021600D6
+#define DDRSS0_CTL_171_DATA 0x02161010
+#define DDRSS0_CTL_172_DATA 0x00000000
+#define DDRSS0_CTL_173_DATA 0x00000000
+#define DDRSS0_CTL_174_DATA 0x00000000
+#define DDRSS0_CTL_175_DATA 0x3FF40084
+#define DDRSS0_CTL_176_DATA 0x33003FF4
+#define DDRSS0_CTL_177_DATA 0x00003333
+#define DDRSS0_CTL_178_DATA 0x35000000
+#define DDRSS0_CTL_179_DATA 0x27270035
+#define DDRSS0_CTL_180_DATA 0x0F0F0000
+#define DDRSS0_CTL_181_DATA 0x16000000
+#define DDRSS0_CTL_182_DATA 0x00841616
+#define DDRSS0_CTL_183_DATA 0x3FF43FF4
+#define DDRSS0_CTL_184_DATA 0x33333300
+#define DDRSS0_CTL_185_DATA 0x00000000
+#define DDRSS0_CTL_186_DATA 0x00353500
+#define DDRSS0_CTL_187_DATA 0x00002727
+#define DDRSS0_CTL_188_DATA 0x00000F0F
+#define DDRSS0_CTL_189_DATA 0x16161600
+#define DDRSS0_CTL_190_DATA 0x00000020
+#define DDRSS0_CTL_191_DATA 0x00000000
+#define DDRSS0_CTL_192_DATA 0x00000001
+#define DDRSS0_CTL_193_DATA 0x00000000
+#define DDRSS0_CTL_194_DATA 0x01000000
+#define DDRSS0_CTL_195_DATA 0x00000001
+#define DDRSS0_CTL_196_DATA 0x00000000
+#define DDRSS0_CTL_197_DATA 0x00000000
+#define DDRSS0_CTL_198_DATA 0x00000000
+#define DDRSS0_CTL_199_DATA 0x00000000
+#define DDRSS0_CTL_200_DATA 0x00000000
+#define DDRSS0_CTL_201_DATA 0x00000000
+#define DDRSS0_CTL_202_DATA 0x00000000
+#define DDRSS0_CTL_203_DATA 0x00000000
+#define DDRSS0_CTL_204_DATA 0x00000000
+#define DDRSS0_CTL_205_DATA 0x00000000
+#define DDRSS0_CTL_206_DATA 0x02000000
+#define DDRSS0_CTL_207_DATA 0x01080101
+#define DDRSS0_CTL_208_DATA 0x00000000
+#define DDRSS0_CTL_209_DATA 0x00000000
+#define DDRSS0_CTL_210_DATA 0x00000000
+#define DDRSS0_CTL_211_DATA 0x00000000
+#define DDRSS0_CTL_212_DATA 0x00000000
+#define DDRSS0_CTL_213_DATA 0x00000000
+#define DDRSS0_CTL_214_DATA 0x00000000
+#define DDRSS0_CTL_215_DATA 0x00000000
+#define DDRSS0_CTL_216_DATA 0x00000000
+#define DDRSS0_CTL_217_DATA 0x00000000
+#define DDRSS0_CTL_218_DATA 0x00000000
+#define DDRSS0_CTL_219_DATA 0x00000000
+#define DDRSS0_CTL_220_DATA 0x00000000
+#define DDRSS0_CTL_221_DATA 0x00000000
+#define DDRSS0_CTL_222_DATA 0x00001000
+#define DDRSS0_CTL_223_DATA 0x006403E8
+#define DDRSS0_CTL_224_DATA 0x00000000
+#define DDRSS0_CTL_225_DATA 0x00000000
+#define DDRSS0_CTL_226_DATA 0x00000000
+#define DDRSS0_CTL_227_DATA 0x15110000
+#define DDRSS0_CTL_228_DATA 0x00040C18
+#define DDRSS0_CTL_229_DATA 0xF000C000
+#define DDRSS0_CTL_230_DATA 0x0000F000
+#define DDRSS0_CTL_231_DATA 0x00000000
+#define DDRSS0_CTL_232_DATA 0x00000000
+#define DDRSS0_CTL_233_DATA 0xC0000000
+#define DDRSS0_CTL_234_DATA 0xF000F000
+#define DDRSS0_CTL_235_DATA 0x00000000
+#define DDRSS0_CTL_236_DATA 0x00000000
+#define DDRSS0_CTL_237_DATA 0x00000000
+#define DDRSS0_CTL_238_DATA 0xF000C000
+#define DDRSS0_CTL_239_DATA 0x0000F000
+#define DDRSS0_CTL_240_DATA 0x00000000
+#define DDRSS0_CTL_241_DATA 0x00000000
+#define DDRSS0_CTL_242_DATA 0x00030000
+#define DDRSS0_CTL_243_DATA 0x00000000
+#define DDRSS0_CTL_244_DATA 0x00000000
+#define DDRSS0_CTL_245_DATA 0x00000000
+#define DDRSS0_CTL_246_DATA 0x00000000
+#define DDRSS0_CTL_247_DATA 0x00000000
+#define DDRSS0_CTL_248_DATA 0x00000000
+#define DDRSS0_CTL_249_DATA 0x00000000
+#define DDRSS0_CTL_250_DATA 0x00000000
+#define DDRSS0_CTL_251_DATA 0x00000000
+#define DDRSS0_CTL_252_DATA 0x00000000
+#define DDRSS0_CTL_253_DATA 0x00000000
+#define DDRSS0_CTL_254_DATA 0x00000000
+#define DDRSS0_CTL_255_DATA 0x00000000
+#define DDRSS0_CTL_256_DATA 0x00000000
+#define DDRSS0_CTL_257_DATA 0x01000200
+#define DDRSS0_CTL_258_DATA 0x00370040
+#define DDRSS0_CTL_259_DATA 0x00020008
+#define DDRSS0_CTL_260_DATA 0x00400100
+#define DDRSS0_CTL_261_DATA 0x00400855
+#define DDRSS0_CTL_262_DATA 0x01000200
+#define DDRSS0_CTL_263_DATA 0x08550040
+#define DDRSS0_CTL_264_DATA 0x00000040
+#define DDRSS0_CTL_265_DATA 0x006B0003
+#define DDRSS0_CTL_266_DATA 0x0100006B
+#define DDRSS0_CTL_267_DATA 0x03030303
+#define DDRSS0_CTL_268_DATA 0x00000000
+#define DDRSS0_CTL_269_DATA 0x00000202
+#define DDRSS0_CTL_270_DATA 0x00001FFF
+#define DDRSS0_CTL_271_DATA 0x3FFF2000
+#define DDRSS0_CTL_272_DATA 0x03FF0000
+#define DDRSS0_CTL_273_DATA 0x000103FF
+#define DDRSS0_CTL_274_DATA 0x0FFF0B00
+#define DDRSS0_CTL_275_DATA 0x01010001
+#define DDRSS0_CTL_276_DATA 0x01010101
+#define DDRSS0_CTL_277_DATA 0x01180101
+#define DDRSS0_CTL_278_DATA 0x00030000
+#define DDRSS0_CTL_279_DATA 0x00000000
+#define DDRSS0_CTL_280_DATA 0x00000000
+#define DDRSS0_CTL_281_DATA 0x00000000
+#define DDRSS0_CTL_282_DATA 0x00000000
+#define DDRSS0_CTL_283_DATA 0x00000000
+#define DDRSS0_CTL_284_DATA 0x00000000
+#define DDRSS0_CTL_285_DATA 0x00000000
+#define DDRSS0_CTL_286_DATA 0x00040101
+#define DDRSS0_CTL_287_DATA 0x04010100
+#define DDRSS0_CTL_288_DATA 0x00000000
+#define DDRSS0_CTL_289_DATA 0x00000000
+#define DDRSS0_CTL_290_DATA 0x03030300
+#define DDRSS0_CTL_291_DATA 0x00000001
+#define DDRSS0_CTL_292_DATA 0x00000000
+#define DDRSS0_CTL_293_DATA 0x00000000
+#define DDRSS0_CTL_294_DATA 0x00000000
+#define DDRSS0_CTL_295_DATA 0x00000000
+#define DDRSS0_CTL_296_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0x00000000
+#define DDRSS0_CTL_298_DATA 0x00000000
+#define DDRSS0_CTL_299_DATA 0x00000000
+#define DDRSS0_CTL_300_DATA 0x00000000
+#define DDRSS0_CTL_301_DATA 0x00000000
+#define DDRSS0_CTL_302_DATA 0x00000000
+#define DDRSS0_CTL_303_DATA 0x00000000
+#define DDRSS0_CTL_304_DATA 0x00000000
+#define DDRSS0_CTL_305_DATA 0x00000000
+#define DDRSS0_CTL_306_DATA 0x00000000
+#define DDRSS0_CTL_307_DATA 0x00000000
+#define DDRSS0_CTL_308_DATA 0x00000000
+#define DDRSS0_CTL_309_DATA 0x00000000
+#define DDRSS0_CTL_310_DATA 0x00000000
+#define DDRSS0_CTL_311_DATA 0x00000000
+#define DDRSS0_CTL_312_DATA 0x00000000
+#define DDRSS0_CTL_313_DATA 0x01000000
+#define DDRSS0_CTL_314_DATA 0x00020201
+#define DDRSS0_CTL_315_DATA 0x01000101
+#define DDRSS0_CTL_316_DATA 0x01010001
+#define DDRSS0_CTL_317_DATA 0x00010101
+#define DDRSS0_CTL_318_DATA 0x050A0A03
+#define DDRSS0_CTL_319_DATA 0x10081F1F
+#define DDRSS0_CTL_320_DATA 0x00090310
+#define DDRSS0_CTL_321_DATA 0x0B0C030F
+#define DDRSS0_CTL_322_DATA 0x0B0C0306
+#define DDRSS0_CTL_323_DATA 0x0C090006
+#define DDRSS0_CTL_324_DATA 0x0100000C
+#define DDRSS0_CTL_325_DATA 0x08040801
+#define DDRSS0_CTL_326_DATA 0x00000004
+#define DDRSS0_CTL_327_DATA 0x00000000
+#define DDRSS0_CTL_328_DATA 0x00010000
+#define DDRSS0_CTL_329_DATA 0x00280D00
+#define DDRSS0_CTL_330_DATA 0x00000001
+#define DDRSS0_CTL_331_DATA 0x00030001
+#define DDRSS0_CTL_332_DATA 0x00000000
+#define DDRSS0_CTL_333_DATA 0x00000000
+#define DDRSS0_CTL_334_DATA 0x00000000
+#define DDRSS0_CTL_335_DATA 0x00000000
+#define DDRSS0_CTL_336_DATA 0x00000000
+#define DDRSS0_CTL_337_DATA 0x00000000
+#define DDRSS0_CTL_338_DATA 0x00000000
+#define DDRSS0_CTL_339_DATA 0x00000000
+#define DDRSS0_CTL_340_DATA 0x01000000
+#define DDRSS0_CTL_341_DATA 0x00000001
+#define DDRSS0_CTL_342_DATA 0x00010100
+#define DDRSS0_CTL_343_DATA 0x03030000
+#define DDRSS0_CTL_344_DATA 0x00000000
+#define DDRSS0_CTL_345_DATA 0x00000000
+#define DDRSS0_CTL_346_DATA 0x00000000
+#define DDRSS0_CTL_347_DATA 0x00000000
+#define DDRSS0_CTL_348_DATA 0x00000000
+#define DDRSS0_CTL_349_DATA 0x00000000
+#define DDRSS0_CTL_350_DATA 0x00000000
+#define DDRSS0_CTL_351_DATA 0x00000000
+#define DDRSS0_CTL_352_DATA 0x00000000
+#define DDRSS0_CTL_353_DATA 0x00000000
+#define DDRSS0_CTL_354_DATA 0x00000000
+#define DDRSS0_CTL_355_DATA 0x00000000
+#define DDRSS0_CTL_356_DATA 0x00000000
+#define DDRSS0_CTL_357_DATA 0x00000000
+#define DDRSS0_CTL_358_DATA 0x00000000
+#define DDRSS0_CTL_359_DATA 0x00000000
+#define DDRSS0_CTL_360_DATA 0x000556AA
+#define DDRSS0_CTL_361_DATA 0x000AAAAA
+#define DDRSS0_CTL_362_DATA 0x000AA955
+#define DDRSS0_CTL_363_DATA 0x00055555
+#define DDRSS0_CTL_364_DATA 0x000B3133
+#define DDRSS0_CTL_365_DATA 0x0004CD33
+#define DDRSS0_CTL_366_DATA 0x0004CECC
+#define DDRSS0_CTL_367_DATA 0x000B32CC
+#define DDRSS0_CTL_368_DATA 0x00010300
+#define DDRSS0_CTL_369_DATA 0x03000100
+#define DDRSS0_CTL_370_DATA 0x00000000
+#define DDRSS0_CTL_371_DATA 0x00000000
+#define DDRSS0_CTL_372_DATA 0x00000000
+#define DDRSS0_CTL_373_DATA 0x00000000
+#define DDRSS0_CTL_374_DATA 0x00000000
+#define DDRSS0_CTL_375_DATA 0x00000000
+#define DDRSS0_CTL_376_DATA 0x00000000
+#define DDRSS0_CTL_377_DATA 0x00010000
+#define DDRSS0_CTL_378_DATA 0x00000404
+#define DDRSS0_CTL_379_DATA 0x00000000
+#define DDRSS0_CTL_380_DATA 0x00000000
+#define DDRSS0_CTL_381_DATA 0x00000000
+#define DDRSS0_CTL_382_DATA 0x00000000
+#define DDRSS0_CTL_383_DATA 0x00000000
+#define DDRSS0_CTL_384_DATA 0x00000000
+#define DDRSS0_CTL_385_DATA 0x00000000
+#define DDRSS0_CTL_386_DATA 0x00000000
+#define DDRSS0_CTL_387_DATA 0x3A3A1B00
+#define DDRSS0_CTL_388_DATA 0x000A0000
+#define DDRSS0_CTL_389_DATA 0x0000019C
+#define DDRSS0_CTL_390_DATA 0x00000200
+#define DDRSS0_CTL_391_DATA 0x00000200
+#define DDRSS0_CTL_392_DATA 0x00000200
+#define DDRSS0_CTL_393_DATA 0x00000200
+#define DDRSS0_CTL_394_DATA 0x000004D4
+#define DDRSS0_CTL_395_DATA 0x00001018
+#define DDRSS0_CTL_396_DATA 0x00000204
+#define DDRSS0_CTL_397_DATA 0x000040E6
+#define DDRSS0_CTL_398_DATA 0x00000200
+#define DDRSS0_CTL_399_DATA 0x00000200
+#define DDRSS0_CTL_400_DATA 0x00000200
+#define DDRSS0_CTL_401_DATA 0x00000200
+#define DDRSS0_CTL_402_DATA 0x0000C2B2
+#define DDRSS0_CTL_403_DATA 0x000288FC
+#define DDRSS0_CTL_404_DATA 0x00000E15
+#define DDRSS0_CTL_405_DATA 0x000040E6
+#define DDRSS0_CTL_406_DATA 0x00000200
+#define DDRSS0_CTL_407_DATA 0x00000200
+#define DDRSS0_CTL_408_DATA 0x00000200
+#define DDRSS0_CTL_409_DATA 0x00000200
+#define DDRSS0_CTL_410_DATA 0x0000C2B2
+#define DDRSS0_CTL_411_DATA 0x000288FC
+#define DDRSS0_CTL_412_DATA 0x02020E15
+#define DDRSS0_CTL_413_DATA 0x03030202
+#define DDRSS0_CTL_414_DATA 0x00000022
+#define DDRSS0_CTL_415_DATA 0x00000000
+#define DDRSS0_CTL_416_DATA 0x00000000
+#define DDRSS0_CTL_417_DATA 0x00001403
+#define DDRSS0_CTL_418_DATA 0x000007D0
+#define DDRSS0_CTL_419_DATA 0x00000000
+#define DDRSS0_CTL_420_DATA 0x00000000
+#define DDRSS0_CTL_421_DATA 0x00030000
+#define DDRSS0_CTL_422_DATA 0x0007001F
+#define DDRSS0_CTL_423_DATA 0x001B0033
+#define DDRSS0_CTL_424_DATA 0x001B0033
+#define DDRSS0_CTL_425_DATA 0x00000000
+#define DDRSS0_CTL_426_DATA 0x00000000
+#define DDRSS0_CTL_427_DATA 0x02000000
+#define DDRSS0_CTL_428_DATA 0x01000404
+#define DDRSS0_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS0_CTL_430_DATA 0x00000105
+#define DDRSS0_CTL_431_DATA 0x00010101
+#define DDRSS0_CTL_432_DATA 0x00010101
+#define DDRSS0_CTL_433_DATA 0x00010001
+#define DDRSS0_CTL_434_DATA 0x00000101
+#define DDRSS0_CTL_435_DATA 0x02000201
+#define DDRSS0_CTL_436_DATA 0x02010000
+#define DDRSS0_CTL_437_DATA 0x00000200
+#define DDRSS0_CTL_438_DATA 0x28060000
+#define DDRSS0_CTL_439_DATA 0x00000128
+#define DDRSS0_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_442_DATA 0x00000000
+#define DDRSS0_CTL_443_DATA 0x00000000
+#define DDRSS0_CTL_444_DATA 0x00000000
+#define DDRSS0_CTL_445_DATA 0x00000000
+#define DDRSS0_CTL_446_DATA 0x00000000
+#define DDRSS0_CTL_447_DATA 0x00000000
+#define DDRSS0_CTL_448_DATA 0x00000000
+#define DDRSS0_CTL_449_DATA 0x00000000
+#define DDRSS0_CTL_450_DATA 0x00000000
+#define DDRSS0_CTL_451_DATA 0x00000000
+#define DDRSS0_CTL_452_DATA 0x00000000
+#define DDRSS0_CTL_453_DATA 0x00000000
+#define DDRSS0_CTL_454_DATA 0x00000000
+#define DDRSS0_CTL_455_DATA 0x00000000
+#define DDRSS0_CTL_456_DATA 0x00000000
+#define DDRSS0_CTL_457_DATA 0x00000000
+#define DDRSS0_CTL_458_DATA 0x00000000
+
+#define DDRSS0_PI_00_DATA 0x00000B00
+#define DDRSS0_PI_01_DATA 0x00000000
+#define DDRSS0_PI_02_DATA 0x00000000
+#define DDRSS0_PI_03_DATA 0x00000000
+#define DDRSS0_PI_04_DATA 0x00000000
+#define DDRSS0_PI_05_DATA 0x00000101
+#define DDRSS0_PI_06_DATA 0x00640000
+#define DDRSS0_PI_07_DATA 0x00000001
+#define DDRSS0_PI_08_DATA 0x00000000
+#define DDRSS0_PI_09_DATA 0x00000000
+#define DDRSS0_PI_10_DATA 0x00000000
+#define DDRSS0_PI_11_DATA 0x00000000
+#define DDRSS0_PI_12_DATA 0x00000007
+#define DDRSS0_PI_13_DATA 0x00010002
+#define DDRSS0_PI_14_DATA 0x0800000F
+#define DDRSS0_PI_15_DATA 0x00000103
+#define DDRSS0_PI_16_DATA 0x00000005
+#define DDRSS0_PI_17_DATA 0x00000000
+#define DDRSS0_PI_18_DATA 0x00000000
+#define DDRSS0_PI_19_DATA 0x00000000
+#define DDRSS0_PI_20_DATA 0x00000000
+#define DDRSS0_PI_21_DATA 0x00000000
+#define DDRSS0_PI_22_DATA 0x00000000
+#define DDRSS0_PI_23_DATA 0x00000000
+#define DDRSS0_PI_24_DATA 0x00000000
+#define DDRSS0_PI_25_DATA 0x00000000
+#define DDRSS0_PI_26_DATA 0x00010100
+#define DDRSS0_PI_27_DATA 0x00280A00
+#define DDRSS0_PI_28_DATA 0x00000000
+#define DDRSS0_PI_29_DATA 0x0F000000
+#define DDRSS0_PI_30_DATA 0x00003200
+#define DDRSS0_PI_31_DATA 0x00000000
+#define DDRSS0_PI_32_DATA 0x00000000
+#define DDRSS0_PI_33_DATA 0x01010102
+#define DDRSS0_PI_34_DATA 0x00000000
+#define DDRSS0_PI_35_DATA 0x000000AA
+#define DDRSS0_PI_36_DATA 0x00000055
+#define DDRSS0_PI_37_DATA 0x000000B5
+#define DDRSS0_PI_38_DATA 0x0000004A
+#define DDRSS0_PI_39_DATA 0x00000056
+#define DDRSS0_PI_40_DATA 0x000000A9
+#define DDRSS0_PI_41_DATA 0x000000A9
+#define DDRSS0_PI_42_DATA 0x000000B5
+#define DDRSS0_PI_43_DATA 0x00000000
+#define DDRSS0_PI_44_DATA 0x00000000
+#define DDRSS0_PI_45_DATA 0x000F0F00
+#define DDRSS0_PI_46_DATA 0x0000001B
+#define DDRSS0_PI_47_DATA 0x000007D0
+#define DDRSS0_PI_48_DATA 0x00000300
+#define DDRSS0_PI_49_DATA 0x00000000
+#define DDRSS0_PI_50_DATA 0x00000000
+#define DDRSS0_PI_51_DATA 0x01000000
+#define DDRSS0_PI_52_DATA 0x00010101
+#define DDRSS0_PI_53_DATA 0x00000000
+#define DDRSS0_PI_54_DATA 0x00030000
+#define DDRSS0_PI_55_DATA 0x0F000000
+#define DDRSS0_PI_56_DATA 0x00000017
+#define DDRSS0_PI_57_DATA 0x00000000
+#define DDRSS0_PI_58_DATA 0x00000000
+#define DDRSS0_PI_59_DATA 0x00000000
+#define DDRSS0_PI_60_DATA 0x0A0A140A
+#define DDRSS0_PI_61_DATA 0x10020101
+#define DDRSS0_PI_62_DATA 0x00020805
+#define DDRSS0_PI_63_DATA 0x01000404
+#define DDRSS0_PI_64_DATA 0x00000000
+#define DDRSS0_PI_65_DATA 0x00000000
+#define DDRSS0_PI_66_DATA 0x00000100
+#define DDRSS0_PI_67_DATA 0x0001010F
+#define DDRSS0_PI_68_DATA 0x00340000
+#define DDRSS0_PI_69_DATA 0x00000000
+#define DDRSS0_PI_70_DATA 0x00000000
+#define DDRSS0_PI_71_DATA 0x0000FFFF
+#define DDRSS0_PI_72_DATA 0x00000000
+#define DDRSS0_PI_73_DATA 0x00080000
+#define DDRSS0_PI_74_DATA 0x02000200
+#define DDRSS0_PI_75_DATA 0x01000100
+#define DDRSS0_PI_76_DATA 0x01000000
+#define DDRSS0_PI_77_DATA 0x02000200
+#define DDRSS0_PI_78_DATA 0x00000200
+#define DDRSS0_PI_79_DATA 0x00000000
+#define DDRSS0_PI_80_DATA 0x00000000
+#define DDRSS0_PI_81_DATA 0x00000000
+#define DDRSS0_PI_82_DATA 0x00000000
+#define DDRSS0_PI_83_DATA 0x00000000
+#define DDRSS0_PI_84_DATA 0x00000000
+#define DDRSS0_PI_85_DATA 0x00000000
+#define DDRSS0_PI_86_DATA 0x00000000
+#define DDRSS0_PI_87_DATA 0x00000000
+#define DDRSS0_PI_88_DATA 0x00000000
+#define DDRSS0_PI_89_DATA 0x00000000
+#define DDRSS0_PI_90_DATA 0x00000000
+#define DDRSS0_PI_91_DATA 0x00000400
+#define DDRSS0_PI_92_DATA 0x02010000
+#define DDRSS0_PI_93_DATA 0x00080003
+#define DDRSS0_PI_94_DATA 0x00080000
+#define DDRSS0_PI_95_DATA 0x00000001
+#define DDRSS0_PI_96_DATA 0x00000000
+#define DDRSS0_PI_97_DATA 0x0000AA00
+#define DDRSS0_PI_98_DATA 0x00000000
+#define DDRSS0_PI_99_DATA 0x00000000
+#define DDRSS0_PI_100_DATA 0x00010000
+#define DDRSS0_PI_101_DATA 0x00000000
+#define DDRSS0_PI_102_DATA 0x00000000
+#define DDRSS0_PI_103_DATA 0x00000000
+#define DDRSS0_PI_104_DATA 0x00000000
+#define DDRSS0_PI_105_DATA 0x00000000
+#define DDRSS0_PI_106_DATA 0x00000000
+#define DDRSS0_PI_107_DATA 0x00000000
+#define DDRSS0_PI_108_DATA 0x00000000
+#define DDRSS0_PI_109_DATA 0x00000000
+#define DDRSS0_PI_110_DATA 0x00000000
+#define DDRSS0_PI_111_DATA 0x00000000
+#define DDRSS0_PI_112_DATA 0x00000000
+#define DDRSS0_PI_113_DATA 0x00000000
+#define DDRSS0_PI_114_DATA 0x00000000
+#define DDRSS0_PI_115_DATA 0x00000000
+#define DDRSS0_PI_116_DATA 0x00000000
+#define DDRSS0_PI_117_DATA 0x00000000
+#define DDRSS0_PI_118_DATA 0x00000000
+#define DDRSS0_PI_119_DATA 0x00000000
+#define DDRSS0_PI_120_DATA 0x00000000
+#define DDRSS0_PI_121_DATA 0x00000000
+#define DDRSS0_PI_122_DATA 0x00000000
+#define DDRSS0_PI_123_DATA 0x00000000
+#define DDRSS0_PI_124_DATA 0x00000000
+#define DDRSS0_PI_125_DATA 0x00000008
+#define DDRSS0_PI_126_DATA 0x00000000
+#define DDRSS0_PI_127_DATA 0x00000000
+#define DDRSS0_PI_128_DATA 0x00000000
+#define DDRSS0_PI_129_DATA 0x00000000
+#define DDRSS0_PI_130_DATA 0x00000000
+#define DDRSS0_PI_131_DATA 0x00000000
+#define DDRSS0_PI_132_DATA 0x00000000
+#define DDRSS0_PI_133_DATA 0x00000000
+#define DDRSS0_PI_134_DATA 0x00000002
+#define DDRSS0_PI_135_DATA 0x00000000
+#define DDRSS0_PI_136_DATA 0x00000000
+#define DDRSS0_PI_137_DATA 0x0000000A
+#define DDRSS0_PI_138_DATA 0x00000019
+#define DDRSS0_PI_139_DATA 0x00000100
+#define DDRSS0_PI_140_DATA 0x00000000
+#define DDRSS0_PI_141_DATA 0x00000000
+#define DDRSS0_PI_142_DATA 0x00000000
+#define DDRSS0_PI_143_DATA 0x00000000
+#define DDRSS0_PI_144_DATA 0x01000000
+#define DDRSS0_PI_145_DATA 0x00010003
+#define DDRSS0_PI_146_DATA 0x02000101
+#define DDRSS0_PI_147_DATA 0x01030001
+#define DDRSS0_PI_148_DATA 0x00010400
+#define DDRSS0_PI_149_DATA 0x06000105
+#define DDRSS0_PI_150_DATA 0x01070001
+#define DDRSS0_PI_151_DATA 0x00000000
+#define DDRSS0_PI_152_DATA 0x00000000
+#define DDRSS0_PI_153_DATA 0x00000000
+#define DDRSS0_PI_154_DATA 0x00010001
+#define DDRSS0_PI_155_DATA 0x00000000
+#define DDRSS0_PI_156_DATA 0x00000000
+#define DDRSS0_PI_157_DATA 0x00000000
+#define DDRSS0_PI_158_DATA 0x00000000
+#define DDRSS0_PI_159_DATA 0x00000401
+#define DDRSS0_PI_160_DATA 0x00000000
+#define DDRSS0_PI_161_DATA 0x00010000
+#define DDRSS0_PI_162_DATA 0x00000000
+#define DDRSS0_PI_163_DATA 0x2B2B0200
+#define DDRSS0_PI_164_DATA 0x00000034
+#define DDRSS0_PI_165_DATA 0x00000064
+#define DDRSS0_PI_166_DATA 0x00020064
+#define DDRSS0_PI_167_DATA 0x02000200
+#define DDRSS0_PI_168_DATA 0x48120C04
+#define DDRSS0_PI_169_DATA 0x00154812
+#define DDRSS0_PI_170_DATA 0x000000CE
+#define DDRSS0_PI_171_DATA 0x0000032B
+#define DDRSS0_PI_172_DATA 0x00002073
+#define DDRSS0_PI_173_DATA 0x0000032B
+#define DDRSS0_PI_174_DATA 0x04002073
+#define DDRSS0_PI_175_DATA 0x01010404
+#define DDRSS0_PI_176_DATA 0x00001501
+#define DDRSS0_PI_177_DATA 0x00150015
+#define DDRSS0_PI_178_DATA 0x01000100
+#define DDRSS0_PI_179_DATA 0x00000100
+#define DDRSS0_PI_180_DATA 0x00000000
+#define DDRSS0_PI_181_DATA 0x01010101
+#define DDRSS0_PI_182_DATA 0x00000101
+#define DDRSS0_PI_183_DATA 0x00000000
+#define DDRSS0_PI_184_DATA 0x00000000
+#define DDRSS0_PI_185_DATA 0x15040000
+#define DDRSS0_PI_186_DATA 0x0E0E0215
+#define DDRSS0_PI_187_DATA 0x00040402
+#define DDRSS0_PI_188_DATA 0x000D0035
+#define DDRSS0_PI_189_DATA 0x00218049
+#define DDRSS0_PI_190_DATA 0x00218049
+#define DDRSS0_PI_191_DATA 0x01010101
+#define DDRSS0_PI_192_DATA 0x0004000E
+#define DDRSS0_PI_193_DATA 0x00040216
+#define DDRSS0_PI_194_DATA 0x01000216
+#define DDRSS0_PI_195_DATA 0x000F000F
+#define DDRSS0_PI_196_DATA 0x02170100
+#define DDRSS0_PI_197_DATA 0x01000217
+#define DDRSS0_PI_198_DATA 0x02170217
+#define DDRSS0_PI_199_DATA 0x32103200
+#define DDRSS0_PI_200_DATA 0x01013210
+#define DDRSS0_PI_201_DATA 0x0A070601
+#define DDRSS0_PI_202_DATA 0x1F130A0D
+#define DDRSS0_PI_203_DATA 0x1F130A14
+#define DDRSS0_PI_204_DATA 0x0000C014
+#define DDRSS0_PI_205_DATA 0x00C01000
+#define DDRSS0_PI_206_DATA 0x00C01000
+#define DDRSS0_PI_207_DATA 0x00021000
+#define DDRSS0_PI_208_DATA 0x0024000E
+#define DDRSS0_PI_209_DATA 0x00240216
+#define DDRSS0_PI_210_DATA 0x00110216
+#define DDRSS0_PI_211_DATA 0x32000056
+#define DDRSS0_PI_212_DATA 0x00000301
+#define DDRSS0_PI_213_DATA 0x005B0036
+#define DDRSS0_PI_214_DATA 0x03013212
+#define DDRSS0_PI_215_DATA 0x00003600
+#define DDRSS0_PI_216_DATA 0x3212005B
+#define DDRSS0_PI_217_DATA 0x09000301
+#define DDRSS0_PI_218_DATA 0x04010504
+#define DDRSS0_PI_219_DATA 0x040006C9
+#define DDRSS0_PI_220_DATA 0x0A032001
+#define DDRSS0_PI_221_DATA 0x2C31110A
+#define DDRSS0_PI_222_DATA 0x00002918
+#define DDRSS0_PI_223_DATA 0x6001071C
+#define DDRSS0_PI_224_DATA 0x1E202008
+#define DDRSS0_PI_225_DATA 0x2C311116
+#define DDRSS0_PI_226_DATA 0x00002918
+#define DDRSS0_PI_227_DATA 0x6001071C
+#define DDRSS0_PI_228_DATA 0x1E202008
+#define DDRSS0_PI_229_DATA 0x00019C16
+#define DDRSS0_PI_230_DATA 0x00001018
+#define DDRSS0_PI_231_DATA 0x000040E6
+#define DDRSS0_PI_232_DATA 0x000288FC
+#define DDRSS0_PI_233_DATA 0x000040E6
+#define DDRSS0_PI_234_DATA 0x000288FC
+#define DDRSS0_PI_235_DATA 0x033B0016
+#define DDRSS0_PI_236_DATA 0x0303033B
+#define DDRSS0_PI_237_DATA 0x002AF803
+#define DDRSS0_PI_238_DATA 0x0001ADAF
+#define DDRSS0_PI_239_DATA 0x00000005
+#define DDRSS0_PI_240_DATA 0x0000006E
+#define DDRSS0_PI_241_DATA 0x00000016
+#define DDRSS0_PI_242_DATA 0x000681C8
+#define DDRSS0_PI_243_DATA 0x0001ADAF
+#define DDRSS0_PI_244_DATA 0x00000005
+#define DDRSS0_PI_245_DATA 0x000010A9
+#define DDRSS0_PI_246_DATA 0x0000033B
+#define DDRSS0_PI_247_DATA 0x000681C8
+#define DDRSS0_PI_248_DATA 0x0001ADAF
+#define DDRSS0_PI_249_DATA 0x00000005
+#define DDRSS0_PI_250_DATA 0x000010A9
+#define DDRSS0_PI_251_DATA 0x0100033B
+#define DDRSS0_PI_252_DATA 0x00370040
+#define DDRSS0_PI_253_DATA 0x00010008
+#define DDRSS0_PI_254_DATA 0x08550040
+#define DDRSS0_PI_255_DATA 0x00010040
+#define DDRSS0_PI_256_DATA 0x08550040
+#define DDRSS0_PI_257_DATA 0x00000340
+#define DDRSS0_PI_258_DATA 0x006B006B
+#define DDRSS0_PI_259_DATA 0x08040404
+#define DDRSS0_PI_260_DATA 0x00000055
+#define DDRSS0_PI_261_DATA 0x55083C5A
+#define DDRSS0_PI_262_DATA 0x5A000000
+#define DDRSS0_PI_263_DATA 0x0055083C
+#define DDRSS0_PI_264_DATA 0x3C5A0000
+#define DDRSS0_PI_265_DATA 0x00005508
+#define DDRSS0_PI_266_DATA 0x0C3C5A00
+#define DDRSS0_PI_267_DATA 0x080F0E0D
+#define DDRSS0_PI_268_DATA 0x000B0A09
+#define DDRSS0_PI_269_DATA 0x00030201
+#define DDRSS0_PI_270_DATA 0x01000000
+#define DDRSS0_PI_271_DATA 0x04020201
+#define DDRSS0_PI_272_DATA 0x00080804
+#define DDRSS0_PI_273_DATA 0x00000000
+#define DDRSS0_PI_274_DATA 0x00000000
+#define DDRSS0_PI_275_DATA 0x00330084
+#define DDRSS0_PI_276_DATA 0x00160000
+#define DDRSS0_PI_277_DATA 0x35333FF4
+#define DDRSS0_PI_278_DATA 0x00160F27
+#define DDRSS0_PI_279_DATA 0x35333FF4
+#define DDRSS0_PI_280_DATA 0x00160F27
+#define DDRSS0_PI_281_DATA 0x00330084
+#define DDRSS0_PI_282_DATA 0x00160000
+#define DDRSS0_PI_283_DATA 0x35333FF4
+#define DDRSS0_PI_284_DATA 0x00160F27
+#define DDRSS0_PI_285_DATA 0x35333FF4
+#define DDRSS0_PI_286_DATA 0x00160F27
+#define DDRSS0_PI_287_DATA 0x00330084
+#define DDRSS0_PI_288_DATA 0x00160000
+#define DDRSS0_PI_289_DATA 0x35333FF4
+#define DDRSS0_PI_290_DATA 0x00160F27
+#define DDRSS0_PI_291_DATA 0x35333FF4
+#define DDRSS0_PI_292_DATA 0x00160F27
+#define DDRSS0_PI_293_DATA 0x00330084
+#define DDRSS0_PI_294_DATA 0x00160000
+#define DDRSS0_PI_295_DATA 0x35333FF4
+#define DDRSS0_PI_296_DATA 0x00160F27
+#define DDRSS0_PI_297_DATA 0x35333FF4
+#define DDRSS0_PI_298_DATA 0x00160F27
+#define DDRSS0_PI_299_DATA 0x00000000
+
+#define DDRSS0_PHY_00_DATA 0x000004F0
+#define DDRSS0_PHY_01_DATA 0x00000000
+#define DDRSS0_PHY_02_DATA 0x00030200
+#define DDRSS0_PHY_03_DATA 0x00000000
+#define DDRSS0_PHY_04_DATA 0x00000000
+#define DDRSS0_PHY_05_DATA 0x01030000
+#define DDRSS0_PHY_06_DATA 0x00010000
+#define DDRSS0_PHY_07_DATA 0x01030004
+#define DDRSS0_PHY_08_DATA 0x01000000
+#define DDRSS0_PHY_09_DATA 0x00000000
+#define DDRSS0_PHY_10_DATA 0x00000000
+#define DDRSS0_PHY_11_DATA 0x01000001
+#define DDRSS0_PHY_12_DATA 0x00000100
+#define DDRSS0_PHY_13_DATA 0x000800C0
+#define DDRSS0_PHY_14_DATA 0x060100CC
+#define DDRSS0_PHY_15_DATA 0x00030066
+#define DDRSS0_PHY_16_DATA 0x00000000
+#define DDRSS0_PHY_17_DATA 0x00000301
+#define DDRSS0_PHY_18_DATA 0x0000AAAA
+#define DDRSS0_PHY_19_DATA 0x00005555
+#define DDRSS0_PHY_20_DATA 0x0000B5B5
+#define DDRSS0_PHY_21_DATA 0x00004A4A
+#define DDRSS0_PHY_22_DATA 0x00005656
+#define DDRSS0_PHY_23_DATA 0x0000A9A9
+#define DDRSS0_PHY_24_DATA 0x0000A9A9
+#define DDRSS0_PHY_25_DATA 0x0000B5B5
+#define DDRSS0_PHY_26_DATA 0x00000000
+#define DDRSS0_PHY_27_DATA 0x00000000
+#define DDRSS0_PHY_28_DATA 0x2A000000
+#define DDRSS0_PHY_29_DATA 0x00000808
+#define DDRSS0_PHY_30_DATA 0x0F000000
+#define DDRSS0_PHY_31_DATA 0x00000F0F
+#define DDRSS0_PHY_32_DATA 0x10400000
+#define DDRSS0_PHY_33_DATA 0x0C002006
+#define DDRSS0_PHY_34_DATA 0x00000000
+#define DDRSS0_PHY_35_DATA 0x00000000
+#define DDRSS0_PHY_36_DATA 0x55555555
+#define DDRSS0_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_38_DATA 0x55555555
+#define DDRSS0_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_40_DATA 0x00005555
+#define DDRSS0_PHY_41_DATA 0x01000100
+#define DDRSS0_PHY_42_DATA 0x00800180
+#define DDRSS0_PHY_43_DATA 0x00000001
+#define DDRSS0_PHY_44_DATA 0x00000000
+#define DDRSS0_PHY_45_DATA 0x00000000
+#define DDRSS0_PHY_46_DATA 0x00000000
+#define DDRSS0_PHY_47_DATA 0x00000000
+#define DDRSS0_PHY_48_DATA 0x00000000
+#define DDRSS0_PHY_49_DATA 0x00000000
+#define DDRSS0_PHY_50_DATA 0x00000000
+#define DDRSS0_PHY_51_DATA 0x00000000
+#define DDRSS0_PHY_52_DATA 0x00000000
+#define DDRSS0_PHY_53_DATA 0x00000000
+#define DDRSS0_PHY_54_DATA 0x00000000
+#define DDRSS0_PHY_55_DATA 0x00000000
+#define DDRSS0_PHY_56_DATA 0x00000000
+#define DDRSS0_PHY_57_DATA 0x00000000
+#define DDRSS0_PHY_58_DATA 0x00000000
+#define DDRSS0_PHY_59_DATA 0x00000000
+#define DDRSS0_PHY_60_DATA 0x00000000
+#define DDRSS0_PHY_61_DATA 0x00000000
+#define DDRSS0_PHY_62_DATA 0x00000000
+#define DDRSS0_PHY_63_DATA 0x00000000
+#define DDRSS0_PHY_64_DATA 0x00000000
+#define DDRSS0_PHY_65_DATA 0x00000000
+#define DDRSS0_PHY_66_DATA 0x00000104
+#define DDRSS0_PHY_67_DATA 0x00000120
+#define DDRSS0_PHY_68_DATA 0x00000000
+#define DDRSS0_PHY_69_DATA 0x00000000
+#define DDRSS0_PHY_70_DATA 0x00000000
+#define DDRSS0_PHY_71_DATA 0x00000000
+#define DDRSS0_PHY_72_DATA 0x00000000
+#define DDRSS0_PHY_73_DATA 0x00000000
+#define DDRSS0_PHY_74_DATA 0x00000000
+#define DDRSS0_PHY_75_DATA 0x00000001
+#define DDRSS0_PHY_76_DATA 0x07FF0000
+#define DDRSS0_PHY_77_DATA 0x0080081F
+#define DDRSS0_PHY_78_DATA 0x00081020
+#define DDRSS0_PHY_79_DATA 0x04010000
+#define DDRSS0_PHY_80_DATA 0x00000000
+#define DDRSS0_PHY_81_DATA 0x00000000
+#define DDRSS0_PHY_82_DATA 0x00000000
+#define DDRSS0_PHY_83_DATA 0x00000100
+#define DDRSS0_PHY_84_DATA 0x01CC0C01
+#define DDRSS0_PHY_85_DATA 0x1003CC0C
+#define DDRSS0_PHY_86_DATA 0x20000140
+#define DDRSS0_PHY_87_DATA 0x07FF0200
+#define DDRSS0_PHY_88_DATA 0x0000DD01
+#define DDRSS0_PHY_89_DATA 0x10100303
+#define DDRSS0_PHY_90_DATA 0x10101010
+#define DDRSS0_PHY_91_DATA 0x10101010
+#define DDRSS0_PHY_92_DATA 0x00021010
+#define DDRSS0_PHY_93_DATA 0x00100010
+#define DDRSS0_PHY_94_DATA 0x00100010
+#define DDRSS0_PHY_95_DATA 0x00100010
+#define DDRSS0_PHY_96_DATA 0x00100010
+#define DDRSS0_PHY_97_DATA 0x00050010
+#define DDRSS0_PHY_98_DATA 0x51517041
+#define DDRSS0_PHY_99_DATA 0x31C06001
+#define DDRSS0_PHY_100_DATA 0x07AB0340
+#define DDRSS0_PHY_101_DATA 0x00C0C001
+#define DDRSS0_PHY_102_DATA 0x0E0D0001
+#define DDRSS0_PHY_103_DATA 0x10001000
+#define DDRSS0_PHY_104_DATA 0x0C083E42
+#define DDRSS0_PHY_105_DATA 0x0F0C3701
+#define DDRSS0_PHY_106_DATA 0x01000140
+#define DDRSS0_PHY_107_DATA 0x0C000420
+#define DDRSS0_PHY_108_DATA 0x00000198
+#define DDRSS0_PHY_109_DATA 0x0A0000D0
+#define DDRSS0_PHY_110_DATA 0x00030200
+#define DDRSS0_PHY_111_DATA 0x02800000
+#define DDRSS0_PHY_112_DATA 0x80800000
+#define DDRSS0_PHY_113_DATA 0x000E2010
+#define DDRSS0_PHY_114_DATA 0x76543210
+#define DDRSS0_PHY_115_DATA 0x00000008
+#define DDRSS0_PHY_116_DATA 0x02800280
+#define DDRSS0_PHY_117_DATA 0x02800280
+#define DDRSS0_PHY_118_DATA 0x02800280
+#define DDRSS0_PHY_119_DATA 0x02800280
+#define DDRSS0_PHY_120_DATA 0x00000280
+#define DDRSS0_PHY_121_DATA 0x0000A000
+#define DDRSS0_PHY_122_DATA 0x00A000A0
+#define DDRSS0_PHY_123_DATA 0x00A000A0
+#define DDRSS0_PHY_124_DATA 0x00A000A0
+#define DDRSS0_PHY_125_DATA 0x00A000A0
+#define DDRSS0_PHY_126_DATA 0x00A000A0
+#define DDRSS0_PHY_127_DATA 0x00A000A0
+#define DDRSS0_PHY_128_DATA 0x00A000A0
+#define DDRSS0_PHY_129_DATA 0x00A000A0
+#define DDRSS0_PHY_130_DATA 0x01C200A0
+#define DDRSS0_PHY_131_DATA 0x01A00005
+#define DDRSS0_PHY_132_DATA 0x00000000
+#define DDRSS0_PHY_133_DATA 0x00000000
+#define DDRSS0_PHY_134_DATA 0x00080200
+#define DDRSS0_PHY_135_DATA 0x00000000
+#define DDRSS0_PHY_136_DATA 0x20202000
+#define DDRSS0_PHY_137_DATA 0x20202020
+#define DDRSS0_PHY_138_DATA 0xF0F02020
+#define DDRSS0_PHY_139_DATA 0x00000000
+#define DDRSS0_PHY_140_DATA 0x00000000
+#define DDRSS0_PHY_141_DATA 0x00000000
+#define DDRSS0_PHY_142_DATA 0x00000000
+#define DDRSS0_PHY_143_DATA 0x00000000
+#define DDRSS0_PHY_144_DATA 0x00000000
+#define DDRSS0_PHY_145_DATA 0x00000000
+#define DDRSS0_PHY_146_DATA 0x00000000
+#define DDRSS0_PHY_147_DATA 0x00000000
+#define DDRSS0_PHY_148_DATA 0x00000000
+#define DDRSS0_PHY_149_DATA 0x00000000
+#define DDRSS0_PHY_150_DATA 0x00000000
+#define DDRSS0_PHY_151_DATA 0x00000000
+#define DDRSS0_PHY_152_DATA 0x00000000
+#define DDRSS0_PHY_153_DATA 0x00000000
+#define DDRSS0_PHY_154_DATA 0x00000000
+#define DDRSS0_PHY_155_DATA 0x00000000
+#define DDRSS0_PHY_156_DATA 0x00000000
+#define DDRSS0_PHY_157_DATA 0x00000000
+#define DDRSS0_PHY_158_DATA 0x00000000
+#define DDRSS0_PHY_159_DATA 0x00000000
+#define DDRSS0_PHY_160_DATA 0x00000000
+#define DDRSS0_PHY_161_DATA 0x00000000
+#define DDRSS0_PHY_162_DATA 0x00000000
+#define DDRSS0_PHY_163_DATA 0x00000000
+#define DDRSS0_PHY_164_DATA 0x00000000
+#define DDRSS0_PHY_165_DATA 0x00000000
+#define DDRSS0_PHY_166_DATA 0x00000000
+#define DDRSS0_PHY_167_DATA 0x00000000
+#define DDRSS0_PHY_168_DATA 0x00000000
+#define DDRSS0_PHY_169_DATA 0x00000000
+#define DDRSS0_PHY_170_DATA 0x00000000
+#define DDRSS0_PHY_171_DATA 0x00000000
+#define DDRSS0_PHY_172_DATA 0x00000000
+#define DDRSS0_PHY_173_DATA 0x00000000
+#define DDRSS0_PHY_174_DATA 0x00000000
+#define DDRSS0_PHY_175_DATA 0x00000000
+#define DDRSS0_PHY_176_DATA 0x00000000
+#define DDRSS0_PHY_177_DATA 0x00000000
+#define DDRSS0_PHY_178_DATA 0x00000000
+#define DDRSS0_PHY_179_DATA 0x00000000
+#define DDRSS0_PHY_180_DATA 0x00000000
+#define DDRSS0_PHY_181_DATA 0x00000000
+#define DDRSS0_PHY_182_DATA 0x00000000
+#define DDRSS0_PHY_183_DATA 0x00000000
+#define DDRSS0_PHY_184_DATA 0x00000000
+#define DDRSS0_PHY_185_DATA 0x00000000
+#define DDRSS0_PHY_186_DATA 0x00000000
+#define DDRSS0_PHY_187_DATA 0x00000000
+#define DDRSS0_PHY_188_DATA 0x00000000
+#define DDRSS0_PHY_189_DATA 0x00000000
+#define DDRSS0_PHY_190_DATA 0x00000000
+#define DDRSS0_PHY_191_DATA 0x00000000
+#define DDRSS0_PHY_192_DATA 0x00000000
+#define DDRSS0_PHY_193_DATA 0x00000000
+#define DDRSS0_PHY_194_DATA 0x00000000
+#define DDRSS0_PHY_195_DATA 0x00000000
+#define DDRSS0_PHY_196_DATA 0x00000000
+#define DDRSS0_PHY_197_DATA 0x00000000
+#define DDRSS0_PHY_198_DATA 0x00000000
+#define DDRSS0_PHY_199_DATA 0x00000000
+#define DDRSS0_PHY_200_DATA 0x00000000
+#define DDRSS0_PHY_201_DATA 0x00000000
+#define DDRSS0_PHY_202_DATA 0x00000000
+#define DDRSS0_PHY_203_DATA 0x00000000
+#define DDRSS0_PHY_204_DATA 0x00000000
+#define DDRSS0_PHY_205_DATA 0x00000000
+#define DDRSS0_PHY_206_DATA 0x00000000
+#define DDRSS0_PHY_207_DATA 0x00000000
+#define DDRSS0_PHY_208_DATA 0x00000000
+#define DDRSS0_PHY_209_DATA 0x00000000
+#define DDRSS0_PHY_210_DATA 0x00000000
+#define DDRSS0_PHY_211_DATA 0x00000000
+#define DDRSS0_PHY_212_DATA 0x00000000
+#define DDRSS0_PHY_213_DATA 0x00000000
+#define DDRSS0_PHY_214_DATA 0x00000000
+#define DDRSS0_PHY_215_DATA 0x00000000
+#define DDRSS0_PHY_216_DATA 0x00000000
+#define DDRSS0_PHY_217_DATA 0x00000000
+#define DDRSS0_PHY_218_DATA 0x00000000
+#define DDRSS0_PHY_219_DATA 0x00000000
+#define DDRSS0_PHY_220_DATA 0x00000000
+#define DDRSS0_PHY_221_DATA 0x00000000
+#define DDRSS0_PHY_222_DATA 0x00000000
+#define DDRSS0_PHY_223_DATA 0x00000000
+#define DDRSS0_PHY_224_DATA 0x00000000
+#define DDRSS0_PHY_225_DATA 0x00000000
+#define DDRSS0_PHY_226_DATA 0x00000000
+#define DDRSS0_PHY_227_DATA 0x00000000
+#define DDRSS0_PHY_228_DATA 0x00000000
+#define DDRSS0_PHY_229_DATA 0x00000000
+#define DDRSS0_PHY_230_DATA 0x00000000
+#define DDRSS0_PHY_231_DATA 0x00000000
+#define DDRSS0_PHY_232_DATA 0x00000000
+#define DDRSS0_PHY_233_DATA 0x00000000
+#define DDRSS0_PHY_234_DATA 0x00000000
+#define DDRSS0_PHY_235_DATA 0x00000000
+#define DDRSS0_PHY_236_DATA 0x00000000
+#define DDRSS0_PHY_237_DATA 0x00000000
+#define DDRSS0_PHY_238_DATA 0x00000000
+#define DDRSS0_PHY_239_DATA 0x00000000
+#define DDRSS0_PHY_240_DATA 0x00000000
+#define DDRSS0_PHY_241_DATA 0x00000000
+#define DDRSS0_PHY_242_DATA 0x00000000
+#define DDRSS0_PHY_243_DATA 0x00000000
+#define DDRSS0_PHY_244_DATA 0x00000000
+#define DDRSS0_PHY_245_DATA 0x00000000
+#define DDRSS0_PHY_246_DATA 0x00000000
+#define DDRSS0_PHY_247_DATA 0x00000000
+#define DDRSS0_PHY_248_DATA 0x00000000
+#define DDRSS0_PHY_249_DATA 0x00000000
+#define DDRSS0_PHY_250_DATA 0x00000000
+#define DDRSS0_PHY_251_DATA 0x00000000
+#define DDRSS0_PHY_252_DATA 0x00000000
+#define DDRSS0_PHY_253_DATA 0x00000000
+#define DDRSS0_PHY_254_DATA 0x00000000
+#define DDRSS0_PHY_255_DATA 0x00000000
+#define DDRSS0_PHY_256_DATA 0x000004F0
+#define DDRSS0_PHY_257_DATA 0x00000000
+#define DDRSS0_PHY_258_DATA 0x00030200
+#define DDRSS0_PHY_259_DATA 0x00000000
+#define DDRSS0_PHY_260_DATA 0x00000000
+#define DDRSS0_PHY_261_DATA 0x01030000
+#define DDRSS0_PHY_262_DATA 0x00010000
+#define DDRSS0_PHY_263_DATA 0x01030004
+#define DDRSS0_PHY_264_DATA 0x01000000
+#define DDRSS0_PHY_265_DATA 0x00000000
+#define DDRSS0_PHY_266_DATA 0x00000000
+#define DDRSS0_PHY_267_DATA 0x01000001
+#define DDRSS0_PHY_268_DATA 0x00000100
+#define DDRSS0_PHY_269_DATA 0x000800C0
+#define DDRSS0_PHY_270_DATA 0x060100CC
+#define DDRSS0_PHY_271_DATA 0x00030066
+#define DDRSS0_PHY_272_DATA 0x00000000
+#define DDRSS0_PHY_273_DATA 0x00000301
+#define DDRSS0_PHY_274_DATA 0x0000AAAA
+#define DDRSS0_PHY_275_DATA 0x00005555
+#define DDRSS0_PHY_276_DATA 0x0000B5B5
+#define DDRSS0_PHY_277_DATA 0x00004A4A
+#define DDRSS0_PHY_278_DATA 0x00005656
+#define DDRSS0_PHY_279_DATA 0x0000A9A9
+#define DDRSS0_PHY_280_DATA 0x0000A9A9
+#define DDRSS0_PHY_281_DATA 0x0000B5B5
+#define DDRSS0_PHY_282_DATA 0x00000000
+#define DDRSS0_PHY_283_DATA 0x00000000
+#define DDRSS0_PHY_284_DATA 0x2A000000
+#define DDRSS0_PHY_285_DATA 0x00000808
+#define DDRSS0_PHY_286_DATA 0x0F000000
+#define DDRSS0_PHY_287_DATA 0x00000F0F
+#define DDRSS0_PHY_288_DATA 0x10400000
+#define DDRSS0_PHY_289_DATA 0x0C002006
+#define DDRSS0_PHY_290_DATA 0x00000000
+#define DDRSS0_PHY_291_DATA 0x00000000
+#define DDRSS0_PHY_292_DATA 0x55555555
+#define DDRSS0_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_294_DATA 0x55555555
+#define DDRSS0_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_296_DATA 0x00005555
+#define DDRSS0_PHY_297_DATA 0x01000100
+#define DDRSS0_PHY_298_DATA 0x00800180
+#define DDRSS0_PHY_299_DATA 0x00000000
+#define DDRSS0_PHY_300_DATA 0x00000000
+#define DDRSS0_PHY_301_DATA 0x00000000
+#define DDRSS0_PHY_302_DATA 0x00000000
+#define DDRSS0_PHY_303_DATA 0x00000000
+#define DDRSS0_PHY_304_DATA 0x00000000
+#define DDRSS0_PHY_305_DATA 0x00000000
+#define DDRSS0_PHY_306_DATA 0x00000000
+#define DDRSS0_PHY_307_DATA 0x00000000
+#define DDRSS0_PHY_308_DATA 0x00000000
+#define DDRSS0_PHY_309_DATA 0x00000000
+#define DDRSS0_PHY_310_DATA 0x00000000
+#define DDRSS0_PHY_311_DATA 0x00000000
+#define DDRSS0_PHY_312_DATA 0x00000000
+#define DDRSS0_PHY_313_DATA 0x00000000
+#define DDRSS0_PHY_314_DATA 0x00000000
+#define DDRSS0_PHY_315_DATA 0x00000000
+#define DDRSS0_PHY_316_DATA 0x00000000
+#define DDRSS0_PHY_317_DATA 0x00000000
+#define DDRSS0_PHY_318_DATA 0x00000000
+#define DDRSS0_PHY_319_DATA 0x00000000
+#define DDRSS0_PHY_320_DATA 0x00000000
+#define DDRSS0_PHY_321_DATA 0x00000000
+#define DDRSS0_PHY_322_DATA 0x00000104
+#define DDRSS0_PHY_323_DATA 0x00000120
+#define DDRSS0_PHY_324_DATA 0x00000000
+#define DDRSS0_PHY_325_DATA 0x00000000
+#define DDRSS0_PHY_326_DATA 0x00000000
+#define DDRSS0_PHY_327_DATA 0x00000000
+#define DDRSS0_PHY_328_DATA 0x00000000
+#define DDRSS0_PHY_329_DATA 0x00000000
+#define DDRSS0_PHY_330_DATA 0x00000000
+#define DDRSS0_PHY_331_DATA 0x00000001
+#define DDRSS0_PHY_332_DATA 0x07FF0000
+#define DDRSS0_PHY_333_DATA 0x0080081F
+#define DDRSS0_PHY_334_DATA 0x00081020
+#define DDRSS0_PHY_335_DATA 0x04010000
+#define DDRSS0_PHY_336_DATA 0x00000000
+#define DDRSS0_PHY_337_DATA 0x00000000
+#define DDRSS0_PHY_338_DATA 0x00000000
+#define DDRSS0_PHY_339_DATA 0x00000100
+#define DDRSS0_PHY_340_DATA 0x01CC0C01
+#define DDRSS0_PHY_341_DATA 0x1003CC0C
+#define DDRSS0_PHY_342_DATA 0x20000140
+#define DDRSS0_PHY_343_DATA 0x07FF0200
+#define DDRSS0_PHY_344_DATA 0x0000DD01
+#define DDRSS0_PHY_345_DATA 0x10100303
+#define DDRSS0_PHY_346_DATA 0x10101010
+#define DDRSS0_PHY_347_DATA 0x10101010
+#define DDRSS0_PHY_348_DATA 0x00021010
+#define DDRSS0_PHY_349_DATA 0x00100010
+#define DDRSS0_PHY_350_DATA 0x00100010
+#define DDRSS0_PHY_351_DATA 0x00100010
+#define DDRSS0_PHY_352_DATA 0x00100010
+#define DDRSS0_PHY_353_DATA 0x00050010
+#define DDRSS0_PHY_354_DATA 0x51517041
+#define DDRSS0_PHY_355_DATA 0x31C06001
+#define DDRSS0_PHY_356_DATA 0x07AB0340
+#define DDRSS0_PHY_357_DATA 0x00C0C001
+#define DDRSS0_PHY_358_DATA 0x0E0D0001
+#define DDRSS0_PHY_359_DATA 0x10001000
+#define DDRSS0_PHY_360_DATA 0x0C083E42
+#define DDRSS0_PHY_361_DATA 0x0F0C3701
+#define DDRSS0_PHY_362_DATA 0x01000140
+#define DDRSS0_PHY_363_DATA 0x0C000420
+#define DDRSS0_PHY_364_DATA 0x00000198
+#define DDRSS0_PHY_365_DATA 0x0A0000D0
+#define DDRSS0_PHY_366_DATA 0x00030200
+#define DDRSS0_PHY_367_DATA 0x02800000
+#define DDRSS0_PHY_368_DATA 0x80800000
+#define DDRSS0_PHY_369_DATA 0x000E2010
+#define DDRSS0_PHY_370_DATA 0x76543210
+#define DDRSS0_PHY_371_DATA 0x00000008
+#define DDRSS0_PHY_372_DATA 0x02800280
+#define DDRSS0_PHY_373_DATA 0x02800280
+#define DDRSS0_PHY_374_DATA 0x02800280
+#define DDRSS0_PHY_375_DATA 0x02800280
+#define DDRSS0_PHY_376_DATA 0x00000280
+#define DDRSS0_PHY_377_DATA 0x0000A000
+#define DDRSS0_PHY_378_DATA 0x00A000A0
+#define DDRSS0_PHY_379_DATA 0x00A000A0
+#define DDRSS0_PHY_380_DATA 0x00A000A0
+#define DDRSS0_PHY_381_DATA 0x00A000A0
+#define DDRSS0_PHY_382_DATA 0x00A000A0
+#define DDRSS0_PHY_383_DATA 0x00A000A0
+#define DDRSS0_PHY_384_DATA 0x00A000A0
+#define DDRSS0_PHY_385_DATA 0x00A000A0
+#define DDRSS0_PHY_386_DATA 0x01C200A0
+#define DDRSS0_PHY_387_DATA 0x01A00005
+#define DDRSS0_PHY_388_DATA 0x00000000
+#define DDRSS0_PHY_389_DATA 0x00000000
+#define DDRSS0_PHY_390_DATA 0x00080200
+#define DDRSS0_PHY_391_DATA 0x00000000
+#define DDRSS0_PHY_392_DATA 0x20202000
+#define DDRSS0_PHY_393_DATA 0x20202020
+#define DDRSS0_PHY_394_DATA 0xF0F02020
+#define DDRSS0_PHY_395_DATA 0x00000000
+#define DDRSS0_PHY_396_DATA 0x00000000
+#define DDRSS0_PHY_397_DATA 0x00000000
+#define DDRSS0_PHY_398_DATA 0x00000000
+#define DDRSS0_PHY_399_DATA 0x00000000
+#define DDRSS0_PHY_400_DATA 0x00000000
+#define DDRSS0_PHY_401_DATA 0x00000000
+#define DDRSS0_PHY_402_DATA 0x00000000
+#define DDRSS0_PHY_403_DATA 0x00000000
+#define DDRSS0_PHY_404_DATA 0x00000000
+#define DDRSS0_PHY_405_DATA 0x00000000
+#define DDRSS0_PHY_406_DATA 0x00000000
+#define DDRSS0_PHY_407_DATA 0x00000000
+#define DDRSS0_PHY_408_DATA 0x00000000
+#define DDRSS0_PHY_409_DATA 0x00000000
+#define DDRSS0_PHY_410_DATA 0x00000000
+#define DDRSS0_PHY_411_DATA 0x00000000
+#define DDRSS0_PHY_412_DATA 0x00000000
+#define DDRSS0_PHY_413_DATA 0x00000000
+#define DDRSS0_PHY_414_DATA 0x00000000
+#define DDRSS0_PHY_415_DATA 0x00000000
+#define DDRSS0_PHY_416_DATA 0x00000000
+#define DDRSS0_PHY_417_DATA 0x00000000
+#define DDRSS0_PHY_418_DATA 0x00000000
+#define DDRSS0_PHY_419_DATA 0x00000000
+#define DDRSS0_PHY_420_DATA 0x00000000
+#define DDRSS0_PHY_421_DATA 0x00000000
+#define DDRSS0_PHY_422_DATA 0x00000000
+#define DDRSS0_PHY_423_DATA 0x00000000
+#define DDRSS0_PHY_424_DATA 0x00000000
+#define DDRSS0_PHY_425_DATA 0x00000000
+#define DDRSS0_PHY_426_DATA 0x00000000
+#define DDRSS0_PHY_427_DATA 0x00000000
+#define DDRSS0_PHY_428_DATA 0x00000000
+#define DDRSS0_PHY_429_DATA 0x00000000
+#define DDRSS0_PHY_430_DATA 0x00000000
+#define DDRSS0_PHY_431_DATA 0x00000000
+#define DDRSS0_PHY_432_DATA 0x00000000
+#define DDRSS0_PHY_433_DATA 0x00000000
+#define DDRSS0_PHY_434_DATA 0x00000000
+#define DDRSS0_PHY_435_DATA 0x00000000
+#define DDRSS0_PHY_436_DATA 0x00000000
+#define DDRSS0_PHY_437_DATA 0x00000000
+#define DDRSS0_PHY_438_DATA 0x00000000
+#define DDRSS0_PHY_439_DATA 0x00000000
+#define DDRSS0_PHY_440_DATA 0x00000000
+#define DDRSS0_PHY_441_DATA 0x00000000
+#define DDRSS0_PHY_442_DATA 0x00000000
+#define DDRSS0_PHY_443_DATA 0x00000000
+#define DDRSS0_PHY_444_DATA 0x00000000
+#define DDRSS0_PHY_445_DATA 0x00000000
+#define DDRSS0_PHY_446_DATA 0x00000000
+#define DDRSS0_PHY_447_DATA 0x00000000
+#define DDRSS0_PHY_448_DATA 0x00000000
+#define DDRSS0_PHY_449_DATA 0x00000000
+#define DDRSS0_PHY_450_DATA 0x00000000
+#define DDRSS0_PHY_451_DATA 0x00000000
+#define DDRSS0_PHY_452_DATA 0x00000000
+#define DDRSS0_PHY_453_DATA 0x00000000
+#define DDRSS0_PHY_454_DATA 0x00000000
+#define DDRSS0_PHY_455_DATA 0x00000000
+#define DDRSS0_PHY_456_DATA 0x00000000
+#define DDRSS0_PHY_457_DATA 0x00000000
+#define DDRSS0_PHY_458_DATA 0x00000000
+#define DDRSS0_PHY_459_DATA 0x00000000
+#define DDRSS0_PHY_460_DATA 0x00000000
+#define DDRSS0_PHY_461_DATA 0x00000000
+#define DDRSS0_PHY_462_DATA 0x00000000
+#define DDRSS0_PHY_463_DATA 0x00000000
+#define DDRSS0_PHY_464_DATA 0x00000000
+#define DDRSS0_PHY_465_DATA 0x00000000
+#define DDRSS0_PHY_466_DATA 0x00000000
+#define DDRSS0_PHY_467_DATA 0x00000000
+#define DDRSS0_PHY_468_DATA 0x00000000
+#define DDRSS0_PHY_469_DATA 0x00000000
+#define DDRSS0_PHY_470_DATA 0x00000000
+#define DDRSS0_PHY_471_DATA 0x00000000
+#define DDRSS0_PHY_472_DATA 0x00000000
+#define DDRSS0_PHY_473_DATA 0x00000000
+#define DDRSS0_PHY_474_DATA 0x00000000
+#define DDRSS0_PHY_475_DATA 0x00000000
+#define DDRSS0_PHY_476_DATA 0x00000000
+#define DDRSS0_PHY_477_DATA 0x00000000
+#define DDRSS0_PHY_478_DATA 0x00000000
+#define DDRSS0_PHY_479_DATA 0x00000000
+#define DDRSS0_PHY_480_DATA 0x00000000
+#define DDRSS0_PHY_481_DATA 0x00000000
+#define DDRSS0_PHY_482_DATA 0x00000000
+#define DDRSS0_PHY_483_DATA 0x00000000
+#define DDRSS0_PHY_484_DATA 0x00000000
+#define DDRSS0_PHY_485_DATA 0x00000000
+#define DDRSS0_PHY_486_DATA 0x00000000
+#define DDRSS0_PHY_487_DATA 0x00000000
+#define DDRSS0_PHY_488_DATA 0x00000000
+#define DDRSS0_PHY_489_DATA 0x00000000
+#define DDRSS0_PHY_490_DATA 0x00000000
+#define DDRSS0_PHY_491_DATA 0x00000000
+#define DDRSS0_PHY_492_DATA 0x00000000
+#define DDRSS0_PHY_493_DATA 0x00000000
+#define DDRSS0_PHY_494_DATA 0x00000000
+#define DDRSS0_PHY_495_DATA 0x00000000
+#define DDRSS0_PHY_496_DATA 0x00000000
+#define DDRSS0_PHY_497_DATA 0x00000000
+#define DDRSS0_PHY_498_DATA 0x00000000
+#define DDRSS0_PHY_499_DATA 0x00000000
+#define DDRSS0_PHY_500_DATA 0x00000000
+#define DDRSS0_PHY_501_DATA 0x00000000
+#define DDRSS0_PHY_502_DATA 0x00000000
+#define DDRSS0_PHY_503_DATA 0x00000000
+#define DDRSS0_PHY_504_DATA 0x00000000
+#define DDRSS0_PHY_505_DATA 0x00000000
+#define DDRSS0_PHY_506_DATA 0x00000000
+#define DDRSS0_PHY_507_DATA 0x00000000
+#define DDRSS0_PHY_508_DATA 0x00000000
+#define DDRSS0_PHY_509_DATA 0x00000000
+#define DDRSS0_PHY_510_DATA 0x00000000
+#define DDRSS0_PHY_511_DATA 0x00000000
+#define DDRSS0_PHY_512_DATA 0x000004F0
+#define DDRSS0_PHY_513_DATA 0x00000000
+#define DDRSS0_PHY_514_DATA 0x00030200
+#define DDRSS0_PHY_515_DATA 0x00000000
+#define DDRSS0_PHY_516_DATA 0x00000000
+#define DDRSS0_PHY_517_DATA 0x01030000
+#define DDRSS0_PHY_518_DATA 0x00010000
+#define DDRSS0_PHY_519_DATA 0x01030004
+#define DDRSS0_PHY_520_DATA 0x01000000
+#define DDRSS0_PHY_521_DATA 0x00000000
+#define DDRSS0_PHY_522_DATA 0x00000000
+#define DDRSS0_PHY_523_DATA 0x01000001
+#define DDRSS0_PHY_524_DATA 0x00000100
+#define DDRSS0_PHY_525_DATA 0x000800C0
+#define DDRSS0_PHY_526_DATA 0x060100CC
+#define DDRSS0_PHY_527_DATA 0x00030066
+#define DDRSS0_PHY_528_DATA 0x00000000
+#define DDRSS0_PHY_529_DATA 0x00000301
+#define DDRSS0_PHY_530_DATA 0x0000AAAA
+#define DDRSS0_PHY_531_DATA 0x00005555
+#define DDRSS0_PHY_532_DATA 0x0000B5B5
+#define DDRSS0_PHY_533_DATA 0x00004A4A
+#define DDRSS0_PHY_534_DATA 0x00005656
+#define DDRSS0_PHY_535_DATA 0x0000A9A9
+#define DDRSS0_PHY_536_DATA 0x0000A9A9
+#define DDRSS0_PHY_537_DATA 0x0000B5B5
+#define DDRSS0_PHY_538_DATA 0x00000000
+#define DDRSS0_PHY_539_DATA 0x00000000
+#define DDRSS0_PHY_540_DATA 0x2A000000
+#define DDRSS0_PHY_541_DATA 0x00000808
+#define DDRSS0_PHY_542_DATA 0x0F000000
+#define DDRSS0_PHY_543_DATA 0x00000F0F
+#define DDRSS0_PHY_544_DATA 0x10400000
+#define DDRSS0_PHY_545_DATA 0x0C002006
+#define DDRSS0_PHY_546_DATA 0x00000000
+#define DDRSS0_PHY_547_DATA 0x00000000
+#define DDRSS0_PHY_548_DATA 0x55555555
+#define DDRSS0_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_550_DATA 0x55555555
+#define DDRSS0_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_552_DATA 0x00005555
+#define DDRSS0_PHY_553_DATA 0x01000100
+#define DDRSS0_PHY_554_DATA 0x00800180
+#define DDRSS0_PHY_555_DATA 0x00000001
+#define DDRSS0_PHY_556_DATA 0x00000000
+#define DDRSS0_PHY_557_DATA 0x00000000
+#define DDRSS0_PHY_558_DATA 0x00000000
+#define DDRSS0_PHY_559_DATA 0x00000000
+#define DDRSS0_PHY_560_DATA 0x00000000
+#define DDRSS0_PHY_561_DATA 0x00000000
+#define DDRSS0_PHY_562_DATA 0x00000000
+#define DDRSS0_PHY_563_DATA 0x00000000
+#define DDRSS0_PHY_564_DATA 0x00000000
+#define DDRSS0_PHY_565_DATA 0x00000000
+#define DDRSS0_PHY_566_DATA 0x00000000
+#define DDRSS0_PHY_567_DATA 0x00000000
+#define DDRSS0_PHY_568_DATA 0x00000000
+#define DDRSS0_PHY_569_DATA 0x00000000
+#define DDRSS0_PHY_570_DATA 0x00000000
+#define DDRSS0_PHY_571_DATA 0x00000000
+#define DDRSS0_PHY_572_DATA 0x00000000
+#define DDRSS0_PHY_573_DATA 0x00000000
+#define DDRSS0_PHY_574_DATA 0x00000000
+#define DDRSS0_PHY_575_DATA 0x00000000
+#define DDRSS0_PHY_576_DATA 0x00000000
+#define DDRSS0_PHY_577_DATA 0x00000000
+#define DDRSS0_PHY_578_DATA 0x00000104
+#define DDRSS0_PHY_579_DATA 0x00000120
+#define DDRSS0_PHY_580_DATA 0x00000000
+#define DDRSS0_PHY_581_DATA 0x00000000
+#define DDRSS0_PHY_582_DATA 0x00000000
+#define DDRSS0_PHY_583_DATA 0x00000000
+#define DDRSS0_PHY_584_DATA 0x00000000
+#define DDRSS0_PHY_585_DATA 0x00000000
+#define DDRSS0_PHY_586_DATA 0x00000000
+#define DDRSS0_PHY_587_DATA 0x00000001
+#define DDRSS0_PHY_588_DATA 0x07FF0000
+#define DDRSS0_PHY_589_DATA 0x0080081F
+#define DDRSS0_PHY_590_DATA 0x00081020
+#define DDRSS0_PHY_591_DATA 0x04010000
+#define DDRSS0_PHY_592_DATA 0x00000000
+#define DDRSS0_PHY_593_DATA 0x00000000
+#define DDRSS0_PHY_594_DATA 0x00000000
+#define DDRSS0_PHY_595_DATA 0x00000100
+#define DDRSS0_PHY_596_DATA 0x01CC0C01
+#define DDRSS0_PHY_597_DATA 0x1003CC0C
+#define DDRSS0_PHY_598_DATA 0x20000140
+#define DDRSS0_PHY_599_DATA 0x07FF0200
+#define DDRSS0_PHY_600_DATA 0x0000DD01
+#define DDRSS0_PHY_601_DATA 0x10100303
+#define DDRSS0_PHY_602_DATA 0x10101010
+#define DDRSS0_PHY_603_DATA 0x10101010
+#define DDRSS0_PHY_604_DATA 0x00021010
+#define DDRSS0_PHY_605_DATA 0x00100010
+#define DDRSS0_PHY_606_DATA 0x00100010
+#define DDRSS0_PHY_607_DATA 0x00100010
+#define DDRSS0_PHY_608_DATA 0x00100010
+#define DDRSS0_PHY_609_DATA 0x00050010
+#define DDRSS0_PHY_610_DATA 0x51517041
+#define DDRSS0_PHY_611_DATA 0x31C06001
+#define DDRSS0_PHY_612_DATA 0x07AB0340
+#define DDRSS0_PHY_613_DATA 0x00C0C001
+#define DDRSS0_PHY_614_DATA 0x0E0D0001
+#define DDRSS0_PHY_615_DATA 0x10001000
+#define DDRSS0_PHY_616_DATA 0x0C083E42
+#define DDRSS0_PHY_617_DATA 0x0F0C3701
+#define DDRSS0_PHY_618_DATA 0x01000140
+#define DDRSS0_PHY_619_DATA 0x0C000420
+#define DDRSS0_PHY_620_DATA 0x00000198
+#define DDRSS0_PHY_621_DATA 0x0A0000D0
+#define DDRSS0_PHY_622_DATA 0x00030200
+#define DDRSS0_PHY_623_DATA 0x02800000
+#define DDRSS0_PHY_624_DATA 0x80800000
+#define DDRSS0_PHY_625_DATA 0x000E2010
+#define DDRSS0_PHY_626_DATA 0x76543210
+#define DDRSS0_PHY_627_DATA 0x00000008
+#define DDRSS0_PHY_628_DATA 0x02800280
+#define DDRSS0_PHY_629_DATA 0x02800280
+#define DDRSS0_PHY_630_DATA 0x02800280
+#define DDRSS0_PHY_631_DATA 0x02800280
+#define DDRSS0_PHY_632_DATA 0x00000280
+#define DDRSS0_PHY_633_DATA 0x0000A000
+#define DDRSS0_PHY_634_DATA 0x00A000A0
+#define DDRSS0_PHY_635_DATA 0x00A000A0
+#define DDRSS0_PHY_636_DATA 0x00A000A0
+#define DDRSS0_PHY_637_DATA 0x00A000A0
+#define DDRSS0_PHY_638_DATA 0x00A000A0
+#define DDRSS0_PHY_639_DATA 0x00A000A0
+#define DDRSS0_PHY_640_DATA 0x00A000A0
+#define DDRSS0_PHY_641_DATA 0x00A000A0
+#define DDRSS0_PHY_642_DATA 0x01C200A0
+#define DDRSS0_PHY_643_DATA 0x01A00005
+#define DDRSS0_PHY_644_DATA 0x00000000
+#define DDRSS0_PHY_645_DATA 0x00000000
+#define DDRSS0_PHY_646_DATA 0x00080200
+#define DDRSS0_PHY_647_DATA 0x00000000
+#define DDRSS0_PHY_648_DATA 0x20202000
+#define DDRSS0_PHY_649_DATA 0x20202020
+#define DDRSS0_PHY_650_DATA 0xF0F02020
+#define DDRSS0_PHY_651_DATA 0x00000000
+#define DDRSS0_PHY_652_DATA 0x00000000
+#define DDRSS0_PHY_653_DATA 0x00000000
+#define DDRSS0_PHY_654_DATA 0x00000000
+#define DDRSS0_PHY_655_DATA 0x00000000
+#define DDRSS0_PHY_656_DATA 0x00000000
+#define DDRSS0_PHY_657_DATA 0x00000000
+#define DDRSS0_PHY_658_DATA 0x00000000
+#define DDRSS0_PHY_659_DATA 0x00000000
+#define DDRSS0_PHY_660_DATA 0x00000000
+#define DDRSS0_PHY_661_DATA 0x00000000
+#define DDRSS0_PHY_662_DATA 0x00000000
+#define DDRSS0_PHY_663_DATA 0x00000000
+#define DDRSS0_PHY_664_DATA 0x00000000
+#define DDRSS0_PHY_665_DATA 0x00000000
+#define DDRSS0_PHY_666_DATA 0x00000000
+#define DDRSS0_PHY_667_DATA 0x00000000
+#define DDRSS0_PHY_668_DATA 0x00000000
+#define DDRSS0_PHY_669_DATA 0x00000000
+#define DDRSS0_PHY_670_DATA 0x00000000
+#define DDRSS0_PHY_671_DATA 0x00000000
+#define DDRSS0_PHY_672_DATA 0x00000000
+#define DDRSS0_PHY_673_DATA 0x00000000
+#define DDRSS0_PHY_674_DATA 0x00000000
+#define DDRSS0_PHY_675_DATA 0x00000000
+#define DDRSS0_PHY_676_DATA 0x00000000
+#define DDRSS0_PHY_677_DATA 0x00000000
+#define DDRSS0_PHY_678_DATA 0x00000000
+#define DDRSS0_PHY_679_DATA 0x00000000
+#define DDRSS0_PHY_680_DATA 0x00000000
+#define DDRSS0_PHY_681_DATA 0x00000000
+#define DDRSS0_PHY_682_DATA 0x00000000
+#define DDRSS0_PHY_683_DATA 0x00000000
+#define DDRSS0_PHY_684_DATA 0x00000000
+#define DDRSS0_PHY_685_DATA 0x00000000
+#define DDRSS0_PHY_686_DATA 0x00000000
+#define DDRSS0_PHY_687_DATA 0x00000000
+#define DDRSS0_PHY_688_DATA 0x00000000
+#define DDRSS0_PHY_689_DATA 0x00000000
+#define DDRSS0_PHY_690_DATA 0x00000000
+#define DDRSS0_PHY_691_DATA 0x00000000
+#define DDRSS0_PHY_692_DATA 0x00000000
+#define DDRSS0_PHY_693_DATA 0x00000000
+#define DDRSS0_PHY_694_DATA 0x00000000
+#define DDRSS0_PHY_695_DATA 0x00000000
+#define DDRSS0_PHY_696_DATA 0x00000000
+#define DDRSS0_PHY_697_DATA 0x00000000
+#define DDRSS0_PHY_698_DATA 0x00000000
+#define DDRSS0_PHY_699_DATA 0x00000000
+#define DDRSS0_PHY_700_DATA 0x00000000
+#define DDRSS0_PHY_701_DATA 0x00000000
+#define DDRSS0_PHY_702_DATA 0x00000000
+#define DDRSS0_PHY_703_DATA 0x00000000
+#define DDRSS0_PHY_704_DATA 0x00000000
+#define DDRSS0_PHY_705_DATA 0x00000000
+#define DDRSS0_PHY_706_DATA 0x00000000
+#define DDRSS0_PHY_707_DATA 0x00000000
+#define DDRSS0_PHY_708_DATA 0x00000000
+#define DDRSS0_PHY_709_DATA 0x00000000
+#define DDRSS0_PHY_710_DATA 0x00000000
+#define DDRSS0_PHY_711_DATA 0x00000000
+#define DDRSS0_PHY_712_DATA 0x00000000
+#define DDRSS0_PHY_713_DATA 0x00000000
+#define DDRSS0_PHY_714_DATA 0x00000000
+#define DDRSS0_PHY_715_DATA 0x00000000
+#define DDRSS0_PHY_716_DATA 0x00000000
+#define DDRSS0_PHY_717_DATA 0x00000000
+#define DDRSS0_PHY_718_DATA 0x00000000
+#define DDRSS0_PHY_719_DATA 0x00000000
+#define DDRSS0_PHY_720_DATA 0x00000000
+#define DDRSS0_PHY_721_DATA 0x00000000
+#define DDRSS0_PHY_722_DATA 0x00000000
+#define DDRSS0_PHY_723_DATA 0x00000000
+#define DDRSS0_PHY_724_DATA 0x00000000
+#define DDRSS0_PHY_725_DATA 0x00000000
+#define DDRSS0_PHY_726_DATA 0x00000000
+#define DDRSS0_PHY_727_DATA 0x00000000
+#define DDRSS0_PHY_728_DATA 0x00000000
+#define DDRSS0_PHY_729_DATA 0x00000000
+#define DDRSS0_PHY_730_DATA 0x00000000
+#define DDRSS0_PHY_731_DATA 0x00000000
+#define DDRSS0_PHY_732_DATA 0x00000000
+#define DDRSS0_PHY_733_DATA 0x00000000
+#define DDRSS0_PHY_734_DATA 0x00000000
+#define DDRSS0_PHY_735_DATA 0x00000000
+#define DDRSS0_PHY_736_DATA 0x00000000
+#define DDRSS0_PHY_737_DATA 0x00000000
+#define DDRSS0_PHY_738_DATA 0x00000000
+#define DDRSS0_PHY_739_DATA 0x00000000
+#define DDRSS0_PHY_740_DATA 0x00000000
+#define DDRSS0_PHY_741_DATA 0x00000000
+#define DDRSS0_PHY_742_DATA 0x00000000
+#define DDRSS0_PHY_743_DATA 0x00000000
+#define DDRSS0_PHY_744_DATA 0x00000000
+#define DDRSS0_PHY_745_DATA 0x00000000
+#define DDRSS0_PHY_746_DATA 0x00000000
+#define DDRSS0_PHY_747_DATA 0x00000000
+#define DDRSS0_PHY_748_DATA 0x00000000
+#define DDRSS0_PHY_749_DATA 0x00000000
+#define DDRSS0_PHY_750_DATA 0x00000000
+#define DDRSS0_PHY_751_DATA 0x00000000
+#define DDRSS0_PHY_752_DATA 0x00000000
+#define DDRSS0_PHY_753_DATA 0x00000000
+#define DDRSS0_PHY_754_DATA 0x00000000
+#define DDRSS0_PHY_755_DATA 0x00000000
+#define DDRSS0_PHY_756_DATA 0x00000000
+#define DDRSS0_PHY_757_DATA 0x00000000
+#define DDRSS0_PHY_758_DATA 0x00000000
+#define DDRSS0_PHY_759_DATA 0x00000000
+#define DDRSS0_PHY_760_DATA 0x00000000
+#define DDRSS0_PHY_761_DATA 0x00000000
+#define DDRSS0_PHY_762_DATA 0x00000000
+#define DDRSS0_PHY_763_DATA 0x00000000
+#define DDRSS0_PHY_764_DATA 0x00000000
+#define DDRSS0_PHY_765_DATA 0x00000000
+#define DDRSS0_PHY_766_DATA 0x00000000
+#define DDRSS0_PHY_767_DATA 0x00000000
+#define DDRSS0_PHY_768_DATA 0x000004F0
+#define DDRSS0_PHY_769_DATA 0x00000000
+#define DDRSS0_PHY_770_DATA 0x00030200
+#define DDRSS0_PHY_771_DATA 0x00000000
+#define DDRSS0_PHY_772_DATA 0x00000000
+#define DDRSS0_PHY_773_DATA 0x01030000
+#define DDRSS0_PHY_774_DATA 0x00010000
+#define DDRSS0_PHY_775_DATA 0x01030004
+#define DDRSS0_PHY_776_DATA 0x01000000
+#define DDRSS0_PHY_777_DATA 0x00000000
+#define DDRSS0_PHY_778_DATA 0x00000000
+#define DDRSS0_PHY_779_DATA 0x01000001
+#define DDRSS0_PHY_780_DATA 0x00000100
+#define DDRSS0_PHY_781_DATA 0x000800C0
+#define DDRSS0_PHY_782_DATA 0x060100CC
+#define DDRSS0_PHY_783_DATA 0x00030066
+#define DDRSS0_PHY_784_DATA 0x00000000
+#define DDRSS0_PHY_785_DATA 0x00000301
+#define DDRSS0_PHY_786_DATA 0x0000AAAA
+#define DDRSS0_PHY_787_DATA 0x00005555
+#define DDRSS0_PHY_788_DATA 0x0000B5B5
+#define DDRSS0_PHY_789_DATA 0x00004A4A
+#define DDRSS0_PHY_790_DATA 0x00005656
+#define DDRSS0_PHY_791_DATA 0x0000A9A9
+#define DDRSS0_PHY_792_DATA 0x0000A9A9
+#define DDRSS0_PHY_793_DATA 0x0000B5B5
+#define DDRSS0_PHY_794_DATA 0x00000000
+#define DDRSS0_PHY_795_DATA 0x00000000
+#define DDRSS0_PHY_796_DATA 0x2A000000
+#define DDRSS0_PHY_797_DATA 0x00000808
+#define DDRSS0_PHY_798_DATA 0x0F000000
+#define DDRSS0_PHY_799_DATA 0x00000F0F
+#define DDRSS0_PHY_800_DATA 0x10400000
+#define DDRSS0_PHY_801_DATA 0x0C002006
+#define DDRSS0_PHY_802_DATA 0x00000000
+#define DDRSS0_PHY_803_DATA 0x00000000
+#define DDRSS0_PHY_804_DATA 0x55555555
+#define DDRSS0_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_806_DATA 0x55555555
+#define DDRSS0_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_808_DATA 0x00005555
+#define DDRSS0_PHY_809_DATA 0x01000100
+#define DDRSS0_PHY_810_DATA 0x00800180
+#define DDRSS0_PHY_811_DATA 0x00000000
+#define DDRSS0_PHY_812_DATA 0x00000000
+#define DDRSS0_PHY_813_DATA 0x00000000
+#define DDRSS0_PHY_814_DATA 0x00000000
+#define DDRSS0_PHY_815_DATA 0x00000000
+#define DDRSS0_PHY_816_DATA 0x00000000
+#define DDRSS0_PHY_817_DATA 0x00000000
+#define DDRSS0_PHY_818_DATA 0x00000000
+#define DDRSS0_PHY_819_DATA 0x00000000
+#define DDRSS0_PHY_820_DATA 0x00000000
+#define DDRSS0_PHY_821_DATA 0x00000000
+#define DDRSS0_PHY_822_DATA 0x00000000
+#define DDRSS0_PHY_823_DATA 0x00000000
+#define DDRSS0_PHY_824_DATA 0x00000000
+#define DDRSS0_PHY_825_DATA 0x00000000
+#define DDRSS0_PHY_826_DATA 0x00000000
+#define DDRSS0_PHY_827_DATA 0x00000000
+#define DDRSS0_PHY_828_DATA 0x00000000
+#define DDRSS0_PHY_829_DATA 0x00000000
+#define DDRSS0_PHY_830_DATA 0x00000000
+#define DDRSS0_PHY_831_DATA 0x00000000
+#define DDRSS0_PHY_832_DATA 0x00000000
+#define DDRSS0_PHY_833_DATA 0x00000000
+#define DDRSS0_PHY_834_DATA 0x00000104
+#define DDRSS0_PHY_835_DATA 0x00000120
+#define DDRSS0_PHY_836_DATA 0x00000000
+#define DDRSS0_PHY_837_DATA 0x00000000
+#define DDRSS0_PHY_838_DATA 0x00000000
+#define DDRSS0_PHY_839_DATA 0x00000000
+#define DDRSS0_PHY_840_DATA 0x00000000
+#define DDRSS0_PHY_841_DATA 0x00000000
+#define DDRSS0_PHY_842_DATA 0x00000000
+#define DDRSS0_PHY_843_DATA 0x00000001
+#define DDRSS0_PHY_844_DATA 0x07FF0000
+#define DDRSS0_PHY_845_DATA 0x0080081F
+#define DDRSS0_PHY_846_DATA 0x00081020
+#define DDRSS0_PHY_847_DATA 0x04010000
+#define DDRSS0_PHY_848_DATA 0x00000000
+#define DDRSS0_PHY_849_DATA 0x00000000
+#define DDRSS0_PHY_850_DATA 0x00000000
+#define DDRSS0_PHY_851_DATA 0x00000100
+#define DDRSS0_PHY_852_DATA 0x01CC0C01
+#define DDRSS0_PHY_853_DATA 0x1003CC0C
+#define DDRSS0_PHY_854_DATA 0x20000140
+#define DDRSS0_PHY_855_DATA 0x07FF0200
+#define DDRSS0_PHY_856_DATA 0x0000DD01
+#define DDRSS0_PHY_857_DATA 0x10100303
+#define DDRSS0_PHY_858_DATA 0x10101010
+#define DDRSS0_PHY_859_DATA 0x10101010
+#define DDRSS0_PHY_860_DATA 0x00021010
+#define DDRSS0_PHY_861_DATA 0x00100010
+#define DDRSS0_PHY_862_DATA 0x00100010
+#define DDRSS0_PHY_863_DATA 0x00100010
+#define DDRSS0_PHY_864_DATA 0x00100010
+#define DDRSS0_PHY_865_DATA 0x00050010
+#define DDRSS0_PHY_866_DATA 0x51517041
+#define DDRSS0_PHY_867_DATA 0x31C06001
+#define DDRSS0_PHY_868_DATA 0x07AB0340
+#define DDRSS0_PHY_869_DATA 0x00C0C001
+#define DDRSS0_PHY_870_DATA 0x0E0D0001
+#define DDRSS0_PHY_871_DATA 0x10001000
+#define DDRSS0_PHY_872_DATA 0x0C083E42
+#define DDRSS0_PHY_873_DATA 0x0F0C3701
+#define DDRSS0_PHY_874_DATA 0x01000140
+#define DDRSS0_PHY_875_DATA 0x0C000420
+#define DDRSS0_PHY_876_DATA 0x00000198
+#define DDRSS0_PHY_877_DATA 0x0A0000D0
+#define DDRSS0_PHY_878_DATA 0x00030200
+#define DDRSS0_PHY_879_DATA 0x02800000
+#define DDRSS0_PHY_880_DATA 0x80800000
+#define DDRSS0_PHY_881_DATA 0x000E2010
+#define DDRSS0_PHY_882_DATA 0x76543210
+#define DDRSS0_PHY_883_DATA 0x00000008
+#define DDRSS0_PHY_884_DATA 0x02800280
+#define DDRSS0_PHY_885_DATA 0x02800280
+#define DDRSS0_PHY_886_DATA 0x02800280
+#define DDRSS0_PHY_887_DATA 0x02800280
+#define DDRSS0_PHY_888_DATA 0x00000280
+#define DDRSS0_PHY_889_DATA 0x0000A000
+#define DDRSS0_PHY_890_DATA 0x00A000A0
+#define DDRSS0_PHY_891_DATA 0x00A000A0
+#define DDRSS0_PHY_892_DATA 0x00A000A0
+#define DDRSS0_PHY_893_DATA 0x00A000A0
+#define DDRSS0_PHY_894_DATA 0x00A000A0
+#define DDRSS0_PHY_895_DATA 0x00A000A0
+#define DDRSS0_PHY_896_DATA 0x00A000A0
+#define DDRSS0_PHY_897_DATA 0x00A000A0
+#define DDRSS0_PHY_898_DATA 0x01C200A0
+#define DDRSS0_PHY_899_DATA 0x01A00005
+#define DDRSS0_PHY_900_DATA 0x00000000
+#define DDRSS0_PHY_901_DATA 0x00000000
+#define DDRSS0_PHY_902_DATA 0x00080200
+#define DDRSS0_PHY_903_DATA 0x00000000
+#define DDRSS0_PHY_904_DATA 0x20202000
+#define DDRSS0_PHY_905_DATA 0x20202020
+#define DDRSS0_PHY_906_DATA 0xF0F02020
+#define DDRSS0_PHY_907_DATA 0x00000000
+#define DDRSS0_PHY_908_DATA 0x00000000
+#define DDRSS0_PHY_909_DATA 0x00000000
+#define DDRSS0_PHY_910_DATA 0x00000000
+#define DDRSS0_PHY_911_DATA 0x00000000
+#define DDRSS0_PHY_912_DATA 0x00000000
+#define DDRSS0_PHY_913_DATA 0x00000000
+#define DDRSS0_PHY_914_DATA 0x00000000
+#define DDRSS0_PHY_915_DATA 0x00000000
+#define DDRSS0_PHY_916_DATA 0x00000000
+#define DDRSS0_PHY_917_DATA 0x00000000
+#define DDRSS0_PHY_918_DATA 0x00000000
+#define DDRSS0_PHY_919_DATA 0x00000000
+#define DDRSS0_PHY_920_DATA 0x00000000
+#define DDRSS0_PHY_921_DATA 0x00000000
+#define DDRSS0_PHY_922_DATA 0x00000000
+#define DDRSS0_PHY_923_DATA 0x00000000
+#define DDRSS0_PHY_924_DATA 0x00000000
+#define DDRSS0_PHY_925_DATA 0x00000000
+#define DDRSS0_PHY_926_DATA 0x00000000
+#define DDRSS0_PHY_927_DATA 0x00000000
+#define DDRSS0_PHY_928_DATA 0x00000000
+#define DDRSS0_PHY_929_DATA 0x00000000
+#define DDRSS0_PHY_930_DATA 0x00000000
+#define DDRSS0_PHY_931_DATA 0x00000000
+#define DDRSS0_PHY_932_DATA 0x00000000
+#define DDRSS0_PHY_933_DATA 0x00000000
+#define DDRSS0_PHY_934_DATA 0x00000000
+#define DDRSS0_PHY_935_DATA 0x00000000
+#define DDRSS0_PHY_936_DATA 0x00000000
+#define DDRSS0_PHY_937_DATA 0x00000000
+#define DDRSS0_PHY_938_DATA 0x00000000
+#define DDRSS0_PHY_939_DATA 0x00000000
+#define DDRSS0_PHY_940_DATA 0x00000000
+#define DDRSS0_PHY_941_DATA 0x00000000
+#define DDRSS0_PHY_942_DATA 0x00000000
+#define DDRSS0_PHY_943_DATA 0x00000000
+#define DDRSS0_PHY_944_DATA 0x00000000
+#define DDRSS0_PHY_945_DATA 0x00000000
+#define DDRSS0_PHY_946_DATA 0x00000000
+#define DDRSS0_PHY_947_DATA 0x00000000
+#define DDRSS0_PHY_948_DATA 0x00000000
+#define DDRSS0_PHY_949_DATA 0x00000000
+#define DDRSS0_PHY_950_DATA 0x00000000
+#define DDRSS0_PHY_951_DATA 0x00000000
+#define DDRSS0_PHY_952_DATA 0x00000000
+#define DDRSS0_PHY_953_DATA 0x00000000
+#define DDRSS0_PHY_954_DATA 0x00000000
+#define DDRSS0_PHY_955_DATA 0x00000000
+#define DDRSS0_PHY_956_DATA 0x00000000
+#define DDRSS0_PHY_957_DATA 0x00000000
+#define DDRSS0_PHY_958_DATA 0x00000000
+#define DDRSS0_PHY_959_DATA 0x00000000
+#define DDRSS0_PHY_960_DATA 0x00000000
+#define DDRSS0_PHY_961_DATA 0x00000000
+#define DDRSS0_PHY_962_DATA 0x00000000
+#define DDRSS0_PHY_963_DATA 0x00000000
+#define DDRSS0_PHY_964_DATA 0x00000000
+#define DDRSS0_PHY_965_DATA 0x00000000
+#define DDRSS0_PHY_966_DATA 0x00000000
+#define DDRSS0_PHY_967_DATA 0x00000000
+#define DDRSS0_PHY_968_DATA 0x00000000
+#define DDRSS0_PHY_969_DATA 0x00000000
+#define DDRSS0_PHY_970_DATA 0x00000000
+#define DDRSS0_PHY_971_DATA 0x00000000
+#define DDRSS0_PHY_972_DATA 0x00000000
+#define DDRSS0_PHY_973_DATA 0x00000000
+#define DDRSS0_PHY_974_DATA 0x00000000
+#define DDRSS0_PHY_975_DATA 0x00000000
+#define DDRSS0_PHY_976_DATA 0x00000000
+#define DDRSS0_PHY_977_DATA 0x00000000
+#define DDRSS0_PHY_978_DATA 0x00000000
+#define DDRSS0_PHY_979_DATA 0x00000000
+#define DDRSS0_PHY_980_DATA 0x00000000
+#define DDRSS0_PHY_981_DATA 0x00000000
+#define DDRSS0_PHY_982_DATA 0x00000000
+#define DDRSS0_PHY_983_DATA 0x00000000
+#define DDRSS0_PHY_984_DATA 0x00000000
+#define DDRSS0_PHY_985_DATA 0x00000000
+#define DDRSS0_PHY_986_DATA 0x00000000
+#define DDRSS0_PHY_987_DATA 0x00000000
+#define DDRSS0_PHY_988_DATA 0x00000000
+#define DDRSS0_PHY_989_DATA 0x00000000
+#define DDRSS0_PHY_990_DATA 0x00000000
+#define DDRSS0_PHY_991_DATA 0x00000000
+#define DDRSS0_PHY_992_DATA 0x00000000
+#define DDRSS0_PHY_993_DATA 0x00000000
+#define DDRSS0_PHY_994_DATA 0x00000000
+#define DDRSS0_PHY_995_DATA 0x00000000
+#define DDRSS0_PHY_996_DATA 0x00000000
+#define DDRSS0_PHY_997_DATA 0x00000000
+#define DDRSS0_PHY_998_DATA 0x00000000
+#define DDRSS0_PHY_999_DATA 0x00000000
+#define DDRSS0_PHY_1000_DATA 0x00000000
+#define DDRSS0_PHY_1001_DATA 0x00000000
+#define DDRSS0_PHY_1002_DATA 0x00000000
+#define DDRSS0_PHY_1003_DATA 0x00000000
+#define DDRSS0_PHY_1004_DATA 0x00000000
+#define DDRSS0_PHY_1005_DATA 0x00000000
+#define DDRSS0_PHY_1006_DATA 0x00000000
+#define DDRSS0_PHY_1007_DATA 0x00000000
+#define DDRSS0_PHY_1008_DATA 0x00000000
+#define DDRSS0_PHY_1009_DATA 0x00000000
+#define DDRSS0_PHY_1010_DATA 0x00000000
+#define DDRSS0_PHY_1011_DATA 0x00000000
+#define DDRSS0_PHY_1012_DATA 0x00000000
+#define DDRSS0_PHY_1013_DATA 0x00000000
+#define DDRSS0_PHY_1014_DATA 0x00000000
+#define DDRSS0_PHY_1015_DATA 0x00000000
+#define DDRSS0_PHY_1016_DATA 0x00000000
+#define DDRSS0_PHY_1017_DATA 0x00000000
+#define DDRSS0_PHY_1018_DATA 0x00000000
+#define DDRSS0_PHY_1019_DATA 0x00000000
+#define DDRSS0_PHY_1020_DATA 0x00000000
+#define DDRSS0_PHY_1021_DATA 0x00000000
+#define DDRSS0_PHY_1022_DATA 0x00000000
+#define DDRSS0_PHY_1023_DATA 0x00000000
+#define DDRSS0_PHY_1024_DATA 0x00000000
+#define DDRSS0_PHY_1025_DATA 0x00000000
+#define DDRSS0_PHY_1026_DATA 0x00000000
+#define DDRSS0_PHY_1027_DATA 0x00000000
+#define DDRSS0_PHY_1028_DATA 0x00000000
+#define DDRSS0_PHY_1029_DATA 0x00000100
+#define DDRSS0_PHY_1030_DATA 0x00000200
+#define DDRSS0_PHY_1031_DATA 0x00000000
+#define DDRSS0_PHY_1032_DATA 0x00000000
+#define DDRSS0_PHY_1033_DATA 0x00000000
+#define DDRSS0_PHY_1034_DATA 0x00000000
+#define DDRSS0_PHY_1035_DATA 0x00400000
+#define DDRSS0_PHY_1036_DATA 0x00000080
+#define DDRSS0_PHY_1037_DATA 0x00DCBA98
+#define DDRSS0_PHY_1038_DATA 0x03000000
+#define DDRSS0_PHY_1039_DATA 0x00200000
+#define DDRSS0_PHY_1040_DATA 0x00000000
+#define DDRSS0_PHY_1041_DATA 0x00000000
+#define DDRSS0_PHY_1042_DATA 0x00000000
+#define DDRSS0_PHY_1043_DATA 0x00000000
+#define DDRSS0_PHY_1044_DATA 0x00000000
+#define DDRSS0_PHY_1045_DATA 0x0000002A
+#define DDRSS0_PHY_1046_DATA 0x00000015
+#define DDRSS0_PHY_1047_DATA 0x00000015
+#define DDRSS0_PHY_1048_DATA 0x0000002A
+#define DDRSS0_PHY_1049_DATA 0x00000033
+#define DDRSS0_PHY_1050_DATA 0x0000000C
+#define DDRSS0_PHY_1051_DATA 0x0000000C
+#define DDRSS0_PHY_1052_DATA 0x00000033
+#define DDRSS0_PHY_1053_DATA 0x00543210
+#define DDRSS0_PHY_1054_DATA 0x003F0000
+#define DDRSS0_PHY_1055_DATA 0x000F013F
+#define DDRSS0_PHY_1056_DATA 0x20202003
+#define DDRSS0_PHY_1057_DATA 0x00202020
+#define DDRSS0_PHY_1058_DATA 0x20008008
+#define DDRSS0_PHY_1059_DATA 0x00000810
+#define DDRSS0_PHY_1060_DATA 0x00000F00
+#define DDRSS0_PHY_1061_DATA 0x00000000
+#define DDRSS0_PHY_1062_DATA 0x00000000
+#define DDRSS0_PHY_1063_DATA 0x00000000
+#define DDRSS0_PHY_1064_DATA 0x000305CC
+#define DDRSS0_PHY_1065_DATA 0x00030000
+#define DDRSS0_PHY_1066_DATA 0x00000300
+#define DDRSS0_PHY_1067_DATA 0x00000300
+#define DDRSS0_PHY_1068_DATA 0x00000300
+#define DDRSS0_PHY_1069_DATA 0x00000300
+#define DDRSS0_PHY_1070_DATA 0x00000300
+#define DDRSS0_PHY_1071_DATA 0x42080010
+#define DDRSS0_PHY_1072_DATA 0x0000803E
+#define DDRSS0_PHY_1073_DATA 0x00000001
+#define DDRSS0_PHY_1074_DATA 0x01000102
+#define DDRSS0_PHY_1075_DATA 0x00008000
+#define DDRSS0_PHY_1076_DATA 0x00000000
+#define DDRSS0_PHY_1077_DATA 0x00000000
+#define DDRSS0_PHY_1078_DATA 0x00000000
+#define DDRSS0_PHY_1079_DATA 0x00000000
+#define DDRSS0_PHY_1080_DATA 0x00000000
+#define DDRSS0_PHY_1081_DATA 0x00000000
+#define DDRSS0_PHY_1082_DATA 0x00000000
+#define DDRSS0_PHY_1083_DATA 0x00000000
+#define DDRSS0_PHY_1084_DATA 0x00000000
+#define DDRSS0_PHY_1085_DATA 0x00000000
+#define DDRSS0_PHY_1086_DATA 0x00000000
+#define DDRSS0_PHY_1087_DATA 0x00000000
+#define DDRSS0_PHY_1088_DATA 0x00000000
+#define DDRSS0_PHY_1089_DATA 0x00000000
+#define DDRSS0_PHY_1090_DATA 0x00000000
+#define DDRSS0_PHY_1091_DATA 0x00000000
+#define DDRSS0_PHY_1092_DATA 0x00000000
+#define DDRSS0_PHY_1093_DATA 0x00000000
+#define DDRSS0_PHY_1094_DATA 0x00000000
+#define DDRSS0_PHY_1095_DATA 0x00000000
+#define DDRSS0_PHY_1096_DATA 0x00000000
+#define DDRSS0_PHY_1097_DATA 0x00000000
+#define DDRSS0_PHY_1098_DATA 0x00000000
+#define DDRSS0_PHY_1099_DATA 0x00000000
+#define DDRSS0_PHY_1100_DATA 0x00000000
+#define DDRSS0_PHY_1101_DATA 0x00000000
+#define DDRSS0_PHY_1102_DATA 0x00000000
+#define DDRSS0_PHY_1103_DATA 0x00000000
+#define DDRSS0_PHY_1104_DATA 0x00000000
+#define DDRSS0_PHY_1105_DATA 0x00000000
+#define DDRSS0_PHY_1106_DATA 0x00000000
+#define DDRSS0_PHY_1107_DATA 0x00000000
+#define DDRSS0_PHY_1108_DATA 0x00000000
+#define DDRSS0_PHY_1109_DATA 0x00000000
+#define DDRSS0_PHY_1110_DATA 0x00000000
+#define DDRSS0_PHY_1111_DATA 0x00000000
+#define DDRSS0_PHY_1112_DATA 0x00000000
+#define DDRSS0_PHY_1113_DATA 0x00000000
+#define DDRSS0_PHY_1114_DATA 0x00000000
+#define DDRSS0_PHY_1115_DATA 0x00000000
+#define DDRSS0_PHY_1116_DATA 0x00000000
+#define DDRSS0_PHY_1117_DATA 0x00000000
+#define DDRSS0_PHY_1118_DATA 0x00000000
+#define DDRSS0_PHY_1119_DATA 0x00000000
+#define DDRSS0_PHY_1120_DATA 0x00000000
+#define DDRSS0_PHY_1121_DATA 0x00000000
+#define DDRSS0_PHY_1122_DATA 0x00000000
+#define DDRSS0_PHY_1123_DATA 0x00000000
+#define DDRSS0_PHY_1124_DATA 0x00000000
+#define DDRSS0_PHY_1125_DATA 0x00000000
+#define DDRSS0_PHY_1126_DATA 0x00000000
+#define DDRSS0_PHY_1127_DATA 0x00000000
+#define DDRSS0_PHY_1128_DATA 0x00000000
+#define DDRSS0_PHY_1129_DATA 0x00000000
+#define DDRSS0_PHY_1130_DATA 0x00000000
+#define DDRSS0_PHY_1131_DATA 0x00000000
+#define DDRSS0_PHY_1132_DATA 0x00000000
+#define DDRSS0_PHY_1133_DATA 0x00000000
+#define DDRSS0_PHY_1134_DATA 0x00000000
+#define DDRSS0_PHY_1135_DATA 0x00000000
+#define DDRSS0_PHY_1136_DATA 0x00000000
+#define DDRSS0_PHY_1137_DATA 0x00000000
+#define DDRSS0_PHY_1138_DATA 0x00000000
+#define DDRSS0_PHY_1139_DATA 0x00000000
+#define DDRSS0_PHY_1140_DATA 0x00000000
+#define DDRSS0_PHY_1141_DATA 0x00000000
+#define DDRSS0_PHY_1142_DATA 0x00000000
+#define DDRSS0_PHY_1143_DATA 0x00000000
+#define DDRSS0_PHY_1144_DATA 0x00000000
+#define DDRSS0_PHY_1145_DATA 0x00000000
+#define DDRSS0_PHY_1146_DATA 0x00000000
+#define DDRSS0_PHY_1147_DATA 0x00000000
+#define DDRSS0_PHY_1148_DATA 0x00000000
+#define DDRSS0_PHY_1149_DATA 0x00000000
+#define DDRSS0_PHY_1150_DATA 0x00000000
+#define DDRSS0_PHY_1151_DATA 0x00000000
+#define DDRSS0_PHY_1152_DATA 0x00000000
+#define DDRSS0_PHY_1153_DATA 0x00000000
+#define DDRSS0_PHY_1154_DATA 0x00000000
+#define DDRSS0_PHY_1155_DATA 0x00000000
+#define DDRSS0_PHY_1156_DATA 0x00000000
+#define DDRSS0_PHY_1157_DATA 0x00000000
+#define DDRSS0_PHY_1158_DATA 0x00000000
+#define DDRSS0_PHY_1159_DATA 0x00000000
+#define DDRSS0_PHY_1160_DATA 0x00000000
+#define DDRSS0_PHY_1161_DATA 0x00000000
+#define DDRSS0_PHY_1162_DATA 0x00000000
+#define DDRSS0_PHY_1163_DATA 0x00000000
+#define DDRSS0_PHY_1164_DATA 0x00000000
+#define DDRSS0_PHY_1165_DATA 0x00000000
+#define DDRSS0_PHY_1166_DATA 0x00000000
+#define DDRSS0_PHY_1167_DATA 0x00000000
+#define DDRSS0_PHY_1168_DATA 0x00000000
+#define DDRSS0_PHY_1169_DATA 0x00000000
+#define DDRSS0_PHY_1170_DATA 0x00000000
+#define DDRSS0_PHY_1171_DATA 0x00000000
+#define DDRSS0_PHY_1172_DATA 0x00000000
+#define DDRSS0_PHY_1173_DATA 0x00000000
+#define DDRSS0_PHY_1174_DATA 0x00000000
+#define DDRSS0_PHY_1175_DATA 0x00000000
+#define DDRSS0_PHY_1176_DATA 0x00000000
+#define DDRSS0_PHY_1177_DATA 0x00000000
+#define DDRSS0_PHY_1178_DATA 0x00000000
+#define DDRSS0_PHY_1179_DATA 0x00000000
+#define DDRSS0_PHY_1180_DATA 0x00000000
+#define DDRSS0_PHY_1181_DATA 0x00000000
+#define DDRSS0_PHY_1182_DATA 0x00000000
+#define DDRSS0_PHY_1183_DATA 0x00000000
+#define DDRSS0_PHY_1184_DATA 0x00000000
+#define DDRSS0_PHY_1185_DATA 0x00000000
+#define DDRSS0_PHY_1186_DATA 0x00000000
+#define DDRSS0_PHY_1187_DATA 0x00000000
+#define DDRSS0_PHY_1188_DATA 0x00000000
+#define DDRSS0_PHY_1189_DATA 0x00000000
+#define DDRSS0_PHY_1190_DATA 0x00000000
+#define DDRSS0_PHY_1191_DATA 0x00000000
+#define DDRSS0_PHY_1192_DATA 0x00000000
+#define DDRSS0_PHY_1193_DATA 0x00000000
+#define DDRSS0_PHY_1194_DATA 0x00000000
+#define DDRSS0_PHY_1195_DATA 0x00000000
+#define DDRSS0_PHY_1196_DATA 0x00000000
+#define DDRSS0_PHY_1197_DATA 0x00000000
+#define DDRSS0_PHY_1198_DATA 0x00000000
+#define DDRSS0_PHY_1199_DATA 0x00000000
+#define DDRSS0_PHY_1200_DATA 0x00000000
+#define DDRSS0_PHY_1201_DATA 0x00000000
+#define DDRSS0_PHY_1202_DATA 0x00000000
+#define DDRSS0_PHY_1203_DATA 0x00000000
+#define DDRSS0_PHY_1204_DATA 0x00000000
+#define DDRSS0_PHY_1205_DATA 0x00000000
+#define DDRSS0_PHY_1206_DATA 0x00000000
+#define DDRSS0_PHY_1207_DATA 0x00000000
+#define DDRSS0_PHY_1208_DATA 0x00000000
+#define DDRSS0_PHY_1209_DATA 0x00000000
+#define DDRSS0_PHY_1210_DATA 0x00000000
+#define DDRSS0_PHY_1211_DATA 0x00000000
+#define DDRSS0_PHY_1212_DATA 0x00000000
+#define DDRSS0_PHY_1213_DATA 0x00000000
+#define DDRSS0_PHY_1214_DATA 0x00000000
+#define DDRSS0_PHY_1215_DATA 0x00000000
+#define DDRSS0_PHY_1216_DATA 0x00000000
+#define DDRSS0_PHY_1217_DATA 0x00000000
+#define DDRSS0_PHY_1218_DATA 0x00000000
+#define DDRSS0_PHY_1219_DATA 0x00000000
+#define DDRSS0_PHY_1220_DATA 0x00000000
+#define DDRSS0_PHY_1221_DATA 0x00000000
+#define DDRSS0_PHY_1222_DATA 0x00000000
+#define DDRSS0_PHY_1223_DATA 0x00000000
+#define DDRSS0_PHY_1224_DATA 0x00000000
+#define DDRSS0_PHY_1225_DATA 0x00000000
+#define DDRSS0_PHY_1226_DATA 0x00000000
+#define DDRSS0_PHY_1227_DATA 0x00000000
+#define DDRSS0_PHY_1228_DATA 0x00000000
+#define DDRSS0_PHY_1229_DATA 0x00000000
+#define DDRSS0_PHY_1230_DATA 0x00000000
+#define DDRSS0_PHY_1231_DATA 0x00000000
+#define DDRSS0_PHY_1232_DATA 0x00000000
+#define DDRSS0_PHY_1233_DATA 0x00000000
+#define DDRSS0_PHY_1234_DATA 0x00000000
+#define DDRSS0_PHY_1235_DATA 0x00000000
+#define DDRSS0_PHY_1236_DATA 0x00000000
+#define DDRSS0_PHY_1237_DATA 0x00000000
+#define DDRSS0_PHY_1238_DATA 0x00000000
+#define DDRSS0_PHY_1239_DATA 0x00000000
+#define DDRSS0_PHY_1240_DATA 0x00000000
+#define DDRSS0_PHY_1241_DATA 0x00000000
+#define DDRSS0_PHY_1242_DATA 0x00000000
+#define DDRSS0_PHY_1243_DATA 0x00000000
+#define DDRSS0_PHY_1244_DATA 0x00000000
+#define DDRSS0_PHY_1245_DATA 0x00000000
+#define DDRSS0_PHY_1246_DATA 0x00000000
+#define DDRSS0_PHY_1247_DATA 0x00000000
+#define DDRSS0_PHY_1248_DATA 0x00000000
+#define DDRSS0_PHY_1249_DATA 0x00000000
+#define DDRSS0_PHY_1250_DATA 0x00000000
+#define DDRSS0_PHY_1251_DATA 0x00000000
+#define DDRSS0_PHY_1252_DATA 0x00000000
+#define DDRSS0_PHY_1253_DATA 0x00000000
+#define DDRSS0_PHY_1254_DATA 0x00000000
+#define DDRSS0_PHY_1255_DATA 0x00000000
+#define DDRSS0_PHY_1256_DATA 0x00000000
+#define DDRSS0_PHY_1257_DATA 0x00000000
+#define DDRSS0_PHY_1258_DATA 0x00000000
+#define DDRSS0_PHY_1259_DATA 0x00000000
+#define DDRSS0_PHY_1260_DATA 0x00000000
+#define DDRSS0_PHY_1261_DATA 0x00000000
+#define DDRSS0_PHY_1262_DATA 0x00000000
+#define DDRSS0_PHY_1263_DATA 0x00000000
+#define DDRSS0_PHY_1264_DATA 0x00000000
+#define DDRSS0_PHY_1265_DATA 0x00000000
+#define DDRSS0_PHY_1266_DATA 0x00000000
+#define DDRSS0_PHY_1267_DATA 0x00000000
+#define DDRSS0_PHY_1268_DATA 0x00000000
+#define DDRSS0_PHY_1269_DATA 0x00000000
+#define DDRSS0_PHY_1270_DATA 0x00000000
+#define DDRSS0_PHY_1271_DATA 0x00000000
+#define DDRSS0_PHY_1272_DATA 0x00000000
+#define DDRSS0_PHY_1273_DATA 0x00000000
+#define DDRSS0_PHY_1274_DATA 0x00000000
+#define DDRSS0_PHY_1275_DATA 0x00000000
+#define DDRSS0_PHY_1276_DATA 0x00000000
+#define DDRSS0_PHY_1277_DATA 0x00000000
+#define DDRSS0_PHY_1278_DATA 0x00000000
+#define DDRSS0_PHY_1279_DATA 0x00000000
+#define DDRSS0_PHY_1280_DATA 0x00000000
+#define DDRSS0_PHY_1281_DATA 0x00010100
+#define DDRSS0_PHY_1282_DATA 0x00000000
+#define DDRSS0_PHY_1283_DATA 0x00000000
+#define DDRSS0_PHY_1284_DATA 0x00050000
+#define DDRSS0_PHY_1285_DATA 0x04000000
+#define DDRSS0_PHY_1286_DATA 0x00000055
+#define DDRSS0_PHY_1287_DATA 0x00000000
+#define DDRSS0_PHY_1288_DATA 0x00000000
+#define DDRSS0_PHY_1289_DATA 0x00000000
+#define DDRSS0_PHY_1290_DATA 0x00000000
+#define DDRSS0_PHY_1291_DATA 0x00002001
+#define DDRSS0_PHY_1292_DATA 0x0000400F
+#define DDRSS0_PHY_1293_DATA 0x50020028
+#define DDRSS0_PHY_1294_DATA 0x01010000
+#define DDRSS0_PHY_1295_DATA 0x80080001
+#define DDRSS0_PHY_1296_DATA 0x10200000
+#define DDRSS0_PHY_1297_DATA 0x00000008
+#define DDRSS0_PHY_1298_DATA 0x00000000
+#define DDRSS0_PHY_1299_DATA 0x01090E00
+#define DDRSS0_PHY_1300_DATA 0x00040101
+#define DDRSS0_PHY_1301_DATA 0x0000010F
+#define DDRSS0_PHY_1302_DATA 0x00000000
+#define DDRSS0_PHY_1303_DATA 0x0000FFFF
+#define DDRSS0_PHY_1304_DATA 0x00000000
+#define DDRSS0_PHY_1305_DATA 0x01010000
+#define DDRSS0_PHY_1306_DATA 0x01080402
+#define DDRSS0_PHY_1307_DATA 0x01200F02
+#define DDRSS0_PHY_1308_DATA 0x00194280
+#define DDRSS0_PHY_1309_DATA 0x00000004
+#define DDRSS0_PHY_1310_DATA 0x00042000
+#define DDRSS0_PHY_1311_DATA 0x00000000
+#define DDRSS0_PHY_1312_DATA 0x00000000
+#define DDRSS0_PHY_1313_DATA 0x00000000
+#define DDRSS0_PHY_1314_DATA 0x00000000
+#define DDRSS0_PHY_1315_DATA 0x00000000
+#define DDRSS0_PHY_1316_DATA 0x00000000
+#define DDRSS0_PHY_1317_DATA 0x01000000
+#define DDRSS0_PHY_1318_DATA 0x00000705
+#define DDRSS0_PHY_1319_DATA 0x00000054
+#define DDRSS0_PHY_1320_DATA 0x00030820
+#define DDRSS0_PHY_1321_DATA 0x00010820
+#define DDRSS0_PHY_1322_DATA 0x00010820
+#define DDRSS0_PHY_1323_DATA 0x00010820
+#define DDRSS0_PHY_1324_DATA 0x00010820
+#define DDRSS0_PHY_1325_DATA 0x00010820
+#define DDRSS0_PHY_1326_DATA 0x00010820
+#define DDRSS0_PHY_1327_DATA 0x00010820
+#define DDRSS0_PHY_1328_DATA 0x00010820
+#define DDRSS0_PHY_1329_DATA 0x00000000
+#define DDRSS0_PHY_1330_DATA 0x00000074
+#define DDRSS0_PHY_1331_DATA 0x00000400
+#define DDRSS0_PHY_1332_DATA 0x00000108
+#define DDRSS0_PHY_1333_DATA 0x00000000
+#define DDRSS0_PHY_1334_DATA 0x00000000
+#define DDRSS0_PHY_1335_DATA 0x00000000
+#define DDRSS0_PHY_1336_DATA 0x00000000
+#define DDRSS0_PHY_1337_DATA 0x00000000
+#define DDRSS0_PHY_1338_DATA 0x03000000
+#define DDRSS0_PHY_1339_DATA 0x00000000
+#define DDRSS0_PHY_1340_DATA 0x00000000
+#define DDRSS0_PHY_1341_DATA 0x00000000
+#define DDRSS0_PHY_1342_DATA 0x04102006
+#define DDRSS0_PHY_1343_DATA 0x00041020
+#define DDRSS0_PHY_1344_DATA 0x01C98C98
+#define DDRSS0_PHY_1345_DATA 0x3F400000
+#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS0_PHY_1347_DATA 0x0000001F
+#define DDRSS0_PHY_1348_DATA 0x00000000
+#define DDRSS0_PHY_1349_DATA 0x00000000
+#define DDRSS0_PHY_1350_DATA 0x00000000
+#define DDRSS0_PHY_1351_DATA 0x00010000
+#define DDRSS0_PHY_1352_DATA 0x00000000
+#define DDRSS0_PHY_1353_DATA 0x00000000
+#define DDRSS0_PHY_1354_DATA 0x00000000
+#define DDRSS0_PHY_1355_DATA 0x00000000
+#define DDRSS0_PHY_1356_DATA 0x76543210
+#define DDRSS0_PHY_1357_DATA 0x00010198
+#define DDRSS0_PHY_1358_DATA 0x00000000
+#define DDRSS0_PHY_1359_DATA 0x00000000
+#define DDRSS0_PHY_1360_DATA 0x00000000
+#define DDRSS0_PHY_1361_DATA 0x00040700
+#define DDRSS0_PHY_1362_DATA 0x00000000
+#define DDRSS0_PHY_1363_DATA 0x00000000
+#define DDRSS0_PHY_1364_DATA 0x00000000
+#define DDRSS0_PHY_1365_DATA 0x00000000
+#define DDRSS0_PHY_1366_DATA 0x00000000
+#define DDRSS0_PHY_1367_DATA 0x00000002
+#define DDRSS0_PHY_1368_DATA 0x00000000
+#define DDRSS0_PHY_1369_DATA 0x00000000
+#define DDRSS0_PHY_1370_DATA 0x00000000
+#define DDRSS0_PHY_1371_DATA 0x00000000
+#define DDRSS0_PHY_1372_DATA 0x00000000
+#define DDRSS0_PHY_1373_DATA 0x00000000
+#define DDRSS0_PHY_1374_DATA 0x00080000
+#define DDRSS0_PHY_1375_DATA 0x000007FF
+#define DDRSS0_PHY_1376_DATA 0x00000000
+#define DDRSS0_PHY_1377_DATA 0x00000000
+#define DDRSS0_PHY_1378_DATA 0x00000000
+#define DDRSS0_PHY_1379_DATA 0x00000000
+#define DDRSS0_PHY_1380_DATA 0x00000000
+#define DDRSS0_PHY_1381_DATA 0x00000000
+#define DDRSS0_PHY_1382_DATA 0x000FFFFF
+#define DDRSS0_PHY_1383_DATA 0x000FFFFF
+#define DDRSS0_PHY_1384_DATA 0x0000FFFF
+#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS0_PHY_1386_DATA 0x030FFFFF
+#define DDRSS0_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS0_PHY_1388_DATA 0x0000FFFF
+#define DDRSS0_PHY_1389_DATA 0x00000000
+#define DDRSS0_PHY_1390_DATA 0x00000000
+#define DDRSS0_PHY_1391_DATA 0x00000000
+#define DDRSS0_PHY_1392_DATA 0x00000000
+#define DDRSS0_PHY_1393_DATA 0x0001F7C0
+#define DDRSS0_PHY_1394_DATA 0x00000003
+#define DDRSS0_PHY_1395_DATA 0x00000000
+#define DDRSS0_PHY_1396_DATA 0x00001142
+#define DDRSS0_PHY_1397_DATA 0x010207AB
+#define DDRSS0_PHY_1398_DATA 0x01000080
+#define DDRSS0_PHY_1399_DATA 0x03900390
+#define DDRSS0_PHY_1400_DATA 0x03900390
+#define DDRSS0_PHY_1401_DATA 0x00000390
+#define DDRSS0_PHY_1402_DATA 0x00000390
+#define DDRSS0_PHY_1403_DATA 0x00000390
+#define DDRSS0_PHY_1404_DATA 0x00000390
+#define DDRSS0_PHY_1405_DATA 0x00000005
+#define DDRSS0_PHY_1406_DATA 0x01813FCC
+#define DDRSS0_PHY_1407_DATA 0x000000CC
+#define DDRSS0_PHY_1408_DATA 0x0C000DFF
+#define DDRSS0_PHY_1409_DATA 0x30000DFF
+#define DDRSS0_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1411_DATA 0x000100F0
+#define DDRSS0_PHY_1412_DATA 0x780DFFCC
+#define DDRSS0_PHY_1413_DATA 0x00007E31
+#define DDRSS0_PHY_1414_DATA 0x000CBF11
+#define DDRSS0_PHY_1415_DATA 0x01990010
+#define DDRSS0_PHY_1416_DATA 0x000CBF11
+#define DDRSS0_PHY_1417_DATA 0x01990010
+#define DDRSS0_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1419_DATA 0x00EF00F0
+#define DDRSS0_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1421_DATA 0x01FF00F0
+#define DDRSS0_PHY_1422_DATA 0x20040006
+
+#define DDRSS1_CTL_00_DATA 0x00000B00
+#define DDRSS1_CTL_01_DATA 0x00000000
+#define DDRSS1_CTL_02_DATA 0x00000000
+#define DDRSS1_CTL_03_DATA 0x00000000
+#define DDRSS1_CTL_04_DATA 0x00000000
+#define DDRSS1_CTL_05_DATA 0x00000000
+#define DDRSS1_CTL_06_DATA 0x00000000
+#define DDRSS1_CTL_07_DATA 0x00002AF8
+#define DDRSS1_CTL_08_DATA 0x0001ADAF
+#define DDRSS1_CTL_09_DATA 0x00000005
+#define DDRSS1_CTL_10_DATA 0x0000006E
+#define DDRSS1_CTL_11_DATA 0x000681C8
+#define DDRSS1_CTL_12_DATA 0x004111C9
+#define DDRSS1_CTL_13_DATA 0x00000005
+#define DDRSS1_CTL_14_DATA 0x000010A9
+#define DDRSS1_CTL_15_DATA 0x000681C8
+#define DDRSS1_CTL_16_DATA 0x004111C9
+#define DDRSS1_CTL_17_DATA 0x00000005
+#define DDRSS1_CTL_18_DATA 0x000010A9
+#define DDRSS1_CTL_19_DATA 0x01010000
+#define DDRSS1_CTL_20_DATA 0x02011001
+#define DDRSS1_CTL_21_DATA 0x02010000
+#define DDRSS1_CTL_22_DATA 0x00020100
+#define DDRSS1_CTL_23_DATA 0x0000000B
+#define DDRSS1_CTL_24_DATA 0x0000001C
+#define DDRSS1_CTL_25_DATA 0x00000000
+#define DDRSS1_CTL_26_DATA 0x00000000
+#define DDRSS1_CTL_27_DATA 0x03020200
+#define DDRSS1_CTL_28_DATA 0x00005656
+#define DDRSS1_CTL_29_DATA 0x00100000
+#define DDRSS1_CTL_30_DATA 0x00000000
+#define DDRSS1_CTL_31_DATA 0x00000000
+#define DDRSS1_CTL_32_DATA 0x00000000
+#define DDRSS1_CTL_33_DATA 0x00000000
+#define DDRSS1_CTL_34_DATA 0x040C0000
+#define DDRSS1_CTL_35_DATA 0x12481248
+#define DDRSS1_CTL_36_DATA 0x00050804
+#define DDRSS1_CTL_37_DATA 0x09040008
+#define DDRSS1_CTL_38_DATA 0x15000204
+#define DDRSS1_CTL_39_DATA 0x1760008B
+#define DDRSS1_CTL_40_DATA 0x1500422B
+#define DDRSS1_CTL_41_DATA 0x1760008B
+#define DDRSS1_CTL_42_DATA 0x2000422B
+#define DDRSS1_CTL_43_DATA 0x000A0A09
+#define DDRSS1_CTL_44_DATA 0x0400078A
+#define DDRSS1_CTL_45_DATA 0x1E161104
+#define DDRSS1_CTL_46_DATA 0x10012458
+#define DDRSS1_CTL_47_DATA 0x1E161110
+#define DDRSS1_CTL_48_DATA 0x10012458
+#define DDRSS1_CTL_49_DATA 0x02030410
+#define DDRSS1_CTL_50_DATA 0x2C040500
+#define DDRSS1_CTL_51_DATA 0x08292C29
+#define DDRSS1_CTL_52_DATA 0x14000E0A
+#define DDRSS1_CTL_53_DATA 0x04010A0A
+#define DDRSS1_CTL_54_DATA 0x01010004
+#define DDRSS1_CTL_55_DATA 0x04545408
+#define DDRSS1_CTL_56_DATA 0x04313104
+#define DDRSS1_CTL_57_DATA 0x00003131
+#define DDRSS1_CTL_58_DATA 0x00010100
+#define DDRSS1_CTL_59_DATA 0x03010000
+#define DDRSS1_CTL_60_DATA 0x00001508
+#define DDRSS1_CTL_61_DATA 0x000000CE
+#define DDRSS1_CTL_62_DATA 0x0000032B
+#define DDRSS1_CTL_63_DATA 0x00002073
+#define DDRSS1_CTL_64_DATA 0x0000032B
+#define DDRSS1_CTL_65_DATA 0x00002073
+#define DDRSS1_CTL_66_DATA 0x00000005
+#define DDRSS1_CTL_67_DATA 0x00050000
+#define DDRSS1_CTL_68_DATA 0x00CB0012
+#define DDRSS1_CTL_69_DATA 0x00CB0408
+#define DDRSS1_CTL_70_DATA 0x00400408
+#define DDRSS1_CTL_71_DATA 0x00120103
+#define DDRSS1_CTL_72_DATA 0x00100005
+#define DDRSS1_CTL_73_DATA 0x2F080010
+#define DDRSS1_CTL_74_DATA 0x0505012F
+#define DDRSS1_CTL_75_DATA 0x0401030A
+#define DDRSS1_CTL_76_DATA 0x041E100B
+#define DDRSS1_CTL_77_DATA 0x100B0401
+#define DDRSS1_CTL_78_DATA 0x0001041E
+#define DDRSS1_CTL_79_DATA 0x00160016
+#define DDRSS1_CTL_80_DATA 0x033B033B
+#define DDRSS1_CTL_81_DATA 0x033B033B
+#define DDRSS1_CTL_82_DATA 0x03050505
+#define DDRSS1_CTL_83_DATA 0x03010303
+#define DDRSS1_CTL_84_DATA 0x200B100B
+#define DDRSS1_CTL_85_DATA 0x04041004
+#define DDRSS1_CTL_86_DATA 0x200B100B
+#define DDRSS1_CTL_87_DATA 0x04041004
+#define DDRSS1_CTL_88_DATA 0x03010000
+#define DDRSS1_CTL_89_DATA 0x00010000
+#define DDRSS1_CTL_90_DATA 0x00000000
+#define DDRSS1_CTL_91_DATA 0x00000000
+#define DDRSS1_CTL_92_DATA 0x01000000
+#define DDRSS1_CTL_93_DATA 0x80104002
+#define DDRSS1_CTL_94_DATA 0x00000000
+#define DDRSS1_CTL_95_DATA 0x00040005
+#define DDRSS1_CTL_96_DATA 0x00000000
+#define DDRSS1_CTL_97_DATA 0x00050000
+#define DDRSS1_CTL_98_DATA 0x00000004
+#define DDRSS1_CTL_99_DATA 0x00000000
+#define DDRSS1_CTL_100_DATA 0x00040005
+#define DDRSS1_CTL_101_DATA 0x00000000
+#define DDRSS1_CTL_102_DATA 0x00003380
+#define DDRSS1_CTL_103_DATA 0x00003380
+#define DDRSS1_CTL_104_DATA 0x00003380
+#define DDRSS1_CTL_105_DATA 0x00003380
+#define DDRSS1_CTL_106_DATA 0x00003380
+#define DDRSS1_CTL_107_DATA 0x00000000
+#define DDRSS1_CTL_108_DATA 0x000005A2
+#define DDRSS1_CTL_109_DATA 0x00081CC0
+#define DDRSS1_CTL_110_DATA 0x00081CC0
+#define DDRSS1_CTL_111_DATA 0x00081CC0
+#define DDRSS1_CTL_112_DATA 0x00081CC0
+#define DDRSS1_CTL_113_DATA 0x00081CC0
+#define DDRSS1_CTL_114_DATA 0x00000000
+#define DDRSS1_CTL_115_DATA 0x0000E325
+#define DDRSS1_CTL_116_DATA 0x00081CC0
+#define DDRSS1_CTL_117_DATA 0x00081CC0
+#define DDRSS1_CTL_118_DATA 0x00081CC0
+#define DDRSS1_CTL_119_DATA 0x00081CC0
+#define DDRSS1_CTL_120_DATA 0x00081CC0
+#define DDRSS1_CTL_121_DATA 0x00000000
+#define DDRSS1_CTL_122_DATA 0x0000E325
+#define DDRSS1_CTL_123_DATA 0x00000000
+#define DDRSS1_CTL_124_DATA 0x00000000
+#define DDRSS1_CTL_125_DATA 0x00000000
+#define DDRSS1_CTL_126_DATA 0x00000000
+#define DDRSS1_CTL_127_DATA 0x00000000
+#define DDRSS1_CTL_128_DATA 0x00000000
+#define DDRSS1_CTL_129_DATA 0x00000000
+#define DDRSS1_CTL_130_DATA 0x00000000
+#define DDRSS1_CTL_131_DATA 0x0B030500
+#define DDRSS1_CTL_132_DATA 0x00040B04
+#define DDRSS1_CTL_133_DATA 0x0A090000
+#define DDRSS1_CTL_134_DATA 0x0A090701
+#define DDRSS1_CTL_135_DATA 0x0900000E
+#define DDRSS1_CTL_136_DATA 0x0907010A
+#define DDRSS1_CTL_137_DATA 0x00000E0A
+#define DDRSS1_CTL_138_DATA 0x07010A09
+#define DDRSS1_CTL_139_DATA 0x000E0A09
+#define DDRSS1_CTL_140_DATA 0x07000401
+#define DDRSS1_CTL_141_DATA 0x00000000
+#define DDRSS1_CTL_142_DATA 0x00000000
+#define DDRSS1_CTL_143_DATA 0x00000000
+#define DDRSS1_CTL_144_DATA 0x00000000
+#define DDRSS1_CTL_145_DATA 0x00000000
+#define DDRSS1_CTL_146_DATA 0x00000000
+#define DDRSS1_CTL_147_DATA 0x00000000
+#define DDRSS1_CTL_148_DATA 0x08080000
+#define DDRSS1_CTL_149_DATA 0x01000000
+#define DDRSS1_CTL_150_DATA 0x800000C0
+#define DDRSS1_CTL_151_DATA 0x800000C0
+#define DDRSS1_CTL_152_DATA 0x800000C0
+#define DDRSS1_CTL_153_DATA 0x00000000
+#define DDRSS1_CTL_154_DATA 0x00001500
+#define DDRSS1_CTL_155_DATA 0x00000000
+#define DDRSS1_CTL_156_DATA 0x00000001
+#define DDRSS1_CTL_157_DATA 0x00000002
+#define DDRSS1_CTL_158_DATA 0x0000100E
+#define DDRSS1_CTL_159_DATA 0x00000000
+#define DDRSS1_CTL_160_DATA 0x00000000
+#define DDRSS1_CTL_161_DATA 0x00000000
+#define DDRSS1_CTL_162_DATA 0x00000000
+#define DDRSS1_CTL_163_DATA 0x00000000
+#define DDRSS1_CTL_164_DATA 0x000B0000
+#define DDRSS1_CTL_165_DATA 0x000E0006
+#define DDRSS1_CTL_166_DATA 0x000E0404
+#define DDRSS1_CTL_167_DATA 0x00D601AB
+#define DDRSS1_CTL_168_DATA 0x10100216
+#define DDRSS1_CTL_169_DATA 0x01AB0216
+#define DDRSS1_CTL_170_DATA 0x021600D6
+#define DDRSS1_CTL_171_DATA 0x02161010
+#define DDRSS1_CTL_172_DATA 0x00000000
+#define DDRSS1_CTL_173_DATA 0x00000000
+#define DDRSS1_CTL_174_DATA 0x00000000
+#define DDRSS1_CTL_175_DATA 0x3FF40084
+#define DDRSS1_CTL_176_DATA 0x33003FF4
+#define DDRSS1_CTL_177_DATA 0x00003333
+#define DDRSS1_CTL_178_DATA 0x35000000
+#define DDRSS1_CTL_179_DATA 0x27270035
+#define DDRSS1_CTL_180_DATA 0x0F0F0000
+#define DDRSS1_CTL_181_DATA 0x16000000
+#define DDRSS1_CTL_182_DATA 0x00841616
+#define DDRSS1_CTL_183_DATA 0x3FF43FF4
+#define DDRSS1_CTL_184_DATA 0x33333300
+#define DDRSS1_CTL_185_DATA 0x00000000
+#define DDRSS1_CTL_186_DATA 0x00353500
+#define DDRSS1_CTL_187_DATA 0x00002727
+#define DDRSS1_CTL_188_DATA 0x00000F0F
+#define DDRSS1_CTL_189_DATA 0x16161600
+#define DDRSS1_CTL_190_DATA 0x00000020
+#define DDRSS1_CTL_191_DATA 0x00000000
+#define DDRSS1_CTL_192_DATA 0x00000001
+#define DDRSS1_CTL_193_DATA 0x00000000
+#define DDRSS1_CTL_194_DATA 0x01000000
+#define DDRSS1_CTL_195_DATA 0x00000001
+#define DDRSS1_CTL_196_DATA 0x00000000
+#define DDRSS1_CTL_197_DATA 0x00000000
+#define DDRSS1_CTL_198_DATA 0x00000000
+#define DDRSS1_CTL_199_DATA 0x00000000
+#define DDRSS1_CTL_200_DATA 0x00000000
+#define DDRSS1_CTL_201_DATA 0x00000000
+#define DDRSS1_CTL_202_DATA 0x00000000
+#define DDRSS1_CTL_203_DATA 0x00000000
+#define DDRSS1_CTL_204_DATA 0x00000000
+#define DDRSS1_CTL_205_DATA 0x00000000
+#define DDRSS1_CTL_206_DATA 0x02000000
+#define DDRSS1_CTL_207_DATA 0x01080101
+#define DDRSS1_CTL_208_DATA 0x00000000
+#define DDRSS1_CTL_209_DATA 0x00000000
+#define DDRSS1_CTL_210_DATA 0x00000000
+#define DDRSS1_CTL_211_DATA 0x00000000
+#define DDRSS1_CTL_212_DATA 0x00000000
+#define DDRSS1_CTL_213_DATA 0x00000000
+#define DDRSS1_CTL_214_DATA 0x00000000
+#define DDRSS1_CTL_215_DATA 0x00000000
+#define DDRSS1_CTL_216_DATA 0x00000000
+#define DDRSS1_CTL_217_DATA 0x00000000
+#define DDRSS1_CTL_218_DATA 0x00000000
+#define DDRSS1_CTL_219_DATA 0x00000000
+#define DDRSS1_CTL_220_DATA 0x00000000
+#define DDRSS1_CTL_221_DATA 0x00000000
+#define DDRSS1_CTL_222_DATA 0x00001000
+#define DDRSS1_CTL_223_DATA 0x006403E8
+#define DDRSS1_CTL_224_DATA 0x00000000
+#define DDRSS1_CTL_225_DATA 0x00000000
+#define DDRSS1_CTL_226_DATA 0x00000000
+#define DDRSS1_CTL_227_DATA 0x15110000
+#define DDRSS1_CTL_228_DATA 0x00040C18
+#define DDRSS1_CTL_229_DATA 0xF000C000
+#define DDRSS1_CTL_230_DATA 0x0000F000
+#define DDRSS1_CTL_231_DATA 0x00000000
+#define DDRSS1_CTL_232_DATA 0x00000000
+#define DDRSS1_CTL_233_DATA 0xC0000000
+#define DDRSS1_CTL_234_DATA 0xF000F000
+#define DDRSS1_CTL_235_DATA 0x00000000
+#define DDRSS1_CTL_236_DATA 0x00000000
+#define DDRSS1_CTL_237_DATA 0x00000000
+#define DDRSS1_CTL_238_DATA 0xF000C000
+#define DDRSS1_CTL_239_DATA 0x0000F000
+#define DDRSS1_CTL_240_DATA 0x00000000
+#define DDRSS1_CTL_241_DATA 0x00000000
+#define DDRSS1_CTL_242_DATA 0x00030000
+#define DDRSS1_CTL_243_DATA 0x00000000
+#define DDRSS1_CTL_244_DATA 0x00000000
+#define DDRSS1_CTL_245_DATA 0x00000000
+#define DDRSS1_CTL_246_DATA 0x00000000
+#define DDRSS1_CTL_247_DATA 0x00000000
+#define DDRSS1_CTL_248_DATA 0x00000000
+#define DDRSS1_CTL_249_DATA 0x00000000
+#define DDRSS1_CTL_250_DATA 0x00000000
+#define DDRSS1_CTL_251_DATA 0x00000000
+#define DDRSS1_CTL_252_DATA 0x00000000
+#define DDRSS1_CTL_253_DATA 0x00000000
+#define DDRSS1_CTL_254_DATA 0x00000000
+#define DDRSS1_CTL_255_DATA 0x00000000
+#define DDRSS1_CTL_256_DATA 0x00000000
+#define DDRSS1_CTL_257_DATA 0x01000200
+#define DDRSS1_CTL_258_DATA 0x00370040
+#define DDRSS1_CTL_259_DATA 0x00020008
+#define DDRSS1_CTL_260_DATA 0x00400100
+#define DDRSS1_CTL_261_DATA 0x00400855
+#define DDRSS1_CTL_262_DATA 0x01000200
+#define DDRSS1_CTL_263_DATA 0x08550040
+#define DDRSS1_CTL_264_DATA 0x00000040
+#define DDRSS1_CTL_265_DATA 0x006B0003
+#define DDRSS1_CTL_266_DATA 0x0100006B
+#define DDRSS1_CTL_267_DATA 0x03030303
+#define DDRSS1_CTL_268_DATA 0x00000000
+#define DDRSS1_CTL_269_DATA 0x00000202
+#define DDRSS1_CTL_270_DATA 0x00001FFF
+#define DDRSS1_CTL_271_DATA 0x3FFF2000
+#define DDRSS1_CTL_272_DATA 0x03FF0000
+#define DDRSS1_CTL_273_DATA 0x000103FF
+#define DDRSS1_CTL_274_DATA 0x0FFF0B00
+#define DDRSS1_CTL_275_DATA 0x01010001
+#define DDRSS1_CTL_276_DATA 0x01010101
+#define DDRSS1_CTL_277_DATA 0x01180101
+#define DDRSS1_CTL_278_DATA 0x00030000
+#define DDRSS1_CTL_279_DATA 0x00000000
+#define DDRSS1_CTL_280_DATA 0x00000000
+#define DDRSS1_CTL_281_DATA 0x00000000
+#define DDRSS1_CTL_282_DATA 0x00000000
+#define DDRSS1_CTL_283_DATA 0x00000000
+#define DDRSS1_CTL_284_DATA 0x00000000
+#define DDRSS1_CTL_285_DATA 0x00000000
+#define DDRSS1_CTL_286_DATA 0x00040101
+#define DDRSS1_CTL_287_DATA 0x04010100
+#define DDRSS1_CTL_288_DATA 0x00000000
+#define DDRSS1_CTL_289_DATA 0x00000000
+#define DDRSS1_CTL_290_DATA 0x03030300
+#define DDRSS1_CTL_291_DATA 0x00000001
+#define DDRSS1_CTL_292_DATA 0x00000000
+#define DDRSS1_CTL_293_DATA 0x00000000
+#define DDRSS1_CTL_294_DATA 0x00000000
+#define DDRSS1_CTL_295_DATA 0x00000000
+#define DDRSS1_CTL_296_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0x00000000
+#define DDRSS1_CTL_298_DATA 0x00000000
+#define DDRSS1_CTL_299_DATA 0x00000000
+#define DDRSS1_CTL_300_DATA 0x00000000
+#define DDRSS1_CTL_301_DATA 0x00000000
+#define DDRSS1_CTL_302_DATA 0x00000000
+#define DDRSS1_CTL_303_DATA 0x00000000
+#define DDRSS1_CTL_304_DATA 0x00000000
+#define DDRSS1_CTL_305_DATA 0x00000000
+#define DDRSS1_CTL_306_DATA 0x00000000
+#define DDRSS1_CTL_307_DATA 0x00000000
+#define DDRSS1_CTL_308_DATA 0x00000000
+#define DDRSS1_CTL_309_DATA 0x00000000
+#define DDRSS1_CTL_310_DATA 0x00000000
+#define DDRSS1_CTL_311_DATA 0x00000000
+#define DDRSS1_CTL_312_DATA 0x00000000
+#define DDRSS1_CTL_313_DATA 0x01000000
+#define DDRSS1_CTL_314_DATA 0x00020201
+#define DDRSS1_CTL_315_DATA 0x01000101
+#define DDRSS1_CTL_316_DATA 0x01010001
+#define DDRSS1_CTL_317_DATA 0x00010101
+#define DDRSS1_CTL_318_DATA 0x050A0A03
+#define DDRSS1_CTL_319_DATA 0x10081F1F
+#define DDRSS1_CTL_320_DATA 0x00090310
+#define DDRSS1_CTL_321_DATA 0x0B0C030F
+#define DDRSS1_CTL_322_DATA 0x0B0C0306
+#define DDRSS1_CTL_323_DATA 0x0C090006
+#define DDRSS1_CTL_324_DATA 0x0100000C
+#define DDRSS1_CTL_325_DATA 0x08040801
+#define DDRSS1_CTL_326_DATA 0x00000004
+#define DDRSS1_CTL_327_DATA 0x00000000
+#define DDRSS1_CTL_328_DATA 0x00010000
+#define DDRSS1_CTL_329_DATA 0x00280D00
+#define DDRSS1_CTL_330_DATA 0x00000001
+#define DDRSS1_CTL_331_DATA 0x00030001
+#define DDRSS1_CTL_332_DATA 0x00000000
+#define DDRSS1_CTL_333_DATA 0x00000000
+#define DDRSS1_CTL_334_DATA 0x00000000
+#define DDRSS1_CTL_335_DATA 0x00000000
+#define DDRSS1_CTL_336_DATA 0x00000000
+#define DDRSS1_CTL_337_DATA 0x00000000
+#define DDRSS1_CTL_338_DATA 0x00000000
+#define DDRSS1_CTL_339_DATA 0x00000000
+#define DDRSS1_CTL_340_DATA 0x01000000
+#define DDRSS1_CTL_341_DATA 0x00000001
+#define DDRSS1_CTL_342_DATA 0x00010100
+#define DDRSS1_CTL_343_DATA 0x03030000
+#define DDRSS1_CTL_344_DATA 0x00000000
+#define DDRSS1_CTL_345_DATA 0x00000000
+#define DDRSS1_CTL_346_DATA 0x00000000
+#define DDRSS1_CTL_347_DATA 0x00000000
+#define DDRSS1_CTL_348_DATA 0x00000000
+#define DDRSS1_CTL_349_DATA 0x00000000
+#define DDRSS1_CTL_350_DATA 0x00000000
+#define DDRSS1_CTL_351_DATA 0x00000000
+#define DDRSS1_CTL_352_DATA 0x00000000
+#define DDRSS1_CTL_353_DATA 0x00000000
+#define DDRSS1_CTL_354_DATA 0x00000000
+#define DDRSS1_CTL_355_DATA 0x00000000
+#define DDRSS1_CTL_356_DATA 0x00000000
+#define DDRSS1_CTL_357_DATA 0x00000000
+#define DDRSS1_CTL_358_DATA 0x00000000
+#define DDRSS1_CTL_359_DATA 0x00000000
+#define DDRSS1_CTL_360_DATA 0x000556AA
+#define DDRSS1_CTL_361_DATA 0x000AAAAA
+#define DDRSS1_CTL_362_DATA 0x000AA955
+#define DDRSS1_CTL_363_DATA 0x00055555
+#define DDRSS1_CTL_364_DATA 0x000B3133
+#define DDRSS1_CTL_365_DATA 0x0004CD33
+#define DDRSS1_CTL_366_DATA 0x0004CECC
+#define DDRSS1_CTL_367_DATA 0x000B32CC
+#define DDRSS1_CTL_368_DATA 0x00010300
+#define DDRSS1_CTL_369_DATA 0x03000100
+#define DDRSS1_CTL_370_DATA 0x00000000
+#define DDRSS1_CTL_371_DATA 0x00000000
+#define DDRSS1_CTL_372_DATA 0x00000000
+#define DDRSS1_CTL_373_DATA 0x00000000
+#define DDRSS1_CTL_374_DATA 0x00000000
+#define DDRSS1_CTL_375_DATA 0x00000000
+#define DDRSS1_CTL_376_DATA 0x00000000
+#define DDRSS1_CTL_377_DATA 0x00010000
+#define DDRSS1_CTL_378_DATA 0x00000404
+#define DDRSS1_CTL_379_DATA 0x00000000
+#define DDRSS1_CTL_380_DATA 0x00000000
+#define DDRSS1_CTL_381_DATA 0x00000000
+#define DDRSS1_CTL_382_DATA 0x00000000
+#define DDRSS1_CTL_383_DATA 0x00000000
+#define DDRSS1_CTL_384_DATA 0x00000000
+#define DDRSS1_CTL_385_DATA 0x00000000
+#define DDRSS1_CTL_386_DATA 0x00000000
+#define DDRSS1_CTL_387_DATA 0x3A3A1B00
+#define DDRSS1_CTL_388_DATA 0x000A0000
+#define DDRSS1_CTL_389_DATA 0x0000019C
+#define DDRSS1_CTL_390_DATA 0x00000200
+#define DDRSS1_CTL_391_DATA 0x00000200
+#define DDRSS1_CTL_392_DATA 0x00000200
+#define DDRSS1_CTL_393_DATA 0x00000200
+#define DDRSS1_CTL_394_DATA 0x000004D4
+#define DDRSS1_CTL_395_DATA 0x00001018
+#define DDRSS1_CTL_396_DATA 0x00000204
+#define DDRSS1_CTL_397_DATA 0x000040E6
+#define DDRSS1_CTL_398_DATA 0x00000200
+#define DDRSS1_CTL_399_DATA 0x00000200
+#define DDRSS1_CTL_400_DATA 0x00000200
+#define DDRSS1_CTL_401_DATA 0x00000200
+#define DDRSS1_CTL_402_DATA 0x0000C2B2
+#define DDRSS1_CTL_403_DATA 0x000288FC
+#define DDRSS1_CTL_404_DATA 0x00000E15
+#define DDRSS1_CTL_405_DATA 0x000040E6
+#define DDRSS1_CTL_406_DATA 0x00000200
+#define DDRSS1_CTL_407_DATA 0x00000200
+#define DDRSS1_CTL_408_DATA 0x00000200
+#define DDRSS1_CTL_409_DATA 0x00000200
+#define DDRSS1_CTL_410_DATA 0x0000C2B2
+#define DDRSS1_CTL_411_DATA 0x000288FC
+#define DDRSS1_CTL_412_DATA 0x02020E15
+#define DDRSS1_CTL_413_DATA 0x03030202
+#define DDRSS1_CTL_414_DATA 0x00000022
+#define DDRSS1_CTL_415_DATA 0x00000000
+#define DDRSS1_CTL_416_DATA 0x00000000
+#define DDRSS1_CTL_417_DATA 0x00001403
+#define DDRSS1_CTL_418_DATA 0x000007D0
+#define DDRSS1_CTL_419_DATA 0x00000000
+#define DDRSS1_CTL_420_DATA 0x00000000
+#define DDRSS1_CTL_421_DATA 0x00030000
+#define DDRSS1_CTL_422_DATA 0x0007001F
+#define DDRSS1_CTL_423_DATA 0x001B0033
+#define DDRSS1_CTL_424_DATA 0x001B0033
+#define DDRSS1_CTL_425_DATA 0x00000000
+#define DDRSS1_CTL_426_DATA 0x00000000
+#define DDRSS1_CTL_427_DATA 0x02000000
+#define DDRSS1_CTL_428_DATA 0x01000404
+#define DDRSS1_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS1_CTL_430_DATA 0x00000105
+#define DDRSS1_CTL_431_DATA 0x00010101
+#define DDRSS1_CTL_432_DATA 0x00010101
+#define DDRSS1_CTL_433_DATA 0x00010001
+#define DDRSS1_CTL_434_DATA 0x00000101
+#define DDRSS1_CTL_435_DATA 0x02000201
+#define DDRSS1_CTL_436_DATA 0x02010000
+#define DDRSS1_CTL_437_DATA 0x00000200
+#define DDRSS1_CTL_438_DATA 0x28060000
+#define DDRSS1_CTL_439_DATA 0x00000128
+#define DDRSS1_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_442_DATA 0x00000000
+#define DDRSS1_CTL_443_DATA 0x00000000
+#define DDRSS1_CTL_444_DATA 0x00000000
+#define DDRSS1_CTL_445_DATA 0x00000000
+#define DDRSS1_CTL_446_DATA 0x00000000
+#define DDRSS1_CTL_447_DATA 0x00000000
+#define DDRSS1_CTL_448_DATA 0x00000000
+#define DDRSS1_CTL_449_DATA 0x00000000
+#define DDRSS1_CTL_450_DATA 0x00000000
+#define DDRSS1_CTL_451_DATA 0x00000000
+#define DDRSS1_CTL_452_DATA 0x00000000
+#define DDRSS1_CTL_453_DATA 0x00000000
+#define DDRSS1_CTL_454_DATA 0x00000000
+#define DDRSS1_CTL_455_DATA 0x00000000
+#define DDRSS1_CTL_456_DATA 0x00000000
+#define DDRSS1_CTL_457_DATA 0x00000000
+#define DDRSS1_CTL_458_DATA 0x00000000
+
+#define DDRSS1_PI_00_DATA 0x00000B00
+#define DDRSS1_PI_01_DATA 0x00000000
+#define DDRSS1_PI_02_DATA 0x00000000
+#define DDRSS1_PI_03_DATA 0x00000000
+#define DDRSS1_PI_04_DATA 0x00000000
+#define DDRSS1_PI_05_DATA 0x00000101
+#define DDRSS1_PI_06_DATA 0x00640000
+#define DDRSS1_PI_07_DATA 0x00000001
+#define DDRSS1_PI_08_DATA 0x00000000
+#define DDRSS1_PI_09_DATA 0x00000000
+#define DDRSS1_PI_10_DATA 0x00000000
+#define DDRSS1_PI_11_DATA 0x00000000
+#define DDRSS1_PI_12_DATA 0x00000007
+#define DDRSS1_PI_13_DATA 0x00010002
+#define DDRSS1_PI_14_DATA 0x0800000F
+#define DDRSS1_PI_15_DATA 0x00000103
+#define DDRSS1_PI_16_DATA 0x00000005
+#define DDRSS1_PI_17_DATA 0x00000000
+#define DDRSS1_PI_18_DATA 0x00000000
+#define DDRSS1_PI_19_DATA 0x00000000
+#define DDRSS1_PI_20_DATA 0x00000000
+#define DDRSS1_PI_21_DATA 0x00000000
+#define DDRSS1_PI_22_DATA 0x00000000
+#define DDRSS1_PI_23_DATA 0x00000000
+#define DDRSS1_PI_24_DATA 0x00000000
+#define DDRSS1_PI_25_DATA 0x00000000
+#define DDRSS1_PI_26_DATA 0x00010100
+#define DDRSS1_PI_27_DATA 0x00280A00
+#define DDRSS1_PI_28_DATA 0x00000000
+#define DDRSS1_PI_29_DATA 0x0F000000
+#define DDRSS1_PI_30_DATA 0x00003200
+#define DDRSS1_PI_31_DATA 0x00000000
+#define DDRSS1_PI_32_DATA 0x00000000
+#define DDRSS1_PI_33_DATA 0x01010102
+#define DDRSS1_PI_34_DATA 0x00000000
+#define DDRSS1_PI_35_DATA 0x000000AA
+#define DDRSS1_PI_36_DATA 0x00000055
+#define DDRSS1_PI_37_DATA 0x000000B5
+#define DDRSS1_PI_38_DATA 0x0000004A
+#define DDRSS1_PI_39_DATA 0x00000056
+#define DDRSS1_PI_40_DATA 0x000000A9
+#define DDRSS1_PI_41_DATA 0x000000A9
+#define DDRSS1_PI_42_DATA 0x000000B5
+#define DDRSS1_PI_43_DATA 0x00000000
+#define DDRSS1_PI_44_DATA 0x00000000
+#define DDRSS1_PI_45_DATA 0x000F0F00
+#define DDRSS1_PI_46_DATA 0x0000001B
+#define DDRSS1_PI_47_DATA 0x000007D0
+#define DDRSS1_PI_48_DATA 0x00000300
+#define DDRSS1_PI_49_DATA 0x00000000
+#define DDRSS1_PI_50_DATA 0x00000000
+#define DDRSS1_PI_51_DATA 0x01000000
+#define DDRSS1_PI_52_DATA 0x00010101
+#define DDRSS1_PI_53_DATA 0x00000000
+#define DDRSS1_PI_54_DATA 0x00030000
+#define DDRSS1_PI_55_DATA 0x0F000000
+#define DDRSS1_PI_56_DATA 0x00000017
+#define DDRSS1_PI_57_DATA 0x00000000
+#define DDRSS1_PI_58_DATA 0x00000000
+#define DDRSS1_PI_59_DATA 0x00000000
+#define DDRSS1_PI_60_DATA 0x0A0A140A
+#define DDRSS1_PI_61_DATA 0x10020101
+#define DDRSS1_PI_62_DATA 0x00020805
+#define DDRSS1_PI_63_DATA 0x01000404
+#define DDRSS1_PI_64_DATA 0x00000000
+#define DDRSS1_PI_65_DATA 0x00000000
+#define DDRSS1_PI_66_DATA 0x00000100
+#define DDRSS1_PI_67_DATA 0x0001010F
+#define DDRSS1_PI_68_DATA 0x00340000
+#define DDRSS1_PI_69_DATA 0x00000000
+#define DDRSS1_PI_70_DATA 0x00000000
+#define DDRSS1_PI_71_DATA 0x0000FFFF
+#define DDRSS1_PI_72_DATA 0x00000000
+#define DDRSS1_PI_73_DATA 0x00080000
+#define DDRSS1_PI_74_DATA 0x02000200
+#define DDRSS1_PI_75_DATA 0x01000100
+#define DDRSS1_PI_76_DATA 0x01000000
+#define DDRSS1_PI_77_DATA 0x02000200
+#define DDRSS1_PI_78_DATA 0x00000200
+#define DDRSS1_PI_79_DATA 0x00000000
+#define DDRSS1_PI_80_DATA 0x00000000
+#define DDRSS1_PI_81_DATA 0x00000000
+#define DDRSS1_PI_82_DATA 0x00000000
+#define DDRSS1_PI_83_DATA 0x00000000
+#define DDRSS1_PI_84_DATA 0x00000000
+#define DDRSS1_PI_85_DATA 0x00000000
+#define DDRSS1_PI_86_DATA 0x00000000
+#define DDRSS1_PI_87_DATA 0x00000000
+#define DDRSS1_PI_88_DATA 0x00000000
+#define DDRSS1_PI_89_DATA 0x00000000
+#define DDRSS1_PI_90_DATA 0x00000000
+#define DDRSS1_PI_91_DATA 0x00000400
+#define DDRSS1_PI_92_DATA 0x02010000
+#define DDRSS1_PI_93_DATA 0x00080003
+#define DDRSS1_PI_94_DATA 0x00080000
+#define DDRSS1_PI_95_DATA 0x00000001
+#define DDRSS1_PI_96_DATA 0x00000000
+#define DDRSS1_PI_97_DATA 0x0000AA00
+#define DDRSS1_PI_98_DATA 0x00000000
+#define DDRSS1_PI_99_DATA 0x00000000
+#define DDRSS1_PI_100_DATA 0x00010000
+#define DDRSS1_PI_101_DATA 0x00000000
+#define DDRSS1_PI_102_DATA 0x00000000
+#define DDRSS1_PI_103_DATA 0x00000000
+#define DDRSS1_PI_104_DATA 0x00000000
+#define DDRSS1_PI_105_DATA 0x00000000
+#define DDRSS1_PI_106_DATA 0x00000000
+#define DDRSS1_PI_107_DATA 0x00000000
+#define DDRSS1_PI_108_DATA 0x00000000
+#define DDRSS1_PI_109_DATA 0x00000000
+#define DDRSS1_PI_110_DATA 0x00000000
+#define DDRSS1_PI_111_DATA 0x00000000
+#define DDRSS1_PI_112_DATA 0x00000000
+#define DDRSS1_PI_113_DATA 0x00000000
+#define DDRSS1_PI_114_DATA 0x00000000
+#define DDRSS1_PI_115_DATA 0x00000000
+#define DDRSS1_PI_116_DATA 0x00000000
+#define DDRSS1_PI_117_DATA 0x00000000
+#define DDRSS1_PI_118_DATA 0x00000000
+#define DDRSS1_PI_119_DATA 0x00000000
+#define DDRSS1_PI_120_DATA 0x00000000
+#define DDRSS1_PI_121_DATA 0x00000000
+#define DDRSS1_PI_122_DATA 0x00000000
+#define DDRSS1_PI_123_DATA 0x00000000
+#define DDRSS1_PI_124_DATA 0x00000000
+#define DDRSS1_PI_125_DATA 0x00000008
+#define DDRSS1_PI_126_DATA 0x00000000
+#define DDRSS1_PI_127_DATA 0x00000000
+#define DDRSS1_PI_128_DATA 0x00000000
+#define DDRSS1_PI_129_DATA 0x00000000
+#define DDRSS1_PI_130_DATA 0x00000000
+#define DDRSS1_PI_131_DATA 0x00000000
+#define DDRSS1_PI_132_DATA 0x00000000
+#define DDRSS1_PI_133_DATA 0x00000000
+#define DDRSS1_PI_134_DATA 0x00000002
+#define DDRSS1_PI_135_DATA 0x00000000
+#define DDRSS1_PI_136_DATA 0x00000000
+#define DDRSS1_PI_137_DATA 0x0000000A
+#define DDRSS1_PI_138_DATA 0x00000019
+#define DDRSS1_PI_139_DATA 0x00000100
+#define DDRSS1_PI_140_DATA 0x00000000
+#define DDRSS1_PI_141_DATA 0x00000000
+#define DDRSS1_PI_142_DATA 0x00000000
+#define DDRSS1_PI_143_DATA 0x00000000
+#define DDRSS1_PI_144_DATA 0x01000000
+#define DDRSS1_PI_145_DATA 0x00010003
+#define DDRSS1_PI_146_DATA 0x02000101
+#define DDRSS1_PI_147_DATA 0x01030001
+#define DDRSS1_PI_148_DATA 0x00010400
+#define DDRSS1_PI_149_DATA 0x06000105
+#define DDRSS1_PI_150_DATA 0x01070001
+#define DDRSS1_PI_151_DATA 0x00000000
+#define DDRSS1_PI_152_DATA 0x00000000
+#define DDRSS1_PI_153_DATA 0x00000000
+#define DDRSS1_PI_154_DATA 0x00010001
+#define DDRSS1_PI_155_DATA 0x00000000
+#define DDRSS1_PI_156_DATA 0x00000000
+#define DDRSS1_PI_157_DATA 0x00000000
+#define DDRSS1_PI_158_DATA 0x00000000
+#define DDRSS1_PI_159_DATA 0x00000401
+#define DDRSS1_PI_160_DATA 0x00000000
+#define DDRSS1_PI_161_DATA 0x00010000
+#define DDRSS1_PI_162_DATA 0x00000000
+#define DDRSS1_PI_163_DATA 0x2B2B0200
+#define DDRSS1_PI_164_DATA 0x00000034
+#define DDRSS1_PI_165_DATA 0x00000064
+#define DDRSS1_PI_166_DATA 0x00020064
+#define DDRSS1_PI_167_DATA 0x02000200
+#define DDRSS1_PI_168_DATA 0x48120C04
+#define DDRSS1_PI_169_DATA 0x00154812
+#define DDRSS1_PI_170_DATA 0x000000CE
+#define DDRSS1_PI_171_DATA 0x0000032B
+#define DDRSS1_PI_172_DATA 0x00002073
+#define DDRSS1_PI_173_DATA 0x0000032B
+#define DDRSS1_PI_174_DATA 0x04002073
+#define DDRSS1_PI_175_DATA 0x01010404
+#define DDRSS1_PI_176_DATA 0x00001501
+#define DDRSS1_PI_177_DATA 0x00150015
+#define DDRSS1_PI_178_DATA 0x01000100
+#define DDRSS1_PI_179_DATA 0x00000100
+#define DDRSS1_PI_180_DATA 0x00000000
+#define DDRSS1_PI_181_DATA 0x01010101
+#define DDRSS1_PI_182_DATA 0x00000101
+#define DDRSS1_PI_183_DATA 0x00000000
+#define DDRSS1_PI_184_DATA 0x00000000
+#define DDRSS1_PI_185_DATA 0x15040000
+#define DDRSS1_PI_186_DATA 0x0E0E0215
+#define DDRSS1_PI_187_DATA 0x00040402
+#define DDRSS1_PI_188_DATA 0x000D0035
+#define DDRSS1_PI_189_DATA 0x00218049
+#define DDRSS1_PI_190_DATA 0x00218049
+#define DDRSS1_PI_191_DATA 0x01010101
+#define DDRSS1_PI_192_DATA 0x0004000E
+#define DDRSS1_PI_193_DATA 0x00040216
+#define DDRSS1_PI_194_DATA 0x01000216
+#define DDRSS1_PI_195_DATA 0x000F000F
+#define DDRSS1_PI_196_DATA 0x02170100
+#define DDRSS1_PI_197_DATA 0x01000217
+#define DDRSS1_PI_198_DATA 0x02170217
+#define DDRSS1_PI_199_DATA 0x32103200
+#define DDRSS1_PI_200_DATA 0x01013210
+#define DDRSS1_PI_201_DATA 0x0A070601
+#define DDRSS1_PI_202_DATA 0x1F130A0D
+#define DDRSS1_PI_203_DATA 0x1F130A14
+#define DDRSS1_PI_204_DATA 0x0000C014
+#define DDRSS1_PI_205_DATA 0x00C01000
+#define DDRSS1_PI_206_DATA 0x00C01000
+#define DDRSS1_PI_207_DATA 0x00021000
+#define DDRSS1_PI_208_DATA 0x0024000E
+#define DDRSS1_PI_209_DATA 0x00240216
+#define DDRSS1_PI_210_DATA 0x00110216
+#define DDRSS1_PI_211_DATA 0x32000056
+#define DDRSS1_PI_212_DATA 0x00000301
+#define DDRSS1_PI_213_DATA 0x005B0036
+#define DDRSS1_PI_214_DATA 0x03013212
+#define DDRSS1_PI_215_DATA 0x00003600
+#define DDRSS1_PI_216_DATA 0x3212005B
+#define DDRSS1_PI_217_DATA 0x09000301
+#define DDRSS1_PI_218_DATA 0x04010504
+#define DDRSS1_PI_219_DATA 0x040006C9
+#define DDRSS1_PI_220_DATA 0x0A032001
+#define DDRSS1_PI_221_DATA 0x2C31110A
+#define DDRSS1_PI_222_DATA 0x00002918
+#define DDRSS1_PI_223_DATA 0x6001071C
+#define DDRSS1_PI_224_DATA 0x1E202008
+#define DDRSS1_PI_225_DATA 0x2C311116
+#define DDRSS1_PI_226_DATA 0x00002918
+#define DDRSS1_PI_227_DATA 0x6001071C
+#define DDRSS1_PI_228_DATA 0x1E202008
+#define DDRSS1_PI_229_DATA 0x00019C16
+#define DDRSS1_PI_230_DATA 0x00001018
+#define DDRSS1_PI_231_DATA 0x000040E6
+#define DDRSS1_PI_232_DATA 0x000288FC
+#define DDRSS1_PI_233_DATA 0x000040E6
+#define DDRSS1_PI_234_DATA 0x000288FC
+#define DDRSS1_PI_235_DATA 0x033B0016
+#define DDRSS1_PI_236_DATA 0x0303033B
+#define DDRSS1_PI_237_DATA 0x002AF803
+#define DDRSS1_PI_238_DATA 0x0001ADAF
+#define DDRSS1_PI_239_DATA 0x00000005
+#define DDRSS1_PI_240_DATA 0x0000006E
+#define DDRSS1_PI_241_DATA 0x00000016
+#define DDRSS1_PI_242_DATA 0x000681C8
+#define DDRSS1_PI_243_DATA 0x0001ADAF
+#define DDRSS1_PI_244_DATA 0x00000005
+#define DDRSS1_PI_245_DATA 0x000010A9
+#define DDRSS1_PI_246_DATA 0x0000033B
+#define DDRSS1_PI_247_DATA 0x000681C8
+#define DDRSS1_PI_248_DATA 0x0001ADAF
+#define DDRSS1_PI_249_DATA 0x00000005
+#define DDRSS1_PI_250_DATA 0x000010A9
+#define DDRSS1_PI_251_DATA 0x0100033B
+#define DDRSS1_PI_252_DATA 0x00370040
+#define DDRSS1_PI_253_DATA 0x00010008
+#define DDRSS1_PI_254_DATA 0x08550040
+#define DDRSS1_PI_255_DATA 0x00010040
+#define DDRSS1_PI_256_DATA 0x08550040
+#define DDRSS1_PI_257_DATA 0x00000340
+#define DDRSS1_PI_258_DATA 0x006B006B
+#define DDRSS1_PI_259_DATA 0x08040404
+#define DDRSS1_PI_260_DATA 0x00000055
+#define DDRSS1_PI_261_DATA 0x55083C5A
+#define DDRSS1_PI_262_DATA 0x5A000000
+#define DDRSS1_PI_263_DATA 0x0055083C
+#define DDRSS1_PI_264_DATA 0x3C5A0000
+#define DDRSS1_PI_265_DATA 0x00005508
+#define DDRSS1_PI_266_DATA 0x0C3C5A00
+#define DDRSS1_PI_267_DATA 0x080F0E0D
+#define DDRSS1_PI_268_DATA 0x000B0A09
+#define DDRSS1_PI_269_DATA 0x00030201
+#define DDRSS1_PI_270_DATA 0x01000000
+#define DDRSS1_PI_271_DATA 0x04020201
+#define DDRSS1_PI_272_DATA 0x00080804
+#define DDRSS1_PI_273_DATA 0x00000000
+#define DDRSS1_PI_274_DATA 0x00000000
+#define DDRSS1_PI_275_DATA 0x00330084
+#define DDRSS1_PI_276_DATA 0x00160000
+#define DDRSS1_PI_277_DATA 0x35333FF4
+#define DDRSS1_PI_278_DATA 0x00160F27
+#define DDRSS1_PI_279_DATA 0x35333FF4
+#define DDRSS1_PI_280_DATA 0x00160F27
+#define DDRSS1_PI_281_DATA 0x00330084
+#define DDRSS1_PI_282_DATA 0x00160000
+#define DDRSS1_PI_283_DATA 0x35333FF4
+#define DDRSS1_PI_284_DATA 0x00160F27
+#define DDRSS1_PI_285_DATA 0x35333FF4
+#define DDRSS1_PI_286_DATA 0x00160F27
+#define DDRSS1_PI_287_DATA 0x00330084
+#define DDRSS1_PI_288_DATA 0x00160000
+#define DDRSS1_PI_289_DATA 0x35333FF4
+#define DDRSS1_PI_290_DATA 0x00160F27
+#define DDRSS1_PI_291_DATA 0x35333FF4
+#define DDRSS1_PI_292_DATA 0x00160F27
+#define DDRSS1_PI_293_DATA 0x00330084
+#define DDRSS1_PI_294_DATA 0x00160000
+#define DDRSS1_PI_295_DATA 0x35333FF4
+#define DDRSS1_PI_296_DATA 0x00160F27
+#define DDRSS1_PI_297_DATA 0x35333FF4
+#define DDRSS1_PI_298_DATA 0x00160F27
+#define DDRSS1_PI_299_DATA 0x00000000
+
+#define DDRSS1_PHY_00_DATA 0x000004F0
+#define DDRSS1_PHY_01_DATA 0x00000000
+#define DDRSS1_PHY_02_DATA 0x00030200
+#define DDRSS1_PHY_03_DATA 0x00000000
+#define DDRSS1_PHY_04_DATA 0x00000000
+#define DDRSS1_PHY_05_DATA 0x01030000
+#define DDRSS1_PHY_06_DATA 0x00010000
+#define DDRSS1_PHY_07_DATA 0x01030004
+#define DDRSS1_PHY_08_DATA 0x01000000
+#define DDRSS1_PHY_09_DATA 0x00000000
+#define DDRSS1_PHY_10_DATA 0x00000000
+#define DDRSS1_PHY_11_DATA 0x01000001
+#define DDRSS1_PHY_12_DATA 0x00000100
+#define DDRSS1_PHY_13_DATA 0x000800C0
+#define DDRSS1_PHY_14_DATA 0x060100CC
+#define DDRSS1_PHY_15_DATA 0x00030066
+#define DDRSS1_PHY_16_DATA 0x00000000
+#define DDRSS1_PHY_17_DATA 0x00000301
+#define DDRSS1_PHY_18_DATA 0x0000AAAA
+#define DDRSS1_PHY_19_DATA 0x00005555
+#define DDRSS1_PHY_20_DATA 0x0000B5B5
+#define DDRSS1_PHY_21_DATA 0x00004A4A
+#define DDRSS1_PHY_22_DATA 0x00005656
+#define DDRSS1_PHY_23_DATA 0x0000A9A9
+#define DDRSS1_PHY_24_DATA 0x0000A9A9
+#define DDRSS1_PHY_25_DATA 0x0000B5B5
+#define DDRSS1_PHY_26_DATA 0x00000000
+#define DDRSS1_PHY_27_DATA 0x00000000
+#define DDRSS1_PHY_28_DATA 0x2A000000
+#define DDRSS1_PHY_29_DATA 0x00000808
+#define DDRSS1_PHY_30_DATA 0x0F000000
+#define DDRSS1_PHY_31_DATA 0x00000F0F
+#define DDRSS1_PHY_32_DATA 0x10400000
+#define DDRSS1_PHY_33_DATA 0x0C002006
+#define DDRSS1_PHY_34_DATA 0x00000000
+#define DDRSS1_PHY_35_DATA 0x00000000
+#define DDRSS1_PHY_36_DATA 0x55555555
+#define DDRSS1_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_38_DATA 0x55555555
+#define DDRSS1_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_40_DATA 0x00005555
+#define DDRSS1_PHY_41_DATA 0x01000100
+#define DDRSS1_PHY_42_DATA 0x00800180
+#define DDRSS1_PHY_43_DATA 0x00000001
+#define DDRSS1_PHY_44_DATA 0x00000000
+#define DDRSS1_PHY_45_DATA 0x00000000
+#define DDRSS1_PHY_46_DATA 0x00000000
+#define DDRSS1_PHY_47_DATA 0x00000000
+#define DDRSS1_PHY_48_DATA 0x00000000
+#define DDRSS1_PHY_49_DATA 0x00000000
+#define DDRSS1_PHY_50_DATA 0x00000000
+#define DDRSS1_PHY_51_DATA 0x00000000
+#define DDRSS1_PHY_52_DATA 0x00000000
+#define DDRSS1_PHY_53_DATA 0x00000000
+#define DDRSS1_PHY_54_DATA 0x00000000
+#define DDRSS1_PHY_55_DATA 0x00000000
+#define DDRSS1_PHY_56_DATA 0x00000000
+#define DDRSS1_PHY_57_DATA 0x00000000
+#define DDRSS1_PHY_58_DATA 0x00000000
+#define DDRSS1_PHY_59_DATA 0x00000000
+#define DDRSS1_PHY_60_DATA 0x00000000
+#define DDRSS1_PHY_61_DATA 0x00000000
+#define DDRSS1_PHY_62_DATA 0x00000000
+#define DDRSS1_PHY_63_DATA 0x00000000
+#define DDRSS1_PHY_64_DATA 0x00000000
+#define DDRSS1_PHY_65_DATA 0x00000000
+#define DDRSS1_PHY_66_DATA 0x00000104
+#define DDRSS1_PHY_67_DATA 0x00000120
+#define DDRSS1_PHY_68_DATA 0x00000000
+#define DDRSS1_PHY_69_DATA 0x00000000
+#define DDRSS1_PHY_70_DATA 0x00000000
+#define DDRSS1_PHY_71_DATA 0x00000000
+#define DDRSS1_PHY_72_DATA 0x00000000
+#define DDRSS1_PHY_73_DATA 0x00000000
+#define DDRSS1_PHY_74_DATA 0x00000000
+#define DDRSS1_PHY_75_DATA 0x00000001
+#define DDRSS1_PHY_76_DATA 0x07FF0000
+#define DDRSS1_PHY_77_DATA 0x0080081F
+#define DDRSS1_PHY_78_DATA 0x00081020
+#define DDRSS1_PHY_79_DATA 0x04010000
+#define DDRSS1_PHY_80_DATA 0x00000000
+#define DDRSS1_PHY_81_DATA 0x00000000
+#define DDRSS1_PHY_82_DATA 0x00000000
+#define DDRSS1_PHY_83_DATA 0x00000100
+#define DDRSS1_PHY_84_DATA 0x01CC0C01
+#define DDRSS1_PHY_85_DATA 0x1003CC0C
+#define DDRSS1_PHY_86_DATA 0x20000140
+#define DDRSS1_PHY_87_DATA 0x07FF0200
+#define DDRSS1_PHY_88_DATA 0x0000DD01
+#define DDRSS1_PHY_89_DATA 0x10100303
+#define DDRSS1_PHY_90_DATA 0x10101010
+#define DDRSS1_PHY_91_DATA 0x10101010
+#define DDRSS1_PHY_92_DATA 0x00021010
+#define DDRSS1_PHY_93_DATA 0x00100010
+#define DDRSS1_PHY_94_DATA 0x00100010
+#define DDRSS1_PHY_95_DATA 0x00100010
+#define DDRSS1_PHY_96_DATA 0x00100010
+#define DDRSS1_PHY_97_DATA 0x00050010
+#define DDRSS1_PHY_98_DATA 0x51517041
+#define DDRSS1_PHY_99_DATA 0x31C06001
+#define DDRSS1_PHY_100_DATA 0x07AB0340
+#define DDRSS1_PHY_101_DATA 0x00C0C001
+#define DDRSS1_PHY_102_DATA 0x0E0D0001
+#define DDRSS1_PHY_103_DATA 0x10001000
+#define DDRSS1_PHY_104_DATA 0x0C083E42
+#define DDRSS1_PHY_105_DATA 0x0F0C3701
+#define DDRSS1_PHY_106_DATA 0x01000140
+#define DDRSS1_PHY_107_DATA 0x0C000420
+#define DDRSS1_PHY_108_DATA 0x00000198
+#define DDRSS1_PHY_109_DATA 0x0A0000D0
+#define DDRSS1_PHY_110_DATA 0x00030200
+#define DDRSS1_PHY_111_DATA 0x02800000
+#define DDRSS1_PHY_112_DATA 0x80800000
+#define DDRSS1_PHY_113_DATA 0x000E2010
+#define DDRSS1_PHY_114_DATA 0x76543210
+#define DDRSS1_PHY_115_DATA 0x00000008
+#define DDRSS1_PHY_116_DATA 0x02800280
+#define DDRSS1_PHY_117_DATA 0x02800280
+#define DDRSS1_PHY_118_DATA 0x02800280
+#define DDRSS1_PHY_119_DATA 0x02800280
+#define DDRSS1_PHY_120_DATA 0x00000280
+#define DDRSS1_PHY_121_DATA 0x0000A000
+#define DDRSS1_PHY_122_DATA 0x00A000A0
+#define DDRSS1_PHY_123_DATA 0x00A000A0
+#define DDRSS1_PHY_124_DATA 0x00A000A0
+#define DDRSS1_PHY_125_DATA 0x00A000A0
+#define DDRSS1_PHY_126_DATA 0x00A000A0
+#define DDRSS1_PHY_127_DATA 0x00A000A0
+#define DDRSS1_PHY_128_DATA 0x00A000A0
+#define DDRSS1_PHY_129_DATA 0x00A000A0
+#define DDRSS1_PHY_130_DATA 0x01C200A0
+#define DDRSS1_PHY_131_DATA 0x01A00005
+#define DDRSS1_PHY_132_DATA 0x00000000
+#define DDRSS1_PHY_133_DATA 0x00000000
+#define DDRSS1_PHY_134_DATA 0x00080200
+#define DDRSS1_PHY_135_DATA 0x00000000
+#define DDRSS1_PHY_136_DATA 0x20202000
+#define DDRSS1_PHY_137_DATA 0x20202020
+#define DDRSS1_PHY_138_DATA 0xF0F02020
+#define DDRSS1_PHY_139_DATA 0x00000000
+#define DDRSS1_PHY_140_DATA 0x00000000
+#define DDRSS1_PHY_141_DATA 0x00000000
+#define DDRSS1_PHY_142_DATA 0x00000000
+#define DDRSS1_PHY_143_DATA 0x00000000
+#define DDRSS1_PHY_144_DATA 0x00000000
+#define DDRSS1_PHY_145_DATA 0x00000000
+#define DDRSS1_PHY_146_DATA 0x00000000
+#define DDRSS1_PHY_147_DATA 0x00000000
+#define DDRSS1_PHY_148_DATA 0x00000000
+#define DDRSS1_PHY_149_DATA 0x00000000
+#define DDRSS1_PHY_150_DATA 0x00000000
+#define DDRSS1_PHY_151_DATA 0x00000000
+#define DDRSS1_PHY_152_DATA 0x00000000
+#define DDRSS1_PHY_153_DATA 0x00000000
+#define DDRSS1_PHY_154_DATA 0x00000000
+#define DDRSS1_PHY_155_DATA 0x00000000
+#define DDRSS1_PHY_156_DATA 0x00000000
+#define DDRSS1_PHY_157_DATA 0x00000000
+#define DDRSS1_PHY_158_DATA 0x00000000
+#define DDRSS1_PHY_159_DATA 0x00000000
+#define DDRSS1_PHY_160_DATA 0x00000000
+#define DDRSS1_PHY_161_DATA 0x00000000
+#define DDRSS1_PHY_162_DATA 0x00000000
+#define DDRSS1_PHY_163_DATA 0x00000000
+#define DDRSS1_PHY_164_DATA 0x00000000
+#define DDRSS1_PHY_165_DATA 0x00000000
+#define DDRSS1_PHY_166_DATA 0x00000000
+#define DDRSS1_PHY_167_DATA 0x00000000
+#define DDRSS1_PHY_168_DATA 0x00000000
+#define DDRSS1_PHY_169_DATA 0x00000000
+#define DDRSS1_PHY_170_DATA 0x00000000
+#define DDRSS1_PHY_171_DATA 0x00000000
+#define DDRSS1_PHY_172_DATA 0x00000000
+#define DDRSS1_PHY_173_DATA 0x00000000
+#define DDRSS1_PHY_174_DATA 0x00000000
+#define DDRSS1_PHY_175_DATA 0x00000000
+#define DDRSS1_PHY_176_DATA 0x00000000
+#define DDRSS1_PHY_177_DATA 0x00000000
+#define DDRSS1_PHY_178_DATA 0x00000000
+#define DDRSS1_PHY_179_DATA 0x00000000
+#define DDRSS1_PHY_180_DATA 0x00000000
+#define DDRSS1_PHY_181_DATA 0x00000000
+#define DDRSS1_PHY_182_DATA 0x00000000
+#define DDRSS1_PHY_183_DATA 0x00000000
+#define DDRSS1_PHY_184_DATA 0x00000000
+#define DDRSS1_PHY_185_DATA 0x00000000
+#define DDRSS1_PHY_186_DATA 0x00000000
+#define DDRSS1_PHY_187_DATA 0x00000000
+#define DDRSS1_PHY_188_DATA 0x00000000
+#define DDRSS1_PHY_189_DATA 0x00000000
+#define DDRSS1_PHY_190_DATA 0x00000000
+#define DDRSS1_PHY_191_DATA 0x00000000
+#define DDRSS1_PHY_192_DATA 0x00000000
+#define DDRSS1_PHY_193_DATA 0x00000000
+#define DDRSS1_PHY_194_DATA 0x00000000
+#define DDRSS1_PHY_195_DATA 0x00000000
+#define DDRSS1_PHY_196_DATA 0x00000000
+#define DDRSS1_PHY_197_DATA 0x00000000
+#define DDRSS1_PHY_198_DATA 0x00000000
+#define DDRSS1_PHY_199_DATA 0x00000000
+#define DDRSS1_PHY_200_DATA 0x00000000
+#define DDRSS1_PHY_201_DATA 0x00000000
+#define DDRSS1_PHY_202_DATA 0x00000000
+#define DDRSS1_PHY_203_DATA 0x00000000
+#define DDRSS1_PHY_204_DATA 0x00000000
+#define DDRSS1_PHY_205_DATA 0x00000000
+#define DDRSS1_PHY_206_DATA 0x00000000
+#define DDRSS1_PHY_207_DATA 0x00000000
+#define DDRSS1_PHY_208_DATA 0x00000000
+#define DDRSS1_PHY_209_DATA 0x00000000
+#define DDRSS1_PHY_210_DATA 0x00000000
+#define DDRSS1_PHY_211_DATA 0x00000000
+#define DDRSS1_PHY_212_DATA 0x00000000
+#define DDRSS1_PHY_213_DATA 0x00000000
+#define DDRSS1_PHY_214_DATA 0x00000000
+#define DDRSS1_PHY_215_DATA 0x00000000
+#define DDRSS1_PHY_216_DATA 0x00000000
+#define DDRSS1_PHY_217_DATA 0x00000000
+#define DDRSS1_PHY_218_DATA 0x00000000
+#define DDRSS1_PHY_219_DATA 0x00000000
+#define DDRSS1_PHY_220_DATA 0x00000000
+#define DDRSS1_PHY_221_DATA 0x00000000
+#define DDRSS1_PHY_222_DATA 0x00000000
+#define DDRSS1_PHY_223_DATA 0x00000000
+#define DDRSS1_PHY_224_DATA 0x00000000
+#define DDRSS1_PHY_225_DATA 0x00000000
+#define DDRSS1_PHY_226_DATA 0x00000000
+#define DDRSS1_PHY_227_DATA 0x00000000
+#define DDRSS1_PHY_228_DATA 0x00000000
+#define DDRSS1_PHY_229_DATA 0x00000000
+#define DDRSS1_PHY_230_DATA 0x00000000
+#define DDRSS1_PHY_231_DATA 0x00000000
+#define DDRSS1_PHY_232_DATA 0x00000000
+#define DDRSS1_PHY_233_DATA 0x00000000
+#define DDRSS1_PHY_234_DATA 0x00000000
+#define DDRSS1_PHY_235_DATA 0x00000000
+#define DDRSS1_PHY_236_DATA 0x00000000
+#define DDRSS1_PHY_237_DATA 0x00000000
+#define DDRSS1_PHY_238_DATA 0x00000000
+#define DDRSS1_PHY_239_DATA 0x00000000
+#define DDRSS1_PHY_240_DATA 0x00000000
+#define DDRSS1_PHY_241_DATA 0x00000000
+#define DDRSS1_PHY_242_DATA 0x00000000
+#define DDRSS1_PHY_243_DATA 0x00000000
+#define DDRSS1_PHY_244_DATA 0x00000000
+#define DDRSS1_PHY_245_DATA 0x00000000
+#define DDRSS1_PHY_246_DATA 0x00000000
+#define DDRSS1_PHY_247_DATA 0x00000000
+#define DDRSS1_PHY_248_DATA 0x00000000
+#define DDRSS1_PHY_249_DATA 0x00000000
+#define DDRSS1_PHY_250_DATA 0x00000000
+#define DDRSS1_PHY_251_DATA 0x00000000
+#define DDRSS1_PHY_252_DATA 0x00000000
+#define DDRSS1_PHY_253_DATA 0x00000000
+#define DDRSS1_PHY_254_DATA 0x00000000
+#define DDRSS1_PHY_255_DATA 0x00000000
+#define DDRSS1_PHY_256_DATA 0x000004F0
+#define DDRSS1_PHY_257_DATA 0x00000000
+#define DDRSS1_PHY_258_DATA 0x00030200
+#define DDRSS1_PHY_259_DATA 0x00000000
+#define DDRSS1_PHY_260_DATA 0x00000000
+#define DDRSS1_PHY_261_DATA 0x01030000
+#define DDRSS1_PHY_262_DATA 0x00010000
+#define DDRSS1_PHY_263_DATA 0x01030004
+#define DDRSS1_PHY_264_DATA 0x01000000
+#define DDRSS1_PHY_265_DATA 0x00000000
+#define DDRSS1_PHY_266_DATA 0x00000000
+#define DDRSS1_PHY_267_DATA 0x01000001
+#define DDRSS1_PHY_268_DATA 0x00000100
+#define DDRSS1_PHY_269_DATA 0x000800C0
+#define DDRSS1_PHY_270_DATA 0x060100CC
+#define DDRSS1_PHY_271_DATA 0x00030066
+#define DDRSS1_PHY_272_DATA 0x00000000
+#define DDRSS1_PHY_273_DATA 0x00000301
+#define DDRSS1_PHY_274_DATA 0x0000AAAA
+#define DDRSS1_PHY_275_DATA 0x00005555
+#define DDRSS1_PHY_276_DATA 0x0000B5B5
+#define DDRSS1_PHY_277_DATA 0x00004A4A
+#define DDRSS1_PHY_278_DATA 0x00005656
+#define DDRSS1_PHY_279_DATA 0x0000A9A9
+#define DDRSS1_PHY_280_DATA 0x0000A9A9
+#define DDRSS1_PHY_281_DATA 0x0000B5B5
+#define DDRSS1_PHY_282_DATA 0x00000000
+#define DDRSS1_PHY_283_DATA 0x00000000
+#define DDRSS1_PHY_284_DATA 0x2A000000
+#define DDRSS1_PHY_285_DATA 0x00000808
+#define DDRSS1_PHY_286_DATA 0x0F000000
+#define DDRSS1_PHY_287_DATA 0x00000F0F
+#define DDRSS1_PHY_288_DATA 0x10400000
+#define DDRSS1_PHY_289_DATA 0x0C002006
+#define DDRSS1_PHY_290_DATA 0x00000000
+#define DDRSS1_PHY_291_DATA 0x00000000
+#define DDRSS1_PHY_292_DATA 0x55555555
+#define DDRSS1_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_294_DATA 0x55555555
+#define DDRSS1_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_296_DATA 0x00005555
+#define DDRSS1_PHY_297_DATA 0x01000100
+#define DDRSS1_PHY_298_DATA 0x00800180
+#define DDRSS1_PHY_299_DATA 0x00000000
+#define DDRSS1_PHY_300_DATA 0x00000000
+#define DDRSS1_PHY_301_DATA 0x00000000
+#define DDRSS1_PHY_302_DATA 0x00000000
+#define DDRSS1_PHY_303_DATA 0x00000000
+#define DDRSS1_PHY_304_DATA 0x00000000
+#define DDRSS1_PHY_305_DATA 0x00000000
+#define DDRSS1_PHY_306_DATA 0x00000000
+#define DDRSS1_PHY_307_DATA 0x00000000
+#define DDRSS1_PHY_308_DATA 0x00000000
+#define DDRSS1_PHY_309_DATA 0x00000000
+#define DDRSS1_PHY_310_DATA 0x00000000
+#define DDRSS1_PHY_311_DATA 0x00000000
+#define DDRSS1_PHY_312_DATA 0x00000000
+#define DDRSS1_PHY_313_DATA 0x00000000
+#define DDRSS1_PHY_314_DATA 0x00000000
+#define DDRSS1_PHY_315_DATA 0x00000000
+#define DDRSS1_PHY_316_DATA 0x00000000
+#define DDRSS1_PHY_317_DATA 0x00000000
+#define DDRSS1_PHY_318_DATA 0x00000000
+#define DDRSS1_PHY_319_DATA 0x00000000
+#define DDRSS1_PHY_320_DATA 0x00000000
+#define DDRSS1_PHY_321_DATA 0x00000000
+#define DDRSS1_PHY_322_DATA 0x00000104
+#define DDRSS1_PHY_323_DATA 0x00000120
+#define DDRSS1_PHY_324_DATA 0x00000000
+#define DDRSS1_PHY_325_DATA 0x00000000
+#define DDRSS1_PHY_326_DATA 0x00000000
+#define DDRSS1_PHY_327_DATA 0x00000000
+#define DDRSS1_PHY_328_DATA 0x00000000
+#define DDRSS1_PHY_329_DATA 0x00000000
+#define DDRSS1_PHY_330_DATA 0x00000000
+#define DDRSS1_PHY_331_DATA 0x00000001
+#define DDRSS1_PHY_332_DATA 0x07FF0000
+#define DDRSS1_PHY_333_DATA 0x0080081F
+#define DDRSS1_PHY_334_DATA 0x00081020
+#define DDRSS1_PHY_335_DATA 0x04010000
+#define DDRSS1_PHY_336_DATA 0x00000000
+#define DDRSS1_PHY_337_DATA 0x00000000
+#define DDRSS1_PHY_338_DATA 0x00000000
+#define DDRSS1_PHY_339_DATA 0x00000100
+#define DDRSS1_PHY_340_DATA 0x01CC0C01
+#define DDRSS1_PHY_341_DATA 0x1003CC0C
+#define DDRSS1_PHY_342_DATA 0x20000140
+#define DDRSS1_PHY_343_DATA 0x07FF0200
+#define DDRSS1_PHY_344_DATA 0x0000DD01
+#define DDRSS1_PHY_345_DATA 0x10100303
+#define DDRSS1_PHY_346_DATA 0x10101010
+#define DDRSS1_PHY_347_DATA 0x10101010
+#define DDRSS1_PHY_348_DATA 0x00021010
+#define DDRSS1_PHY_349_DATA 0x00100010
+#define DDRSS1_PHY_350_DATA 0x00100010
+#define DDRSS1_PHY_351_DATA 0x00100010
+#define DDRSS1_PHY_352_DATA 0x00100010
+#define DDRSS1_PHY_353_DATA 0x00050010
+#define DDRSS1_PHY_354_DATA 0x51517041
+#define DDRSS1_PHY_355_DATA 0x31C06001
+#define DDRSS1_PHY_356_DATA 0x07AB0340
+#define DDRSS1_PHY_357_DATA 0x00C0C001
+#define DDRSS1_PHY_358_DATA 0x0E0D0001
+#define DDRSS1_PHY_359_DATA 0x10001000
+#define DDRSS1_PHY_360_DATA 0x0C083E42
+#define DDRSS1_PHY_361_DATA 0x0F0C3701
+#define DDRSS1_PHY_362_DATA 0x01000140
+#define DDRSS1_PHY_363_DATA 0x0C000420
+#define DDRSS1_PHY_364_DATA 0x00000198
+#define DDRSS1_PHY_365_DATA 0x0A0000D0
+#define DDRSS1_PHY_366_DATA 0x00030200
+#define DDRSS1_PHY_367_DATA 0x02800000
+#define DDRSS1_PHY_368_DATA 0x80800000
+#define DDRSS1_PHY_369_DATA 0x000E2010
+#define DDRSS1_PHY_370_DATA 0x76543210
+#define DDRSS1_PHY_371_DATA 0x00000008
+#define DDRSS1_PHY_372_DATA 0x02800280
+#define DDRSS1_PHY_373_DATA 0x02800280
+#define DDRSS1_PHY_374_DATA 0x02800280
+#define DDRSS1_PHY_375_DATA 0x02800280
+#define DDRSS1_PHY_376_DATA 0x00000280
+#define DDRSS1_PHY_377_DATA 0x0000A000
+#define DDRSS1_PHY_378_DATA 0x00A000A0
+#define DDRSS1_PHY_379_DATA 0x00A000A0
+#define DDRSS1_PHY_380_DATA 0x00A000A0
+#define DDRSS1_PHY_381_DATA 0x00A000A0
+#define DDRSS1_PHY_382_DATA 0x00A000A0
+#define DDRSS1_PHY_383_DATA 0x00A000A0
+#define DDRSS1_PHY_384_DATA 0x00A000A0
+#define DDRSS1_PHY_385_DATA 0x00A000A0
+#define DDRSS1_PHY_386_DATA 0x01C200A0
+#define DDRSS1_PHY_387_DATA 0x01A00005
+#define DDRSS1_PHY_388_DATA 0x00000000
+#define DDRSS1_PHY_389_DATA 0x00000000
+#define DDRSS1_PHY_390_DATA 0x00080200
+#define DDRSS1_PHY_391_DATA 0x00000000
+#define DDRSS1_PHY_392_DATA 0x20202000
+#define DDRSS1_PHY_393_DATA 0x20202020
+#define DDRSS1_PHY_394_DATA 0xF0F02020
+#define DDRSS1_PHY_395_DATA 0x00000000
+#define DDRSS1_PHY_396_DATA 0x00000000
+#define DDRSS1_PHY_397_DATA 0x00000000
+#define DDRSS1_PHY_398_DATA 0x00000000
+#define DDRSS1_PHY_399_DATA 0x00000000
+#define DDRSS1_PHY_400_DATA 0x00000000
+#define DDRSS1_PHY_401_DATA 0x00000000
+#define DDRSS1_PHY_402_DATA 0x00000000
+#define DDRSS1_PHY_403_DATA 0x00000000
+#define DDRSS1_PHY_404_DATA 0x00000000
+#define DDRSS1_PHY_405_DATA 0x00000000
+#define DDRSS1_PHY_406_DATA 0x00000000
+#define DDRSS1_PHY_407_DATA 0x00000000
+#define DDRSS1_PHY_408_DATA 0x00000000
+#define DDRSS1_PHY_409_DATA 0x00000000
+#define DDRSS1_PHY_410_DATA 0x00000000
+#define DDRSS1_PHY_411_DATA 0x00000000
+#define DDRSS1_PHY_412_DATA 0x00000000
+#define DDRSS1_PHY_413_DATA 0x00000000
+#define DDRSS1_PHY_414_DATA 0x00000000
+#define DDRSS1_PHY_415_DATA 0x00000000
+#define DDRSS1_PHY_416_DATA 0x00000000
+#define DDRSS1_PHY_417_DATA 0x00000000
+#define DDRSS1_PHY_418_DATA 0x00000000
+#define DDRSS1_PHY_419_DATA 0x00000000
+#define DDRSS1_PHY_420_DATA 0x00000000
+#define DDRSS1_PHY_421_DATA 0x00000000
+#define DDRSS1_PHY_422_DATA 0x00000000
+#define DDRSS1_PHY_423_DATA 0x00000000
+#define DDRSS1_PHY_424_DATA 0x00000000
+#define DDRSS1_PHY_425_DATA 0x00000000
+#define DDRSS1_PHY_426_DATA 0x00000000
+#define DDRSS1_PHY_427_DATA 0x00000000
+#define DDRSS1_PHY_428_DATA 0x00000000
+#define DDRSS1_PHY_429_DATA 0x00000000
+#define DDRSS1_PHY_430_DATA 0x00000000
+#define DDRSS1_PHY_431_DATA 0x00000000
+#define DDRSS1_PHY_432_DATA 0x00000000
+#define DDRSS1_PHY_433_DATA 0x00000000
+#define DDRSS1_PHY_434_DATA 0x00000000
+#define DDRSS1_PHY_435_DATA 0x00000000
+#define DDRSS1_PHY_436_DATA 0x00000000
+#define DDRSS1_PHY_437_DATA 0x00000000
+#define DDRSS1_PHY_438_DATA 0x00000000
+#define DDRSS1_PHY_439_DATA 0x00000000
+#define DDRSS1_PHY_440_DATA 0x00000000
+#define DDRSS1_PHY_441_DATA 0x00000000
+#define DDRSS1_PHY_442_DATA 0x00000000
+#define DDRSS1_PHY_443_DATA 0x00000000
+#define DDRSS1_PHY_444_DATA 0x00000000
+#define DDRSS1_PHY_445_DATA 0x00000000
+#define DDRSS1_PHY_446_DATA 0x00000000
+#define DDRSS1_PHY_447_DATA 0x00000000
+#define DDRSS1_PHY_448_DATA 0x00000000
+#define DDRSS1_PHY_449_DATA 0x00000000
+#define DDRSS1_PHY_450_DATA 0x00000000
+#define DDRSS1_PHY_451_DATA 0x00000000
+#define DDRSS1_PHY_452_DATA 0x00000000
+#define DDRSS1_PHY_453_DATA 0x00000000
+#define DDRSS1_PHY_454_DATA 0x00000000
+#define DDRSS1_PHY_455_DATA 0x00000000
+#define DDRSS1_PHY_456_DATA 0x00000000
+#define DDRSS1_PHY_457_DATA 0x00000000
+#define DDRSS1_PHY_458_DATA 0x00000000
+#define DDRSS1_PHY_459_DATA 0x00000000
+#define DDRSS1_PHY_460_DATA 0x00000000
+#define DDRSS1_PHY_461_DATA 0x00000000
+#define DDRSS1_PHY_462_DATA 0x00000000
+#define DDRSS1_PHY_463_DATA 0x00000000
+#define DDRSS1_PHY_464_DATA 0x00000000
+#define DDRSS1_PHY_465_DATA 0x00000000
+#define DDRSS1_PHY_466_DATA 0x00000000
+#define DDRSS1_PHY_467_DATA 0x00000000
+#define DDRSS1_PHY_468_DATA 0x00000000
+#define DDRSS1_PHY_469_DATA 0x00000000
+#define DDRSS1_PHY_470_DATA 0x00000000
+#define DDRSS1_PHY_471_DATA 0x00000000
+#define DDRSS1_PHY_472_DATA 0x00000000
+#define DDRSS1_PHY_473_DATA 0x00000000
+#define DDRSS1_PHY_474_DATA 0x00000000
+#define DDRSS1_PHY_475_DATA 0x00000000
+#define DDRSS1_PHY_476_DATA 0x00000000
+#define DDRSS1_PHY_477_DATA 0x00000000
+#define DDRSS1_PHY_478_DATA 0x00000000
+#define DDRSS1_PHY_479_DATA 0x00000000
+#define DDRSS1_PHY_480_DATA 0x00000000
+#define DDRSS1_PHY_481_DATA 0x00000000
+#define DDRSS1_PHY_482_DATA 0x00000000
+#define DDRSS1_PHY_483_DATA 0x00000000
+#define DDRSS1_PHY_484_DATA 0x00000000
+#define DDRSS1_PHY_485_DATA 0x00000000
+#define DDRSS1_PHY_486_DATA 0x00000000
+#define DDRSS1_PHY_487_DATA 0x00000000
+#define DDRSS1_PHY_488_DATA 0x00000000
+#define DDRSS1_PHY_489_DATA 0x00000000
+#define DDRSS1_PHY_490_DATA 0x00000000
+#define DDRSS1_PHY_491_DATA 0x00000000
+#define DDRSS1_PHY_492_DATA 0x00000000
+#define DDRSS1_PHY_493_DATA 0x00000000
+#define DDRSS1_PHY_494_DATA 0x00000000
+#define DDRSS1_PHY_495_DATA 0x00000000
+#define DDRSS1_PHY_496_DATA 0x00000000
+#define DDRSS1_PHY_497_DATA 0x00000000
+#define DDRSS1_PHY_498_DATA 0x00000000
+#define DDRSS1_PHY_499_DATA 0x00000000
+#define DDRSS1_PHY_500_DATA 0x00000000
+#define DDRSS1_PHY_501_DATA 0x00000000
+#define DDRSS1_PHY_502_DATA 0x00000000
+#define DDRSS1_PHY_503_DATA 0x00000000
+#define DDRSS1_PHY_504_DATA 0x00000000
+#define DDRSS1_PHY_505_DATA 0x00000000
+#define DDRSS1_PHY_506_DATA 0x00000000
+#define DDRSS1_PHY_507_DATA 0x00000000
+#define DDRSS1_PHY_508_DATA 0x00000000
+#define DDRSS1_PHY_509_DATA 0x00000000
+#define DDRSS1_PHY_510_DATA 0x00000000
+#define DDRSS1_PHY_511_DATA 0x00000000
+#define DDRSS1_PHY_512_DATA 0x000004F0
+#define DDRSS1_PHY_513_DATA 0x00000000
+#define DDRSS1_PHY_514_DATA 0x00030200
+#define DDRSS1_PHY_515_DATA 0x00000000
+#define DDRSS1_PHY_516_DATA 0x00000000
+#define DDRSS1_PHY_517_DATA 0x01030000
+#define DDRSS1_PHY_518_DATA 0x00010000
+#define DDRSS1_PHY_519_DATA 0x01030004
+#define DDRSS1_PHY_520_DATA 0x01000000
+#define DDRSS1_PHY_521_DATA 0x00000000
+#define DDRSS1_PHY_522_DATA 0x00000000
+#define DDRSS1_PHY_523_DATA 0x01000001
+#define DDRSS1_PHY_524_DATA 0x00000100
+#define DDRSS1_PHY_525_DATA 0x000800C0
+#define DDRSS1_PHY_526_DATA 0x060100CC
+#define DDRSS1_PHY_527_DATA 0x00030066
+#define DDRSS1_PHY_528_DATA 0x00000000
+#define DDRSS1_PHY_529_DATA 0x00000301
+#define DDRSS1_PHY_530_DATA 0x0000AAAA
+#define DDRSS1_PHY_531_DATA 0x00005555
+#define DDRSS1_PHY_532_DATA 0x0000B5B5
+#define DDRSS1_PHY_533_DATA 0x00004A4A
+#define DDRSS1_PHY_534_DATA 0x00005656
+#define DDRSS1_PHY_535_DATA 0x0000A9A9
+#define DDRSS1_PHY_536_DATA 0x0000A9A9
+#define DDRSS1_PHY_537_DATA 0x0000B5B5
+#define DDRSS1_PHY_538_DATA 0x00000000
+#define DDRSS1_PHY_539_DATA 0x00000000
+#define DDRSS1_PHY_540_DATA 0x2A000000
+#define DDRSS1_PHY_541_DATA 0x00000808
+#define DDRSS1_PHY_542_DATA 0x0F000000
+#define DDRSS1_PHY_543_DATA 0x00000F0F
+#define DDRSS1_PHY_544_DATA 0x10400000
+#define DDRSS1_PHY_545_DATA 0x0C002006
+#define DDRSS1_PHY_546_DATA 0x00000000
+#define DDRSS1_PHY_547_DATA 0x00000000
+#define DDRSS1_PHY_548_DATA 0x55555555
+#define DDRSS1_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_550_DATA 0x55555555
+#define DDRSS1_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_552_DATA 0x00005555
+#define DDRSS1_PHY_553_DATA 0x01000100
+#define DDRSS1_PHY_554_DATA 0x00800180
+#define DDRSS1_PHY_555_DATA 0x00000001
+#define DDRSS1_PHY_556_DATA 0x00000000
+#define DDRSS1_PHY_557_DATA 0x00000000
+#define DDRSS1_PHY_558_DATA 0x00000000
+#define DDRSS1_PHY_559_DATA 0x00000000
+#define DDRSS1_PHY_560_DATA 0x00000000
+#define DDRSS1_PHY_561_DATA 0x00000000
+#define DDRSS1_PHY_562_DATA 0x00000000
+#define DDRSS1_PHY_563_DATA 0x00000000
+#define DDRSS1_PHY_564_DATA 0x00000000
+#define DDRSS1_PHY_565_DATA 0x00000000
+#define DDRSS1_PHY_566_DATA 0x00000000
+#define DDRSS1_PHY_567_DATA 0x00000000
+#define DDRSS1_PHY_568_DATA 0x00000000
+#define DDRSS1_PHY_569_DATA 0x00000000
+#define DDRSS1_PHY_570_DATA 0x00000000
+#define DDRSS1_PHY_571_DATA 0x00000000
+#define DDRSS1_PHY_572_DATA 0x00000000
+#define DDRSS1_PHY_573_DATA 0x00000000
+#define DDRSS1_PHY_574_DATA 0x00000000
+#define DDRSS1_PHY_575_DATA 0x00000000
+#define DDRSS1_PHY_576_DATA 0x00000000
+#define DDRSS1_PHY_577_DATA 0x00000000
+#define DDRSS1_PHY_578_DATA 0x00000104
+#define DDRSS1_PHY_579_DATA 0x00000120
+#define DDRSS1_PHY_580_DATA 0x00000000
+#define DDRSS1_PHY_581_DATA 0x00000000
+#define DDRSS1_PHY_582_DATA 0x00000000
+#define DDRSS1_PHY_583_DATA 0x00000000
+#define DDRSS1_PHY_584_DATA 0x00000000
+#define DDRSS1_PHY_585_DATA 0x00000000
+#define DDRSS1_PHY_586_DATA 0x00000000
+#define DDRSS1_PHY_587_DATA 0x00000001
+#define DDRSS1_PHY_588_DATA 0x07FF0000
+#define DDRSS1_PHY_589_DATA 0x0080081F
+#define DDRSS1_PHY_590_DATA 0x00081020
+#define DDRSS1_PHY_591_DATA 0x04010000
+#define DDRSS1_PHY_592_DATA 0x00000000
+#define DDRSS1_PHY_593_DATA 0x00000000
+#define DDRSS1_PHY_594_DATA 0x00000000
+#define DDRSS1_PHY_595_DATA 0x00000100
+#define DDRSS1_PHY_596_DATA 0x01CC0C01
+#define DDRSS1_PHY_597_DATA 0x1003CC0C
+#define DDRSS1_PHY_598_DATA 0x20000140
+#define DDRSS1_PHY_599_DATA 0x07FF0200
+#define DDRSS1_PHY_600_DATA 0x0000DD01
+#define DDRSS1_PHY_601_DATA 0x10100303
+#define DDRSS1_PHY_602_DATA 0x10101010
+#define DDRSS1_PHY_603_DATA 0x10101010
+#define DDRSS1_PHY_604_DATA 0x00021010
+#define DDRSS1_PHY_605_DATA 0x00100010
+#define DDRSS1_PHY_606_DATA 0x00100010
+#define DDRSS1_PHY_607_DATA 0x00100010
+#define DDRSS1_PHY_608_DATA 0x00100010
+#define DDRSS1_PHY_609_DATA 0x00050010
+#define DDRSS1_PHY_610_DATA 0x51517041
+#define DDRSS1_PHY_611_DATA 0x31C06001
+#define DDRSS1_PHY_612_DATA 0x07AB0340
+#define DDRSS1_PHY_613_DATA 0x00C0C001
+#define DDRSS1_PHY_614_DATA 0x0E0D0001
+#define DDRSS1_PHY_615_DATA 0x10001000
+#define DDRSS1_PHY_616_DATA 0x0C083E42
+#define DDRSS1_PHY_617_DATA 0x0F0C3701
+#define DDRSS1_PHY_618_DATA 0x01000140
+#define DDRSS1_PHY_619_DATA 0x0C000420
+#define DDRSS1_PHY_620_DATA 0x00000198
+#define DDRSS1_PHY_621_DATA 0x0A0000D0
+#define DDRSS1_PHY_622_DATA 0x00030200
+#define DDRSS1_PHY_623_DATA 0x02800000
+#define DDRSS1_PHY_624_DATA 0x80800000
+#define DDRSS1_PHY_625_DATA 0x000E2010
+#define DDRSS1_PHY_626_DATA 0x76543210
+#define DDRSS1_PHY_627_DATA 0x00000008
+#define DDRSS1_PHY_628_DATA 0x02800280
+#define DDRSS1_PHY_629_DATA 0x02800280
+#define DDRSS1_PHY_630_DATA 0x02800280
+#define DDRSS1_PHY_631_DATA 0x02800280
+#define DDRSS1_PHY_632_DATA 0x00000280
+#define DDRSS1_PHY_633_DATA 0x0000A000
+#define DDRSS1_PHY_634_DATA 0x00A000A0
+#define DDRSS1_PHY_635_DATA 0x00A000A0
+#define DDRSS1_PHY_636_DATA 0x00A000A0
+#define DDRSS1_PHY_637_DATA 0x00A000A0
+#define DDRSS1_PHY_638_DATA 0x00A000A0
+#define DDRSS1_PHY_639_DATA 0x00A000A0
+#define DDRSS1_PHY_640_DATA 0x00A000A0
+#define DDRSS1_PHY_641_DATA 0x00A000A0
+#define DDRSS1_PHY_642_DATA 0x01C200A0
+#define DDRSS1_PHY_643_DATA 0x01A00005
+#define DDRSS1_PHY_644_DATA 0x00000000
+#define DDRSS1_PHY_645_DATA 0x00000000
+#define DDRSS1_PHY_646_DATA 0x00080200
+#define DDRSS1_PHY_647_DATA 0x00000000
+#define DDRSS1_PHY_648_DATA 0x20202000
+#define DDRSS1_PHY_649_DATA 0x20202020
+#define DDRSS1_PHY_650_DATA 0xF0F02020
+#define DDRSS1_PHY_651_DATA 0x00000000
+#define DDRSS1_PHY_652_DATA 0x00000000
+#define DDRSS1_PHY_653_DATA 0x00000000
+#define DDRSS1_PHY_654_DATA 0x00000000
+#define DDRSS1_PHY_655_DATA 0x00000000
+#define DDRSS1_PHY_656_DATA 0x00000000
+#define DDRSS1_PHY_657_DATA 0x00000000
+#define DDRSS1_PHY_658_DATA 0x00000000
+#define DDRSS1_PHY_659_DATA 0x00000000
+#define DDRSS1_PHY_660_DATA 0x00000000
+#define DDRSS1_PHY_661_DATA 0x00000000
+#define DDRSS1_PHY_662_DATA 0x00000000
+#define DDRSS1_PHY_663_DATA 0x00000000
+#define DDRSS1_PHY_664_DATA 0x00000000
+#define DDRSS1_PHY_665_DATA 0x00000000
+#define DDRSS1_PHY_666_DATA 0x00000000
+#define DDRSS1_PHY_667_DATA 0x00000000
+#define DDRSS1_PHY_668_DATA 0x00000000
+#define DDRSS1_PHY_669_DATA 0x00000000
+#define DDRSS1_PHY_670_DATA 0x00000000
+#define DDRSS1_PHY_671_DATA 0x00000000
+#define DDRSS1_PHY_672_DATA 0x00000000
+#define DDRSS1_PHY_673_DATA 0x00000000
+#define DDRSS1_PHY_674_DATA 0x00000000
+#define DDRSS1_PHY_675_DATA 0x00000000
+#define DDRSS1_PHY_676_DATA 0x00000000
+#define DDRSS1_PHY_677_DATA 0x00000000
+#define DDRSS1_PHY_678_DATA 0x00000000
+#define DDRSS1_PHY_679_DATA 0x00000000
+#define DDRSS1_PHY_680_DATA 0x00000000
+#define DDRSS1_PHY_681_DATA 0x00000000
+#define DDRSS1_PHY_682_DATA 0x00000000
+#define DDRSS1_PHY_683_DATA 0x00000000
+#define DDRSS1_PHY_684_DATA 0x00000000
+#define DDRSS1_PHY_685_DATA 0x00000000
+#define DDRSS1_PHY_686_DATA 0x00000000
+#define DDRSS1_PHY_687_DATA 0x00000000
+#define DDRSS1_PHY_688_DATA 0x00000000
+#define DDRSS1_PHY_689_DATA 0x00000000
+#define DDRSS1_PHY_690_DATA 0x00000000
+#define DDRSS1_PHY_691_DATA 0x00000000
+#define DDRSS1_PHY_692_DATA 0x00000000
+#define DDRSS1_PHY_693_DATA 0x00000000
+#define DDRSS1_PHY_694_DATA 0x00000000
+#define DDRSS1_PHY_695_DATA 0x00000000
+#define DDRSS1_PHY_696_DATA 0x00000000
+#define DDRSS1_PHY_697_DATA 0x00000000
+#define DDRSS1_PHY_698_DATA 0x00000000
+#define DDRSS1_PHY_699_DATA 0x00000000
+#define DDRSS1_PHY_700_DATA 0x00000000
+#define DDRSS1_PHY_701_DATA 0x00000000
+#define DDRSS1_PHY_702_DATA 0x00000000
+#define DDRSS1_PHY_703_DATA 0x00000000
+#define DDRSS1_PHY_704_DATA 0x00000000
+#define DDRSS1_PHY_705_DATA 0x00000000
+#define DDRSS1_PHY_706_DATA 0x00000000
+#define DDRSS1_PHY_707_DATA 0x00000000
+#define DDRSS1_PHY_708_DATA 0x00000000
+#define DDRSS1_PHY_709_DATA 0x00000000
+#define DDRSS1_PHY_710_DATA 0x00000000
+#define DDRSS1_PHY_711_DATA 0x00000000
+#define DDRSS1_PHY_712_DATA 0x00000000
+#define DDRSS1_PHY_713_DATA 0x00000000
+#define DDRSS1_PHY_714_DATA 0x00000000
+#define DDRSS1_PHY_715_DATA 0x00000000
+#define DDRSS1_PHY_716_DATA 0x00000000
+#define DDRSS1_PHY_717_DATA 0x00000000
+#define DDRSS1_PHY_718_DATA 0x00000000
+#define DDRSS1_PHY_719_DATA 0x00000000
+#define DDRSS1_PHY_720_DATA 0x00000000
+#define DDRSS1_PHY_721_DATA 0x00000000
+#define DDRSS1_PHY_722_DATA 0x00000000
+#define DDRSS1_PHY_723_DATA 0x00000000
+#define DDRSS1_PHY_724_DATA 0x00000000
+#define DDRSS1_PHY_725_DATA 0x00000000
+#define DDRSS1_PHY_726_DATA 0x00000000
+#define DDRSS1_PHY_727_DATA 0x00000000
+#define DDRSS1_PHY_728_DATA 0x00000000
+#define DDRSS1_PHY_729_DATA 0x00000000
+#define DDRSS1_PHY_730_DATA 0x00000000
+#define DDRSS1_PHY_731_DATA 0x00000000
+#define DDRSS1_PHY_732_DATA 0x00000000
+#define DDRSS1_PHY_733_DATA 0x00000000
+#define DDRSS1_PHY_734_DATA 0x00000000
+#define DDRSS1_PHY_735_DATA 0x00000000
+#define DDRSS1_PHY_736_DATA 0x00000000
+#define DDRSS1_PHY_737_DATA 0x00000000
+#define DDRSS1_PHY_738_DATA 0x00000000
+#define DDRSS1_PHY_739_DATA 0x00000000
+#define DDRSS1_PHY_740_DATA 0x00000000
+#define DDRSS1_PHY_741_DATA 0x00000000
+#define DDRSS1_PHY_742_DATA 0x00000000
+#define DDRSS1_PHY_743_DATA 0x00000000
+#define DDRSS1_PHY_744_DATA 0x00000000
+#define DDRSS1_PHY_745_DATA 0x00000000
+#define DDRSS1_PHY_746_DATA 0x00000000
+#define DDRSS1_PHY_747_DATA 0x00000000
+#define DDRSS1_PHY_748_DATA 0x00000000
+#define DDRSS1_PHY_749_DATA 0x00000000
+#define DDRSS1_PHY_750_DATA 0x00000000
+#define DDRSS1_PHY_751_DATA 0x00000000
+#define DDRSS1_PHY_752_DATA 0x00000000
+#define DDRSS1_PHY_753_DATA 0x00000000
+#define DDRSS1_PHY_754_DATA 0x00000000
+#define DDRSS1_PHY_755_DATA 0x00000000
+#define DDRSS1_PHY_756_DATA 0x00000000
+#define DDRSS1_PHY_757_DATA 0x00000000
+#define DDRSS1_PHY_758_DATA 0x00000000
+#define DDRSS1_PHY_759_DATA 0x00000000
+#define DDRSS1_PHY_760_DATA 0x00000000
+#define DDRSS1_PHY_761_DATA 0x00000000
+#define DDRSS1_PHY_762_DATA 0x00000000
+#define DDRSS1_PHY_763_DATA 0x00000000
+#define DDRSS1_PHY_764_DATA 0x00000000
+#define DDRSS1_PHY_765_DATA 0x00000000
+#define DDRSS1_PHY_766_DATA 0x00000000
+#define DDRSS1_PHY_767_DATA 0x00000000
+#define DDRSS1_PHY_768_DATA 0x000004F0
+#define DDRSS1_PHY_769_DATA 0x00000000
+#define DDRSS1_PHY_770_DATA 0x00030200
+#define DDRSS1_PHY_771_DATA 0x00000000
+#define DDRSS1_PHY_772_DATA 0x00000000
+#define DDRSS1_PHY_773_DATA 0x01030000
+#define DDRSS1_PHY_774_DATA 0x00010000
+#define DDRSS1_PHY_775_DATA 0x01030004
+#define DDRSS1_PHY_776_DATA 0x01000000
+#define DDRSS1_PHY_777_DATA 0x00000000
+#define DDRSS1_PHY_778_DATA 0x00000000
+#define DDRSS1_PHY_779_DATA 0x01000001
+#define DDRSS1_PHY_780_DATA 0x00000100
+#define DDRSS1_PHY_781_DATA 0x000800C0
+#define DDRSS1_PHY_782_DATA 0x060100CC
+#define DDRSS1_PHY_783_DATA 0x00030066
+#define DDRSS1_PHY_784_DATA 0x00000000
+#define DDRSS1_PHY_785_DATA 0x00000301
+#define DDRSS1_PHY_786_DATA 0x0000AAAA
+#define DDRSS1_PHY_787_DATA 0x00005555
+#define DDRSS1_PHY_788_DATA 0x0000B5B5
+#define DDRSS1_PHY_789_DATA 0x00004A4A
+#define DDRSS1_PHY_790_DATA 0x00005656
+#define DDRSS1_PHY_791_DATA 0x0000A9A9
+#define DDRSS1_PHY_792_DATA 0x0000A9A9
+#define DDRSS1_PHY_793_DATA 0x0000B5B5
+#define DDRSS1_PHY_794_DATA 0x00000000
+#define DDRSS1_PHY_795_DATA 0x00000000
+#define DDRSS1_PHY_796_DATA 0x2A000000
+#define DDRSS1_PHY_797_DATA 0x00000808
+#define DDRSS1_PHY_798_DATA 0x0F000000
+#define DDRSS1_PHY_799_DATA 0x00000F0F
+#define DDRSS1_PHY_800_DATA 0x10400000
+#define DDRSS1_PHY_801_DATA 0x0C002006
+#define DDRSS1_PHY_802_DATA 0x00000000
+#define DDRSS1_PHY_803_DATA 0x00000000
+#define DDRSS1_PHY_804_DATA 0x55555555
+#define DDRSS1_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_806_DATA 0x55555555
+#define DDRSS1_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_808_DATA 0x00005555
+#define DDRSS1_PHY_809_DATA 0x01000100
+#define DDRSS1_PHY_810_DATA 0x00800180
+#define DDRSS1_PHY_811_DATA 0x00000000
+#define DDRSS1_PHY_812_DATA 0x00000000
+#define DDRSS1_PHY_813_DATA 0x00000000
+#define DDRSS1_PHY_814_DATA 0x00000000
+#define DDRSS1_PHY_815_DATA 0x00000000
+#define DDRSS1_PHY_816_DATA 0x00000000
+#define DDRSS1_PHY_817_DATA 0x00000000
+#define DDRSS1_PHY_818_DATA 0x00000000
+#define DDRSS1_PHY_819_DATA 0x00000000
+#define DDRSS1_PHY_820_DATA 0x00000000
+#define DDRSS1_PHY_821_DATA 0x00000000
+#define DDRSS1_PHY_822_DATA 0x00000000
+#define DDRSS1_PHY_823_DATA 0x00000000
+#define DDRSS1_PHY_824_DATA 0x00000000
+#define DDRSS1_PHY_825_DATA 0x00000000
+#define DDRSS1_PHY_826_DATA 0x00000000
+#define DDRSS1_PHY_827_DATA 0x00000000
+#define DDRSS1_PHY_828_DATA 0x00000000
+#define DDRSS1_PHY_829_DATA 0x00000000
+#define DDRSS1_PHY_830_DATA 0x00000000
+#define DDRSS1_PHY_831_DATA 0x00000000
+#define DDRSS1_PHY_832_DATA 0x00000000
+#define DDRSS1_PHY_833_DATA 0x00000000
+#define DDRSS1_PHY_834_DATA 0x00000104
+#define DDRSS1_PHY_835_DATA 0x00000120
+#define DDRSS1_PHY_836_DATA 0x00000000
+#define DDRSS1_PHY_837_DATA 0x00000000
+#define DDRSS1_PHY_838_DATA 0x00000000
+#define DDRSS1_PHY_839_DATA 0x00000000
+#define DDRSS1_PHY_840_DATA 0x00000000
+#define DDRSS1_PHY_841_DATA 0x00000000
+#define DDRSS1_PHY_842_DATA 0x00000000
+#define DDRSS1_PHY_843_DATA 0x00000001
+#define DDRSS1_PHY_844_DATA 0x07FF0000
+#define DDRSS1_PHY_845_DATA 0x0080081F
+#define DDRSS1_PHY_846_DATA 0x00081020
+#define DDRSS1_PHY_847_DATA 0x04010000
+#define DDRSS1_PHY_848_DATA 0x00000000
+#define DDRSS1_PHY_849_DATA 0x00000000
+#define DDRSS1_PHY_850_DATA 0x00000000
+#define DDRSS1_PHY_851_DATA 0x00000100
+#define DDRSS1_PHY_852_DATA 0x01CC0C01
+#define DDRSS1_PHY_853_DATA 0x1003CC0C
+#define DDRSS1_PHY_854_DATA 0x20000140
+#define DDRSS1_PHY_855_DATA 0x07FF0200
+#define DDRSS1_PHY_856_DATA 0x0000DD01
+#define DDRSS1_PHY_857_DATA 0x10100303
+#define DDRSS1_PHY_858_DATA 0x10101010
+#define DDRSS1_PHY_859_DATA 0x10101010
+#define DDRSS1_PHY_860_DATA 0x00021010
+#define DDRSS1_PHY_861_DATA 0x00100010
+#define DDRSS1_PHY_862_DATA 0x00100010
+#define DDRSS1_PHY_863_DATA 0x00100010
+#define DDRSS1_PHY_864_DATA 0x00100010
+#define DDRSS1_PHY_865_DATA 0x00050010
+#define DDRSS1_PHY_866_DATA 0x51517041
+#define DDRSS1_PHY_867_DATA 0x31C06001
+#define DDRSS1_PHY_868_DATA 0x07AB0340
+#define DDRSS1_PHY_869_DATA 0x00C0C001
+#define DDRSS1_PHY_870_DATA 0x0E0D0001
+#define DDRSS1_PHY_871_DATA 0x10001000
+#define DDRSS1_PHY_872_DATA 0x0C083E42
+#define DDRSS1_PHY_873_DATA 0x0F0C3701
+#define DDRSS1_PHY_874_DATA 0x01000140
+#define DDRSS1_PHY_875_DATA 0x0C000420
+#define DDRSS1_PHY_876_DATA 0x00000198
+#define DDRSS1_PHY_877_DATA 0x0A0000D0
+#define DDRSS1_PHY_878_DATA 0x00030200
+#define DDRSS1_PHY_879_DATA 0x02800000
+#define DDRSS1_PHY_880_DATA 0x80800000
+#define DDRSS1_PHY_881_DATA 0x000E2010
+#define DDRSS1_PHY_882_DATA 0x76543210
+#define DDRSS1_PHY_883_DATA 0x00000008
+#define DDRSS1_PHY_884_DATA 0x02800280
+#define DDRSS1_PHY_885_DATA 0x02800280
+#define DDRSS1_PHY_886_DATA 0x02800280
+#define DDRSS1_PHY_887_DATA 0x02800280
+#define DDRSS1_PHY_888_DATA 0x00000280
+#define DDRSS1_PHY_889_DATA 0x0000A000
+#define DDRSS1_PHY_890_DATA 0x00A000A0
+#define DDRSS1_PHY_891_DATA 0x00A000A0
+#define DDRSS1_PHY_892_DATA 0x00A000A0
+#define DDRSS1_PHY_893_DATA 0x00A000A0
+#define DDRSS1_PHY_894_DATA 0x00A000A0
+#define DDRSS1_PHY_895_DATA 0x00A000A0
+#define DDRSS1_PHY_896_DATA 0x00A000A0
+#define DDRSS1_PHY_897_DATA 0x00A000A0
+#define DDRSS1_PHY_898_DATA 0x01C200A0
+#define DDRSS1_PHY_899_DATA 0x01A00005
+#define DDRSS1_PHY_900_DATA 0x00000000
+#define DDRSS1_PHY_901_DATA 0x00000000
+#define DDRSS1_PHY_902_DATA 0x00080200
+#define DDRSS1_PHY_903_DATA 0x00000000
+#define DDRSS1_PHY_904_DATA 0x20202000
+#define DDRSS1_PHY_905_DATA 0x20202020
+#define DDRSS1_PHY_906_DATA 0xF0F02020
+#define DDRSS1_PHY_907_DATA 0x00000000
+#define DDRSS1_PHY_908_DATA 0x00000000
+#define DDRSS1_PHY_909_DATA 0x00000000
+#define DDRSS1_PHY_910_DATA 0x00000000
+#define DDRSS1_PHY_911_DATA 0x00000000
+#define DDRSS1_PHY_912_DATA 0x00000000
+#define DDRSS1_PHY_913_DATA 0x00000000
+#define DDRSS1_PHY_914_DATA 0x00000000
+#define DDRSS1_PHY_915_DATA 0x00000000
+#define DDRSS1_PHY_916_DATA 0x00000000
+#define DDRSS1_PHY_917_DATA 0x00000000
+#define DDRSS1_PHY_918_DATA 0x00000000
+#define DDRSS1_PHY_919_DATA 0x00000000
+#define DDRSS1_PHY_920_DATA 0x00000000
+#define DDRSS1_PHY_921_DATA 0x00000000
+#define DDRSS1_PHY_922_DATA 0x00000000
+#define DDRSS1_PHY_923_DATA 0x00000000
+#define DDRSS1_PHY_924_DATA 0x00000000
+#define DDRSS1_PHY_925_DATA 0x00000000
+#define DDRSS1_PHY_926_DATA 0x00000000
+#define DDRSS1_PHY_927_DATA 0x00000000
+#define DDRSS1_PHY_928_DATA 0x00000000
+#define DDRSS1_PHY_929_DATA 0x00000000
+#define DDRSS1_PHY_930_DATA 0x00000000
+#define DDRSS1_PHY_931_DATA 0x00000000
+#define DDRSS1_PHY_932_DATA 0x00000000
+#define DDRSS1_PHY_933_DATA 0x00000000
+#define DDRSS1_PHY_934_DATA 0x00000000
+#define DDRSS1_PHY_935_DATA 0x00000000
+#define DDRSS1_PHY_936_DATA 0x00000000
+#define DDRSS1_PHY_937_DATA 0x00000000
+#define DDRSS1_PHY_938_DATA 0x00000000
+#define DDRSS1_PHY_939_DATA 0x00000000
+#define DDRSS1_PHY_940_DATA 0x00000000
+#define DDRSS1_PHY_941_DATA 0x00000000
+#define DDRSS1_PHY_942_DATA 0x00000000
+#define DDRSS1_PHY_943_DATA 0x00000000
+#define DDRSS1_PHY_944_DATA 0x00000000
+#define DDRSS1_PHY_945_DATA 0x00000000
+#define DDRSS1_PHY_946_DATA 0x00000000
+#define DDRSS1_PHY_947_DATA 0x00000000
+#define DDRSS1_PHY_948_DATA 0x00000000
+#define DDRSS1_PHY_949_DATA 0x00000000
+#define DDRSS1_PHY_950_DATA 0x00000000
+#define DDRSS1_PHY_951_DATA 0x00000000
+#define DDRSS1_PHY_952_DATA 0x00000000
+#define DDRSS1_PHY_953_DATA 0x00000000
+#define DDRSS1_PHY_954_DATA 0x00000000
+#define DDRSS1_PHY_955_DATA 0x00000000
+#define DDRSS1_PHY_956_DATA 0x00000000
+#define DDRSS1_PHY_957_DATA 0x00000000
+#define DDRSS1_PHY_958_DATA 0x00000000
+#define DDRSS1_PHY_959_DATA 0x00000000
+#define DDRSS1_PHY_960_DATA 0x00000000
+#define DDRSS1_PHY_961_DATA 0x00000000
+#define DDRSS1_PHY_962_DATA 0x00000000
+#define DDRSS1_PHY_963_DATA 0x00000000
+#define DDRSS1_PHY_964_DATA 0x00000000
+#define DDRSS1_PHY_965_DATA 0x00000000
+#define DDRSS1_PHY_966_DATA 0x00000000
+#define DDRSS1_PHY_967_DATA 0x00000000
+#define DDRSS1_PHY_968_DATA 0x00000000
+#define DDRSS1_PHY_969_DATA 0x00000000
+#define DDRSS1_PHY_970_DATA 0x00000000
+#define DDRSS1_PHY_971_DATA 0x00000000
+#define DDRSS1_PHY_972_DATA 0x00000000
+#define DDRSS1_PHY_973_DATA 0x00000000
+#define DDRSS1_PHY_974_DATA 0x00000000
+#define DDRSS1_PHY_975_DATA 0x00000000
+#define DDRSS1_PHY_976_DATA 0x00000000
+#define DDRSS1_PHY_977_DATA 0x00000000
+#define DDRSS1_PHY_978_DATA 0x00000000
+#define DDRSS1_PHY_979_DATA 0x00000000
+#define DDRSS1_PHY_980_DATA 0x00000000
+#define DDRSS1_PHY_981_DATA 0x00000000
+#define DDRSS1_PHY_982_DATA 0x00000000
+#define DDRSS1_PHY_983_DATA 0x00000000
+#define DDRSS1_PHY_984_DATA 0x00000000
+#define DDRSS1_PHY_985_DATA 0x00000000
+#define DDRSS1_PHY_986_DATA 0x00000000
+#define DDRSS1_PHY_987_DATA 0x00000000
+#define DDRSS1_PHY_988_DATA 0x00000000
+#define DDRSS1_PHY_989_DATA 0x00000000
+#define DDRSS1_PHY_990_DATA 0x00000000
+#define DDRSS1_PHY_991_DATA 0x00000000
+#define DDRSS1_PHY_992_DATA 0x00000000
+#define DDRSS1_PHY_993_DATA 0x00000000
+#define DDRSS1_PHY_994_DATA 0x00000000
+#define DDRSS1_PHY_995_DATA 0x00000000
+#define DDRSS1_PHY_996_DATA 0x00000000
+#define DDRSS1_PHY_997_DATA 0x00000000
+#define DDRSS1_PHY_998_DATA 0x00000000
+#define DDRSS1_PHY_999_DATA 0x00000000
+#define DDRSS1_PHY_1000_DATA 0x00000000
+#define DDRSS1_PHY_1001_DATA 0x00000000
+#define DDRSS1_PHY_1002_DATA 0x00000000
+#define DDRSS1_PHY_1003_DATA 0x00000000
+#define DDRSS1_PHY_1004_DATA 0x00000000
+#define DDRSS1_PHY_1005_DATA 0x00000000
+#define DDRSS1_PHY_1006_DATA 0x00000000
+#define DDRSS1_PHY_1007_DATA 0x00000000
+#define DDRSS1_PHY_1008_DATA 0x00000000
+#define DDRSS1_PHY_1009_DATA 0x00000000
+#define DDRSS1_PHY_1010_DATA 0x00000000
+#define DDRSS1_PHY_1011_DATA 0x00000000
+#define DDRSS1_PHY_1012_DATA 0x00000000
+#define DDRSS1_PHY_1013_DATA 0x00000000
+#define DDRSS1_PHY_1014_DATA 0x00000000
+#define DDRSS1_PHY_1015_DATA 0x00000000
+#define DDRSS1_PHY_1016_DATA 0x00000000
+#define DDRSS1_PHY_1017_DATA 0x00000000
+#define DDRSS1_PHY_1018_DATA 0x00000000
+#define DDRSS1_PHY_1019_DATA 0x00000000
+#define DDRSS1_PHY_1020_DATA 0x00000000
+#define DDRSS1_PHY_1021_DATA 0x00000000
+#define DDRSS1_PHY_1022_DATA 0x00000000
+#define DDRSS1_PHY_1023_DATA 0x00000000
+#define DDRSS1_PHY_1024_DATA 0x00000000
+#define DDRSS1_PHY_1025_DATA 0x00000000
+#define DDRSS1_PHY_1026_DATA 0x00000000
+#define DDRSS1_PHY_1027_DATA 0x00000000
+#define DDRSS1_PHY_1028_DATA 0x00000000
+#define DDRSS1_PHY_1029_DATA 0x00000100
+#define DDRSS1_PHY_1030_DATA 0x00000200
+#define DDRSS1_PHY_1031_DATA 0x00000000
+#define DDRSS1_PHY_1032_DATA 0x00000000
+#define DDRSS1_PHY_1033_DATA 0x00000000
+#define DDRSS1_PHY_1034_DATA 0x00000000
+#define DDRSS1_PHY_1035_DATA 0x00400000
+#define DDRSS1_PHY_1036_DATA 0x00000080
+#define DDRSS1_PHY_1037_DATA 0x00DCBA98
+#define DDRSS1_PHY_1038_DATA 0x03000000
+#define DDRSS1_PHY_1039_DATA 0x00200000
+#define DDRSS1_PHY_1040_DATA 0x00000000
+#define DDRSS1_PHY_1041_DATA 0x00000000
+#define DDRSS1_PHY_1042_DATA 0x00000000
+#define DDRSS1_PHY_1043_DATA 0x00000000
+#define DDRSS1_PHY_1044_DATA 0x00000000
+#define DDRSS1_PHY_1045_DATA 0x0000002A
+#define DDRSS1_PHY_1046_DATA 0x00000015
+#define DDRSS1_PHY_1047_DATA 0x00000015
+#define DDRSS1_PHY_1048_DATA 0x0000002A
+#define DDRSS1_PHY_1049_DATA 0x00000033
+#define DDRSS1_PHY_1050_DATA 0x0000000C
+#define DDRSS1_PHY_1051_DATA 0x0000000C
+#define DDRSS1_PHY_1052_DATA 0x00000033
+#define DDRSS1_PHY_1053_DATA 0x00543210
+#define DDRSS1_PHY_1054_DATA 0x003F0000
+#define DDRSS1_PHY_1055_DATA 0x000F013F
+#define DDRSS1_PHY_1056_DATA 0x20202003
+#define DDRSS1_PHY_1057_DATA 0x00202020
+#define DDRSS1_PHY_1058_DATA 0x20008008
+#define DDRSS1_PHY_1059_DATA 0x00000810
+#define DDRSS1_PHY_1060_DATA 0x00000F00
+#define DDRSS1_PHY_1061_DATA 0x00000000
+#define DDRSS1_PHY_1062_DATA 0x00000000
+#define DDRSS1_PHY_1063_DATA 0x00000000
+#define DDRSS1_PHY_1064_DATA 0x000305CC
+#define DDRSS1_PHY_1065_DATA 0x00030000
+#define DDRSS1_PHY_1066_DATA 0x00000300
+#define DDRSS1_PHY_1067_DATA 0x00000300
+#define DDRSS1_PHY_1068_DATA 0x00000300
+#define DDRSS1_PHY_1069_DATA 0x00000300
+#define DDRSS1_PHY_1070_DATA 0x00000300
+#define DDRSS1_PHY_1071_DATA 0x42080010
+#define DDRSS1_PHY_1072_DATA 0x0000803E
+#define DDRSS1_PHY_1073_DATA 0x00000001
+#define DDRSS1_PHY_1074_DATA 0x01000102
+#define DDRSS1_PHY_1075_DATA 0x00008000
+#define DDRSS1_PHY_1076_DATA 0x00000000
+#define DDRSS1_PHY_1077_DATA 0x00000000
+#define DDRSS1_PHY_1078_DATA 0x00000000
+#define DDRSS1_PHY_1079_DATA 0x00000000
+#define DDRSS1_PHY_1080_DATA 0x00000000
+#define DDRSS1_PHY_1081_DATA 0x00000000
+#define DDRSS1_PHY_1082_DATA 0x00000000
+#define DDRSS1_PHY_1083_DATA 0x00000000
+#define DDRSS1_PHY_1084_DATA 0x00000000
+#define DDRSS1_PHY_1085_DATA 0x00000000
+#define DDRSS1_PHY_1086_DATA 0x00000000
+#define DDRSS1_PHY_1087_DATA 0x00000000
+#define DDRSS1_PHY_1088_DATA 0x00000000
+#define DDRSS1_PHY_1089_DATA 0x00000000
+#define DDRSS1_PHY_1090_DATA 0x00000000
+#define DDRSS1_PHY_1091_DATA 0x00000000
+#define DDRSS1_PHY_1092_DATA 0x00000000
+#define DDRSS1_PHY_1093_DATA 0x00000000
+#define DDRSS1_PHY_1094_DATA 0x00000000
+#define DDRSS1_PHY_1095_DATA 0x00000000
+#define DDRSS1_PHY_1096_DATA 0x00000000
+#define DDRSS1_PHY_1097_DATA 0x00000000
+#define DDRSS1_PHY_1098_DATA 0x00000000
+#define DDRSS1_PHY_1099_DATA 0x00000000
+#define DDRSS1_PHY_1100_DATA 0x00000000
+#define DDRSS1_PHY_1101_DATA 0x00000000
+#define DDRSS1_PHY_1102_DATA 0x00000000
+#define DDRSS1_PHY_1103_DATA 0x00000000
+#define DDRSS1_PHY_1104_DATA 0x00000000
+#define DDRSS1_PHY_1105_DATA 0x00000000
+#define DDRSS1_PHY_1106_DATA 0x00000000
+#define DDRSS1_PHY_1107_DATA 0x00000000
+#define DDRSS1_PHY_1108_DATA 0x00000000
+#define DDRSS1_PHY_1109_DATA 0x00000000
+#define DDRSS1_PHY_1110_DATA 0x00000000
+#define DDRSS1_PHY_1111_DATA 0x00000000
+#define DDRSS1_PHY_1112_DATA 0x00000000
+#define DDRSS1_PHY_1113_DATA 0x00000000
+#define DDRSS1_PHY_1114_DATA 0x00000000
+#define DDRSS1_PHY_1115_DATA 0x00000000
+#define DDRSS1_PHY_1116_DATA 0x00000000
+#define DDRSS1_PHY_1117_DATA 0x00000000
+#define DDRSS1_PHY_1118_DATA 0x00000000
+#define DDRSS1_PHY_1119_DATA 0x00000000
+#define DDRSS1_PHY_1120_DATA 0x00000000
+#define DDRSS1_PHY_1121_DATA 0x00000000
+#define DDRSS1_PHY_1122_DATA 0x00000000
+#define DDRSS1_PHY_1123_DATA 0x00000000
+#define DDRSS1_PHY_1124_DATA 0x00000000
+#define DDRSS1_PHY_1125_DATA 0x00000000
+#define DDRSS1_PHY_1126_DATA 0x00000000
+#define DDRSS1_PHY_1127_DATA 0x00000000
+#define DDRSS1_PHY_1128_DATA 0x00000000
+#define DDRSS1_PHY_1129_DATA 0x00000000
+#define DDRSS1_PHY_1130_DATA 0x00000000
+#define DDRSS1_PHY_1131_DATA 0x00000000
+#define DDRSS1_PHY_1132_DATA 0x00000000
+#define DDRSS1_PHY_1133_DATA 0x00000000
+#define DDRSS1_PHY_1134_DATA 0x00000000
+#define DDRSS1_PHY_1135_DATA 0x00000000
+#define DDRSS1_PHY_1136_DATA 0x00000000
+#define DDRSS1_PHY_1137_DATA 0x00000000
+#define DDRSS1_PHY_1138_DATA 0x00000000
+#define DDRSS1_PHY_1139_DATA 0x00000000
+#define DDRSS1_PHY_1140_DATA 0x00000000
+#define DDRSS1_PHY_1141_DATA 0x00000000
+#define DDRSS1_PHY_1142_DATA 0x00000000
+#define DDRSS1_PHY_1143_DATA 0x00000000
+#define DDRSS1_PHY_1144_DATA 0x00000000
+#define DDRSS1_PHY_1145_DATA 0x00000000
+#define DDRSS1_PHY_1146_DATA 0x00000000
+#define DDRSS1_PHY_1147_DATA 0x00000000
+#define DDRSS1_PHY_1148_DATA 0x00000000
+#define DDRSS1_PHY_1149_DATA 0x00000000
+#define DDRSS1_PHY_1150_DATA 0x00000000
+#define DDRSS1_PHY_1151_DATA 0x00000000
+#define DDRSS1_PHY_1152_DATA 0x00000000
+#define DDRSS1_PHY_1153_DATA 0x00000000
+#define DDRSS1_PHY_1154_DATA 0x00000000
+#define DDRSS1_PHY_1155_DATA 0x00000000
+#define DDRSS1_PHY_1156_DATA 0x00000000
+#define DDRSS1_PHY_1157_DATA 0x00000000
+#define DDRSS1_PHY_1158_DATA 0x00000000
+#define DDRSS1_PHY_1159_DATA 0x00000000
+#define DDRSS1_PHY_1160_DATA 0x00000000
+#define DDRSS1_PHY_1161_DATA 0x00000000
+#define DDRSS1_PHY_1162_DATA 0x00000000
+#define DDRSS1_PHY_1163_DATA 0x00000000
+#define DDRSS1_PHY_1164_DATA 0x00000000
+#define DDRSS1_PHY_1165_DATA 0x00000000
+#define DDRSS1_PHY_1166_DATA 0x00000000
+#define DDRSS1_PHY_1167_DATA 0x00000000
+#define DDRSS1_PHY_1168_DATA 0x00000000
+#define DDRSS1_PHY_1169_DATA 0x00000000
+#define DDRSS1_PHY_1170_DATA 0x00000000
+#define DDRSS1_PHY_1171_DATA 0x00000000
+#define DDRSS1_PHY_1172_DATA 0x00000000
+#define DDRSS1_PHY_1173_DATA 0x00000000
+#define DDRSS1_PHY_1174_DATA 0x00000000
+#define DDRSS1_PHY_1175_DATA 0x00000000
+#define DDRSS1_PHY_1176_DATA 0x00000000
+#define DDRSS1_PHY_1177_DATA 0x00000000
+#define DDRSS1_PHY_1178_DATA 0x00000000
+#define DDRSS1_PHY_1179_DATA 0x00000000
+#define DDRSS1_PHY_1180_DATA 0x00000000
+#define DDRSS1_PHY_1181_DATA 0x00000000
+#define DDRSS1_PHY_1182_DATA 0x00000000
+#define DDRSS1_PHY_1183_DATA 0x00000000
+#define DDRSS1_PHY_1184_DATA 0x00000000
+#define DDRSS1_PHY_1185_DATA 0x00000000
+#define DDRSS1_PHY_1186_DATA 0x00000000
+#define DDRSS1_PHY_1187_DATA 0x00000000
+#define DDRSS1_PHY_1188_DATA 0x00000000
+#define DDRSS1_PHY_1189_DATA 0x00000000
+#define DDRSS1_PHY_1190_DATA 0x00000000
+#define DDRSS1_PHY_1191_DATA 0x00000000
+#define DDRSS1_PHY_1192_DATA 0x00000000
+#define DDRSS1_PHY_1193_DATA 0x00000000
+#define DDRSS1_PHY_1194_DATA 0x00000000
+#define DDRSS1_PHY_1195_DATA 0x00000000
+#define DDRSS1_PHY_1196_DATA 0x00000000
+#define DDRSS1_PHY_1197_DATA 0x00000000
+#define DDRSS1_PHY_1198_DATA 0x00000000
+#define DDRSS1_PHY_1199_DATA 0x00000000
+#define DDRSS1_PHY_1200_DATA 0x00000000
+#define DDRSS1_PHY_1201_DATA 0x00000000
+#define DDRSS1_PHY_1202_DATA 0x00000000
+#define DDRSS1_PHY_1203_DATA 0x00000000
+#define DDRSS1_PHY_1204_DATA 0x00000000
+#define DDRSS1_PHY_1205_DATA 0x00000000
+#define DDRSS1_PHY_1206_DATA 0x00000000
+#define DDRSS1_PHY_1207_DATA 0x00000000
+#define DDRSS1_PHY_1208_DATA 0x00000000
+#define DDRSS1_PHY_1209_DATA 0x00000000
+#define DDRSS1_PHY_1210_DATA 0x00000000
+#define DDRSS1_PHY_1211_DATA 0x00000000
+#define DDRSS1_PHY_1212_DATA 0x00000000
+#define DDRSS1_PHY_1213_DATA 0x00000000
+#define DDRSS1_PHY_1214_DATA 0x00000000
+#define DDRSS1_PHY_1215_DATA 0x00000000
+#define DDRSS1_PHY_1216_DATA 0x00000000
+#define DDRSS1_PHY_1217_DATA 0x00000000
+#define DDRSS1_PHY_1218_DATA 0x00000000
+#define DDRSS1_PHY_1219_DATA 0x00000000
+#define DDRSS1_PHY_1220_DATA 0x00000000
+#define DDRSS1_PHY_1221_DATA 0x00000000
+#define DDRSS1_PHY_1222_DATA 0x00000000
+#define DDRSS1_PHY_1223_DATA 0x00000000
+#define DDRSS1_PHY_1224_DATA 0x00000000
+#define DDRSS1_PHY_1225_DATA 0x00000000
+#define DDRSS1_PHY_1226_DATA 0x00000000
+#define DDRSS1_PHY_1227_DATA 0x00000000
+#define DDRSS1_PHY_1228_DATA 0x00000000
+#define DDRSS1_PHY_1229_DATA 0x00000000
+#define DDRSS1_PHY_1230_DATA 0x00000000
+#define DDRSS1_PHY_1231_DATA 0x00000000
+#define DDRSS1_PHY_1232_DATA 0x00000000
+#define DDRSS1_PHY_1233_DATA 0x00000000
+#define DDRSS1_PHY_1234_DATA 0x00000000
+#define DDRSS1_PHY_1235_DATA 0x00000000
+#define DDRSS1_PHY_1236_DATA 0x00000000
+#define DDRSS1_PHY_1237_DATA 0x00000000
+#define DDRSS1_PHY_1238_DATA 0x00000000
+#define DDRSS1_PHY_1239_DATA 0x00000000
+#define DDRSS1_PHY_1240_DATA 0x00000000
+#define DDRSS1_PHY_1241_DATA 0x00000000
+#define DDRSS1_PHY_1242_DATA 0x00000000
+#define DDRSS1_PHY_1243_DATA 0x00000000
+#define DDRSS1_PHY_1244_DATA 0x00000000
+#define DDRSS1_PHY_1245_DATA 0x00000000
+#define DDRSS1_PHY_1246_DATA 0x00000000
+#define DDRSS1_PHY_1247_DATA 0x00000000
+#define DDRSS1_PHY_1248_DATA 0x00000000
+#define DDRSS1_PHY_1249_DATA 0x00000000
+#define DDRSS1_PHY_1250_DATA 0x00000000
+#define DDRSS1_PHY_1251_DATA 0x00000000
+#define DDRSS1_PHY_1252_DATA 0x00000000
+#define DDRSS1_PHY_1253_DATA 0x00000000
+#define DDRSS1_PHY_1254_DATA 0x00000000
+#define DDRSS1_PHY_1255_DATA 0x00000000
+#define DDRSS1_PHY_1256_DATA 0x00000000
+#define DDRSS1_PHY_1257_DATA 0x00000000
+#define DDRSS1_PHY_1258_DATA 0x00000000
+#define DDRSS1_PHY_1259_DATA 0x00000000
+#define DDRSS1_PHY_1260_DATA 0x00000000
+#define DDRSS1_PHY_1261_DATA 0x00000000
+#define DDRSS1_PHY_1262_DATA 0x00000000
+#define DDRSS1_PHY_1263_DATA 0x00000000
+#define DDRSS1_PHY_1264_DATA 0x00000000
+#define DDRSS1_PHY_1265_DATA 0x00000000
+#define DDRSS1_PHY_1266_DATA 0x00000000
+#define DDRSS1_PHY_1267_DATA 0x00000000
+#define DDRSS1_PHY_1268_DATA 0x00000000
+#define DDRSS1_PHY_1269_DATA 0x00000000
+#define DDRSS1_PHY_1270_DATA 0x00000000
+#define DDRSS1_PHY_1271_DATA 0x00000000
+#define DDRSS1_PHY_1272_DATA 0x00000000
+#define DDRSS1_PHY_1273_DATA 0x00000000
+#define DDRSS1_PHY_1274_DATA 0x00000000
+#define DDRSS1_PHY_1275_DATA 0x00000000
+#define DDRSS1_PHY_1276_DATA 0x00000000
+#define DDRSS1_PHY_1277_DATA 0x00000000
+#define DDRSS1_PHY_1278_DATA 0x00000000
+#define DDRSS1_PHY_1279_DATA 0x00000000
+#define DDRSS1_PHY_1280_DATA 0x00000000
+#define DDRSS1_PHY_1281_DATA 0x00010100
+#define DDRSS1_PHY_1282_DATA 0x00000000
+#define DDRSS1_PHY_1283_DATA 0x00000000
+#define DDRSS1_PHY_1284_DATA 0x00050000
+#define DDRSS1_PHY_1285_DATA 0x04000000
+#define DDRSS1_PHY_1286_DATA 0x00000055
+#define DDRSS1_PHY_1287_DATA 0x00000000
+#define DDRSS1_PHY_1288_DATA 0x00000000
+#define DDRSS1_PHY_1289_DATA 0x00000000
+#define DDRSS1_PHY_1290_DATA 0x00000000
+#define DDRSS1_PHY_1291_DATA 0x00002001
+#define DDRSS1_PHY_1292_DATA 0x0000400F
+#define DDRSS1_PHY_1293_DATA 0x50020028
+#define DDRSS1_PHY_1294_DATA 0x01010000
+#define DDRSS1_PHY_1295_DATA 0x80080001
+#define DDRSS1_PHY_1296_DATA 0x10200000
+#define DDRSS1_PHY_1297_DATA 0x00000008
+#define DDRSS1_PHY_1298_DATA 0x00000000
+#define DDRSS1_PHY_1299_DATA 0x01090E00
+#define DDRSS1_PHY_1300_DATA 0x00040101
+#define DDRSS1_PHY_1301_DATA 0x0000010F
+#define DDRSS1_PHY_1302_DATA 0x00000000
+#define DDRSS1_PHY_1303_DATA 0x0000FFFF
+#define DDRSS1_PHY_1304_DATA 0x00000000
+#define DDRSS1_PHY_1305_DATA 0x01010000
+#define DDRSS1_PHY_1306_DATA 0x01080402
+#define DDRSS1_PHY_1307_DATA 0x01200F02
+#define DDRSS1_PHY_1308_DATA 0x00194280
+#define DDRSS1_PHY_1309_DATA 0x00000004
+#define DDRSS1_PHY_1310_DATA 0x00042000
+#define DDRSS1_PHY_1311_DATA 0x00000000
+#define DDRSS1_PHY_1312_DATA 0x00000000
+#define DDRSS1_PHY_1313_DATA 0x00000000
+#define DDRSS1_PHY_1314_DATA 0x00000000
+#define DDRSS1_PHY_1315_DATA 0x00000000
+#define DDRSS1_PHY_1316_DATA 0x00000000
+#define DDRSS1_PHY_1317_DATA 0x01000000
+#define DDRSS1_PHY_1318_DATA 0x00000705
+#define DDRSS1_PHY_1319_DATA 0x00000054
+#define DDRSS1_PHY_1320_DATA 0x00030820
+#define DDRSS1_PHY_1321_DATA 0x00010820
+#define DDRSS1_PHY_1322_DATA 0x00010820
+#define DDRSS1_PHY_1323_DATA 0x00010820
+#define DDRSS1_PHY_1324_DATA 0x00010820
+#define DDRSS1_PHY_1325_DATA 0x00010820
+#define DDRSS1_PHY_1326_DATA 0x00010820
+#define DDRSS1_PHY_1327_DATA 0x00010820
+#define DDRSS1_PHY_1328_DATA 0x00010820
+#define DDRSS1_PHY_1329_DATA 0x00000000
+#define DDRSS1_PHY_1330_DATA 0x00000074
+#define DDRSS1_PHY_1331_DATA 0x00000400
+#define DDRSS1_PHY_1332_DATA 0x00000108
+#define DDRSS1_PHY_1333_DATA 0x00000000
+#define DDRSS1_PHY_1334_DATA 0x00000000
+#define DDRSS1_PHY_1335_DATA 0x00000000
+#define DDRSS1_PHY_1336_DATA 0x00000000
+#define DDRSS1_PHY_1337_DATA 0x00000000
+#define DDRSS1_PHY_1338_DATA 0x03000000
+#define DDRSS1_PHY_1339_DATA 0x00000000
+#define DDRSS1_PHY_1340_DATA 0x00000000
+#define DDRSS1_PHY_1341_DATA 0x00000000
+#define DDRSS1_PHY_1342_DATA 0x04102006
+#define DDRSS1_PHY_1343_DATA 0x00041020
+#define DDRSS1_PHY_1344_DATA 0x01C98C98
+#define DDRSS1_PHY_1345_DATA 0x3F400000
+#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS1_PHY_1347_DATA 0x0000001F
+#define DDRSS1_PHY_1348_DATA 0x00000000
+#define DDRSS1_PHY_1349_DATA 0x00000000
+#define DDRSS1_PHY_1350_DATA 0x00000000
+#define DDRSS1_PHY_1351_DATA 0x00010000
+#define DDRSS1_PHY_1352_DATA 0x00000000
+#define DDRSS1_PHY_1353_DATA 0x00000000
+#define DDRSS1_PHY_1354_DATA 0x00000000
+#define DDRSS1_PHY_1355_DATA 0x00000000
+#define DDRSS1_PHY_1356_DATA 0x76543210
+#define DDRSS1_PHY_1357_DATA 0x00010198
+#define DDRSS1_PHY_1358_DATA 0x00000000
+#define DDRSS1_PHY_1359_DATA 0x00000000
+#define DDRSS1_PHY_1360_DATA 0x00000000
+#define DDRSS1_PHY_1361_DATA 0x00040700
+#define DDRSS1_PHY_1362_DATA 0x00000000
+#define DDRSS1_PHY_1363_DATA 0x00000000
+#define DDRSS1_PHY_1364_DATA 0x00000000
+#define DDRSS1_PHY_1365_DATA 0x00000000
+#define DDRSS1_PHY_1366_DATA 0x00000000
+#define DDRSS1_PHY_1367_DATA 0x00000002
+#define DDRSS1_PHY_1368_DATA 0x00000000
+#define DDRSS1_PHY_1369_DATA 0x00000000
+#define DDRSS1_PHY_1370_DATA 0x00000000
+#define DDRSS1_PHY_1371_DATA 0x00000000
+#define DDRSS1_PHY_1372_DATA 0x00000000
+#define DDRSS1_PHY_1373_DATA 0x00000000
+#define DDRSS1_PHY_1374_DATA 0x00080000
+#define DDRSS1_PHY_1375_DATA 0x000007FF
+#define DDRSS1_PHY_1376_DATA 0x00000000
+#define DDRSS1_PHY_1377_DATA 0x00000000
+#define DDRSS1_PHY_1378_DATA 0x00000000
+#define DDRSS1_PHY_1379_DATA 0x00000000
+#define DDRSS1_PHY_1380_DATA 0x00000000
+#define DDRSS1_PHY_1381_DATA 0x00000000
+#define DDRSS1_PHY_1382_DATA 0x000FFFFF
+#define DDRSS1_PHY_1383_DATA 0x000FFFFF
+#define DDRSS1_PHY_1384_DATA 0x0000FFFF
+#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS1_PHY_1386_DATA 0x030FFFFF
+#define DDRSS1_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS1_PHY_1388_DATA 0x0000FFFF
+#define DDRSS1_PHY_1389_DATA 0x00000000
+#define DDRSS1_PHY_1390_DATA 0x00000000
+#define DDRSS1_PHY_1391_DATA 0x00000000
+#define DDRSS1_PHY_1392_DATA 0x00000000
+#define DDRSS1_PHY_1393_DATA 0x0001F7C0
+#define DDRSS1_PHY_1394_DATA 0x00000003
+#define DDRSS1_PHY_1395_DATA 0x00000000
+#define DDRSS1_PHY_1396_DATA 0x00001142
+#define DDRSS1_PHY_1397_DATA 0x010207AB
+#define DDRSS1_PHY_1398_DATA 0x01000080
+#define DDRSS1_PHY_1399_DATA 0x03900390
+#define DDRSS1_PHY_1400_DATA 0x03900390
+#define DDRSS1_PHY_1401_DATA 0x00000390
+#define DDRSS1_PHY_1402_DATA 0x00000390
+#define DDRSS1_PHY_1403_DATA 0x00000390
+#define DDRSS1_PHY_1404_DATA 0x00000390
+#define DDRSS1_PHY_1405_DATA 0x00000005
+#define DDRSS1_PHY_1406_DATA 0x01813FCC
+#define DDRSS1_PHY_1407_DATA 0x000000CC
+#define DDRSS1_PHY_1408_DATA 0x0C000DFF
+#define DDRSS1_PHY_1409_DATA 0x30000DFF
+#define DDRSS1_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1411_DATA 0x000100F0
+#define DDRSS1_PHY_1412_DATA 0x780DFFCC
+#define DDRSS1_PHY_1413_DATA 0x00007E31
+#define DDRSS1_PHY_1414_DATA 0x000CBF11
+#define DDRSS1_PHY_1415_DATA 0x01990010
+#define DDRSS1_PHY_1416_DATA 0x000CBF11
+#define DDRSS1_PHY_1417_DATA 0x01990010
+#define DDRSS1_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1419_DATA 0x00EF00F0
+#define DDRSS1_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1421_DATA 0x01FF00F0
+#define DDRSS1_PHY_1422_DATA 0x20040006
+
+#define DDRSS2_CTL_00_DATA 0x00000B00
+#define DDRSS2_CTL_01_DATA 0x00000000
+#define DDRSS2_CTL_02_DATA 0x00000000
+#define DDRSS2_CTL_03_DATA 0x00000000
+#define DDRSS2_CTL_04_DATA 0x00000000
+#define DDRSS2_CTL_05_DATA 0x00000000
+#define DDRSS2_CTL_06_DATA 0x00000000
+#define DDRSS2_CTL_07_DATA 0x00002AF8
+#define DDRSS2_CTL_08_DATA 0x0001ADAF
+#define DDRSS2_CTL_09_DATA 0x00000005
+#define DDRSS2_CTL_10_DATA 0x0000006E
+#define DDRSS2_CTL_11_DATA 0x000681C8
+#define DDRSS2_CTL_12_DATA 0x004111C9
+#define DDRSS2_CTL_13_DATA 0x00000005
+#define DDRSS2_CTL_14_DATA 0x000010A9
+#define DDRSS2_CTL_15_DATA 0x000681C8
+#define DDRSS2_CTL_16_DATA 0x004111C9
+#define DDRSS2_CTL_17_DATA 0x00000005
+#define DDRSS2_CTL_18_DATA 0x000010A9
+#define DDRSS2_CTL_19_DATA 0x01010000
+#define DDRSS2_CTL_20_DATA 0x02011001
+#define DDRSS2_CTL_21_DATA 0x02010000
+#define DDRSS2_CTL_22_DATA 0x00020100
+#define DDRSS2_CTL_23_DATA 0x0000000B
+#define DDRSS2_CTL_24_DATA 0x0000001C
+#define DDRSS2_CTL_25_DATA 0x00000000
+#define DDRSS2_CTL_26_DATA 0x00000000
+#define DDRSS2_CTL_27_DATA 0x03020200
+#define DDRSS2_CTL_28_DATA 0x00005656
+#define DDRSS2_CTL_29_DATA 0x00100000
+#define DDRSS2_CTL_30_DATA 0x00000000
+#define DDRSS2_CTL_31_DATA 0x00000000
+#define DDRSS2_CTL_32_DATA 0x00000000
+#define DDRSS2_CTL_33_DATA 0x00000000
+#define DDRSS2_CTL_34_DATA 0x040C0000
+#define DDRSS2_CTL_35_DATA 0x12481248
+#define DDRSS2_CTL_36_DATA 0x00050804
+#define DDRSS2_CTL_37_DATA 0x09040008
+#define DDRSS2_CTL_38_DATA 0x15000204
+#define DDRSS2_CTL_39_DATA 0x1760008B
+#define DDRSS2_CTL_40_DATA 0x1500422B
+#define DDRSS2_CTL_41_DATA 0x1760008B
+#define DDRSS2_CTL_42_DATA 0x2000422B
+#define DDRSS2_CTL_43_DATA 0x000A0A09
+#define DDRSS2_CTL_44_DATA 0x0400078A
+#define DDRSS2_CTL_45_DATA 0x1E161104
+#define DDRSS2_CTL_46_DATA 0x10012458
+#define DDRSS2_CTL_47_DATA 0x1E161110
+#define DDRSS2_CTL_48_DATA 0x10012458
+#define DDRSS2_CTL_49_DATA 0x02030410
+#define DDRSS2_CTL_50_DATA 0x2C040500
+#define DDRSS2_CTL_51_DATA 0x08292C29
+#define DDRSS2_CTL_52_DATA 0x14000E0A
+#define DDRSS2_CTL_53_DATA 0x04010A0A
+#define DDRSS2_CTL_54_DATA 0x01010004
+#define DDRSS2_CTL_55_DATA 0x04545408
+#define DDRSS2_CTL_56_DATA 0x04313104
+#define DDRSS2_CTL_57_DATA 0x00003131
+#define DDRSS2_CTL_58_DATA 0x00010100
+#define DDRSS2_CTL_59_DATA 0x03010000
+#define DDRSS2_CTL_60_DATA 0x00001508
+#define DDRSS2_CTL_61_DATA 0x000000CE
+#define DDRSS2_CTL_62_DATA 0x0000032B
+#define DDRSS2_CTL_63_DATA 0x00002073
+#define DDRSS2_CTL_64_DATA 0x0000032B
+#define DDRSS2_CTL_65_DATA 0x00002073
+#define DDRSS2_CTL_66_DATA 0x00000005
+#define DDRSS2_CTL_67_DATA 0x00050000
+#define DDRSS2_CTL_68_DATA 0x00CB0012
+#define DDRSS2_CTL_69_DATA 0x00CB0408
+#define DDRSS2_CTL_70_DATA 0x00400408
+#define DDRSS2_CTL_71_DATA 0x00120103
+#define DDRSS2_CTL_72_DATA 0x00100005
+#define DDRSS2_CTL_73_DATA 0x2F080010
+#define DDRSS2_CTL_74_DATA 0x0505012F
+#define DDRSS2_CTL_75_DATA 0x0401030A
+#define DDRSS2_CTL_76_DATA 0x041E100B
+#define DDRSS2_CTL_77_DATA 0x100B0401
+#define DDRSS2_CTL_78_DATA 0x0001041E
+#define DDRSS2_CTL_79_DATA 0x00160016
+#define DDRSS2_CTL_80_DATA 0x033B033B
+#define DDRSS2_CTL_81_DATA 0x033B033B
+#define DDRSS2_CTL_82_DATA 0x03050505
+#define DDRSS2_CTL_83_DATA 0x03010303
+#define DDRSS2_CTL_84_DATA 0x200B100B
+#define DDRSS2_CTL_85_DATA 0x04041004
+#define DDRSS2_CTL_86_DATA 0x200B100B
+#define DDRSS2_CTL_87_DATA 0x04041004
+#define DDRSS2_CTL_88_DATA 0x03010000
+#define DDRSS2_CTL_89_DATA 0x00010000
+#define DDRSS2_CTL_90_DATA 0x00000000
+#define DDRSS2_CTL_91_DATA 0x00000000
+#define DDRSS2_CTL_92_DATA 0x01000000
+#define DDRSS2_CTL_93_DATA 0x80104002
+#define DDRSS2_CTL_94_DATA 0x00000000
+#define DDRSS2_CTL_95_DATA 0x00040005
+#define DDRSS2_CTL_96_DATA 0x00000000
+#define DDRSS2_CTL_97_DATA 0x00050000
+#define DDRSS2_CTL_98_DATA 0x00000004
+#define DDRSS2_CTL_99_DATA 0x00000000
+#define DDRSS2_CTL_100_DATA 0x00040005
+#define DDRSS2_CTL_101_DATA 0x00000000
+#define DDRSS2_CTL_102_DATA 0x00003380
+#define DDRSS2_CTL_103_DATA 0x00003380
+#define DDRSS2_CTL_104_DATA 0x00003380
+#define DDRSS2_CTL_105_DATA 0x00003380
+#define DDRSS2_CTL_106_DATA 0x00003380
+#define DDRSS2_CTL_107_DATA 0x00000000
+#define DDRSS2_CTL_108_DATA 0x000005A2
+#define DDRSS2_CTL_109_DATA 0x00081CC0
+#define DDRSS2_CTL_110_DATA 0x00081CC0
+#define DDRSS2_CTL_111_DATA 0x00081CC0
+#define DDRSS2_CTL_112_DATA 0x00081CC0
+#define DDRSS2_CTL_113_DATA 0x00081CC0
+#define DDRSS2_CTL_114_DATA 0x00000000
+#define DDRSS2_CTL_115_DATA 0x0000E325
+#define DDRSS2_CTL_116_DATA 0x00081CC0
+#define DDRSS2_CTL_117_DATA 0x00081CC0
+#define DDRSS2_CTL_118_DATA 0x00081CC0
+#define DDRSS2_CTL_119_DATA 0x00081CC0
+#define DDRSS2_CTL_120_DATA 0x00081CC0
+#define DDRSS2_CTL_121_DATA 0x00000000
+#define DDRSS2_CTL_122_DATA 0x0000E325
+#define DDRSS2_CTL_123_DATA 0x00000000
+#define DDRSS2_CTL_124_DATA 0x00000000
+#define DDRSS2_CTL_125_DATA 0x00000000
+#define DDRSS2_CTL_126_DATA 0x00000000
+#define DDRSS2_CTL_127_DATA 0x00000000
+#define DDRSS2_CTL_128_DATA 0x00000000
+#define DDRSS2_CTL_129_DATA 0x00000000
+#define DDRSS2_CTL_130_DATA 0x00000000
+#define DDRSS2_CTL_131_DATA 0x0B030500
+#define DDRSS2_CTL_132_DATA 0x00040B04
+#define DDRSS2_CTL_133_DATA 0x0A090000
+#define DDRSS2_CTL_134_DATA 0x0A090701
+#define DDRSS2_CTL_135_DATA 0x0900000E
+#define DDRSS2_CTL_136_DATA 0x0907010A
+#define DDRSS2_CTL_137_DATA 0x00000E0A
+#define DDRSS2_CTL_138_DATA 0x07010A09
+#define DDRSS2_CTL_139_DATA 0x000E0A09
+#define DDRSS2_CTL_140_DATA 0x07000401
+#define DDRSS2_CTL_141_DATA 0x00000000
+#define DDRSS2_CTL_142_DATA 0x00000000
+#define DDRSS2_CTL_143_DATA 0x00000000
+#define DDRSS2_CTL_144_DATA 0x00000000
+#define DDRSS2_CTL_145_DATA 0x00000000
+#define DDRSS2_CTL_146_DATA 0x00000000
+#define DDRSS2_CTL_147_DATA 0x00000000
+#define DDRSS2_CTL_148_DATA 0x08080000
+#define DDRSS2_CTL_149_DATA 0x01000000
+#define DDRSS2_CTL_150_DATA 0x800000C0
+#define DDRSS2_CTL_151_DATA 0x800000C0
+#define DDRSS2_CTL_152_DATA 0x800000C0
+#define DDRSS2_CTL_153_DATA 0x00000000
+#define DDRSS2_CTL_154_DATA 0x00001500
+#define DDRSS2_CTL_155_DATA 0x00000000
+#define DDRSS2_CTL_156_DATA 0x00000001
+#define DDRSS2_CTL_157_DATA 0x00000002
+#define DDRSS2_CTL_158_DATA 0x0000100E
+#define DDRSS2_CTL_159_DATA 0x00000000
+#define DDRSS2_CTL_160_DATA 0x00000000
+#define DDRSS2_CTL_161_DATA 0x00000000
+#define DDRSS2_CTL_162_DATA 0x00000000
+#define DDRSS2_CTL_163_DATA 0x00000000
+#define DDRSS2_CTL_164_DATA 0x000B0000
+#define DDRSS2_CTL_165_DATA 0x000E0006
+#define DDRSS2_CTL_166_DATA 0x000E0404
+#define DDRSS2_CTL_167_DATA 0x00D601AB
+#define DDRSS2_CTL_168_DATA 0x10100216
+#define DDRSS2_CTL_169_DATA 0x01AB0216
+#define DDRSS2_CTL_170_DATA 0x021600D6
+#define DDRSS2_CTL_171_DATA 0x02161010
+#define DDRSS2_CTL_172_DATA 0x00000000
+#define DDRSS2_CTL_173_DATA 0x00000000
+#define DDRSS2_CTL_174_DATA 0x00000000
+#define DDRSS2_CTL_175_DATA 0x3FF40084
+#define DDRSS2_CTL_176_DATA 0x33003FF4
+#define DDRSS2_CTL_177_DATA 0x00003333
+#define DDRSS2_CTL_178_DATA 0x35000000
+#define DDRSS2_CTL_179_DATA 0x27270035
+#define DDRSS2_CTL_180_DATA 0x0F0F0000
+#define DDRSS2_CTL_181_DATA 0x16000000
+#define DDRSS2_CTL_182_DATA 0x00841616
+#define DDRSS2_CTL_183_DATA 0x3FF43FF4
+#define DDRSS2_CTL_184_DATA 0x33333300
+#define DDRSS2_CTL_185_DATA 0x00000000
+#define DDRSS2_CTL_186_DATA 0x00353500
+#define DDRSS2_CTL_187_DATA 0x00002727
+#define DDRSS2_CTL_188_DATA 0x00000F0F
+#define DDRSS2_CTL_189_DATA 0x16161600
+#define DDRSS2_CTL_190_DATA 0x00000020
+#define DDRSS2_CTL_191_DATA 0x00000000
+#define DDRSS2_CTL_192_DATA 0x00000001
+#define DDRSS2_CTL_193_DATA 0x00000000
+#define DDRSS2_CTL_194_DATA 0x01000000
+#define DDRSS2_CTL_195_DATA 0x00000001
+#define DDRSS2_CTL_196_DATA 0x00000000
+#define DDRSS2_CTL_197_DATA 0x00000000
+#define DDRSS2_CTL_198_DATA 0x00000000
+#define DDRSS2_CTL_199_DATA 0x00000000
+#define DDRSS2_CTL_200_DATA 0x00000000
+#define DDRSS2_CTL_201_DATA 0x00000000
+#define DDRSS2_CTL_202_DATA 0x00000000
+#define DDRSS2_CTL_203_DATA 0x00000000
+#define DDRSS2_CTL_204_DATA 0x00000000
+#define DDRSS2_CTL_205_DATA 0x00000000
+#define DDRSS2_CTL_206_DATA 0x02000000
+#define DDRSS2_CTL_207_DATA 0x01080101
+#define DDRSS2_CTL_208_DATA 0x00000000
+#define DDRSS2_CTL_209_DATA 0x00000000
+#define DDRSS2_CTL_210_DATA 0x00000000
+#define DDRSS2_CTL_211_DATA 0x00000000
+#define DDRSS2_CTL_212_DATA 0x00000000
+#define DDRSS2_CTL_213_DATA 0x00000000
+#define DDRSS2_CTL_214_DATA 0x00000000
+#define DDRSS2_CTL_215_DATA 0x00000000
+#define DDRSS2_CTL_216_DATA 0x00000000
+#define DDRSS2_CTL_217_DATA 0x00000000
+#define DDRSS2_CTL_218_DATA 0x00000000
+#define DDRSS2_CTL_219_DATA 0x00000000
+#define DDRSS2_CTL_220_DATA 0x00000000
+#define DDRSS2_CTL_221_DATA 0x00000000
+#define DDRSS2_CTL_222_DATA 0x00001000
+#define DDRSS2_CTL_223_DATA 0x006403E8
+#define DDRSS2_CTL_224_DATA 0x00000000
+#define DDRSS2_CTL_225_DATA 0x00000000
+#define DDRSS2_CTL_226_DATA 0x00000000
+#define DDRSS2_CTL_227_DATA 0x15110000
+#define DDRSS2_CTL_228_DATA 0x00040C18
+#define DDRSS2_CTL_229_DATA 0xF000C000
+#define DDRSS2_CTL_230_DATA 0x0000F000
+#define DDRSS2_CTL_231_DATA 0x00000000
+#define DDRSS2_CTL_232_DATA 0x00000000
+#define DDRSS2_CTL_233_DATA 0xC0000000
+#define DDRSS2_CTL_234_DATA 0xF000F000
+#define DDRSS2_CTL_235_DATA 0x00000000
+#define DDRSS2_CTL_236_DATA 0x00000000
+#define DDRSS2_CTL_237_DATA 0x00000000
+#define DDRSS2_CTL_238_DATA 0xF000C000
+#define DDRSS2_CTL_239_DATA 0x0000F000
+#define DDRSS2_CTL_240_DATA 0x00000000
+#define DDRSS2_CTL_241_DATA 0x00000000
+#define DDRSS2_CTL_242_DATA 0x00030000
+#define DDRSS2_CTL_243_DATA 0x00000000
+#define DDRSS2_CTL_244_DATA 0x00000000
+#define DDRSS2_CTL_245_DATA 0x00000000
+#define DDRSS2_CTL_246_DATA 0x00000000
+#define DDRSS2_CTL_247_DATA 0x00000000
+#define DDRSS2_CTL_248_DATA 0x00000000
+#define DDRSS2_CTL_249_DATA 0x00000000
+#define DDRSS2_CTL_250_DATA 0x00000000
+#define DDRSS2_CTL_251_DATA 0x00000000
+#define DDRSS2_CTL_252_DATA 0x00000000
+#define DDRSS2_CTL_253_DATA 0x00000000
+#define DDRSS2_CTL_254_DATA 0x00000000
+#define DDRSS2_CTL_255_DATA 0x00000000
+#define DDRSS2_CTL_256_DATA 0x00000000
+#define DDRSS2_CTL_257_DATA 0x01000200
+#define DDRSS2_CTL_258_DATA 0x00370040
+#define DDRSS2_CTL_259_DATA 0x00020008
+#define DDRSS2_CTL_260_DATA 0x00400100
+#define DDRSS2_CTL_261_DATA 0x00400855
+#define DDRSS2_CTL_262_DATA 0x01000200
+#define DDRSS2_CTL_263_DATA 0x08550040
+#define DDRSS2_CTL_264_DATA 0x00000040
+#define DDRSS2_CTL_265_DATA 0x006B0003
+#define DDRSS2_CTL_266_DATA 0x0100006B
+#define DDRSS2_CTL_267_DATA 0x03030303
+#define DDRSS2_CTL_268_DATA 0x00000000
+#define DDRSS2_CTL_269_DATA 0x00000202
+#define DDRSS2_CTL_270_DATA 0x00001FFF
+#define DDRSS2_CTL_271_DATA 0x3FFF2000
+#define DDRSS2_CTL_272_DATA 0x03FF0000
+#define DDRSS2_CTL_273_DATA 0x000103FF
+#define DDRSS2_CTL_274_DATA 0x0FFF0B00
+#define DDRSS2_CTL_275_DATA 0x01010001
+#define DDRSS2_CTL_276_DATA 0x01010101
+#define DDRSS2_CTL_277_DATA 0x01180101
+#define DDRSS2_CTL_278_DATA 0x00030000
+#define DDRSS2_CTL_279_DATA 0x00000000
+#define DDRSS2_CTL_280_DATA 0x00000000
+#define DDRSS2_CTL_281_DATA 0x00000000
+#define DDRSS2_CTL_282_DATA 0x00000000
+#define DDRSS2_CTL_283_DATA 0x00000000
+#define DDRSS2_CTL_284_DATA 0x00000000
+#define DDRSS2_CTL_285_DATA 0x00000000
+#define DDRSS2_CTL_286_DATA 0x00040101
+#define DDRSS2_CTL_287_DATA 0x04010100
+#define DDRSS2_CTL_288_DATA 0x00000000
+#define DDRSS2_CTL_289_DATA 0x00000000
+#define DDRSS2_CTL_290_DATA 0x03030300
+#define DDRSS2_CTL_291_DATA 0x00000001
+#define DDRSS2_CTL_292_DATA 0x00000000
+#define DDRSS2_CTL_293_DATA 0x00000000
+#define DDRSS2_CTL_294_DATA 0x00000000
+#define DDRSS2_CTL_295_DATA 0x00000000
+#define DDRSS2_CTL_296_DATA 0x00000000
+#define DDRSS2_CTL_297_DATA 0x00000000
+#define DDRSS2_CTL_298_DATA 0x00000000
+#define DDRSS2_CTL_299_DATA 0x00000000
+#define DDRSS2_CTL_300_DATA 0x00000000
+#define DDRSS2_CTL_301_DATA 0x00000000
+#define DDRSS2_CTL_302_DATA 0x00000000
+#define DDRSS2_CTL_303_DATA 0x00000000
+#define DDRSS2_CTL_304_DATA 0x00000000
+#define DDRSS2_CTL_305_DATA 0x00000000
+#define DDRSS2_CTL_306_DATA 0x00000000
+#define DDRSS2_CTL_307_DATA 0x00000000
+#define DDRSS2_CTL_308_DATA 0x00000000
+#define DDRSS2_CTL_309_DATA 0x00000000
+#define DDRSS2_CTL_310_DATA 0x00000000
+#define DDRSS2_CTL_311_DATA 0x00000000
+#define DDRSS2_CTL_312_DATA 0x00000000
+#define DDRSS2_CTL_313_DATA 0x01000000
+#define DDRSS2_CTL_314_DATA 0x00020201
+#define DDRSS2_CTL_315_DATA 0x01000101
+#define DDRSS2_CTL_316_DATA 0x01010001
+#define DDRSS2_CTL_317_DATA 0x00010101
+#define DDRSS2_CTL_318_DATA 0x050A0A03
+#define DDRSS2_CTL_319_DATA 0x10081F1F
+#define DDRSS2_CTL_320_DATA 0x00090310
+#define DDRSS2_CTL_321_DATA 0x0B0C030F
+#define DDRSS2_CTL_322_DATA 0x0B0C0306
+#define DDRSS2_CTL_323_DATA 0x0C090006
+#define DDRSS2_CTL_324_DATA 0x0100000C
+#define DDRSS2_CTL_325_DATA 0x08040801
+#define DDRSS2_CTL_326_DATA 0x00000004
+#define DDRSS2_CTL_327_DATA 0x00000000
+#define DDRSS2_CTL_328_DATA 0x00010000
+#define DDRSS2_CTL_329_DATA 0x00280D00
+#define DDRSS2_CTL_330_DATA 0x00000001
+#define DDRSS2_CTL_331_DATA 0x00030001
+#define DDRSS2_CTL_332_DATA 0x00000000
+#define DDRSS2_CTL_333_DATA 0x00000000
+#define DDRSS2_CTL_334_DATA 0x00000000
+#define DDRSS2_CTL_335_DATA 0x00000000
+#define DDRSS2_CTL_336_DATA 0x00000000
+#define DDRSS2_CTL_337_DATA 0x00000000
+#define DDRSS2_CTL_338_DATA 0x00000000
+#define DDRSS2_CTL_339_DATA 0x00000000
+#define DDRSS2_CTL_340_DATA 0x01000000
+#define DDRSS2_CTL_341_DATA 0x00000001
+#define DDRSS2_CTL_342_DATA 0x00010100
+#define DDRSS2_CTL_343_DATA 0x03030000
+#define DDRSS2_CTL_344_DATA 0x00000000
+#define DDRSS2_CTL_345_DATA 0x00000000
+#define DDRSS2_CTL_346_DATA 0x00000000
+#define DDRSS2_CTL_347_DATA 0x00000000
+#define DDRSS2_CTL_348_DATA 0x00000000
+#define DDRSS2_CTL_349_DATA 0x00000000
+#define DDRSS2_CTL_350_DATA 0x00000000
+#define DDRSS2_CTL_351_DATA 0x00000000
+#define DDRSS2_CTL_352_DATA 0x00000000
+#define DDRSS2_CTL_353_DATA 0x00000000
+#define DDRSS2_CTL_354_DATA 0x00000000
+#define DDRSS2_CTL_355_DATA 0x00000000
+#define DDRSS2_CTL_356_DATA 0x00000000
+#define DDRSS2_CTL_357_DATA 0x00000000
+#define DDRSS2_CTL_358_DATA 0x00000000
+#define DDRSS2_CTL_359_DATA 0x00000000
+#define DDRSS2_CTL_360_DATA 0x000556AA
+#define DDRSS2_CTL_361_DATA 0x000AAAAA
+#define DDRSS2_CTL_362_DATA 0x000AA955
+#define DDRSS2_CTL_363_DATA 0x00055555
+#define DDRSS2_CTL_364_DATA 0x000B3133
+#define DDRSS2_CTL_365_DATA 0x0004CD33
+#define DDRSS2_CTL_366_DATA 0x0004CECC
+#define DDRSS2_CTL_367_DATA 0x000B32CC
+#define DDRSS2_CTL_368_DATA 0x00010300
+#define DDRSS2_CTL_369_DATA 0x03000100
+#define DDRSS2_CTL_370_DATA 0x00000000
+#define DDRSS2_CTL_371_DATA 0x00000000
+#define DDRSS2_CTL_372_DATA 0x00000000
+#define DDRSS2_CTL_373_DATA 0x00000000
+#define DDRSS2_CTL_374_DATA 0x00000000
+#define DDRSS2_CTL_375_DATA 0x00000000
+#define DDRSS2_CTL_376_DATA 0x00000000
+#define DDRSS2_CTL_377_DATA 0x00010000
+#define DDRSS2_CTL_378_DATA 0x00000404
+#define DDRSS2_CTL_379_DATA 0x00000000
+#define DDRSS2_CTL_380_DATA 0x00000000
+#define DDRSS2_CTL_381_DATA 0x00000000
+#define DDRSS2_CTL_382_DATA 0x00000000
+#define DDRSS2_CTL_383_DATA 0x00000000
+#define DDRSS2_CTL_384_DATA 0x00000000
+#define DDRSS2_CTL_385_DATA 0x00000000
+#define DDRSS2_CTL_386_DATA 0x00000000
+#define DDRSS2_CTL_387_DATA 0x3A3A1B00
+#define DDRSS2_CTL_388_DATA 0x000A0000
+#define DDRSS2_CTL_389_DATA 0x0000019C
+#define DDRSS2_CTL_390_DATA 0x00000200
+#define DDRSS2_CTL_391_DATA 0x00000200
+#define DDRSS2_CTL_392_DATA 0x00000200
+#define DDRSS2_CTL_393_DATA 0x00000200
+#define DDRSS2_CTL_394_DATA 0x000004D4
+#define DDRSS2_CTL_395_DATA 0x00001018
+#define DDRSS2_CTL_396_DATA 0x00000204
+#define DDRSS2_CTL_397_DATA 0x000040E6
+#define DDRSS2_CTL_398_DATA 0x00000200
+#define DDRSS2_CTL_399_DATA 0x00000200
+#define DDRSS2_CTL_400_DATA 0x00000200
+#define DDRSS2_CTL_401_DATA 0x00000200
+#define DDRSS2_CTL_402_DATA 0x0000C2B2
+#define DDRSS2_CTL_403_DATA 0x000288FC
+#define DDRSS2_CTL_404_DATA 0x00000E15
+#define DDRSS2_CTL_405_DATA 0x000040E6
+#define DDRSS2_CTL_406_DATA 0x00000200
+#define DDRSS2_CTL_407_DATA 0x00000200
+#define DDRSS2_CTL_408_DATA 0x00000200
+#define DDRSS2_CTL_409_DATA 0x00000200
+#define DDRSS2_CTL_410_DATA 0x0000C2B2
+#define DDRSS2_CTL_411_DATA 0x000288FC
+#define DDRSS2_CTL_412_DATA 0x02020E15
+#define DDRSS2_CTL_413_DATA 0x03030202
+#define DDRSS2_CTL_414_DATA 0x00000022
+#define DDRSS2_CTL_415_DATA 0x00000000
+#define DDRSS2_CTL_416_DATA 0x00000000
+#define DDRSS2_CTL_417_DATA 0x00001403
+#define DDRSS2_CTL_418_DATA 0x000007D0
+#define DDRSS2_CTL_419_DATA 0x00000000
+#define DDRSS2_CTL_420_DATA 0x00000000
+#define DDRSS2_CTL_421_DATA 0x00030000
+#define DDRSS2_CTL_422_DATA 0x0007001F
+#define DDRSS2_CTL_423_DATA 0x001B0033
+#define DDRSS2_CTL_424_DATA 0x001B0033
+#define DDRSS2_CTL_425_DATA 0x00000000
+#define DDRSS2_CTL_426_DATA 0x00000000
+#define DDRSS2_CTL_427_DATA 0x02000000
+#define DDRSS2_CTL_428_DATA 0x01000404
+#define DDRSS2_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS2_CTL_430_DATA 0x00000105
+#define DDRSS2_CTL_431_DATA 0x00010101
+#define DDRSS2_CTL_432_DATA 0x00010101
+#define DDRSS2_CTL_433_DATA 0x00010001
+#define DDRSS2_CTL_434_DATA 0x00000101
+#define DDRSS2_CTL_435_DATA 0x02000201
+#define DDRSS2_CTL_436_DATA 0x02010000
+#define DDRSS2_CTL_437_DATA 0x00000200
+#define DDRSS2_CTL_438_DATA 0x28060000
+#define DDRSS2_CTL_439_DATA 0x00000128
+#define DDRSS2_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_442_DATA 0x00000000
+#define DDRSS2_CTL_443_DATA 0x00000000
+#define DDRSS2_CTL_444_DATA 0x00000000
+#define DDRSS2_CTL_445_DATA 0x00000000
+#define DDRSS2_CTL_446_DATA 0x00000000
+#define DDRSS2_CTL_447_DATA 0x00000000
+#define DDRSS2_CTL_448_DATA 0x00000000
+#define DDRSS2_CTL_449_DATA 0x00000000
+#define DDRSS2_CTL_450_DATA 0x00000000
+#define DDRSS2_CTL_451_DATA 0x00000000
+#define DDRSS2_CTL_452_DATA 0x00000000
+#define DDRSS2_CTL_453_DATA 0x00000000
+#define DDRSS2_CTL_454_DATA 0x00000000
+#define DDRSS2_CTL_455_DATA 0x00000000
+#define DDRSS2_CTL_456_DATA 0x00000000
+#define DDRSS2_CTL_457_DATA 0x00000000
+#define DDRSS2_CTL_458_DATA 0x00000000
+
+#define DDRSS2_PI_00_DATA 0x00000B00
+#define DDRSS2_PI_01_DATA 0x00000000
+#define DDRSS2_PI_02_DATA 0x00000000
+#define DDRSS2_PI_03_DATA 0x00000000
+#define DDRSS2_PI_04_DATA 0x00000000
+#define DDRSS2_PI_05_DATA 0x00000101
+#define DDRSS2_PI_06_DATA 0x00640000
+#define DDRSS2_PI_07_DATA 0x00000001
+#define DDRSS2_PI_08_DATA 0x00000000
+#define DDRSS2_PI_09_DATA 0x00000000
+#define DDRSS2_PI_10_DATA 0x00000000
+#define DDRSS2_PI_11_DATA 0x00000000
+#define DDRSS2_PI_12_DATA 0x00000007
+#define DDRSS2_PI_13_DATA 0x00010002
+#define DDRSS2_PI_14_DATA 0x0800000F
+#define DDRSS2_PI_15_DATA 0x00000103
+#define DDRSS2_PI_16_DATA 0x00000005
+#define DDRSS2_PI_17_DATA 0x00000000
+#define DDRSS2_PI_18_DATA 0x00000000
+#define DDRSS2_PI_19_DATA 0x00000000
+#define DDRSS2_PI_20_DATA 0x00000000
+#define DDRSS2_PI_21_DATA 0x00000000
+#define DDRSS2_PI_22_DATA 0x00000000
+#define DDRSS2_PI_23_DATA 0x00000000
+#define DDRSS2_PI_24_DATA 0x00000000
+#define DDRSS2_PI_25_DATA 0x00000000
+#define DDRSS2_PI_26_DATA 0x00010100
+#define DDRSS2_PI_27_DATA 0x00280A00
+#define DDRSS2_PI_28_DATA 0x00000000
+#define DDRSS2_PI_29_DATA 0x0F000000
+#define DDRSS2_PI_30_DATA 0x00003200
+#define DDRSS2_PI_31_DATA 0x00000000
+#define DDRSS2_PI_32_DATA 0x00000000
+#define DDRSS2_PI_33_DATA 0x01010102
+#define DDRSS2_PI_34_DATA 0x00000000
+#define DDRSS2_PI_35_DATA 0x000000AA
+#define DDRSS2_PI_36_DATA 0x00000055
+#define DDRSS2_PI_37_DATA 0x000000B5
+#define DDRSS2_PI_38_DATA 0x0000004A
+#define DDRSS2_PI_39_DATA 0x00000056
+#define DDRSS2_PI_40_DATA 0x000000A9
+#define DDRSS2_PI_41_DATA 0x000000A9
+#define DDRSS2_PI_42_DATA 0x000000B5
+#define DDRSS2_PI_43_DATA 0x00000000
+#define DDRSS2_PI_44_DATA 0x00000000
+#define DDRSS2_PI_45_DATA 0x000F0F00
+#define DDRSS2_PI_46_DATA 0x0000001B
+#define DDRSS2_PI_47_DATA 0x000007D0
+#define DDRSS2_PI_48_DATA 0x00000300
+#define DDRSS2_PI_49_DATA 0x00000000
+#define DDRSS2_PI_50_DATA 0x00000000
+#define DDRSS2_PI_51_DATA 0x01000000
+#define DDRSS2_PI_52_DATA 0x00010101
+#define DDRSS2_PI_53_DATA 0x00000000
+#define DDRSS2_PI_54_DATA 0x00030000
+#define DDRSS2_PI_55_DATA 0x0F000000
+#define DDRSS2_PI_56_DATA 0x00000017
+#define DDRSS2_PI_57_DATA 0x00000000
+#define DDRSS2_PI_58_DATA 0x00000000
+#define DDRSS2_PI_59_DATA 0x00000000
+#define DDRSS2_PI_60_DATA 0x0A0A140A
+#define DDRSS2_PI_61_DATA 0x10020101
+#define DDRSS2_PI_62_DATA 0x00020805
+#define DDRSS2_PI_63_DATA 0x01000404
+#define DDRSS2_PI_64_DATA 0x00000000
+#define DDRSS2_PI_65_DATA 0x00000000
+#define DDRSS2_PI_66_DATA 0x00000100
+#define DDRSS2_PI_67_DATA 0x0001010F
+#define DDRSS2_PI_68_DATA 0x00340000
+#define DDRSS2_PI_69_DATA 0x00000000
+#define DDRSS2_PI_70_DATA 0x00000000
+#define DDRSS2_PI_71_DATA 0x0000FFFF
+#define DDRSS2_PI_72_DATA 0x00000000
+#define DDRSS2_PI_73_DATA 0x00080000
+#define DDRSS2_PI_74_DATA 0x02000200
+#define DDRSS2_PI_75_DATA 0x01000100
+#define DDRSS2_PI_76_DATA 0x01000000
+#define DDRSS2_PI_77_DATA 0x02000200
+#define DDRSS2_PI_78_DATA 0x00000200
+#define DDRSS2_PI_79_DATA 0x00000000
+#define DDRSS2_PI_80_DATA 0x00000000
+#define DDRSS2_PI_81_DATA 0x00000000
+#define DDRSS2_PI_82_DATA 0x00000000
+#define DDRSS2_PI_83_DATA 0x00000000
+#define DDRSS2_PI_84_DATA 0x00000000
+#define DDRSS2_PI_85_DATA 0x00000000
+#define DDRSS2_PI_86_DATA 0x00000000
+#define DDRSS2_PI_87_DATA 0x00000000
+#define DDRSS2_PI_88_DATA 0x00000000
+#define DDRSS2_PI_89_DATA 0x00000000
+#define DDRSS2_PI_90_DATA 0x00000000
+#define DDRSS2_PI_91_DATA 0x00000400
+#define DDRSS2_PI_92_DATA 0x02010000
+#define DDRSS2_PI_93_DATA 0x00080003
+#define DDRSS2_PI_94_DATA 0x00080000
+#define DDRSS2_PI_95_DATA 0x00000001
+#define DDRSS2_PI_96_DATA 0x00000000
+#define DDRSS2_PI_97_DATA 0x0000AA00
+#define DDRSS2_PI_98_DATA 0x00000000
+#define DDRSS2_PI_99_DATA 0x00000000
+#define DDRSS2_PI_100_DATA 0x00010000
+#define DDRSS2_PI_101_DATA 0x00000000
+#define DDRSS2_PI_102_DATA 0x00000000
+#define DDRSS2_PI_103_DATA 0x00000000
+#define DDRSS2_PI_104_DATA 0x00000000
+#define DDRSS2_PI_105_DATA 0x00000000
+#define DDRSS2_PI_106_DATA 0x00000000
+#define DDRSS2_PI_107_DATA 0x00000000
+#define DDRSS2_PI_108_DATA 0x00000000
+#define DDRSS2_PI_109_DATA 0x00000000
+#define DDRSS2_PI_110_DATA 0x00000000
+#define DDRSS2_PI_111_DATA 0x00000000
+#define DDRSS2_PI_112_DATA 0x00000000
+#define DDRSS2_PI_113_DATA 0x00000000
+#define DDRSS2_PI_114_DATA 0x00000000
+#define DDRSS2_PI_115_DATA 0x00000000
+#define DDRSS2_PI_116_DATA 0x00000000
+#define DDRSS2_PI_117_DATA 0x00000000
+#define DDRSS2_PI_118_DATA 0x00000000
+#define DDRSS2_PI_119_DATA 0x00000000
+#define DDRSS2_PI_120_DATA 0x00000000
+#define DDRSS2_PI_121_DATA 0x00000000
+#define DDRSS2_PI_122_DATA 0x00000000
+#define DDRSS2_PI_123_DATA 0x00000000
+#define DDRSS2_PI_124_DATA 0x00000000
+#define DDRSS2_PI_125_DATA 0x00000008
+#define DDRSS2_PI_126_DATA 0x00000000
+#define DDRSS2_PI_127_DATA 0x00000000
+#define DDRSS2_PI_128_DATA 0x00000000
+#define DDRSS2_PI_129_DATA 0x00000000
+#define DDRSS2_PI_130_DATA 0x00000000
+#define DDRSS2_PI_131_DATA 0x00000000
+#define DDRSS2_PI_132_DATA 0x00000000
+#define DDRSS2_PI_133_DATA 0x00000000
+#define DDRSS2_PI_134_DATA 0x00000002
+#define DDRSS2_PI_135_DATA 0x00000000
+#define DDRSS2_PI_136_DATA 0x00000000
+#define DDRSS2_PI_137_DATA 0x0000000A
+#define DDRSS2_PI_138_DATA 0x00000019
+#define DDRSS2_PI_139_DATA 0x00000100
+#define DDRSS2_PI_140_DATA 0x00000000
+#define DDRSS2_PI_141_DATA 0x00000000
+#define DDRSS2_PI_142_DATA 0x00000000
+#define DDRSS2_PI_143_DATA 0x00000000
+#define DDRSS2_PI_144_DATA 0x01000000
+#define DDRSS2_PI_145_DATA 0x00010003
+#define DDRSS2_PI_146_DATA 0x02000101
+#define DDRSS2_PI_147_DATA 0x01030001
+#define DDRSS2_PI_148_DATA 0x00010400
+#define DDRSS2_PI_149_DATA 0x06000105
+#define DDRSS2_PI_150_DATA 0x01070001
+#define DDRSS2_PI_151_DATA 0x00000000
+#define DDRSS2_PI_152_DATA 0x00000000
+#define DDRSS2_PI_153_DATA 0x00000000
+#define DDRSS2_PI_154_DATA 0x00010001
+#define DDRSS2_PI_155_DATA 0x00000000
+#define DDRSS2_PI_156_DATA 0x00000000
+#define DDRSS2_PI_157_DATA 0x00000000
+#define DDRSS2_PI_158_DATA 0x00000000
+#define DDRSS2_PI_159_DATA 0x00000401
+#define DDRSS2_PI_160_DATA 0x00000000
+#define DDRSS2_PI_161_DATA 0x00010000
+#define DDRSS2_PI_162_DATA 0x00000000
+#define DDRSS2_PI_163_DATA 0x2B2B0200
+#define DDRSS2_PI_164_DATA 0x00000034
+#define DDRSS2_PI_165_DATA 0x00000064
+#define DDRSS2_PI_166_DATA 0x00020064
+#define DDRSS2_PI_167_DATA 0x02000200
+#define DDRSS2_PI_168_DATA 0x48120C04
+#define DDRSS2_PI_169_DATA 0x00154812
+#define DDRSS2_PI_170_DATA 0x000000CE
+#define DDRSS2_PI_171_DATA 0x0000032B
+#define DDRSS2_PI_172_DATA 0x00002073
+#define DDRSS2_PI_173_DATA 0x0000032B
+#define DDRSS2_PI_174_DATA 0x04002073
+#define DDRSS2_PI_175_DATA 0x01010404
+#define DDRSS2_PI_176_DATA 0x00001501
+#define DDRSS2_PI_177_DATA 0x00150015
+#define DDRSS2_PI_178_DATA 0x01000100
+#define DDRSS2_PI_179_DATA 0x00000100
+#define DDRSS2_PI_180_DATA 0x00000000
+#define DDRSS2_PI_181_DATA 0x01010101
+#define DDRSS2_PI_182_DATA 0x00000101
+#define DDRSS2_PI_183_DATA 0x00000000
+#define DDRSS2_PI_184_DATA 0x00000000
+#define DDRSS2_PI_185_DATA 0x15040000
+#define DDRSS2_PI_186_DATA 0x0E0E0215
+#define DDRSS2_PI_187_DATA 0x00040402
+#define DDRSS2_PI_188_DATA 0x000D0035
+#define DDRSS2_PI_189_DATA 0x00218049
+#define DDRSS2_PI_190_DATA 0x00218049
+#define DDRSS2_PI_191_DATA 0x01010101
+#define DDRSS2_PI_192_DATA 0x0004000E
+#define DDRSS2_PI_193_DATA 0x00040216
+#define DDRSS2_PI_194_DATA 0x01000216
+#define DDRSS2_PI_195_DATA 0x000F000F
+#define DDRSS2_PI_196_DATA 0x02170100
+#define DDRSS2_PI_197_DATA 0x01000217
+#define DDRSS2_PI_198_DATA 0x02170217
+#define DDRSS2_PI_199_DATA 0x32103200
+#define DDRSS2_PI_200_DATA 0x01013210
+#define DDRSS2_PI_201_DATA 0x0A070601
+#define DDRSS2_PI_202_DATA 0x1F130A0D
+#define DDRSS2_PI_203_DATA 0x1F130A14
+#define DDRSS2_PI_204_DATA 0x0000C014
+#define DDRSS2_PI_205_DATA 0x00C01000
+#define DDRSS2_PI_206_DATA 0x00C01000
+#define DDRSS2_PI_207_DATA 0x00021000
+#define DDRSS2_PI_208_DATA 0x0024000E
+#define DDRSS2_PI_209_DATA 0x00240216
+#define DDRSS2_PI_210_DATA 0x00110216
+#define DDRSS2_PI_211_DATA 0x32000056
+#define DDRSS2_PI_212_DATA 0x00000301
+#define DDRSS2_PI_213_DATA 0x005B0036
+#define DDRSS2_PI_214_DATA 0x03013212
+#define DDRSS2_PI_215_DATA 0x00003600
+#define DDRSS2_PI_216_DATA 0x3212005B
+#define DDRSS2_PI_217_DATA 0x09000301
+#define DDRSS2_PI_218_DATA 0x04010504
+#define DDRSS2_PI_219_DATA 0x040006C9
+#define DDRSS2_PI_220_DATA 0x0A032001
+#define DDRSS2_PI_221_DATA 0x2C31110A
+#define DDRSS2_PI_222_DATA 0x00002918
+#define DDRSS2_PI_223_DATA 0x6001071C
+#define DDRSS2_PI_224_DATA 0x1E202008
+#define DDRSS2_PI_225_DATA 0x2C311116
+#define DDRSS2_PI_226_DATA 0x00002918
+#define DDRSS2_PI_227_DATA 0x6001071C
+#define DDRSS2_PI_228_DATA 0x1E202008
+#define DDRSS2_PI_229_DATA 0x00019C16
+#define DDRSS2_PI_230_DATA 0x00001018
+#define DDRSS2_PI_231_DATA 0x000040E6
+#define DDRSS2_PI_232_DATA 0x000288FC
+#define DDRSS2_PI_233_DATA 0x000040E6
+#define DDRSS2_PI_234_DATA 0x000288FC
+#define DDRSS2_PI_235_DATA 0x033B0016
+#define DDRSS2_PI_236_DATA 0x0303033B
+#define DDRSS2_PI_237_DATA 0x002AF803
+#define DDRSS2_PI_238_DATA 0x0001ADAF
+#define DDRSS2_PI_239_DATA 0x00000005
+#define DDRSS2_PI_240_DATA 0x0000006E
+#define DDRSS2_PI_241_DATA 0x00000016
+#define DDRSS2_PI_242_DATA 0x000681C8
+#define DDRSS2_PI_243_DATA 0x0001ADAF
+#define DDRSS2_PI_244_DATA 0x00000005
+#define DDRSS2_PI_245_DATA 0x000010A9
+#define DDRSS2_PI_246_DATA 0x0000033B
+#define DDRSS2_PI_247_DATA 0x000681C8
+#define DDRSS2_PI_248_DATA 0x0001ADAF
+#define DDRSS2_PI_249_DATA 0x00000005
+#define DDRSS2_PI_250_DATA 0x000010A9
+#define DDRSS2_PI_251_DATA 0x0100033B
+#define DDRSS2_PI_252_DATA 0x00370040
+#define DDRSS2_PI_253_DATA 0x00010008
+#define DDRSS2_PI_254_DATA 0x08550040
+#define DDRSS2_PI_255_DATA 0x00010040
+#define DDRSS2_PI_256_DATA 0x08550040
+#define DDRSS2_PI_257_DATA 0x00000340
+#define DDRSS2_PI_258_DATA 0x006B006B
+#define DDRSS2_PI_259_DATA 0x08040404
+#define DDRSS2_PI_260_DATA 0x00000055
+#define DDRSS2_PI_261_DATA 0x55083C5A
+#define DDRSS2_PI_262_DATA 0x5A000000
+#define DDRSS2_PI_263_DATA 0x0055083C
+#define DDRSS2_PI_264_DATA 0x3C5A0000
+#define DDRSS2_PI_265_DATA 0x00005508
+#define DDRSS2_PI_266_DATA 0x0C3C5A00
+#define DDRSS2_PI_267_DATA 0x080F0E0D
+#define DDRSS2_PI_268_DATA 0x000B0A09
+#define DDRSS2_PI_269_DATA 0x00030201
+#define DDRSS2_PI_270_DATA 0x01000000
+#define DDRSS2_PI_271_DATA 0x04020201
+#define DDRSS2_PI_272_DATA 0x00080804
+#define DDRSS2_PI_273_DATA 0x00000000
+#define DDRSS2_PI_274_DATA 0x00000000
+#define DDRSS2_PI_275_DATA 0x00330084
+#define DDRSS2_PI_276_DATA 0x00160000
+#define DDRSS2_PI_277_DATA 0x35333FF4
+#define DDRSS2_PI_278_DATA 0x00160F27
+#define DDRSS2_PI_279_DATA 0x35333FF4
+#define DDRSS2_PI_280_DATA 0x00160F27
+#define DDRSS2_PI_281_DATA 0x00330084
+#define DDRSS2_PI_282_DATA 0x00160000
+#define DDRSS2_PI_283_DATA 0x35333FF4
+#define DDRSS2_PI_284_DATA 0x00160F27
+#define DDRSS2_PI_285_DATA 0x35333FF4
+#define DDRSS2_PI_286_DATA 0x00160F27
+#define DDRSS2_PI_287_DATA 0x00330084
+#define DDRSS2_PI_288_DATA 0x00160000
+#define DDRSS2_PI_289_DATA 0x35333FF4
+#define DDRSS2_PI_290_DATA 0x00160F27
+#define DDRSS2_PI_291_DATA 0x35333FF4
+#define DDRSS2_PI_292_DATA 0x00160F27
+#define DDRSS2_PI_293_DATA 0x00330084
+#define DDRSS2_PI_294_DATA 0x00160000
+#define DDRSS2_PI_295_DATA 0x35333FF4
+#define DDRSS2_PI_296_DATA 0x00160F27
+#define DDRSS2_PI_297_DATA 0x35333FF4
+#define DDRSS2_PI_298_DATA 0x00160F27
+#define DDRSS2_PI_299_DATA 0x00000000
+
+#define DDRSS2_PHY_00_DATA 0x000004F0
+#define DDRSS2_PHY_01_DATA 0x00000000
+#define DDRSS2_PHY_02_DATA 0x00030200
+#define DDRSS2_PHY_03_DATA 0x00000000
+#define DDRSS2_PHY_04_DATA 0x00000000
+#define DDRSS2_PHY_05_DATA 0x01030000
+#define DDRSS2_PHY_06_DATA 0x00010000
+#define DDRSS2_PHY_07_DATA 0x01030004
+#define DDRSS2_PHY_08_DATA 0x01000000
+#define DDRSS2_PHY_09_DATA 0x00000000
+#define DDRSS2_PHY_10_DATA 0x00000000
+#define DDRSS2_PHY_11_DATA 0x01000001
+#define DDRSS2_PHY_12_DATA 0x00000100
+#define DDRSS2_PHY_13_DATA 0x000800C0
+#define DDRSS2_PHY_14_DATA 0x060100CC
+#define DDRSS2_PHY_15_DATA 0x00030066
+#define DDRSS2_PHY_16_DATA 0x00000000
+#define DDRSS2_PHY_17_DATA 0x00000301
+#define DDRSS2_PHY_18_DATA 0x0000AAAA
+#define DDRSS2_PHY_19_DATA 0x00005555
+#define DDRSS2_PHY_20_DATA 0x0000B5B5
+#define DDRSS2_PHY_21_DATA 0x00004A4A
+#define DDRSS2_PHY_22_DATA 0x00005656
+#define DDRSS2_PHY_23_DATA 0x0000A9A9
+#define DDRSS2_PHY_24_DATA 0x0000A9A9
+#define DDRSS2_PHY_25_DATA 0x0000B5B5
+#define DDRSS2_PHY_26_DATA 0x00000000
+#define DDRSS2_PHY_27_DATA 0x00000000
+#define DDRSS2_PHY_28_DATA 0x2A000000
+#define DDRSS2_PHY_29_DATA 0x00000808
+#define DDRSS2_PHY_30_DATA 0x0F000000
+#define DDRSS2_PHY_31_DATA 0x00000F0F
+#define DDRSS2_PHY_32_DATA 0x10400000
+#define DDRSS2_PHY_33_DATA 0x0C002006
+#define DDRSS2_PHY_34_DATA 0x00000000
+#define DDRSS2_PHY_35_DATA 0x00000000
+#define DDRSS2_PHY_36_DATA 0x55555555
+#define DDRSS2_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_38_DATA 0x55555555
+#define DDRSS2_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_40_DATA 0x00005555
+#define DDRSS2_PHY_41_DATA 0x01000100
+#define DDRSS2_PHY_42_DATA 0x00800180
+#define DDRSS2_PHY_43_DATA 0x00000001
+#define DDRSS2_PHY_44_DATA 0x00000000
+#define DDRSS2_PHY_45_DATA 0x00000000
+#define DDRSS2_PHY_46_DATA 0x00000000
+#define DDRSS2_PHY_47_DATA 0x00000000
+#define DDRSS2_PHY_48_DATA 0x00000000
+#define DDRSS2_PHY_49_DATA 0x00000000
+#define DDRSS2_PHY_50_DATA 0x00000000
+#define DDRSS2_PHY_51_DATA 0x00000000
+#define DDRSS2_PHY_52_DATA 0x00000000
+#define DDRSS2_PHY_53_DATA 0x00000000
+#define DDRSS2_PHY_54_DATA 0x00000000
+#define DDRSS2_PHY_55_DATA 0x00000000
+#define DDRSS2_PHY_56_DATA 0x00000000
+#define DDRSS2_PHY_57_DATA 0x00000000
+#define DDRSS2_PHY_58_DATA 0x00000000
+#define DDRSS2_PHY_59_DATA 0x00000000
+#define DDRSS2_PHY_60_DATA 0x00000000
+#define DDRSS2_PHY_61_DATA 0x00000000
+#define DDRSS2_PHY_62_DATA 0x00000000
+#define DDRSS2_PHY_63_DATA 0x00000000
+#define DDRSS2_PHY_64_DATA 0x00000000
+#define DDRSS2_PHY_65_DATA 0x00000000
+#define DDRSS2_PHY_66_DATA 0x00000104
+#define DDRSS2_PHY_67_DATA 0x00000120
+#define DDRSS2_PHY_68_DATA 0x00000000
+#define DDRSS2_PHY_69_DATA 0x00000000
+#define DDRSS2_PHY_70_DATA 0x00000000
+#define DDRSS2_PHY_71_DATA 0x00000000
+#define DDRSS2_PHY_72_DATA 0x00000000
+#define DDRSS2_PHY_73_DATA 0x00000000
+#define DDRSS2_PHY_74_DATA 0x00000000
+#define DDRSS2_PHY_75_DATA 0x00000001
+#define DDRSS2_PHY_76_DATA 0x07FF0000
+#define DDRSS2_PHY_77_DATA 0x0080081F
+#define DDRSS2_PHY_78_DATA 0x00081020
+#define DDRSS2_PHY_79_DATA 0x04010000
+#define DDRSS2_PHY_80_DATA 0x00000000
+#define DDRSS2_PHY_81_DATA 0x00000000
+#define DDRSS2_PHY_82_DATA 0x00000000
+#define DDRSS2_PHY_83_DATA 0x00000100
+#define DDRSS2_PHY_84_DATA 0x01CC0C01
+#define DDRSS2_PHY_85_DATA 0x1003CC0C
+#define DDRSS2_PHY_86_DATA 0x20000140
+#define DDRSS2_PHY_87_DATA 0x07FF0200
+#define DDRSS2_PHY_88_DATA 0x0000DD01
+#define DDRSS2_PHY_89_DATA 0x10100303
+#define DDRSS2_PHY_90_DATA 0x10101010
+#define DDRSS2_PHY_91_DATA 0x10101010
+#define DDRSS2_PHY_92_DATA 0x00021010
+#define DDRSS2_PHY_93_DATA 0x00100010
+#define DDRSS2_PHY_94_DATA 0x00100010
+#define DDRSS2_PHY_95_DATA 0x00100010
+#define DDRSS2_PHY_96_DATA 0x00100010
+#define DDRSS2_PHY_97_DATA 0x00050010
+#define DDRSS2_PHY_98_DATA 0x51517041
+#define DDRSS2_PHY_99_DATA 0x31C06001
+#define DDRSS2_PHY_100_DATA 0x07AB0340
+#define DDRSS2_PHY_101_DATA 0x00C0C001
+#define DDRSS2_PHY_102_DATA 0x0E0D0001
+#define DDRSS2_PHY_103_DATA 0x10001000
+#define DDRSS2_PHY_104_DATA 0x0C083E42
+#define DDRSS2_PHY_105_DATA 0x0F0C3701
+#define DDRSS2_PHY_106_DATA 0x01000140
+#define DDRSS2_PHY_107_DATA 0x0C000420
+#define DDRSS2_PHY_108_DATA 0x00000198
+#define DDRSS2_PHY_109_DATA 0x0A0000D0
+#define DDRSS2_PHY_110_DATA 0x00030200
+#define DDRSS2_PHY_111_DATA 0x02800000
+#define DDRSS2_PHY_112_DATA 0x80800000
+#define DDRSS2_PHY_113_DATA 0x000E2010
+#define DDRSS2_PHY_114_DATA 0x76543210
+#define DDRSS2_PHY_115_DATA 0x00000008
+#define DDRSS2_PHY_116_DATA 0x02800280
+#define DDRSS2_PHY_117_DATA 0x02800280
+#define DDRSS2_PHY_118_DATA 0x02800280
+#define DDRSS2_PHY_119_DATA 0x02800280
+#define DDRSS2_PHY_120_DATA 0x00000280
+#define DDRSS2_PHY_121_DATA 0x0000A000
+#define DDRSS2_PHY_122_DATA 0x00A000A0
+#define DDRSS2_PHY_123_DATA 0x00A000A0
+#define DDRSS2_PHY_124_DATA 0x00A000A0
+#define DDRSS2_PHY_125_DATA 0x00A000A0
+#define DDRSS2_PHY_126_DATA 0x00A000A0
+#define DDRSS2_PHY_127_DATA 0x00A000A0
+#define DDRSS2_PHY_128_DATA 0x00A000A0
+#define DDRSS2_PHY_129_DATA 0x00A000A0
+#define DDRSS2_PHY_130_DATA 0x01C200A0
+#define DDRSS2_PHY_131_DATA 0x01A00005
+#define DDRSS2_PHY_132_DATA 0x00000000
+#define DDRSS2_PHY_133_DATA 0x00000000
+#define DDRSS2_PHY_134_DATA 0x00080200
+#define DDRSS2_PHY_135_DATA 0x00000000
+#define DDRSS2_PHY_136_DATA 0x20202000
+#define DDRSS2_PHY_137_DATA 0x20202020
+#define DDRSS2_PHY_138_DATA 0xF0F02020
+#define DDRSS2_PHY_139_DATA 0x00000000
+#define DDRSS2_PHY_140_DATA 0x00000000
+#define DDRSS2_PHY_141_DATA 0x00000000
+#define DDRSS2_PHY_142_DATA 0x00000000
+#define DDRSS2_PHY_143_DATA 0x00000000
+#define DDRSS2_PHY_144_DATA 0x00000000
+#define DDRSS2_PHY_145_DATA 0x00000000
+#define DDRSS2_PHY_146_DATA 0x00000000
+#define DDRSS2_PHY_147_DATA 0x00000000
+#define DDRSS2_PHY_148_DATA 0x00000000
+#define DDRSS2_PHY_149_DATA 0x00000000
+#define DDRSS2_PHY_150_DATA 0x00000000
+#define DDRSS2_PHY_151_DATA 0x00000000
+#define DDRSS2_PHY_152_DATA 0x00000000
+#define DDRSS2_PHY_153_DATA 0x00000000
+#define DDRSS2_PHY_154_DATA 0x00000000
+#define DDRSS2_PHY_155_DATA 0x00000000
+#define DDRSS2_PHY_156_DATA 0x00000000
+#define DDRSS2_PHY_157_DATA 0x00000000
+#define DDRSS2_PHY_158_DATA 0x00000000
+#define DDRSS2_PHY_159_DATA 0x00000000
+#define DDRSS2_PHY_160_DATA 0x00000000
+#define DDRSS2_PHY_161_DATA 0x00000000
+#define DDRSS2_PHY_162_DATA 0x00000000
+#define DDRSS2_PHY_163_DATA 0x00000000
+#define DDRSS2_PHY_164_DATA 0x00000000
+#define DDRSS2_PHY_165_DATA 0x00000000
+#define DDRSS2_PHY_166_DATA 0x00000000
+#define DDRSS2_PHY_167_DATA 0x00000000
+#define DDRSS2_PHY_168_DATA 0x00000000
+#define DDRSS2_PHY_169_DATA 0x00000000
+#define DDRSS2_PHY_170_DATA 0x00000000
+#define DDRSS2_PHY_171_DATA 0x00000000
+#define DDRSS2_PHY_172_DATA 0x00000000
+#define DDRSS2_PHY_173_DATA 0x00000000
+#define DDRSS2_PHY_174_DATA 0x00000000
+#define DDRSS2_PHY_175_DATA 0x00000000
+#define DDRSS2_PHY_176_DATA 0x00000000
+#define DDRSS2_PHY_177_DATA 0x00000000
+#define DDRSS2_PHY_178_DATA 0x00000000
+#define DDRSS2_PHY_179_DATA 0x00000000
+#define DDRSS2_PHY_180_DATA 0x00000000
+#define DDRSS2_PHY_181_DATA 0x00000000
+#define DDRSS2_PHY_182_DATA 0x00000000
+#define DDRSS2_PHY_183_DATA 0x00000000
+#define DDRSS2_PHY_184_DATA 0x00000000
+#define DDRSS2_PHY_185_DATA 0x00000000
+#define DDRSS2_PHY_186_DATA 0x00000000
+#define DDRSS2_PHY_187_DATA 0x00000000
+#define DDRSS2_PHY_188_DATA 0x00000000
+#define DDRSS2_PHY_189_DATA 0x00000000
+#define DDRSS2_PHY_190_DATA 0x00000000
+#define DDRSS2_PHY_191_DATA 0x00000000
+#define DDRSS2_PHY_192_DATA 0x00000000
+#define DDRSS2_PHY_193_DATA 0x00000000
+#define DDRSS2_PHY_194_DATA 0x00000000
+#define DDRSS2_PHY_195_DATA 0x00000000
+#define DDRSS2_PHY_196_DATA 0x00000000
+#define DDRSS2_PHY_197_DATA 0x00000000
+#define DDRSS2_PHY_198_DATA 0x00000000
+#define DDRSS2_PHY_199_DATA 0x00000000
+#define DDRSS2_PHY_200_DATA 0x00000000
+#define DDRSS2_PHY_201_DATA 0x00000000
+#define DDRSS2_PHY_202_DATA 0x00000000
+#define DDRSS2_PHY_203_DATA 0x00000000
+#define DDRSS2_PHY_204_DATA 0x00000000
+#define DDRSS2_PHY_205_DATA 0x00000000
+#define DDRSS2_PHY_206_DATA 0x00000000
+#define DDRSS2_PHY_207_DATA 0x00000000
+#define DDRSS2_PHY_208_DATA 0x00000000
+#define DDRSS2_PHY_209_DATA 0x00000000
+#define DDRSS2_PHY_210_DATA 0x00000000
+#define DDRSS2_PHY_211_DATA 0x00000000
+#define DDRSS2_PHY_212_DATA 0x00000000
+#define DDRSS2_PHY_213_DATA 0x00000000
+#define DDRSS2_PHY_214_DATA 0x00000000
+#define DDRSS2_PHY_215_DATA 0x00000000
+#define DDRSS2_PHY_216_DATA 0x00000000
+#define DDRSS2_PHY_217_DATA 0x00000000
+#define DDRSS2_PHY_218_DATA 0x00000000
+#define DDRSS2_PHY_219_DATA 0x00000000
+#define DDRSS2_PHY_220_DATA 0x00000000
+#define DDRSS2_PHY_221_DATA 0x00000000
+#define DDRSS2_PHY_222_DATA 0x00000000
+#define DDRSS2_PHY_223_DATA 0x00000000
+#define DDRSS2_PHY_224_DATA 0x00000000
+#define DDRSS2_PHY_225_DATA 0x00000000
+#define DDRSS2_PHY_226_DATA 0x00000000
+#define DDRSS2_PHY_227_DATA 0x00000000
+#define DDRSS2_PHY_228_DATA 0x00000000
+#define DDRSS2_PHY_229_DATA 0x00000000
+#define DDRSS2_PHY_230_DATA 0x00000000
+#define DDRSS2_PHY_231_DATA 0x00000000
+#define DDRSS2_PHY_232_DATA 0x00000000
+#define DDRSS2_PHY_233_DATA 0x00000000
+#define DDRSS2_PHY_234_DATA 0x00000000
+#define DDRSS2_PHY_235_DATA 0x00000000
+#define DDRSS2_PHY_236_DATA 0x00000000
+#define DDRSS2_PHY_237_DATA 0x00000000
+#define DDRSS2_PHY_238_DATA 0x00000000
+#define DDRSS2_PHY_239_DATA 0x00000000
+#define DDRSS2_PHY_240_DATA 0x00000000
+#define DDRSS2_PHY_241_DATA 0x00000000
+#define DDRSS2_PHY_242_DATA 0x00000000
+#define DDRSS2_PHY_243_DATA 0x00000000
+#define DDRSS2_PHY_244_DATA 0x00000000
+#define DDRSS2_PHY_245_DATA 0x00000000
+#define DDRSS2_PHY_246_DATA 0x00000000
+#define DDRSS2_PHY_247_DATA 0x00000000
+#define DDRSS2_PHY_248_DATA 0x00000000
+#define DDRSS2_PHY_249_DATA 0x00000000
+#define DDRSS2_PHY_250_DATA 0x00000000
+#define DDRSS2_PHY_251_DATA 0x00000000
+#define DDRSS2_PHY_252_DATA 0x00000000
+#define DDRSS2_PHY_253_DATA 0x00000000
+#define DDRSS2_PHY_254_DATA 0x00000000
+#define DDRSS2_PHY_255_DATA 0x00000000
+#define DDRSS2_PHY_256_DATA 0x000004F0
+#define DDRSS2_PHY_257_DATA 0x00000000
+#define DDRSS2_PHY_258_DATA 0x00030200
+#define DDRSS2_PHY_259_DATA 0x00000000
+#define DDRSS2_PHY_260_DATA 0x00000000
+#define DDRSS2_PHY_261_DATA 0x01030000
+#define DDRSS2_PHY_262_DATA 0x00010000
+#define DDRSS2_PHY_263_DATA 0x01030004
+#define DDRSS2_PHY_264_DATA 0x01000000
+#define DDRSS2_PHY_265_DATA 0x00000000
+#define DDRSS2_PHY_266_DATA 0x00000000
+#define DDRSS2_PHY_267_DATA 0x01000001
+#define DDRSS2_PHY_268_DATA 0x00000100
+#define DDRSS2_PHY_269_DATA 0x000800C0
+#define DDRSS2_PHY_270_DATA 0x060100CC
+#define DDRSS2_PHY_271_DATA 0x00030066
+#define DDRSS2_PHY_272_DATA 0x00000000
+#define DDRSS2_PHY_273_DATA 0x00000301
+#define DDRSS2_PHY_274_DATA 0x0000AAAA
+#define DDRSS2_PHY_275_DATA 0x00005555
+#define DDRSS2_PHY_276_DATA 0x0000B5B5
+#define DDRSS2_PHY_277_DATA 0x00004A4A
+#define DDRSS2_PHY_278_DATA 0x00005656
+#define DDRSS2_PHY_279_DATA 0x0000A9A9
+#define DDRSS2_PHY_280_DATA 0x0000A9A9
+#define DDRSS2_PHY_281_DATA 0x0000B5B5
+#define DDRSS2_PHY_282_DATA 0x00000000
+#define DDRSS2_PHY_283_DATA 0x00000000
+#define DDRSS2_PHY_284_DATA 0x2A000000
+#define DDRSS2_PHY_285_DATA 0x00000808
+#define DDRSS2_PHY_286_DATA 0x0F000000
+#define DDRSS2_PHY_287_DATA 0x00000F0F
+#define DDRSS2_PHY_288_DATA 0x10400000
+#define DDRSS2_PHY_289_DATA 0x0C002006
+#define DDRSS2_PHY_290_DATA 0x00000000
+#define DDRSS2_PHY_291_DATA 0x00000000
+#define DDRSS2_PHY_292_DATA 0x55555555
+#define DDRSS2_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_294_DATA 0x55555555
+#define DDRSS2_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_296_DATA 0x00005555
+#define DDRSS2_PHY_297_DATA 0x01000100
+#define DDRSS2_PHY_298_DATA 0x00800180
+#define DDRSS2_PHY_299_DATA 0x00000000
+#define DDRSS2_PHY_300_DATA 0x00000000
+#define DDRSS2_PHY_301_DATA 0x00000000
+#define DDRSS2_PHY_302_DATA 0x00000000
+#define DDRSS2_PHY_303_DATA 0x00000000
+#define DDRSS2_PHY_304_DATA 0x00000000
+#define DDRSS2_PHY_305_DATA 0x00000000
+#define DDRSS2_PHY_306_DATA 0x00000000
+#define DDRSS2_PHY_307_DATA 0x00000000
+#define DDRSS2_PHY_308_DATA 0x00000000
+#define DDRSS2_PHY_309_DATA 0x00000000
+#define DDRSS2_PHY_310_DATA 0x00000000
+#define DDRSS2_PHY_311_DATA 0x00000000
+#define DDRSS2_PHY_312_DATA 0x00000000
+#define DDRSS2_PHY_313_DATA 0x00000000
+#define DDRSS2_PHY_314_DATA 0x00000000
+#define DDRSS2_PHY_315_DATA 0x00000000
+#define DDRSS2_PHY_316_DATA 0x00000000
+#define DDRSS2_PHY_317_DATA 0x00000000
+#define DDRSS2_PHY_318_DATA 0x00000000
+#define DDRSS2_PHY_319_DATA 0x00000000
+#define DDRSS2_PHY_320_DATA 0x00000000
+#define DDRSS2_PHY_321_DATA 0x00000000
+#define DDRSS2_PHY_322_DATA 0x00000104
+#define DDRSS2_PHY_323_DATA 0x00000120
+#define DDRSS2_PHY_324_DATA 0x00000000
+#define DDRSS2_PHY_325_DATA 0x00000000
+#define DDRSS2_PHY_326_DATA 0x00000000
+#define DDRSS2_PHY_327_DATA 0x00000000
+#define DDRSS2_PHY_328_DATA 0x00000000
+#define DDRSS2_PHY_329_DATA 0x00000000
+#define DDRSS2_PHY_330_DATA 0x00000000
+#define DDRSS2_PHY_331_DATA 0x00000001
+#define DDRSS2_PHY_332_DATA 0x07FF0000
+#define DDRSS2_PHY_333_DATA 0x0080081F
+#define DDRSS2_PHY_334_DATA 0x00081020
+#define DDRSS2_PHY_335_DATA 0x04010000
+#define DDRSS2_PHY_336_DATA 0x00000000
+#define DDRSS2_PHY_337_DATA 0x00000000
+#define DDRSS2_PHY_338_DATA 0x00000000
+#define DDRSS2_PHY_339_DATA 0x00000100
+#define DDRSS2_PHY_340_DATA 0x01CC0C01
+#define DDRSS2_PHY_341_DATA 0x1003CC0C
+#define DDRSS2_PHY_342_DATA 0x20000140
+#define DDRSS2_PHY_343_DATA 0x07FF0200
+#define DDRSS2_PHY_344_DATA 0x0000DD01
+#define DDRSS2_PHY_345_DATA 0x10100303
+#define DDRSS2_PHY_346_DATA 0x10101010
+#define DDRSS2_PHY_347_DATA 0x10101010
+#define DDRSS2_PHY_348_DATA 0x00021010
+#define DDRSS2_PHY_349_DATA 0x00100010
+#define DDRSS2_PHY_350_DATA 0x00100010
+#define DDRSS2_PHY_351_DATA 0x00100010
+#define DDRSS2_PHY_352_DATA 0x00100010
+#define DDRSS2_PHY_353_DATA 0x00050010
+#define DDRSS2_PHY_354_DATA 0x51517041
+#define DDRSS2_PHY_355_DATA 0x31C06001
+#define DDRSS2_PHY_356_DATA 0x07AB0340
+#define DDRSS2_PHY_357_DATA 0x00C0C001
+#define DDRSS2_PHY_358_DATA 0x0E0D0001
+#define DDRSS2_PHY_359_DATA 0x10001000
+#define DDRSS2_PHY_360_DATA 0x0C083E42
+#define DDRSS2_PHY_361_DATA 0x0F0C3701
+#define DDRSS2_PHY_362_DATA 0x01000140
+#define DDRSS2_PHY_363_DATA 0x0C000420
+#define DDRSS2_PHY_364_DATA 0x00000198
+#define DDRSS2_PHY_365_DATA 0x0A0000D0
+#define DDRSS2_PHY_366_DATA 0x00030200
+#define DDRSS2_PHY_367_DATA 0x02800000
+#define DDRSS2_PHY_368_DATA 0x80800000
+#define DDRSS2_PHY_369_DATA 0x000E2010
+#define DDRSS2_PHY_370_DATA 0x76543210
+#define DDRSS2_PHY_371_DATA 0x00000008
+#define DDRSS2_PHY_372_DATA 0x02800280
+#define DDRSS2_PHY_373_DATA 0x02800280
+#define DDRSS2_PHY_374_DATA 0x02800280
+#define DDRSS2_PHY_375_DATA 0x02800280
+#define DDRSS2_PHY_376_DATA 0x00000280
+#define DDRSS2_PHY_377_DATA 0x0000A000
+#define DDRSS2_PHY_378_DATA 0x00A000A0
+#define DDRSS2_PHY_379_DATA 0x00A000A0
+#define DDRSS2_PHY_380_DATA 0x00A000A0
+#define DDRSS2_PHY_381_DATA 0x00A000A0
+#define DDRSS2_PHY_382_DATA 0x00A000A0
+#define DDRSS2_PHY_383_DATA 0x00A000A0
+#define DDRSS2_PHY_384_DATA 0x00A000A0
+#define DDRSS2_PHY_385_DATA 0x00A000A0
+#define DDRSS2_PHY_386_DATA 0x01C200A0
+#define DDRSS2_PHY_387_DATA 0x01A00005
+#define DDRSS2_PHY_388_DATA 0x00000000
+#define DDRSS2_PHY_389_DATA 0x00000000
+#define DDRSS2_PHY_390_DATA 0x00080200
+#define DDRSS2_PHY_391_DATA 0x00000000
+#define DDRSS2_PHY_392_DATA 0x20202000
+#define DDRSS2_PHY_393_DATA 0x20202020
+#define DDRSS2_PHY_394_DATA 0xF0F02020
+#define DDRSS2_PHY_395_DATA 0x00000000
+#define DDRSS2_PHY_396_DATA 0x00000000
+#define DDRSS2_PHY_397_DATA 0x00000000
+#define DDRSS2_PHY_398_DATA 0x00000000
+#define DDRSS2_PHY_399_DATA 0x00000000
+#define DDRSS2_PHY_400_DATA 0x00000000
+#define DDRSS2_PHY_401_DATA 0x00000000
+#define DDRSS2_PHY_402_DATA 0x00000000
+#define DDRSS2_PHY_403_DATA 0x00000000
+#define DDRSS2_PHY_404_DATA 0x00000000
+#define DDRSS2_PHY_405_DATA 0x00000000
+#define DDRSS2_PHY_406_DATA 0x00000000
+#define DDRSS2_PHY_407_DATA 0x00000000
+#define DDRSS2_PHY_408_DATA 0x00000000
+#define DDRSS2_PHY_409_DATA 0x00000000
+#define DDRSS2_PHY_410_DATA 0x00000000
+#define DDRSS2_PHY_411_DATA 0x00000000
+#define DDRSS2_PHY_412_DATA 0x00000000
+#define DDRSS2_PHY_413_DATA 0x00000000
+#define DDRSS2_PHY_414_DATA 0x00000000
+#define DDRSS2_PHY_415_DATA 0x00000000
+#define DDRSS2_PHY_416_DATA 0x00000000
+#define DDRSS2_PHY_417_DATA 0x00000000
+#define DDRSS2_PHY_418_DATA 0x00000000
+#define DDRSS2_PHY_419_DATA 0x00000000
+#define DDRSS2_PHY_420_DATA 0x00000000
+#define DDRSS2_PHY_421_DATA 0x00000000
+#define DDRSS2_PHY_422_DATA 0x00000000
+#define DDRSS2_PHY_423_DATA 0x00000000
+#define DDRSS2_PHY_424_DATA 0x00000000
+#define DDRSS2_PHY_425_DATA 0x00000000
+#define DDRSS2_PHY_426_DATA 0x00000000
+#define DDRSS2_PHY_427_DATA 0x00000000
+#define DDRSS2_PHY_428_DATA 0x00000000
+#define DDRSS2_PHY_429_DATA 0x00000000
+#define DDRSS2_PHY_430_DATA 0x00000000
+#define DDRSS2_PHY_431_DATA 0x00000000
+#define DDRSS2_PHY_432_DATA 0x00000000
+#define DDRSS2_PHY_433_DATA 0x00000000
+#define DDRSS2_PHY_434_DATA 0x00000000
+#define DDRSS2_PHY_435_DATA 0x00000000
+#define DDRSS2_PHY_436_DATA 0x00000000
+#define DDRSS2_PHY_437_DATA 0x00000000
+#define DDRSS2_PHY_438_DATA 0x00000000
+#define DDRSS2_PHY_439_DATA 0x00000000
+#define DDRSS2_PHY_440_DATA 0x00000000
+#define DDRSS2_PHY_441_DATA 0x00000000
+#define DDRSS2_PHY_442_DATA 0x00000000
+#define DDRSS2_PHY_443_DATA 0x00000000
+#define DDRSS2_PHY_444_DATA 0x00000000
+#define DDRSS2_PHY_445_DATA 0x00000000
+#define DDRSS2_PHY_446_DATA 0x00000000
+#define DDRSS2_PHY_447_DATA 0x00000000
+#define DDRSS2_PHY_448_DATA 0x00000000
+#define DDRSS2_PHY_449_DATA 0x00000000
+#define DDRSS2_PHY_450_DATA 0x00000000
+#define DDRSS2_PHY_451_DATA 0x00000000
+#define DDRSS2_PHY_452_DATA 0x00000000
+#define DDRSS2_PHY_453_DATA 0x00000000
+#define DDRSS2_PHY_454_DATA 0x00000000
+#define DDRSS2_PHY_455_DATA 0x00000000
+#define DDRSS2_PHY_456_DATA 0x00000000
+#define DDRSS2_PHY_457_DATA 0x00000000
+#define DDRSS2_PHY_458_DATA 0x00000000
+#define DDRSS2_PHY_459_DATA 0x00000000
+#define DDRSS2_PHY_460_DATA 0x00000000
+#define DDRSS2_PHY_461_DATA 0x00000000
+#define DDRSS2_PHY_462_DATA 0x00000000
+#define DDRSS2_PHY_463_DATA 0x00000000
+#define DDRSS2_PHY_464_DATA 0x00000000
+#define DDRSS2_PHY_465_DATA 0x00000000
+#define DDRSS2_PHY_466_DATA 0x00000000
+#define DDRSS2_PHY_467_DATA 0x00000000
+#define DDRSS2_PHY_468_DATA 0x00000000
+#define DDRSS2_PHY_469_DATA 0x00000000
+#define DDRSS2_PHY_470_DATA 0x00000000
+#define DDRSS2_PHY_471_DATA 0x00000000
+#define DDRSS2_PHY_472_DATA 0x00000000
+#define DDRSS2_PHY_473_DATA 0x00000000
+#define DDRSS2_PHY_474_DATA 0x00000000
+#define DDRSS2_PHY_475_DATA 0x00000000
+#define DDRSS2_PHY_476_DATA 0x00000000
+#define DDRSS2_PHY_477_DATA 0x00000000
+#define DDRSS2_PHY_478_DATA 0x00000000
+#define DDRSS2_PHY_479_DATA 0x00000000
+#define DDRSS2_PHY_480_DATA 0x00000000
+#define DDRSS2_PHY_481_DATA 0x00000000
+#define DDRSS2_PHY_482_DATA 0x00000000
+#define DDRSS2_PHY_483_DATA 0x00000000
+#define DDRSS2_PHY_484_DATA 0x00000000
+#define DDRSS2_PHY_485_DATA 0x00000000
+#define DDRSS2_PHY_486_DATA 0x00000000
+#define DDRSS2_PHY_487_DATA 0x00000000
+#define DDRSS2_PHY_488_DATA 0x00000000
+#define DDRSS2_PHY_489_DATA 0x00000000
+#define DDRSS2_PHY_490_DATA 0x00000000
+#define DDRSS2_PHY_491_DATA 0x00000000
+#define DDRSS2_PHY_492_DATA 0x00000000
+#define DDRSS2_PHY_493_DATA 0x00000000
+#define DDRSS2_PHY_494_DATA 0x00000000
+#define DDRSS2_PHY_495_DATA 0x00000000
+#define DDRSS2_PHY_496_DATA 0x00000000
+#define DDRSS2_PHY_497_DATA 0x00000000
+#define DDRSS2_PHY_498_DATA 0x00000000
+#define DDRSS2_PHY_499_DATA 0x00000000
+#define DDRSS2_PHY_500_DATA 0x00000000
+#define DDRSS2_PHY_501_DATA 0x00000000
+#define DDRSS2_PHY_502_DATA 0x00000000
+#define DDRSS2_PHY_503_DATA 0x00000000
+#define DDRSS2_PHY_504_DATA 0x00000000
+#define DDRSS2_PHY_505_DATA 0x00000000
+#define DDRSS2_PHY_506_DATA 0x00000000
+#define DDRSS2_PHY_507_DATA 0x00000000
+#define DDRSS2_PHY_508_DATA 0x00000000
+#define DDRSS2_PHY_509_DATA 0x00000000
+#define DDRSS2_PHY_510_DATA 0x00000000
+#define DDRSS2_PHY_511_DATA 0x00000000
+#define DDRSS2_PHY_512_DATA 0x000004F0
+#define DDRSS2_PHY_513_DATA 0x00000000
+#define DDRSS2_PHY_514_DATA 0x00030200
+#define DDRSS2_PHY_515_DATA 0x00000000
+#define DDRSS2_PHY_516_DATA 0x00000000
+#define DDRSS2_PHY_517_DATA 0x01030000
+#define DDRSS2_PHY_518_DATA 0x00010000
+#define DDRSS2_PHY_519_DATA 0x01030004
+#define DDRSS2_PHY_520_DATA 0x01000000
+#define DDRSS2_PHY_521_DATA 0x00000000
+#define DDRSS2_PHY_522_DATA 0x00000000
+#define DDRSS2_PHY_523_DATA 0x01000001
+#define DDRSS2_PHY_524_DATA 0x00000100
+#define DDRSS2_PHY_525_DATA 0x000800C0
+#define DDRSS2_PHY_526_DATA 0x060100CC
+#define DDRSS2_PHY_527_DATA 0x00030066
+#define DDRSS2_PHY_528_DATA 0x00000000
+#define DDRSS2_PHY_529_DATA 0x00000301
+#define DDRSS2_PHY_530_DATA 0x0000AAAA
+#define DDRSS2_PHY_531_DATA 0x00005555
+#define DDRSS2_PHY_532_DATA 0x0000B5B5
+#define DDRSS2_PHY_533_DATA 0x00004A4A
+#define DDRSS2_PHY_534_DATA 0x00005656
+#define DDRSS2_PHY_535_DATA 0x0000A9A9
+#define DDRSS2_PHY_536_DATA 0x0000A9A9
+#define DDRSS2_PHY_537_DATA 0x0000B5B5
+#define DDRSS2_PHY_538_DATA 0x00000000
+#define DDRSS2_PHY_539_DATA 0x00000000
+#define DDRSS2_PHY_540_DATA 0x2A000000
+#define DDRSS2_PHY_541_DATA 0x00000808
+#define DDRSS2_PHY_542_DATA 0x0F000000
+#define DDRSS2_PHY_543_DATA 0x00000F0F
+#define DDRSS2_PHY_544_DATA 0x10400000
+#define DDRSS2_PHY_545_DATA 0x0C002006
+#define DDRSS2_PHY_546_DATA 0x00000000
+#define DDRSS2_PHY_547_DATA 0x00000000
+#define DDRSS2_PHY_548_DATA 0x55555555
+#define DDRSS2_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_550_DATA 0x55555555
+#define DDRSS2_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_552_DATA 0x00005555
+#define DDRSS2_PHY_553_DATA 0x01000100
+#define DDRSS2_PHY_554_DATA 0x00800180
+#define DDRSS2_PHY_555_DATA 0x00000001
+#define DDRSS2_PHY_556_DATA 0x00000000
+#define DDRSS2_PHY_557_DATA 0x00000000
+#define DDRSS2_PHY_558_DATA 0x00000000
+#define DDRSS2_PHY_559_DATA 0x00000000
+#define DDRSS2_PHY_560_DATA 0x00000000
+#define DDRSS2_PHY_561_DATA 0x00000000
+#define DDRSS2_PHY_562_DATA 0x00000000
+#define DDRSS2_PHY_563_DATA 0x00000000
+#define DDRSS2_PHY_564_DATA 0x00000000
+#define DDRSS2_PHY_565_DATA 0x00000000
+#define DDRSS2_PHY_566_DATA 0x00000000
+#define DDRSS2_PHY_567_DATA 0x00000000
+#define DDRSS2_PHY_568_DATA 0x00000000
+#define DDRSS2_PHY_569_DATA 0x00000000
+#define DDRSS2_PHY_570_DATA 0x00000000
+#define DDRSS2_PHY_571_DATA 0x00000000
+#define DDRSS2_PHY_572_DATA 0x00000000
+#define DDRSS2_PHY_573_DATA 0x00000000
+#define DDRSS2_PHY_574_DATA 0x00000000
+#define DDRSS2_PHY_575_DATA 0x00000000
+#define DDRSS2_PHY_576_DATA 0x00000000
+#define DDRSS2_PHY_577_DATA 0x00000000
+#define DDRSS2_PHY_578_DATA 0x00000104
+#define DDRSS2_PHY_579_DATA 0x00000120
+#define DDRSS2_PHY_580_DATA 0x00000000
+#define DDRSS2_PHY_581_DATA 0x00000000
+#define DDRSS2_PHY_582_DATA 0x00000000
+#define DDRSS2_PHY_583_DATA 0x00000000
+#define DDRSS2_PHY_584_DATA 0x00000000
+#define DDRSS2_PHY_585_DATA 0x00000000
+#define DDRSS2_PHY_586_DATA 0x00000000
+#define DDRSS2_PHY_587_DATA 0x00000001
+#define DDRSS2_PHY_588_DATA 0x07FF0000
+#define DDRSS2_PHY_589_DATA 0x0080081F
+#define DDRSS2_PHY_590_DATA 0x00081020
+#define DDRSS2_PHY_591_DATA 0x04010000
+#define DDRSS2_PHY_592_DATA 0x00000000
+#define DDRSS2_PHY_593_DATA 0x00000000
+#define DDRSS2_PHY_594_DATA 0x00000000
+#define DDRSS2_PHY_595_DATA 0x00000100
+#define DDRSS2_PHY_596_DATA 0x01CC0C01
+#define DDRSS2_PHY_597_DATA 0x1003CC0C
+#define DDRSS2_PHY_598_DATA 0x20000140
+#define DDRSS2_PHY_599_DATA 0x07FF0200
+#define DDRSS2_PHY_600_DATA 0x0000DD01
+#define DDRSS2_PHY_601_DATA 0x10100303
+#define DDRSS2_PHY_602_DATA 0x10101010
+#define DDRSS2_PHY_603_DATA 0x10101010
+#define DDRSS2_PHY_604_DATA 0x00021010
+#define DDRSS2_PHY_605_DATA 0x00100010
+#define DDRSS2_PHY_606_DATA 0x00100010
+#define DDRSS2_PHY_607_DATA 0x00100010
+#define DDRSS2_PHY_608_DATA 0x00100010
+#define DDRSS2_PHY_609_DATA 0x00050010
+#define DDRSS2_PHY_610_DATA 0x51517041
+#define DDRSS2_PHY_611_DATA 0x31C06001
+#define DDRSS2_PHY_612_DATA 0x07AB0340
+#define DDRSS2_PHY_613_DATA 0x00C0C001
+#define DDRSS2_PHY_614_DATA 0x0E0D0001
+#define DDRSS2_PHY_615_DATA 0x10001000
+#define DDRSS2_PHY_616_DATA 0x0C083E42
+#define DDRSS2_PHY_617_DATA 0x0F0C3701
+#define DDRSS2_PHY_618_DATA 0x01000140
+#define DDRSS2_PHY_619_DATA 0x0C000420
+#define DDRSS2_PHY_620_DATA 0x00000198
+#define DDRSS2_PHY_621_DATA 0x0A0000D0
+#define DDRSS2_PHY_622_DATA 0x00030200
+#define DDRSS2_PHY_623_DATA 0x02800000
+#define DDRSS2_PHY_624_DATA 0x80800000
+#define DDRSS2_PHY_625_DATA 0x000E2010
+#define DDRSS2_PHY_626_DATA 0x76543210
+#define DDRSS2_PHY_627_DATA 0x00000008
+#define DDRSS2_PHY_628_DATA 0x02800280
+#define DDRSS2_PHY_629_DATA 0x02800280
+#define DDRSS2_PHY_630_DATA 0x02800280
+#define DDRSS2_PHY_631_DATA 0x02800280
+#define DDRSS2_PHY_632_DATA 0x00000280
+#define DDRSS2_PHY_633_DATA 0x0000A000
+#define DDRSS2_PHY_634_DATA 0x00A000A0
+#define DDRSS2_PHY_635_DATA 0x00A000A0
+#define DDRSS2_PHY_636_DATA 0x00A000A0
+#define DDRSS2_PHY_637_DATA 0x00A000A0
+#define DDRSS2_PHY_638_DATA 0x00A000A0
+#define DDRSS2_PHY_639_DATA 0x00A000A0
+#define DDRSS2_PHY_640_DATA 0x00A000A0
+#define DDRSS2_PHY_641_DATA 0x00A000A0
+#define DDRSS2_PHY_642_DATA 0x01C200A0
+#define DDRSS2_PHY_643_DATA 0x01A00005
+#define DDRSS2_PHY_644_DATA 0x00000000
+#define DDRSS2_PHY_645_DATA 0x00000000
+#define DDRSS2_PHY_646_DATA 0x00080200
+#define DDRSS2_PHY_647_DATA 0x00000000
+#define DDRSS2_PHY_648_DATA 0x20202000
+#define DDRSS2_PHY_649_DATA 0x20202020
+#define DDRSS2_PHY_650_DATA 0xF0F02020
+#define DDRSS2_PHY_651_DATA 0x00000000
+#define DDRSS2_PHY_652_DATA 0x00000000
+#define DDRSS2_PHY_653_DATA 0x00000000
+#define DDRSS2_PHY_654_DATA 0x00000000
+#define DDRSS2_PHY_655_DATA 0x00000000
+#define DDRSS2_PHY_656_DATA 0x00000000
+#define DDRSS2_PHY_657_DATA 0x00000000
+#define DDRSS2_PHY_658_DATA 0x00000000
+#define DDRSS2_PHY_659_DATA 0x00000000
+#define DDRSS2_PHY_660_DATA 0x00000000
+#define DDRSS2_PHY_661_DATA 0x00000000
+#define DDRSS2_PHY_662_DATA 0x00000000
+#define DDRSS2_PHY_663_DATA 0x00000000
+#define DDRSS2_PHY_664_DATA 0x00000000
+#define DDRSS2_PHY_665_DATA 0x00000000
+#define DDRSS2_PHY_666_DATA 0x00000000
+#define DDRSS2_PHY_667_DATA 0x00000000
+#define DDRSS2_PHY_668_DATA 0x00000000
+#define DDRSS2_PHY_669_DATA 0x00000000
+#define DDRSS2_PHY_670_DATA 0x00000000
+#define DDRSS2_PHY_671_DATA 0x00000000
+#define DDRSS2_PHY_672_DATA 0x00000000
+#define DDRSS2_PHY_673_DATA 0x00000000
+#define DDRSS2_PHY_674_DATA 0x00000000
+#define DDRSS2_PHY_675_DATA 0x00000000
+#define DDRSS2_PHY_676_DATA 0x00000000
+#define DDRSS2_PHY_677_DATA 0x00000000
+#define DDRSS2_PHY_678_DATA 0x00000000
+#define DDRSS2_PHY_679_DATA 0x00000000
+#define DDRSS2_PHY_680_DATA 0x00000000
+#define DDRSS2_PHY_681_DATA 0x00000000
+#define DDRSS2_PHY_682_DATA 0x00000000
+#define DDRSS2_PHY_683_DATA 0x00000000
+#define DDRSS2_PHY_684_DATA 0x00000000
+#define DDRSS2_PHY_685_DATA 0x00000000
+#define DDRSS2_PHY_686_DATA 0x00000000
+#define DDRSS2_PHY_687_DATA 0x00000000
+#define DDRSS2_PHY_688_DATA 0x00000000
+#define DDRSS2_PHY_689_DATA 0x00000000
+#define DDRSS2_PHY_690_DATA 0x00000000
+#define DDRSS2_PHY_691_DATA 0x00000000
+#define DDRSS2_PHY_692_DATA 0x00000000
+#define DDRSS2_PHY_693_DATA 0x00000000
+#define DDRSS2_PHY_694_DATA 0x00000000
+#define DDRSS2_PHY_695_DATA 0x00000000
+#define DDRSS2_PHY_696_DATA 0x00000000
+#define DDRSS2_PHY_697_DATA 0x00000000
+#define DDRSS2_PHY_698_DATA 0x00000000
+#define DDRSS2_PHY_699_DATA 0x00000000
+#define DDRSS2_PHY_700_DATA 0x00000000
+#define DDRSS2_PHY_701_DATA 0x00000000
+#define DDRSS2_PHY_702_DATA 0x00000000
+#define DDRSS2_PHY_703_DATA 0x00000000
+#define DDRSS2_PHY_704_DATA 0x00000000
+#define DDRSS2_PHY_705_DATA 0x00000000
+#define DDRSS2_PHY_706_DATA 0x00000000
+#define DDRSS2_PHY_707_DATA 0x00000000
+#define DDRSS2_PHY_708_DATA 0x00000000
+#define DDRSS2_PHY_709_DATA 0x00000000
+#define DDRSS2_PHY_710_DATA 0x00000000
+#define DDRSS2_PHY_711_DATA 0x00000000
+#define DDRSS2_PHY_712_DATA 0x00000000
+#define DDRSS2_PHY_713_DATA 0x00000000
+#define DDRSS2_PHY_714_DATA 0x00000000
+#define DDRSS2_PHY_715_DATA 0x00000000
+#define DDRSS2_PHY_716_DATA 0x00000000
+#define DDRSS2_PHY_717_DATA 0x00000000
+#define DDRSS2_PHY_718_DATA 0x00000000
+#define DDRSS2_PHY_719_DATA 0x00000000
+#define DDRSS2_PHY_720_DATA 0x00000000
+#define DDRSS2_PHY_721_DATA 0x00000000
+#define DDRSS2_PHY_722_DATA 0x00000000
+#define DDRSS2_PHY_723_DATA 0x00000000
+#define DDRSS2_PHY_724_DATA 0x00000000
+#define DDRSS2_PHY_725_DATA 0x00000000
+#define DDRSS2_PHY_726_DATA 0x00000000
+#define DDRSS2_PHY_727_DATA 0x00000000
+#define DDRSS2_PHY_728_DATA 0x00000000
+#define DDRSS2_PHY_729_DATA 0x00000000
+#define DDRSS2_PHY_730_DATA 0x00000000
+#define DDRSS2_PHY_731_DATA 0x00000000
+#define DDRSS2_PHY_732_DATA 0x00000000
+#define DDRSS2_PHY_733_DATA 0x00000000
+#define DDRSS2_PHY_734_DATA 0x00000000
+#define DDRSS2_PHY_735_DATA 0x00000000
+#define DDRSS2_PHY_736_DATA 0x00000000
+#define DDRSS2_PHY_737_DATA 0x00000000
+#define DDRSS2_PHY_738_DATA 0x00000000
+#define DDRSS2_PHY_739_DATA 0x00000000
+#define DDRSS2_PHY_740_DATA 0x00000000
+#define DDRSS2_PHY_741_DATA 0x00000000
+#define DDRSS2_PHY_742_DATA 0x00000000
+#define DDRSS2_PHY_743_DATA 0x00000000
+#define DDRSS2_PHY_744_DATA 0x00000000
+#define DDRSS2_PHY_745_DATA 0x00000000
+#define DDRSS2_PHY_746_DATA 0x00000000
+#define DDRSS2_PHY_747_DATA 0x00000000
+#define DDRSS2_PHY_748_DATA 0x00000000
+#define DDRSS2_PHY_749_DATA 0x00000000
+#define DDRSS2_PHY_750_DATA 0x00000000
+#define DDRSS2_PHY_751_DATA 0x00000000
+#define DDRSS2_PHY_752_DATA 0x00000000
+#define DDRSS2_PHY_753_DATA 0x00000000
+#define DDRSS2_PHY_754_DATA 0x00000000
+#define DDRSS2_PHY_755_DATA 0x00000000
+#define DDRSS2_PHY_756_DATA 0x00000000
+#define DDRSS2_PHY_757_DATA 0x00000000
+#define DDRSS2_PHY_758_DATA 0x00000000
+#define DDRSS2_PHY_759_DATA 0x00000000
+#define DDRSS2_PHY_760_DATA 0x00000000
+#define DDRSS2_PHY_761_DATA 0x00000000
+#define DDRSS2_PHY_762_DATA 0x00000000
+#define DDRSS2_PHY_763_DATA 0x00000000
+#define DDRSS2_PHY_764_DATA 0x00000000
+#define DDRSS2_PHY_765_DATA 0x00000000
+#define DDRSS2_PHY_766_DATA 0x00000000
+#define DDRSS2_PHY_767_DATA 0x00000000
+#define DDRSS2_PHY_768_DATA 0x000004F0
+#define DDRSS2_PHY_769_DATA 0x00000000
+#define DDRSS2_PHY_770_DATA 0x00030200
+#define DDRSS2_PHY_771_DATA 0x00000000
+#define DDRSS2_PHY_772_DATA 0x00000000
+#define DDRSS2_PHY_773_DATA 0x01030000
+#define DDRSS2_PHY_774_DATA 0x00010000
+#define DDRSS2_PHY_775_DATA 0x01030004
+#define DDRSS2_PHY_776_DATA 0x01000000
+#define DDRSS2_PHY_777_DATA 0x00000000
+#define DDRSS2_PHY_778_DATA 0x00000000
+#define DDRSS2_PHY_779_DATA 0x01000001
+#define DDRSS2_PHY_780_DATA 0x00000100
+#define DDRSS2_PHY_781_DATA 0x000800C0
+#define DDRSS2_PHY_782_DATA 0x060100CC
+#define DDRSS2_PHY_783_DATA 0x00030066
+#define DDRSS2_PHY_784_DATA 0x00000000
+#define DDRSS2_PHY_785_DATA 0x00000301
+#define DDRSS2_PHY_786_DATA 0x0000AAAA
+#define DDRSS2_PHY_787_DATA 0x00005555
+#define DDRSS2_PHY_788_DATA 0x0000B5B5
+#define DDRSS2_PHY_789_DATA 0x00004A4A
+#define DDRSS2_PHY_790_DATA 0x00005656
+#define DDRSS2_PHY_791_DATA 0x0000A9A9
+#define DDRSS2_PHY_792_DATA 0x0000A9A9
+#define DDRSS2_PHY_793_DATA 0x0000B5B5
+#define DDRSS2_PHY_794_DATA 0x00000000
+#define DDRSS2_PHY_795_DATA 0x00000000
+#define DDRSS2_PHY_796_DATA 0x2A000000
+#define DDRSS2_PHY_797_DATA 0x00000808
+#define DDRSS2_PHY_798_DATA 0x0F000000
+#define DDRSS2_PHY_799_DATA 0x00000F0F
+#define DDRSS2_PHY_800_DATA 0x10400000
+#define DDRSS2_PHY_801_DATA 0x0C002006
+#define DDRSS2_PHY_802_DATA 0x00000000
+#define DDRSS2_PHY_803_DATA 0x00000000
+#define DDRSS2_PHY_804_DATA 0x55555555
+#define DDRSS2_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_806_DATA 0x55555555
+#define DDRSS2_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_808_DATA 0x00005555
+#define DDRSS2_PHY_809_DATA 0x01000100
+#define DDRSS2_PHY_810_DATA 0x00800180
+#define DDRSS2_PHY_811_DATA 0x00000000
+#define DDRSS2_PHY_812_DATA 0x00000000
+#define DDRSS2_PHY_813_DATA 0x00000000
+#define DDRSS2_PHY_814_DATA 0x00000000
+#define DDRSS2_PHY_815_DATA 0x00000000
+#define DDRSS2_PHY_816_DATA 0x00000000
+#define DDRSS2_PHY_817_DATA 0x00000000
+#define DDRSS2_PHY_818_DATA 0x00000000
+#define DDRSS2_PHY_819_DATA 0x00000000
+#define DDRSS2_PHY_820_DATA 0x00000000
+#define DDRSS2_PHY_821_DATA 0x00000000
+#define DDRSS2_PHY_822_DATA 0x00000000
+#define DDRSS2_PHY_823_DATA 0x00000000
+#define DDRSS2_PHY_824_DATA 0x00000000
+#define DDRSS2_PHY_825_DATA 0x00000000
+#define DDRSS2_PHY_826_DATA 0x00000000
+#define DDRSS2_PHY_827_DATA 0x00000000
+#define DDRSS2_PHY_828_DATA 0x00000000
+#define DDRSS2_PHY_829_DATA 0x00000000
+#define DDRSS2_PHY_830_DATA 0x00000000
+#define DDRSS2_PHY_831_DATA 0x00000000
+#define DDRSS2_PHY_832_DATA 0x00000000
+#define DDRSS2_PHY_833_DATA 0x00000000
+#define DDRSS2_PHY_834_DATA 0x00000104
+#define DDRSS2_PHY_835_DATA 0x00000120
+#define DDRSS2_PHY_836_DATA 0x00000000
+#define DDRSS2_PHY_837_DATA 0x00000000
+#define DDRSS2_PHY_838_DATA 0x00000000
+#define DDRSS2_PHY_839_DATA 0x00000000
+#define DDRSS2_PHY_840_DATA 0x00000000
+#define DDRSS2_PHY_841_DATA 0x00000000
+#define DDRSS2_PHY_842_DATA 0x00000000
+#define DDRSS2_PHY_843_DATA 0x00000001
+#define DDRSS2_PHY_844_DATA 0x07FF0000
+#define DDRSS2_PHY_845_DATA 0x0080081F
+#define DDRSS2_PHY_846_DATA 0x00081020
+#define DDRSS2_PHY_847_DATA 0x04010000
+#define DDRSS2_PHY_848_DATA 0x00000000
+#define DDRSS2_PHY_849_DATA 0x00000000
+#define DDRSS2_PHY_850_DATA 0x00000000
+#define DDRSS2_PHY_851_DATA 0x00000100
+#define DDRSS2_PHY_852_DATA 0x01CC0C01
+#define DDRSS2_PHY_853_DATA 0x1003CC0C
+#define DDRSS2_PHY_854_DATA 0x20000140
+#define DDRSS2_PHY_855_DATA 0x07FF0200
+#define DDRSS2_PHY_856_DATA 0x0000DD01
+#define DDRSS2_PHY_857_DATA 0x10100303
+#define DDRSS2_PHY_858_DATA 0x10101010
+#define DDRSS2_PHY_859_DATA 0x10101010
+#define DDRSS2_PHY_860_DATA 0x00021010
+#define DDRSS2_PHY_861_DATA 0x00100010
+#define DDRSS2_PHY_862_DATA 0x00100010
+#define DDRSS2_PHY_863_DATA 0x00100010
+#define DDRSS2_PHY_864_DATA 0x00100010
+#define DDRSS2_PHY_865_DATA 0x00050010
+#define DDRSS2_PHY_866_DATA 0x51517041
+#define DDRSS2_PHY_867_DATA 0x31C06001
+#define DDRSS2_PHY_868_DATA 0x07AB0340
+#define DDRSS2_PHY_869_DATA 0x00C0C001
+#define DDRSS2_PHY_870_DATA 0x0E0D0001
+#define DDRSS2_PHY_871_DATA 0x10001000
+#define DDRSS2_PHY_872_DATA 0x0C083E42
+#define DDRSS2_PHY_873_DATA 0x0F0C3701
+#define DDRSS2_PHY_874_DATA 0x01000140
+#define DDRSS2_PHY_875_DATA 0x0C000420
+#define DDRSS2_PHY_876_DATA 0x00000198
+#define DDRSS2_PHY_877_DATA 0x0A0000D0
+#define DDRSS2_PHY_878_DATA 0x00030200
+#define DDRSS2_PHY_879_DATA 0x02800000
+#define DDRSS2_PHY_880_DATA 0x80800000
+#define DDRSS2_PHY_881_DATA 0x000E2010
+#define DDRSS2_PHY_882_DATA 0x76543210
+#define DDRSS2_PHY_883_DATA 0x00000008
+#define DDRSS2_PHY_884_DATA 0x02800280
+#define DDRSS2_PHY_885_DATA 0x02800280
+#define DDRSS2_PHY_886_DATA 0x02800280
+#define DDRSS2_PHY_887_DATA 0x02800280
+#define DDRSS2_PHY_888_DATA 0x00000280
+#define DDRSS2_PHY_889_DATA 0x0000A000
+#define DDRSS2_PHY_890_DATA 0x00A000A0
+#define DDRSS2_PHY_891_DATA 0x00A000A0
+#define DDRSS2_PHY_892_DATA 0x00A000A0
+#define DDRSS2_PHY_893_DATA 0x00A000A0
+#define DDRSS2_PHY_894_DATA 0x00A000A0
+#define DDRSS2_PHY_895_DATA 0x00A000A0
+#define DDRSS2_PHY_896_DATA 0x00A000A0
+#define DDRSS2_PHY_897_DATA 0x00A000A0
+#define DDRSS2_PHY_898_DATA 0x01C200A0
+#define DDRSS2_PHY_899_DATA 0x01A00005
+#define DDRSS2_PHY_900_DATA 0x00000000
+#define DDRSS2_PHY_901_DATA 0x00000000
+#define DDRSS2_PHY_902_DATA 0x00080200
+#define DDRSS2_PHY_903_DATA 0x00000000
+#define DDRSS2_PHY_904_DATA 0x20202000
+#define DDRSS2_PHY_905_DATA 0x20202020
+#define DDRSS2_PHY_906_DATA 0xF0F02020
+#define DDRSS2_PHY_907_DATA 0x00000000
+#define DDRSS2_PHY_908_DATA 0x00000000
+#define DDRSS2_PHY_909_DATA 0x00000000
+#define DDRSS2_PHY_910_DATA 0x00000000
+#define DDRSS2_PHY_911_DATA 0x00000000
+#define DDRSS2_PHY_912_DATA 0x00000000
+#define DDRSS2_PHY_913_DATA 0x00000000
+#define DDRSS2_PHY_914_DATA 0x00000000
+#define DDRSS2_PHY_915_DATA 0x00000000
+#define DDRSS2_PHY_916_DATA 0x00000000
+#define DDRSS2_PHY_917_DATA 0x00000000
+#define DDRSS2_PHY_918_DATA 0x00000000
+#define DDRSS2_PHY_919_DATA 0x00000000
+#define DDRSS2_PHY_920_DATA 0x00000000
+#define DDRSS2_PHY_921_DATA 0x00000000
+#define DDRSS2_PHY_922_DATA 0x00000000
+#define DDRSS2_PHY_923_DATA 0x00000000
+#define DDRSS2_PHY_924_DATA 0x00000000
+#define DDRSS2_PHY_925_DATA 0x00000000
+#define DDRSS2_PHY_926_DATA 0x00000000
+#define DDRSS2_PHY_927_DATA 0x00000000
+#define DDRSS2_PHY_928_DATA 0x00000000
+#define DDRSS2_PHY_929_DATA 0x00000000
+#define DDRSS2_PHY_930_DATA 0x00000000
+#define DDRSS2_PHY_931_DATA 0x00000000
+#define DDRSS2_PHY_932_DATA 0x00000000
+#define DDRSS2_PHY_933_DATA 0x00000000
+#define DDRSS2_PHY_934_DATA 0x00000000
+#define DDRSS2_PHY_935_DATA 0x00000000
+#define DDRSS2_PHY_936_DATA 0x00000000
+#define DDRSS2_PHY_937_DATA 0x00000000
+#define DDRSS2_PHY_938_DATA 0x00000000
+#define DDRSS2_PHY_939_DATA 0x00000000
+#define DDRSS2_PHY_940_DATA 0x00000000
+#define DDRSS2_PHY_941_DATA 0x00000000
+#define DDRSS2_PHY_942_DATA 0x00000000
+#define DDRSS2_PHY_943_DATA 0x00000000
+#define DDRSS2_PHY_944_DATA 0x00000000
+#define DDRSS2_PHY_945_DATA 0x00000000
+#define DDRSS2_PHY_946_DATA 0x00000000
+#define DDRSS2_PHY_947_DATA 0x00000000
+#define DDRSS2_PHY_948_DATA 0x00000000
+#define DDRSS2_PHY_949_DATA 0x00000000
+#define DDRSS2_PHY_950_DATA 0x00000000
+#define DDRSS2_PHY_951_DATA 0x00000000
+#define DDRSS2_PHY_952_DATA 0x00000000
+#define DDRSS2_PHY_953_DATA 0x00000000
+#define DDRSS2_PHY_954_DATA 0x00000000
+#define DDRSS2_PHY_955_DATA 0x00000000
+#define DDRSS2_PHY_956_DATA 0x00000000
+#define DDRSS2_PHY_957_DATA 0x00000000
+#define DDRSS2_PHY_958_DATA 0x00000000
+#define DDRSS2_PHY_959_DATA 0x00000000
+#define DDRSS2_PHY_960_DATA 0x00000000
+#define DDRSS2_PHY_961_DATA 0x00000000
+#define DDRSS2_PHY_962_DATA 0x00000000
+#define DDRSS2_PHY_963_DATA 0x00000000
+#define DDRSS2_PHY_964_DATA 0x00000000
+#define DDRSS2_PHY_965_DATA 0x00000000
+#define DDRSS2_PHY_966_DATA 0x00000000
+#define DDRSS2_PHY_967_DATA 0x00000000
+#define DDRSS2_PHY_968_DATA 0x00000000
+#define DDRSS2_PHY_969_DATA 0x00000000
+#define DDRSS2_PHY_970_DATA 0x00000000
+#define DDRSS2_PHY_971_DATA 0x00000000
+#define DDRSS2_PHY_972_DATA 0x00000000
+#define DDRSS2_PHY_973_DATA 0x00000000
+#define DDRSS2_PHY_974_DATA 0x00000000
+#define DDRSS2_PHY_975_DATA 0x00000000
+#define DDRSS2_PHY_976_DATA 0x00000000
+#define DDRSS2_PHY_977_DATA 0x00000000
+#define DDRSS2_PHY_978_DATA 0x00000000
+#define DDRSS2_PHY_979_DATA 0x00000000
+#define DDRSS2_PHY_980_DATA 0x00000000
+#define DDRSS2_PHY_981_DATA 0x00000000
+#define DDRSS2_PHY_982_DATA 0x00000000
+#define DDRSS2_PHY_983_DATA 0x00000000
+#define DDRSS2_PHY_984_DATA 0x00000000
+#define DDRSS2_PHY_985_DATA 0x00000000
+#define DDRSS2_PHY_986_DATA 0x00000000
+#define DDRSS2_PHY_987_DATA 0x00000000
+#define DDRSS2_PHY_988_DATA 0x00000000
+#define DDRSS2_PHY_989_DATA 0x00000000
+#define DDRSS2_PHY_990_DATA 0x00000000
+#define DDRSS2_PHY_991_DATA 0x00000000
+#define DDRSS2_PHY_992_DATA 0x00000000
+#define DDRSS2_PHY_993_DATA 0x00000000
+#define DDRSS2_PHY_994_DATA 0x00000000
+#define DDRSS2_PHY_995_DATA 0x00000000
+#define DDRSS2_PHY_996_DATA 0x00000000
+#define DDRSS2_PHY_997_DATA 0x00000000
+#define DDRSS2_PHY_998_DATA 0x00000000
+#define DDRSS2_PHY_999_DATA 0x00000000
+#define DDRSS2_PHY_1000_DATA 0x00000000
+#define DDRSS2_PHY_1001_DATA 0x00000000
+#define DDRSS2_PHY_1002_DATA 0x00000000
+#define DDRSS2_PHY_1003_DATA 0x00000000
+#define DDRSS2_PHY_1004_DATA 0x00000000
+#define DDRSS2_PHY_1005_DATA 0x00000000
+#define DDRSS2_PHY_1006_DATA 0x00000000
+#define DDRSS2_PHY_1007_DATA 0x00000000
+#define DDRSS2_PHY_1008_DATA 0x00000000
+#define DDRSS2_PHY_1009_DATA 0x00000000
+#define DDRSS2_PHY_1010_DATA 0x00000000
+#define DDRSS2_PHY_1011_DATA 0x00000000
+#define DDRSS2_PHY_1012_DATA 0x00000000
+#define DDRSS2_PHY_1013_DATA 0x00000000
+#define DDRSS2_PHY_1014_DATA 0x00000000
+#define DDRSS2_PHY_1015_DATA 0x00000000
+#define DDRSS2_PHY_1016_DATA 0x00000000
+#define DDRSS2_PHY_1017_DATA 0x00000000
+#define DDRSS2_PHY_1018_DATA 0x00000000
+#define DDRSS2_PHY_1019_DATA 0x00000000
+#define DDRSS2_PHY_1020_DATA 0x00000000
+#define DDRSS2_PHY_1021_DATA 0x00000000
+#define DDRSS2_PHY_1022_DATA 0x00000000
+#define DDRSS2_PHY_1023_DATA 0x00000000
+#define DDRSS2_PHY_1024_DATA 0x00000000
+#define DDRSS2_PHY_1025_DATA 0x00000000
+#define DDRSS2_PHY_1026_DATA 0x00000000
+#define DDRSS2_PHY_1027_DATA 0x00000000
+#define DDRSS2_PHY_1028_DATA 0x00000000
+#define DDRSS2_PHY_1029_DATA 0x00000100
+#define DDRSS2_PHY_1030_DATA 0x00000200
+#define DDRSS2_PHY_1031_DATA 0x00000000
+#define DDRSS2_PHY_1032_DATA 0x00000000
+#define DDRSS2_PHY_1033_DATA 0x00000000
+#define DDRSS2_PHY_1034_DATA 0x00000000
+#define DDRSS2_PHY_1035_DATA 0x00400000
+#define DDRSS2_PHY_1036_DATA 0x00000080
+#define DDRSS2_PHY_1037_DATA 0x00DCBA98
+#define DDRSS2_PHY_1038_DATA 0x03000000
+#define DDRSS2_PHY_1039_DATA 0x00200000
+#define DDRSS2_PHY_1040_DATA 0x00000000
+#define DDRSS2_PHY_1041_DATA 0x00000000
+#define DDRSS2_PHY_1042_DATA 0x00000000
+#define DDRSS2_PHY_1043_DATA 0x00000000
+#define DDRSS2_PHY_1044_DATA 0x00000000
+#define DDRSS2_PHY_1045_DATA 0x0000002A
+#define DDRSS2_PHY_1046_DATA 0x00000015
+#define DDRSS2_PHY_1047_DATA 0x00000015
+#define DDRSS2_PHY_1048_DATA 0x0000002A
+#define DDRSS2_PHY_1049_DATA 0x00000033
+#define DDRSS2_PHY_1050_DATA 0x0000000C
+#define DDRSS2_PHY_1051_DATA 0x0000000C
+#define DDRSS2_PHY_1052_DATA 0x00000033
+#define DDRSS2_PHY_1053_DATA 0x00543210
+#define DDRSS2_PHY_1054_DATA 0x003F0000
+#define DDRSS2_PHY_1055_DATA 0x000F013F
+#define DDRSS2_PHY_1056_DATA 0x20202003
+#define DDRSS2_PHY_1057_DATA 0x00202020
+#define DDRSS2_PHY_1058_DATA 0x20008008
+#define DDRSS2_PHY_1059_DATA 0x00000810
+#define DDRSS2_PHY_1060_DATA 0x00000F00
+#define DDRSS2_PHY_1061_DATA 0x00000000
+#define DDRSS2_PHY_1062_DATA 0x00000000
+#define DDRSS2_PHY_1063_DATA 0x00000000
+#define DDRSS2_PHY_1064_DATA 0x000305CC
+#define DDRSS2_PHY_1065_DATA 0x00030000
+#define DDRSS2_PHY_1066_DATA 0x00000300
+#define DDRSS2_PHY_1067_DATA 0x00000300
+#define DDRSS2_PHY_1068_DATA 0x00000300
+#define DDRSS2_PHY_1069_DATA 0x00000300
+#define DDRSS2_PHY_1070_DATA 0x00000300
+#define DDRSS2_PHY_1071_DATA 0x42080010
+#define DDRSS2_PHY_1072_DATA 0x0000803E
+#define DDRSS2_PHY_1073_DATA 0x00000001
+#define DDRSS2_PHY_1074_DATA 0x01000102
+#define DDRSS2_PHY_1075_DATA 0x00008000
+#define DDRSS2_PHY_1076_DATA 0x00000000
+#define DDRSS2_PHY_1077_DATA 0x00000000
+#define DDRSS2_PHY_1078_DATA 0x00000000
+#define DDRSS2_PHY_1079_DATA 0x00000000
+#define DDRSS2_PHY_1080_DATA 0x00000000
+#define DDRSS2_PHY_1081_DATA 0x00000000
+#define DDRSS2_PHY_1082_DATA 0x00000000
+#define DDRSS2_PHY_1083_DATA 0x00000000
+#define DDRSS2_PHY_1084_DATA 0x00000000
+#define DDRSS2_PHY_1085_DATA 0x00000000
+#define DDRSS2_PHY_1086_DATA 0x00000000
+#define DDRSS2_PHY_1087_DATA 0x00000000
+#define DDRSS2_PHY_1088_DATA 0x00000000
+#define DDRSS2_PHY_1089_DATA 0x00000000
+#define DDRSS2_PHY_1090_DATA 0x00000000
+#define DDRSS2_PHY_1091_DATA 0x00000000
+#define DDRSS2_PHY_1092_DATA 0x00000000
+#define DDRSS2_PHY_1093_DATA 0x00000000
+#define DDRSS2_PHY_1094_DATA 0x00000000
+#define DDRSS2_PHY_1095_DATA 0x00000000
+#define DDRSS2_PHY_1096_DATA 0x00000000
+#define DDRSS2_PHY_1097_DATA 0x00000000
+#define DDRSS2_PHY_1098_DATA 0x00000000
+#define DDRSS2_PHY_1099_DATA 0x00000000
+#define DDRSS2_PHY_1100_DATA 0x00000000
+#define DDRSS2_PHY_1101_DATA 0x00000000
+#define DDRSS2_PHY_1102_DATA 0x00000000
+#define DDRSS2_PHY_1103_DATA 0x00000000
+#define DDRSS2_PHY_1104_DATA 0x00000000
+#define DDRSS2_PHY_1105_DATA 0x00000000
+#define DDRSS2_PHY_1106_DATA 0x00000000
+#define DDRSS2_PHY_1107_DATA 0x00000000
+#define DDRSS2_PHY_1108_DATA 0x00000000
+#define DDRSS2_PHY_1109_DATA 0x00000000
+#define DDRSS2_PHY_1110_DATA 0x00000000
+#define DDRSS2_PHY_1111_DATA 0x00000000
+#define DDRSS2_PHY_1112_DATA 0x00000000
+#define DDRSS2_PHY_1113_DATA 0x00000000
+#define DDRSS2_PHY_1114_DATA 0x00000000
+#define DDRSS2_PHY_1115_DATA 0x00000000
+#define DDRSS2_PHY_1116_DATA 0x00000000
+#define DDRSS2_PHY_1117_DATA 0x00000000
+#define DDRSS2_PHY_1118_DATA 0x00000000
+#define DDRSS2_PHY_1119_DATA 0x00000000
+#define DDRSS2_PHY_1120_DATA 0x00000000
+#define DDRSS2_PHY_1121_DATA 0x00000000
+#define DDRSS2_PHY_1122_DATA 0x00000000
+#define DDRSS2_PHY_1123_DATA 0x00000000
+#define DDRSS2_PHY_1124_DATA 0x00000000
+#define DDRSS2_PHY_1125_DATA 0x00000000
+#define DDRSS2_PHY_1126_DATA 0x00000000
+#define DDRSS2_PHY_1127_DATA 0x00000000
+#define DDRSS2_PHY_1128_DATA 0x00000000
+#define DDRSS2_PHY_1129_DATA 0x00000000
+#define DDRSS2_PHY_1130_DATA 0x00000000
+#define DDRSS2_PHY_1131_DATA 0x00000000
+#define DDRSS2_PHY_1132_DATA 0x00000000
+#define DDRSS2_PHY_1133_DATA 0x00000000
+#define DDRSS2_PHY_1134_DATA 0x00000000
+#define DDRSS2_PHY_1135_DATA 0x00000000
+#define DDRSS2_PHY_1136_DATA 0x00000000
+#define DDRSS2_PHY_1137_DATA 0x00000000
+#define DDRSS2_PHY_1138_DATA 0x00000000
+#define DDRSS2_PHY_1139_DATA 0x00000000
+#define DDRSS2_PHY_1140_DATA 0x00000000
+#define DDRSS2_PHY_1141_DATA 0x00000000
+#define DDRSS2_PHY_1142_DATA 0x00000000
+#define DDRSS2_PHY_1143_DATA 0x00000000
+#define DDRSS2_PHY_1144_DATA 0x00000000
+#define DDRSS2_PHY_1145_DATA 0x00000000
+#define DDRSS2_PHY_1146_DATA 0x00000000
+#define DDRSS2_PHY_1147_DATA 0x00000000
+#define DDRSS2_PHY_1148_DATA 0x00000000
+#define DDRSS2_PHY_1149_DATA 0x00000000
+#define DDRSS2_PHY_1150_DATA 0x00000000
+#define DDRSS2_PHY_1151_DATA 0x00000000
+#define DDRSS2_PHY_1152_DATA 0x00000000
+#define DDRSS2_PHY_1153_DATA 0x00000000
+#define DDRSS2_PHY_1154_DATA 0x00000000
+#define DDRSS2_PHY_1155_DATA 0x00000000
+#define DDRSS2_PHY_1156_DATA 0x00000000
+#define DDRSS2_PHY_1157_DATA 0x00000000
+#define DDRSS2_PHY_1158_DATA 0x00000000
+#define DDRSS2_PHY_1159_DATA 0x00000000
+#define DDRSS2_PHY_1160_DATA 0x00000000
+#define DDRSS2_PHY_1161_DATA 0x00000000
+#define DDRSS2_PHY_1162_DATA 0x00000000
+#define DDRSS2_PHY_1163_DATA 0x00000000
+#define DDRSS2_PHY_1164_DATA 0x00000000
+#define DDRSS2_PHY_1165_DATA 0x00000000
+#define DDRSS2_PHY_1166_DATA 0x00000000
+#define DDRSS2_PHY_1167_DATA 0x00000000
+#define DDRSS2_PHY_1168_DATA 0x00000000
+#define DDRSS2_PHY_1169_DATA 0x00000000
+#define DDRSS2_PHY_1170_DATA 0x00000000
+#define DDRSS2_PHY_1171_DATA 0x00000000
+#define DDRSS2_PHY_1172_DATA 0x00000000
+#define DDRSS2_PHY_1173_DATA 0x00000000
+#define DDRSS2_PHY_1174_DATA 0x00000000
+#define DDRSS2_PHY_1175_DATA 0x00000000
+#define DDRSS2_PHY_1176_DATA 0x00000000
+#define DDRSS2_PHY_1177_DATA 0x00000000
+#define DDRSS2_PHY_1178_DATA 0x00000000
+#define DDRSS2_PHY_1179_DATA 0x00000000
+#define DDRSS2_PHY_1180_DATA 0x00000000
+#define DDRSS2_PHY_1181_DATA 0x00000000
+#define DDRSS2_PHY_1182_DATA 0x00000000
+#define DDRSS2_PHY_1183_DATA 0x00000000
+#define DDRSS2_PHY_1184_DATA 0x00000000
+#define DDRSS2_PHY_1185_DATA 0x00000000
+#define DDRSS2_PHY_1186_DATA 0x00000000
+#define DDRSS2_PHY_1187_DATA 0x00000000
+#define DDRSS2_PHY_1188_DATA 0x00000000
+#define DDRSS2_PHY_1189_DATA 0x00000000
+#define DDRSS2_PHY_1190_DATA 0x00000000
+#define DDRSS2_PHY_1191_DATA 0x00000000
+#define DDRSS2_PHY_1192_DATA 0x00000000
+#define DDRSS2_PHY_1193_DATA 0x00000000
+#define DDRSS2_PHY_1194_DATA 0x00000000
+#define DDRSS2_PHY_1195_DATA 0x00000000
+#define DDRSS2_PHY_1196_DATA 0x00000000
+#define DDRSS2_PHY_1197_DATA 0x00000000
+#define DDRSS2_PHY_1198_DATA 0x00000000
+#define DDRSS2_PHY_1199_DATA 0x00000000
+#define DDRSS2_PHY_1200_DATA 0x00000000
+#define DDRSS2_PHY_1201_DATA 0x00000000
+#define DDRSS2_PHY_1202_DATA 0x00000000
+#define DDRSS2_PHY_1203_DATA 0x00000000
+#define DDRSS2_PHY_1204_DATA 0x00000000
+#define DDRSS2_PHY_1205_DATA 0x00000000
+#define DDRSS2_PHY_1206_DATA 0x00000000
+#define DDRSS2_PHY_1207_DATA 0x00000000
+#define DDRSS2_PHY_1208_DATA 0x00000000
+#define DDRSS2_PHY_1209_DATA 0x00000000
+#define DDRSS2_PHY_1210_DATA 0x00000000
+#define DDRSS2_PHY_1211_DATA 0x00000000
+#define DDRSS2_PHY_1212_DATA 0x00000000
+#define DDRSS2_PHY_1213_DATA 0x00000000
+#define DDRSS2_PHY_1214_DATA 0x00000000
+#define DDRSS2_PHY_1215_DATA 0x00000000
+#define DDRSS2_PHY_1216_DATA 0x00000000
+#define DDRSS2_PHY_1217_DATA 0x00000000
+#define DDRSS2_PHY_1218_DATA 0x00000000
+#define DDRSS2_PHY_1219_DATA 0x00000000
+#define DDRSS2_PHY_1220_DATA 0x00000000
+#define DDRSS2_PHY_1221_DATA 0x00000000
+#define DDRSS2_PHY_1222_DATA 0x00000000
+#define DDRSS2_PHY_1223_DATA 0x00000000
+#define DDRSS2_PHY_1224_DATA 0x00000000
+#define DDRSS2_PHY_1225_DATA 0x00000000
+#define DDRSS2_PHY_1226_DATA 0x00000000
+#define DDRSS2_PHY_1227_DATA 0x00000000
+#define DDRSS2_PHY_1228_DATA 0x00000000
+#define DDRSS2_PHY_1229_DATA 0x00000000
+#define DDRSS2_PHY_1230_DATA 0x00000000
+#define DDRSS2_PHY_1231_DATA 0x00000000
+#define DDRSS2_PHY_1232_DATA 0x00000000
+#define DDRSS2_PHY_1233_DATA 0x00000000
+#define DDRSS2_PHY_1234_DATA 0x00000000
+#define DDRSS2_PHY_1235_DATA 0x00000000
+#define DDRSS2_PHY_1236_DATA 0x00000000
+#define DDRSS2_PHY_1237_DATA 0x00000000
+#define DDRSS2_PHY_1238_DATA 0x00000000
+#define DDRSS2_PHY_1239_DATA 0x00000000
+#define DDRSS2_PHY_1240_DATA 0x00000000
+#define DDRSS2_PHY_1241_DATA 0x00000000
+#define DDRSS2_PHY_1242_DATA 0x00000000
+#define DDRSS2_PHY_1243_DATA 0x00000000
+#define DDRSS2_PHY_1244_DATA 0x00000000
+#define DDRSS2_PHY_1245_DATA 0x00000000
+#define DDRSS2_PHY_1246_DATA 0x00000000
+#define DDRSS2_PHY_1247_DATA 0x00000000
+#define DDRSS2_PHY_1248_DATA 0x00000000
+#define DDRSS2_PHY_1249_DATA 0x00000000
+#define DDRSS2_PHY_1250_DATA 0x00000000
+#define DDRSS2_PHY_1251_DATA 0x00000000
+#define DDRSS2_PHY_1252_DATA 0x00000000
+#define DDRSS2_PHY_1253_DATA 0x00000000
+#define DDRSS2_PHY_1254_DATA 0x00000000
+#define DDRSS2_PHY_1255_DATA 0x00000000
+#define DDRSS2_PHY_1256_DATA 0x00000000
+#define DDRSS2_PHY_1257_DATA 0x00000000
+#define DDRSS2_PHY_1258_DATA 0x00000000
+#define DDRSS2_PHY_1259_DATA 0x00000000
+#define DDRSS2_PHY_1260_DATA 0x00000000
+#define DDRSS2_PHY_1261_DATA 0x00000000
+#define DDRSS2_PHY_1262_DATA 0x00000000
+#define DDRSS2_PHY_1263_DATA 0x00000000
+#define DDRSS2_PHY_1264_DATA 0x00000000
+#define DDRSS2_PHY_1265_DATA 0x00000000
+#define DDRSS2_PHY_1266_DATA 0x00000000
+#define DDRSS2_PHY_1267_DATA 0x00000000
+#define DDRSS2_PHY_1268_DATA 0x00000000
+#define DDRSS2_PHY_1269_DATA 0x00000000
+#define DDRSS2_PHY_1270_DATA 0x00000000
+#define DDRSS2_PHY_1271_DATA 0x00000000
+#define DDRSS2_PHY_1272_DATA 0x00000000
+#define DDRSS2_PHY_1273_DATA 0x00000000
+#define DDRSS2_PHY_1274_DATA 0x00000000
+#define DDRSS2_PHY_1275_DATA 0x00000000
+#define DDRSS2_PHY_1276_DATA 0x00000000
+#define DDRSS2_PHY_1277_DATA 0x00000000
+#define DDRSS2_PHY_1278_DATA 0x00000000
+#define DDRSS2_PHY_1279_DATA 0x00000000
+#define DDRSS2_PHY_1280_DATA 0x00000000
+#define DDRSS2_PHY_1281_DATA 0x00010100
+#define DDRSS2_PHY_1282_DATA 0x00000000
+#define DDRSS2_PHY_1283_DATA 0x00000000
+#define DDRSS2_PHY_1284_DATA 0x00050000
+#define DDRSS2_PHY_1285_DATA 0x04000000
+#define DDRSS2_PHY_1286_DATA 0x00000055
+#define DDRSS2_PHY_1287_DATA 0x00000000
+#define DDRSS2_PHY_1288_DATA 0x00000000
+#define DDRSS2_PHY_1289_DATA 0x00000000
+#define DDRSS2_PHY_1290_DATA 0x00000000
+#define DDRSS2_PHY_1291_DATA 0x00002001
+#define DDRSS2_PHY_1292_DATA 0x0000400F
+#define DDRSS2_PHY_1293_DATA 0x50020028
+#define DDRSS2_PHY_1294_DATA 0x01010000
+#define DDRSS2_PHY_1295_DATA 0x80080001
+#define DDRSS2_PHY_1296_DATA 0x10200000
+#define DDRSS2_PHY_1297_DATA 0x00000008
+#define DDRSS2_PHY_1298_DATA 0x00000000
+#define DDRSS2_PHY_1299_DATA 0x01090E00
+#define DDRSS2_PHY_1300_DATA 0x00040101
+#define DDRSS2_PHY_1301_DATA 0x0000010F
+#define DDRSS2_PHY_1302_DATA 0x00000000
+#define DDRSS2_PHY_1303_DATA 0x0000FFFF
+#define DDRSS2_PHY_1304_DATA 0x00000000
+#define DDRSS2_PHY_1305_DATA 0x01010000
+#define DDRSS2_PHY_1306_DATA 0x01080402
+#define DDRSS2_PHY_1307_DATA 0x01200F02
+#define DDRSS2_PHY_1308_DATA 0x00194280
+#define DDRSS2_PHY_1309_DATA 0x00000004
+#define DDRSS2_PHY_1310_DATA 0x00042000
+#define DDRSS2_PHY_1311_DATA 0x00000000
+#define DDRSS2_PHY_1312_DATA 0x00000000
+#define DDRSS2_PHY_1313_DATA 0x00000000
+#define DDRSS2_PHY_1314_DATA 0x00000000
+#define DDRSS2_PHY_1315_DATA 0x00000000
+#define DDRSS2_PHY_1316_DATA 0x00000000
+#define DDRSS2_PHY_1317_DATA 0x01000000
+#define DDRSS2_PHY_1318_DATA 0x00000705
+#define DDRSS2_PHY_1319_DATA 0x00000054
+#define DDRSS2_PHY_1320_DATA 0x00030820
+#define DDRSS2_PHY_1321_DATA 0x00010820
+#define DDRSS2_PHY_1322_DATA 0x00010820
+#define DDRSS2_PHY_1323_DATA 0x00010820
+#define DDRSS2_PHY_1324_DATA 0x00010820
+#define DDRSS2_PHY_1325_DATA 0x00010820
+#define DDRSS2_PHY_1326_DATA 0x00010820
+#define DDRSS2_PHY_1327_DATA 0x00010820
+#define DDRSS2_PHY_1328_DATA 0x00010820
+#define DDRSS2_PHY_1329_DATA 0x00000000
+#define DDRSS2_PHY_1330_DATA 0x00000074
+#define DDRSS2_PHY_1331_DATA 0x00000400
+#define DDRSS2_PHY_1332_DATA 0x00000108
+#define DDRSS2_PHY_1333_DATA 0x00000000
+#define DDRSS2_PHY_1334_DATA 0x00000000
+#define DDRSS2_PHY_1335_DATA 0x00000000
+#define DDRSS2_PHY_1336_DATA 0x00000000
+#define DDRSS2_PHY_1337_DATA 0x00000000
+#define DDRSS2_PHY_1338_DATA 0x03000000
+#define DDRSS2_PHY_1339_DATA 0x00000000
+#define DDRSS2_PHY_1340_DATA 0x00000000
+#define DDRSS2_PHY_1341_DATA 0x00000000
+#define DDRSS2_PHY_1342_DATA 0x04102006
+#define DDRSS2_PHY_1343_DATA 0x00041020
+#define DDRSS2_PHY_1344_DATA 0x01C98C98
+#define DDRSS2_PHY_1345_DATA 0x3F400000
+#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS2_PHY_1347_DATA 0x0000001F
+#define DDRSS2_PHY_1348_DATA 0x00000000
+#define DDRSS2_PHY_1349_DATA 0x00000000
+#define DDRSS2_PHY_1350_DATA 0x00000000
+#define DDRSS2_PHY_1351_DATA 0x00010000
+#define DDRSS2_PHY_1352_DATA 0x00000000
+#define DDRSS2_PHY_1353_DATA 0x00000000
+#define DDRSS2_PHY_1354_DATA 0x00000000
+#define DDRSS2_PHY_1355_DATA 0x00000000
+#define DDRSS2_PHY_1356_DATA 0x76543210
+#define DDRSS2_PHY_1357_DATA 0x00010198
+#define DDRSS2_PHY_1358_DATA 0x00000000
+#define DDRSS2_PHY_1359_DATA 0x00000000
+#define DDRSS2_PHY_1360_DATA 0x00000000
+#define DDRSS2_PHY_1361_DATA 0x00040700
+#define DDRSS2_PHY_1362_DATA 0x00000000
+#define DDRSS2_PHY_1363_DATA 0x00000000
+#define DDRSS2_PHY_1364_DATA 0x00000000
+#define DDRSS2_PHY_1365_DATA 0x00000000
+#define DDRSS2_PHY_1366_DATA 0x00000000
+#define DDRSS2_PHY_1367_DATA 0x00000002
+#define DDRSS2_PHY_1368_DATA 0x00000000
+#define DDRSS2_PHY_1369_DATA 0x00000000
+#define DDRSS2_PHY_1370_DATA 0x00000000
+#define DDRSS2_PHY_1371_DATA 0x00000000
+#define DDRSS2_PHY_1372_DATA 0x00000000
+#define DDRSS2_PHY_1373_DATA 0x00000000
+#define DDRSS2_PHY_1374_DATA 0x00080000
+#define DDRSS2_PHY_1375_DATA 0x000007FF
+#define DDRSS2_PHY_1376_DATA 0x00000000
+#define DDRSS2_PHY_1377_DATA 0x00000000
+#define DDRSS2_PHY_1378_DATA 0x00000000
+#define DDRSS2_PHY_1379_DATA 0x00000000
+#define DDRSS2_PHY_1380_DATA 0x00000000
+#define DDRSS2_PHY_1381_DATA 0x00000000
+#define DDRSS2_PHY_1382_DATA 0x000FFFFF
+#define DDRSS2_PHY_1383_DATA 0x000FFFFF
+#define DDRSS2_PHY_1384_DATA 0x0000FFFF
+#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS2_PHY_1386_DATA 0x030FFFFF
+#define DDRSS2_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS2_PHY_1388_DATA 0x0000FFFF
+#define DDRSS2_PHY_1389_DATA 0x00000000
+#define DDRSS2_PHY_1390_DATA 0x00000000
+#define DDRSS2_PHY_1391_DATA 0x00000000
+#define DDRSS2_PHY_1392_DATA 0x00000000
+#define DDRSS2_PHY_1393_DATA 0x0001F7C0
+#define DDRSS2_PHY_1394_DATA 0x00000003
+#define DDRSS2_PHY_1395_DATA 0x00000000
+#define DDRSS2_PHY_1396_DATA 0x00001142
+#define DDRSS2_PHY_1397_DATA 0x010207AB
+#define DDRSS2_PHY_1398_DATA 0x01000080
+#define DDRSS2_PHY_1399_DATA 0x03900390
+#define DDRSS2_PHY_1400_DATA 0x03900390
+#define DDRSS2_PHY_1401_DATA 0x00000390
+#define DDRSS2_PHY_1402_DATA 0x00000390
+#define DDRSS2_PHY_1403_DATA 0x00000390
+#define DDRSS2_PHY_1404_DATA 0x00000390
+#define DDRSS2_PHY_1405_DATA 0x00000005
+#define DDRSS2_PHY_1406_DATA 0x01813FCC
+#define DDRSS2_PHY_1407_DATA 0x000000CC
+#define DDRSS2_PHY_1408_DATA 0x0C000DFF
+#define DDRSS2_PHY_1409_DATA 0x30000DFF
+#define DDRSS2_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1411_DATA 0x000100F0
+#define DDRSS2_PHY_1412_DATA 0x780DFFCC
+#define DDRSS2_PHY_1413_DATA 0x00007E31
+#define DDRSS2_PHY_1414_DATA 0x000CBF11
+#define DDRSS2_PHY_1415_DATA 0x01990010
+#define DDRSS2_PHY_1416_DATA 0x000CBF11
+#define DDRSS2_PHY_1417_DATA 0x01990010
+#define DDRSS2_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1419_DATA 0x00EF00F0
+#define DDRSS2_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1421_DATA 0x01FF00F0
+#define DDRSS2_PHY_1422_DATA 0x20040006
+
+#define DDRSS3_CTL_00_DATA 0x00000B00
+#define DDRSS3_CTL_01_DATA 0x00000000
+#define DDRSS3_CTL_02_DATA 0x00000000
+#define DDRSS3_CTL_03_DATA 0x00000000
+#define DDRSS3_CTL_04_DATA 0x00000000
+#define DDRSS3_CTL_05_DATA 0x00000000
+#define DDRSS3_CTL_06_DATA 0x00000000
+#define DDRSS3_CTL_07_DATA 0x00002AF8
+#define DDRSS3_CTL_08_DATA 0x0001ADAF
+#define DDRSS3_CTL_09_DATA 0x00000005
+#define DDRSS3_CTL_10_DATA 0x0000006E
+#define DDRSS3_CTL_11_DATA 0x000681C8
+#define DDRSS3_CTL_12_DATA 0x004111C9
+#define DDRSS3_CTL_13_DATA 0x00000005
+#define DDRSS3_CTL_14_DATA 0x000010A9
+#define DDRSS3_CTL_15_DATA 0x000681C8
+#define DDRSS3_CTL_16_DATA 0x004111C9
+#define DDRSS3_CTL_17_DATA 0x00000005
+#define DDRSS3_CTL_18_DATA 0x000010A9
+#define DDRSS3_CTL_19_DATA 0x01010000
+#define DDRSS3_CTL_20_DATA 0x02011001
+#define DDRSS3_CTL_21_DATA 0x02010000
+#define DDRSS3_CTL_22_DATA 0x00020100
+#define DDRSS3_CTL_23_DATA 0x0000000B
+#define DDRSS3_CTL_24_DATA 0x0000001C
+#define DDRSS3_CTL_25_DATA 0x00000000
+#define DDRSS3_CTL_26_DATA 0x00000000
+#define DDRSS3_CTL_27_DATA 0x03020200
+#define DDRSS3_CTL_28_DATA 0x00005656
+#define DDRSS3_CTL_29_DATA 0x00100000
+#define DDRSS3_CTL_30_DATA 0x00000000
+#define DDRSS3_CTL_31_DATA 0x00000000
+#define DDRSS3_CTL_32_DATA 0x00000000
+#define DDRSS3_CTL_33_DATA 0x00000000
+#define DDRSS3_CTL_34_DATA 0x040C0000
+#define DDRSS3_CTL_35_DATA 0x12481248
+#define DDRSS3_CTL_36_DATA 0x00050804
+#define DDRSS3_CTL_37_DATA 0x09040008
+#define DDRSS3_CTL_38_DATA 0x15000204
+#define DDRSS3_CTL_39_DATA 0x1760008B
+#define DDRSS3_CTL_40_DATA 0x1500422B
+#define DDRSS3_CTL_41_DATA 0x1760008B
+#define DDRSS3_CTL_42_DATA 0x2000422B
+#define DDRSS3_CTL_43_DATA 0x000A0A09
+#define DDRSS3_CTL_44_DATA 0x0400078A
+#define DDRSS3_CTL_45_DATA 0x1E161104
+#define DDRSS3_CTL_46_DATA 0x10012458
+#define DDRSS3_CTL_47_DATA 0x1E161110
+#define DDRSS3_CTL_48_DATA 0x10012458
+#define DDRSS3_CTL_49_DATA 0x02030410
+#define DDRSS3_CTL_50_DATA 0x2C040500
+#define DDRSS3_CTL_51_DATA 0x08292C29
+#define DDRSS3_CTL_52_DATA 0x14000E0A
+#define DDRSS3_CTL_53_DATA 0x04010A0A
+#define DDRSS3_CTL_54_DATA 0x01010004
+#define DDRSS3_CTL_55_DATA 0x04545408
+#define DDRSS3_CTL_56_DATA 0x04313104
+#define DDRSS3_CTL_57_DATA 0x00003131
+#define DDRSS3_CTL_58_DATA 0x00010100
+#define DDRSS3_CTL_59_DATA 0x03010000
+#define DDRSS3_CTL_60_DATA 0x00001508
+#define DDRSS3_CTL_61_DATA 0x000000CE
+#define DDRSS3_CTL_62_DATA 0x0000032B
+#define DDRSS3_CTL_63_DATA 0x00002073
+#define DDRSS3_CTL_64_DATA 0x0000032B
+#define DDRSS3_CTL_65_DATA 0x00002073
+#define DDRSS3_CTL_66_DATA 0x00000005
+#define DDRSS3_CTL_67_DATA 0x00050000
+#define DDRSS3_CTL_68_DATA 0x00CB0012
+#define DDRSS3_CTL_69_DATA 0x00CB0408
+#define DDRSS3_CTL_70_DATA 0x00400408
+#define DDRSS3_CTL_71_DATA 0x00120103
+#define DDRSS3_CTL_72_DATA 0x00100005
+#define DDRSS3_CTL_73_DATA 0x2F080010
+#define DDRSS3_CTL_74_DATA 0x0505012F
+#define DDRSS3_CTL_75_DATA 0x0401030A
+#define DDRSS3_CTL_76_DATA 0x041E100B
+#define DDRSS3_CTL_77_DATA 0x100B0401
+#define DDRSS3_CTL_78_DATA 0x0001041E
+#define DDRSS3_CTL_79_DATA 0x00160016
+#define DDRSS3_CTL_80_DATA 0x033B033B
+#define DDRSS3_CTL_81_DATA 0x033B033B
+#define DDRSS3_CTL_82_DATA 0x03050505
+#define DDRSS3_CTL_83_DATA 0x03010303
+#define DDRSS3_CTL_84_DATA 0x200B100B
+#define DDRSS3_CTL_85_DATA 0x04041004
+#define DDRSS3_CTL_86_DATA 0x200B100B
+#define DDRSS3_CTL_87_DATA 0x04041004
+#define DDRSS3_CTL_88_DATA 0x03010000
+#define DDRSS3_CTL_89_DATA 0x00010000
+#define DDRSS3_CTL_90_DATA 0x00000000
+#define DDRSS3_CTL_91_DATA 0x00000000
+#define DDRSS3_CTL_92_DATA 0x01000000
+#define DDRSS3_CTL_93_DATA 0x80104002
+#define DDRSS3_CTL_94_DATA 0x00000000
+#define DDRSS3_CTL_95_DATA 0x00040005
+#define DDRSS3_CTL_96_DATA 0x00000000
+#define DDRSS3_CTL_97_DATA 0x00050000
+#define DDRSS3_CTL_98_DATA 0x00000004
+#define DDRSS3_CTL_99_DATA 0x00000000
+#define DDRSS3_CTL_100_DATA 0x00040005
+#define DDRSS3_CTL_101_DATA 0x00000000
+#define DDRSS3_CTL_102_DATA 0x00003380
+#define DDRSS3_CTL_103_DATA 0x00003380
+#define DDRSS3_CTL_104_DATA 0x00003380
+#define DDRSS3_CTL_105_DATA 0x00003380
+#define DDRSS3_CTL_106_DATA 0x00003380
+#define DDRSS3_CTL_107_DATA 0x00000000
+#define DDRSS3_CTL_108_DATA 0x000005A2
+#define DDRSS3_CTL_109_DATA 0x00081CC0
+#define DDRSS3_CTL_110_DATA 0x00081CC0
+#define DDRSS3_CTL_111_DATA 0x00081CC0
+#define DDRSS3_CTL_112_DATA 0x00081CC0
+#define DDRSS3_CTL_113_DATA 0x00081CC0
+#define DDRSS3_CTL_114_DATA 0x00000000
+#define DDRSS3_CTL_115_DATA 0x0000E325
+#define DDRSS3_CTL_116_DATA 0x00081CC0
+#define DDRSS3_CTL_117_DATA 0x00081CC0
+#define DDRSS3_CTL_118_DATA 0x00081CC0
+#define DDRSS3_CTL_119_DATA 0x00081CC0
+#define DDRSS3_CTL_120_DATA 0x00081CC0
+#define DDRSS3_CTL_121_DATA 0x00000000
+#define DDRSS3_CTL_122_DATA 0x0000E325
+#define DDRSS3_CTL_123_DATA 0x00000000
+#define DDRSS3_CTL_124_DATA 0x00000000
+#define DDRSS3_CTL_125_DATA 0x00000000
+#define DDRSS3_CTL_126_DATA 0x00000000
+#define DDRSS3_CTL_127_DATA 0x00000000
+#define DDRSS3_CTL_128_DATA 0x00000000
+#define DDRSS3_CTL_129_DATA 0x00000000
+#define DDRSS3_CTL_130_DATA 0x00000000
+#define DDRSS3_CTL_131_DATA 0x0B030500
+#define DDRSS3_CTL_132_DATA 0x00040B04
+#define DDRSS3_CTL_133_DATA 0x0A090000
+#define DDRSS3_CTL_134_DATA 0x0A090701
+#define DDRSS3_CTL_135_DATA 0x0900000E
+#define DDRSS3_CTL_136_DATA 0x0907010A
+#define DDRSS3_CTL_137_DATA 0x00000E0A
+#define DDRSS3_CTL_138_DATA 0x07010A09
+#define DDRSS3_CTL_139_DATA 0x000E0A09
+#define DDRSS3_CTL_140_DATA 0x07000401
+#define DDRSS3_CTL_141_DATA 0x00000000
+#define DDRSS3_CTL_142_DATA 0x00000000
+#define DDRSS3_CTL_143_DATA 0x00000000
+#define DDRSS3_CTL_144_DATA 0x00000000
+#define DDRSS3_CTL_145_DATA 0x00000000
+#define DDRSS3_CTL_146_DATA 0x00000000
+#define DDRSS3_CTL_147_DATA 0x00000000
+#define DDRSS3_CTL_148_DATA 0x08080000
+#define DDRSS3_CTL_149_DATA 0x01000000
+#define DDRSS3_CTL_150_DATA 0x800000C0
+#define DDRSS3_CTL_151_DATA 0x800000C0
+#define DDRSS3_CTL_152_DATA 0x800000C0
+#define DDRSS3_CTL_153_DATA 0x00000000
+#define DDRSS3_CTL_154_DATA 0x00001500
+#define DDRSS3_CTL_155_DATA 0x00000000
+#define DDRSS3_CTL_156_DATA 0x00000001
+#define DDRSS3_CTL_157_DATA 0x00000002
+#define DDRSS3_CTL_158_DATA 0x0000100E
+#define DDRSS3_CTL_159_DATA 0x00000000
+#define DDRSS3_CTL_160_DATA 0x00000000
+#define DDRSS3_CTL_161_DATA 0x00000000
+#define DDRSS3_CTL_162_DATA 0x00000000
+#define DDRSS3_CTL_163_DATA 0x00000000
+#define DDRSS3_CTL_164_DATA 0x000B0000
+#define DDRSS3_CTL_165_DATA 0x000E0006
+#define DDRSS3_CTL_166_DATA 0x000E0404
+#define DDRSS3_CTL_167_DATA 0x00D601AB
+#define DDRSS3_CTL_168_DATA 0x10100216
+#define DDRSS3_CTL_169_DATA 0x01AB0216
+#define DDRSS3_CTL_170_DATA 0x021600D6
+#define DDRSS3_CTL_171_DATA 0x02161010
+#define DDRSS3_CTL_172_DATA 0x00000000
+#define DDRSS3_CTL_173_DATA 0x00000000
+#define DDRSS3_CTL_174_DATA 0x00000000
+#define DDRSS3_CTL_175_DATA 0x3FF40084
+#define DDRSS3_CTL_176_DATA 0x33003FF4
+#define DDRSS3_CTL_177_DATA 0x00003333
+#define DDRSS3_CTL_178_DATA 0x35000000
+#define DDRSS3_CTL_179_DATA 0x27270035
+#define DDRSS3_CTL_180_DATA 0x0F0F0000
+#define DDRSS3_CTL_181_DATA 0x16000000
+#define DDRSS3_CTL_182_DATA 0x00841616
+#define DDRSS3_CTL_183_DATA 0x3FF43FF4
+#define DDRSS3_CTL_184_DATA 0x33333300
+#define DDRSS3_CTL_185_DATA 0x00000000
+#define DDRSS3_CTL_186_DATA 0x00353500
+#define DDRSS3_CTL_187_DATA 0x00002727
+#define DDRSS3_CTL_188_DATA 0x00000F0F
+#define DDRSS3_CTL_189_DATA 0x16161600
+#define DDRSS3_CTL_190_DATA 0x00000020
+#define DDRSS3_CTL_191_DATA 0x00000000
+#define DDRSS3_CTL_192_DATA 0x00000001
+#define DDRSS3_CTL_193_DATA 0x00000000
+#define DDRSS3_CTL_194_DATA 0x01000000
+#define DDRSS3_CTL_195_DATA 0x00000001
+#define DDRSS3_CTL_196_DATA 0x00000000
+#define DDRSS3_CTL_197_DATA 0x00000000
+#define DDRSS3_CTL_198_DATA 0x00000000
+#define DDRSS3_CTL_199_DATA 0x00000000
+#define DDRSS3_CTL_200_DATA 0x00000000
+#define DDRSS3_CTL_201_DATA 0x00000000
+#define DDRSS3_CTL_202_DATA 0x00000000
+#define DDRSS3_CTL_203_DATA 0x00000000
+#define DDRSS3_CTL_204_DATA 0x00000000
+#define DDRSS3_CTL_205_DATA 0x00000000
+#define DDRSS3_CTL_206_DATA 0x02000000
+#define DDRSS3_CTL_207_DATA 0x01080101
+#define DDRSS3_CTL_208_DATA 0x00000000
+#define DDRSS3_CTL_209_DATA 0x00000000
+#define DDRSS3_CTL_210_DATA 0x00000000
+#define DDRSS3_CTL_211_DATA 0x00000000
+#define DDRSS3_CTL_212_DATA 0x00000000
+#define DDRSS3_CTL_213_DATA 0x00000000
+#define DDRSS3_CTL_214_DATA 0x00000000
+#define DDRSS3_CTL_215_DATA 0x00000000
+#define DDRSS3_CTL_216_DATA 0x00000000
+#define DDRSS3_CTL_217_DATA 0x00000000
+#define DDRSS3_CTL_218_DATA 0x00000000
+#define DDRSS3_CTL_219_DATA 0x00000000
+#define DDRSS3_CTL_220_DATA 0x00000000
+#define DDRSS3_CTL_221_DATA 0x00000000
+#define DDRSS3_CTL_222_DATA 0x00001000
+#define DDRSS3_CTL_223_DATA 0x006403E8
+#define DDRSS3_CTL_224_DATA 0x00000000
+#define DDRSS3_CTL_225_DATA 0x00000000
+#define DDRSS3_CTL_226_DATA 0x00000000
+#define DDRSS3_CTL_227_DATA 0x15110000
+#define DDRSS3_CTL_228_DATA 0x00040C18
+#define DDRSS3_CTL_229_DATA 0xF000C000
+#define DDRSS3_CTL_230_DATA 0x0000F000
+#define DDRSS3_CTL_231_DATA 0x00000000
+#define DDRSS3_CTL_232_DATA 0x00000000
+#define DDRSS3_CTL_233_DATA 0xC0000000
+#define DDRSS3_CTL_234_DATA 0xF000F000
+#define DDRSS3_CTL_235_DATA 0x00000000
+#define DDRSS3_CTL_236_DATA 0x00000000
+#define DDRSS3_CTL_237_DATA 0x00000000
+#define DDRSS3_CTL_238_DATA 0xF000C000
+#define DDRSS3_CTL_239_DATA 0x0000F000
+#define DDRSS3_CTL_240_DATA 0x00000000
+#define DDRSS3_CTL_241_DATA 0x00000000
+#define DDRSS3_CTL_242_DATA 0x00030000
+#define DDRSS3_CTL_243_DATA 0x00000000
+#define DDRSS3_CTL_244_DATA 0x00000000
+#define DDRSS3_CTL_245_DATA 0x00000000
+#define DDRSS3_CTL_246_DATA 0x00000000
+#define DDRSS3_CTL_247_DATA 0x00000000
+#define DDRSS3_CTL_248_DATA 0x00000000
+#define DDRSS3_CTL_249_DATA 0x00000000
+#define DDRSS3_CTL_250_DATA 0x00000000
+#define DDRSS3_CTL_251_DATA 0x00000000
+#define DDRSS3_CTL_252_DATA 0x00000000
+#define DDRSS3_CTL_253_DATA 0x00000000
+#define DDRSS3_CTL_254_DATA 0x00000000
+#define DDRSS3_CTL_255_DATA 0x00000000
+#define DDRSS3_CTL_256_DATA 0x00000000
+#define DDRSS3_CTL_257_DATA 0x01000200
+#define DDRSS3_CTL_258_DATA 0x00370040
+#define DDRSS3_CTL_259_DATA 0x00020008
+#define DDRSS3_CTL_260_DATA 0x00400100
+#define DDRSS3_CTL_261_DATA 0x00400855
+#define DDRSS3_CTL_262_DATA 0x01000200
+#define DDRSS3_CTL_263_DATA 0x08550040
+#define DDRSS3_CTL_264_DATA 0x00000040
+#define DDRSS3_CTL_265_DATA 0x006B0003
+#define DDRSS3_CTL_266_DATA 0x0100006B
+#define DDRSS3_CTL_267_DATA 0x03030303
+#define DDRSS3_CTL_268_DATA 0x00000000
+#define DDRSS3_CTL_269_DATA 0x00000202
+#define DDRSS3_CTL_270_DATA 0x00001FFF
+#define DDRSS3_CTL_271_DATA 0x3FFF2000
+#define DDRSS3_CTL_272_DATA 0x03FF0000
+#define DDRSS3_CTL_273_DATA 0x000103FF
+#define DDRSS3_CTL_274_DATA 0x0FFF0B00
+#define DDRSS3_CTL_275_DATA 0x01010001
+#define DDRSS3_CTL_276_DATA 0x01010101
+#define DDRSS3_CTL_277_DATA 0x01180101
+#define DDRSS3_CTL_278_DATA 0x00030000
+#define DDRSS3_CTL_279_DATA 0x00000000
+#define DDRSS3_CTL_280_DATA 0x00000000
+#define DDRSS3_CTL_281_DATA 0x00000000
+#define DDRSS3_CTL_282_DATA 0x00000000
+#define DDRSS3_CTL_283_DATA 0x00000000
+#define DDRSS3_CTL_284_DATA 0x00000000
+#define DDRSS3_CTL_285_DATA 0x00000000
+#define DDRSS3_CTL_286_DATA 0x00040101
+#define DDRSS3_CTL_287_DATA 0x04010100
+#define DDRSS3_CTL_288_DATA 0x00000000
+#define DDRSS3_CTL_289_DATA 0x00000000
+#define DDRSS3_CTL_290_DATA 0x03030300
+#define DDRSS3_CTL_291_DATA 0x00000001
+#define DDRSS3_CTL_292_DATA 0x00000000
+#define DDRSS3_CTL_293_DATA 0x00000000
+#define DDRSS3_CTL_294_DATA 0x00000000
+#define DDRSS3_CTL_295_DATA 0x00000000
+#define DDRSS3_CTL_296_DATA 0x00000000
+#define DDRSS3_CTL_297_DATA 0x00000000
+#define DDRSS3_CTL_298_DATA 0x00000000
+#define DDRSS3_CTL_299_DATA 0x00000000
+#define DDRSS3_CTL_300_DATA 0x00000000
+#define DDRSS3_CTL_301_DATA 0x00000000
+#define DDRSS3_CTL_302_DATA 0x00000000
+#define DDRSS3_CTL_303_DATA 0x00000000
+#define DDRSS3_CTL_304_DATA 0x00000000
+#define DDRSS3_CTL_305_DATA 0x00000000
+#define DDRSS3_CTL_306_DATA 0x00000000
+#define DDRSS3_CTL_307_DATA 0x00000000
+#define DDRSS3_CTL_308_DATA 0x00000000
+#define DDRSS3_CTL_309_DATA 0x00000000
+#define DDRSS3_CTL_310_DATA 0x00000000
+#define DDRSS3_CTL_311_DATA 0x00000000
+#define DDRSS3_CTL_312_DATA 0x00000000
+#define DDRSS3_CTL_313_DATA 0x01000000
+#define DDRSS3_CTL_314_DATA 0x00020201
+#define DDRSS3_CTL_315_DATA 0x01000101
+#define DDRSS3_CTL_316_DATA 0x01010001
+#define DDRSS3_CTL_317_DATA 0x00010101
+#define DDRSS3_CTL_318_DATA 0x050A0A03
+#define DDRSS3_CTL_319_DATA 0x10081F1F
+#define DDRSS3_CTL_320_DATA 0x00090310
+#define DDRSS3_CTL_321_DATA 0x0B0C030F
+#define DDRSS3_CTL_322_DATA 0x0B0C0306
+#define DDRSS3_CTL_323_DATA 0x0C090006
+#define DDRSS3_CTL_324_DATA 0x0100000C
+#define DDRSS3_CTL_325_DATA 0x08040801
+#define DDRSS3_CTL_326_DATA 0x00000004
+#define DDRSS3_CTL_327_DATA 0x00000000
+#define DDRSS3_CTL_328_DATA 0x00010000
+#define DDRSS3_CTL_329_DATA 0x00280D00
+#define DDRSS3_CTL_330_DATA 0x00000001
+#define DDRSS3_CTL_331_DATA 0x00030001
+#define DDRSS3_CTL_332_DATA 0x00000000
+#define DDRSS3_CTL_333_DATA 0x00000000
+#define DDRSS3_CTL_334_DATA 0x00000000
+#define DDRSS3_CTL_335_DATA 0x00000000
+#define DDRSS3_CTL_336_DATA 0x00000000
+#define DDRSS3_CTL_337_DATA 0x00000000
+#define DDRSS3_CTL_338_DATA 0x00000000
+#define DDRSS3_CTL_339_DATA 0x00000000
+#define DDRSS3_CTL_340_DATA 0x01000000
+#define DDRSS3_CTL_341_DATA 0x00000001
+#define DDRSS3_CTL_342_DATA 0x00010100
+#define DDRSS3_CTL_343_DATA 0x03030000
+#define DDRSS3_CTL_344_DATA 0x00000000
+#define DDRSS3_CTL_345_DATA 0x00000000
+#define DDRSS3_CTL_346_DATA 0x00000000
+#define DDRSS3_CTL_347_DATA 0x00000000
+#define DDRSS3_CTL_348_DATA 0x00000000
+#define DDRSS3_CTL_349_DATA 0x00000000
+#define DDRSS3_CTL_350_DATA 0x00000000
+#define DDRSS3_CTL_351_DATA 0x00000000
+#define DDRSS3_CTL_352_DATA 0x00000000
+#define DDRSS3_CTL_353_DATA 0x00000000
+#define DDRSS3_CTL_354_DATA 0x00000000
+#define DDRSS3_CTL_355_DATA 0x00000000
+#define DDRSS3_CTL_356_DATA 0x00000000
+#define DDRSS3_CTL_357_DATA 0x00000000
+#define DDRSS3_CTL_358_DATA 0x00000000
+#define DDRSS3_CTL_359_DATA 0x00000000
+#define DDRSS3_CTL_360_DATA 0x000556AA
+#define DDRSS3_CTL_361_DATA 0x000AAAAA
+#define DDRSS3_CTL_362_DATA 0x000AA955
+#define DDRSS3_CTL_363_DATA 0x00055555
+#define DDRSS3_CTL_364_DATA 0x000B3133
+#define DDRSS3_CTL_365_DATA 0x0004CD33
+#define DDRSS3_CTL_366_DATA 0x0004CECC
+#define DDRSS3_CTL_367_DATA 0x000B32CC
+#define DDRSS3_CTL_368_DATA 0x00010300
+#define DDRSS3_CTL_369_DATA 0x03000100
+#define DDRSS3_CTL_370_DATA 0x00000000
+#define DDRSS3_CTL_371_DATA 0x00000000
+#define DDRSS3_CTL_372_DATA 0x00000000
+#define DDRSS3_CTL_373_DATA 0x00000000
+#define DDRSS3_CTL_374_DATA 0x00000000
+#define DDRSS3_CTL_375_DATA 0x00000000
+#define DDRSS3_CTL_376_DATA 0x00000000
+#define DDRSS3_CTL_377_DATA 0x00010000
+#define DDRSS3_CTL_378_DATA 0x00000404
+#define DDRSS3_CTL_379_DATA 0x00000000
+#define DDRSS3_CTL_380_DATA 0x00000000
+#define DDRSS3_CTL_381_DATA 0x00000000
+#define DDRSS3_CTL_382_DATA 0x00000000
+#define DDRSS3_CTL_383_DATA 0x00000000
+#define DDRSS3_CTL_384_DATA 0x00000000
+#define DDRSS3_CTL_385_DATA 0x00000000
+#define DDRSS3_CTL_386_DATA 0x00000000
+#define DDRSS3_CTL_387_DATA 0x3A3A1B00
+#define DDRSS3_CTL_388_DATA 0x000A0000
+#define DDRSS3_CTL_389_DATA 0x0000019C
+#define DDRSS3_CTL_390_DATA 0x00000200
+#define DDRSS3_CTL_391_DATA 0x00000200
+#define DDRSS3_CTL_392_DATA 0x00000200
+#define DDRSS3_CTL_393_DATA 0x00000200
+#define DDRSS3_CTL_394_DATA 0x000004D4
+#define DDRSS3_CTL_395_DATA 0x00001018
+#define DDRSS3_CTL_396_DATA 0x00000204
+#define DDRSS3_CTL_397_DATA 0x000040E6
+#define DDRSS3_CTL_398_DATA 0x00000200
+#define DDRSS3_CTL_399_DATA 0x00000200
+#define DDRSS3_CTL_400_DATA 0x00000200
+#define DDRSS3_CTL_401_DATA 0x00000200
+#define DDRSS3_CTL_402_DATA 0x0000C2B2
+#define DDRSS3_CTL_403_DATA 0x000288FC
+#define DDRSS3_CTL_404_DATA 0x00000E15
+#define DDRSS3_CTL_405_DATA 0x000040E6
+#define DDRSS3_CTL_406_DATA 0x00000200
+#define DDRSS3_CTL_407_DATA 0x00000200
+#define DDRSS3_CTL_408_DATA 0x00000200
+#define DDRSS3_CTL_409_DATA 0x00000200
+#define DDRSS3_CTL_410_DATA 0x0000C2B2
+#define DDRSS3_CTL_411_DATA 0x000288FC
+#define DDRSS3_CTL_412_DATA 0x02020E15
+#define DDRSS3_CTL_413_DATA 0x03030202
+#define DDRSS3_CTL_414_DATA 0x00000022
+#define DDRSS3_CTL_415_DATA 0x00000000
+#define DDRSS3_CTL_416_DATA 0x00000000
+#define DDRSS3_CTL_417_DATA 0x00001403
+#define DDRSS3_CTL_418_DATA 0x000007D0
+#define DDRSS3_CTL_419_DATA 0x00000000
+#define DDRSS3_CTL_420_DATA 0x00000000
+#define DDRSS3_CTL_421_DATA 0x00030000
+#define DDRSS3_CTL_422_DATA 0x0007001F
+#define DDRSS3_CTL_423_DATA 0x001B0033
+#define DDRSS3_CTL_424_DATA 0x001B0033
+#define DDRSS3_CTL_425_DATA 0x00000000
+#define DDRSS3_CTL_426_DATA 0x00000000
+#define DDRSS3_CTL_427_DATA 0x02000000
+#define DDRSS3_CTL_428_DATA 0x01000404
+#define DDRSS3_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS3_CTL_430_DATA 0x00000105
+#define DDRSS3_CTL_431_DATA 0x00010101
+#define DDRSS3_CTL_432_DATA 0x00010101
+#define DDRSS3_CTL_433_DATA 0x00010001
+#define DDRSS3_CTL_434_DATA 0x00000101
+#define DDRSS3_CTL_435_DATA 0x02000201
+#define DDRSS3_CTL_436_DATA 0x02010000
+#define DDRSS3_CTL_437_DATA 0x00000200
+#define DDRSS3_CTL_438_DATA 0x28060000
+#define DDRSS3_CTL_439_DATA 0x00000128
+#define DDRSS3_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_442_DATA 0x00000000
+#define DDRSS3_CTL_443_DATA 0x00000000
+#define DDRSS3_CTL_444_DATA 0x00000000
+#define DDRSS3_CTL_445_DATA 0x00000000
+#define DDRSS3_CTL_446_DATA 0x00000000
+#define DDRSS3_CTL_447_DATA 0x00000000
+#define DDRSS3_CTL_448_DATA 0x00000000
+#define DDRSS3_CTL_449_DATA 0x00000000
+#define DDRSS3_CTL_450_DATA 0x00000000
+#define DDRSS3_CTL_451_DATA 0x00000000
+#define DDRSS3_CTL_452_DATA 0x00000000
+#define DDRSS3_CTL_453_DATA 0x00000000
+#define DDRSS3_CTL_454_DATA 0x00000000
+#define DDRSS3_CTL_455_DATA 0x00000000
+#define DDRSS3_CTL_456_DATA 0x00000000
+#define DDRSS3_CTL_457_DATA 0x00000000
+#define DDRSS3_CTL_458_DATA 0x00000000
+
+#define DDRSS3_PI_00_DATA 0x00000B00
+#define DDRSS3_PI_01_DATA 0x00000000
+#define DDRSS3_PI_02_DATA 0x00000000
+#define DDRSS3_PI_03_DATA 0x00000000
+#define DDRSS3_PI_04_DATA 0x00000000
+#define DDRSS3_PI_05_DATA 0x00000101
+#define DDRSS3_PI_06_DATA 0x00640000
+#define DDRSS3_PI_07_DATA 0x00000001
+#define DDRSS3_PI_08_DATA 0x00000000
+#define DDRSS3_PI_09_DATA 0x00000000
+#define DDRSS3_PI_10_DATA 0x00000000
+#define DDRSS3_PI_11_DATA 0x00000000
+#define DDRSS3_PI_12_DATA 0x00000007
+#define DDRSS3_PI_13_DATA 0x00010002
+#define DDRSS3_PI_14_DATA 0x0800000F
+#define DDRSS3_PI_15_DATA 0x00000103
+#define DDRSS3_PI_16_DATA 0x00000005
+#define DDRSS3_PI_17_DATA 0x00000000
+#define DDRSS3_PI_18_DATA 0x00000000
+#define DDRSS3_PI_19_DATA 0x00000000
+#define DDRSS3_PI_20_DATA 0x00000000
+#define DDRSS3_PI_21_DATA 0x00000000
+#define DDRSS3_PI_22_DATA 0x00000000
+#define DDRSS3_PI_23_DATA 0x00000000
+#define DDRSS3_PI_24_DATA 0x00000000
+#define DDRSS3_PI_25_DATA 0x00000000
+#define DDRSS3_PI_26_DATA 0x00010100
+#define DDRSS3_PI_27_DATA 0x00280A00
+#define DDRSS3_PI_28_DATA 0x00000000
+#define DDRSS3_PI_29_DATA 0x0F000000
+#define DDRSS3_PI_30_DATA 0x00003200
+#define DDRSS3_PI_31_DATA 0x00000000
+#define DDRSS3_PI_32_DATA 0x00000000
+#define DDRSS3_PI_33_DATA 0x01010102
+#define DDRSS3_PI_34_DATA 0x00000000
+#define DDRSS3_PI_35_DATA 0x000000AA
+#define DDRSS3_PI_36_DATA 0x00000055
+#define DDRSS3_PI_37_DATA 0x000000B5
+#define DDRSS3_PI_38_DATA 0x0000004A
+#define DDRSS3_PI_39_DATA 0x00000056
+#define DDRSS3_PI_40_DATA 0x000000A9
+#define DDRSS3_PI_41_DATA 0x000000A9
+#define DDRSS3_PI_42_DATA 0x000000B5
+#define DDRSS3_PI_43_DATA 0x00000000
+#define DDRSS3_PI_44_DATA 0x00000000
+#define DDRSS3_PI_45_DATA 0x000F0F00
+#define DDRSS3_PI_46_DATA 0x0000001B
+#define DDRSS3_PI_47_DATA 0x000007D0
+#define DDRSS3_PI_48_DATA 0x00000300
+#define DDRSS3_PI_49_DATA 0x00000000
+#define DDRSS3_PI_50_DATA 0x00000000
+#define DDRSS3_PI_51_DATA 0x01000000
+#define DDRSS3_PI_52_DATA 0x00010101
+#define DDRSS3_PI_53_DATA 0x00000000
+#define DDRSS3_PI_54_DATA 0x00030000
+#define DDRSS3_PI_55_DATA 0x0F000000
+#define DDRSS3_PI_56_DATA 0x00000017
+#define DDRSS3_PI_57_DATA 0x00000000
+#define DDRSS3_PI_58_DATA 0x00000000
+#define DDRSS3_PI_59_DATA 0x00000000
+#define DDRSS3_PI_60_DATA 0x0A0A140A
+#define DDRSS3_PI_61_DATA 0x10020101
+#define DDRSS3_PI_62_DATA 0x00020805
+#define DDRSS3_PI_63_DATA 0x01000404
+#define DDRSS3_PI_64_DATA 0x00000000
+#define DDRSS3_PI_65_DATA 0x00000000
+#define DDRSS3_PI_66_DATA 0x00000100
+#define DDRSS3_PI_67_DATA 0x0001010F
+#define DDRSS3_PI_68_DATA 0x00340000
+#define DDRSS3_PI_69_DATA 0x00000000
+#define DDRSS3_PI_70_DATA 0x00000000
+#define DDRSS3_PI_71_DATA 0x0000FFFF
+#define DDRSS3_PI_72_DATA 0x00000000
+#define DDRSS3_PI_73_DATA 0x00080000
+#define DDRSS3_PI_74_DATA 0x02000200
+#define DDRSS3_PI_75_DATA 0x01000100
+#define DDRSS3_PI_76_DATA 0x01000000
+#define DDRSS3_PI_77_DATA 0x02000200
+#define DDRSS3_PI_78_DATA 0x00000200
+#define DDRSS3_PI_79_DATA 0x00000000
+#define DDRSS3_PI_80_DATA 0x00000000
+#define DDRSS3_PI_81_DATA 0x00000000
+#define DDRSS3_PI_82_DATA 0x00000000
+#define DDRSS3_PI_83_DATA 0x00000000
+#define DDRSS3_PI_84_DATA 0x00000000
+#define DDRSS3_PI_85_DATA 0x00000000
+#define DDRSS3_PI_86_DATA 0x00000000
+#define DDRSS3_PI_87_DATA 0x00000000
+#define DDRSS3_PI_88_DATA 0x00000000
+#define DDRSS3_PI_89_DATA 0x00000000
+#define DDRSS3_PI_90_DATA 0x00000000
+#define DDRSS3_PI_91_DATA 0x00000400
+#define DDRSS3_PI_92_DATA 0x02010000
+#define DDRSS3_PI_93_DATA 0x00080003
+#define DDRSS3_PI_94_DATA 0x00080000
+#define DDRSS3_PI_95_DATA 0x00000001
+#define DDRSS3_PI_96_DATA 0x00000000
+#define DDRSS3_PI_97_DATA 0x0000AA00
+#define DDRSS3_PI_98_DATA 0x00000000
+#define DDRSS3_PI_99_DATA 0x00000000
+#define DDRSS3_PI_100_DATA 0x00010000
+#define DDRSS3_PI_101_DATA 0x00000000
+#define DDRSS3_PI_102_DATA 0x00000000
+#define DDRSS3_PI_103_DATA 0x00000000
+#define DDRSS3_PI_104_DATA 0x00000000
+#define DDRSS3_PI_105_DATA 0x00000000
+#define DDRSS3_PI_106_DATA 0x00000000
+#define DDRSS3_PI_107_DATA 0x00000000
+#define DDRSS3_PI_108_DATA 0x00000000
+#define DDRSS3_PI_109_DATA 0x00000000
+#define DDRSS3_PI_110_DATA 0x00000000
+#define DDRSS3_PI_111_DATA 0x00000000
+#define DDRSS3_PI_112_DATA 0x00000000
+#define DDRSS3_PI_113_DATA 0x00000000
+#define DDRSS3_PI_114_DATA 0x00000000
+#define DDRSS3_PI_115_DATA 0x00000000
+#define DDRSS3_PI_116_DATA 0x00000000
+#define DDRSS3_PI_117_DATA 0x00000000
+#define DDRSS3_PI_118_DATA 0x00000000
+#define DDRSS3_PI_119_DATA 0x00000000
+#define DDRSS3_PI_120_DATA 0x00000000
+#define DDRSS3_PI_121_DATA 0x00000000
+#define DDRSS3_PI_122_DATA 0x00000000
+#define DDRSS3_PI_123_DATA 0x00000000
+#define DDRSS3_PI_124_DATA 0x00000000
+#define DDRSS3_PI_125_DATA 0x00000008
+#define DDRSS3_PI_126_DATA 0x00000000
+#define DDRSS3_PI_127_DATA 0x00000000
+#define DDRSS3_PI_128_DATA 0x00000000
+#define DDRSS3_PI_129_DATA 0x00000000
+#define DDRSS3_PI_130_DATA 0x00000000
+#define DDRSS3_PI_131_DATA 0x00000000
+#define DDRSS3_PI_132_DATA 0x00000000
+#define DDRSS3_PI_133_DATA 0x00000000
+#define DDRSS3_PI_134_DATA 0x00000002
+#define DDRSS3_PI_135_DATA 0x00000000
+#define DDRSS3_PI_136_DATA 0x00000000
+#define DDRSS3_PI_137_DATA 0x0000000A
+#define DDRSS3_PI_138_DATA 0x00000019
+#define DDRSS3_PI_139_DATA 0x00000100
+#define DDRSS3_PI_140_DATA 0x00000000
+#define DDRSS3_PI_141_DATA 0x00000000
+#define DDRSS3_PI_142_DATA 0x00000000
+#define DDRSS3_PI_143_DATA 0x00000000
+#define DDRSS3_PI_144_DATA 0x01000000
+#define DDRSS3_PI_145_DATA 0x00010003
+#define DDRSS3_PI_146_DATA 0x02000101
+#define DDRSS3_PI_147_DATA 0x01030001
+#define DDRSS3_PI_148_DATA 0x00010400
+#define DDRSS3_PI_149_DATA 0x06000105
+#define DDRSS3_PI_150_DATA 0x01070001
+#define DDRSS3_PI_151_DATA 0x00000000
+#define DDRSS3_PI_152_DATA 0x00000000
+#define DDRSS3_PI_153_DATA 0x00000000
+#define DDRSS3_PI_154_DATA 0x00010001
+#define DDRSS3_PI_155_DATA 0x00000000
+#define DDRSS3_PI_156_DATA 0x00000000
+#define DDRSS3_PI_157_DATA 0x00000000
+#define DDRSS3_PI_158_DATA 0x00000000
+#define DDRSS3_PI_159_DATA 0x00000401
+#define DDRSS3_PI_160_DATA 0x00000000
+#define DDRSS3_PI_161_DATA 0x00010000
+#define DDRSS3_PI_162_DATA 0x00000000
+#define DDRSS3_PI_163_DATA 0x2B2B0200
+#define DDRSS3_PI_164_DATA 0x00000034
+#define DDRSS3_PI_165_DATA 0x00000064
+#define DDRSS3_PI_166_DATA 0x00020064
+#define DDRSS3_PI_167_DATA 0x02000200
+#define DDRSS3_PI_168_DATA 0x48120C04
+#define DDRSS3_PI_169_DATA 0x00154812
+#define DDRSS3_PI_170_DATA 0x000000CE
+#define DDRSS3_PI_171_DATA 0x0000032B
+#define DDRSS3_PI_172_DATA 0x00002073
+#define DDRSS3_PI_173_DATA 0x0000032B
+#define DDRSS3_PI_174_DATA 0x04002073
+#define DDRSS3_PI_175_DATA 0x01010404
+#define DDRSS3_PI_176_DATA 0x00001501
+#define DDRSS3_PI_177_DATA 0x00150015
+#define DDRSS3_PI_178_DATA 0x01000100
+#define DDRSS3_PI_179_DATA 0x00000100
+#define DDRSS3_PI_180_DATA 0x00000000
+#define DDRSS3_PI_181_DATA 0x01010101
+#define DDRSS3_PI_182_DATA 0x00000101
+#define DDRSS3_PI_183_DATA 0x00000000
+#define DDRSS3_PI_184_DATA 0x00000000
+#define DDRSS3_PI_185_DATA 0x15040000
+#define DDRSS3_PI_186_DATA 0x0E0E0215
+#define DDRSS3_PI_187_DATA 0x00040402
+#define DDRSS3_PI_188_DATA 0x000D0035
+#define DDRSS3_PI_189_DATA 0x00218049
+#define DDRSS3_PI_190_DATA 0x00218049
+#define DDRSS3_PI_191_DATA 0x01010101
+#define DDRSS3_PI_192_DATA 0x0004000E
+#define DDRSS3_PI_193_DATA 0x00040216
+#define DDRSS3_PI_194_DATA 0x01000216
+#define DDRSS3_PI_195_DATA 0x000F000F
+#define DDRSS3_PI_196_DATA 0x02170100
+#define DDRSS3_PI_197_DATA 0x01000217
+#define DDRSS3_PI_198_DATA 0x02170217
+#define DDRSS3_PI_199_DATA 0x32103200
+#define DDRSS3_PI_200_DATA 0x01013210
+#define DDRSS3_PI_201_DATA 0x0A070601
+#define DDRSS3_PI_202_DATA 0x1F130A0D
+#define DDRSS3_PI_203_DATA 0x1F130A14
+#define DDRSS3_PI_204_DATA 0x0000C014
+#define DDRSS3_PI_205_DATA 0x00C01000
+#define DDRSS3_PI_206_DATA 0x00C01000
+#define DDRSS3_PI_207_DATA 0x00021000
+#define DDRSS3_PI_208_DATA 0x0024000E
+#define DDRSS3_PI_209_DATA 0x00240216
+#define DDRSS3_PI_210_DATA 0x00110216
+#define DDRSS3_PI_211_DATA 0x32000056
+#define DDRSS3_PI_212_DATA 0x00000301
+#define DDRSS3_PI_213_DATA 0x005B0036
+#define DDRSS3_PI_214_DATA 0x03013212
+#define DDRSS3_PI_215_DATA 0x00003600
+#define DDRSS3_PI_216_DATA 0x3212005B
+#define DDRSS3_PI_217_DATA 0x09000301
+#define DDRSS3_PI_218_DATA 0x04010504
+#define DDRSS3_PI_219_DATA 0x040006C9
+#define DDRSS3_PI_220_DATA 0x0A032001
+#define DDRSS3_PI_221_DATA 0x2C31110A
+#define DDRSS3_PI_222_DATA 0x00002918
+#define DDRSS3_PI_223_DATA 0x6001071C
+#define DDRSS3_PI_224_DATA 0x1E202008
+#define DDRSS3_PI_225_DATA 0x2C311116
+#define DDRSS3_PI_226_DATA 0x00002918
+#define DDRSS3_PI_227_DATA 0x6001071C
+#define DDRSS3_PI_228_DATA 0x1E202008
+#define DDRSS3_PI_229_DATA 0x00019C16
+#define DDRSS3_PI_230_DATA 0x00001018
+#define DDRSS3_PI_231_DATA 0x000040E6
+#define DDRSS3_PI_232_DATA 0x000288FC
+#define DDRSS3_PI_233_DATA 0x000040E6
+#define DDRSS3_PI_234_DATA 0x000288FC
+#define DDRSS3_PI_235_DATA 0x033B0016
+#define DDRSS3_PI_236_DATA 0x0303033B
+#define DDRSS3_PI_237_DATA 0x002AF803
+#define DDRSS3_PI_238_DATA 0x0001ADAF
+#define DDRSS3_PI_239_DATA 0x00000005
+#define DDRSS3_PI_240_DATA 0x0000006E
+#define DDRSS3_PI_241_DATA 0x00000016
+#define DDRSS3_PI_242_DATA 0x000681C8
+#define DDRSS3_PI_243_DATA 0x0001ADAF
+#define DDRSS3_PI_244_DATA 0x00000005
+#define DDRSS3_PI_245_DATA 0x000010A9
+#define DDRSS3_PI_246_DATA 0x0000033B
+#define DDRSS3_PI_247_DATA 0x000681C8
+#define DDRSS3_PI_248_DATA 0x0001ADAF
+#define DDRSS3_PI_249_DATA 0x00000005
+#define DDRSS3_PI_250_DATA 0x000010A9
+#define DDRSS3_PI_251_DATA 0x0100033B
+#define DDRSS3_PI_252_DATA 0x00370040
+#define DDRSS3_PI_253_DATA 0x00010008
+#define DDRSS3_PI_254_DATA 0x08550040
+#define DDRSS3_PI_255_DATA 0x00010040
+#define DDRSS3_PI_256_DATA 0x08550040
+#define DDRSS3_PI_257_DATA 0x00000340
+#define DDRSS3_PI_258_DATA 0x006B006B
+#define DDRSS3_PI_259_DATA 0x08040404
+#define DDRSS3_PI_260_DATA 0x00000055
+#define DDRSS3_PI_261_DATA 0x55083C5A
+#define DDRSS3_PI_262_DATA 0x5A000000
+#define DDRSS3_PI_263_DATA 0x0055083C
+#define DDRSS3_PI_264_DATA 0x3C5A0000
+#define DDRSS3_PI_265_DATA 0x00005508
+#define DDRSS3_PI_266_DATA 0x0C3C5A00
+#define DDRSS3_PI_267_DATA 0x080F0E0D
+#define DDRSS3_PI_268_DATA 0x000B0A09
+#define DDRSS3_PI_269_DATA 0x00030201
+#define DDRSS3_PI_270_DATA 0x01000000
+#define DDRSS3_PI_271_DATA 0x04020201
+#define DDRSS3_PI_272_DATA 0x00080804
+#define DDRSS3_PI_273_DATA 0x00000000
+#define DDRSS3_PI_274_DATA 0x00000000
+#define DDRSS3_PI_275_DATA 0x00330084
+#define DDRSS3_PI_276_DATA 0x00160000
+#define DDRSS3_PI_277_DATA 0x35333FF4
+#define DDRSS3_PI_278_DATA 0x00160F27
+#define DDRSS3_PI_279_DATA 0x35333FF4
+#define DDRSS3_PI_280_DATA 0x00160F27
+#define DDRSS3_PI_281_DATA 0x00330084
+#define DDRSS3_PI_282_DATA 0x00160000
+#define DDRSS3_PI_283_DATA 0x35333FF4
+#define DDRSS3_PI_284_DATA 0x00160F27
+#define DDRSS3_PI_285_DATA 0x35333FF4
+#define DDRSS3_PI_286_DATA 0x00160F27
+#define DDRSS3_PI_287_DATA 0x00330084
+#define DDRSS3_PI_288_DATA 0x00160000
+#define DDRSS3_PI_289_DATA 0x35333FF4
+#define DDRSS3_PI_290_DATA 0x00160F27
+#define DDRSS3_PI_291_DATA 0x35333FF4
+#define DDRSS3_PI_292_DATA 0x00160F27
+#define DDRSS3_PI_293_DATA 0x00330084
+#define DDRSS3_PI_294_DATA 0x00160000
+#define DDRSS3_PI_295_DATA 0x35333FF4
+#define DDRSS3_PI_296_DATA 0x00160F27
+#define DDRSS3_PI_297_DATA 0x35333FF4
+#define DDRSS3_PI_298_DATA 0x00160F27
+#define DDRSS3_PI_299_DATA 0x00000000
+
+#define DDRSS3_PHY_00_DATA 0x000004F0
+#define DDRSS3_PHY_01_DATA 0x00000000
+#define DDRSS3_PHY_02_DATA 0x00030200
+#define DDRSS3_PHY_03_DATA 0x00000000
+#define DDRSS3_PHY_04_DATA 0x00000000
+#define DDRSS3_PHY_05_DATA 0x01030000
+#define DDRSS3_PHY_06_DATA 0x00010000
+#define DDRSS3_PHY_07_DATA 0x01030004
+#define DDRSS3_PHY_08_DATA 0x01000000
+#define DDRSS3_PHY_09_DATA 0x00000000
+#define DDRSS3_PHY_10_DATA 0x00000000
+#define DDRSS3_PHY_11_DATA 0x01000001
+#define DDRSS3_PHY_12_DATA 0x00000100
+#define DDRSS3_PHY_13_DATA 0x000800C0
+#define DDRSS3_PHY_14_DATA 0x060100CC
+#define DDRSS3_PHY_15_DATA 0x00030066
+#define DDRSS3_PHY_16_DATA 0x00000000
+#define DDRSS3_PHY_17_DATA 0x00000301
+#define DDRSS3_PHY_18_DATA 0x0000AAAA
+#define DDRSS3_PHY_19_DATA 0x00005555
+#define DDRSS3_PHY_20_DATA 0x0000B5B5
+#define DDRSS3_PHY_21_DATA 0x00004A4A
+#define DDRSS3_PHY_22_DATA 0x00005656
+#define DDRSS3_PHY_23_DATA 0x0000A9A9
+#define DDRSS3_PHY_24_DATA 0x0000A9A9
+#define DDRSS3_PHY_25_DATA 0x0000B5B5
+#define DDRSS3_PHY_26_DATA 0x00000000
+#define DDRSS3_PHY_27_DATA 0x00000000
+#define DDRSS3_PHY_28_DATA 0x2A000000
+#define DDRSS3_PHY_29_DATA 0x00000808
+#define DDRSS3_PHY_30_DATA 0x0F000000
+#define DDRSS3_PHY_31_DATA 0x00000F0F
+#define DDRSS3_PHY_32_DATA 0x10400000
+#define DDRSS3_PHY_33_DATA 0x0C002006
+#define DDRSS3_PHY_34_DATA 0x00000000
+#define DDRSS3_PHY_35_DATA 0x00000000
+#define DDRSS3_PHY_36_DATA 0x55555555
+#define DDRSS3_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_38_DATA 0x55555555
+#define DDRSS3_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_40_DATA 0x00005555
+#define DDRSS3_PHY_41_DATA 0x01000100
+#define DDRSS3_PHY_42_DATA 0x00800180
+#define DDRSS3_PHY_43_DATA 0x00000001
+#define DDRSS3_PHY_44_DATA 0x00000000
+#define DDRSS3_PHY_45_DATA 0x00000000
+#define DDRSS3_PHY_46_DATA 0x00000000
+#define DDRSS3_PHY_47_DATA 0x00000000
+#define DDRSS3_PHY_48_DATA 0x00000000
+#define DDRSS3_PHY_49_DATA 0x00000000
+#define DDRSS3_PHY_50_DATA 0x00000000
+#define DDRSS3_PHY_51_DATA 0x00000000
+#define DDRSS3_PHY_52_DATA 0x00000000
+#define DDRSS3_PHY_53_DATA 0x00000000
+#define DDRSS3_PHY_54_DATA 0x00000000
+#define DDRSS3_PHY_55_DATA 0x00000000
+#define DDRSS3_PHY_56_DATA 0x00000000
+#define DDRSS3_PHY_57_DATA 0x00000000
+#define DDRSS3_PHY_58_DATA 0x00000000
+#define DDRSS3_PHY_59_DATA 0x00000000
+#define DDRSS3_PHY_60_DATA 0x00000000
+#define DDRSS3_PHY_61_DATA 0x00000000
+#define DDRSS3_PHY_62_DATA 0x00000000
+#define DDRSS3_PHY_63_DATA 0x00000000
+#define DDRSS3_PHY_64_DATA 0x00000000
+#define DDRSS3_PHY_65_DATA 0x00000000
+#define DDRSS3_PHY_66_DATA 0x00000104
+#define DDRSS3_PHY_67_DATA 0x00000120
+#define DDRSS3_PHY_68_DATA 0x00000000
+#define DDRSS3_PHY_69_DATA 0x00000000
+#define DDRSS3_PHY_70_DATA 0x00000000
+#define DDRSS3_PHY_71_DATA 0x00000000
+#define DDRSS3_PHY_72_DATA 0x00000000
+#define DDRSS3_PHY_73_DATA 0x00000000
+#define DDRSS3_PHY_74_DATA 0x00000000
+#define DDRSS3_PHY_75_DATA 0x00000001
+#define DDRSS3_PHY_76_DATA 0x07FF0000
+#define DDRSS3_PHY_77_DATA 0x0080081F
+#define DDRSS3_PHY_78_DATA 0x00081020
+#define DDRSS3_PHY_79_DATA 0x04010000
+#define DDRSS3_PHY_80_DATA 0x00000000
+#define DDRSS3_PHY_81_DATA 0x00000000
+#define DDRSS3_PHY_82_DATA 0x00000000
+#define DDRSS3_PHY_83_DATA 0x00000100
+#define DDRSS3_PHY_84_DATA 0x01CC0C01
+#define DDRSS3_PHY_85_DATA 0x1003CC0C
+#define DDRSS3_PHY_86_DATA 0x20000140
+#define DDRSS3_PHY_87_DATA 0x07FF0200
+#define DDRSS3_PHY_88_DATA 0x0000DD01
+#define DDRSS3_PHY_89_DATA 0x10100303
+#define DDRSS3_PHY_90_DATA 0x10101010
+#define DDRSS3_PHY_91_DATA 0x10101010
+#define DDRSS3_PHY_92_DATA 0x00021010
+#define DDRSS3_PHY_93_DATA 0x00100010
+#define DDRSS3_PHY_94_DATA 0x00100010
+#define DDRSS3_PHY_95_DATA 0x00100010
+#define DDRSS3_PHY_96_DATA 0x00100010
+#define DDRSS3_PHY_97_DATA 0x00050010
+#define DDRSS3_PHY_98_DATA 0x51517041
+#define DDRSS3_PHY_99_DATA 0x31C06001
+#define DDRSS3_PHY_100_DATA 0x07AB0340
+#define DDRSS3_PHY_101_DATA 0x00C0C001
+#define DDRSS3_PHY_102_DATA 0x0E0D0001
+#define DDRSS3_PHY_103_DATA 0x10001000
+#define DDRSS3_PHY_104_DATA 0x0C083E42
+#define DDRSS3_PHY_105_DATA 0x0F0C3701
+#define DDRSS3_PHY_106_DATA 0x01000140
+#define DDRSS3_PHY_107_DATA 0x0C000420
+#define DDRSS3_PHY_108_DATA 0x00000198
+#define DDRSS3_PHY_109_DATA 0x0A0000D0
+#define DDRSS3_PHY_110_DATA 0x00030200
+#define DDRSS3_PHY_111_DATA 0x02800000
+#define DDRSS3_PHY_112_DATA 0x80800000
+#define DDRSS3_PHY_113_DATA 0x000E2010
+#define DDRSS3_PHY_114_DATA 0x76543210
+#define DDRSS3_PHY_115_DATA 0x00000008
+#define DDRSS3_PHY_116_DATA 0x02800280
+#define DDRSS3_PHY_117_DATA 0x02800280
+#define DDRSS3_PHY_118_DATA 0x02800280
+#define DDRSS3_PHY_119_DATA 0x02800280
+#define DDRSS3_PHY_120_DATA 0x00000280
+#define DDRSS3_PHY_121_DATA 0x0000A000
+#define DDRSS3_PHY_122_DATA 0x00A000A0
+#define DDRSS3_PHY_123_DATA 0x00A000A0
+#define DDRSS3_PHY_124_DATA 0x00A000A0
+#define DDRSS3_PHY_125_DATA 0x00A000A0
+#define DDRSS3_PHY_126_DATA 0x00A000A0
+#define DDRSS3_PHY_127_DATA 0x00A000A0
+#define DDRSS3_PHY_128_DATA 0x00A000A0
+#define DDRSS3_PHY_129_DATA 0x00A000A0
+#define DDRSS3_PHY_130_DATA 0x01C200A0
+#define DDRSS3_PHY_131_DATA 0x01A00005
+#define DDRSS3_PHY_132_DATA 0x00000000
+#define DDRSS3_PHY_133_DATA 0x00000000
+#define DDRSS3_PHY_134_DATA 0x00080200
+#define DDRSS3_PHY_135_DATA 0x00000000
+#define DDRSS3_PHY_136_DATA 0x20202000
+#define DDRSS3_PHY_137_DATA 0x20202020
+#define DDRSS3_PHY_138_DATA 0xF0F02020
+#define DDRSS3_PHY_139_DATA 0x00000000
+#define DDRSS3_PHY_140_DATA 0x00000000
+#define DDRSS3_PHY_141_DATA 0x00000000
+#define DDRSS3_PHY_142_DATA 0x00000000
+#define DDRSS3_PHY_143_DATA 0x00000000
+#define DDRSS3_PHY_144_DATA 0x00000000
+#define DDRSS3_PHY_145_DATA 0x00000000
+#define DDRSS3_PHY_146_DATA 0x00000000
+#define DDRSS3_PHY_147_DATA 0x00000000
+#define DDRSS3_PHY_148_DATA 0x00000000
+#define DDRSS3_PHY_149_DATA 0x00000000
+#define DDRSS3_PHY_150_DATA 0x00000000
+#define DDRSS3_PHY_151_DATA 0x00000000
+#define DDRSS3_PHY_152_DATA 0x00000000
+#define DDRSS3_PHY_153_DATA 0x00000000
+#define DDRSS3_PHY_154_DATA 0x00000000
+#define DDRSS3_PHY_155_DATA 0x00000000
+#define DDRSS3_PHY_156_DATA 0x00000000
+#define DDRSS3_PHY_157_DATA 0x00000000
+#define DDRSS3_PHY_158_DATA 0x00000000
+#define DDRSS3_PHY_159_DATA 0x00000000
+#define DDRSS3_PHY_160_DATA 0x00000000
+#define DDRSS3_PHY_161_DATA 0x00000000
+#define DDRSS3_PHY_162_DATA 0x00000000
+#define DDRSS3_PHY_163_DATA 0x00000000
+#define DDRSS3_PHY_164_DATA 0x00000000
+#define DDRSS3_PHY_165_DATA 0x00000000
+#define DDRSS3_PHY_166_DATA 0x00000000
+#define DDRSS3_PHY_167_DATA 0x00000000
+#define DDRSS3_PHY_168_DATA 0x00000000
+#define DDRSS3_PHY_169_DATA 0x00000000
+#define DDRSS3_PHY_170_DATA 0x00000000
+#define DDRSS3_PHY_171_DATA 0x00000000
+#define DDRSS3_PHY_172_DATA 0x00000000
+#define DDRSS3_PHY_173_DATA 0x00000000
+#define DDRSS3_PHY_174_DATA 0x00000000
+#define DDRSS3_PHY_175_DATA 0x00000000
+#define DDRSS3_PHY_176_DATA 0x00000000
+#define DDRSS3_PHY_177_DATA 0x00000000
+#define DDRSS3_PHY_178_DATA 0x00000000
+#define DDRSS3_PHY_179_DATA 0x00000000
+#define DDRSS3_PHY_180_DATA 0x00000000
+#define DDRSS3_PHY_181_DATA 0x00000000
+#define DDRSS3_PHY_182_DATA 0x00000000
+#define DDRSS3_PHY_183_DATA 0x00000000
+#define DDRSS3_PHY_184_DATA 0x00000000
+#define DDRSS3_PHY_185_DATA 0x00000000
+#define DDRSS3_PHY_186_DATA 0x00000000
+#define DDRSS3_PHY_187_DATA 0x00000000
+#define DDRSS3_PHY_188_DATA 0x00000000
+#define DDRSS3_PHY_189_DATA 0x00000000
+#define DDRSS3_PHY_190_DATA 0x00000000
+#define DDRSS3_PHY_191_DATA 0x00000000
+#define DDRSS3_PHY_192_DATA 0x00000000
+#define DDRSS3_PHY_193_DATA 0x00000000
+#define DDRSS3_PHY_194_DATA 0x00000000
+#define DDRSS3_PHY_195_DATA 0x00000000
+#define DDRSS3_PHY_196_DATA 0x00000000
+#define DDRSS3_PHY_197_DATA 0x00000000
+#define DDRSS3_PHY_198_DATA 0x00000000
+#define DDRSS3_PHY_199_DATA 0x00000000
+#define DDRSS3_PHY_200_DATA 0x00000000
+#define DDRSS3_PHY_201_DATA 0x00000000
+#define DDRSS3_PHY_202_DATA 0x00000000
+#define DDRSS3_PHY_203_DATA 0x00000000
+#define DDRSS3_PHY_204_DATA 0x00000000
+#define DDRSS3_PHY_205_DATA 0x00000000
+#define DDRSS3_PHY_206_DATA 0x00000000
+#define DDRSS3_PHY_207_DATA 0x00000000
+#define DDRSS3_PHY_208_DATA 0x00000000
+#define DDRSS3_PHY_209_DATA 0x00000000
+#define DDRSS3_PHY_210_DATA 0x00000000
+#define DDRSS3_PHY_211_DATA 0x00000000
+#define DDRSS3_PHY_212_DATA 0x00000000
+#define DDRSS3_PHY_213_DATA 0x00000000
+#define DDRSS3_PHY_214_DATA 0x00000000
+#define DDRSS3_PHY_215_DATA 0x00000000
+#define DDRSS3_PHY_216_DATA 0x00000000
+#define DDRSS3_PHY_217_DATA 0x00000000
+#define DDRSS3_PHY_218_DATA 0x00000000
+#define DDRSS3_PHY_219_DATA 0x00000000
+#define DDRSS3_PHY_220_DATA 0x00000000
+#define DDRSS3_PHY_221_DATA 0x00000000
+#define DDRSS3_PHY_222_DATA 0x00000000
+#define DDRSS3_PHY_223_DATA 0x00000000
+#define DDRSS3_PHY_224_DATA 0x00000000
+#define DDRSS3_PHY_225_DATA 0x00000000
+#define DDRSS3_PHY_226_DATA 0x00000000
+#define DDRSS3_PHY_227_DATA 0x00000000
+#define DDRSS3_PHY_228_DATA 0x00000000
+#define DDRSS3_PHY_229_DATA 0x00000000
+#define DDRSS3_PHY_230_DATA 0x00000000
+#define DDRSS3_PHY_231_DATA 0x00000000
+#define DDRSS3_PHY_232_DATA 0x00000000
+#define DDRSS3_PHY_233_DATA 0x00000000
+#define DDRSS3_PHY_234_DATA 0x00000000
+#define DDRSS3_PHY_235_DATA 0x00000000
+#define DDRSS3_PHY_236_DATA 0x00000000
+#define DDRSS3_PHY_237_DATA 0x00000000
+#define DDRSS3_PHY_238_DATA 0x00000000
+#define DDRSS3_PHY_239_DATA 0x00000000
+#define DDRSS3_PHY_240_DATA 0x00000000
+#define DDRSS3_PHY_241_DATA 0x00000000
+#define DDRSS3_PHY_242_DATA 0x00000000
+#define DDRSS3_PHY_243_DATA 0x00000000
+#define DDRSS3_PHY_244_DATA 0x00000000
+#define DDRSS3_PHY_245_DATA 0x00000000
+#define DDRSS3_PHY_246_DATA 0x00000000
+#define DDRSS3_PHY_247_DATA 0x00000000
+#define DDRSS3_PHY_248_DATA 0x00000000
+#define DDRSS3_PHY_249_DATA 0x00000000
+#define DDRSS3_PHY_250_DATA 0x00000000
+#define DDRSS3_PHY_251_DATA 0x00000000
+#define DDRSS3_PHY_252_DATA 0x00000000
+#define DDRSS3_PHY_253_DATA 0x00000000
+#define DDRSS3_PHY_254_DATA 0x00000000
+#define DDRSS3_PHY_255_DATA 0x00000000
+#define DDRSS3_PHY_256_DATA 0x000004F0
+#define DDRSS3_PHY_257_DATA 0x00000000
+#define DDRSS3_PHY_258_DATA 0x00030200
+#define DDRSS3_PHY_259_DATA 0x00000000
+#define DDRSS3_PHY_260_DATA 0x00000000
+#define DDRSS3_PHY_261_DATA 0x01030000
+#define DDRSS3_PHY_262_DATA 0x00010000
+#define DDRSS3_PHY_263_DATA 0x01030004
+#define DDRSS3_PHY_264_DATA 0x01000000
+#define DDRSS3_PHY_265_DATA 0x00000000
+#define DDRSS3_PHY_266_DATA 0x00000000
+#define DDRSS3_PHY_267_DATA 0x01000001
+#define DDRSS3_PHY_268_DATA 0x00000100
+#define DDRSS3_PHY_269_DATA 0x000800C0
+#define DDRSS3_PHY_270_DATA 0x060100CC
+#define DDRSS3_PHY_271_DATA 0x00030066
+#define DDRSS3_PHY_272_DATA 0x00000000
+#define DDRSS3_PHY_273_DATA 0x00000301
+#define DDRSS3_PHY_274_DATA 0x0000AAAA
+#define DDRSS3_PHY_275_DATA 0x00005555
+#define DDRSS3_PHY_276_DATA 0x0000B5B5
+#define DDRSS3_PHY_277_DATA 0x00004A4A
+#define DDRSS3_PHY_278_DATA 0x00005656
+#define DDRSS3_PHY_279_DATA 0x0000A9A9
+#define DDRSS3_PHY_280_DATA 0x0000A9A9
+#define DDRSS3_PHY_281_DATA 0x0000B5B5
+#define DDRSS3_PHY_282_DATA 0x00000000
+#define DDRSS3_PHY_283_DATA 0x00000000
+#define DDRSS3_PHY_284_DATA 0x2A000000
+#define DDRSS3_PHY_285_DATA 0x00000808
+#define DDRSS3_PHY_286_DATA 0x0F000000
+#define DDRSS3_PHY_287_DATA 0x00000F0F
+#define DDRSS3_PHY_288_DATA 0x10400000
+#define DDRSS3_PHY_289_DATA 0x0C002006
+#define DDRSS3_PHY_290_DATA 0x00000000
+#define DDRSS3_PHY_291_DATA 0x00000000
+#define DDRSS3_PHY_292_DATA 0x55555555
+#define DDRSS3_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_294_DATA 0x55555555
+#define DDRSS3_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_296_DATA 0x00005555
+#define DDRSS3_PHY_297_DATA 0x01000100
+#define DDRSS3_PHY_298_DATA 0x00800180
+#define DDRSS3_PHY_299_DATA 0x00000000
+#define DDRSS3_PHY_300_DATA 0x00000000
+#define DDRSS3_PHY_301_DATA 0x00000000
+#define DDRSS3_PHY_302_DATA 0x00000000
+#define DDRSS3_PHY_303_DATA 0x00000000
+#define DDRSS3_PHY_304_DATA 0x00000000
+#define DDRSS3_PHY_305_DATA 0x00000000
+#define DDRSS3_PHY_306_DATA 0x00000000
+#define DDRSS3_PHY_307_DATA 0x00000000
+#define DDRSS3_PHY_308_DATA 0x00000000
+#define DDRSS3_PHY_309_DATA 0x00000000
+#define DDRSS3_PHY_310_DATA 0x00000000
+#define DDRSS3_PHY_311_DATA 0x00000000
+#define DDRSS3_PHY_312_DATA 0x00000000
+#define DDRSS3_PHY_313_DATA 0x00000000
+#define DDRSS3_PHY_314_DATA 0x00000000
+#define DDRSS3_PHY_315_DATA 0x00000000
+#define DDRSS3_PHY_316_DATA 0x00000000
+#define DDRSS3_PHY_317_DATA 0x00000000
+#define DDRSS3_PHY_318_DATA 0x00000000
+#define DDRSS3_PHY_319_DATA 0x00000000
+#define DDRSS3_PHY_320_DATA 0x00000000
+#define DDRSS3_PHY_321_DATA 0x00000000
+#define DDRSS3_PHY_322_DATA 0x00000104
+#define DDRSS3_PHY_323_DATA 0x00000120
+#define DDRSS3_PHY_324_DATA 0x00000000
+#define DDRSS3_PHY_325_DATA 0x00000000
+#define DDRSS3_PHY_326_DATA 0x00000000
+#define DDRSS3_PHY_327_DATA 0x00000000
+#define DDRSS3_PHY_328_DATA 0x00000000
+#define DDRSS3_PHY_329_DATA 0x00000000
+#define DDRSS3_PHY_330_DATA 0x00000000
+#define DDRSS3_PHY_331_DATA 0x00000001
+#define DDRSS3_PHY_332_DATA 0x07FF0000
+#define DDRSS3_PHY_333_DATA 0x0080081F
+#define DDRSS3_PHY_334_DATA 0x00081020
+#define DDRSS3_PHY_335_DATA 0x04010000
+#define DDRSS3_PHY_336_DATA 0x00000000
+#define DDRSS3_PHY_337_DATA 0x00000000
+#define DDRSS3_PHY_338_DATA 0x00000000
+#define DDRSS3_PHY_339_DATA 0x00000100
+#define DDRSS3_PHY_340_DATA 0x01CC0C01
+#define DDRSS3_PHY_341_DATA 0x1003CC0C
+#define DDRSS3_PHY_342_DATA 0x20000140
+#define DDRSS3_PHY_343_DATA 0x07FF0200
+#define DDRSS3_PHY_344_DATA 0x0000DD01
+#define DDRSS3_PHY_345_DATA 0x10100303
+#define DDRSS3_PHY_346_DATA 0x10101010
+#define DDRSS3_PHY_347_DATA 0x10101010
+#define DDRSS3_PHY_348_DATA 0x00021010
+#define DDRSS3_PHY_349_DATA 0x00100010
+#define DDRSS3_PHY_350_DATA 0x00100010
+#define DDRSS3_PHY_351_DATA 0x00100010
+#define DDRSS3_PHY_352_DATA 0x00100010
+#define DDRSS3_PHY_353_DATA 0x00050010
+#define DDRSS3_PHY_354_DATA 0x51517041
+#define DDRSS3_PHY_355_DATA 0x31C06001
+#define DDRSS3_PHY_356_DATA 0x07AB0340
+#define DDRSS3_PHY_357_DATA 0x00C0C001
+#define DDRSS3_PHY_358_DATA 0x0E0D0001
+#define DDRSS3_PHY_359_DATA 0x10001000
+#define DDRSS3_PHY_360_DATA 0x0C083E42
+#define DDRSS3_PHY_361_DATA 0x0F0C3701
+#define DDRSS3_PHY_362_DATA 0x01000140
+#define DDRSS3_PHY_363_DATA 0x0C000420
+#define DDRSS3_PHY_364_DATA 0x00000198
+#define DDRSS3_PHY_365_DATA 0x0A0000D0
+#define DDRSS3_PHY_366_DATA 0x00030200
+#define DDRSS3_PHY_367_DATA 0x02800000
+#define DDRSS3_PHY_368_DATA 0x80800000
+#define DDRSS3_PHY_369_DATA 0x000E2010
+#define DDRSS3_PHY_370_DATA 0x76543210
+#define DDRSS3_PHY_371_DATA 0x00000008
+#define DDRSS3_PHY_372_DATA 0x02800280
+#define DDRSS3_PHY_373_DATA 0x02800280
+#define DDRSS3_PHY_374_DATA 0x02800280
+#define DDRSS3_PHY_375_DATA 0x02800280
+#define DDRSS3_PHY_376_DATA 0x00000280
+#define DDRSS3_PHY_377_DATA 0x0000A000
+#define DDRSS3_PHY_378_DATA 0x00A000A0
+#define DDRSS3_PHY_379_DATA 0x00A000A0
+#define DDRSS3_PHY_380_DATA 0x00A000A0
+#define DDRSS3_PHY_381_DATA 0x00A000A0
+#define DDRSS3_PHY_382_DATA 0x00A000A0
+#define DDRSS3_PHY_383_DATA 0x00A000A0
+#define DDRSS3_PHY_384_DATA 0x00A000A0
+#define DDRSS3_PHY_385_DATA 0x00A000A0
+#define DDRSS3_PHY_386_DATA 0x01C200A0
+#define DDRSS3_PHY_387_DATA 0x01A00005
+#define DDRSS3_PHY_388_DATA 0x00000000
+#define DDRSS3_PHY_389_DATA 0x00000000
+#define DDRSS3_PHY_390_DATA 0x00080200
+#define DDRSS3_PHY_391_DATA 0x00000000
+#define DDRSS3_PHY_392_DATA 0x20202000
+#define DDRSS3_PHY_393_DATA 0x20202020
+#define DDRSS3_PHY_394_DATA 0xF0F02020
+#define DDRSS3_PHY_395_DATA 0x00000000
+#define DDRSS3_PHY_396_DATA 0x00000000
+#define DDRSS3_PHY_397_DATA 0x00000000
+#define DDRSS3_PHY_398_DATA 0x00000000
+#define DDRSS3_PHY_399_DATA 0x00000000
+#define DDRSS3_PHY_400_DATA 0x00000000
+#define DDRSS3_PHY_401_DATA 0x00000000
+#define DDRSS3_PHY_402_DATA 0x00000000
+#define DDRSS3_PHY_403_DATA 0x00000000
+#define DDRSS3_PHY_404_DATA 0x00000000
+#define DDRSS3_PHY_405_DATA 0x00000000
+#define DDRSS3_PHY_406_DATA 0x00000000
+#define DDRSS3_PHY_407_DATA 0x00000000
+#define DDRSS3_PHY_408_DATA 0x00000000
+#define DDRSS3_PHY_409_DATA 0x00000000
+#define DDRSS3_PHY_410_DATA 0x00000000
+#define DDRSS3_PHY_411_DATA 0x00000000
+#define DDRSS3_PHY_412_DATA 0x00000000
+#define DDRSS3_PHY_413_DATA 0x00000000
+#define DDRSS3_PHY_414_DATA 0x00000000
+#define DDRSS3_PHY_415_DATA 0x00000000
+#define DDRSS3_PHY_416_DATA 0x00000000
+#define DDRSS3_PHY_417_DATA 0x00000000
+#define DDRSS3_PHY_418_DATA 0x00000000
+#define DDRSS3_PHY_419_DATA 0x00000000
+#define DDRSS3_PHY_420_DATA 0x00000000
+#define DDRSS3_PHY_421_DATA 0x00000000
+#define DDRSS3_PHY_422_DATA 0x00000000
+#define DDRSS3_PHY_423_DATA 0x00000000
+#define DDRSS3_PHY_424_DATA 0x00000000
+#define DDRSS3_PHY_425_DATA 0x00000000
+#define DDRSS3_PHY_426_DATA 0x00000000
+#define DDRSS3_PHY_427_DATA 0x00000000
+#define DDRSS3_PHY_428_DATA 0x00000000
+#define DDRSS3_PHY_429_DATA 0x00000000
+#define DDRSS3_PHY_430_DATA 0x00000000
+#define DDRSS3_PHY_431_DATA 0x00000000
+#define DDRSS3_PHY_432_DATA 0x00000000
+#define DDRSS3_PHY_433_DATA 0x00000000
+#define DDRSS3_PHY_434_DATA 0x00000000
+#define DDRSS3_PHY_435_DATA 0x00000000
+#define DDRSS3_PHY_436_DATA 0x00000000
+#define DDRSS3_PHY_437_DATA 0x00000000
+#define DDRSS3_PHY_438_DATA 0x00000000
+#define DDRSS3_PHY_439_DATA 0x00000000
+#define DDRSS3_PHY_440_DATA 0x00000000
+#define DDRSS3_PHY_441_DATA 0x00000000
+#define DDRSS3_PHY_442_DATA 0x00000000
+#define DDRSS3_PHY_443_DATA 0x00000000
+#define DDRSS3_PHY_444_DATA 0x00000000
+#define DDRSS3_PHY_445_DATA 0x00000000
+#define DDRSS3_PHY_446_DATA 0x00000000
+#define DDRSS3_PHY_447_DATA 0x00000000
+#define DDRSS3_PHY_448_DATA 0x00000000
+#define DDRSS3_PHY_449_DATA 0x00000000
+#define DDRSS3_PHY_450_DATA 0x00000000
+#define DDRSS3_PHY_451_DATA 0x00000000
+#define DDRSS3_PHY_452_DATA 0x00000000
+#define DDRSS3_PHY_453_DATA 0x00000000
+#define DDRSS3_PHY_454_DATA 0x00000000
+#define DDRSS3_PHY_455_DATA 0x00000000
+#define DDRSS3_PHY_456_DATA 0x00000000
+#define DDRSS3_PHY_457_DATA 0x00000000
+#define DDRSS3_PHY_458_DATA 0x00000000
+#define DDRSS3_PHY_459_DATA 0x00000000
+#define DDRSS3_PHY_460_DATA 0x00000000
+#define DDRSS3_PHY_461_DATA 0x00000000
+#define DDRSS3_PHY_462_DATA 0x00000000
+#define DDRSS3_PHY_463_DATA 0x00000000
+#define DDRSS3_PHY_464_DATA 0x00000000
+#define DDRSS3_PHY_465_DATA 0x00000000
+#define DDRSS3_PHY_466_DATA 0x00000000
+#define DDRSS3_PHY_467_DATA 0x00000000
+#define DDRSS3_PHY_468_DATA 0x00000000
+#define DDRSS3_PHY_469_DATA 0x00000000
+#define DDRSS3_PHY_470_DATA 0x00000000
+#define DDRSS3_PHY_471_DATA 0x00000000
+#define DDRSS3_PHY_472_DATA 0x00000000
+#define DDRSS3_PHY_473_DATA 0x00000000
+#define DDRSS3_PHY_474_DATA 0x00000000
+#define DDRSS3_PHY_475_DATA 0x00000000
+#define DDRSS3_PHY_476_DATA 0x00000000
+#define DDRSS3_PHY_477_DATA 0x00000000
+#define DDRSS3_PHY_478_DATA 0x00000000
+#define DDRSS3_PHY_479_DATA 0x00000000
+#define DDRSS3_PHY_480_DATA 0x00000000
+#define DDRSS3_PHY_481_DATA 0x00000000
+#define DDRSS3_PHY_482_DATA 0x00000000
+#define DDRSS3_PHY_483_DATA 0x00000000
+#define DDRSS3_PHY_484_DATA 0x00000000
+#define DDRSS3_PHY_485_DATA 0x00000000
+#define DDRSS3_PHY_486_DATA 0x00000000
+#define DDRSS3_PHY_487_DATA 0x00000000
+#define DDRSS3_PHY_488_DATA 0x00000000
+#define DDRSS3_PHY_489_DATA 0x00000000
+#define DDRSS3_PHY_490_DATA 0x00000000
+#define DDRSS3_PHY_491_DATA 0x00000000
+#define DDRSS3_PHY_492_DATA 0x00000000
+#define DDRSS3_PHY_493_DATA 0x00000000
+#define DDRSS3_PHY_494_DATA 0x00000000
+#define DDRSS3_PHY_495_DATA 0x00000000
+#define DDRSS3_PHY_496_DATA 0x00000000
+#define DDRSS3_PHY_497_DATA 0x00000000
+#define DDRSS3_PHY_498_DATA 0x00000000
+#define DDRSS3_PHY_499_DATA 0x00000000
+#define DDRSS3_PHY_500_DATA 0x00000000
+#define DDRSS3_PHY_501_DATA 0x00000000
+#define DDRSS3_PHY_502_DATA 0x00000000
+#define DDRSS3_PHY_503_DATA 0x00000000
+#define DDRSS3_PHY_504_DATA 0x00000000
+#define DDRSS3_PHY_505_DATA 0x00000000
+#define DDRSS3_PHY_506_DATA 0x00000000
+#define DDRSS3_PHY_507_DATA 0x00000000
+#define DDRSS3_PHY_508_DATA 0x00000000
+#define DDRSS3_PHY_509_DATA 0x00000000
+#define DDRSS3_PHY_510_DATA 0x00000000
+#define DDRSS3_PHY_511_DATA 0x00000000
+#define DDRSS3_PHY_512_DATA 0x000004F0
+#define DDRSS3_PHY_513_DATA 0x00000000
+#define DDRSS3_PHY_514_DATA 0x00030200
+#define DDRSS3_PHY_515_DATA 0x00000000
+#define DDRSS3_PHY_516_DATA 0x00000000
+#define DDRSS3_PHY_517_DATA 0x01030000
+#define DDRSS3_PHY_518_DATA 0x00010000
+#define DDRSS3_PHY_519_DATA 0x01030004
+#define DDRSS3_PHY_520_DATA 0x01000000
+#define DDRSS3_PHY_521_DATA 0x00000000
+#define DDRSS3_PHY_522_DATA 0x00000000
+#define DDRSS3_PHY_523_DATA 0x01000001
+#define DDRSS3_PHY_524_DATA 0x00000100
+#define DDRSS3_PHY_525_DATA 0x000800C0
+#define DDRSS3_PHY_526_DATA 0x060100CC
+#define DDRSS3_PHY_527_DATA 0x00030066
+#define DDRSS3_PHY_528_DATA 0x00000000
+#define DDRSS3_PHY_529_DATA 0x00000301
+#define DDRSS3_PHY_530_DATA 0x0000AAAA
+#define DDRSS3_PHY_531_DATA 0x00005555
+#define DDRSS3_PHY_532_DATA 0x0000B5B5
+#define DDRSS3_PHY_533_DATA 0x00004A4A
+#define DDRSS3_PHY_534_DATA 0x00005656
+#define DDRSS3_PHY_535_DATA 0x0000A9A9
+#define DDRSS3_PHY_536_DATA 0x0000A9A9
+#define DDRSS3_PHY_537_DATA 0x0000B5B5
+#define DDRSS3_PHY_538_DATA 0x00000000
+#define DDRSS3_PHY_539_DATA 0x00000000
+#define DDRSS3_PHY_540_DATA 0x2A000000
+#define DDRSS3_PHY_541_DATA 0x00000808
+#define DDRSS3_PHY_542_DATA 0x0F000000
+#define DDRSS3_PHY_543_DATA 0x00000F0F
+#define DDRSS3_PHY_544_DATA 0x10400000
+#define DDRSS3_PHY_545_DATA 0x0C002006
+#define DDRSS3_PHY_546_DATA 0x00000000
+#define DDRSS3_PHY_547_DATA 0x00000000
+#define DDRSS3_PHY_548_DATA 0x55555555
+#define DDRSS3_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_550_DATA 0x55555555
+#define DDRSS3_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_552_DATA 0x00005555
+#define DDRSS3_PHY_553_DATA 0x01000100
+#define DDRSS3_PHY_554_DATA 0x00800180
+#define DDRSS3_PHY_555_DATA 0x00000001
+#define DDRSS3_PHY_556_DATA 0x00000000
+#define DDRSS3_PHY_557_DATA 0x00000000
+#define DDRSS3_PHY_558_DATA 0x00000000
+#define DDRSS3_PHY_559_DATA 0x00000000
+#define DDRSS3_PHY_560_DATA 0x00000000
+#define DDRSS3_PHY_561_DATA 0x00000000
+#define DDRSS3_PHY_562_DATA 0x00000000
+#define DDRSS3_PHY_563_DATA 0x00000000
+#define DDRSS3_PHY_564_DATA 0x00000000
+#define DDRSS3_PHY_565_DATA 0x00000000
+#define DDRSS3_PHY_566_DATA 0x00000000
+#define DDRSS3_PHY_567_DATA 0x00000000
+#define DDRSS3_PHY_568_DATA 0x00000000
+#define DDRSS3_PHY_569_DATA 0x00000000
+#define DDRSS3_PHY_570_DATA 0x00000000
+#define DDRSS3_PHY_571_DATA 0x00000000
+#define DDRSS3_PHY_572_DATA 0x00000000
+#define DDRSS3_PHY_573_DATA 0x00000000
+#define DDRSS3_PHY_574_DATA 0x00000000
+#define DDRSS3_PHY_575_DATA 0x00000000
+#define DDRSS3_PHY_576_DATA 0x00000000
+#define DDRSS3_PHY_577_DATA 0x00000000
+#define DDRSS3_PHY_578_DATA 0x00000104
+#define DDRSS3_PHY_579_DATA 0x00000120
+#define DDRSS3_PHY_580_DATA 0x00000000
+#define DDRSS3_PHY_581_DATA 0x00000000
+#define DDRSS3_PHY_582_DATA 0x00000000
+#define DDRSS3_PHY_583_DATA 0x00000000
+#define DDRSS3_PHY_584_DATA 0x00000000
+#define DDRSS3_PHY_585_DATA 0x00000000
+#define DDRSS3_PHY_586_DATA 0x00000000
+#define DDRSS3_PHY_587_DATA 0x00000001
+#define DDRSS3_PHY_588_DATA 0x07FF0000
+#define DDRSS3_PHY_589_DATA 0x0080081F
+#define DDRSS3_PHY_590_DATA 0x00081020
+#define DDRSS3_PHY_591_DATA 0x04010000
+#define DDRSS3_PHY_592_DATA 0x00000000
+#define DDRSS3_PHY_593_DATA 0x00000000
+#define DDRSS3_PHY_594_DATA 0x00000000
+#define DDRSS3_PHY_595_DATA 0x00000100
+#define DDRSS3_PHY_596_DATA 0x01CC0C01
+#define DDRSS3_PHY_597_DATA 0x1003CC0C
+#define DDRSS3_PHY_598_DATA 0x20000140
+#define DDRSS3_PHY_599_DATA 0x07FF0200
+#define DDRSS3_PHY_600_DATA 0x0000DD01
+#define DDRSS3_PHY_601_DATA 0x10100303
+#define DDRSS3_PHY_602_DATA 0x10101010
+#define DDRSS3_PHY_603_DATA 0x10101010
+#define DDRSS3_PHY_604_DATA 0x00021010
+#define DDRSS3_PHY_605_DATA 0x00100010
+#define DDRSS3_PHY_606_DATA 0x00100010
+#define DDRSS3_PHY_607_DATA 0x00100010
+#define DDRSS3_PHY_608_DATA 0x00100010
+#define DDRSS3_PHY_609_DATA 0x00050010
+#define DDRSS3_PHY_610_DATA 0x51517041
+#define DDRSS3_PHY_611_DATA 0x31C06001
+#define DDRSS3_PHY_612_DATA 0x07AB0340
+#define DDRSS3_PHY_613_DATA 0x00C0C001
+#define DDRSS3_PHY_614_DATA 0x0E0D0001
+#define DDRSS3_PHY_615_DATA 0x10001000
+#define DDRSS3_PHY_616_DATA 0x0C083E42
+#define DDRSS3_PHY_617_DATA 0x0F0C3701
+#define DDRSS3_PHY_618_DATA 0x01000140
+#define DDRSS3_PHY_619_DATA 0x0C000420
+#define DDRSS3_PHY_620_DATA 0x00000198
+#define DDRSS3_PHY_621_DATA 0x0A0000D0
+#define DDRSS3_PHY_622_DATA 0x00030200
+#define DDRSS3_PHY_623_DATA 0x02800000
+#define DDRSS3_PHY_624_DATA 0x80800000
+#define DDRSS3_PHY_625_DATA 0x000E2010
+#define DDRSS3_PHY_626_DATA 0x76543210
+#define DDRSS3_PHY_627_DATA 0x00000008
+#define DDRSS3_PHY_628_DATA 0x02800280
+#define DDRSS3_PHY_629_DATA 0x02800280
+#define DDRSS3_PHY_630_DATA 0x02800280
+#define DDRSS3_PHY_631_DATA 0x02800280
+#define DDRSS3_PHY_632_DATA 0x00000280
+#define DDRSS3_PHY_633_DATA 0x0000A000
+#define DDRSS3_PHY_634_DATA 0x00A000A0
+#define DDRSS3_PHY_635_DATA 0x00A000A0
+#define DDRSS3_PHY_636_DATA 0x00A000A0
+#define DDRSS3_PHY_637_DATA 0x00A000A0
+#define DDRSS3_PHY_638_DATA 0x00A000A0
+#define DDRSS3_PHY_639_DATA 0x00A000A0
+#define DDRSS3_PHY_640_DATA 0x00A000A0
+#define DDRSS3_PHY_641_DATA 0x00A000A0
+#define DDRSS3_PHY_642_DATA 0x01C200A0
+#define DDRSS3_PHY_643_DATA 0x01A00005
+#define DDRSS3_PHY_644_DATA 0x00000000
+#define DDRSS3_PHY_645_DATA 0x00000000
+#define DDRSS3_PHY_646_DATA 0x00080200
+#define DDRSS3_PHY_647_DATA 0x00000000
+#define DDRSS3_PHY_648_DATA 0x20202000
+#define DDRSS3_PHY_649_DATA 0x20202020
+#define DDRSS3_PHY_650_DATA 0xF0F02020
+#define DDRSS3_PHY_651_DATA 0x00000000
+#define DDRSS3_PHY_652_DATA 0x00000000
+#define DDRSS3_PHY_653_DATA 0x00000000
+#define DDRSS3_PHY_654_DATA 0x00000000
+#define DDRSS3_PHY_655_DATA 0x00000000
+#define DDRSS3_PHY_656_DATA 0x00000000
+#define DDRSS3_PHY_657_DATA 0x00000000
+#define DDRSS3_PHY_658_DATA 0x00000000
+#define DDRSS3_PHY_659_DATA 0x00000000
+#define DDRSS3_PHY_660_DATA 0x00000000
+#define DDRSS3_PHY_661_DATA 0x00000000
+#define DDRSS3_PHY_662_DATA 0x00000000
+#define DDRSS3_PHY_663_DATA 0x00000000
+#define DDRSS3_PHY_664_DATA 0x00000000
+#define DDRSS3_PHY_665_DATA 0x00000000
+#define DDRSS3_PHY_666_DATA 0x00000000
+#define DDRSS3_PHY_667_DATA 0x00000000
+#define DDRSS3_PHY_668_DATA 0x00000000
+#define DDRSS3_PHY_669_DATA 0x00000000
+#define DDRSS3_PHY_670_DATA 0x00000000
+#define DDRSS3_PHY_671_DATA 0x00000000
+#define DDRSS3_PHY_672_DATA 0x00000000
+#define DDRSS3_PHY_673_DATA 0x00000000
+#define DDRSS3_PHY_674_DATA 0x00000000
+#define DDRSS3_PHY_675_DATA 0x00000000
+#define DDRSS3_PHY_676_DATA 0x00000000
+#define DDRSS3_PHY_677_DATA 0x00000000
+#define DDRSS3_PHY_678_DATA 0x00000000
+#define DDRSS3_PHY_679_DATA 0x00000000
+#define DDRSS3_PHY_680_DATA 0x00000000
+#define DDRSS3_PHY_681_DATA 0x00000000
+#define DDRSS3_PHY_682_DATA 0x00000000
+#define DDRSS3_PHY_683_DATA 0x00000000
+#define DDRSS3_PHY_684_DATA 0x00000000
+#define DDRSS3_PHY_685_DATA 0x00000000
+#define DDRSS3_PHY_686_DATA 0x00000000
+#define DDRSS3_PHY_687_DATA 0x00000000
+#define DDRSS3_PHY_688_DATA 0x00000000
+#define DDRSS3_PHY_689_DATA 0x00000000
+#define DDRSS3_PHY_690_DATA 0x00000000
+#define DDRSS3_PHY_691_DATA 0x00000000
+#define DDRSS3_PHY_692_DATA 0x00000000
+#define DDRSS3_PHY_693_DATA 0x00000000
+#define DDRSS3_PHY_694_DATA 0x00000000
+#define DDRSS3_PHY_695_DATA 0x00000000
+#define DDRSS3_PHY_696_DATA 0x00000000
+#define DDRSS3_PHY_697_DATA 0x00000000
+#define DDRSS3_PHY_698_DATA 0x00000000
+#define DDRSS3_PHY_699_DATA 0x00000000
+#define DDRSS3_PHY_700_DATA 0x00000000
+#define DDRSS3_PHY_701_DATA 0x00000000
+#define DDRSS3_PHY_702_DATA 0x00000000
+#define DDRSS3_PHY_703_DATA 0x00000000
+#define DDRSS3_PHY_704_DATA 0x00000000
+#define DDRSS3_PHY_705_DATA 0x00000000
+#define DDRSS3_PHY_706_DATA 0x00000000
+#define DDRSS3_PHY_707_DATA 0x00000000
+#define DDRSS3_PHY_708_DATA 0x00000000
+#define DDRSS3_PHY_709_DATA 0x00000000
+#define DDRSS3_PHY_710_DATA 0x00000000
+#define DDRSS3_PHY_711_DATA 0x00000000
+#define DDRSS3_PHY_712_DATA 0x00000000
+#define DDRSS3_PHY_713_DATA 0x00000000
+#define DDRSS3_PHY_714_DATA 0x00000000
+#define DDRSS3_PHY_715_DATA 0x00000000
+#define DDRSS3_PHY_716_DATA 0x00000000
+#define DDRSS3_PHY_717_DATA 0x00000000
+#define DDRSS3_PHY_718_DATA 0x00000000
+#define DDRSS3_PHY_719_DATA 0x00000000
+#define DDRSS3_PHY_720_DATA 0x00000000
+#define DDRSS3_PHY_721_DATA 0x00000000
+#define DDRSS3_PHY_722_DATA 0x00000000
+#define DDRSS3_PHY_723_DATA 0x00000000
+#define DDRSS3_PHY_724_DATA 0x00000000
+#define DDRSS3_PHY_725_DATA 0x00000000
+#define DDRSS3_PHY_726_DATA 0x00000000
+#define DDRSS3_PHY_727_DATA 0x00000000
+#define DDRSS3_PHY_728_DATA 0x00000000
+#define DDRSS3_PHY_729_DATA 0x00000000
+#define DDRSS3_PHY_730_DATA 0x00000000
+#define DDRSS3_PHY_731_DATA 0x00000000
+#define DDRSS3_PHY_732_DATA 0x00000000
+#define DDRSS3_PHY_733_DATA 0x00000000
+#define DDRSS3_PHY_734_DATA 0x00000000
+#define DDRSS3_PHY_735_DATA 0x00000000
+#define DDRSS3_PHY_736_DATA 0x00000000
+#define DDRSS3_PHY_737_DATA 0x00000000
+#define DDRSS3_PHY_738_DATA 0x00000000
+#define DDRSS3_PHY_739_DATA 0x00000000
+#define DDRSS3_PHY_740_DATA 0x00000000
+#define DDRSS3_PHY_741_DATA 0x00000000
+#define DDRSS3_PHY_742_DATA 0x00000000
+#define DDRSS3_PHY_743_DATA 0x00000000
+#define DDRSS3_PHY_744_DATA 0x00000000
+#define DDRSS3_PHY_745_DATA 0x00000000
+#define DDRSS3_PHY_746_DATA 0x00000000
+#define DDRSS3_PHY_747_DATA 0x00000000
+#define DDRSS3_PHY_748_DATA 0x00000000
+#define DDRSS3_PHY_749_DATA 0x00000000
+#define DDRSS3_PHY_750_DATA 0x00000000
+#define DDRSS3_PHY_751_DATA 0x00000000
+#define DDRSS3_PHY_752_DATA 0x00000000
+#define DDRSS3_PHY_753_DATA 0x00000000
+#define DDRSS3_PHY_754_DATA 0x00000000
+#define DDRSS3_PHY_755_DATA 0x00000000
+#define DDRSS3_PHY_756_DATA 0x00000000
+#define DDRSS3_PHY_757_DATA 0x00000000
+#define DDRSS3_PHY_758_DATA 0x00000000
+#define DDRSS3_PHY_759_DATA 0x00000000
+#define DDRSS3_PHY_760_DATA 0x00000000
+#define DDRSS3_PHY_761_DATA 0x00000000
+#define DDRSS3_PHY_762_DATA 0x00000000
+#define DDRSS3_PHY_763_DATA 0x00000000
+#define DDRSS3_PHY_764_DATA 0x00000000
+#define DDRSS3_PHY_765_DATA 0x00000000
+#define DDRSS3_PHY_766_DATA 0x00000000
+#define DDRSS3_PHY_767_DATA 0x00000000
+#define DDRSS3_PHY_768_DATA 0x000004F0
+#define DDRSS3_PHY_769_DATA 0x00000000
+#define DDRSS3_PHY_770_DATA 0x00030200
+#define DDRSS3_PHY_771_DATA 0x00000000
+#define DDRSS3_PHY_772_DATA 0x00000000
+#define DDRSS3_PHY_773_DATA 0x01030000
+#define DDRSS3_PHY_774_DATA 0x00010000
+#define DDRSS3_PHY_775_DATA 0x01030004
+#define DDRSS3_PHY_776_DATA 0x01000000
+#define DDRSS3_PHY_777_DATA 0x00000000
+#define DDRSS3_PHY_778_DATA 0x00000000
+#define DDRSS3_PHY_779_DATA 0x01000001
+#define DDRSS3_PHY_780_DATA 0x00000100
+#define DDRSS3_PHY_781_DATA 0x000800C0
+#define DDRSS3_PHY_782_DATA 0x060100CC
+#define DDRSS3_PHY_783_DATA 0x00030066
+#define DDRSS3_PHY_784_DATA 0x00000000
+#define DDRSS3_PHY_785_DATA 0x00000301
+#define DDRSS3_PHY_786_DATA 0x0000AAAA
+#define DDRSS3_PHY_787_DATA 0x00005555
+#define DDRSS3_PHY_788_DATA 0x0000B5B5
+#define DDRSS3_PHY_789_DATA 0x00004A4A
+#define DDRSS3_PHY_790_DATA 0x00005656
+#define DDRSS3_PHY_791_DATA 0x0000A9A9
+#define DDRSS3_PHY_792_DATA 0x0000A9A9
+#define DDRSS3_PHY_793_DATA 0x0000B5B5
+#define DDRSS3_PHY_794_DATA 0x00000000
+#define DDRSS3_PHY_795_DATA 0x00000000
+#define DDRSS3_PHY_796_DATA 0x2A000000
+#define DDRSS3_PHY_797_DATA 0x00000808
+#define DDRSS3_PHY_798_DATA 0x0F000000
+#define DDRSS3_PHY_799_DATA 0x00000F0F
+#define DDRSS3_PHY_800_DATA 0x10400000
+#define DDRSS3_PHY_801_DATA 0x0C002006
+#define DDRSS3_PHY_802_DATA 0x00000000
+#define DDRSS3_PHY_803_DATA 0x00000000
+#define DDRSS3_PHY_804_DATA 0x55555555
+#define DDRSS3_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_806_DATA 0x55555555
+#define DDRSS3_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_808_DATA 0x00005555
+#define DDRSS3_PHY_809_DATA 0x01000100
+#define DDRSS3_PHY_810_DATA 0x00800180
+#define DDRSS3_PHY_811_DATA 0x00000000
+#define DDRSS3_PHY_812_DATA 0x00000000
+#define DDRSS3_PHY_813_DATA 0x00000000
+#define DDRSS3_PHY_814_DATA 0x00000000
+#define DDRSS3_PHY_815_DATA 0x00000000
+#define DDRSS3_PHY_816_DATA 0x00000000
+#define DDRSS3_PHY_817_DATA 0x00000000
+#define DDRSS3_PHY_818_DATA 0x00000000
+#define DDRSS3_PHY_819_DATA 0x00000000
+#define DDRSS3_PHY_820_DATA 0x00000000
+#define DDRSS3_PHY_821_DATA 0x00000000
+#define DDRSS3_PHY_822_DATA 0x00000000
+#define DDRSS3_PHY_823_DATA 0x00000000
+#define DDRSS3_PHY_824_DATA 0x00000000
+#define DDRSS3_PHY_825_DATA 0x00000000
+#define DDRSS3_PHY_826_DATA 0x00000000
+#define DDRSS3_PHY_827_DATA 0x00000000
+#define DDRSS3_PHY_828_DATA 0x00000000
+#define DDRSS3_PHY_829_DATA 0x00000000
+#define DDRSS3_PHY_830_DATA 0x00000000
+#define DDRSS3_PHY_831_DATA 0x00000000
+#define DDRSS3_PHY_832_DATA 0x00000000
+#define DDRSS3_PHY_833_DATA 0x00000000
+#define DDRSS3_PHY_834_DATA 0x00000104
+#define DDRSS3_PHY_835_DATA 0x00000120
+#define DDRSS3_PHY_836_DATA 0x00000000
+#define DDRSS3_PHY_837_DATA 0x00000000
+#define DDRSS3_PHY_838_DATA 0x00000000
+#define DDRSS3_PHY_839_DATA 0x00000000
+#define DDRSS3_PHY_840_DATA 0x00000000
+#define DDRSS3_PHY_841_DATA 0x00000000
+#define DDRSS3_PHY_842_DATA 0x00000000
+#define DDRSS3_PHY_843_DATA 0x00000001
+#define DDRSS3_PHY_844_DATA 0x07FF0000
+#define DDRSS3_PHY_845_DATA 0x0080081F
+#define DDRSS3_PHY_846_DATA 0x00081020
+#define DDRSS3_PHY_847_DATA 0x04010000
+#define DDRSS3_PHY_848_DATA 0x00000000
+#define DDRSS3_PHY_849_DATA 0x00000000
+#define DDRSS3_PHY_850_DATA 0x00000000
+#define DDRSS3_PHY_851_DATA 0x00000100
+#define DDRSS3_PHY_852_DATA 0x01CC0C01
+#define DDRSS3_PHY_853_DATA 0x1003CC0C
+#define DDRSS3_PHY_854_DATA 0x20000140
+#define DDRSS3_PHY_855_DATA 0x07FF0200
+#define DDRSS3_PHY_856_DATA 0x0000DD01
+#define DDRSS3_PHY_857_DATA 0x10100303
+#define DDRSS3_PHY_858_DATA 0x10101010
+#define DDRSS3_PHY_859_DATA 0x10101010
+#define DDRSS3_PHY_860_DATA 0x00021010
+#define DDRSS3_PHY_861_DATA 0x00100010
+#define DDRSS3_PHY_862_DATA 0x00100010
+#define DDRSS3_PHY_863_DATA 0x00100010
+#define DDRSS3_PHY_864_DATA 0x00100010
+#define DDRSS3_PHY_865_DATA 0x00050010
+#define DDRSS3_PHY_866_DATA 0x51517041
+#define DDRSS3_PHY_867_DATA 0x31C06001
+#define DDRSS3_PHY_868_DATA 0x07AB0340
+#define DDRSS3_PHY_869_DATA 0x00C0C001
+#define DDRSS3_PHY_870_DATA 0x0E0D0001
+#define DDRSS3_PHY_871_DATA 0x10001000
+#define DDRSS3_PHY_872_DATA 0x0C083E42
+#define DDRSS3_PHY_873_DATA 0x0F0C3701
+#define DDRSS3_PHY_874_DATA 0x01000140
+#define DDRSS3_PHY_875_DATA 0x0C000420
+#define DDRSS3_PHY_876_DATA 0x00000198
+#define DDRSS3_PHY_877_DATA 0x0A0000D0
+#define DDRSS3_PHY_878_DATA 0x00030200
+#define DDRSS3_PHY_879_DATA 0x02800000
+#define DDRSS3_PHY_880_DATA 0x80800000
+#define DDRSS3_PHY_881_DATA 0x000E2010
+#define DDRSS3_PHY_882_DATA 0x76543210
+#define DDRSS3_PHY_883_DATA 0x00000008
+#define DDRSS3_PHY_884_DATA 0x02800280
+#define DDRSS3_PHY_885_DATA 0x02800280
+#define DDRSS3_PHY_886_DATA 0x02800280
+#define DDRSS3_PHY_887_DATA 0x02800280
+#define DDRSS3_PHY_888_DATA 0x00000280
+#define DDRSS3_PHY_889_DATA 0x0000A000
+#define DDRSS3_PHY_890_DATA 0x00A000A0
+#define DDRSS3_PHY_891_DATA 0x00A000A0
+#define DDRSS3_PHY_892_DATA 0x00A000A0
+#define DDRSS3_PHY_893_DATA 0x00A000A0
+#define DDRSS3_PHY_894_DATA 0x00A000A0
+#define DDRSS3_PHY_895_DATA 0x00A000A0
+#define DDRSS3_PHY_896_DATA 0x00A000A0
+#define DDRSS3_PHY_897_DATA 0x00A000A0
+#define DDRSS3_PHY_898_DATA 0x01C200A0
+#define DDRSS3_PHY_899_DATA 0x01A00005
+#define DDRSS3_PHY_900_DATA 0x00000000
+#define DDRSS3_PHY_901_DATA 0x00000000
+#define DDRSS3_PHY_902_DATA 0x00080200
+#define DDRSS3_PHY_903_DATA 0x00000000
+#define DDRSS3_PHY_904_DATA 0x20202000
+#define DDRSS3_PHY_905_DATA 0x20202020
+#define DDRSS3_PHY_906_DATA 0xF0F02020
+#define DDRSS3_PHY_907_DATA 0x00000000
+#define DDRSS3_PHY_908_DATA 0x00000000
+#define DDRSS3_PHY_909_DATA 0x00000000
+#define DDRSS3_PHY_910_DATA 0x00000000
+#define DDRSS3_PHY_911_DATA 0x00000000
+#define DDRSS3_PHY_912_DATA 0x00000000
+#define DDRSS3_PHY_913_DATA 0x00000000
+#define DDRSS3_PHY_914_DATA 0x00000000
+#define DDRSS3_PHY_915_DATA 0x00000000
+#define DDRSS3_PHY_916_DATA 0x00000000
+#define DDRSS3_PHY_917_DATA 0x00000000
+#define DDRSS3_PHY_918_DATA 0x00000000
+#define DDRSS3_PHY_919_DATA 0x00000000
+#define DDRSS3_PHY_920_DATA 0x00000000
+#define DDRSS3_PHY_921_DATA 0x00000000
+#define DDRSS3_PHY_922_DATA 0x00000000
+#define DDRSS3_PHY_923_DATA 0x00000000
+#define DDRSS3_PHY_924_DATA 0x00000000
+#define DDRSS3_PHY_925_DATA 0x00000000
+#define DDRSS3_PHY_926_DATA 0x00000000
+#define DDRSS3_PHY_927_DATA 0x00000000
+#define DDRSS3_PHY_928_DATA 0x00000000
+#define DDRSS3_PHY_929_DATA 0x00000000
+#define DDRSS3_PHY_930_DATA 0x00000000
+#define DDRSS3_PHY_931_DATA 0x00000000
+#define DDRSS3_PHY_932_DATA 0x00000000
+#define DDRSS3_PHY_933_DATA 0x00000000
+#define DDRSS3_PHY_934_DATA 0x00000000
+#define DDRSS3_PHY_935_DATA 0x00000000
+#define DDRSS3_PHY_936_DATA 0x00000000
+#define DDRSS3_PHY_937_DATA 0x00000000
+#define DDRSS3_PHY_938_DATA 0x00000000
+#define DDRSS3_PHY_939_DATA 0x00000000
+#define DDRSS3_PHY_940_DATA 0x00000000
+#define DDRSS3_PHY_941_DATA 0x00000000
+#define DDRSS3_PHY_942_DATA 0x00000000
+#define DDRSS3_PHY_943_DATA 0x00000000
+#define DDRSS3_PHY_944_DATA 0x00000000
+#define DDRSS3_PHY_945_DATA 0x00000000
+#define DDRSS3_PHY_946_DATA 0x00000000
+#define DDRSS3_PHY_947_DATA 0x00000000
+#define DDRSS3_PHY_948_DATA 0x00000000
+#define DDRSS3_PHY_949_DATA 0x00000000
+#define DDRSS3_PHY_950_DATA 0x00000000
+#define DDRSS3_PHY_951_DATA 0x00000000
+#define DDRSS3_PHY_952_DATA 0x00000000
+#define DDRSS3_PHY_953_DATA 0x00000000
+#define DDRSS3_PHY_954_DATA 0x00000000
+#define DDRSS3_PHY_955_DATA 0x00000000
+#define DDRSS3_PHY_956_DATA 0x00000000
+#define DDRSS3_PHY_957_DATA 0x00000000
+#define DDRSS3_PHY_958_DATA 0x00000000
+#define DDRSS3_PHY_959_DATA 0x00000000
+#define DDRSS3_PHY_960_DATA 0x00000000
+#define DDRSS3_PHY_961_DATA 0x00000000
+#define DDRSS3_PHY_962_DATA 0x00000000
+#define DDRSS3_PHY_963_DATA 0x00000000
+#define DDRSS3_PHY_964_DATA 0x00000000
+#define DDRSS3_PHY_965_DATA 0x00000000
+#define DDRSS3_PHY_966_DATA 0x00000000
+#define DDRSS3_PHY_967_DATA 0x00000000
+#define DDRSS3_PHY_968_DATA 0x00000000
+#define DDRSS3_PHY_969_DATA 0x00000000
+#define DDRSS3_PHY_970_DATA 0x00000000
+#define DDRSS3_PHY_971_DATA 0x00000000
+#define DDRSS3_PHY_972_DATA 0x00000000
+#define DDRSS3_PHY_973_DATA 0x00000000
+#define DDRSS3_PHY_974_DATA 0x00000000
+#define DDRSS3_PHY_975_DATA 0x00000000
+#define DDRSS3_PHY_976_DATA 0x00000000
+#define DDRSS3_PHY_977_DATA 0x00000000
+#define DDRSS3_PHY_978_DATA 0x00000000
+#define DDRSS3_PHY_979_DATA 0x00000000
+#define DDRSS3_PHY_980_DATA 0x00000000
+#define DDRSS3_PHY_981_DATA 0x00000000
+#define DDRSS3_PHY_982_DATA 0x00000000
+#define DDRSS3_PHY_983_DATA 0x00000000
+#define DDRSS3_PHY_984_DATA 0x00000000
+#define DDRSS3_PHY_985_DATA 0x00000000
+#define DDRSS3_PHY_986_DATA 0x00000000
+#define DDRSS3_PHY_987_DATA 0x00000000
+#define DDRSS3_PHY_988_DATA 0x00000000
+#define DDRSS3_PHY_989_DATA 0x00000000
+#define DDRSS3_PHY_990_DATA 0x00000000
+#define DDRSS3_PHY_991_DATA 0x00000000
+#define DDRSS3_PHY_992_DATA 0x00000000
+#define DDRSS3_PHY_993_DATA 0x00000000
+#define DDRSS3_PHY_994_DATA 0x00000000
+#define DDRSS3_PHY_995_DATA 0x00000000
+#define DDRSS3_PHY_996_DATA 0x00000000
+#define DDRSS3_PHY_997_DATA 0x00000000
+#define DDRSS3_PHY_998_DATA 0x00000000
+#define DDRSS3_PHY_999_DATA 0x00000000
+#define DDRSS3_PHY_1000_DATA 0x00000000
+#define DDRSS3_PHY_1001_DATA 0x00000000
+#define DDRSS3_PHY_1002_DATA 0x00000000
+#define DDRSS3_PHY_1003_DATA 0x00000000
+#define DDRSS3_PHY_1004_DATA 0x00000000
+#define DDRSS3_PHY_1005_DATA 0x00000000
+#define DDRSS3_PHY_1006_DATA 0x00000000
+#define DDRSS3_PHY_1007_DATA 0x00000000
+#define DDRSS3_PHY_1008_DATA 0x00000000
+#define DDRSS3_PHY_1009_DATA 0x00000000
+#define DDRSS3_PHY_1010_DATA 0x00000000
+#define DDRSS3_PHY_1011_DATA 0x00000000
+#define DDRSS3_PHY_1012_DATA 0x00000000
+#define DDRSS3_PHY_1013_DATA 0x00000000
+#define DDRSS3_PHY_1014_DATA 0x00000000
+#define DDRSS3_PHY_1015_DATA 0x00000000
+#define DDRSS3_PHY_1016_DATA 0x00000000
+#define DDRSS3_PHY_1017_DATA 0x00000000
+#define DDRSS3_PHY_1018_DATA 0x00000000
+#define DDRSS3_PHY_1019_DATA 0x00000000
+#define DDRSS3_PHY_1020_DATA 0x00000000
+#define DDRSS3_PHY_1021_DATA 0x00000000
+#define DDRSS3_PHY_1022_DATA 0x00000000
+#define DDRSS3_PHY_1023_DATA 0x00000000
+#define DDRSS3_PHY_1024_DATA 0x00000000
+#define DDRSS3_PHY_1025_DATA 0x00000000
+#define DDRSS3_PHY_1026_DATA 0x00000000
+#define DDRSS3_PHY_1027_DATA 0x00000000
+#define DDRSS3_PHY_1028_DATA 0x00000000
+#define DDRSS3_PHY_1029_DATA 0x00000100
+#define DDRSS3_PHY_1030_DATA 0x00000200
+#define DDRSS3_PHY_1031_DATA 0x00000000
+#define DDRSS3_PHY_1032_DATA 0x00000000
+#define DDRSS3_PHY_1033_DATA 0x00000000
+#define DDRSS3_PHY_1034_DATA 0x00000000
+#define DDRSS3_PHY_1035_DATA 0x00400000
+#define DDRSS3_PHY_1036_DATA 0x00000080
+#define DDRSS3_PHY_1037_DATA 0x00DCBA98
+#define DDRSS3_PHY_1038_DATA 0x03000000
+#define DDRSS3_PHY_1039_DATA 0x00200000
+#define DDRSS3_PHY_1040_DATA 0x00000000
+#define DDRSS3_PHY_1041_DATA 0x00000000
+#define DDRSS3_PHY_1042_DATA 0x00000000
+#define DDRSS3_PHY_1043_DATA 0x00000000
+#define DDRSS3_PHY_1044_DATA 0x00000000
+#define DDRSS3_PHY_1045_DATA 0x0000002A
+#define DDRSS3_PHY_1046_DATA 0x00000015
+#define DDRSS3_PHY_1047_DATA 0x00000015
+#define DDRSS3_PHY_1048_DATA 0x0000002A
+#define DDRSS3_PHY_1049_DATA 0x00000033
+#define DDRSS3_PHY_1050_DATA 0x0000000C
+#define DDRSS3_PHY_1051_DATA 0x0000000C
+#define DDRSS3_PHY_1052_DATA 0x00000033
+#define DDRSS3_PHY_1053_DATA 0x00543210
+#define DDRSS3_PHY_1054_DATA 0x003F0000
+#define DDRSS3_PHY_1055_DATA 0x000F013F
+#define DDRSS3_PHY_1056_DATA 0x20202003
+#define DDRSS3_PHY_1057_DATA 0x00202020
+#define DDRSS3_PHY_1058_DATA 0x20008008
+#define DDRSS3_PHY_1059_DATA 0x00000810
+#define DDRSS3_PHY_1060_DATA 0x00000F00
+#define DDRSS3_PHY_1061_DATA 0x00000000
+#define DDRSS3_PHY_1062_DATA 0x00000000
+#define DDRSS3_PHY_1063_DATA 0x00000000
+#define DDRSS3_PHY_1064_DATA 0x000305CC
+#define DDRSS3_PHY_1065_DATA 0x00030000
+#define DDRSS3_PHY_1066_DATA 0x00000300
+#define DDRSS3_PHY_1067_DATA 0x00000300
+#define DDRSS3_PHY_1068_DATA 0x00000300
+#define DDRSS3_PHY_1069_DATA 0x00000300
+#define DDRSS3_PHY_1070_DATA 0x00000300
+#define DDRSS3_PHY_1071_DATA 0x42080010
+#define DDRSS3_PHY_1072_DATA 0x0000803E
+#define DDRSS3_PHY_1073_DATA 0x00000001
+#define DDRSS3_PHY_1074_DATA 0x01000102
+#define DDRSS3_PHY_1075_DATA 0x00008000
+#define DDRSS3_PHY_1076_DATA 0x00000000
+#define DDRSS3_PHY_1077_DATA 0x00000000
+#define DDRSS3_PHY_1078_DATA 0x00000000
+#define DDRSS3_PHY_1079_DATA 0x00000000
+#define DDRSS3_PHY_1080_DATA 0x00000000
+#define DDRSS3_PHY_1081_DATA 0x00000000
+#define DDRSS3_PHY_1082_DATA 0x00000000
+#define DDRSS3_PHY_1083_DATA 0x00000000
+#define DDRSS3_PHY_1084_DATA 0x00000000
+#define DDRSS3_PHY_1085_DATA 0x00000000
+#define DDRSS3_PHY_1086_DATA 0x00000000
+#define DDRSS3_PHY_1087_DATA 0x00000000
+#define DDRSS3_PHY_1088_DATA 0x00000000
+#define DDRSS3_PHY_1089_DATA 0x00000000
+#define DDRSS3_PHY_1090_DATA 0x00000000
+#define DDRSS3_PHY_1091_DATA 0x00000000
+#define DDRSS3_PHY_1092_DATA 0x00000000
+#define DDRSS3_PHY_1093_DATA 0x00000000
+#define DDRSS3_PHY_1094_DATA 0x00000000
+#define DDRSS3_PHY_1095_DATA 0x00000000
+#define DDRSS3_PHY_1096_DATA 0x00000000
+#define DDRSS3_PHY_1097_DATA 0x00000000
+#define DDRSS3_PHY_1098_DATA 0x00000000
+#define DDRSS3_PHY_1099_DATA 0x00000000
+#define DDRSS3_PHY_1100_DATA 0x00000000
+#define DDRSS3_PHY_1101_DATA 0x00000000
+#define DDRSS3_PHY_1102_DATA 0x00000000
+#define DDRSS3_PHY_1103_DATA 0x00000000
+#define DDRSS3_PHY_1104_DATA 0x00000000
+#define DDRSS3_PHY_1105_DATA 0x00000000
+#define DDRSS3_PHY_1106_DATA 0x00000000
+#define DDRSS3_PHY_1107_DATA 0x00000000
+#define DDRSS3_PHY_1108_DATA 0x00000000
+#define DDRSS3_PHY_1109_DATA 0x00000000
+#define DDRSS3_PHY_1110_DATA 0x00000000
+#define DDRSS3_PHY_1111_DATA 0x00000000
+#define DDRSS3_PHY_1112_DATA 0x00000000
+#define DDRSS3_PHY_1113_DATA 0x00000000
+#define DDRSS3_PHY_1114_DATA 0x00000000
+#define DDRSS3_PHY_1115_DATA 0x00000000
+#define DDRSS3_PHY_1116_DATA 0x00000000
+#define DDRSS3_PHY_1117_DATA 0x00000000
+#define DDRSS3_PHY_1118_DATA 0x00000000
+#define DDRSS3_PHY_1119_DATA 0x00000000
+#define DDRSS3_PHY_1120_DATA 0x00000000
+#define DDRSS3_PHY_1121_DATA 0x00000000
+#define DDRSS3_PHY_1122_DATA 0x00000000
+#define DDRSS3_PHY_1123_DATA 0x00000000
+#define DDRSS3_PHY_1124_DATA 0x00000000
+#define DDRSS3_PHY_1125_DATA 0x00000000
+#define DDRSS3_PHY_1126_DATA 0x00000000
+#define DDRSS3_PHY_1127_DATA 0x00000000
+#define DDRSS3_PHY_1128_DATA 0x00000000
+#define DDRSS3_PHY_1129_DATA 0x00000000
+#define DDRSS3_PHY_1130_DATA 0x00000000
+#define DDRSS3_PHY_1131_DATA 0x00000000
+#define DDRSS3_PHY_1132_DATA 0x00000000
+#define DDRSS3_PHY_1133_DATA 0x00000000
+#define DDRSS3_PHY_1134_DATA 0x00000000
+#define DDRSS3_PHY_1135_DATA 0x00000000
+#define DDRSS3_PHY_1136_DATA 0x00000000
+#define DDRSS3_PHY_1137_DATA 0x00000000
+#define DDRSS3_PHY_1138_DATA 0x00000000
+#define DDRSS3_PHY_1139_DATA 0x00000000
+#define DDRSS3_PHY_1140_DATA 0x00000000
+#define DDRSS3_PHY_1141_DATA 0x00000000
+#define DDRSS3_PHY_1142_DATA 0x00000000
+#define DDRSS3_PHY_1143_DATA 0x00000000
+#define DDRSS3_PHY_1144_DATA 0x00000000
+#define DDRSS3_PHY_1145_DATA 0x00000000
+#define DDRSS3_PHY_1146_DATA 0x00000000
+#define DDRSS3_PHY_1147_DATA 0x00000000
+#define DDRSS3_PHY_1148_DATA 0x00000000
+#define DDRSS3_PHY_1149_DATA 0x00000000
+#define DDRSS3_PHY_1150_DATA 0x00000000
+#define DDRSS3_PHY_1151_DATA 0x00000000
+#define DDRSS3_PHY_1152_DATA 0x00000000
+#define DDRSS3_PHY_1153_DATA 0x00000000
+#define DDRSS3_PHY_1154_DATA 0x00000000
+#define DDRSS3_PHY_1155_DATA 0x00000000
+#define DDRSS3_PHY_1156_DATA 0x00000000
+#define DDRSS3_PHY_1157_DATA 0x00000000
+#define DDRSS3_PHY_1158_DATA 0x00000000
+#define DDRSS3_PHY_1159_DATA 0x00000000
+#define DDRSS3_PHY_1160_DATA 0x00000000
+#define DDRSS3_PHY_1161_DATA 0x00000000
+#define DDRSS3_PHY_1162_DATA 0x00000000
+#define DDRSS3_PHY_1163_DATA 0x00000000
+#define DDRSS3_PHY_1164_DATA 0x00000000
+#define DDRSS3_PHY_1165_DATA 0x00000000
+#define DDRSS3_PHY_1166_DATA 0x00000000
+#define DDRSS3_PHY_1167_DATA 0x00000000
+#define DDRSS3_PHY_1168_DATA 0x00000000
+#define DDRSS3_PHY_1169_DATA 0x00000000
+#define DDRSS3_PHY_1170_DATA 0x00000000
+#define DDRSS3_PHY_1171_DATA 0x00000000
+#define DDRSS3_PHY_1172_DATA 0x00000000
+#define DDRSS3_PHY_1173_DATA 0x00000000
+#define DDRSS3_PHY_1174_DATA 0x00000000
+#define DDRSS3_PHY_1175_DATA 0x00000000
+#define DDRSS3_PHY_1176_DATA 0x00000000
+#define DDRSS3_PHY_1177_DATA 0x00000000
+#define DDRSS3_PHY_1178_DATA 0x00000000
+#define DDRSS3_PHY_1179_DATA 0x00000000
+#define DDRSS3_PHY_1180_DATA 0x00000000
+#define DDRSS3_PHY_1181_DATA 0x00000000
+#define DDRSS3_PHY_1182_DATA 0x00000000
+#define DDRSS3_PHY_1183_DATA 0x00000000
+#define DDRSS3_PHY_1184_DATA 0x00000000
+#define DDRSS3_PHY_1185_DATA 0x00000000
+#define DDRSS3_PHY_1186_DATA 0x00000000
+#define DDRSS3_PHY_1187_DATA 0x00000000
+#define DDRSS3_PHY_1188_DATA 0x00000000
+#define DDRSS3_PHY_1189_DATA 0x00000000
+#define DDRSS3_PHY_1190_DATA 0x00000000
+#define DDRSS3_PHY_1191_DATA 0x00000000
+#define DDRSS3_PHY_1192_DATA 0x00000000
+#define DDRSS3_PHY_1193_DATA 0x00000000
+#define DDRSS3_PHY_1194_DATA 0x00000000
+#define DDRSS3_PHY_1195_DATA 0x00000000
+#define DDRSS3_PHY_1196_DATA 0x00000000
+#define DDRSS3_PHY_1197_DATA 0x00000000
+#define DDRSS3_PHY_1198_DATA 0x00000000
+#define DDRSS3_PHY_1199_DATA 0x00000000
+#define DDRSS3_PHY_1200_DATA 0x00000000
+#define DDRSS3_PHY_1201_DATA 0x00000000
+#define DDRSS3_PHY_1202_DATA 0x00000000
+#define DDRSS3_PHY_1203_DATA 0x00000000
+#define DDRSS3_PHY_1204_DATA 0x00000000
+#define DDRSS3_PHY_1205_DATA 0x00000000
+#define DDRSS3_PHY_1206_DATA 0x00000000
+#define DDRSS3_PHY_1207_DATA 0x00000000
+#define DDRSS3_PHY_1208_DATA 0x00000000
+#define DDRSS3_PHY_1209_DATA 0x00000000
+#define DDRSS3_PHY_1210_DATA 0x00000000
+#define DDRSS3_PHY_1211_DATA 0x00000000
+#define DDRSS3_PHY_1212_DATA 0x00000000
+#define DDRSS3_PHY_1213_DATA 0x00000000
+#define DDRSS3_PHY_1214_DATA 0x00000000
+#define DDRSS3_PHY_1215_DATA 0x00000000
+#define DDRSS3_PHY_1216_DATA 0x00000000
+#define DDRSS3_PHY_1217_DATA 0x00000000
+#define DDRSS3_PHY_1218_DATA 0x00000000
+#define DDRSS3_PHY_1219_DATA 0x00000000
+#define DDRSS3_PHY_1220_DATA 0x00000000
+#define DDRSS3_PHY_1221_DATA 0x00000000
+#define DDRSS3_PHY_1222_DATA 0x00000000
+#define DDRSS3_PHY_1223_DATA 0x00000000
+#define DDRSS3_PHY_1224_DATA 0x00000000
+#define DDRSS3_PHY_1225_DATA 0x00000000
+#define DDRSS3_PHY_1226_DATA 0x00000000
+#define DDRSS3_PHY_1227_DATA 0x00000000
+#define DDRSS3_PHY_1228_DATA 0x00000000
+#define DDRSS3_PHY_1229_DATA 0x00000000
+#define DDRSS3_PHY_1230_DATA 0x00000000
+#define DDRSS3_PHY_1231_DATA 0x00000000
+#define DDRSS3_PHY_1232_DATA 0x00000000
+#define DDRSS3_PHY_1233_DATA 0x00000000
+#define DDRSS3_PHY_1234_DATA 0x00000000
+#define DDRSS3_PHY_1235_DATA 0x00000000
+#define DDRSS3_PHY_1236_DATA 0x00000000
+#define DDRSS3_PHY_1237_DATA 0x00000000
+#define DDRSS3_PHY_1238_DATA 0x00000000
+#define DDRSS3_PHY_1239_DATA 0x00000000
+#define DDRSS3_PHY_1240_DATA 0x00000000
+#define DDRSS3_PHY_1241_DATA 0x00000000
+#define DDRSS3_PHY_1242_DATA 0x00000000
+#define DDRSS3_PHY_1243_DATA 0x00000000
+#define DDRSS3_PHY_1244_DATA 0x00000000
+#define DDRSS3_PHY_1245_DATA 0x00000000
+#define DDRSS3_PHY_1246_DATA 0x00000000
+#define DDRSS3_PHY_1247_DATA 0x00000000
+#define DDRSS3_PHY_1248_DATA 0x00000000
+#define DDRSS3_PHY_1249_DATA 0x00000000
+#define DDRSS3_PHY_1250_DATA 0x00000000
+#define DDRSS3_PHY_1251_DATA 0x00000000
+#define DDRSS3_PHY_1252_DATA 0x00000000
+#define DDRSS3_PHY_1253_DATA 0x00000000
+#define DDRSS3_PHY_1254_DATA 0x00000000
+#define DDRSS3_PHY_1255_DATA 0x00000000
+#define DDRSS3_PHY_1256_DATA 0x00000000
+#define DDRSS3_PHY_1257_DATA 0x00000000
+#define DDRSS3_PHY_1258_DATA 0x00000000
+#define DDRSS3_PHY_1259_DATA 0x00000000
+#define DDRSS3_PHY_1260_DATA 0x00000000
+#define DDRSS3_PHY_1261_DATA 0x00000000
+#define DDRSS3_PHY_1262_DATA 0x00000000
+#define DDRSS3_PHY_1263_DATA 0x00000000
+#define DDRSS3_PHY_1264_DATA 0x00000000
+#define DDRSS3_PHY_1265_DATA 0x00000000
+#define DDRSS3_PHY_1266_DATA 0x00000000
+#define DDRSS3_PHY_1267_DATA 0x00000000
+#define DDRSS3_PHY_1268_DATA 0x00000000
+#define DDRSS3_PHY_1269_DATA 0x00000000
+#define DDRSS3_PHY_1270_DATA 0x00000000
+#define DDRSS3_PHY_1271_DATA 0x00000000
+#define DDRSS3_PHY_1272_DATA 0x00000000
+#define DDRSS3_PHY_1273_DATA 0x00000000
+#define DDRSS3_PHY_1274_DATA 0x00000000
+#define DDRSS3_PHY_1275_DATA 0x00000000
+#define DDRSS3_PHY_1276_DATA 0x00000000
+#define DDRSS3_PHY_1277_DATA 0x00000000
+#define DDRSS3_PHY_1278_DATA 0x00000000
+#define DDRSS3_PHY_1279_DATA 0x00000000
+#define DDRSS3_PHY_1280_DATA 0x00000000
+#define DDRSS3_PHY_1281_DATA 0x00010100
+#define DDRSS3_PHY_1282_DATA 0x00000000
+#define DDRSS3_PHY_1283_DATA 0x00000000
+#define DDRSS3_PHY_1284_DATA 0x00050000
+#define DDRSS3_PHY_1285_DATA 0x04000000
+#define DDRSS3_PHY_1286_DATA 0x00000055
+#define DDRSS3_PHY_1287_DATA 0x00000000
+#define DDRSS3_PHY_1288_DATA 0x00000000
+#define DDRSS3_PHY_1289_DATA 0x00000000
+#define DDRSS3_PHY_1290_DATA 0x00000000
+#define DDRSS3_PHY_1291_DATA 0x00002001
+#define DDRSS3_PHY_1292_DATA 0x0000400F
+#define DDRSS3_PHY_1293_DATA 0x50020028
+#define DDRSS3_PHY_1294_DATA 0x01010000
+#define DDRSS3_PHY_1295_DATA 0x80080001
+#define DDRSS3_PHY_1296_DATA 0x10200000
+#define DDRSS3_PHY_1297_DATA 0x00000008
+#define DDRSS3_PHY_1298_DATA 0x00000000
+#define DDRSS3_PHY_1299_DATA 0x01090E00
+#define DDRSS3_PHY_1300_DATA 0x00040101
+#define DDRSS3_PHY_1301_DATA 0x0000010F
+#define DDRSS3_PHY_1302_DATA 0x00000000
+#define DDRSS3_PHY_1303_DATA 0x0000FFFF
+#define DDRSS3_PHY_1304_DATA 0x00000000
+#define DDRSS3_PHY_1305_DATA 0x01010000
+#define DDRSS3_PHY_1306_DATA 0x01080402
+#define DDRSS3_PHY_1307_DATA 0x01200F02
+#define DDRSS3_PHY_1308_DATA 0x00194280
+#define DDRSS3_PHY_1309_DATA 0x00000004
+#define DDRSS3_PHY_1310_DATA 0x00042000
+#define DDRSS3_PHY_1311_DATA 0x00000000
+#define DDRSS3_PHY_1312_DATA 0x00000000
+#define DDRSS3_PHY_1313_DATA 0x00000000
+#define DDRSS3_PHY_1314_DATA 0x00000000
+#define DDRSS3_PHY_1315_DATA 0x00000000
+#define DDRSS3_PHY_1316_DATA 0x00000000
+#define DDRSS3_PHY_1317_DATA 0x01000000
+#define DDRSS3_PHY_1318_DATA 0x00000705
+#define DDRSS3_PHY_1319_DATA 0x00000054
+#define DDRSS3_PHY_1320_DATA 0x00030820
+#define DDRSS3_PHY_1321_DATA 0x00010820
+#define DDRSS3_PHY_1322_DATA 0x00010820
+#define DDRSS3_PHY_1323_DATA 0x00010820
+#define DDRSS3_PHY_1324_DATA 0x00010820
+#define DDRSS3_PHY_1325_DATA 0x00010820
+#define DDRSS3_PHY_1326_DATA 0x00010820
+#define DDRSS3_PHY_1327_DATA 0x00010820
+#define DDRSS3_PHY_1328_DATA 0x00010820
+#define DDRSS3_PHY_1329_DATA 0x00000000
+#define DDRSS3_PHY_1330_DATA 0x00000074
+#define DDRSS3_PHY_1331_DATA 0x00000400
+#define DDRSS3_PHY_1332_DATA 0x00000108
+#define DDRSS3_PHY_1333_DATA 0x00000000
+#define DDRSS3_PHY_1334_DATA 0x00000000
+#define DDRSS3_PHY_1335_DATA 0x00000000
+#define DDRSS3_PHY_1336_DATA 0x00000000
+#define DDRSS3_PHY_1337_DATA 0x00000000
+#define DDRSS3_PHY_1338_DATA 0x03000000
+#define DDRSS3_PHY_1339_DATA 0x00000000
+#define DDRSS3_PHY_1340_DATA 0x00000000
+#define DDRSS3_PHY_1341_DATA 0x00000000
+#define DDRSS3_PHY_1342_DATA 0x04102006
+#define DDRSS3_PHY_1343_DATA 0x00041020
+#define DDRSS3_PHY_1344_DATA 0x01C98C98
+#define DDRSS3_PHY_1345_DATA 0x3F400000
+#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS3_PHY_1347_DATA 0x0000001F
+#define DDRSS3_PHY_1348_DATA 0x00000000
+#define DDRSS3_PHY_1349_DATA 0x00000000
+#define DDRSS3_PHY_1350_DATA 0x00000000
+#define DDRSS3_PHY_1351_DATA 0x00010000
+#define DDRSS3_PHY_1352_DATA 0x00000000
+#define DDRSS3_PHY_1353_DATA 0x00000000
+#define DDRSS3_PHY_1354_DATA 0x00000000
+#define DDRSS3_PHY_1355_DATA 0x00000000
+#define DDRSS3_PHY_1356_DATA 0x76543210
+#define DDRSS3_PHY_1357_DATA 0x00010198
+#define DDRSS3_PHY_1358_DATA 0x00000000
+#define DDRSS3_PHY_1359_DATA 0x00000000
+#define DDRSS3_PHY_1360_DATA 0x00000000
+#define DDRSS3_PHY_1361_DATA 0x00040700
+#define DDRSS3_PHY_1362_DATA 0x00000000
+#define DDRSS3_PHY_1363_DATA 0x00000000
+#define DDRSS3_PHY_1364_DATA 0x00000000
+#define DDRSS3_PHY_1365_DATA 0x00000000
+#define DDRSS3_PHY_1366_DATA 0x00000000
+#define DDRSS3_PHY_1367_DATA 0x00000002
+#define DDRSS3_PHY_1368_DATA 0x00000000
+#define DDRSS3_PHY_1369_DATA 0x00000000
+#define DDRSS3_PHY_1370_DATA 0x00000000
+#define DDRSS3_PHY_1371_DATA 0x00000000
+#define DDRSS3_PHY_1372_DATA 0x00000000
+#define DDRSS3_PHY_1373_DATA 0x00000000
+#define DDRSS3_PHY_1374_DATA 0x00080000
+#define DDRSS3_PHY_1375_DATA 0x000007FF
+#define DDRSS3_PHY_1376_DATA 0x00000000
+#define DDRSS3_PHY_1377_DATA 0x00000000
+#define DDRSS3_PHY_1378_DATA 0x00000000
+#define DDRSS3_PHY_1379_DATA 0x00000000
+#define DDRSS3_PHY_1380_DATA 0x00000000
+#define DDRSS3_PHY_1381_DATA 0x00000000
+#define DDRSS3_PHY_1382_DATA 0x000FFFFF
+#define DDRSS3_PHY_1383_DATA 0x000FFFFF
+#define DDRSS3_PHY_1384_DATA 0x0000FFFF
+#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS3_PHY_1386_DATA 0x030FFFFF
+#define DDRSS3_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS3_PHY_1388_DATA 0x0000FFFF
+#define DDRSS3_PHY_1389_DATA 0x00000000
+#define DDRSS3_PHY_1390_DATA 0x00000000
+#define DDRSS3_PHY_1391_DATA 0x00000000
+#define DDRSS3_PHY_1392_DATA 0x00000000
+#define DDRSS3_PHY_1393_DATA 0x0001F7C0
+#define DDRSS3_PHY_1394_DATA 0x00000003
+#define DDRSS3_PHY_1395_DATA 0x00000000
+#define DDRSS3_PHY_1396_DATA 0x00001142
+#define DDRSS3_PHY_1397_DATA 0x010207AB
+#define DDRSS3_PHY_1398_DATA 0x01000080
+#define DDRSS3_PHY_1399_DATA 0x03900390
+#define DDRSS3_PHY_1400_DATA 0x03900390
+#define DDRSS3_PHY_1401_DATA 0x00000390
+#define DDRSS3_PHY_1402_DATA 0x00000390
+#define DDRSS3_PHY_1403_DATA 0x00000390
+#define DDRSS3_PHY_1404_DATA 0x00000390
+#define DDRSS3_PHY_1405_DATA 0x00000005
+#define DDRSS3_PHY_1406_DATA 0x01813FCC
+#define DDRSS3_PHY_1407_DATA 0x000000CC
+#define DDRSS3_PHY_1408_DATA 0x0C000DFF
+#define DDRSS3_PHY_1409_DATA 0x30000DFF
+#define DDRSS3_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1411_DATA 0x000100F0
+#define DDRSS3_PHY_1412_DATA 0x780DFFCC
+#define DDRSS3_PHY_1413_DATA 0x00007E31
+#define DDRSS3_PHY_1414_DATA 0x000CBF11
+#define DDRSS3_PHY_1415_DATA 0x01990010
+#define DDRSS3_PHY_1416_DATA 0x000CBF11
+#define DDRSS3_PHY_1417_DATA 0x01990010
+#define DDRSS3_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1419_DATA 0x00EF00F0
+#define DDRSS3_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1421_DATA 0x01FF00F0
+#define DDRSS3_PHY_1422_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
new file mode 100644
index 00000000000..ede5d6e58f5
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SPL_BOARD_DTB "spl/dts/ti/k3-j742s2-evm.dtb"
+#define BOARD_DESCRIPTION "k3-j742s2-evm"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for J742S2 board"
+
+#include "k3-j784s4-binman.dtsi"
+
+#if !defined(CONFIG_ARM64)
+
+&binman {
+	tiboot3-j742s2-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j742s2-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+
+	tiboot3-j742s2-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j742s2-hs-evm.bin";
+	};
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-cert.bin";
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
diff --git a/arch/arm/dts/k3-j742s2-r5-evm.dts b/arch/arm/dts/k3-j742s2-r5-evm.dts
new file mode 100644
index 00000000000..6dde13c4e75
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-r5-evm.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+/dts-v1/;
+
+#include "k3-j742s2-evm.dts"
+#include "k3-j742s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-j742s2-ddr.dtsi"
+#include "k3-j742s2-evm-u-boot.dtsi"
+#include "k3-j784s4-r5.dtsi"
+
+&tps659413 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 85bdd1f5b6c..0553825b383 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -5,16 +5,15 @@
 
 #include "k3-binman.dtsi"
 
-#ifdef CONFIG_TARGET_J784S4_R5_EVM
+#if defined(CONFIG_CPU_V7R)
 
 &rcfg_yaml_tifs {
 	config = "tifs-rm-cfg.yaml";
 };
 
 &binman {
-	tiboot3-j784s4-hs-evm.bin {
-		filename = "tiboot3-j784s4-hs-evm.bin";
-
+	tiboot3_j784s4_hs: template-9 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
 				<&combined_dm_cfg>, <&sysfw_inner_cert>;
@@ -39,7 +38,6 @@
 		};
 
 		ti_fs_enc: ti-fs-enc.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -50,7 +48,6 @@
 		};
 
 		sysfw_inner_cert: sysfw-inner-cert {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -59,13 +56,13 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
+		};
 	};
 };
 
 &binman {
-	tiboot3-j784s4-hs-fs-evm.bin {
-		filename = "tiboot3-j784s4-hs-fs-evm.bin";
-
+	tiboot3_j784s4_hs_fs: template-10 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
 				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
@@ -90,7 +87,6 @@
 		};
 
 		ti_fs_enc_fs: ti-fs-enc.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -101,7 +97,6 @@
 		};
 
 		sysfw_inner_cert_fs: sysfw-inner-cert {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -110,14 +105,13 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
+		};
 	};
 };
 
 &binman {
-	tiboot3-j784s4-gp-evm.bin {
-		filename = "tiboot3-j784s4-gp-evm.bin";
-		symlink = "tiboot3.bin";
-
+	tiboot3_j784s4_gp: template-11 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
 				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
@@ -140,7 +134,6 @@
 		};
 
 		ti_fs_gp: ti-fs-gp.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -154,43 +147,14 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
-
-	};
-};
-
-#include "k3-binman-capsule-r5.dtsi"
-
-// Capsule update GUIDs in string form.  See j784s4_evm.h
-#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
-
-&capsule_tiboot3 {
-	efi-capsule {
-		image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
-
-		blob {
-			filename = "tiboot3-j784s4-hs-fs-evm.bin";
 		};
 	};
 };
 
-#endif
-
-#ifdef CONFIG_TARGET_J784S4_A72_EVM
-
-#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
-#define J784S4_EVM_DTB "u-boot.dtb"
+#else
 
 &binman {
-	ti-dm {
-		filename = "ti-dm.bin";
-
-		blob-ext {
-			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
-			optional;
-		};
-	};
-
-	ti-spl {
+	ti_spl: template-12 {
 		insert-template = <&ti_spl_template>;
 
 		fit {
@@ -207,19 +171,20 @@
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					ti-secure {
-						content = <&spl_j784s4_evm_dtb>;
+						content = <&spl_board_dtb>;
 						keyfile = "custMpk.pem";
 					};
 
-					spl_j784s4_evm_dtb: blob-ext {
-						filename = SPL_J784S4_EVM_DTB;
+					spl_board_dtb: blob-ext {
+						filename = SPL_BOARD_DTB;
 					};
+
 				};
 			};
 
@@ -227,7 +192,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "atf";
 					loadables = "tee", "dm", "spl";
 					fdt = "fdt-0";
@@ -238,17 +203,17 @@
 };
 
 &binman {
-	u-boot {
+	u_boot: template-13 {
 		insert-template = <&u_boot_template>;
 
 		fit {
 			images {
 				uboot {
-					description = "U-Boot for J784S4 board";
+					description = UBOOT_BOARD_DESCRIPTION;
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
@@ -259,7 +224,7 @@
 					};
 
 					j784s4_evm_dtb: blob-ext {
-						filename = J784S4_EVM_DTB;
+						filename = "u-boot.dtb";
 					};
 
 					hash {
@@ -272,7 +237,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "uboot";
 					loadables = "uboot";
 					fdt = "fdt-0";
@@ -283,7 +248,7 @@
 };
 
 &binman {
-	ti-spl_unsigned {
+	ti_spl_unsigned: template-14 {
 		insert-template = <&ti_spl_unsigned_template>;
 
 		fit {
@@ -295,13 +260,13 @@
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					spl_j784s4_evm_dtb_unsigned: blob {
-						filename = SPL_J784S4_EVM_DTB;
+						filename = SPL_BOARD_DTB;
 					};
 				};
 			};
@@ -310,7 +275,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "atf";
 					loadables = "tee", "dm", "spl";
 					fdt = "fdt-0";
@@ -321,23 +286,23 @@
 };
 
 &binman {
-	u-boot_unsigned {
+	u_boot_unsigned: template-15 {
 		insert-template = <&u_boot_unsigned_template>;
 
 		fit {
 			images {
 				uboot {
-					description = "U-Boot for J784S4 board";
+					description = UBOOT_BOARD_DESCRIPTION;
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					j784s4_evm_dtb_unsigned: blob {
-						filename = J784S4_EVM_DTB;
+						filename = "u-boot.dtb";
 					};
 
 					hash {
@@ -350,7 +315,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "uboot";
 					loadables = "uboot";
 					fdt = "fdt-0";
@@ -359,23 +324,4 @@
 		};
 	};
 };
-
-#include "k3-binman-capsule.dtsi"
-
-// Capsule update GUIDs in string form.  See j784s4_evm.h
-#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
-#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
-
-&capsule_tispl {
-	efi-capsule {
-		image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
-	};
-};
-
-&capsule_uboot {
-	efi-capsule {
-		image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
-	};
-};
-
 #endif
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
index fc74c539331..47ed3f05eb2 100644
--- a/arch/arm/dts/k3-j784s4-ddr.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -3,8864 +3,4424 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-&main_navss {
-	ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
-		 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
-		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
-		 <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
-		 <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
-		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
-		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
-		 <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
-		 <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
-		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+#include "k3-j784s4-j742s2-ddr.dtsi"
 
-	msmc0: msmc {
-		compatible = "ti,j721s2-msmc";
-		intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
-		intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
-		ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
-		emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
-		emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
-		#address-cells = <2>;
-		#size-cells = <2>;
+&msmc0 {
+	memorycontroller2: memorycontroller@29d0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029d0000 0x0 0x4000>,
+			  <0x0 0x0114000 0x0 0x100>,
+			  <0x0 0x029c0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+			<&k3_pds 133 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
+		ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+		instance = <2>;
 
 		bootph-pre-ram;
 
-		memorycontroller0: memorycontroller@2990000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x02990000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x02980000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
-				<&k3_pds 131 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <0>;
+		ti,ctl-data = <
+			DDRSS2_CTL_00_DATA
+			DDRSS2_CTL_01_DATA
+			DDRSS2_CTL_02_DATA
+			DDRSS2_CTL_03_DATA
+			DDRSS2_CTL_04_DATA
+			DDRSS2_CTL_05_DATA
+			DDRSS2_CTL_06_DATA
+			DDRSS2_CTL_07_DATA
+			DDRSS2_CTL_08_DATA
+			DDRSS2_CTL_09_DATA
+			DDRSS2_CTL_10_DATA
+			DDRSS2_CTL_11_DATA
+			DDRSS2_CTL_12_DATA
+			DDRSS2_CTL_13_DATA
+			DDRSS2_CTL_14_DATA
+			DDRSS2_CTL_15_DATA
+			DDRSS2_CTL_16_DATA
+			DDRSS2_CTL_17_DATA
+			DDRSS2_CTL_18_DATA
+			DDRSS2_CTL_19_DATA
+			DDRSS2_CTL_20_DATA
+			DDRSS2_CTL_21_DATA
+			DDRSS2_CTL_22_DATA
+			DDRSS2_CTL_23_DATA
+			DDRSS2_CTL_24_DATA
+			DDRSS2_CTL_25_DATA
+			DDRSS2_CTL_26_DATA
+			DDRSS2_CTL_27_DATA
+			DDRSS2_CTL_28_DATA
+			DDRSS2_CTL_29_DATA
+			DDRSS2_CTL_30_DATA
+			DDRSS2_CTL_31_DATA
+			DDRSS2_CTL_32_DATA
+			DDRSS2_CTL_33_DATA
+			DDRSS2_CTL_34_DATA
+			DDRSS2_CTL_35_DATA
+			DDRSS2_CTL_36_DATA
+			DDRSS2_CTL_37_DATA
+			DDRSS2_CTL_38_DATA
+			DDRSS2_CTL_39_DATA
+			DDRSS2_CTL_40_DATA
+			DDRSS2_CTL_41_DATA
+			DDRSS2_CTL_42_DATA
+			DDRSS2_CTL_43_DATA
+			DDRSS2_CTL_44_DATA
+			DDRSS2_CTL_45_DATA
+			DDRSS2_CTL_46_DATA
+			DDRSS2_CTL_47_DATA
+			DDRSS2_CTL_48_DATA
+			DDRSS2_CTL_49_DATA
+			DDRSS2_CTL_50_DATA
+			DDRSS2_CTL_51_DATA
+			DDRSS2_CTL_52_DATA
+			DDRSS2_CTL_53_DATA
+			DDRSS2_CTL_54_DATA
+			DDRSS2_CTL_55_DATA
+			DDRSS2_CTL_56_DATA
+			DDRSS2_CTL_57_DATA
+			DDRSS2_CTL_58_DATA
+			DDRSS2_CTL_59_DATA
+			DDRSS2_CTL_60_DATA
+			DDRSS2_CTL_61_DATA
+			DDRSS2_CTL_62_DATA
+			DDRSS2_CTL_63_DATA
+			DDRSS2_CTL_64_DATA
+			DDRSS2_CTL_65_DATA
+			DDRSS2_CTL_66_DATA
+			DDRSS2_CTL_67_DATA
+			DDRSS2_CTL_68_DATA
+			DDRSS2_CTL_69_DATA
+			DDRSS2_CTL_70_DATA
+			DDRSS2_CTL_71_DATA
+			DDRSS2_CTL_72_DATA
+			DDRSS2_CTL_73_DATA
+			DDRSS2_CTL_74_DATA
+			DDRSS2_CTL_75_DATA
+			DDRSS2_CTL_76_DATA
+			DDRSS2_CTL_77_DATA
+			DDRSS2_CTL_78_DATA
+			DDRSS2_CTL_79_DATA
+			DDRSS2_CTL_80_DATA
+			DDRSS2_CTL_81_DATA
+			DDRSS2_CTL_82_DATA
+			DDRSS2_CTL_83_DATA
+			DDRSS2_CTL_84_DATA
+			DDRSS2_CTL_85_DATA
+			DDRSS2_CTL_86_DATA
+			DDRSS2_CTL_87_DATA
+			DDRSS2_CTL_88_DATA
+			DDRSS2_CTL_89_DATA
+			DDRSS2_CTL_90_DATA
+			DDRSS2_CTL_91_DATA
+			DDRSS2_CTL_92_DATA
+			DDRSS2_CTL_93_DATA
+			DDRSS2_CTL_94_DATA
+			DDRSS2_CTL_95_DATA
+			DDRSS2_CTL_96_DATA
+			DDRSS2_CTL_97_DATA
+			DDRSS2_CTL_98_DATA
+			DDRSS2_CTL_99_DATA
+			DDRSS2_CTL_100_DATA
+			DDRSS2_CTL_101_DATA
+			DDRSS2_CTL_102_DATA
+			DDRSS2_CTL_103_DATA
+			DDRSS2_CTL_104_DATA
+			DDRSS2_CTL_105_DATA
+			DDRSS2_CTL_106_DATA
+			DDRSS2_CTL_107_DATA
+			DDRSS2_CTL_108_DATA
+			DDRSS2_CTL_109_DATA
+			DDRSS2_CTL_110_DATA
+			DDRSS2_CTL_111_DATA
+			DDRSS2_CTL_112_DATA
+			DDRSS2_CTL_113_DATA
+			DDRSS2_CTL_114_DATA
+			DDRSS2_CTL_115_DATA
+			DDRSS2_CTL_116_DATA
+			DDRSS2_CTL_117_DATA
+			DDRSS2_CTL_118_DATA
+			DDRSS2_CTL_119_DATA
+			DDRSS2_CTL_120_DATA
+			DDRSS2_CTL_121_DATA
+			DDRSS2_CTL_122_DATA
+			DDRSS2_CTL_123_DATA
+			DDRSS2_CTL_124_DATA
+			DDRSS2_CTL_125_DATA
+			DDRSS2_CTL_126_DATA
+			DDRSS2_CTL_127_DATA
+			DDRSS2_CTL_128_DATA
+			DDRSS2_CTL_129_DATA
+			DDRSS2_CTL_130_DATA
+			DDRSS2_CTL_131_DATA
+			DDRSS2_CTL_132_DATA
+			DDRSS2_CTL_133_DATA
+			DDRSS2_CTL_134_DATA
+			DDRSS2_CTL_135_DATA
+			DDRSS2_CTL_136_DATA
+			DDRSS2_CTL_137_DATA
+			DDRSS2_CTL_138_DATA
+			DDRSS2_CTL_139_DATA
+			DDRSS2_CTL_140_DATA
+			DDRSS2_CTL_141_DATA
+			DDRSS2_CTL_142_DATA
+			DDRSS2_CTL_143_DATA
+			DDRSS2_CTL_144_DATA
+			DDRSS2_CTL_145_DATA
+			DDRSS2_CTL_146_DATA
+			DDRSS2_CTL_147_DATA
+			DDRSS2_CTL_148_DATA
+			DDRSS2_CTL_149_DATA
+			DDRSS2_CTL_150_DATA
+			DDRSS2_CTL_151_DATA
+			DDRSS2_CTL_152_DATA
+			DDRSS2_CTL_153_DATA
+			DDRSS2_CTL_154_DATA
+			DDRSS2_CTL_155_DATA
+			DDRSS2_CTL_156_DATA
+			DDRSS2_CTL_157_DATA
+			DDRSS2_CTL_158_DATA
+			DDRSS2_CTL_159_DATA
+			DDRSS2_CTL_160_DATA
+			DDRSS2_CTL_161_DATA
+			DDRSS2_CTL_162_DATA
+			DDRSS2_CTL_163_DATA
+			DDRSS2_CTL_164_DATA
+			DDRSS2_CTL_165_DATA
+			DDRSS2_CTL_166_DATA
+			DDRSS2_CTL_167_DATA
+			DDRSS2_CTL_168_DATA
+			DDRSS2_CTL_169_DATA
+			DDRSS2_CTL_170_DATA
+			DDRSS2_CTL_171_DATA
+			DDRSS2_CTL_172_DATA
+			DDRSS2_CTL_173_DATA
+			DDRSS2_CTL_174_DATA
+			DDRSS2_CTL_175_DATA
+			DDRSS2_CTL_176_DATA
+			DDRSS2_CTL_177_DATA
+			DDRSS2_CTL_178_DATA
+			DDRSS2_CTL_179_DATA
+			DDRSS2_CTL_180_DATA
+			DDRSS2_CTL_181_DATA
+			DDRSS2_CTL_182_DATA
+			DDRSS2_CTL_183_DATA
+			DDRSS2_CTL_184_DATA
+			DDRSS2_CTL_185_DATA
+			DDRSS2_CTL_186_DATA
+			DDRSS2_CTL_187_DATA
+			DDRSS2_CTL_188_DATA
+			DDRSS2_CTL_189_DATA
+			DDRSS2_CTL_190_DATA
+			DDRSS2_CTL_191_DATA
+			DDRSS2_CTL_192_DATA
+			DDRSS2_CTL_193_DATA
+			DDRSS2_CTL_194_DATA
+			DDRSS2_CTL_195_DATA
+			DDRSS2_CTL_196_DATA
+			DDRSS2_CTL_197_DATA
+			DDRSS2_CTL_198_DATA
+			DDRSS2_CTL_199_DATA
+			DDRSS2_CTL_200_DATA
+			DDRSS2_CTL_201_DATA
+			DDRSS2_CTL_202_DATA
+			DDRSS2_CTL_203_DATA
+			DDRSS2_CTL_204_DATA
+			DDRSS2_CTL_205_DATA
+			DDRSS2_CTL_206_DATA
+			DDRSS2_CTL_207_DATA
+			DDRSS2_CTL_208_DATA
+			DDRSS2_CTL_209_DATA
+			DDRSS2_CTL_210_DATA
+			DDRSS2_CTL_211_DATA
+			DDRSS2_CTL_212_DATA
+			DDRSS2_CTL_213_DATA
+			DDRSS2_CTL_214_DATA
+			DDRSS2_CTL_215_DATA
+			DDRSS2_CTL_216_DATA
+			DDRSS2_CTL_217_DATA
+			DDRSS2_CTL_218_DATA
+			DDRSS2_CTL_219_DATA
+			DDRSS2_CTL_220_DATA
+			DDRSS2_CTL_221_DATA
+			DDRSS2_CTL_222_DATA
+			DDRSS2_CTL_223_DATA
+			DDRSS2_CTL_224_DATA
+			DDRSS2_CTL_225_DATA
+			DDRSS2_CTL_226_DATA
+			DDRSS2_CTL_227_DATA
+			DDRSS2_CTL_228_DATA
+			DDRSS2_CTL_229_DATA
+			DDRSS2_CTL_230_DATA
+			DDRSS2_CTL_231_DATA
+			DDRSS2_CTL_232_DATA
+			DDRSS2_CTL_233_DATA
+			DDRSS2_CTL_234_DATA
+			DDRSS2_CTL_235_DATA
+			DDRSS2_CTL_236_DATA
+			DDRSS2_CTL_237_DATA
+			DDRSS2_CTL_238_DATA
+			DDRSS2_CTL_239_DATA
+			DDRSS2_CTL_240_DATA
+			DDRSS2_CTL_241_DATA
+			DDRSS2_CTL_242_DATA
+			DDRSS2_CTL_243_DATA
+			DDRSS2_CTL_244_DATA
+			DDRSS2_CTL_245_DATA
+			DDRSS2_CTL_246_DATA
+			DDRSS2_CTL_247_DATA
+			DDRSS2_CTL_248_DATA
+			DDRSS2_CTL_249_DATA
+			DDRSS2_CTL_250_DATA
+			DDRSS2_CTL_251_DATA
+			DDRSS2_CTL_252_DATA
+			DDRSS2_CTL_253_DATA
+			DDRSS2_CTL_254_DATA
+			DDRSS2_CTL_255_DATA
+			DDRSS2_CTL_256_DATA
+			DDRSS2_CTL_257_DATA
+			DDRSS2_CTL_258_DATA
+			DDRSS2_CTL_259_DATA
+			DDRSS2_CTL_260_DATA
+			DDRSS2_CTL_261_DATA
+			DDRSS2_CTL_262_DATA
+			DDRSS2_CTL_263_DATA
+			DDRSS2_CTL_264_DATA
+			DDRSS2_CTL_265_DATA
+			DDRSS2_CTL_266_DATA
+			DDRSS2_CTL_267_DATA
+			DDRSS2_CTL_268_DATA
+			DDRSS2_CTL_269_DATA
+			DDRSS2_CTL_270_DATA
+			DDRSS2_CTL_271_DATA
+			DDRSS2_CTL_272_DATA
+			DDRSS2_CTL_273_DATA
+			DDRSS2_CTL_274_DATA
+			DDRSS2_CTL_275_DATA
+			DDRSS2_CTL_276_DATA
+			DDRSS2_CTL_277_DATA
+			DDRSS2_CTL_278_DATA
+			DDRSS2_CTL_279_DATA
+			DDRSS2_CTL_280_DATA
+			DDRSS2_CTL_281_DATA
+			DDRSS2_CTL_282_DATA
+			DDRSS2_CTL_283_DATA
+			DDRSS2_CTL_284_DATA
+			DDRSS2_CTL_285_DATA
+			DDRSS2_CTL_286_DATA
+			DDRSS2_CTL_287_DATA
+			DDRSS2_CTL_288_DATA
+			DDRSS2_CTL_289_DATA
+			DDRSS2_CTL_290_DATA
+			DDRSS2_CTL_291_DATA
+			DDRSS2_CTL_292_DATA
+			DDRSS2_CTL_293_DATA
+			DDRSS2_CTL_294_DATA
+			DDRSS2_CTL_295_DATA
+			DDRSS2_CTL_296_DATA
+			DDRSS2_CTL_297_DATA
+			DDRSS2_CTL_298_DATA
+			DDRSS2_CTL_299_DATA
+			DDRSS2_CTL_300_DATA
+			DDRSS2_CTL_301_DATA
+			DDRSS2_CTL_302_DATA
+			DDRSS2_CTL_303_DATA
+			DDRSS2_CTL_304_DATA
+			DDRSS2_CTL_305_DATA
+			DDRSS2_CTL_306_DATA
+			DDRSS2_CTL_307_DATA
+			DDRSS2_CTL_308_DATA
+			DDRSS2_CTL_309_DATA
+			DDRSS2_CTL_310_DATA
+			DDRSS2_CTL_311_DATA
+			DDRSS2_CTL_312_DATA
+			DDRSS2_CTL_313_DATA
+			DDRSS2_CTL_314_DATA
+			DDRSS2_CTL_315_DATA
+			DDRSS2_CTL_316_DATA
+			DDRSS2_CTL_317_DATA
+			DDRSS2_CTL_318_DATA
+			DDRSS2_CTL_319_DATA
+			DDRSS2_CTL_320_DATA
+			DDRSS2_CTL_321_DATA
+			DDRSS2_CTL_322_DATA
+			DDRSS2_CTL_323_DATA
+			DDRSS2_CTL_324_DATA
+			DDRSS2_CTL_325_DATA
+			DDRSS2_CTL_326_DATA
+			DDRSS2_CTL_327_DATA
+			DDRSS2_CTL_328_DATA
+			DDRSS2_CTL_329_DATA
+			DDRSS2_CTL_330_DATA
+			DDRSS2_CTL_331_DATA
+			DDRSS2_CTL_332_DATA
+			DDRSS2_CTL_333_DATA
+			DDRSS2_CTL_334_DATA
+			DDRSS2_CTL_335_DATA
+			DDRSS2_CTL_336_DATA
+			DDRSS2_CTL_337_DATA
+			DDRSS2_CTL_338_DATA
+			DDRSS2_CTL_339_DATA
+			DDRSS2_CTL_340_DATA
+			DDRSS2_CTL_341_DATA
+			DDRSS2_CTL_342_DATA
+			DDRSS2_CTL_343_DATA
+			DDRSS2_CTL_344_DATA
+			DDRSS2_CTL_345_DATA
+			DDRSS2_CTL_346_DATA
+			DDRSS2_CTL_347_DATA
+			DDRSS2_CTL_348_DATA
+			DDRSS2_CTL_349_DATA
+			DDRSS2_CTL_350_DATA
+			DDRSS2_CTL_351_DATA
+			DDRSS2_CTL_352_DATA
+			DDRSS2_CTL_353_DATA
+			DDRSS2_CTL_354_DATA
+			DDRSS2_CTL_355_DATA
+			DDRSS2_CTL_356_DATA
+			DDRSS2_CTL_357_DATA
+			DDRSS2_CTL_358_DATA
+			DDRSS2_CTL_359_DATA
+			DDRSS2_CTL_360_DATA
+			DDRSS2_CTL_361_DATA
+			DDRSS2_CTL_362_DATA
+			DDRSS2_CTL_363_DATA
+			DDRSS2_CTL_364_DATA
+			DDRSS2_CTL_365_DATA
+			DDRSS2_CTL_366_DATA
+			DDRSS2_CTL_367_DATA
+			DDRSS2_CTL_368_DATA
+			DDRSS2_CTL_369_DATA
+			DDRSS2_CTL_370_DATA
+			DDRSS2_CTL_371_DATA
+			DDRSS2_CTL_372_DATA
+			DDRSS2_CTL_373_DATA
+			DDRSS2_CTL_374_DATA
+			DDRSS2_CTL_375_DATA
+			DDRSS2_CTL_376_DATA
+			DDRSS2_CTL_377_DATA
+			DDRSS2_CTL_378_DATA
+			DDRSS2_CTL_379_DATA
+			DDRSS2_CTL_380_DATA
+			DDRSS2_CTL_381_DATA
+			DDRSS2_CTL_382_DATA
+			DDRSS2_CTL_383_DATA
+			DDRSS2_CTL_384_DATA
+			DDRSS2_CTL_385_DATA
+			DDRSS2_CTL_386_DATA
+			DDRSS2_CTL_387_DATA
+			DDRSS2_CTL_388_DATA
+			DDRSS2_CTL_389_DATA
+			DDRSS2_CTL_390_DATA
+			DDRSS2_CTL_391_DATA
+			DDRSS2_CTL_392_DATA
+			DDRSS2_CTL_393_DATA
+			DDRSS2_CTL_394_DATA
+			DDRSS2_CTL_395_DATA
+			DDRSS2_CTL_396_DATA
+			DDRSS2_CTL_397_DATA
+			DDRSS2_CTL_398_DATA
+			DDRSS2_CTL_399_DATA
+			DDRSS2_CTL_400_DATA
+			DDRSS2_CTL_401_DATA
+			DDRSS2_CTL_402_DATA
+			DDRSS2_CTL_403_DATA
+			DDRSS2_CTL_404_DATA
+			DDRSS2_CTL_405_DATA
+			DDRSS2_CTL_406_DATA
+			DDRSS2_CTL_407_DATA
+			DDRSS2_CTL_408_DATA
+			DDRSS2_CTL_409_DATA
+			DDRSS2_CTL_410_DATA
+			DDRSS2_CTL_411_DATA
+			DDRSS2_CTL_412_DATA
+			DDRSS2_CTL_413_DATA
+			DDRSS2_CTL_414_DATA
+			DDRSS2_CTL_415_DATA
+			DDRSS2_CTL_416_DATA
+			DDRSS2_CTL_417_DATA
+			DDRSS2_CTL_418_DATA
+			DDRSS2_CTL_419_DATA
+			DDRSS2_CTL_420_DATA
+			DDRSS2_CTL_421_DATA
+			DDRSS2_CTL_422_DATA
+			DDRSS2_CTL_423_DATA
+			DDRSS2_CTL_424_DATA
+			DDRSS2_CTL_425_DATA
+			DDRSS2_CTL_426_DATA
+			DDRSS2_CTL_427_DATA
+			DDRSS2_CTL_428_DATA
+			DDRSS2_CTL_429_DATA
+			DDRSS2_CTL_430_DATA
+			DDRSS2_CTL_431_DATA
+			DDRSS2_CTL_432_DATA
+			DDRSS2_CTL_433_DATA
+			DDRSS2_CTL_434_DATA
+			DDRSS2_CTL_435_DATA
+			DDRSS2_CTL_436_DATA
+			DDRSS2_CTL_437_DATA
+			DDRSS2_CTL_438_DATA
+			DDRSS2_CTL_439_DATA
+			DDRSS2_CTL_440_DATA
+			DDRSS2_CTL_441_DATA
+			DDRSS2_CTL_442_DATA
+			DDRSS2_CTL_443_DATA
+			DDRSS2_CTL_444_DATA
+			DDRSS2_CTL_445_DATA
+			DDRSS2_CTL_446_DATA
+			DDRSS2_CTL_447_DATA
+			DDRSS2_CTL_448_DATA
+			DDRSS2_CTL_449_DATA
+			DDRSS2_CTL_450_DATA
+			DDRSS2_CTL_451_DATA
+			DDRSS2_CTL_452_DATA
+			DDRSS2_CTL_453_DATA
+			DDRSS2_CTL_454_DATA
+			DDRSS2_CTL_455_DATA
+			DDRSS2_CTL_456_DATA
+			DDRSS2_CTL_457_DATA
+			DDRSS2_CTL_458_DATA
+		>;
 
-			bootph-pre-ram;
+		ti,pi-data = <
+			DDRSS2_PI_00_DATA
+			DDRSS2_PI_01_DATA
+			DDRSS2_PI_02_DATA
+			DDRSS2_PI_03_DATA
+			DDRSS2_PI_04_DATA
+			DDRSS2_PI_05_DATA
+			DDRSS2_PI_06_DATA
+			DDRSS2_PI_07_DATA
+			DDRSS2_PI_08_DATA
+			DDRSS2_PI_09_DATA
+			DDRSS2_PI_10_DATA
+			DDRSS2_PI_11_DATA
+			DDRSS2_PI_12_DATA
+			DDRSS2_PI_13_DATA
+			DDRSS2_PI_14_DATA
+			DDRSS2_PI_15_DATA
+			DDRSS2_PI_16_DATA
+			DDRSS2_PI_17_DATA
+			DDRSS2_PI_18_DATA
+			DDRSS2_PI_19_DATA
+			DDRSS2_PI_20_DATA
+			DDRSS2_PI_21_DATA
+			DDRSS2_PI_22_DATA
+			DDRSS2_PI_23_DATA
+			DDRSS2_PI_24_DATA
+			DDRSS2_PI_25_DATA
+			DDRSS2_PI_26_DATA
+			DDRSS2_PI_27_DATA
+			DDRSS2_PI_28_DATA
+			DDRSS2_PI_29_DATA
+			DDRSS2_PI_30_DATA
+			DDRSS2_PI_31_DATA
+			DDRSS2_PI_32_DATA
+			DDRSS2_PI_33_DATA
+			DDRSS2_PI_34_DATA
+			DDRSS2_PI_35_DATA
+			DDRSS2_PI_36_DATA
+			DDRSS2_PI_37_DATA
+			DDRSS2_PI_38_DATA
+			DDRSS2_PI_39_DATA
+			DDRSS2_PI_40_DATA
+			DDRSS2_PI_41_DATA
+			DDRSS2_PI_42_DATA
+			DDRSS2_PI_43_DATA
+			DDRSS2_PI_44_DATA
+			DDRSS2_PI_45_DATA
+			DDRSS2_PI_46_DATA
+			DDRSS2_PI_47_DATA
+			DDRSS2_PI_48_DATA
+			DDRSS2_PI_49_DATA
+			DDRSS2_PI_50_DATA
+			DDRSS2_PI_51_DATA
+			DDRSS2_PI_52_DATA
+			DDRSS2_PI_53_DATA
+			DDRSS2_PI_54_DATA
+			DDRSS2_PI_55_DATA
+			DDRSS2_PI_56_DATA
+			DDRSS2_PI_57_DATA
+			DDRSS2_PI_58_DATA
+			DDRSS2_PI_59_DATA
+			DDRSS2_PI_60_DATA
+			DDRSS2_PI_61_DATA
+			DDRSS2_PI_62_DATA
+			DDRSS2_PI_63_DATA
+			DDRSS2_PI_64_DATA
+			DDRSS2_PI_65_DATA
+			DDRSS2_PI_66_DATA
+			DDRSS2_PI_67_DATA
+			DDRSS2_PI_68_DATA
+			DDRSS2_PI_69_DATA
+			DDRSS2_PI_70_DATA
+			DDRSS2_PI_71_DATA
+			DDRSS2_PI_72_DATA
+			DDRSS2_PI_73_DATA
+			DDRSS2_PI_74_DATA
+			DDRSS2_PI_75_DATA
+			DDRSS2_PI_76_DATA
+			DDRSS2_PI_77_DATA
+			DDRSS2_PI_78_DATA
+			DDRSS2_PI_79_DATA
+			DDRSS2_PI_80_DATA
+			DDRSS2_PI_81_DATA
+			DDRSS2_PI_82_DATA
+			DDRSS2_PI_83_DATA
+			DDRSS2_PI_84_DATA
+			DDRSS2_PI_85_DATA
+			DDRSS2_PI_86_DATA
+			DDRSS2_PI_87_DATA
+			DDRSS2_PI_88_DATA
+			DDRSS2_PI_89_DATA
+			DDRSS2_PI_90_DATA
+			DDRSS2_PI_91_DATA
+			DDRSS2_PI_92_DATA
+			DDRSS2_PI_93_DATA
+			DDRSS2_PI_94_DATA
+			DDRSS2_PI_95_DATA
+			DDRSS2_PI_96_DATA
+			DDRSS2_PI_97_DATA
+			DDRSS2_PI_98_DATA
+			DDRSS2_PI_99_DATA
+			DDRSS2_PI_100_DATA
+			DDRSS2_PI_101_DATA
+			DDRSS2_PI_102_DATA
+			DDRSS2_PI_103_DATA
+			DDRSS2_PI_104_DATA
+			DDRSS2_PI_105_DATA
+			DDRSS2_PI_106_DATA
+			DDRSS2_PI_107_DATA
+			DDRSS2_PI_108_DATA
+			DDRSS2_PI_109_DATA
+			DDRSS2_PI_110_DATA
+			DDRSS2_PI_111_DATA
+			DDRSS2_PI_112_DATA
+			DDRSS2_PI_113_DATA
+			DDRSS2_PI_114_DATA
+			DDRSS2_PI_115_DATA
+			DDRSS2_PI_116_DATA
+			DDRSS2_PI_117_DATA
+			DDRSS2_PI_118_DATA
+			DDRSS2_PI_119_DATA
+			DDRSS2_PI_120_DATA
+			DDRSS2_PI_121_DATA
+			DDRSS2_PI_122_DATA
+			DDRSS2_PI_123_DATA
+			DDRSS2_PI_124_DATA
+			DDRSS2_PI_125_DATA
+			DDRSS2_PI_126_DATA
+			DDRSS2_PI_127_DATA
+			DDRSS2_PI_128_DATA
+			DDRSS2_PI_129_DATA
+			DDRSS2_PI_130_DATA
+			DDRSS2_PI_131_DATA
+			DDRSS2_PI_132_DATA
+			DDRSS2_PI_133_DATA
+			DDRSS2_PI_134_DATA
+			DDRSS2_PI_135_DATA
+			DDRSS2_PI_136_DATA
+			DDRSS2_PI_137_DATA
+			DDRSS2_PI_138_DATA
+			DDRSS2_PI_139_DATA
+			DDRSS2_PI_140_DATA
+			DDRSS2_PI_141_DATA
+			DDRSS2_PI_142_DATA
+			DDRSS2_PI_143_DATA
+			DDRSS2_PI_144_DATA
+			DDRSS2_PI_145_DATA
+			DDRSS2_PI_146_DATA
+			DDRSS2_PI_147_DATA
+			DDRSS2_PI_148_DATA
+			DDRSS2_PI_149_DATA
+			DDRSS2_PI_150_DATA
+			DDRSS2_PI_151_DATA
+			DDRSS2_PI_152_DATA
+			DDRSS2_PI_153_DATA
+			DDRSS2_PI_154_DATA
+			DDRSS2_PI_155_DATA
+			DDRSS2_PI_156_DATA
+			DDRSS2_PI_157_DATA
+			DDRSS2_PI_158_DATA
+			DDRSS2_PI_159_DATA
+			DDRSS2_PI_160_DATA
+			DDRSS2_PI_161_DATA
+			DDRSS2_PI_162_DATA
+			DDRSS2_PI_163_DATA
+			DDRSS2_PI_164_DATA
+			DDRSS2_PI_165_DATA
+			DDRSS2_PI_166_DATA
+			DDRSS2_PI_167_DATA
+			DDRSS2_PI_168_DATA
+			DDRSS2_PI_169_DATA
+			DDRSS2_PI_170_DATA
+			DDRSS2_PI_171_DATA
+			DDRSS2_PI_172_DATA
+			DDRSS2_PI_173_DATA
+			DDRSS2_PI_174_DATA
+			DDRSS2_PI_175_DATA
+			DDRSS2_PI_176_DATA
+			DDRSS2_PI_177_DATA
+			DDRSS2_PI_178_DATA
+			DDRSS2_PI_179_DATA
+			DDRSS2_PI_180_DATA
+			DDRSS2_PI_181_DATA
+			DDRSS2_PI_182_DATA
+			DDRSS2_PI_183_DATA
+			DDRSS2_PI_184_DATA
+			DDRSS2_PI_185_DATA
+			DDRSS2_PI_186_DATA
+			DDRSS2_PI_187_DATA
+			DDRSS2_PI_188_DATA
+			DDRSS2_PI_189_DATA
+			DDRSS2_PI_190_DATA
+			DDRSS2_PI_191_DATA
+			DDRSS2_PI_192_DATA
+			DDRSS2_PI_193_DATA
+			DDRSS2_PI_194_DATA
+			DDRSS2_PI_195_DATA
+			DDRSS2_PI_196_DATA
+			DDRSS2_PI_197_DATA
+			DDRSS2_PI_198_DATA
+			DDRSS2_PI_199_DATA
+			DDRSS2_PI_200_DATA
+			DDRSS2_PI_201_DATA
+			DDRSS2_PI_202_DATA
+			DDRSS2_PI_203_DATA
+			DDRSS2_PI_204_DATA
+			DDRSS2_PI_205_DATA
+			DDRSS2_PI_206_DATA
+			DDRSS2_PI_207_DATA
+			DDRSS2_PI_208_DATA
+			DDRSS2_PI_209_DATA
+			DDRSS2_PI_210_DATA
+			DDRSS2_PI_211_DATA
+			DDRSS2_PI_212_DATA
+			DDRSS2_PI_213_DATA
+			DDRSS2_PI_214_DATA
+			DDRSS2_PI_215_DATA
+			DDRSS2_PI_216_DATA
+			DDRSS2_PI_217_DATA
+			DDRSS2_PI_218_DATA
+			DDRSS2_PI_219_DATA
+			DDRSS2_PI_220_DATA
+			DDRSS2_PI_221_DATA
+			DDRSS2_PI_222_DATA
+			DDRSS2_PI_223_DATA
+			DDRSS2_PI_224_DATA
+			DDRSS2_PI_225_DATA
+			DDRSS2_PI_226_DATA
+			DDRSS2_PI_227_DATA
+			DDRSS2_PI_228_DATA
+			DDRSS2_PI_229_DATA
+			DDRSS2_PI_230_DATA
+			DDRSS2_PI_231_DATA
+			DDRSS2_PI_232_DATA
+			DDRSS2_PI_233_DATA
+			DDRSS2_PI_234_DATA
+			DDRSS2_PI_235_DATA
+			DDRSS2_PI_236_DATA
+			DDRSS2_PI_237_DATA
+			DDRSS2_PI_238_DATA
+			DDRSS2_PI_239_DATA
+			DDRSS2_PI_240_DATA
+			DDRSS2_PI_241_DATA
+			DDRSS2_PI_242_DATA
+			DDRSS2_PI_243_DATA
+			DDRSS2_PI_244_DATA
+			DDRSS2_PI_245_DATA
+			DDRSS2_PI_246_DATA
+			DDRSS2_PI_247_DATA
+			DDRSS2_PI_248_DATA
+			DDRSS2_PI_249_DATA
+			DDRSS2_PI_250_DATA
+			DDRSS2_PI_251_DATA
+			DDRSS2_PI_252_DATA
+			DDRSS2_PI_253_DATA
+			DDRSS2_PI_254_DATA
+			DDRSS2_PI_255_DATA
+			DDRSS2_PI_256_DATA
+			DDRSS2_PI_257_DATA
+			DDRSS2_PI_258_DATA
+			DDRSS2_PI_259_DATA
+			DDRSS2_PI_260_DATA
+			DDRSS2_PI_261_DATA
+			DDRSS2_PI_262_DATA
+			DDRSS2_PI_263_DATA
+			DDRSS2_PI_264_DATA
+			DDRSS2_PI_265_DATA
+			DDRSS2_PI_266_DATA
+			DDRSS2_PI_267_DATA
+			DDRSS2_PI_268_DATA
+			DDRSS2_PI_269_DATA
+			DDRSS2_PI_270_DATA
+			DDRSS2_PI_271_DATA
+			DDRSS2_PI_272_DATA
+			DDRSS2_PI_273_DATA
+			DDRSS2_PI_274_DATA
+			DDRSS2_PI_275_DATA
+			DDRSS2_PI_276_DATA
+			DDRSS2_PI_277_DATA
+			DDRSS2_PI_278_DATA
+			DDRSS2_PI_279_DATA
+			DDRSS2_PI_280_DATA
+			DDRSS2_PI_281_DATA
+			DDRSS2_PI_282_DATA
+			DDRSS2_PI_283_DATA
+			DDRSS2_PI_284_DATA
+			DDRSS2_PI_285_DATA
+			DDRSS2_PI_286_DATA
+			DDRSS2_PI_287_DATA
+			DDRSS2_PI_288_DATA
+			DDRSS2_PI_289_DATA
+			DDRSS2_PI_290_DATA
+			DDRSS2_PI_291_DATA
+			DDRSS2_PI_292_DATA
+			DDRSS2_PI_293_DATA
+			DDRSS2_PI_294_DATA
+			DDRSS2_PI_295_DATA
+			DDRSS2_PI_296_DATA
+			DDRSS2_PI_297_DATA
+			DDRSS2_PI_298_DATA
+			DDRSS2_PI_299_DATA
+		>;
 
-			ti,ctl-data = <
-				DDRSS0_CTL_00_DATA
-				DDRSS0_CTL_01_DATA
-				DDRSS0_CTL_02_DATA
-				DDRSS0_CTL_03_DATA
-				DDRSS0_CTL_04_DATA
-				DDRSS0_CTL_05_DATA
-				DDRSS0_CTL_06_DATA
-				DDRSS0_CTL_07_DATA
-				DDRSS0_CTL_08_DATA
-				DDRSS0_CTL_09_DATA
-				DDRSS0_CTL_10_DATA
-				DDRSS0_CTL_11_DATA
-				DDRSS0_CTL_12_DATA
-				DDRSS0_CTL_13_DATA
-				DDRSS0_CTL_14_DATA
-				DDRSS0_CTL_15_DATA
-				DDRSS0_CTL_16_DATA
-				DDRSS0_CTL_17_DATA
-				DDRSS0_CTL_18_DATA
-				DDRSS0_CTL_19_DATA
-				DDRSS0_CTL_20_DATA
-				DDRSS0_CTL_21_DATA
-				DDRSS0_CTL_22_DATA
-				DDRSS0_CTL_23_DATA
-				DDRSS0_CTL_24_DATA
-				DDRSS0_CTL_25_DATA
-				DDRSS0_CTL_26_DATA
-				DDRSS0_CTL_27_DATA
-				DDRSS0_CTL_28_DATA
-				DDRSS0_CTL_29_DATA
-				DDRSS0_CTL_30_DATA
-				DDRSS0_CTL_31_DATA
-				DDRSS0_CTL_32_DATA
-				DDRSS0_CTL_33_DATA
-				DDRSS0_CTL_34_DATA
-				DDRSS0_CTL_35_DATA
-				DDRSS0_CTL_36_DATA
-				DDRSS0_CTL_37_DATA
-				DDRSS0_CTL_38_DATA
-				DDRSS0_CTL_39_DATA
-				DDRSS0_CTL_40_DATA
-				DDRSS0_CTL_41_DATA
-				DDRSS0_CTL_42_DATA
-				DDRSS0_CTL_43_DATA
-				DDRSS0_CTL_44_DATA
-				DDRSS0_CTL_45_DATA
-				DDRSS0_CTL_46_DATA
-				DDRSS0_CTL_47_DATA
-				DDRSS0_CTL_48_DATA
-				DDRSS0_CTL_49_DATA
-				DDRSS0_CTL_50_DATA
-				DDRSS0_CTL_51_DATA
-				DDRSS0_CTL_52_DATA
-				DDRSS0_CTL_53_DATA
-				DDRSS0_CTL_54_DATA
-				DDRSS0_CTL_55_DATA
-				DDRSS0_CTL_56_DATA
-				DDRSS0_CTL_57_DATA
-				DDRSS0_CTL_58_DATA
-				DDRSS0_CTL_59_DATA
-				DDRSS0_CTL_60_DATA
-				DDRSS0_CTL_61_DATA
-				DDRSS0_CTL_62_DATA
-				DDRSS0_CTL_63_DATA
-				DDRSS0_CTL_64_DATA
-				DDRSS0_CTL_65_DATA
-				DDRSS0_CTL_66_DATA
-				DDRSS0_CTL_67_DATA
-				DDRSS0_CTL_68_DATA
-				DDRSS0_CTL_69_DATA
-				DDRSS0_CTL_70_DATA
-				DDRSS0_CTL_71_DATA
-				DDRSS0_CTL_72_DATA
-				DDRSS0_CTL_73_DATA
-				DDRSS0_CTL_74_DATA
-				DDRSS0_CTL_75_DATA
-				DDRSS0_CTL_76_DATA
-				DDRSS0_CTL_77_DATA
-				DDRSS0_CTL_78_DATA
-				DDRSS0_CTL_79_DATA
-				DDRSS0_CTL_80_DATA
-				DDRSS0_CTL_81_DATA
-				DDRSS0_CTL_82_DATA
-				DDRSS0_CTL_83_DATA
-				DDRSS0_CTL_84_DATA
-				DDRSS0_CTL_85_DATA
-				DDRSS0_CTL_86_DATA
-				DDRSS0_CTL_87_DATA
-				DDRSS0_CTL_88_DATA
-				DDRSS0_CTL_89_DATA
-				DDRSS0_CTL_90_DATA
-				DDRSS0_CTL_91_DATA
-				DDRSS0_CTL_92_DATA
-				DDRSS0_CTL_93_DATA
-				DDRSS0_CTL_94_DATA
-				DDRSS0_CTL_95_DATA
-				DDRSS0_CTL_96_DATA
-				DDRSS0_CTL_97_DATA
-				DDRSS0_CTL_98_DATA
-				DDRSS0_CTL_99_DATA
-				DDRSS0_CTL_100_DATA
-				DDRSS0_CTL_101_DATA
-				DDRSS0_CTL_102_DATA
-				DDRSS0_CTL_103_DATA
-				DDRSS0_CTL_104_DATA
-				DDRSS0_CTL_105_DATA
-				DDRSS0_CTL_106_DATA
-				DDRSS0_CTL_107_DATA
-				DDRSS0_CTL_108_DATA
-				DDRSS0_CTL_109_DATA
-				DDRSS0_CTL_110_DATA
-				DDRSS0_CTL_111_DATA
-				DDRSS0_CTL_112_DATA
-				DDRSS0_CTL_113_DATA
-				DDRSS0_CTL_114_DATA
-				DDRSS0_CTL_115_DATA
-				DDRSS0_CTL_116_DATA
-				DDRSS0_CTL_117_DATA
-				DDRSS0_CTL_118_DATA
-				DDRSS0_CTL_119_DATA
-				DDRSS0_CTL_120_DATA
-				DDRSS0_CTL_121_DATA
-				DDRSS0_CTL_122_DATA
-				DDRSS0_CTL_123_DATA
-				DDRSS0_CTL_124_DATA
-				DDRSS0_CTL_125_DATA
-				DDRSS0_CTL_126_DATA
-				DDRSS0_CTL_127_DATA
-				DDRSS0_CTL_128_DATA
-				DDRSS0_CTL_129_DATA
-				DDRSS0_CTL_130_DATA
-				DDRSS0_CTL_131_DATA
-				DDRSS0_CTL_132_DATA
-				DDRSS0_CTL_133_DATA
-				DDRSS0_CTL_134_DATA
-				DDRSS0_CTL_135_DATA
-				DDRSS0_CTL_136_DATA
-				DDRSS0_CTL_137_DATA
-				DDRSS0_CTL_138_DATA
-				DDRSS0_CTL_139_DATA
-				DDRSS0_CTL_140_DATA
-				DDRSS0_CTL_141_DATA
-				DDRSS0_CTL_142_DATA
-				DDRSS0_CTL_143_DATA
-				DDRSS0_CTL_144_DATA
-				DDRSS0_CTL_145_DATA
-				DDRSS0_CTL_146_DATA
-				DDRSS0_CTL_147_DATA
-				DDRSS0_CTL_148_DATA
-				DDRSS0_CTL_149_DATA
-				DDRSS0_CTL_150_DATA
-				DDRSS0_CTL_151_DATA
-				DDRSS0_CTL_152_DATA
-				DDRSS0_CTL_153_DATA
-				DDRSS0_CTL_154_DATA
-				DDRSS0_CTL_155_DATA
-				DDRSS0_CTL_156_DATA
-				DDRSS0_CTL_157_DATA
-				DDRSS0_CTL_158_DATA
-				DDRSS0_CTL_159_DATA
-				DDRSS0_CTL_160_DATA
-				DDRSS0_CTL_161_DATA
-				DDRSS0_CTL_162_DATA
-				DDRSS0_CTL_163_DATA
-				DDRSS0_CTL_164_DATA
-				DDRSS0_CTL_165_DATA
-				DDRSS0_CTL_166_DATA
-				DDRSS0_CTL_167_DATA
-				DDRSS0_CTL_168_DATA
-				DDRSS0_CTL_169_DATA
-				DDRSS0_CTL_170_DATA
-				DDRSS0_CTL_171_DATA
-				DDRSS0_CTL_172_DATA
-				DDRSS0_CTL_173_DATA
-				DDRSS0_CTL_174_DATA
-				DDRSS0_CTL_175_DATA
-				DDRSS0_CTL_176_DATA
-				DDRSS0_CTL_177_DATA
-				DDRSS0_CTL_178_DATA
-				DDRSS0_CTL_179_DATA
-				DDRSS0_CTL_180_DATA
-				DDRSS0_CTL_181_DATA
-				DDRSS0_CTL_182_DATA
-				DDRSS0_CTL_183_DATA
-				DDRSS0_CTL_184_DATA
-				DDRSS0_CTL_185_DATA
-				DDRSS0_CTL_186_DATA
-				DDRSS0_CTL_187_DATA
-				DDRSS0_CTL_188_DATA
-				DDRSS0_CTL_189_DATA
-				DDRSS0_CTL_190_DATA
-				DDRSS0_CTL_191_DATA
-				DDRSS0_CTL_192_DATA
-				DDRSS0_CTL_193_DATA
-				DDRSS0_CTL_194_DATA
-				DDRSS0_CTL_195_DATA
-				DDRSS0_CTL_196_DATA
-				DDRSS0_CTL_197_DATA
-				DDRSS0_CTL_198_DATA
-				DDRSS0_CTL_199_DATA
-				DDRSS0_CTL_200_DATA
-				DDRSS0_CTL_201_DATA
-				DDRSS0_CTL_202_DATA
-				DDRSS0_CTL_203_DATA
-				DDRSS0_CTL_204_DATA
-				DDRSS0_CTL_205_DATA
-				DDRSS0_CTL_206_DATA
-				DDRSS0_CTL_207_DATA
-				DDRSS0_CTL_208_DATA
-				DDRSS0_CTL_209_DATA
-				DDRSS0_CTL_210_DATA
-				DDRSS0_CTL_211_DATA
-				DDRSS0_CTL_212_DATA
-				DDRSS0_CTL_213_DATA
-				DDRSS0_CTL_214_DATA
-				DDRSS0_CTL_215_DATA
-				DDRSS0_CTL_216_DATA
-				DDRSS0_CTL_217_DATA
-				DDRSS0_CTL_218_DATA
-				DDRSS0_CTL_219_DATA
-				DDRSS0_CTL_220_DATA
-				DDRSS0_CTL_221_DATA
-				DDRSS0_CTL_222_DATA
-				DDRSS0_CTL_223_DATA
-				DDRSS0_CTL_224_DATA
-				DDRSS0_CTL_225_DATA
-				DDRSS0_CTL_226_DATA
-				DDRSS0_CTL_227_DATA
-				DDRSS0_CTL_228_DATA
-				DDRSS0_CTL_229_DATA
-				DDRSS0_CTL_230_DATA
-				DDRSS0_CTL_231_DATA
-				DDRSS0_CTL_232_DATA
-				DDRSS0_CTL_233_DATA
-				DDRSS0_CTL_234_DATA
-				DDRSS0_CTL_235_DATA
-				DDRSS0_CTL_236_DATA
-				DDRSS0_CTL_237_DATA
-				DDRSS0_CTL_238_DATA
-				DDRSS0_CTL_239_DATA
-				DDRSS0_CTL_240_DATA
-				DDRSS0_CTL_241_DATA
-				DDRSS0_CTL_242_DATA
-				DDRSS0_CTL_243_DATA
-				DDRSS0_CTL_244_DATA
-				DDRSS0_CTL_245_DATA
-				DDRSS0_CTL_246_DATA
-				DDRSS0_CTL_247_DATA
-				DDRSS0_CTL_248_DATA
-				DDRSS0_CTL_249_DATA
-				DDRSS0_CTL_250_DATA
-				DDRSS0_CTL_251_DATA
-				DDRSS0_CTL_252_DATA
-				DDRSS0_CTL_253_DATA
-				DDRSS0_CTL_254_DATA
-				DDRSS0_CTL_255_DATA
-				DDRSS0_CTL_256_DATA
-				DDRSS0_CTL_257_DATA
-				DDRSS0_CTL_258_DATA
-				DDRSS0_CTL_259_DATA
-				DDRSS0_CTL_260_DATA
-				DDRSS0_CTL_261_DATA
-				DDRSS0_CTL_262_DATA
-				DDRSS0_CTL_263_DATA
-				DDRSS0_CTL_264_DATA
-				DDRSS0_CTL_265_DATA
-				DDRSS0_CTL_266_DATA
-				DDRSS0_CTL_267_DATA
-				DDRSS0_CTL_268_DATA
-				DDRSS0_CTL_269_DATA
-				DDRSS0_CTL_270_DATA
-				DDRSS0_CTL_271_DATA
-				DDRSS0_CTL_272_DATA
-				DDRSS0_CTL_273_DATA
-				DDRSS0_CTL_274_DATA
-				DDRSS0_CTL_275_DATA
-				DDRSS0_CTL_276_DATA
-				DDRSS0_CTL_277_DATA
-				DDRSS0_CTL_278_DATA
-				DDRSS0_CTL_279_DATA
-				DDRSS0_CTL_280_DATA
-				DDRSS0_CTL_281_DATA
-				DDRSS0_CTL_282_DATA
-				DDRSS0_CTL_283_DATA
-				DDRSS0_CTL_284_DATA
-				DDRSS0_CTL_285_DATA
-				DDRSS0_CTL_286_DATA
-				DDRSS0_CTL_287_DATA
-				DDRSS0_CTL_288_DATA
-				DDRSS0_CTL_289_DATA
-				DDRSS0_CTL_290_DATA
-				DDRSS0_CTL_291_DATA
-				DDRSS0_CTL_292_DATA
-				DDRSS0_CTL_293_DATA
-				DDRSS0_CTL_294_DATA
-				DDRSS0_CTL_295_DATA
-				DDRSS0_CTL_296_DATA
-				DDRSS0_CTL_297_DATA
-				DDRSS0_CTL_298_DATA
-				DDRSS0_CTL_299_DATA
-				DDRSS0_CTL_300_DATA
-				DDRSS0_CTL_301_DATA
-				DDRSS0_CTL_302_DATA
-				DDRSS0_CTL_303_DATA
-				DDRSS0_CTL_304_DATA
-				DDRSS0_CTL_305_DATA
-				DDRSS0_CTL_306_DATA
-				DDRSS0_CTL_307_DATA
-				DDRSS0_CTL_308_DATA
-				DDRSS0_CTL_309_DATA
-				DDRSS0_CTL_310_DATA
-				DDRSS0_CTL_311_DATA
-				DDRSS0_CTL_312_DATA
-				DDRSS0_CTL_313_DATA
-				DDRSS0_CTL_314_DATA
-				DDRSS0_CTL_315_DATA
-				DDRSS0_CTL_316_DATA
-				DDRSS0_CTL_317_DATA
-				DDRSS0_CTL_318_DATA
-				DDRSS0_CTL_319_DATA
-				DDRSS0_CTL_320_DATA
-				DDRSS0_CTL_321_DATA
-				DDRSS0_CTL_322_DATA
-				DDRSS0_CTL_323_DATA
-				DDRSS0_CTL_324_DATA
-				DDRSS0_CTL_325_DATA
-				DDRSS0_CTL_326_DATA
-				DDRSS0_CTL_327_DATA
-				DDRSS0_CTL_328_DATA
-				DDRSS0_CTL_329_DATA
-				DDRSS0_CTL_330_DATA
-				DDRSS0_CTL_331_DATA
-				DDRSS0_CTL_332_DATA
-				DDRSS0_CTL_333_DATA
-				DDRSS0_CTL_334_DATA
-				DDRSS0_CTL_335_DATA
-				DDRSS0_CTL_336_DATA
-				DDRSS0_CTL_337_DATA
-				DDRSS0_CTL_338_DATA
-				DDRSS0_CTL_339_DATA
-				DDRSS0_CTL_340_DATA
-				DDRSS0_CTL_341_DATA
-				DDRSS0_CTL_342_DATA
-				DDRSS0_CTL_343_DATA
-				DDRSS0_CTL_344_DATA
-				DDRSS0_CTL_345_DATA
-				DDRSS0_CTL_346_DATA
-				DDRSS0_CTL_347_DATA
-				DDRSS0_CTL_348_DATA
-				DDRSS0_CTL_349_DATA
-				DDRSS0_CTL_350_DATA
-				DDRSS0_CTL_351_DATA
-				DDRSS0_CTL_352_DATA
-				DDRSS0_CTL_353_DATA
-				DDRSS0_CTL_354_DATA
-				DDRSS0_CTL_355_DATA
-				DDRSS0_CTL_356_DATA
-				DDRSS0_CTL_357_DATA
-				DDRSS0_CTL_358_DATA
-				DDRSS0_CTL_359_DATA
-				DDRSS0_CTL_360_DATA
-				DDRSS0_CTL_361_DATA
-				DDRSS0_CTL_362_DATA
-				DDRSS0_CTL_363_DATA
-				DDRSS0_CTL_364_DATA
-				DDRSS0_CTL_365_DATA
-				DDRSS0_CTL_366_DATA
-				DDRSS0_CTL_367_DATA
-				DDRSS0_CTL_368_DATA
-				DDRSS0_CTL_369_DATA
-				DDRSS0_CTL_370_DATA
-				DDRSS0_CTL_371_DATA
-				DDRSS0_CTL_372_DATA
-				DDRSS0_CTL_373_DATA
-				DDRSS0_CTL_374_DATA
-				DDRSS0_CTL_375_DATA
-				DDRSS0_CTL_376_DATA
-				DDRSS0_CTL_377_DATA
-				DDRSS0_CTL_378_DATA
-				DDRSS0_CTL_379_DATA
-				DDRSS0_CTL_380_DATA
-				DDRSS0_CTL_381_DATA
-				DDRSS0_CTL_382_DATA
-				DDRSS0_CTL_383_DATA
-				DDRSS0_CTL_384_DATA
-				DDRSS0_CTL_385_DATA
-				DDRSS0_CTL_386_DATA
-				DDRSS0_CTL_387_DATA
-				DDRSS0_CTL_388_DATA
-				DDRSS0_CTL_389_DATA
-				DDRSS0_CTL_390_DATA
-				DDRSS0_CTL_391_DATA
-				DDRSS0_CTL_392_DATA
-				DDRSS0_CTL_393_DATA
-				DDRSS0_CTL_394_DATA
-				DDRSS0_CTL_395_DATA
-				DDRSS0_CTL_396_DATA
-				DDRSS0_CTL_397_DATA
-				DDRSS0_CTL_398_DATA
-				DDRSS0_CTL_399_DATA
-				DDRSS0_CTL_400_DATA
-				DDRSS0_CTL_401_DATA
-				DDRSS0_CTL_402_DATA
-				DDRSS0_CTL_403_DATA
-				DDRSS0_CTL_404_DATA
-				DDRSS0_CTL_405_DATA
-				DDRSS0_CTL_406_DATA
-				DDRSS0_CTL_407_DATA
-				DDRSS0_CTL_408_DATA
-				DDRSS0_CTL_409_DATA
-				DDRSS0_CTL_410_DATA
-				DDRSS0_CTL_411_DATA
-				DDRSS0_CTL_412_DATA
-				DDRSS0_CTL_413_DATA
-				DDRSS0_CTL_414_DATA
-				DDRSS0_CTL_415_DATA
-				DDRSS0_CTL_416_DATA
-				DDRSS0_CTL_417_DATA
-				DDRSS0_CTL_418_DATA
-				DDRSS0_CTL_419_DATA
-				DDRSS0_CTL_420_DATA
-				DDRSS0_CTL_421_DATA
-				DDRSS0_CTL_422_DATA
-				DDRSS0_CTL_423_DATA
-				DDRSS0_CTL_424_DATA
-				DDRSS0_CTL_425_DATA
-				DDRSS0_CTL_426_DATA
-				DDRSS0_CTL_427_DATA
-				DDRSS0_CTL_428_DATA
-				DDRSS0_CTL_429_DATA
-				DDRSS0_CTL_430_DATA
-				DDRSS0_CTL_431_DATA
-				DDRSS0_CTL_432_DATA
-				DDRSS0_CTL_433_DATA
-				DDRSS0_CTL_434_DATA
-				DDRSS0_CTL_435_DATA
-				DDRSS0_CTL_436_DATA
-				DDRSS0_CTL_437_DATA
-				DDRSS0_CTL_438_DATA
-				DDRSS0_CTL_439_DATA
-				DDRSS0_CTL_440_DATA
-				DDRSS0_CTL_441_DATA
-				DDRSS0_CTL_442_DATA
-				DDRSS0_CTL_443_DATA
-				DDRSS0_CTL_444_DATA
-				DDRSS0_CTL_445_DATA
-				DDRSS0_CTL_446_DATA
-				DDRSS0_CTL_447_DATA
-				DDRSS0_CTL_448_DATA
-				DDRSS0_CTL_449_DATA
-				DDRSS0_CTL_450_DATA
-				DDRSS0_CTL_451_DATA
-				DDRSS0_CTL_452_DATA
-				DDRSS0_CTL_453_DATA
-				DDRSS0_CTL_454_DATA
-				DDRSS0_CTL_455_DATA
-				DDRSS0_CTL_456_DATA
-				DDRSS0_CTL_457_DATA
-				DDRSS0_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS0_PI_00_DATA
-				DDRSS0_PI_01_DATA
-				DDRSS0_PI_02_DATA
-				DDRSS0_PI_03_DATA
-				DDRSS0_PI_04_DATA
-				DDRSS0_PI_05_DATA
-				DDRSS0_PI_06_DATA
-				DDRSS0_PI_07_DATA
-				DDRSS0_PI_08_DATA
-				DDRSS0_PI_09_DATA
-				DDRSS0_PI_10_DATA
-				DDRSS0_PI_11_DATA
-				DDRSS0_PI_12_DATA
-				DDRSS0_PI_13_DATA
-				DDRSS0_PI_14_DATA
-				DDRSS0_PI_15_DATA
-				DDRSS0_PI_16_DATA
-				DDRSS0_PI_17_DATA
-				DDRSS0_PI_18_DATA
-				DDRSS0_PI_19_DATA
-				DDRSS0_PI_20_DATA
-				DDRSS0_PI_21_DATA
-				DDRSS0_PI_22_DATA
-				DDRSS0_PI_23_DATA
-				DDRSS0_PI_24_DATA
-				DDRSS0_PI_25_DATA
-				DDRSS0_PI_26_DATA
-				DDRSS0_PI_27_DATA
-				DDRSS0_PI_28_DATA
-				DDRSS0_PI_29_DATA
-				DDRSS0_PI_30_DATA
-				DDRSS0_PI_31_DATA
-				DDRSS0_PI_32_DATA
-				DDRSS0_PI_33_DATA
-				DDRSS0_PI_34_DATA
-				DDRSS0_PI_35_DATA
-				DDRSS0_PI_36_DATA
-				DDRSS0_PI_37_DATA
-				DDRSS0_PI_38_DATA
-				DDRSS0_PI_39_DATA
-				DDRSS0_PI_40_DATA
-				DDRSS0_PI_41_DATA
-				DDRSS0_PI_42_DATA
-				DDRSS0_PI_43_DATA
-				DDRSS0_PI_44_DATA
-				DDRSS0_PI_45_DATA
-				DDRSS0_PI_46_DATA
-				DDRSS0_PI_47_DATA
-				DDRSS0_PI_48_DATA
-				DDRSS0_PI_49_DATA
-				DDRSS0_PI_50_DATA
-				DDRSS0_PI_51_DATA
-				DDRSS0_PI_52_DATA
-				DDRSS0_PI_53_DATA
-				DDRSS0_PI_54_DATA
-				DDRSS0_PI_55_DATA
-				DDRSS0_PI_56_DATA
-				DDRSS0_PI_57_DATA
-				DDRSS0_PI_58_DATA
-				DDRSS0_PI_59_DATA
-				DDRSS0_PI_60_DATA
-				DDRSS0_PI_61_DATA
-				DDRSS0_PI_62_DATA
-				DDRSS0_PI_63_DATA
-				DDRSS0_PI_64_DATA
-				DDRSS0_PI_65_DATA
-				DDRSS0_PI_66_DATA
-				DDRSS0_PI_67_DATA
-				DDRSS0_PI_68_DATA
-				DDRSS0_PI_69_DATA
-				DDRSS0_PI_70_DATA
-				DDRSS0_PI_71_DATA
-				DDRSS0_PI_72_DATA
-				DDRSS0_PI_73_DATA
-				DDRSS0_PI_74_DATA
-				DDRSS0_PI_75_DATA
-				DDRSS0_PI_76_DATA
-				DDRSS0_PI_77_DATA
-				DDRSS0_PI_78_DATA
-				DDRSS0_PI_79_DATA
-				DDRSS0_PI_80_DATA
-				DDRSS0_PI_81_DATA
-				DDRSS0_PI_82_DATA
-				DDRSS0_PI_83_DATA
-				DDRSS0_PI_84_DATA
-				DDRSS0_PI_85_DATA
-				DDRSS0_PI_86_DATA
-				DDRSS0_PI_87_DATA
-				DDRSS0_PI_88_DATA
-				DDRSS0_PI_89_DATA
-				DDRSS0_PI_90_DATA
-				DDRSS0_PI_91_DATA
-				DDRSS0_PI_92_DATA
-				DDRSS0_PI_93_DATA
-				DDRSS0_PI_94_DATA
-				DDRSS0_PI_95_DATA
-				DDRSS0_PI_96_DATA
-				DDRSS0_PI_97_DATA
-				DDRSS0_PI_98_DATA
-				DDRSS0_PI_99_DATA
-				DDRSS0_PI_100_DATA
-				DDRSS0_PI_101_DATA
-				DDRSS0_PI_102_DATA
-				DDRSS0_PI_103_DATA
-				DDRSS0_PI_104_DATA
-				DDRSS0_PI_105_DATA
-				DDRSS0_PI_106_DATA
-				DDRSS0_PI_107_DATA
-				DDRSS0_PI_108_DATA
-				DDRSS0_PI_109_DATA
-				DDRSS0_PI_110_DATA
-				DDRSS0_PI_111_DATA
-				DDRSS0_PI_112_DATA
-				DDRSS0_PI_113_DATA
-				DDRSS0_PI_114_DATA
-				DDRSS0_PI_115_DATA
-				DDRSS0_PI_116_DATA
-				DDRSS0_PI_117_DATA
-				DDRSS0_PI_118_DATA
-				DDRSS0_PI_119_DATA
-				DDRSS0_PI_120_DATA
-				DDRSS0_PI_121_DATA
-				DDRSS0_PI_122_DATA
-				DDRSS0_PI_123_DATA
-				DDRSS0_PI_124_DATA
-				DDRSS0_PI_125_DATA
-				DDRSS0_PI_126_DATA
-				DDRSS0_PI_127_DATA
-				DDRSS0_PI_128_DATA
-				DDRSS0_PI_129_DATA
-				DDRSS0_PI_130_DATA
-				DDRSS0_PI_131_DATA
-				DDRSS0_PI_132_DATA
-				DDRSS0_PI_133_DATA
-				DDRSS0_PI_134_DATA
-				DDRSS0_PI_135_DATA
-				DDRSS0_PI_136_DATA
-				DDRSS0_PI_137_DATA
-				DDRSS0_PI_138_DATA
-				DDRSS0_PI_139_DATA
-				DDRSS0_PI_140_DATA
-				DDRSS0_PI_141_DATA
-				DDRSS0_PI_142_DATA
-				DDRSS0_PI_143_DATA
-				DDRSS0_PI_144_DATA
-				DDRSS0_PI_145_DATA
-				DDRSS0_PI_146_DATA
-				DDRSS0_PI_147_DATA
-				DDRSS0_PI_148_DATA
-				DDRSS0_PI_149_DATA
-				DDRSS0_PI_150_DATA
-				DDRSS0_PI_151_DATA
-				DDRSS0_PI_152_DATA
-				DDRSS0_PI_153_DATA
-				DDRSS0_PI_154_DATA
-				DDRSS0_PI_155_DATA
-				DDRSS0_PI_156_DATA
-				DDRSS0_PI_157_DATA
-				DDRSS0_PI_158_DATA
-				DDRSS0_PI_159_DATA
-				DDRSS0_PI_160_DATA
-				DDRSS0_PI_161_DATA
-				DDRSS0_PI_162_DATA
-				DDRSS0_PI_163_DATA
-				DDRSS0_PI_164_DATA
-				DDRSS0_PI_165_DATA
-				DDRSS0_PI_166_DATA
-				DDRSS0_PI_167_DATA
-				DDRSS0_PI_168_DATA
-				DDRSS0_PI_169_DATA
-				DDRSS0_PI_170_DATA
-				DDRSS0_PI_171_DATA
-				DDRSS0_PI_172_DATA
-				DDRSS0_PI_173_DATA
-				DDRSS0_PI_174_DATA
-				DDRSS0_PI_175_DATA
-				DDRSS0_PI_176_DATA
-				DDRSS0_PI_177_DATA
-				DDRSS0_PI_178_DATA
-				DDRSS0_PI_179_DATA
-				DDRSS0_PI_180_DATA
-				DDRSS0_PI_181_DATA
-				DDRSS0_PI_182_DATA
-				DDRSS0_PI_183_DATA
-				DDRSS0_PI_184_DATA
-				DDRSS0_PI_185_DATA
-				DDRSS0_PI_186_DATA
-				DDRSS0_PI_187_DATA
-				DDRSS0_PI_188_DATA
-				DDRSS0_PI_189_DATA
-				DDRSS0_PI_190_DATA
-				DDRSS0_PI_191_DATA
-				DDRSS0_PI_192_DATA
-				DDRSS0_PI_193_DATA
-				DDRSS0_PI_194_DATA
-				DDRSS0_PI_195_DATA
-				DDRSS0_PI_196_DATA
-				DDRSS0_PI_197_DATA
-				DDRSS0_PI_198_DATA
-				DDRSS0_PI_199_DATA
-				DDRSS0_PI_200_DATA
-				DDRSS0_PI_201_DATA
-				DDRSS0_PI_202_DATA
-				DDRSS0_PI_203_DATA
-				DDRSS0_PI_204_DATA
-				DDRSS0_PI_205_DATA
-				DDRSS0_PI_206_DATA
-				DDRSS0_PI_207_DATA
-				DDRSS0_PI_208_DATA
-				DDRSS0_PI_209_DATA
-				DDRSS0_PI_210_DATA
-				DDRSS0_PI_211_DATA
-				DDRSS0_PI_212_DATA
-				DDRSS0_PI_213_DATA
-				DDRSS0_PI_214_DATA
-				DDRSS0_PI_215_DATA
-				DDRSS0_PI_216_DATA
-				DDRSS0_PI_217_DATA
-				DDRSS0_PI_218_DATA
-				DDRSS0_PI_219_DATA
-				DDRSS0_PI_220_DATA
-				DDRSS0_PI_221_DATA
-				DDRSS0_PI_222_DATA
-				DDRSS0_PI_223_DATA
-				DDRSS0_PI_224_DATA
-				DDRSS0_PI_225_DATA
-				DDRSS0_PI_226_DATA
-				DDRSS0_PI_227_DATA
-				DDRSS0_PI_228_DATA
-				DDRSS0_PI_229_DATA
-				DDRSS0_PI_230_DATA
-				DDRSS0_PI_231_DATA
-				DDRSS0_PI_232_DATA
-				DDRSS0_PI_233_DATA
-				DDRSS0_PI_234_DATA
-				DDRSS0_PI_235_DATA
-				DDRSS0_PI_236_DATA
-				DDRSS0_PI_237_DATA
-				DDRSS0_PI_238_DATA
-				DDRSS0_PI_239_DATA
-				DDRSS0_PI_240_DATA
-				DDRSS0_PI_241_DATA
-				DDRSS0_PI_242_DATA
-				DDRSS0_PI_243_DATA
-				DDRSS0_PI_244_DATA
-				DDRSS0_PI_245_DATA
-				DDRSS0_PI_246_DATA
-				DDRSS0_PI_247_DATA
-				DDRSS0_PI_248_DATA
-				DDRSS0_PI_249_DATA
-				DDRSS0_PI_250_DATA
-				DDRSS0_PI_251_DATA
-				DDRSS0_PI_252_DATA
-				DDRSS0_PI_253_DATA
-				DDRSS0_PI_254_DATA
-				DDRSS0_PI_255_DATA
-				DDRSS0_PI_256_DATA
-				DDRSS0_PI_257_DATA
-				DDRSS0_PI_258_DATA
-				DDRSS0_PI_259_DATA
-				DDRSS0_PI_260_DATA
-				DDRSS0_PI_261_DATA
-				DDRSS0_PI_262_DATA
-				DDRSS0_PI_263_DATA
-				DDRSS0_PI_264_DATA
-				DDRSS0_PI_265_DATA
-				DDRSS0_PI_266_DATA
-				DDRSS0_PI_267_DATA
-				DDRSS0_PI_268_DATA
-				DDRSS0_PI_269_DATA
-				DDRSS0_PI_270_DATA
-				DDRSS0_PI_271_DATA
-				DDRSS0_PI_272_DATA
-				DDRSS0_PI_273_DATA
-				DDRSS0_PI_274_DATA
-				DDRSS0_PI_275_DATA
-				DDRSS0_PI_276_DATA
-				DDRSS0_PI_277_DATA
-				DDRSS0_PI_278_DATA
-				DDRSS0_PI_279_DATA
-				DDRSS0_PI_280_DATA
-				DDRSS0_PI_281_DATA
-				DDRSS0_PI_282_DATA
-				DDRSS0_PI_283_DATA
-				DDRSS0_PI_284_DATA
-				DDRSS0_PI_285_DATA
-				DDRSS0_PI_286_DATA
-				DDRSS0_PI_287_DATA
-				DDRSS0_PI_288_DATA
-				DDRSS0_PI_289_DATA
-				DDRSS0_PI_290_DATA
-				DDRSS0_PI_291_DATA
-				DDRSS0_PI_292_DATA
-				DDRSS0_PI_293_DATA
-				DDRSS0_PI_294_DATA
-				DDRSS0_PI_295_DATA
-				DDRSS0_PI_296_DATA
-				DDRSS0_PI_297_DATA
-				DDRSS0_PI_298_DATA
-				DDRSS0_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS0_PHY_00_DATA
-				DDRSS0_PHY_01_DATA
-				DDRSS0_PHY_02_DATA
-				DDRSS0_PHY_03_DATA
-				DDRSS0_PHY_04_DATA
-				DDRSS0_PHY_05_DATA
-				DDRSS0_PHY_06_DATA
-				DDRSS0_PHY_07_DATA
-				DDRSS0_PHY_08_DATA
-				DDRSS0_PHY_09_DATA
-				DDRSS0_PHY_10_DATA
-				DDRSS0_PHY_11_DATA
-				DDRSS0_PHY_12_DATA
-				DDRSS0_PHY_13_DATA
-				DDRSS0_PHY_14_DATA
-				DDRSS0_PHY_15_DATA
-				DDRSS0_PHY_16_DATA
-				DDRSS0_PHY_17_DATA
-				DDRSS0_PHY_18_DATA
-				DDRSS0_PHY_19_DATA
-				DDRSS0_PHY_20_DATA
-				DDRSS0_PHY_21_DATA
-				DDRSS0_PHY_22_DATA
-				DDRSS0_PHY_23_DATA
-				DDRSS0_PHY_24_DATA
-				DDRSS0_PHY_25_DATA
-				DDRSS0_PHY_26_DATA
-				DDRSS0_PHY_27_DATA
-				DDRSS0_PHY_28_DATA
-				DDRSS0_PHY_29_DATA
-				DDRSS0_PHY_30_DATA
-				DDRSS0_PHY_31_DATA
-				DDRSS0_PHY_32_DATA
-				DDRSS0_PHY_33_DATA
-				DDRSS0_PHY_34_DATA
-				DDRSS0_PHY_35_DATA
-				DDRSS0_PHY_36_DATA
-				DDRSS0_PHY_37_DATA
-				DDRSS0_PHY_38_DATA
-				DDRSS0_PHY_39_DATA
-				DDRSS0_PHY_40_DATA
-				DDRSS0_PHY_41_DATA
-				DDRSS0_PHY_42_DATA
-				DDRSS0_PHY_43_DATA
-				DDRSS0_PHY_44_DATA
-				DDRSS0_PHY_45_DATA
-				DDRSS0_PHY_46_DATA
-				DDRSS0_PHY_47_DATA
-				DDRSS0_PHY_48_DATA
-				DDRSS0_PHY_49_DATA
-				DDRSS0_PHY_50_DATA
-				DDRSS0_PHY_51_DATA
-				DDRSS0_PHY_52_DATA
-				DDRSS0_PHY_53_DATA
-				DDRSS0_PHY_54_DATA
-				DDRSS0_PHY_55_DATA
-				DDRSS0_PHY_56_DATA
-				DDRSS0_PHY_57_DATA
-				DDRSS0_PHY_58_DATA
-				DDRSS0_PHY_59_DATA
-				DDRSS0_PHY_60_DATA
-				DDRSS0_PHY_61_DATA
-				DDRSS0_PHY_62_DATA
-				DDRSS0_PHY_63_DATA
-				DDRSS0_PHY_64_DATA
-				DDRSS0_PHY_65_DATA
-				DDRSS0_PHY_66_DATA
-				DDRSS0_PHY_67_DATA
-				DDRSS0_PHY_68_DATA
-				DDRSS0_PHY_69_DATA
-				DDRSS0_PHY_70_DATA
-				DDRSS0_PHY_71_DATA
-				DDRSS0_PHY_72_DATA
-				DDRSS0_PHY_73_DATA
-				DDRSS0_PHY_74_DATA
-				DDRSS0_PHY_75_DATA
-				DDRSS0_PHY_76_DATA
-				DDRSS0_PHY_77_DATA
-				DDRSS0_PHY_78_DATA
-				DDRSS0_PHY_79_DATA
-				DDRSS0_PHY_80_DATA
-				DDRSS0_PHY_81_DATA
-				DDRSS0_PHY_82_DATA
-				DDRSS0_PHY_83_DATA
-				DDRSS0_PHY_84_DATA
-				DDRSS0_PHY_85_DATA
-				DDRSS0_PHY_86_DATA
-				DDRSS0_PHY_87_DATA
-				DDRSS0_PHY_88_DATA
-				DDRSS0_PHY_89_DATA
-				DDRSS0_PHY_90_DATA
-				DDRSS0_PHY_91_DATA
-				DDRSS0_PHY_92_DATA
-				DDRSS0_PHY_93_DATA
-				DDRSS0_PHY_94_DATA
-				DDRSS0_PHY_95_DATA
-				DDRSS0_PHY_96_DATA
-				DDRSS0_PHY_97_DATA
-				DDRSS0_PHY_98_DATA
-				DDRSS0_PHY_99_DATA
-				DDRSS0_PHY_100_DATA
-				DDRSS0_PHY_101_DATA
-				DDRSS0_PHY_102_DATA
-				DDRSS0_PHY_103_DATA
-				DDRSS0_PHY_104_DATA
-				DDRSS0_PHY_105_DATA
-				DDRSS0_PHY_106_DATA
-				DDRSS0_PHY_107_DATA
-				DDRSS0_PHY_108_DATA
-				DDRSS0_PHY_109_DATA
-				DDRSS0_PHY_110_DATA
-				DDRSS0_PHY_111_DATA
-				DDRSS0_PHY_112_DATA
-				DDRSS0_PHY_113_DATA
-				DDRSS0_PHY_114_DATA
-				DDRSS0_PHY_115_DATA
-				DDRSS0_PHY_116_DATA
-				DDRSS0_PHY_117_DATA
-				DDRSS0_PHY_118_DATA
-				DDRSS0_PHY_119_DATA
-				DDRSS0_PHY_120_DATA
-				DDRSS0_PHY_121_DATA
-				DDRSS0_PHY_122_DATA
-				DDRSS0_PHY_123_DATA
-				DDRSS0_PHY_124_DATA
-				DDRSS0_PHY_125_DATA
-				DDRSS0_PHY_126_DATA
-				DDRSS0_PHY_127_DATA
-				DDRSS0_PHY_128_DATA
-				DDRSS0_PHY_129_DATA
-				DDRSS0_PHY_130_DATA
-				DDRSS0_PHY_131_DATA
-				DDRSS0_PHY_132_DATA
-				DDRSS0_PHY_133_DATA
-				DDRSS0_PHY_134_DATA
-				DDRSS0_PHY_135_DATA
-				DDRSS0_PHY_136_DATA
-				DDRSS0_PHY_137_DATA
-				DDRSS0_PHY_138_DATA
-				DDRSS0_PHY_139_DATA
-				DDRSS0_PHY_140_DATA
-				DDRSS0_PHY_141_DATA
-				DDRSS0_PHY_142_DATA
-				DDRSS0_PHY_143_DATA
-				DDRSS0_PHY_144_DATA
-				DDRSS0_PHY_145_DATA
-				DDRSS0_PHY_146_DATA
-				DDRSS0_PHY_147_DATA
-				DDRSS0_PHY_148_DATA
-				DDRSS0_PHY_149_DATA
-				DDRSS0_PHY_150_DATA
-				DDRSS0_PHY_151_DATA
-				DDRSS0_PHY_152_DATA
-				DDRSS0_PHY_153_DATA
-				DDRSS0_PHY_154_DATA
-				DDRSS0_PHY_155_DATA
-				DDRSS0_PHY_156_DATA
-				DDRSS0_PHY_157_DATA
-				DDRSS0_PHY_158_DATA
-				DDRSS0_PHY_159_DATA
-				DDRSS0_PHY_160_DATA
-				DDRSS0_PHY_161_DATA
-				DDRSS0_PHY_162_DATA
-				DDRSS0_PHY_163_DATA
-				DDRSS0_PHY_164_DATA
-				DDRSS0_PHY_165_DATA
-				DDRSS0_PHY_166_DATA
-				DDRSS0_PHY_167_DATA
-				DDRSS0_PHY_168_DATA
-				DDRSS0_PHY_169_DATA
-				DDRSS0_PHY_170_DATA
-				DDRSS0_PHY_171_DATA
-				DDRSS0_PHY_172_DATA
-				DDRSS0_PHY_173_DATA
-				DDRSS0_PHY_174_DATA
-				DDRSS0_PHY_175_DATA
-				DDRSS0_PHY_176_DATA
-				DDRSS0_PHY_177_DATA
-				DDRSS0_PHY_178_DATA
-				DDRSS0_PHY_179_DATA
-				DDRSS0_PHY_180_DATA
-				DDRSS0_PHY_181_DATA
-				DDRSS0_PHY_182_DATA
-				DDRSS0_PHY_183_DATA
-				DDRSS0_PHY_184_DATA
-				DDRSS0_PHY_185_DATA
-				DDRSS0_PHY_186_DATA
-				DDRSS0_PHY_187_DATA
-				DDRSS0_PHY_188_DATA
-				DDRSS0_PHY_189_DATA
-				DDRSS0_PHY_190_DATA
-				DDRSS0_PHY_191_DATA
-				DDRSS0_PHY_192_DATA
-				DDRSS0_PHY_193_DATA
-				DDRSS0_PHY_194_DATA
-				DDRSS0_PHY_195_DATA
-				DDRSS0_PHY_196_DATA
-				DDRSS0_PHY_197_DATA
-				DDRSS0_PHY_198_DATA
-				DDRSS0_PHY_199_DATA
-				DDRSS0_PHY_200_DATA
-				DDRSS0_PHY_201_DATA
-				DDRSS0_PHY_202_DATA
-				DDRSS0_PHY_203_DATA
-				DDRSS0_PHY_204_DATA
-				DDRSS0_PHY_205_DATA
-				DDRSS0_PHY_206_DATA
-				DDRSS0_PHY_207_DATA
-				DDRSS0_PHY_208_DATA
-				DDRSS0_PHY_209_DATA
-				DDRSS0_PHY_210_DATA
-				DDRSS0_PHY_211_DATA
-				DDRSS0_PHY_212_DATA
-				DDRSS0_PHY_213_DATA
-				DDRSS0_PHY_214_DATA
-				DDRSS0_PHY_215_DATA
-				DDRSS0_PHY_216_DATA
-				DDRSS0_PHY_217_DATA
-				DDRSS0_PHY_218_DATA
-				DDRSS0_PHY_219_DATA
-				DDRSS0_PHY_220_DATA
-				DDRSS0_PHY_221_DATA
-				DDRSS0_PHY_222_DATA
-				DDRSS0_PHY_223_DATA
-				DDRSS0_PHY_224_DATA
-				DDRSS0_PHY_225_DATA
-				DDRSS0_PHY_226_DATA
-				DDRSS0_PHY_227_DATA
-				DDRSS0_PHY_228_DATA
-				DDRSS0_PHY_229_DATA
-				DDRSS0_PHY_230_DATA
-				DDRSS0_PHY_231_DATA
-				DDRSS0_PHY_232_DATA
-				DDRSS0_PHY_233_DATA
-				DDRSS0_PHY_234_DATA
-				DDRSS0_PHY_235_DATA
-				DDRSS0_PHY_236_DATA
-				DDRSS0_PHY_237_DATA
-				DDRSS0_PHY_238_DATA
-				DDRSS0_PHY_239_DATA
-				DDRSS0_PHY_240_DATA
-				DDRSS0_PHY_241_DATA
-				DDRSS0_PHY_242_DATA
-				DDRSS0_PHY_243_DATA
-				DDRSS0_PHY_244_DATA
-				DDRSS0_PHY_245_DATA
-				DDRSS0_PHY_246_DATA
-				DDRSS0_PHY_247_DATA
-				DDRSS0_PHY_248_DATA
-				DDRSS0_PHY_249_DATA
-				DDRSS0_PHY_250_DATA
-				DDRSS0_PHY_251_DATA
-				DDRSS0_PHY_252_DATA
-				DDRSS0_PHY_253_DATA
-				DDRSS0_PHY_254_DATA
-				DDRSS0_PHY_255_DATA
-				DDRSS0_PHY_256_DATA
-				DDRSS0_PHY_257_DATA
-				DDRSS0_PHY_258_DATA
-				DDRSS0_PHY_259_DATA
-				DDRSS0_PHY_260_DATA
-				DDRSS0_PHY_261_DATA
-				DDRSS0_PHY_262_DATA
-				DDRSS0_PHY_263_DATA
-				DDRSS0_PHY_264_DATA
-				DDRSS0_PHY_265_DATA
-				DDRSS0_PHY_266_DATA
-				DDRSS0_PHY_267_DATA
-				DDRSS0_PHY_268_DATA
-				DDRSS0_PHY_269_DATA
-				DDRSS0_PHY_270_DATA
-				DDRSS0_PHY_271_DATA
-				DDRSS0_PHY_272_DATA
-				DDRSS0_PHY_273_DATA
-				DDRSS0_PHY_274_DATA
-				DDRSS0_PHY_275_DATA
-				DDRSS0_PHY_276_DATA
-				DDRSS0_PHY_277_DATA
-				DDRSS0_PHY_278_DATA
-				DDRSS0_PHY_279_DATA
-				DDRSS0_PHY_280_DATA
-				DDRSS0_PHY_281_DATA
-				DDRSS0_PHY_282_DATA
-				DDRSS0_PHY_283_DATA
-				DDRSS0_PHY_284_DATA
-				DDRSS0_PHY_285_DATA
-				DDRSS0_PHY_286_DATA
-				DDRSS0_PHY_287_DATA
-				DDRSS0_PHY_288_DATA
-				DDRSS0_PHY_289_DATA
-				DDRSS0_PHY_290_DATA
-				DDRSS0_PHY_291_DATA
-				DDRSS0_PHY_292_DATA
-				DDRSS0_PHY_293_DATA
-				DDRSS0_PHY_294_DATA
-				DDRSS0_PHY_295_DATA
-				DDRSS0_PHY_296_DATA
-				DDRSS0_PHY_297_DATA
-				DDRSS0_PHY_298_DATA
-				DDRSS0_PHY_299_DATA
-				DDRSS0_PHY_300_DATA
-				DDRSS0_PHY_301_DATA
-				DDRSS0_PHY_302_DATA
-				DDRSS0_PHY_303_DATA
-				DDRSS0_PHY_304_DATA
-				DDRSS0_PHY_305_DATA
-				DDRSS0_PHY_306_DATA
-				DDRSS0_PHY_307_DATA
-				DDRSS0_PHY_308_DATA
-				DDRSS0_PHY_309_DATA
-				DDRSS0_PHY_310_DATA
-				DDRSS0_PHY_311_DATA
-				DDRSS0_PHY_312_DATA
-				DDRSS0_PHY_313_DATA
-				DDRSS0_PHY_314_DATA
-				DDRSS0_PHY_315_DATA
-				DDRSS0_PHY_316_DATA
-				DDRSS0_PHY_317_DATA
-				DDRSS0_PHY_318_DATA
-				DDRSS0_PHY_319_DATA
-				DDRSS0_PHY_320_DATA
-				DDRSS0_PHY_321_DATA
-				DDRSS0_PHY_322_DATA
-				DDRSS0_PHY_323_DATA
-				DDRSS0_PHY_324_DATA
-				DDRSS0_PHY_325_DATA
-				DDRSS0_PHY_326_DATA
-				DDRSS0_PHY_327_DATA
-				DDRSS0_PHY_328_DATA
-				DDRSS0_PHY_329_DATA
-				DDRSS0_PHY_330_DATA
-				DDRSS0_PHY_331_DATA
-				DDRSS0_PHY_332_DATA
-				DDRSS0_PHY_333_DATA
-				DDRSS0_PHY_334_DATA
-				DDRSS0_PHY_335_DATA
-				DDRSS0_PHY_336_DATA
-				DDRSS0_PHY_337_DATA
-				DDRSS0_PHY_338_DATA
-				DDRSS0_PHY_339_DATA
-				DDRSS0_PHY_340_DATA
-				DDRSS0_PHY_341_DATA
-				DDRSS0_PHY_342_DATA
-				DDRSS0_PHY_343_DATA
-				DDRSS0_PHY_344_DATA
-				DDRSS0_PHY_345_DATA
-				DDRSS0_PHY_346_DATA
-				DDRSS0_PHY_347_DATA
-				DDRSS0_PHY_348_DATA
-				DDRSS0_PHY_349_DATA
-				DDRSS0_PHY_350_DATA
-				DDRSS0_PHY_351_DATA
-				DDRSS0_PHY_352_DATA
-				DDRSS0_PHY_353_DATA
-				DDRSS0_PHY_354_DATA
-				DDRSS0_PHY_355_DATA
-				DDRSS0_PHY_356_DATA
-				DDRSS0_PHY_357_DATA
-				DDRSS0_PHY_358_DATA
-				DDRSS0_PHY_359_DATA
-				DDRSS0_PHY_360_DATA
-				DDRSS0_PHY_361_DATA
-				DDRSS0_PHY_362_DATA
-				DDRSS0_PHY_363_DATA
-				DDRSS0_PHY_364_DATA
-				DDRSS0_PHY_365_DATA
-				DDRSS0_PHY_366_DATA
-				DDRSS0_PHY_367_DATA
-				DDRSS0_PHY_368_DATA
-				DDRSS0_PHY_369_DATA
-				DDRSS0_PHY_370_DATA
-				DDRSS0_PHY_371_DATA
-				DDRSS0_PHY_372_DATA
-				DDRSS0_PHY_373_DATA
-				DDRSS0_PHY_374_DATA
-				DDRSS0_PHY_375_DATA
-				DDRSS0_PHY_376_DATA
-				DDRSS0_PHY_377_DATA
-				DDRSS0_PHY_378_DATA
-				DDRSS0_PHY_379_DATA
-				DDRSS0_PHY_380_DATA
-				DDRSS0_PHY_381_DATA
-				DDRSS0_PHY_382_DATA
-				DDRSS0_PHY_383_DATA
-				DDRSS0_PHY_384_DATA
-				DDRSS0_PHY_385_DATA
-				DDRSS0_PHY_386_DATA
-				DDRSS0_PHY_387_DATA
-				DDRSS0_PHY_388_DATA
-				DDRSS0_PHY_389_DATA
-				DDRSS0_PHY_390_DATA
-				DDRSS0_PHY_391_DATA
-				DDRSS0_PHY_392_DATA
-				DDRSS0_PHY_393_DATA
-				DDRSS0_PHY_394_DATA
-				DDRSS0_PHY_395_DATA
-				DDRSS0_PHY_396_DATA
-				DDRSS0_PHY_397_DATA
-				DDRSS0_PHY_398_DATA
-				DDRSS0_PHY_399_DATA
-				DDRSS0_PHY_400_DATA
-				DDRSS0_PHY_401_DATA
-				DDRSS0_PHY_402_DATA
-				DDRSS0_PHY_403_DATA
-				DDRSS0_PHY_404_DATA
-				DDRSS0_PHY_405_DATA
-				DDRSS0_PHY_406_DATA
-				DDRSS0_PHY_407_DATA
-				DDRSS0_PHY_408_DATA
-				DDRSS0_PHY_409_DATA
-				DDRSS0_PHY_410_DATA
-				DDRSS0_PHY_411_DATA
-				DDRSS0_PHY_412_DATA
-				DDRSS0_PHY_413_DATA
-				DDRSS0_PHY_414_DATA
-				DDRSS0_PHY_415_DATA
-				DDRSS0_PHY_416_DATA
-				DDRSS0_PHY_417_DATA
-				DDRSS0_PHY_418_DATA
-				DDRSS0_PHY_419_DATA
-				DDRSS0_PHY_420_DATA
-				DDRSS0_PHY_421_DATA
-				DDRSS0_PHY_422_DATA
-				DDRSS0_PHY_423_DATA
-				DDRSS0_PHY_424_DATA
-				DDRSS0_PHY_425_DATA
-				DDRSS0_PHY_426_DATA
-				DDRSS0_PHY_427_DATA
-				DDRSS0_PHY_428_DATA
-				DDRSS0_PHY_429_DATA
-				DDRSS0_PHY_430_DATA
-				DDRSS0_PHY_431_DATA
-				DDRSS0_PHY_432_DATA
-				DDRSS0_PHY_433_DATA
-				DDRSS0_PHY_434_DATA
-				DDRSS0_PHY_435_DATA
-				DDRSS0_PHY_436_DATA
-				DDRSS0_PHY_437_DATA
-				DDRSS0_PHY_438_DATA
-				DDRSS0_PHY_439_DATA
-				DDRSS0_PHY_440_DATA
-				DDRSS0_PHY_441_DATA
-				DDRSS0_PHY_442_DATA
-				DDRSS0_PHY_443_DATA
-				DDRSS0_PHY_444_DATA
-				DDRSS0_PHY_445_DATA
-				DDRSS0_PHY_446_DATA
-				DDRSS0_PHY_447_DATA
-				DDRSS0_PHY_448_DATA
-				DDRSS0_PHY_449_DATA
-				DDRSS0_PHY_450_DATA
-				DDRSS0_PHY_451_DATA
-				DDRSS0_PHY_452_DATA
-				DDRSS0_PHY_453_DATA
-				DDRSS0_PHY_454_DATA
-				DDRSS0_PHY_455_DATA
-				DDRSS0_PHY_456_DATA
-				DDRSS0_PHY_457_DATA
-				DDRSS0_PHY_458_DATA
-				DDRSS0_PHY_459_DATA
-				DDRSS0_PHY_460_DATA
-				DDRSS0_PHY_461_DATA
-				DDRSS0_PHY_462_DATA
-				DDRSS0_PHY_463_DATA
-				DDRSS0_PHY_464_DATA
-				DDRSS0_PHY_465_DATA
-				DDRSS0_PHY_466_DATA
-				DDRSS0_PHY_467_DATA
-				DDRSS0_PHY_468_DATA
-				DDRSS0_PHY_469_DATA
-				DDRSS0_PHY_470_DATA
-				DDRSS0_PHY_471_DATA
-				DDRSS0_PHY_472_DATA
-				DDRSS0_PHY_473_DATA
-				DDRSS0_PHY_474_DATA
-				DDRSS0_PHY_475_DATA
-				DDRSS0_PHY_476_DATA
-				DDRSS0_PHY_477_DATA
-				DDRSS0_PHY_478_DATA
-				DDRSS0_PHY_479_DATA
-				DDRSS0_PHY_480_DATA
-				DDRSS0_PHY_481_DATA
-				DDRSS0_PHY_482_DATA
-				DDRSS0_PHY_483_DATA
-				DDRSS0_PHY_484_DATA
-				DDRSS0_PHY_485_DATA
-				DDRSS0_PHY_486_DATA
-				DDRSS0_PHY_487_DATA
-				DDRSS0_PHY_488_DATA
-				DDRSS0_PHY_489_DATA
-				DDRSS0_PHY_490_DATA
-				DDRSS0_PHY_491_DATA
-				DDRSS0_PHY_492_DATA
-				DDRSS0_PHY_493_DATA
-				DDRSS0_PHY_494_DATA
-				DDRSS0_PHY_495_DATA
-				DDRSS0_PHY_496_DATA
-				DDRSS0_PHY_497_DATA
-				DDRSS0_PHY_498_DATA
-				DDRSS0_PHY_499_DATA
-				DDRSS0_PHY_500_DATA
-				DDRSS0_PHY_501_DATA
-				DDRSS0_PHY_502_DATA
-				DDRSS0_PHY_503_DATA
-				DDRSS0_PHY_504_DATA
-				DDRSS0_PHY_505_DATA
-				DDRSS0_PHY_506_DATA
-				DDRSS0_PHY_507_DATA
-				DDRSS0_PHY_508_DATA
-				DDRSS0_PHY_509_DATA
-				DDRSS0_PHY_510_DATA
-				DDRSS0_PHY_511_DATA
-				DDRSS0_PHY_512_DATA
-				DDRSS0_PHY_513_DATA
-				DDRSS0_PHY_514_DATA
-				DDRSS0_PHY_515_DATA
-				DDRSS0_PHY_516_DATA
-				DDRSS0_PHY_517_DATA
-				DDRSS0_PHY_518_DATA
-				DDRSS0_PHY_519_DATA
-				DDRSS0_PHY_520_DATA
-				DDRSS0_PHY_521_DATA
-				DDRSS0_PHY_522_DATA
-				DDRSS0_PHY_523_DATA
-				DDRSS0_PHY_524_DATA
-				DDRSS0_PHY_525_DATA
-				DDRSS0_PHY_526_DATA
-				DDRSS0_PHY_527_DATA
-				DDRSS0_PHY_528_DATA
-				DDRSS0_PHY_529_DATA
-				DDRSS0_PHY_530_DATA
-				DDRSS0_PHY_531_DATA
-				DDRSS0_PHY_532_DATA
-				DDRSS0_PHY_533_DATA
-				DDRSS0_PHY_534_DATA
-				DDRSS0_PHY_535_DATA
-				DDRSS0_PHY_536_DATA
-				DDRSS0_PHY_537_DATA
-				DDRSS0_PHY_538_DATA
-				DDRSS0_PHY_539_DATA
-				DDRSS0_PHY_540_DATA
-				DDRSS0_PHY_541_DATA
-				DDRSS0_PHY_542_DATA
-				DDRSS0_PHY_543_DATA
-				DDRSS0_PHY_544_DATA
-				DDRSS0_PHY_545_DATA
-				DDRSS0_PHY_546_DATA
-				DDRSS0_PHY_547_DATA
-				DDRSS0_PHY_548_DATA
-				DDRSS0_PHY_549_DATA
-				DDRSS0_PHY_550_DATA
-				DDRSS0_PHY_551_DATA
-				DDRSS0_PHY_552_DATA
-				DDRSS0_PHY_553_DATA
-				DDRSS0_PHY_554_DATA
-				DDRSS0_PHY_555_DATA
-				DDRSS0_PHY_556_DATA
-				DDRSS0_PHY_557_DATA
-				DDRSS0_PHY_558_DATA
-				DDRSS0_PHY_559_DATA
-				DDRSS0_PHY_560_DATA
-				DDRSS0_PHY_561_DATA
-				DDRSS0_PHY_562_DATA
-				DDRSS0_PHY_563_DATA
-				DDRSS0_PHY_564_DATA
-				DDRSS0_PHY_565_DATA
-				DDRSS0_PHY_566_DATA
-				DDRSS0_PHY_567_DATA
-				DDRSS0_PHY_568_DATA
-				DDRSS0_PHY_569_DATA
-				DDRSS0_PHY_570_DATA
-				DDRSS0_PHY_571_DATA
-				DDRSS0_PHY_572_DATA
-				DDRSS0_PHY_573_DATA
-				DDRSS0_PHY_574_DATA
-				DDRSS0_PHY_575_DATA
-				DDRSS0_PHY_576_DATA
-				DDRSS0_PHY_577_DATA
-				DDRSS0_PHY_578_DATA
-				DDRSS0_PHY_579_DATA
-				DDRSS0_PHY_580_DATA
-				DDRSS0_PHY_581_DATA
-				DDRSS0_PHY_582_DATA
-				DDRSS0_PHY_583_DATA
-				DDRSS0_PHY_584_DATA
-				DDRSS0_PHY_585_DATA
-				DDRSS0_PHY_586_DATA
-				DDRSS0_PHY_587_DATA
-				DDRSS0_PHY_588_DATA
-				DDRSS0_PHY_589_DATA
-				DDRSS0_PHY_590_DATA
-				DDRSS0_PHY_591_DATA
-				DDRSS0_PHY_592_DATA
-				DDRSS0_PHY_593_DATA
-				DDRSS0_PHY_594_DATA
-				DDRSS0_PHY_595_DATA
-				DDRSS0_PHY_596_DATA
-				DDRSS0_PHY_597_DATA
-				DDRSS0_PHY_598_DATA
-				DDRSS0_PHY_599_DATA
-				DDRSS0_PHY_600_DATA
-				DDRSS0_PHY_601_DATA
-				DDRSS0_PHY_602_DATA
-				DDRSS0_PHY_603_DATA
-				DDRSS0_PHY_604_DATA
-				DDRSS0_PHY_605_DATA
-				DDRSS0_PHY_606_DATA
-				DDRSS0_PHY_607_DATA
-				DDRSS0_PHY_608_DATA
-				DDRSS0_PHY_609_DATA
-				DDRSS0_PHY_610_DATA
-				DDRSS0_PHY_611_DATA
-				DDRSS0_PHY_612_DATA
-				DDRSS0_PHY_613_DATA
-				DDRSS0_PHY_614_DATA
-				DDRSS0_PHY_615_DATA
-				DDRSS0_PHY_616_DATA
-				DDRSS0_PHY_617_DATA
-				DDRSS0_PHY_618_DATA
-				DDRSS0_PHY_619_DATA
-				DDRSS0_PHY_620_DATA
-				DDRSS0_PHY_621_DATA
-				DDRSS0_PHY_622_DATA
-				DDRSS0_PHY_623_DATA
-				DDRSS0_PHY_624_DATA
-				DDRSS0_PHY_625_DATA
-				DDRSS0_PHY_626_DATA
-				DDRSS0_PHY_627_DATA
-				DDRSS0_PHY_628_DATA
-				DDRSS0_PHY_629_DATA
-				DDRSS0_PHY_630_DATA
-				DDRSS0_PHY_631_DATA
-				DDRSS0_PHY_632_DATA
-				DDRSS0_PHY_633_DATA
-				DDRSS0_PHY_634_DATA
-				DDRSS0_PHY_635_DATA
-				DDRSS0_PHY_636_DATA
-				DDRSS0_PHY_637_DATA
-				DDRSS0_PHY_638_DATA
-				DDRSS0_PHY_639_DATA
-				DDRSS0_PHY_640_DATA
-				DDRSS0_PHY_641_DATA
-				DDRSS0_PHY_642_DATA
-				DDRSS0_PHY_643_DATA
-				DDRSS0_PHY_644_DATA
-				DDRSS0_PHY_645_DATA
-				DDRSS0_PHY_646_DATA
-				DDRSS0_PHY_647_DATA
-				DDRSS0_PHY_648_DATA
-				DDRSS0_PHY_649_DATA
-				DDRSS0_PHY_650_DATA
-				DDRSS0_PHY_651_DATA
-				DDRSS0_PHY_652_DATA
-				DDRSS0_PHY_653_DATA
-				DDRSS0_PHY_654_DATA
-				DDRSS0_PHY_655_DATA
-				DDRSS0_PHY_656_DATA
-				DDRSS0_PHY_657_DATA
-				DDRSS0_PHY_658_DATA
-				DDRSS0_PHY_659_DATA
-				DDRSS0_PHY_660_DATA
-				DDRSS0_PHY_661_DATA
-				DDRSS0_PHY_662_DATA
-				DDRSS0_PHY_663_DATA
-				DDRSS0_PHY_664_DATA
-				DDRSS0_PHY_665_DATA
-				DDRSS0_PHY_666_DATA
-				DDRSS0_PHY_667_DATA
-				DDRSS0_PHY_668_DATA
-				DDRSS0_PHY_669_DATA
-				DDRSS0_PHY_670_DATA
-				DDRSS0_PHY_671_DATA
-				DDRSS0_PHY_672_DATA
-				DDRSS0_PHY_673_DATA
-				DDRSS0_PHY_674_DATA
-				DDRSS0_PHY_675_DATA
-				DDRSS0_PHY_676_DATA
-				DDRSS0_PHY_677_DATA
-				DDRSS0_PHY_678_DATA
-				DDRSS0_PHY_679_DATA
-				DDRSS0_PHY_680_DATA
-				DDRSS0_PHY_681_DATA
-				DDRSS0_PHY_682_DATA
-				DDRSS0_PHY_683_DATA
-				DDRSS0_PHY_684_DATA
-				DDRSS0_PHY_685_DATA
-				DDRSS0_PHY_686_DATA
-				DDRSS0_PHY_687_DATA
-				DDRSS0_PHY_688_DATA
-				DDRSS0_PHY_689_DATA
-				DDRSS0_PHY_690_DATA
-				DDRSS0_PHY_691_DATA
-				DDRSS0_PHY_692_DATA
-				DDRSS0_PHY_693_DATA
-				DDRSS0_PHY_694_DATA
-				DDRSS0_PHY_695_DATA
-				DDRSS0_PHY_696_DATA
-				DDRSS0_PHY_697_DATA
-				DDRSS0_PHY_698_DATA
-				DDRSS0_PHY_699_DATA
-				DDRSS0_PHY_700_DATA
-				DDRSS0_PHY_701_DATA
-				DDRSS0_PHY_702_DATA
-				DDRSS0_PHY_703_DATA
-				DDRSS0_PHY_704_DATA
-				DDRSS0_PHY_705_DATA
-				DDRSS0_PHY_706_DATA
-				DDRSS0_PHY_707_DATA
-				DDRSS0_PHY_708_DATA
-				DDRSS0_PHY_709_DATA
-				DDRSS0_PHY_710_DATA
-				DDRSS0_PHY_711_DATA
-				DDRSS0_PHY_712_DATA
-				DDRSS0_PHY_713_DATA
-				DDRSS0_PHY_714_DATA
-				DDRSS0_PHY_715_DATA
-				DDRSS0_PHY_716_DATA
-				DDRSS0_PHY_717_DATA
-				DDRSS0_PHY_718_DATA
-				DDRSS0_PHY_719_DATA
-				DDRSS0_PHY_720_DATA
-				DDRSS0_PHY_721_DATA
-				DDRSS0_PHY_722_DATA
-				DDRSS0_PHY_723_DATA
-				DDRSS0_PHY_724_DATA
-				DDRSS0_PHY_725_DATA
-				DDRSS0_PHY_726_DATA
-				DDRSS0_PHY_727_DATA
-				DDRSS0_PHY_728_DATA
-				DDRSS0_PHY_729_DATA
-				DDRSS0_PHY_730_DATA
-				DDRSS0_PHY_731_DATA
-				DDRSS0_PHY_732_DATA
-				DDRSS0_PHY_733_DATA
-				DDRSS0_PHY_734_DATA
-				DDRSS0_PHY_735_DATA
-				DDRSS0_PHY_736_DATA
-				DDRSS0_PHY_737_DATA
-				DDRSS0_PHY_738_DATA
-				DDRSS0_PHY_739_DATA
-				DDRSS0_PHY_740_DATA
-				DDRSS0_PHY_741_DATA
-				DDRSS0_PHY_742_DATA
-				DDRSS0_PHY_743_DATA
-				DDRSS0_PHY_744_DATA
-				DDRSS0_PHY_745_DATA
-				DDRSS0_PHY_746_DATA
-				DDRSS0_PHY_747_DATA
-				DDRSS0_PHY_748_DATA
-				DDRSS0_PHY_749_DATA
-				DDRSS0_PHY_750_DATA
-				DDRSS0_PHY_751_DATA
-				DDRSS0_PHY_752_DATA
-				DDRSS0_PHY_753_DATA
-				DDRSS0_PHY_754_DATA
-				DDRSS0_PHY_755_DATA
-				DDRSS0_PHY_756_DATA
-				DDRSS0_PHY_757_DATA
-				DDRSS0_PHY_758_DATA
-				DDRSS0_PHY_759_DATA
-				DDRSS0_PHY_760_DATA
-				DDRSS0_PHY_761_DATA
-				DDRSS0_PHY_762_DATA
-				DDRSS0_PHY_763_DATA
-				DDRSS0_PHY_764_DATA
-				DDRSS0_PHY_765_DATA
-				DDRSS0_PHY_766_DATA
-				DDRSS0_PHY_767_DATA
-				DDRSS0_PHY_768_DATA
-				DDRSS0_PHY_769_DATA
-				DDRSS0_PHY_770_DATA
-				DDRSS0_PHY_771_DATA
-				DDRSS0_PHY_772_DATA
-				DDRSS0_PHY_773_DATA
-				DDRSS0_PHY_774_DATA
-				DDRSS0_PHY_775_DATA
-				DDRSS0_PHY_776_DATA
-				DDRSS0_PHY_777_DATA
-				DDRSS0_PHY_778_DATA
-				DDRSS0_PHY_779_DATA
-				DDRSS0_PHY_780_DATA
-				DDRSS0_PHY_781_DATA
-				DDRSS0_PHY_782_DATA
-				DDRSS0_PHY_783_DATA
-				DDRSS0_PHY_784_DATA
-				DDRSS0_PHY_785_DATA
-				DDRSS0_PHY_786_DATA
-				DDRSS0_PHY_787_DATA
-				DDRSS0_PHY_788_DATA
-				DDRSS0_PHY_789_DATA
-				DDRSS0_PHY_790_DATA
-				DDRSS0_PHY_791_DATA
-				DDRSS0_PHY_792_DATA
-				DDRSS0_PHY_793_DATA
-				DDRSS0_PHY_794_DATA
-				DDRSS0_PHY_795_DATA
-				DDRSS0_PHY_796_DATA
-				DDRSS0_PHY_797_DATA
-				DDRSS0_PHY_798_DATA
-				DDRSS0_PHY_799_DATA
-				DDRSS0_PHY_800_DATA
-				DDRSS0_PHY_801_DATA
-				DDRSS0_PHY_802_DATA
-				DDRSS0_PHY_803_DATA
-				DDRSS0_PHY_804_DATA
-				DDRSS0_PHY_805_DATA
-				DDRSS0_PHY_806_DATA
-				DDRSS0_PHY_807_DATA
-				DDRSS0_PHY_808_DATA
-				DDRSS0_PHY_809_DATA
-				DDRSS0_PHY_810_DATA
-				DDRSS0_PHY_811_DATA
-				DDRSS0_PHY_812_DATA
-				DDRSS0_PHY_813_DATA
-				DDRSS0_PHY_814_DATA
-				DDRSS0_PHY_815_DATA
-				DDRSS0_PHY_816_DATA
-				DDRSS0_PHY_817_DATA
-				DDRSS0_PHY_818_DATA
-				DDRSS0_PHY_819_DATA
-				DDRSS0_PHY_820_DATA
-				DDRSS0_PHY_821_DATA
-				DDRSS0_PHY_822_DATA
-				DDRSS0_PHY_823_DATA
-				DDRSS0_PHY_824_DATA
-				DDRSS0_PHY_825_DATA
-				DDRSS0_PHY_826_DATA
-				DDRSS0_PHY_827_DATA
-				DDRSS0_PHY_828_DATA
-				DDRSS0_PHY_829_DATA
-				DDRSS0_PHY_830_DATA
-				DDRSS0_PHY_831_DATA
-				DDRSS0_PHY_832_DATA
-				DDRSS0_PHY_833_DATA
-				DDRSS0_PHY_834_DATA
-				DDRSS0_PHY_835_DATA
-				DDRSS0_PHY_836_DATA
-				DDRSS0_PHY_837_DATA
-				DDRSS0_PHY_838_DATA
-				DDRSS0_PHY_839_DATA
-				DDRSS0_PHY_840_DATA
-				DDRSS0_PHY_841_DATA
-				DDRSS0_PHY_842_DATA
-				DDRSS0_PHY_843_DATA
-				DDRSS0_PHY_844_DATA
-				DDRSS0_PHY_845_DATA
-				DDRSS0_PHY_846_DATA
-				DDRSS0_PHY_847_DATA
-				DDRSS0_PHY_848_DATA
-				DDRSS0_PHY_849_DATA
-				DDRSS0_PHY_850_DATA
-				DDRSS0_PHY_851_DATA
-				DDRSS0_PHY_852_DATA
-				DDRSS0_PHY_853_DATA
-				DDRSS0_PHY_854_DATA
-				DDRSS0_PHY_855_DATA
-				DDRSS0_PHY_856_DATA
-				DDRSS0_PHY_857_DATA
-				DDRSS0_PHY_858_DATA
-				DDRSS0_PHY_859_DATA
-				DDRSS0_PHY_860_DATA
-				DDRSS0_PHY_861_DATA
-				DDRSS0_PHY_862_DATA
-				DDRSS0_PHY_863_DATA
-				DDRSS0_PHY_864_DATA
-				DDRSS0_PHY_865_DATA
-				DDRSS0_PHY_866_DATA
-				DDRSS0_PHY_867_DATA
-				DDRSS0_PHY_868_DATA
-				DDRSS0_PHY_869_DATA
-				DDRSS0_PHY_870_DATA
-				DDRSS0_PHY_871_DATA
-				DDRSS0_PHY_872_DATA
-				DDRSS0_PHY_873_DATA
-				DDRSS0_PHY_874_DATA
-				DDRSS0_PHY_875_DATA
-				DDRSS0_PHY_876_DATA
-				DDRSS0_PHY_877_DATA
-				DDRSS0_PHY_878_DATA
-				DDRSS0_PHY_879_DATA
-				DDRSS0_PHY_880_DATA
-				DDRSS0_PHY_881_DATA
-				DDRSS0_PHY_882_DATA
-				DDRSS0_PHY_883_DATA
-				DDRSS0_PHY_884_DATA
-				DDRSS0_PHY_885_DATA
-				DDRSS0_PHY_886_DATA
-				DDRSS0_PHY_887_DATA
-				DDRSS0_PHY_888_DATA
-				DDRSS0_PHY_889_DATA
-				DDRSS0_PHY_890_DATA
-				DDRSS0_PHY_891_DATA
-				DDRSS0_PHY_892_DATA
-				DDRSS0_PHY_893_DATA
-				DDRSS0_PHY_894_DATA
-				DDRSS0_PHY_895_DATA
-				DDRSS0_PHY_896_DATA
-				DDRSS0_PHY_897_DATA
-				DDRSS0_PHY_898_DATA
-				DDRSS0_PHY_899_DATA
-				DDRSS0_PHY_900_DATA
-				DDRSS0_PHY_901_DATA
-				DDRSS0_PHY_902_DATA
-				DDRSS0_PHY_903_DATA
-				DDRSS0_PHY_904_DATA
-				DDRSS0_PHY_905_DATA
-				DDRSS0_PHY_906_DATA
-				DDRSS0_PHY_907_DATA
-				DDRSS0_PHY_908_DATA
-				DDRSS0_PHY_909_DATA
-				DDRSS0_PHY_910_DATA
-				DDRSS0_PHY_911_DATA
-				DDRSS0_PHY_912_DATA
-				DDRSS0_PHY_913_DATA
-				DDRSS0_PHY_914_DATA
-				DDRSS0_PHY_915_DATA
-				DDRSS0_PHY_916_DATA
-				DDRSS0_PHY_917_DATA
-				DDRSS0_PHY_918_DATA
-				DDRSS0_PHY_919_DATA
-				DDRSS0_PHY_920_DATA
-				DDRSS0_PHY_921_DATA
-				DDRSS0_PHY_922_DATA
-				DDRSS0_PHY_923_DATA
-				DDRSS0_PHY_924_DATA
-				DDRSS0_PHY_925_DATA
-				DDRSS0_PHY_926_DATA
-				DDRSS0_PHY_927_DATA
-				DDRSS0_PHY_928_DATA
-				DDRSS0_PHY_929_DATA
-				DDRSS0_PHY_930_DATA
-				DDRSS0_PHY_931_DATA
-				DDRSS0_PHY_932_DATA
-				DDRSS0_PHY_933_DATA
-				DDRSS0_PHY_934_DATA
-				DDRSS0_PHY_935_DATA
-				DDRSS0_PHY_936_DATA
-				DDRSS0_PHY_937_DATA
-				DDRSS0_PHY_938_DATA
-				DDRSS0_PHY_939_DATA
-				DDRSS0_PHY_940_DATA
-				DDRSS0_PHY_941_DATA
-				DDRSS0_PHY_942_DATA
-				DDRSS0_PHY_943_DATA
-				DDRSS0_PHY_944_DATA
-				DDRSS0_PHY_945_DATA
-				DDRSS0_PHY_946_DATA
-				DDRSS0_PHY_947_DATA
-				DDRSS0_PHY_948_DATA
-				DDRSS0_PHY_949_DATA
-				DDRSS0_PHY_950_DATA
-				DDRSS0_PHY_951_DATA
-				DDRSS0_PHY_952_DATA
-				DDRSS0_PHY_953_DATA
-				DDRSS0_PHY_954_DATA
-				DDRSS0_PHY_955_DATA
-				DDRSS0_PHY_956_DATA
-				DDRSS0_PHY_957_DATA
-				DDRSS0_PHY_958_DATA
-				DDRSS0_PHY_959_DATA
-				DDRSS0_PHY_960_DATA
-				DDRSS0_PHY_961_DATA
-				DDRSS0_PHY_962_DATA
-				DDRSS0_PHY_963_DATA
-				DDRSS0_PHY_964_DATA
-				DDRSS0_PHY_965_DATA
-				DDRSS0_PHY_966_DATA
-				DDRSS0_PHY_967_DATA
-				DDRSS0_PHY_968_DATA
-				DDRSS0_PHY_969_DATA
-				DDRSS0_PHY_970_DATA
-				DDRSS0_PHY_971_DATA
-				DDRSS0_PHY_972_DATA
-				DDRSS0_PHY_973_DATA
-				DDRSS0_PHY_974_DATA
-				DDRSS0_PHY_975_DATA
-				DDRSS0_PHY_976_DATA
-				DDRSS0_PHY_977_DATA
-				DDRSS0_PHY_978_DATA
-				DDRSS0_PHY_979_DATA
-				DDRSS0_PHY_980_DATA
-				DDRSS0_PHY_981_DATA
-				DDRSS0_PHY_982_DATA
-				DDRSS0_PHY_983_DATA
-				DDRSS0_PHY_984_DATA
-				DDRSS0_PHY_985_DATA
-				DDRSS0_PHY_986_DATA
-				DDRSS0_PHY_987_DATA
-				DDRSS0_PHY_988_DATA
-				DDRSS0_PHY_989_DATA
-				DDRSS0_PHY_990_DATA
-				DDRSS0_PHY_991_DATA
-				DDRSS0_PHY_992_DATA
-				DDRSS0_PHY_993_DATA
-				DDRSS0_PHY_994_DATA
-				DDRSS0_PHY_995_DATA
-				DDRSS0_PHY_996_DATA
-				DDRSS0_PHY_997_DATA
-				DDRSS0_PHY_998_DATA
-				DDRSS0_PHY_999_DATA
-				DDRSS0_PHY_1000_DATA
-				DDRSS0_PHY_1001_DATA
-				DDRSS0_PHY_1002_DATA
-				DDRSS0_PHY_1003_DATA
-				DDRSS0_PHY_1004_DATA
-				DDRSS0_PHY_1005_DATA
-				DDRSS0_PHY_1006_DATA
-				DDRSS0_PHY_1007_DATA
-				DDRSS0_PHY_1008_DATA
-				DDRSS0_PHY_1009_DATA
-				DDRSS0_PHY_1010_DATA
-				DDRSS0_PHY_1011_DATA
-				DDRSS0_PHY_1012_DATA
-				DDRSS0_PHY_1013_DATA
-				DDRSS0_PHY_1014_DATA
-				DDRSS0_PHY_1015_DATA
-				DDRSS0_PHY_1016_DATA
-				DDRSS0_PHY_1017_DATA
-				DDRSS0_PHY_1018_DATA
-				DDRSS0_PHY_1019_DATA
-				DDRSS0_PHY_1020_DATA
-				DDRSS0_PHY_1021_DATA
-				DDRSS0_PHY_1022_DATA
-				DDRSS0_PHY_1023_DATA
-				DDRSS0_PHY_1024_DATA
-				DDRSS0_PHY_1025_DATA
-				DDRSS0_PHY_1026_DATA
-				DDRSS0_PHY_1027_DATA
-				DDRSS0_PHY_1028_DATA
-				DDRSS0_PHY_1029_DATA
-				DDRSS0_PHY_1030_DATA
-				DDRSS0_PHY_1031_DATA
-				DDRSS0_PHY_1032_DATA
-				DDRSS0_PHY_1033_DATA
-				DDRSS0_PHY_1034_DATA
-				DDRSS0_PHY_1035_DATA
-				DDRSS0_PHY_1036_DATA
-				DDRSS0_PHY_1037_DATA
-				DDRSS0_PHY_1038_DATA
-				DDRSS0_PHY_1039_DATA
-				DDRSS0_PHY_1040_DATA
-				DDRSS0_PHY_1041_DATA
-				DDRSS0_PHY_1042_DATA
-				DDRSS0_PHY_1043_DATA
-				DDRSS0_PHY_1044_DATA
-				DDRSS0_PHY_1045_DATA
-				DDRSS0_PHY_1046_DATA
-				DDRSS0_PHY_1047_DATA
-				DDRSS0_PHY_1048_DATA
-				DDRSS0_PHY_1049_DATA
-				DDRSS0_PHY_1050_DATA
-				DDRSS0_PHY_1051_DATA
-				DDRSS0_PHY_1052_DATA
-				DDRSS0_PHY_1053_DATA
-				DDRSS0_PHY_1054_DATA
-				DDRSS0_PHY_1055_DATA
-				DDRSS0_PHY_1056_DATA
-				DDRSS0_PHY_1057_DATA
-				DDRSS0_PHY_1058_DATA
-				DDRSS0_PHY_1059_DATA
-				DDRSS0_PHY_1060_DATA
-				DDRSS0_PHY_1061_DATA
-				DDRSS0_PHY_1062_DATA
-				DDRSS0_PHY_1063_DATA
-				DDRSS0_PHY_1064_DATA
-				DDRSS0_PHY_1065_DATA
-				DDRSS0_PHY_1066_DATA
-				DDRSS0_PHY_1067_DATA
-				DDRSS0_PHY_1068_DATA
-				DDRSS0_PHY_1069_DATA
-				DDRSS0_PHY_1070_DATA
-				DDRSS0_PHY_1071_DATA
-				DDRSS0_PHY_1072_DATA
-				DDRSS0_PHY_1073_DATA
-				DDRSS0_PHY_1074_DATA
-				DDRSS0_PHY_1075_DATA
-				DDRSS0_PHY_1076_DATA
-				DDRSS0_PHY_1077_DATA
-				DDRSS0_PHY_1078_DATA
-				DDRSS0_PHY_1079_DATA
-				DDRSS0_PHY_1080_DATA
-				DDRSS0_PHY_1081_DATA
-				DDRSS0_PHY_1082_DATA
-				DDRSS0_PHY_1083_DATA
-				DDRSS0_PHY_1084_DATA
-				DDRSS0_PHY_1085_DATA
-				DDRSS0_PHY_1086_DATA
-				DDRSS0_PHY_1087_DATA
-				DDRSS0_PHY_1088_DATA
-				DDRSS0_PHY_1089_DATA
-				DDRSS0_PHY_1090_DATA
-				DDRSS0_PHY_1091_DATA
-				DDRSS0_PHY_1092_DATA
-				DDRSS0_PHY_1093_DATA
-				DDRSS0_PHY_1094_DATA
-				DDRSS0_PHY_1095_DATA
-				DDRSS0_PHY_1096_DATA
-				DDRSS0_PHY_1097_DATA
-				DDRSS0_PHY_1098_DATA
-				DDRSS0_PHY_1099_DATA
-				DDRSS0_PHY_1100_DATA
-				DDRSS0_PHY_1101_DATA
-				DDRSS0_PHY_1102_DATA
-				DDRSS0_PHY_1103_DATA
-				DDRSS0_PHY_1104_DATA
-				DDRSS0_PHY_1105_DATA
-				DDRSS0_PHY_1106_DATA
-				DDRSS0_PHY_1107_DATA
-				DDRSS0_PHY_1108_DATA
-				DDRSS0_PHY_1109_DATA
-				DDRSS0_PHY_1110_DATA
-				DDRSS0_PHY_1111_DATA
-				DDRSS0_PHY_1112_DATA
-				DDRSS0_PHY_1113_DATA
-				DDRSS0_PHY_1114_DATA
-				DDRSS0_PHY_1115_DATA
-				DDRSS0_PHY_1116_DATA
-				DDRSS0_PHY_1117_DATA
-				DDRSS0_PHY_1118_DATA
-				DDRSS0_PHY_1119_DATA
-				DDRSS0_PHY_1120_DATA
-				DDRSS0_PHY_1121_DATA
-				DDRSS0_PHY_1122_DATA
-				DDRSS0_PHY_1123_DATA
-				DDRSS0_PHY_1124_DATA
-				DDRSS0_PHY_1125_DATA
-				DDRSS0_PHY_1126_DATA
-				DDRSS0_PHY_1127_DATA
-				DDRSS0_PHY_1128_DATA
-				DDRSS0_PHY_1129_DATA
-				DDRSS0_PHY_1130_DATA
-				DDRSS0_PHY_1131_DATA
-				DDRSS0_PHY_1132_DATA
-				DDRSS0_PHY_1133_DATA
-				DDRSS0_PHY_1134_DATA
-				DDRSS0_PHY_1135_DATA
-				DDRSS0_PHY_1136_DATA
-				DDRSS0_PHY_1137_DATA
-				DDRSS0_PHY_1138_DATA
-				DDRSS0_PHY_1139_DATA
-				DDRSS0_PHY_1140_DATA
-				DDRSS0_PHY_1141_DATA
-				DDRSS0_PHY_1142_DATA
-				DDRSS0_PHY_1143_DATA
-				DDRSS0_PHY_1144_DATA
-				DDRSS0_PHY_1145_DATA
-				DDRSS0_PHY_1146_DATA
-				DDRSS0_PHY_1147_DATA
-				DDRSS0_PHY_1148_DATA
-				DDRSS0_PHY_1149_DATA
-				DDRSS0_PHY_1150_DATA
-				DDRSS0_PHY_1151_DATA
-				DDRSS0_PHY_1152_DATA
-				DDRSS0_PHY_1153_DATA
-				DDRSS0_PHY_1154_DATA
-				DDRSS0_PHY_1155_DATA
-				DDRSS0_PHY_1156_DATA
-				DDRSS0_PHY_1157_DATA
-				DDRSS0_PHY_1158_DATA
-				DDRSS0_PHY_1159_DATA
-				DDRSS0_PHY_1160_DATA
-				DDRSS0_PHY_1161_DATA
-				DDRSS0_PHY_1162_DATA
-				DDRSS0_PHY_1163_DATA
-				DDRSS0_PHY_1164_DATA
-				DDRSS0_PHY_1165_DATA
-				DDRSS0_PHY_1166_DATA
-				DDRSS0_PHY_1167_DATA
-				DDRSS0_PHY_1168_DATA
-				DDRSS0_PHY_1169_DATA
-				DDRSS0_PHY_1170_DATA
-				DDRSS0_PHY_1171_DATA
-				DDRSS0_PHY_1172_DATA
-				DDRSS0_PHY_1173_DATA
-				DDRSS0_PHY_1174_DATA
-				DDRSS0_PHY_1175_DATA
-				DDRSS0_PHY_1176_DATA
-				DDRSS0_PHY_1177_DATA
-				DDRSS0_PHY_1178_DATA
-				DDRSS0_PHY_1179_DATA
-				DDRSS0_PHY_1180_DATA
-				DDRSS0_PHY_1181_DATA
-				DDRSS0_PHY_1182_DATA
-				DDRSS0_PHY_1183_DATA
-				DDRSS0_PHY_1184_DATA
-				DDRSS0_PHY_1185_DATA
-				DDRSS0_PHY_1186_DATA
-				DDRSS0_PHY_1187_DATA
-				DDRSS0_PHY_1188_DATA
-				DDRSS0_PHY_1189_DATA
-				DDRSS0_PHY_1190_DATA
-				DDRSS0_PHY_1191_DATA
-				DDRSS0_PHY_1192_DATA
-				DDRSS0_PHY_1193_DATA
-				DDRSS0_PHY_1194_DATA
-				DDRSS0_PHY_1195_DATA
-				DDRSS0_PHY_1196_DATA
-				DDRSS0_PHY_1197_DATA
-				DDRSS0_PHY_1198_DATA
-				DDRSS0_PHY_1199_DATA
-				DDRSS0_PHY_1200_DATA
-				DDRSS0_PHY_1201_DATA
-				DDRSS0_PHY_1202_DATA
-				DDRSS0_PHY_1203_DATA
-				DDRSS0_PHY_1204_DATA
-				DDRSS0_PHY_1205_DATA
-				DDRSS0_PHY_1206_DATA
-				DDRSS0_PHY_1207_DATA
-				DDRSS0_PHY_1208_DATA
-				DDRSS0_PHY_1209_DATA
-				DDRSS0_PHY_1210_DATA
-				DDRSS0_PHY_1211_DATA
-				DDRSS0_PHY_1212_DATA
-				DDRSS0_PHY_1213_DATA
-				DDRSS0_PHY_1214_DATA
-				DDRSS0_PHY_1215_DATA
-				DDRSS0_PHY_1216_DATA
-				DDRSS0_PHY_1217_DATA
-				DDRSS0_PHY_1218_DATA
-				DDRSS0_PHY_1219_DATA
-				DDRSS0_PHY_1220_DATA
-				DDRSS0_PHY_1221_DATA
-				DDRSS0_PHY_1222_DATA
-				DDRSS0_PHY_1223_DATA
-				DDRSS0_PHY_1224_DATA
-				DDRSS0_PHY_1225_DATA
-				DDRSS0_PHY_1226_DATA
-				DDRSS0_PHY_1227_DATA
-				DDRSS0_PHY_1228_DATA
-				DDRSS0_PHY_1229_DATA
-				DDRSS0_PHY_1230_DATA
-				DDRSS0_PHY_1231_DATA
-				DDRSS0_PHY_1232_DATA
-				DDRSS0_PHY_1233_DATA
-				DDRSS0_PHY_1234_DATA
-				DDRSS0_PHY_1235_DATA
-				DDRSS0_PHY_1236_DATA
-				DDRSS0_PHY_1237_DATA
-				DDRSS0_PHY_1238_DATA
-				DDRSS0_PHY_1239_DATA
-				DDRSS0_PHY_1240_DATA
-				DDRSS0_PHY_1241_DATA
-				DDRSS0_PHY_1242_DATA
-				DDRSS0_PHY_1243_DATA
-				DDRSS0_PHY_1244_DATA
-				DDRSS0_PHY_1245_DATA
-				DDRSS0_PHY_1246_DATA
-				DDRSS0_PHY_1247_DATA
-				DDRSS0_PHY_1248_DATA
-				DDRSS0_PHY_1249_DATA
-				DDRSS0_PHY_1250_DATA
-				DDRSS0_PHY_1251_DATA
-				DDRSS0_PHY_1252_DATA
-				DDRSS0_PHY_1253_DATA
-				DDRSS0_PHY_1254_DATA
-				DDRSS0_PHY_1255_DATA
-				DDRSS0_PHY_1256_DATA
-				DDRSS0_PHY_1257_DATA
-				DDRSS0_PHY_1258_DATA
-				DDRSS0_PHY_1259_DATA
-				DDRSS0_PHY_1260_DATA
-				DDRSS0_PHY_1261_DATA
-				DDRSS0_PHY_1262_DATA
-				DDRSS0_PHY_1263_DATA
-				DDRSS0_PHY_1264_DATA
-				DDRSS0_PHY_1265_DATA
-				DDRSS0_PHY_1266_DATA
-				DDRSS0_PHY_1267_DATA
-				DDRSS0_PHY_1268_DATA
-				DDRSS0_PHY_1269_DATA
-				DDRSS0_PHY_1270_DATA
-				DDRSS0_PHY_1271_DATA
-				DDRSS0_PHY_1272_DATA
-				DDRSS0_PHY_1273_DATA
-				DDRSS0_PHY_1274_DATA
-				DDRSS0_PHY_1275_DATA
-				DDRSS0_PHY_1276_DATA
-				DDRSS0_PHY_1277_DATA
-				DDRSS0_PHY_1278_DATA
-				DDRSS0_PHY_1279_DATA
-				DDRSS0_PHY_1280_DATA
-				DDRSS0_PHY_1281_DATA
-				DDRSS0_PHY_1282_DATA
-				DDRSS0_PHY_1283_DATA
-				DDRSS0_PHY_1284_DATA
-				DDRSS0_PHY_1285_DATA
-				DDRSS0_PHY_1286_DATA
-				DDRSS0_PHY_1287_DATA
-				DDRSS0_PHY_1288_DATA
-				DDRSS0_PHY_1289_DATA
-				DDRSS0_PHY_1290_DATA
-				DDRSS0_PHY_1291_DATA
-				DDRSS0_PHY_1292_DATA
-				DDRSS0_PHY_1293_DATA
-				DDRSS0_PHY_1294_DATA
-				DDRSS0_PHY_1295_DATA
-				DDRSS0_PHY_1296_DATA
-				DDRSS0_PHY_1297_DATA
-				DDRSS0_PHY_1298_DATA
-				DDRSS0_PHY_1299_DATA
-				DDRSS0_PHY_1300_DATA
-				DDRSS0_PHY_1301_DATA
-				DDRSS0_PHY_1302_DATA
-				DDRSS0_PHY_1303_DATA
-				DDRSS0_PHY_1304_DATA
-				DDRSS0_PHY_1305_DATA
-				DDRSS0_PHY_1306_DATA
-				DDRSS0_PHY_1307_DATA
-				DDRSS0_PHY_1308_DATA
-				DDRSS0_PHY_1309_DATA
-				DDRSS0_PHY_1310_DATA
-				DDRSS0_PHY_1311_DATA
-				DDRSS0_PHY_1312_DATA
-				DDRSS0_PHY_1313_DATA
-				DDRSS0_PHY_1314_DATA
-				DDRSS0_PHY_1315_DATA
-				DDRSS0_PHY_1316_DATA
-				DDRSS0_PHY_1317_DATA
-				DDRSS0_PHY_1318_DATA
-				DDRSS0_PHY_1319_DATA
-				DDRSS0_PHY_1320_DATA
-				DDRSS0_PHY_1321_DATA
-				DDRSS0_PHY_1322_DATA
-				DDRSS0_PHY_1323_DATA
-				DDRSS0_PHY_1324_DATA
-				DDRSS0_PHY_1325_DATA
-				DDRSS0_PHY_1326_DATA
-				DDRSS0_PHY_1327_DATA
-				DDRSS0_PHY_1328_DATA
-				DDRSS0_PHY_1329_DATA
-				DDRSS0_PHY_1330_DATA
-				DDRSS0_PHY_1331_DATA
-				DDRSS0_PHY_1332_DATA
-				DDRSS0_PHY_1333_DATA
-				DDRSS0_PHY_1334_DATA
-				DDRSS0_PHY_1335_DATA
-				DDRSS0_PHY_1336_DATA
-				DDRSS0_PHY_1337_DATA
-				DDRSS0_PHY_1338_DATA
-				DDRSS0_PHY_1339_DATA
-				DDRSS0_PHY_1340_DATA
-				DDRSS0_PHY_1341_DATA
-				DDRSS0_PHY_1342_DATA
-				DDRSS0_PHY_1343_DATA
-				DDRSS0_PHY_1344_DATA
-				DDRSS0_PHY_1345_DATA
-				DDRSS0_PHY_1346_DATA
-				DDRSS0_PHY_1347_DATA
-				DDRSS0_PHY_1348_DATA
-				DDRSS0_PHY_1349_DATA
-				DDRSS0_PHY_1350_DATA
-				DDRSS0_PHY_1351_DATA
-				DDRSS0_PHY_1352_DATA
-				DDRSS0_PHY_1353_DATA
-				DDRSS0_PHY_1354_DATA
-				DDRSS0_PHY_1355_DATA
-				DDRSS0_PHY_1356_DATA
-				DDRSS0_PHY_1357_DATA
-				DDRSS0_PHY_1358_DATA
-				DDRSS0_PHY_1359_DATA
-				DDRSS0_PHY_1360_DATA
-				DDRSS0_PHY_1361_DATA
-				DDRSS0_PHY_1362_DATA
-				DDRSS0_PHY_1363_DATA
-				DDRSS0_PHY_1364_DATA
-				DDRSS0_PHY_1365_DATA
-				DDRSS0_PHY_1366_DATA
-				DDRSS0_PHY_1367_DATA
-				DDRSS0_PHY_1368_DATA
-				DDRSS0_PHY_1369_DATA
-				DDRSS0_PHY_1370_DATA
-				DDRSS0_PHY_1371_DATA
-				DDRSS0_PHY_1372_DATA
-				DDRSS0_PHY_1373_DATA
-				DDRSS0_PHY_1374_DATA
-				DDRSS0_PHY_1375_DATA
-				DDRSS0_PHY_1376_DATA
-				DDRSS0_PHY_1377_DATA
-				DDRSS0_PHY_1378_DATA
-				DDRSS0_PHY_1379_DATA
-				DDRSS0_PHY_1380_DATA
-				DDRSS0_PHY_1381_DATA
-				DDRSS0_PHY_1382_DATA
-				DDRSS0_PHY_1383_DATA
-				DDRSS0_PHY_1384_DATA
-				DDRSS0_PHY_1385_DATA
-				DDRSS0_PHY_1386_DATA
-				DDRSS0_PHY_1387_DATA
-				DDRSS0_PHY_1388_DATA
-				DDRSS0_PHY_1389_DATA
-				DDRSS0_PHY_1390_DATA
-				DDRSS0_PHY_1391_DATA
-				DDRSS0_PHY_1392_DATA
-				DDRSS0_PHY_1393_DATA
-				DDRSS0_PHY_1394_DATA
-				DDRSS0_PHY_1395_DATA
-				DDRSS0_PHY_1396_DATA
-				DDRSS0_PHY_1397_DATA
-				DDRSS0_PHY_1398_DATA
-				DDRSS0_PHY_1399_DATA
-				DDRSS0_PHY_1400_DATA
-				DDRSS0_PHY_1401_DATA
-				DDRSS0_PHY_1402_DATA
-				DDRSS0_PHY_1403_DATA
-				DDRSS0_PHY_1404_DATA
-				DDRSS0_PHY_1405_DATA
-				DDRSS0_PHY_1406_DATA
-				DDRSS0_PHY_1407_DATA
-				DDRSS0_PHY_1408_DATA
-				DDRSS0_PHY_1409_DATA
-				DDRSS0_PHY_1410_DATA
-				DDRSS0_PHY_1411_DATA
-				DDRSS0_PHY_1412_DATA
-				DDRSS0_PHY_1413_DATA
-				DDRSS0_PHY_1414_DATA
-				DDRSS0_PHY_1415_DATA
-				DDRSS0_PHY_1416_DATA
-				DDRSS0_PHY_1417_DATA
-				DDRSS0_PHY_1418_DATA
-				DDRSS0_PHY_1419_DATA
-				DDRSS0_PHY_1420_DATA
-				DDRSS0_PHY_1421_DATA
-				DDRSS0_PHY_1422_DATA
-			>;
-		};
-
-		memorycontroller1: memorycontroller@29b0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029b0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x029a0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
-				<&k3_pds 132 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <1>;
-
-			bootph-pre-ram;
-
-			ti,ctl-data = <
-				DDRSS1_CTL_00_DATA
-				DDRSS1_CTL_01_DATA
-				DDRSS1_CTL_02_DATA
-				DDRSS1_CTL_03_DATA
-				DDRSS1_CTL_04_DATA
-				DDRSS1_CTL_05_DATA
-				DDRSS1_CTL_06_DATA
-				DDRSS1_CTL_07_DATA
-				DDRSS1_CTL_08_DATA
-				DDRSS1_CTL_09_DATA
-				DDRSS1_CTL_10_DATA
-				DDRSS1_CTL_11_DATA
-				DDRSS1_CTL_12_DATA
-				DDRSS1_CTL_13_DATA
-				DDRSS1_CTL_14_DATA
-				DDRSS1_CTL_15_DATA
-				DDRSS1_CTL_16_DATA
-				DDRSS1_CTL_17_DATA
-				DDRSS1_CTL_18_DATA
-				DDRSS1_CTL_19_DATA
-				DDRSS1_CTL_20_DATA
-				DDRSS1_CTL_21_DATA
-				DDRSS1_CTL_22_DATA
-				DDRSS1_CTL_23_DATA
-				DDRSS1_CTL_24_DATA
-				DDRSS1_CTL_25_DATA
-				DDRSS1_CTL_26_DATA
-				DDRSS1_CTL_27_DATA
-				DDRSS1_CTL_28_DATA
-				DDRSS1_CTL_29_DATA
-				DDRSS1_CTL_30_DATA
-				DDRSS1_CTL_31_DATA
-				DDRSS1_CTL_32_DATA
-				DDRSS1_CTL_33_DATA
-				DDRSS1_CTL_34_DATA
-				DDRSS1_CTL_35_DATA
-				DDRSS1_CTL_36_DATA
-				DDRSS1_CTL_37_DATA
-				DDRSS1_CTL_38_DATA
-				DDRSS1_CTL_39_DATA
-				DDRSS1_CTL_40_DATA
-				DDRSS1_CTL_41_DATA
-				DDRSS1_CTL_42_DATA
-				DDRSS1_CTL_43_DATA
-				DDRSS1_CTL_44_DATA
-				DDRSS1_CTL_45_DATA
-				DDRSS1_CTL_46_DATA
-				DDRSS1_CTL_47_DATA
-				DDRSS1_CTL_48_DATA
-				DDRSS1_CTL_49_DATA
-				DDRSS1_CTL_50_DATA
-				DDRSS1_CTL_51_DATA
-				DDRSS1_CTL_52_DATA
-				DDRSS1_CTL_53_DATA
-				DDRSS1_CTL_54_DATA
-				DDRSS1_CTL_55_DATA
-				DDRSS1_CTL_56_DATA
-				DDRSS1_CTL_57_DATA
-				DDRSS1_CTL_58_DATA
-				DDRSS1_CTL_59_DATA
-				DDRSS1_CTL_60_DATA
-				DDRSS1_CTL_61_DATA
-				DDRSS1_CTL_62_DATA
-				DDRSS1_CTL_63_DATA
-				DDRSS1_CTL_64_DATA
-				DDRSS1_CTL_65_DATA
-				DDRSS1_CTL_66_DATA
-				DDRSS1_CTL_67_DATA
-				DDRSS1_CTL_68_DATA
-				DDRSS1_CTL_69_DATA
-				DDRSS1_CTL_70_DATA
-				DDRSS1_CTL_71_DATA
-				DDRSS1_CTL_72_DATA
-				DDRSS1_CTL_73_DATA
-				DDRSS1_CTL_74_DATA
-				DDRSS1_CTL_75_DATA
-				DDRSS1_CTL_76_DATA
-				DDRSS1_CTL_77_DATA
-				DDRSS1_CTL_78_DATA
-				DDRSS1_CTL_79_DATA
-				DDRSS1_CTL_80_DATA
-				DDRSS1_CTL_81_DATA
-				DDRSS1_CTL_82_DATA
-				DDRSS1_CTL_83_DATA
-				DDRSS1_CTL_84_DATA
-				DDRSS1_CTL_85_DATA
-				DDRSS1_CTL_86_DATA
-				DDRSS1_CTL_87_DATA
-				DDRSS1_CTL_88_DATA
-				DDRSS1_CTL_89_DATA
-				DDRSS1_CTL_90_DATA
-				DDRSS1_CTL_91_DATA
-				DDRSS1_CTL_92_DATA
-				DDRSS1_CTL_93_DATA
-				DDRSS1_CTL_94_DATA
-				DDRSS1_CTL_95_DATA
-				DDRSS1_CTL_96_DATA
-				DDRSS1_CTL_97_DATA
-				DDRSS1_CTL_98_DATA
-				DDRSS1_CTL_99_DATA
-				DDRSS1_CTL_100_DATA
-				DDRSS1_CTL_101_DATA
-				DDRSS1_CTL_102_DATA
-				DDRSS1_CTL_103_DATA
-				DDRSS1_CTL_104_DATA
-				DDRSS1_CTL_105_DATA
-				DDRSS1_CTL_106_DATA
-				DDRSS1_CTL_107_DATA
-				DDRSS1_CTL_108_DATA
-				DDRSS1_CTL_109_DATA
-				DDRSS1_CTL_110_DATA
-				DDRSS1_CTL_111_DATA
-				DDRSS1_CTL_112_DATA
-				DDRSS1_CTL_113_DATA
-				DDRSS1_CTL_114_DATA
-				DDRSS1_CTL_115_DATA
-				DDRSS1_CTL_116_DATA
-				DDRSS1_CTL_117_DATA
-				DDRSS1_CTL_118_DATA
-				DDRSS1_CTL_119_DATA
-				DDRSS1_CTL_120_DATA
-				DDRSS1_CTL_121_DATA
-				DDRSS1_CTL_122_DATA
-				DDRSS1_CTL_123_DATA
-				DDRSS1_CTL_124_DATA
-				DDRSS1_CTL_125_DATA
-				DDRSS1_CTL_126_DATA
-				DDRSS1_CTL_127_DATA
-				DDRSS1_CTL_128_DATA
-				DDRSS1_CTL_129_DATA
-				DDRSS1_CTL_130_DATA
-				DDRSS1_CTL_131_DATA
-				DDRSS1_CTL_132_DATA
-				DDRSS1_CTL_133_DATA
-				DDRSS1_CTL_134_DATA
-				DDRSS1_CTL_135_DATA
-				DDRSS1_CTL_136_DATA
-				DDRSS1_CTL_137_DATA
-				DDRSS1_CTL_138_DATA
-				DDRSS1_CTL_139_DATA
-				DDRSS1_CTL_140_DATA
-				DDRSS1_CTL_141_DATA
-				DDRSS1_CTL_142_DATA
-				DDRSS1_CTL_143_DATA
-				DDRSS1_CTL_144_DATA
-				DDRSS1_CTL_145_DATA
-				DDRSS1_CTL_146_DATA
-				DDRSS1_CTL_147_DATA
-				DDRSS1_CTL_148_DATA
-				DDRSS1_CTL_149_DATA
-				DDRSS1_CTL_150_DATA
-				DDRSS1_CTL_151_DATA
-				DDRSS1_CTL_152_DATA
-				DDRSS1_CTL_153_DATA
-				DDRSS1_CTL_154_DATA
-				DDRSS1_CTL_155_DATA
-				DDRSS1_CTL_156_DATA
-				DDRSS1_CTL_157_DATA
-				DDRSS1_CTL_158_DATA
-				DDRSS1_CTL_159_DATA
-				DDRSS1_CTL_160_DATA
-				DDRSS1_CTL_161_DATA
-				DDRSS1_CTL_162_DATA
-				DDRSS1_CTL_163_DATA
-				DDRSS1_CTL_164_DATA
-				DDRSS1_CTL_165_DATA
-				DDRSS1_CTL_166_DATA
-				DDRSS1_CTL_167_DATA
-				DDRSS1_CTL_168_DATA
-				DDRSS1_CTL_169_DATA
-				DDRSS1_CTL_170_DATA
-				DDRSS1_CTL_171_DATA
-				DDRSS1_CTL_172_DATA
-				DDRSS1_CTL_173_DATA
-				DDRSS1_CTL_174_DATA
-				DDRSS1_CTL_175_DATA
-				DDRSS1_CTL_176_DATA
-				DDRSS1_CTL_177_DATA
-				DDRSS1_CTL_178_DATA
-				DDRSS1_CTL_179_DATA
-				DDRSS1_CTL_180_DATA
-				DDRSS1_CTL_181_DATA
-				DDRSS1_CTL_182_DATA
-				DDRSS1_CTL_183_DATA
-				DDRSS1_CTL_184_DATA
-				DDRSS1_CTL_185_DATA
-				DDRSS1_CTL_186_DATA
-				DDRSS1_CTL_187_DATA
-				DDRSS1_CTL_188_DATA
-				DDRSS1_CTL_189_DATA
-				DDRSS1_CTL_190_DATA
-				DDRSS1_CTL_191_DATA
-				DDRSS1_CTL_192_DATA
-				DDRSS1_CTL_193_DATA
-				DDRSS1_CTL_194_DATA
-				DDRSS1_CTL_195_DATA
-				DDRSS1_CTL_196_DATA
-				DDRSS1_CTL_197_DATA
-				DDRSS1_CTL_198_DATA
-				DDRSS1_CTL_199_DATA
-				DDRSS1_CTL_200_DATA
-				DDRSS1_CTL_201_DATA
-				DDRSS1_CTL_202_DATA
-				DDRSS1_CTL_203_DATA
-				DDRSS1_CTL_204_DATA
-				DDRSS1_CTL_205_DATA
-				DDRSS1_CTL_206_DATA
-				DDRSS1_CTL_207_DATA
-				DDRSS1_CTL_208_DATA
-				DDRSS1_CTL_209_DATA
-				DDRSS1_CTL_210_DATA
-				DDRSS1_CTL_211_DATA
-				DDRSS1_CTL_212_DATA
-				DDRSS1_CTL_213_DATA
-				DDRSS1_CTL_214_DATA
-				DDRSS1_CTL_215_DATA
-				DDRSS1_CTL_216_DATA
-				DDRSS1_CTL_217_DATA
-				DDRSS1_CTL_218_DATA
-				DDRSS1_CTL_219_DATA
-				DDRSS1_CTL_220_DATA
-				DDRSS1_CTL_221_DATA
-				DDRSS1_CTL_222_DATA
-				DDRSS1_CTL_223_DATA
-				DDRSS1_CTL_224_DATA
-				DDRSS1_CTL_225_DATA
-				DDRSS1_CTL_226_DATA
-				DDRSS1_CTL_227_DATA
-				DDRSS1_CTL_228_DATA
-				DDRSS1_CTL_229_DATA
-				DDRSS1_CTL_230_DATA
-				DDRSS1_CTL_231_DATA
-				DDRSS1_CTL_232_DATA
-				DDRSS1_CTL_233_DATA
-				DDRSS1_CTL_234_DATA
-				DDRSS1_CTL_235_DATA
-				DDRSS1_CTL_236_DATA
-				DDRSS1_CTL_237_DATA
-				DDRSS1_CTL_238_DATA
-				DDRSS1_CTL_239_DATA
-				DDRSS1_CTL_240_DATA
-				DDRSS1_CTL_241_DATA
-				DDRSS1_CTL_242_DATA
-				DDRSS1_CTL_243_DATA
-				DDRSS1_CTL_244_DATA
-				DDRSS1_CTL_245_DATA
-				DDRSS1_CTL_246_DATA
-				DDRSS1_CTL_247_DATA
-				DDRSS1_CTL_248_DATA
-				DDRSS1_CTL_249_DATA
-				DDRSS1_CTL_250_DATA
-				DDRSS1_CTL_251_DATA
-				DDRSS1_CTL_252_DATA
-				DDRSS1_CTL_253_DATA
-				DDRSS1_CTL_254_DATA
-				DDRSS1_CTL_255_DATA
-				DDRSS1_CTL_256_DATA
-				DDRSS1_CTL_257_DATA
-				DDRSS1_CTL_258_DATA
-				DDRSS1_CTL_259_DATA
-				DDRSS1_CTL_260_DATA
-				DDRSS1_CTL_261_DATA
-				DDRSS1_CTL_262_DATA
-				DDRSS1_CTL_263_DATA
-				DDRSS1_CTL_264_DATA
-				DDRSS1_CTL_265_DATA
-				DDRSS1_CTL_266_DATA
-				DDRSS1_CTL_267_DATA
-				DDRSS1_CTL_268_DATA
-				DDRSS1_CTL_269_DATA
-				DDRSS1_CTL_270_DATA
-				DDRSS1_CTL_271_DATA
-				DDRSS1_CTL_272_DATA
-				DDRSS1_CTL_273_DATA
-				DDRSS1_CTL_274_DATA
-				DDRSS1_CTL_275_DATA
-				DDRSS1_CTL_276_DATA
-				DDRSS1_CTL_277_DATA
-				DDRSS1_CTL_278_DATA
-				DDRSS1_CTL_279_DATA
-				DDRSS1_CTL_280_DATA
-				DDRSS1_CTL_281_DATA
-				DDRSS1_CTL_282_DATA
-				DDRSS1_CTL_283_DATA
-				DDRSS1_CTL_284_DATA
-				DDRSS1_CTL_285_DATA
-				DDRSS1_CTL_286_DATA
-				DDRSS1_CTL_287_DATA
-				DDRSS1_CTL_288_DATA
-				DDRSS1_CTL_289_DATA
-				DDRSS1_CTL_290_DATA
-				DDRSS1_CTL_291_DATA
-				DDRSS1_CTL_292_DATA
-				DDRSS1_CTL_293_DATA
-				DDRSS1_CTL_294_DATA
-				DDRSS1_CTL_295_DATA
-				DDRSS1_CTL_296_DATA
-				DDRSS1_CTL_297_DATA
-				DDRSS1_CTL_298_DATA
-				DDRSS1_CTL_299_DATA
-				DDRSS1_CTL_300_DATA
-				DDRSS1_CTL_301_DATA
-				DDRSS1_CTL_302_DATA
-				DDRSS1_CTL_303_DATA
-				DDRSS1_CTL_304_DATA
-				DDRSS1_CTL_305_DATA
-				DDRSS1_CTL_306_DATA
-				DDRSS1_CTL_307_DATA
-				DDRSS1_CTL_308_DATA
-				DDRSS1_CTL_309_DATA
-				DDRSS1_CTL_310_DATA
-				DDRSS1_CTL_311_DATA
-				DDRSS1_CTL_312_DATA
-				DDRSS1_CTL_313_DATA
-				DDRSS1_CTL_314_DATA
-				DDRSS1_CTL_315_DATA
-				DDRSS1_CTL_316_DATA
-				DDRSS1_CTL_317_DATA
-				DDRSS1_CTL_318_DATA
-				DDRSS1_CTL_319_DATA
-				DDRSS1_CTL_320_DATA
-				DDRSS1_CTL_321_DATA
-				DDRSS1_CTL_322_DATA
-				DDRSS1_CTL_323_DATA
-				DDRSS1_CTL_324_DATA
-				DDRSS1_CTL_325_DATA
-				DDRSS1_CTL_326_DATA
-				DDRSS1_CTL_327_DATA
-				DDRSS1_CTL_328_DATA
-				DDRSS1_CTL_329_DATA
-				DDRSS1_CTL_330_DATA
-				DDRSS1_CTL_331_DATA
-				DDRSS1_CTL_332_DATA
-				DDRSS1_CTL_333_DATA
-				DDRSS1_CTL_334_DATA
-				DDRSS1_CTL_335_DATA
-				DDRSS1_CTL_336_DATA
-				DDRSS1_CTL_337_DATA
-				DDRSS1_CTL_338_DATA
-				DDRSS1_CTL_339_DATA
-				DDRSS1_CTL_340_DATA
-				DDRSS1_CTL_341_DATA
-				DDRSS1_CTL_342_DATA
-				DDRSS1_CTL_343_DATA
-				DDRSS1_CTL_344_DATA
-				DDRSS1_CTL_345_DATA
-				DDRSS1_CTL_346_DATA
-				DDRSS1_CTL_347_DATA
-				DDRSS1_CTL_348_DATA
-				DDRSS1_CTL_349_DATA
-				DDRSS1_CTL_350_DATA
-				DDRSS1_CTL_351_DATA
-				DDRSS1_CTL_352_DATA
-				DDRSS1_CTL_353_DATA
-				DDRSS1_CTL_354_DATA
-				DDRSS1_CTL_355_DATA
-				DDRSS1_CTL_356_DATA
-				DDRSS1_CTL_357_DATA
-				DDRSS1_CTL_358_DATA
-				DDRSS1_CTL_359_DATA
-				DDRSS1_CTL_360_DATA
-				DDRSS1_CTL_361_DATA
-				DDRSS1_CTL_362_DATA
-				DDRSS1_CTL_363_DATA
-				DDRSS1_CTL_364_DATA
-				DDRSS1_CTL_365_DATA
-				DDRSS1_CTL_366_DATA
-				DDRSS1_CTL_367_DATA
-				DDRSS1_CTL_368_DATA
-				DDRSS1_CTL_369_DATA
-				DDRSS1_CTL_370_DATA
-				DDRSS1_CTL_371_DATA
-				DDRSS1_CTL_372_DATA
-				DDRSS1_CTL_373_DATA
-				DDRSS1_CTL_374_DATA
-				DDRSS1_CTL_375_DATA
-				DDRSS1_CTL_376_DATA
-				DDRSS1_CTL_377_DATA
-				DDRSS1_CTL_378_DATA
-				DDRSS1_CTL_379_DATA
-				DDRSS1_CTL_380_DATA
-				DDRSS1_CTL_381_DATA
-				DDRSS1_CTL_382_DATA
-				DDRSS1_CTL_383_DATA
-				DDRSS1_CTL_384_DATA
-				DDRSS1_CTL_385_DATA
-				DDRSS1_CTL_386_DATA
-				DDRSS1_CTL_387_DATA
-				DDRSS1_CTL_388_DATA
-				DDRSS1_CTL_389_DATA
-				DDRSS1_CTL_390_DATA
-				DDRSS1_CTL_391_DATA
-				DDRSS1_CTL_392_DATA
-				DDRSS1_CTL_393_DATA
-				DDRSS1_CTL_394_DATA
-				DDRSS1_CTL_395_DATA
-				DDRSS1_CTL_396_DATA
-				DDRSS1_CTL_397_DATA
-				DDRSS1_CTL_398_DATA
-				DDRSS1_CTL_399_DATA
-				DDRSS1_CTL_400_DATA
-				DDRSS1_CTL_401_DATA
-				DDRSS1_CTL_402_DATA
-				DDRSS1_CTL_403_DATA
-				DDRSS1_CTL_404_DATA
-				DDRSS1_CTL_405_DATA
-				DDRSS1_CTL_406_DATA
-				DDRSS1_CTL_407_DATA
-				DDRSS1_CTL_408_DATA
-				DDRSS1_CTL_409_DATA
-				DDRSS1_CTL_410_DATA
-				DDRSS1_CTL_411_DATA
-				DDRSS1_CTL_412_DATA
-				DDRSS1_CTL_413_DATA
-				DDRSS1_CTL_414_DATA
-				DDRSS1_CTL_415_DATA
-				DDRSS1_CTL_416_DATA
-				DDRSS1_CTL_417_DATA
-				DDRSS1_CTL_418_DATA
-				DDRSS1_CTL_419_DATA
-				DDRSS1_CTL_420_DATA
-				DDRSS1_CTL_421_DATA
-				DDRSS1_CTL_422_DATA
-				DDRSS1_CTL_423_DATA
-				DDRSS1_CTL_424_DATA
-				DDRSS1_CTL_425_DATA
-				DDRSS1_CTL_426_DATA
-				DDRSS1_CTL_427_DATA
-				DDRSS1_CTL_428_DATA
-				DDRSS1_CTL_429_DATA
-				DDRSS1_CTL_430_DATA
-				DDRSS1_CTL_431_DATA
-				DDRSS1_CTL_432_DATA
-				DDRSS1_CTL_433_DATA
-				DDRSS1_CTL_434_DATA
-				DDRSS1_CTL_435_DATA
-				DDRSS1_CTL_436_DATA
-				DDRSS1_CTL_437_DATA
-				DDRSS1_CTL_438_DATA
-				DDRSS1_CTL_439_DATA
-				DDRSS1_CTL_440_DATA
-				DDRSS1_CTL_441_DATA
-				DDRSS1_CTL_442_DATA
-				DDRSS1_CTL_443_DATA
-				DDRSS1_CTL_444_DATA
-				DDRSS1_CTL_445_DATA
-				DDRSS1_CTL_446_DATA
-				DDRSS1_CTL_447_DATA
-				DDRSS1_CTL_448_DATA
-				DDRSS1_CTL_449_DATA
-				DDRSS1_CTL_450_DATA
-				DDRSS1_CTL_451_DATA
-				DDRSS1_CTL_452_DATA
-				DDRSS1_CTL_453_DATA
-				DDRSS1_CTL_454_DATA
-				DDRSS1_CTL_455_DATA
-				DDRSS1_CTL_456_DATA
-				DDRSS1_CTL_457_DATA
-				DDRSS1_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS1_PI_00_DATA
-				DDRSS1_PI_01_DATA
-				DDRSS1_PI_02_DATA
-				DDRSS1_PI_03_DATA
-				DDRSS1_PI_04_DATA
-				DDRSS1_PI_05_DATA
-				DDRSS1_PI_06_DATA
-				DDRSS1_PI_07_DATA
-				DDRSS1_PI_08_DATA
-				DDRSS1_PI_09_DATA
-				DDRSS1_PI_10_DATA
-				DDRSS1_PI_11_DATA
-				DDRSS1_PI_12_DATA
-				DDRSS1_PI_13_DATA
-				DDRSS1_PI_14_DATA
-				DDRSS1_PI_15_DATA
-				DDRSS1_PI_16_DATA
-				DDRSS1_PI_17_DATA
-				DDRSS1_PI_18_DATA
-				DDRSS1_PI_19_DATA
-				DDRSS1_PI_20_DATA
-				DDRSS1_PI_21_DATA
-				DDRSS1_PI_22_DATA
-				DDRSS1_PI_23_DATA
-				DDRSS1_PI_24_DATA
-				DDRSS1_PI_25_DATA
-				DDRSS1_PI_26_DATA
-				DDRSS1_PI_27_DATA
-				DDRSS1_PI_28_DATA
-				DDRSS1_PI_29_DATA
-				DDRSS1_PI_30_DATA
-				DDRSS1_PI_31_DATA
-				DDRSS1_PI_32_DATA
-				DDRSS1_PI_33_DATA
-				DDRSS1_PI_34_DATA
-				DDRSS1_PI_35_DATA
-				DDRSS1_PI_36_DATA
-				DDRSS1_PI_37_DATA
-				DDRSS1_PI_38_DATA
-				DDRSS1_PI_39_DATA
-				DDRSS1_PI_40_DATA
-				DDRSS1_PI_41_DATA
-				DDRSS1_PI_42_DATA
-				DDRSS1_PI_43_DATA
-				DDRSS1_PI_44_DATA
-				DDRSS1_PI_45_DATA
-				DDRSS1_PI_46_DATA
-				DDRSS1_PI_47_DATA
-				DDRSS1_PI_48_DATA
-				DDRSS1_PI_49_DATA
-				DDRSS1_PI_50_DATA
-				DDRSS1_PI_51_DATA
-				DDRSS1_PI_52_DATA
-				DDRSS1_PI_53_DATA
-				DDRSS1_PI_54_DATA
-				DDRSS1_PI_55_DATA
-				DDRSS1_PI_56_DATA
-				DDRSS1_PI_57_DATA
-				DDRSS1_PI_58_DATA
-				DDRSS1_PI_59_DATA
-				DDRSS1_PI_60_DATA
-				DDRSS1_PI_61_DATA
-				DDRSS1_PI_62_DATA
-				DDRSS1_PI_63_DATA
-				DDRSS1_PI_64_DATA
-				DDRSS1_PI_65_DATA
-				DDRSS1_PI_66_DATA
-				DDRSS1_PI_67_DATA
-				DDRSS1_PI_68_DATA
-				DDRSS1_PI_69_DATA
-				DDRSS1_PI_70_DATA
-				DDRSS1_PI_71_DATA
-				DDRSS1_PI_72_DATA
-				DDRSS1_PI_73_DATA
-				DDRSS1_PI_74_DATA
-				DDRSS1_PI_75_DATA
-				DDRSS1_PI_76_DATA
-				DDRSS1_PI_77_DATA
-				DDRSS1_PI_78_DATA
-				DDRSS1_PI_79_DATA
-				DDRSS1_PI_80_DATA
-				DDRSS1_PI_81_DATA
-				DDRSS1_PI_82_DATA
-				DDRSS1_PI_83_DATA
-				DDRSS1_PI_84_DATA
-				DDRSS1_PI_85_DATA
-				DDRSS1_PI_86_DATA
-				DDRSS1_PI_87_DATA
-				DDRSS1_PI_88_DATA
-				DDRSS1_PI_89_DATA
-				DDRSS1_PI_90_DATA
-				DDRSS1_PI_91_DATA
-				DDRSS1_PI_92_DATA
-				DDRSS1_PI_93_DATA
-				DDRSS1_PI_94_DATA
-				DDRSS1_PI_95_DATA
-				DDRSS1_PI_96_DATA
-				DDRSS1_PI_97_DATA
-				DDRSS1_PI_98_DATA
-				DDRSS1_PI_99_DATA
-				DDRSS1_PI_100_DATA
-				DDRSS1_PI_101_DATA
-				DDRSS1_PI_102_DATA
-				DDRSS1_PI_103_DATA
-				DDRSS1_PI_104_DATA
-				DDRSS1_PI_105_DATA
-				DDRSS1_PI_106_DATA
-				DDRSS1_PI_107_DATA
-				DDRSS1_PI_108_DATA
-				DDRSS1_PI_109_DATA
-				DDRSS1_PI_110_DATA
-				DDRSS1_PI_111_DATA
-				DDRSS1_PI_112_DATA
-				DDRSS1_PI_113_DATA
-				DDRSS1_PI_114_DATA
-				DDRSS1_PI_115_DATA
-				DDRSS1_PI_116_DATA
-				DDRSS1_PI_117_DATA
-				DDRSS1_PI_118_DATA
-				DDRSS1_PI_119_DATA
-				DDRSS1_PI_120_DATA
-				DDRSS1_PI_121_DATA
-				DDRSS1_PI_122_DATA
-				DDRSS1_PI_123_DATA
-				DDRSS1_PI_124_DATA
-				DDRSS1_PI_125_DATA
-				DDRSS1_PI_126_DATA
-				DDRSS1_PI_127_DATA
-				DDRSS1_PI_128_DATA
-				DDRSS1_PI_129_DATA
-				DDRSS1_PI_130_DATA
-				DDRSS1_PI_131_DATA
-				DDRSS1_PI_132_DATA
-				DDRSS1_PI_133_DATA
-				DDRSS1_PI_134_DATA
-				DDRSS1_PI_135_DATA
-				DDRSS1_PI_136_DATA
-				DDRSS1_PI_137_DATA
-				DDRSS1_PI_138_DATA
-				DDRSS1_PI_139_DATA
-				DDRSS1_PI_140_DATA
-				DDRSS1_PI_141_DATA
-				DDRSS1_PI_142_DATA
-				DDRSS1_PI_143_DATA
-				DDRSS1_PI_144_DATA
-				DDRSS1_PI_145_DATA
-				DDRSS1_PI_146_DATA
-				DDRSS1_PI_147_DATA
-				DDRSS1_PI_148_DATA
-				DDRSS1_PI_149_DATA
-				DDRSS1_PI_150_DATA
-				DDRSS1_PI_151_DATA
-				DDRSS1_PI_152_DATA
-				DDRSS1_PI_153_DATA
-				DDRSS1_PI_154_DATA
-				DDRSS1_PI_155_DATA
-				DDRSS1_PI_156_DATA
-				DDRSS1_PI_157_DATA
-				DDRSS1_PI_158_DATA
-				DDRSS1_PI_159_DATA
-				DDRSS1_PI_160_DATA
-				DDRSS1_PI_161_DATA
-				DDRSS1_PI_162_DATA
-				DDRSS1_PI_163_DATA
-				DDRSS1_PI_164_DATA
-				DDRSS1_PI_165_DATA
-				DDRSS1_PI_166_DATA
-				DDRSS1_PI_167_DATA
-				DDRSS1_PI_168_DATA
-				DDRSS1_PI_169_DATA
-				DDRSS1_PI_170_DATA
-				DDRSS1_PI_171_DATA
-				DDRSS1_PI_172_DATA
-				DDRSS1_PI_173_DATA
-				DDRSS1_PI_174_DATA
-				DDRSS1_PI_175_DATA
-				DDRSS1_PI_176_DATA
-				DDRSS1_PI_177_DATA
-				DDRSS1_PI_178_DATA
-				DDRSS1_PI_179_DATA
-				DDRSS1_PI_180_DATA
-				DDRSS1_PI_181_DATA
-				DDRSS1_PI_182_DATA
-				DDRSS1_PI_183_DATA
-				DDRSS1_PI_184_DATA
-				DDRSS1_PI_185_DATA
-				DDRSS1_PI_186_DATA
-				DDRSS1_PI_187_DATA
-				DDRSS1_PI_188_DATA
-				DDRSS1_PI_189_DATA
-				DDRSS1_PI_190_DATA
-				DDRSS1_PI_191_DATA
-				DDRSS1_PI_192_DATA
-				DDRSS1_PI_193_DATA
-				DDRSS1_PI_194_DATA
-				DDRSS1_PI_195_DATA
-				DDRSS1_PI_196_DATA
-				DDRSS1_PI_197_DATA
-				DDRSS1_PI_198_DATA
-				DDRSS1_PI_199_DATA
-				DDRSS1_PI_200_DATA
-				DDRSS1_PI_201_DATA
-				DDRSS1_PI_202_DATA
-				DDRSS1_PI_203_DATA
-				DDRSS1_PI_204_DATA
-				DDRSS1_PI_205_DATA
-				DDRSS1_PI_206_DATA
-				DDRSS1_PI_207_DATA
-				DDRSS1_PI_208_DATA
-				DDRSS1_PI_209_DATA
-				DDRSS1_PI_210_DATA
-				DDRSS1_PI_211_DATA
-				DDRSS1_PI_212_DATA
-				DDRSS1_PI_213_DATA
-				DDRSS1_PI_214_DATA
-				DDRSS1_PI_215_DATA
-				DDRSS1_PI_216_DATA
-				DDRSS1_PI_217_DATA
-				DDRSS1_PI_218_DATA
-				DDRSS1_PI_219_DATA
-				DDRSS1_PI_220_DATA
-				DDRSS1_PI_221_DATA
-				DDRSS1_PI_222_DATA
-				DDRSS1_PI_223_DATA
-				DDRSS1_PI_224_DATA
-				DDRSS1_PI_225_DATA
-				DDRSS1_PI_226_DATA
-				DDRSS1_PI_227_DATA
-				DDRSS1_PI_228_DATA
-				DDRSS1_PI_229_DATA
-				DDRSS1_PI_230_DATA
-				DDRSS1_PI_231_DATA
-				DDRSS1_PI_232_DATA
-				DDRSS1_PI_233_DATA
-				DDRSS1_PI_234_DATA
-				DDRSS1_PI_235_DATA
-				DDRSS1_PI_236_DATA
-				DDRSS1_PI_237_DATA
-				DDRSS1_PI_238_DATA
-				DDRSS1_PI_239_DATA
-				DDRSS1_PI_240_DATA
-				DDRSS1_PI_241_DATA
-				DDRSS1_PI_242_DATA
-				DDRSS1_PI_243_DATA
-				DDRSS1_PI_244_DATA
-				DDRSS1_PI_245_DATA
-				DDRSS1_PI_246_DATA
-				DDRSS1_PI_247_DATA
-				DDRSS1_PI_248_DATA
-				DDRSS1_PI_249_DATA
-				DDRSS1_PI_250_DATA
-				DDRSS1_PI_251_DATA
-				DDRSS1_PI_252_DATA
-				DDRSS1_PI_253_DATA
-				DDRSS1_PI_254_DATA
-				DDRSS1_PI_255_DATA
-				DDRSS1_PI_256_DATA
-				DDRSS1_PI_257_DATA
-				DDRSS1_PI_258_DATA
-				DDRSS1_PI_259_DATA
-				DDRSS1_PI_260_DATA
-				DDRSS1_PI_261_DATA
-				DDRSS1_PI_262_DATA
-				DDRSS1_PI_263_DATA
-				DDRSS1_PI_264_DATA
-				DDRSS1_PI_265_DATA
-				DDRSS1_PI_266_DATA
-				DDRSS1_PI_267_DATA
-				DDRSS1_PI_268_DATA
-				DDRSS1_PI_269_DATA
-				DDRSS1_PI_270_DATA
-				DDRSS1_PI_271_DATA
-				DDRSS1_PI_272_DATA
-				DDRSS1_PI_273_DATA
-				DDRSS1_PI_274_DATA
-				DDRSS1_PI_275_DATA
-				DDRSS1_PI_276_DATA
-				DDRSS1_PI_277_DATA
-				DDRSS1_PI_278_DATA
-				DDRSS1_PI_279_DATA
-				DDRSS1_PI_280_DATA
-				DDRSS1_PI_281_DATA
-				DDRSS1_PI_282_DATA
-				DDRSS1_PI_283_DATA
-				DDRSS1_PI_284_DATA
-				DDRSS1_PI_285_DATA
-				DDRSS1_PI_286_DATA
-				DDRSS1_PI_287_DATA
-				DDRSS1_PI_288_DATA
-				DDRSS1_PI_289_DATA
-				DDRSS1_PI_290_DATA
-				DDRSS1_PI_291_DATA
-				DDRSS1_PI_292_DATA
-				DDRSS1_PI_293_DATA
-				DDRSS1_PI_294_DATA
-				DDRSS1_PI_295_DATA
-				DDRSS1_PI_296_DATA
-				DDRSS1_PI_297_DATA
-				DDRSS1_PI_298_DATA
-				DDRSS1_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS1_PHY_00_DATA
-				DDRSS1_PHY_01_DATA
-				DDRSS1_PHY_02_DATA
-				DDRSS1_PHY_03_DATA
-				DDRSS1_PHY_04_DATA
-				DDRSS1_PHY_05_DATA
-				DDRSS1_PHY_06_DATA
-				DDRSS1_PHY_07_DATA
-				DDRSS1_PHY_08_DATA
-				DDRSS1_PHY_09_DATA
-				DDRSS1_PHY_10_DATA
-				DDRSS1_PHY_11_DATA
-				DDRSS1_PHY_12_DATA
-				DDRSS1_PHY_13_DATA
-				DDRSS1_PHY_14_DATA
-				DDRSS1_PHY_15_DATA
-				DDRSS1_PHY_16_DATA
-				DDRSS1_PHY_17_DATA
-				DDRSS1_PHY_18_DATA
-				DDRSS1_PHY_19_DATA
-				DDRSS1_PHY_20_DATA
-				DDRSS1_PHY_21_DATA
-				DDRSS1_PHY_22_DATA
-				DDRSS1_PHY_23_DATA
-				DDRSS1_PHY_24_DATA
-				DDRSS1_PHY_25_DATA
-				DDRSS1_PHY_26_DATA
-				DDRSS1_PHY_27_DATA
-				DDRSS1_PHY_28_DATA
-				DDRSS1_PHY_29_DATA
-				DDRSS1_PHY_30_DATA
-				DDRSS1_PHY_31_DATA
-				DDRSS1_PHY_32_DATA
-				DDRSS1_PHY_33_DATA
-				DDRSS1_PHY_34_DATA
-				DDRSS1_PHY_35_DATA
-				DDRSS1_PHY_36_DATA
-				DDRSS1_PHY_37_DATA
-				DDRSS1_PHY_38_DATA
-				DDRSS1_PHY_39_DATA
-				DDRSS1_PHY_40_DATA
-				DDRSS1_PHY_41_DATA
-				DDRSS1_PHY_42_DATA
-				DDRSS1_PHY_43_DATA
-				DDRSS1_PHY_44_DATA
-				DDRSS1_PHY_45_DATA
-				DDRSS1_PHY_46_DATA
-				DDRSS1_PHY_47_DATA
-				DDRSS1_PHY_48_DATA
-				DDRSS1_PHY_49_DATA
-				DDRSS1_PHY_50_DATA
-				DDRSS1_PHY_51_DATA
-				DDRSS1_PHY_52_DATA
-				DDRSS1_PHY_53_DATA
-				DDRSS1_PHY_54_DATA
-				DDRSS1_PHY_55_DATA
-				DDRSS1_PHY_56_DATA
-				DDRSS1_PHY_57_DATA
-				DDRSS1_PHY_58_DATA
-				DDRSS1_PHY_59_DATA
-				DDRSS1_PHY_60_DATA
-				DDRSS1_PHY_61_DATA
-				DDRSS1_PHY_62_DATA
-				DDRSS1_PHY_63_DATA
-				DDRSS1_PHY_64_DATA
-				DDRSS1_PHY_65_DATA
-				DDRSS1_PHY_66_DATA
-				DDRSS1_PHY_67_DATA
-				DDRSS1_PHY_68_DATA
-				DDRSS1_PHY_69_DATA
-				DDRSS1_PHY_70_DATA
-				DDRSS1_PHY_71_DATA
-				DDRSS1_PHY_72_DATA
-				DDRSS1_PHY_73_DATA
-				DDRSS1_PHY_74_DATA
-				DDRSS1_PHY_75_DATA
-				DDRSS1_PHY_76_DATA
-				DDRSS1_PHY_77_DATA
-				DDRSS1_PHY_78_DATA
-				DDRSS1_PHY_79_DATA
-				DDRSS1_PHY_80_DATA
-				DDRSS1_PHY_81_DATA
-				DDRSS1_PHY_82_DATA
-				DDRSS1_PHY_83_DATA
-				DDRSS1_PHY_84_DATA
-				DDRSS1_PHY_85_DATA
-				DDRSS1_PHY_86_DATA
-				DDRSS1_PHY_87_DATA
-				DDRSS1_PHY_88_DATA
-				DDRSS1_PHY_89_DATA
-				DDRSS1_PHY_90_DATA
-				DDRSS1_PHY_91_DATA
-				DDRSS1_PHY_92_DATA
-				DDRSS1_PHY_93_DATA
-				DDRSS1_PHY_94_DATA
-				DDRSS1_PHY_95_DATA
-				DDRSS1_PHY_96_DATA
-				DDRSS1_PHY_97_DATA
-				DDRSS1_PHY_98_DATA
-				DDRSS1_PHY_99_DATA
-				DDRSS1_PHY_100_DATA
-				DDRSS1_PHY_101_DATA
-				DDRSS1_PHY_102_DATA
-				DDRSS1_PHY_103_DATA
-				DDRSS1_PHY_104_DATA
-				DDRSS1_PHY_105_DATA
-				DDRSS1_PHY_106_DATA
-				DDRSS1_PHY_107_DATA
-				DDRSS1_PHY_108_DATA
-				DDRSS1_PHY_109_DATA
-				DDRSS1_PHY_110_DATA
-				DDRSS1_PHY_111_DATA
-				DDRSS1_PHY_112_DATA
-				DDRSS1_PHY_113_DATA
-				DDRSS1_PHY_114_DATA
-				DDRSS1_PHY_115_DATA
-				DDRSS1_PHY_116_DATA
-				DDRSS1_PHY_117_DATA
-				DDRSS1_PHY_118_DATA
-				DDRSS1_PHY_119_DATA
-				DDRSS1_PHY_120_DATA
-				DDRSS1_PHY_121_DATA
-				DDRSS1_PHY_122_DATA
-				DDRSS1_PHY_123_DATA
-				DDRSS1_PHY_124_DATA
-				DDRSS1_PHY_125_DATA
-				DDRSS1_PHY_126_DATA
-				DDRSS1_PHY_127_DATA
-				DDRSS1_PHY_128_DATA
-				DDRSS1_PHY_129_DATA
-				DDRSS1_PHY_130_DATA
-				DDRSS1_PHY_131_DATA
-				DDRSS1_PHY_132_DATA
-				DDRSS1_PHY_133_DATA
-				DDRSS1_PHY_134_DATA
-				DDRSS1_PHY_135_DATA
-				DDRSS1_PHY_136_DATA
-				DDRSS1_PHY_137_DATA
-				DDRSS1_PHY_138_DATA
-				DDRSS1_PHY_139_DATA
-				DDRSS1_PHY_140_DATA
-				DDRSS1_PHY_141_DATA
-				DDRSS1_PHY_142_DATA
-				DDRSS1_PHY_143_DATA
-				DDRSS1_PHY_144_DATA
-				DDRSS1_PHY_145_DATA
-				DDRSS1_PHY_146_DATA
-				DDRSS1_PHY_147_DATA
-				DDRSS1_PHY_148_DATA
-				DDRSS1_PHY_149_DATA
-				DDRSS1_PHY_150_DATA
-				DDRSS1_PHY_151_DATA
-				DDRSS1_PHY_152_DATA
-				DDRSS1_PHY_153_DATA
-				DDRSS1_PHY_154_DATA
-				DDRSS1_PHY_155_DATA
-				DDRSS1_PHY_156_DATA
-				DDRSS1_PHY_157_DATA
-				DDRSS1_PHY_158_DATA
-				DDRSS1_PHY_159_DATA
-				DDRSS1_PHY_160_DATA
-				DDRSS1_PHY_161_DATA
-				DDRSS1_PHY_162_DATA
-				DDRSS1_PHY_163_DATA
-				DDRSS1_PHY_164_DATA
-				DDRSS1_PHY_165_DATA
-				DDRSS1_PHY_166_DATA
-				DDRSS1_PHY_167_DATA
-				DDRSS1_PHY_168_DATA
-				DDRSS1_PHY_169_DATA
-				DDRSS1_PHY_170_DATA
-				DDRSS1_PHY_171_DATA
-				DDRSS1_PHY_172_DATA
-				DDRSS1_PHY_173_DATA
-				DDRSS1_PHY_174_DATA
-				DDRSS1_PHY_175_DATA
-				DDRSS1_PHY_176_DATA
-				DDRSS1_PHY_177_DATA
-				DDRSS1_PHY_178_DATA
-				DDRSS1_PHY_179_DATA
-				DDRSS1_PHY_180_DATA
-				DDRSS1_PHY_181_DATA
-				DDRSS1_PHY_182_DATA
-				DDRSS1_PHY_183_DATA
-				DDRSS1_PHY_184_DATA
-				DDRSS1_PHY_185_DATA
-				DDRSS1_PHY_186_DATA
-				DDRSS1_PHY_187_DATA
-				DDRSS1_PHY_188_DATA
-				DDRSS1_PHY_189_DATA
-				DDRSS1_PHY_190_DATA
-				DDRSS1_PHY_191_DATA
-				DDRSS1_PHY_192_DATA
-				DDRSS1_PHY_193_DATA
-				DDRSS1_PHY_194_DATA
-				DDRSS1_PHY_195_DATA
-				DDRSS1_PHY_196_DATA
-				DDRSS1_PHY_197_DATA
-				DDRSS1_PHY_198_DATA
-				DDRSS1_PHY_199_DATA
-				DDRSS1_PHY_200_DATA
-				DDRSS1_PHY_201_DATA
-				DDRSS1_PHY_202_DATA
-				DDRSS1_PHY_203_DATA
-				DDRSS1_PHY_204_DATA
-				DDRSS1_PHY_205_DATA
-				DDRSS1_PHY_206_DATA
-				DDRSS1_PHY_207_DATA
-				DDRSS1_PHY_208_DATA
-				DDRSS1_PHY_209_DATA
-				DDRSS1_PHY_210_DATA
-				DDRSS1_PHY_211_DATA
-				DDRSS1_PHY_212_DATA
-				DDRSS1_PHY_213_DATA
-				DDRSS1_PHY_214_DATA
-				DDRSS1_PHY_215_DATA
-				DDRSS1_PHY_216_DATA
-				DDRSS1_PHY_217_DATA
-				DDRSS1_PHY_218_DATA
-				DDRSS1_PHY_219_DATA
-				DDRSS1_PHY_220_DATA
-				DDRSS1_PHY_221_DATA
-				DDRSS1_PHY_222_DATA
-				DDRSS1_PHY_223_DATA
-				DDRSS1_PHY_224_DATA
-				DDRSS1_PHY_225_DATA
-				DDRSS1_PHY_226_DATA
-				DDRSS1_PHY_227_DATA
-				DDRSS1_PHY_228_DATA
-				DDRSS1_PHY_229_DATA
-				DDRSS1_PHY_230_DATA
-				DDRSS1_PHY_231_DATA
-				DDRSS1_PHY_232_DATA
-				DDRSS1_PHY_233_DATA
-				DDRSS1_PHY_234_DATA
-				DDRSS1_PHY_235_DATA
-				DDRSS1_PHY_236_DATA
-				DDRSS1_PHY_237_DATA
-				DDRSS1_PHY_238_DATA
-				DDRSS1_PHY_239_DATA
-				DDRSS1_PHY_240_DATA
-				DDRSS1_PHY_241_DATA
-				DDRSS1_PHY_242_DATA
-				DDRSS1_PHY_243_DATA
-				DDRSS1_PHY_244_DATA
-				DDRSS1_PHY_245_DATA
-				DDRSS1_PHY_246_DATA
-				DDRSS1_PHY_247_DATA
-				DDRSS1_PHY_248_DATA
-				DDRSS1_PHY_249_DATA
-				DDRSS1_PHY_250_DATA
-				DDRSS1_PHY_251_DATA
-				DDRSS1_PHY_252_DATA
-				DDRSS1_PHY_253_DATA
-				DDRSS1_PHY_254_DATA
-				DDRSS1_PHY_255_DATA
-				DDRSS1_PHY_256_DATA
-				DDRSS1_PHY_257_DATA
-				DDRSS1_PHY_258_DATA
-				DDRSS1_PHY_259_DATA
-				DDRSS1_PHY_260_DATA
-				DDRSS1_PHY_261_DATA
-				DDRSS1_PHY_262_DATA
-				DDRSS1_PHY_263_DATA
-				DDRSS1_PHY_264_DATA
-				DDRSS1_PHY_265_DATA
-				DDRSS1_PHY_266_DATA
-				DDRSS1_PHY_267_DATA
-				DDRSS1_PHY_268_DATA
-				DDRSS1_PHY_269_DATA
-				DDRSS1_PHY_270_DATA
-				DDRSS1_PHY_271_DATA
-				DDRSS1_PHY_272_DATA
-				DDRSS1_PHY_273_DATA
-				DDRSS1_PHY_274_DATA
-				DDRSS1_PHY_275_DATA
-				DDRSS1_PHY_276_DATA
-				DDRSS1_PHY_277_DATA
-				DDRSS1_PHY_278_DATA
-				DDRSS1_PHY_279_DATA
-				DDRSS1_PHY_280_DATA
-				DDRSS1_PHY_281_DATA
-				DDRSS1_PHY_282_DATA
-				DDRSS1_PHY_283_DATA
-				DDRSS1_PHY_284_DATA
-				DDRSS1_PHY_285_DATA
-				DDRSS1_PHY_286_DATA
-				DDRSS1_PHY_287_DATA
-				DDRSS1_PHY_288_DATA
-				DDRSS1_PHY_289_DATA
-				DDRSS1_PHY_290_DATA
-				DDRSS1_PHY_291_DATA
-				DDRSS1_PHY_292_DATA
-				DDRSS1_PHY_293_DATA
-				DDRSS1_PHY_294_DATA
-				DDRSS1_PHY_295_DATA
-				DDRSS1_PHY_296_DATA
-				DDRSS1_PHY_297_DATA
-				DDRSS1_PHY_298_DATA
-				DDRSS1_PHY_299_DATA
-				DDRSS1_PHY_300_DATA
-				DDRSS1_PHY_301_DATA
-				DDRSS1_PHY_302_DATA
-				DDRSS1_PHY_303_DATA
-				DDRSS1_PHY_304_DATA
-				DDRSS1_PHY_305_DATA
-				DDRSS1_PHY_306_DATA
-				DDRSS1_PHY_307_DATA
-				DDRSS1_PHY_308_DATA
-				DDRSS1_PHY_309_DATA
-				DDRSS1_PHY_310_DATA
-				DDRSS1_PHY_311_DATA
-				DDRSS1_PHY_312_DATA
-				DDRSS1_PHY_313_DATA
-				DDRSS1_PHY_314_DATA
-				DDRSS1_PHY_315_DATA
-				DDRSS1_PHY_316_DATA
-				DDRSS1_PHY_317_DATA
-				DDRSS1_PHY_318_DATA
-				DDRSS1_PHY_319_DATA
-				DDRSS1_PHY_320_DATA
-				DDRSS1_PHY_321_DATA
-				DDRSS1_PHY_322_DATA
-				DDRSS1_PHY_323_DATA
-				DDRSS1_PHY_324_DATA
-				DDRSS1_PHY_325_DATA
-				DDRSS1_PHY_326_DATA
-				DDRSS1_PHY_327_DATA
-				DDRSS1_PHY_328_DATA
-				DDRSS1_PHY_329_DATA
-				DDRSS1_PHY_330_DATA
-				DDRSS1_PHY_331_DATA
-				DDRSS1_PHY_332_DATA
-				DDRSS1_PHY_333_DATA
-				DDRSS1_PHY_334_DATA
-				DDRSS1_PHY_335_DATA
-				DDRSS1_PHY_336_DATA
-				DDRSS1_PHY_337_DATA
-				DDRSS1_PHY_338_DATA
-				DDRSS1_PHY_339_DATA
-				DDRSS1_PHY_340_DATA
-				DDRSS1_PHY_341_DATA
-				DDRSS1_PHY_342_DATA
-				DDRSS1_PHY_343_DATA
-				DDRSS1_PHY_344_DATA
-				DDRSS1_PHY_345_DATA
-				DDRSS1_PHY_346_DATA
-				DDRSS1_PHY_347_DATA
-				DDRSS1_PHY_348_DATA
-				DDRSS1_PHY_349_DATA
-				DDRSS1_PHY_350_DATA
-				DDRSS1_PHY_351_DATA
-				DDRSS1_PHY_352_DATA
-				DDRSS1_PHY_353_DATA
-				DDRSS1_PHY_354_DATA
-				DDRSS1_PHY_355_DATA
-				DDRSS1_PHY_356_DATA
-				DDRSS1_PHY_357_DATA
-				DDRSS1_PHY_358_DATA
-				DDRSS1_PHY_359_DATA
-				DDRSS1_PHY_360_DATA
-				DDRSS1_PHY_361_DATA
-				DDRSS1_PHY_362_DATA
-				DDRSS1_PHY_363_DATA
-				DDRSS1_PHY_364_DATA
-				DDRSS1_PHY_365_DATA
-				DDRSS1_PHY_366_DATA
-				DDRSS1_PHY_367_DATA
-				DDRSS1_PHY_368_DATA
-				DDRSS1_PHY_369_DATA
-				DDRSS1_PHY_370_DATA
-				DDRSS1_PHY_371_DATA
-				DDRSS1_PHY_372_DATA
-				DDRSS1_PHY_373_DATA
-				DDRSS1_PHY_374_DATA
-				DDRSS1_PHY_375_DATA
-				DDRSS1_PHY_376_DATA
-				DDRSS1_PHY_377_DATA
-				DDRSS1_PHY_378_DATA
-				DDRSS1_PHY_379_DATA
-				DDRSS1_PHY_380_DATA
-				DDRSS1_PHY_381_DATA
-				DDRSS1_PHY_382_DATA
-				DDRSS1_PHY_383_DATA
-				DDRSS1_PHY_384_DATA
-				DDRSS1_PHY_385_DATA
-				DDRSS1_PHY_386_DATA
-				DDRSS1_PHY_387_DATA
-				DDRSS1_PHY_388_DATA
-				DDRSS1_PHY_389_DATA
-				DDRSS1_PHY_390_DATA
-				DDRSS1_PHY_391_DATA
-				DDRSS1_PHY_392_DATA
-				DDRSS1_PHY_393_DATA
-				DDRSS1_PHY_394_DATA
-				DDRSS1_PHY_395_DATA
-				DDRSS1_PHY_396_DATA
-				DDRSS1_PHY_397_DATA
-				DDRSS1_PHY_398_DATA
-				DDRSS1_PHY_399_DATA
-				DDRSS1_PHY_400_DATA
-				DDRSS1_PHY_401_DATA
-				DDRSS1_PHY_402_DATA
-				DDRSS1_PHY_403_DATA
-				DDRSS1_PHY_404_DATA
-				DDRSS1_PHY_405_DATA
-				DDRSS1_PHY_406_DATA
-				DDRSS1_PHY_407_DATA
-				DDRSS1_PHY_408_DATA
-				DDRSS1_PHY_409_DATA
-				DDRSS1_PHY_410_DATA
-				DDRSS1_PHY_411_DATA
-				DDRSS1_PHY_412_DATA
-				DDRSS1_PHY_413_DATA
-				DDRSS1_PHY_414_DATA
-				DDRSS1_PHY_415_DATA
-				DDRSS1_PHY_416_DATA
-				DDRSS1_PHY_417_DATA
-				DDRSS1_PHY_418_DATA
-				DDRSS1_PHY_419_DATA
-				DDRSS1_PHY_420_DATA
-				DDRSS1_PHY_421_DATA
-				DDRSS1_PHY_422_DATA
-				DDRSS1_PHY_423_DATA
-				DDRSS1_PHY_424_DATA
-				DDRSS1_PHY_425_DATA
-				DDRSS1_PHY_426_DATA
-				DDRSS1_PHY_427_DATA
-				DDRSS1_PHY_428_DATA
-				DDRSS1_PHY_429_DATA
-				DDRSS1_PHY_430_DATA
-				DDRSS1_PHY_431_DATA
-				DDRSS1_PHY_432_DATA
-				DDRSS1_PHY_433_DATA
-				DDRSS1_PHY_434_DATA
-				DDRSS1_PHY_435_DATA
-				DDRSS1_PHY_436_DATA
-				DDRSS1_PHY_437_DATA
-				DDRSS1_PHY_438_DATA
-				DDRSS1_PHY_439_DATA
-				DDRSS1_PHY_440_DATA
-				DDRSS1_PHY_441_DATA
-				DDRSS1_PHY_442_DATA
-				DDRSS1_PHY_443_DATA
-				DDRSS1_PHY_444_DATA
-				DDRSS1_PHY_445_DATA
-				DDRSS1_PHY_446_DATA
-				DDRSS1_PHY_447_DATA
-				DDRSS1_PHY_448_DATA
-				DDRSS1_PHY_449_DATA
-				DDRSS1_PHY_450_DATA
-				DDRSS1_PHY_451_DATA
-				DDRSS1_PHY_452_DATA
-				DDRSS1_PHY_453_DATA
-				DDRSS1_PHY_454_DATA
-				DDRSS1_PHY_455_DATA
-				DDRSS1_PHY_456_DATA
-				DDRSS1_PHY_457_DATA
-				DDRSS1_PHY_458_DATA
-				DDRSS1_PHY_459_DATA
-				DDRSS1_PHY_460_DATA
-				DDRSS1_PHY_461_DATA
-				DDRSS1_PHY_462_DATA
-				DDRSS1_PHY_463_DATA
-				DDRSS1_PHY_464_DATA
-				DDRSS1_PHY_465_DATA
-				DDRSS1_PHY_466_DATA
-				DDRSS1_PHY_467_DATA
-				DDRSS1_PHY_468_DATA
-				DDRSS1_PHY_469_DATA
-				DDRSS1_PHY_470_DATA
-				DDRSS1_PHY_471_DATA
-				DDRSS1_PHY_472_DATA
-				DDRSS1_PHY_473_DATA
-				DDRSS1_PHY_474_DATA
-				DDRSS1_PHY_475_DATA
-				DDRSS1_PHY_476_DATA
-				DDRSS1_PHY_477_DATA
-				DDRSS1_PHY_478_DATA
-				DDRSS1_PHY_479_DATA
-				DDRSS1_PHY_480_DATA
-				DDRSS1_PHY_481_DATA
-				DDRSS1_PHY_482_DATA
-				DDRSS1_PHY_483_DATA
-				DDRSS1_PHY_484_DATA
-				DDRSS1_PHY_485_DATA
-				DDRSS1_PHY_486_DATA
-				DDRSS1_PHY_487_DATA
-				DDRSS1_PHY_488_DATA
-				DDRSS1_PHY_489_DATA
-				DDRSS1_PHY_490_DATA
-				DDRSS1_PHY_491_DATA
-				DDRSS1_PHY_492_DATA
-				DDRSS1_PHY_493_DATA
-				DDRSS1_PHY_494_DATA
-				DDRSS1_PHY_495_DATA
-				DDRSS1_PHY_496_DATA
-				DDRSS1_PHY_497_DATA
-				DDRSS1_PHY_498_DATA
-				DDRSS1_PHY_499_DATA
-				DDRSS1_PHY_500_DATA
-				DDRSS1_PHY_501_DATA
-				DDRSS1_PHY_502_DATA
-				DDRSS1_PHY_503_DATA
-				DDRSS1_PHY_504_DATA
-				DDRSS1_PHY_505_DATA
-				DDRSS1_PHY_506_DATA
-				DDRSS1_PHY_507_DATA
-				DDRSS1_PHY_508_DATA
-				DDRSS1_PHY_509_DATA
-				DDRSS1_PHY_510_DATA
-				DDRSS1_PHY_511_DATA
-				DDRSS1_PHY_512_DATA
-				DDRSS1_PHY_513_DATA
-				DDRSS1_PHY_514_DATA
-				DDRSS1_PHY_515_DATA
-				DDRSS1_PHY_516_DATA
-				DDRSS1_PHY_517_DATA
-				DDRSS1_PHY_518_DATA
-				DDRSS1_PHY_519_DATA
-				DDRSS1_PHY_520_DATA
-				DDRSS1_PHY_521_DATA
-				DDRSS1_PHY_522_DATA
-				DDRSS1_PHY_523_DATA
-				DDRSS1_PHY_524_DATA
-				DDRSS1_PHY_525_DATA
-				DDRSS1_PHY_526_DATA
-				DDRSS1_PHY_527_DATA
-				DDRSS1_PHY_528_DATA
-				DDRSS1_PHY_529_DATA
-				DDRSS1_PHY_530_DATA
-				DDRSS1_PHY_531_DATA
-				DDRSS1_PHY_532_DATA
-				DDRSS1_PHY_533_DATA
-				DDRSS1_PHY_534_DATA
-				DDRSS1_PHY_535_DATA
-				DDRSS1_PHY_536_DATA
-				DDRSS1_PHY_537_DATA
-				DDRSS1_PHY_538_DATA
-				DDRSS1_PHY_539_DATA
-				DDRSS1_PHY_540_DATA
-				DDRSS1_PHY_541_DATA
-				DDRSS1_PHY_542_DATA
-				DDRSS1_PHY_543_DATA
-				DDRSS1_PHY_544_DATA
-				DDRSS1_PHY_545_DATA
-				DDRSS1_PHY_546_DATA
-				DDRSS1_PHY_547_DATA
-				DDRSS1_PHY_548_DATA
-				DDRSS1_PHY_549_DATA
-				DDRSS1_PHY_550_DATA
-				DDRSS1_PHY_551_DATA
-				DDRSS1_PHY_552_DATA
-				DDRSS1_PHY_553_DATA
-				DDRSS1_PHY_554_DATA
-				DDRSS1_PHY_555_DATA
-				DDRSS1_PHY_556_DATA
-				DDRSS1_PHY_557_DATA
-				DDRSS1_PHY_558_DATA
-				DDRSS1_PHY_559_DATA
-				DDRSS1_PHY_560_DATA
-				DDRSS1_PHY_561_DATA
-				DDRSS1_PHY_562_DATA
-				DDRSS1_PHY_563_DATA
-				DDRSS1_PHY_564_DATA
-				DDRSS1_PHY_565_DATA
-				DDRSS1_PHY_566_DATA
-				DDRSS1_PHY_567_DATA
-				DDRSS1_PHY_568_DATA
-				DDRSS1_PHY_569_DATA
-				DDRSS1_PHY_570_DATA
-				DDRSS1_PHY_571_DATA
-				DDRSS1_PHY_572_DATA
-				DDRSS1_PHY_573_DATA
-				DDRSS1_PHY_574_DATA
-				DDRSS1_PHY_575_DATA
-				DDRSS1_PHY_576_DATA
-				DDRSS1_PHY_577_DATA
-				DDRSS1_PHY_578_DATA
-				DDRSS1_PHY_579_DATA
-				DDRSS1_PHY_580_DATA
-				DDRSS1_PHY_581_DATA
-				DDRSS1_PHY_582_DATA
-				DDRSS1_PHY_583_DATA
-				DDRSS1_PHY_584_DATA
-				DDRSS1_PHY_585_DATA
-				DDRSS1_PHY_586_DATA
-				DDRSS1_PHY_587_DATA
-				DDRSS1_PHY_588_DATA
-				DDRSS1_PHY_589_DATA
-				DDRSS1_PHY_590_DATA
-				DDRSS1_PHY_591_DATA
-				DDRSS1_PHY_592_DATA
-				DDRSS1_PHY_593_DATA
-				DDRSS1_PHY_594_DATA
-				DDRSS1_PHY_595_DATA
-				DDRSS1_PHY_596_DATA
-				DDRSS1_PHY_597_DATA
-				DDRSS1_PHY_598_DATA
-				DDRSS1_PHY_599_DATA
-				DDRSS1_PHY_600_DATA
-				DDRSS1_PHY_601_DATA
-				DDRSS1_PHY_602_DATA
-				DDRSS1_PHY_603_DATA
-				DDRSS1_PHY_604_DATA
-				DDRSS1_PHY_605_DATA
-				DDRSS1_PHY_606_DATA
-				DDRSS1_PHY_607_DATA
-				DDRSS1_PHY_608_DATA
-				DDRSS1_PHY_609_DATA
-				DDRSS1_PHY_610_DATA
-				DDRSS1_PHY_611_DATA
-				DDRSS1_PHY_612_DATA
-				DDRSS1_PHY_613_DATA
-				DDRSS1_PHY_614_DATA
-				DDRSS1_PHY_615_DATA
-				DDRSS1_PHY_616_DATA
-				DDRSS1_PHY_617_DATA
-				DDRSS1_PHY_618_DATA
-				DDRSS1_PHY_619_DATA
-				DDRSS1_PHY_620_DATA
-				DDRSS1_PHY_621_DATA
-				DDRSS1_PHY_622_DATA
-				DDRSS1_PHY_623_DATA
-				DDRSS1_PHY_624_DATA
-				DDRSS1_PHY_625_DATA
-				DDRSS1_PHY_626_DATA
-				DDRSS1_PHY_627_DATA
-				DDRSS1_PHY_628_DATA
-				DDRSS1_PHY_629_DATA
-				DDRSS1_PHY_630_DATA
-				DDRSS1_PHY_631_DATA
-				DDRSS1_PHY_632_DATA
-				DDRSS1_PHY_633_DATA
-				DDRSS1_PHY_634_DATA
-				DDRSS1_PHY_635_DATA
-				DDRSS1_PHY_636_DATA
-				DDRSS1_PHY_637_DATA
-				DDRSS1_PHY_638_DATA
-				DDRSS1_PHY_639_DATA
-				DDRSS1_PHY_640_DATA
-				DDRSS1_PHY_641_DATA
-				DDRSS1_PHY_642_DATA
-				DDRSS1_PHY_643_DATA
-				DDRSS1_PHY_644_DATA
-				DDRSS1_PHY_645_DATA
-				DDRSS1_PHY_646_DATA
-				DDRSS1_PHY_647_DATA
-				DDRSS1_PHY_648_DATA
-				DDRSS1_PHY_649_DATA
-				DDRSS1_PHY_650_DATA
-				DDRSS1_PHY_651_DATA
-				DDRSS1_PHY_652_DATA
-				DDRSS1_PHY_653_DATA
-				DDRSS1_PHY_654_DATA
-				DDRSS1_PHY_655_DATA
-				DDRSS1_PHY_656_DATA
-				DDRSS1_PHY_657_DATA
-				DDRSS1_PHY_658_DATA
-				DDRSS1_PHY_659_DATA
-				DDRSS1_PHY_660_DATA
-				DDRSS1_PHY_661_DATA
-				DDRSS1_PHY_662_DATA
-				DDRSS1_PHY_663_DATA
-				DDRSS1_PHY_664_DATA
-				DDRSS1_PHY_665_DATA
-				DDRSS1_PHY_666_DATA
-				DDRSS1_PHY_667_DATA
-				DDRSS1_PHY_668_DATA
-				DDRSS1_PHY_669_DATA
-				DDRSS1_PHY_670_DATA
-				DDRSS1_PHY_671_DATA
-				DDRSS1_PHY_672_DATA
-				DDRSS1_PHY_673_DATA
-				DDRSS1_PHY_674_DATA
-				DDRSS1_PHY_675_DATA
-				DDRSS1_PHY_676_DATA
-				DDRSS1_PHY_677_DATA
-				DDRSS1_PHY_678_DATA
-				DDRSS1_PHY_679_DATA
-				DDRSS1_PHY_680_DATA
-				DDRSS1_PHY_681_DATA
-				DDRSS1_PHY_682_DATA
-				DDRSS1_PHY_683_DATA
-				DDRSS1_PHY_684_DATA
-				DDRSS1_PHY_685_DATA
-				DDRSS1_PHY_686_DATA
-				DDRSS1_PHY_687_DATA
-				DDRSS1_PHY_688_DATA
-				DDRSS1_PHY_689_DATA
-				DDRSS1_PHY_690_DATA
-				DDRSS1_PHY_691_DATA
-				DDRSS1_PHY_692_DATA
-				DDRSS1_PHY_693_DATA
-				DDRSS1_PHY_694_DATA
-				DDRSS1_PHY_695_DATA
-				DDRSS1_PHY_696_DATA
-				DDRSS1_PHY_697_DATA
-				DDRSS1_PHY_698_DATA
-				DDRSS1_PHY_699_DATA
-				DDRSS1_PHY_700_DATA
-				DDRSS1_PHY_701_DATA
-				DDRSS1_PHY_702_DATA
-				DDRSS1_PHY_703_DATA
-				DDRSS1_PHY_704_DATA
-				DDRSS1_PHY_705_DATA
-				DDRSS1_PHY_706_DATA
-				DDRSS1_PHY_707_DATA
-				DDRSS1_PHY_708_DATA
-				DDRSS1_PHY_709_DATA
-				DDRSS1_PHY_710_DATA
-				DDRSS1_PHY_711_DATA
-				DDRSS1_PHY_712_DATA
-				DDRSS1_PHY_713_DATA
-				DDRSS1_PHY_714_DATA
-				DDRSS1_PHY_715_DATA
-				DDRSS1_PHY_716_DATA
-				DDRSS1_PHY_717_DATA
-				DDRSS1_PHY_718_DATA
-				DDRSS1_PHY_719_DATA
-				DDRSS1_PHY_720_DATA
-				DDRSS1_PHY_721_DATA
-				DDRSS1_PHY_722_DATA
-				DDRSS1_PHY_723_DATA
-				DDRSS1_PHY_724_DATA
-				DDRSS1_PHY_725_DATA
-				DDRSS1_PHY_726_DATA
-				DDRSS1_PHY_727_DATA
-				DDRSS1_PHY_728_DATA
-				DDRSS1_PHY_729_DATA
-				DDRSS1_PHY_730_DATA
-				DDRSS1_PHY_731_DATA
-				DDRSS1_PHY_732_DATA
-				DDRSS1_PHY_733_DATA
-				DDRSS1_PHY_734_DATA
-				DDRSS1_PHY_735_DATA
-				DDRSS1_PHY_736_DATA
-				DDRSS1_PHY_737_DATA
-				DDRSS1_PHY_738_DATA
-				DDRSS1_PHY_739_DATA
-				DDRSS1_PHY_740_DATA
-				DDRSS1_PHY_741_DATA
-				DDRSS1_PHY_742_DATA
-				DDRSS1_PHY_743_DATA
-				DDRSS1_PHY_744_DATA
-				DDRSS1_PHY_745_DATA
-				DDRSS1_PHY_746_DATA
-				DDRSS1_PHY_747_DATA
-				DDRSS1_PHY_748_DATA
-				DDRSS1_PHY_749_DATA
-				DDRSS1_PHY_750_DATA
-				DDRSS1_PHY_751_DATA
-				DDRSS1_PHY_752_DATA
-				DDRSS1_PHY_753_DATA
-				DDRSS1_PHY_754_DATA
-				DDRSS1_PHY_755_DATA
-				DDRSS1_PHY_756_DATA
-				DDRSS1_PHY_757_DATA
-				DDRSS1_PHY_758_DATA
-				DDRSS1_PHY_759_DATA
-				DDRSS1_PHY_760_DATA
-				DDRSS1_PHY_761_DATA
-				DDRSS1_PHY_762_DATA
-				DDRSS1_PHY_763_DATA
-				DDRSS1_PHY_764_DATA
-				DDRSS1_PHY_765_DATA
-				DDRSS1_PHY_766_DATA
-				DDRSS1_PHY_767_DATA
-				DDRSS1_PHY_768_DATA
-				DDRSS1_PHY_769_DATA
-				DDRSS1_PHY_770_DATA
-				DDRSS1_PHY_771_DATA
-				DDRSS1_PHY_772_DATA
-				DDRSS1_PHY_773_DATA
-				DDRSS1_PHY_774_DATA
-				DDRSS1_PHY_775_DATA
-				DDRSS1_PHY_776_DATA
-				DDRSS1_PHY_777_DATA
-				DDRSS1_PHY_778_DATA
-				DDRSS1_PHY_779_DATA
-				DDRSS1_PHY_780_DATA
-				DDRSS1_PHY_781_DATA
-				DDRSS1_PHY_782_DATA
-				DDRSS1_PHY_783_DATA
-				DDRSS1_PHY_784_DATA
-				DDRSS1_PHY_785_DATA
-				DDRSS1_PHY_786_DATA
-				DDRSS1_PHY_787_DATA
-				DDRSS1_PHY_788_DATA
-				DDRSS1_PHY_789_DATA
-				DDRSS1_PHY_790_DATA
-				DDRSS1_PHY_791_DATA
-				DDRSS1_PHY_792_DATA
-				DDRSS1_PHY_793_DATA
-				DDRSS1_PHY_794_DATA
-				DDRSS1_PHY_795_DATA
-				DDRSS1_PHY_796_DATA
-				DDRSS1_PHY_797_DATA
-				DDRSS1_PHY_798_DATA
-				DDRSS1_PHY_799_DATA
-				DDRSS1_PHY_800_DATA
-				DDRSS1_PHY_801_DATA
-				DDRSS1_PHY_802_DATA
-				DDRSS1_PHY_803_DATA
-				DDRSS1_PHY_804_DATA
-				DDRSS1_PHY_805_DATA
-				DDRSS1_PHY_806_DATA
-				DDRSS1_PHY_807_DATA
-				DDRSS1_PHY_808_DATA
-				DDRSS1_PHY_809_DATA
-				DDRSS1_PHY_810_DATA
-				DDRSS1_PHY_811_DATA
-				DDRSS1_PHY_812_DATA
-				DDRSS1_PHY_813_DATA
-				DDRSS1_PHY_814_DATA
-				DDRSS1_PHY_815_DATA
-				DDRSS1_PHY_816_DATA
-				DDRSS1_PHY_817_DATA
-				DDRSS1_PHY_818_DATA
-				DDRSS1_PHY_819_DATA
-				DDRSS1_PHY_820_DATA
-				DDRSS1_PHY_821_DATA
-				DDRSS1_PHY_822_DATA
-				DDRSS1_PHY_823_DATA
-				DDRSS1_PHY_824_DATA
-				DDRSS1_PHY_825_DATA
-				DDRSS1_PHY_826_DATA
-				DDRSS1_PHY_827_DATA
-				DDRSS1_PHY_828_DATA
-				DDRSS1_PHY_829_DATA
-				DDRSS1_PHY_830_DATA
-				DDRSS1_PHY_831_DATA
-				DDRSS1_PHY_832_DATA
-				DDRSS1_PHY_833_DATA
-				DDRSS1_PHY_834_DATA
-				DDRSS1_PHY_835_DATA
-				DDRSS1_PHY_836_DATA
-				DDRSS1_PHY_837_DATA
-				DDRSS1_PHY_838_DATA
-				DDRSS1_PHY_839_DATA
-				DDRSS1_PHY_840_DATA
-				DDRSS1_PHY_841_DATA
-				DDRSS1_PHY_842_DATA
-				DDRSS1_PHY_843_DATA
-				DDRSS1_PHY_844_DATA
-				DDRSS1_PHY_845_DATA
-				DDRSS1_PHY_846_DATA
-				DDRSS1_PHY_847_DATA
-				DDRSS1_PHY_848_DATA
-				DDRSS1_PHY_849_DATA
-				DDRSS1_PHY_850_DATA
-				DDRSS1_PHY_851_DATA
-				DDRSS1_PHY_852_DATA
-				DDRSS1_PHY_853_DATA
-				DDRSS1_PHY_854_DATA
-				DDRSS1_PHY_855_DATA
-				DDRSS1_PHY_856_DATA
-				DDRSS1_PHY_857_DATA
-				DDRSS1_PHY_858_DATA
-				DDRSS1_PHY_859_DATA
-				DDRSS1_PHY_860_DATA
-				DDRSS1_PHY_861_DATA
-				DDRSS1_PHY_862_DATA
-				DDRSS1_PHY_863_DATA
-				DDRSS1_PHY_864_DATA
-				DDRSS1_PHY_865_DATA
-				DDRSS1_PHY_866_DATA
-				DDRSS1_PHY_867_DATA
-				DDRSS1_PHY_868_DATA
-				DDRSS1_PHY_869_DATA
-				DDRSS1_PHY_870_DATA
-				DDRSS1_PHY_871_DATA
-				DDRSS1_PHY_872_DATA
-				DDRSS1_PHY_873_DATA
-				DDRSS1_PHY_874_DATA
-				DDRSS1_PHY_875_DATA
-				DDRSS1_PHY_876_DATA
-				DDRSS1_PHY_877_DATA
-				DDRSS1_PHY_878_DATA
-				DDRSS1_PHY_879_DATA
-				DDRSS1_PHY_880_DATA
-				DDRSS1_PHY_881_DATA
-				DDRSS1_PHY_882_DATA
-				DDRSS1_PHY_883_DATA
-				DDRSS1_PHY_884_DATA
-				DDRSS1_PHY_885_DATA
-				DDRSS1_PHY_886_DATA
-				DDRSS1_PHY_887_DATA
-				DDRSS1_PHY_888_DATA
-				DDRSS1_PHY_889_DATA
-				DDRSS1_PHY_890_DATA
-				DDRSS1_PHY_891_DATA
-				DDRSS1_PHY_892_DATA
-				DDRSS1_PHY_893_DATA
-				DDRSS1_PHY_894_DATA
-				DDRSS1_PHY_895_DATA
-				DDRSS1_PHY_896_DATA
-				DDRSS1_PHY_897_DATA
-				DDRSS1_PHY_898_DATA
-				DDRSS1_PHY_899_DATA
-				DDRSS1_PHY_900_DATA
-				DDRSS1_PHY_901_DATA
-				DDRSS1_PHY_902_DATA
-				DDRSS1_PHY_903_DATA
-				DDRSS1_PHY_904_DATA
-				DDRSS1_PHY_905_DATA
-				DDRSS1_PHY_906_DATA
-				DDRSS1_PHY_907_DATA
-				DDRSS1_PHY_908_DATA
-				DDRSS1_PHY_909_DATA
-				DDRSS1_PHY_910_DATA
-				DDRSS1_PHY_911_DATA
-				DDRSS1_PHY_912_DATA
-				DDRSS1_PHY_913_DATA
-				DDRSS1_PHY_914_DATA
-				DDRSS1_PHY_915_DATA
-				DDRSS1_PHY_916_DATA
-				DDRSS1_PHY_917_DATA
-				DDRSS1_PHY_918_DATA
-				DDRSS1_PHY_919_DATA
-				DDRSS1_PHY_920_DATA
-				DDRSS1_PHY_921_DATA
-				DDRSS1_PHY_922_DATA
-				DDRSS1_PHY_923_DATA
-				DDRSS1_PHY_924_DATA
-				DDRSS1_PHY_925_DATA
-				DDRSS1_PHY_926_DATA
-				DDRSS1_PHY_927_DATA
-				DDRSS1_PHY_928_DATA
-				DDRSS1_PHY_929_DATA
-				DDRSS1_PHY_930_DATA
-				DDRSS1_PHY_931_DATA
-				DDRSS1_PHY_932_DATA
-				DDRSS1_PHY_933_DATA
-				DDRSS1_PHY_934_DATA
-				DDRSS1_PHY_935_DATA
-				DDRSS1_PHY_936_DATA
-				DDRSS1_PHY_937_DATA
-				DDRSS1_PHY_938_DATA
-				DDRSS1_PHY_939_DATA
-				DDRSS1_PHY_940_DATA
-				DDRSS1_PHY_941_DATA
-				DDRSS1_PHY_942_DATA
-				DDRSS1_PHY_943_DATA
-				DDRSS1_PHY_944_DATA
-				DDRSS1_PHY_945_DATA
-				DDRSS1_PHY_946_DATA
-				DDRSS1_PHY_947_DATA
-				DDRSS1_PHY_948_DATA
-				DDRSS1_PHY_949_DATA
-				DDRSS1_PHY_950_DATA
-				DDRSS1_PHY_951_DATA
-				DDRSS1_PHY_952_DATA
-				DDRSS1_PHY_953_DATA
-				DDRSS1_PHY_954_DATA
-				DDRSS1_PHY_955_DATA
-				DDRSS1_PHY_956_DATA
-				DDRSS1_PHY_957_DATA
-				DDRSS1_PHY_958_DATA
-				DDRSS1_PHY_959_DATA
-				DDRSS1_PHY_960_DATA
-				DDRSS1_PHY_961_DATA
-				DDRSS1_PHY_962_DATA
-				DDRSS1_PHY_963_DATA
-				DDRSS1_PHY_964_DATA
-				DDRSS1_PHY_965_DATA
-				DDRSS1_PHY_966_DATA
-				DDRSS1_PHY_967_DATA
-				DDRSS1_PHY_968_DATA
-				DDRSS1_PHY_969_DATA
-				DDRSS1_PHY_970_DATA
-				DDRSS1_PHY_971_DATA
-				DDRSS1_PHY_972_DATA
-				DDRSS1_PHY_973_DATA
-				DDRSS1_PHY_974_DATA
-				DDRSS1_PHY_975_DATA
-				DDRSS1_PHY_976_DATA
-				DDRSS1_PHY_977_DATA
-				DDRSS1_PHY_978_DATA
-				DDRSS1_PHY_979_DATA
-				DDRSS1_PHY_980_DATA
-				DDRSS1_PHY_981_DATA
-				DDRSS1_PHY_982_DATA
-				DDRSS1_PHY_983_DATA
-				DDRSS1_PHY_984_DATA
-				DDRSS1_PHY_985_DATA
-				DDRSS1_PHY_986_DATA
-				DDRSS1_PHY_987_DATA
-				DDRSS1_PHY_988_DATA
-				DDRSS1_PHY_989_DATA
-				DDRSS1_PHY_990_DATA
-				DDRSS1_PHY_991_DATA
-				DDRSS1_PHY_992_DATA
-				DDRSS1_PHY_993_DATA
-				DDRSS1_PHY_994_DATA
-				DDRSS1_PHY_995_DATA
-				DDRSS1_PHY_996_DATA
-				DDRSS1_PHY_997_DATA
-				DDRSS1_PHY_998_DATA
-				DDRSS1_PHY_999_DATA
-				DDRSS1_PHY_1000_DATA
-				DDRSS1_PHY_1001_DATA
-				DDRSS1_PHY_1002_DATA
-				DDRSS1_PHY_1003_DATA
-				DDRSS1_PHY_1004_DATA
-				DDRSS1_PHY_1005_DATA
-				DDRSS1_PHY_1006_DATA
-				DDRSS1_PHY_1007_DATA
-				DDRSS1_PHY_1008_DATA
-				DDRSS1_PHY_1009_DATA
-				DDRSS1_PHY_1010_DATA
-				DDRSS1_PHY_1011_DATA
-				DDRSS1_PHY_1012_DATA
-				DDRSS1_PHY_1013_DATA
-				DDRSS1_PHY_1014_DATA
-				DDRSS1_PHY_1015_DATA
-				DDRSS1_PHY_1016_DATA
-				DDRSS1_PHY_1017_DATA
-				DDRSS1_PHY_1018_DATA
-				DDRSS1_PHY_1019_DATA
-				DDRSS1_PHY_1020_DATA
-				DDRSS1_PHY_1021_DATA
-				DDRSS1_PHY_1022_DATA
-				DDRSS1_PHY_1023_DATA
-				DDRSS1_PHY_1024_DATA
-				DDRSS1_PHY_1025_DATA
-				DDRSS1_PHY_1026_DATA
-				DDRSS1_PHY_1027_DATA
-				DDRSS1_PHY_1028_DATA
-				DDRSS1_PHY_1029_DATA
-				DDRSS1_PHY_1030_DATA
-				DDRSS1_PHY_1031_DATA
-				DDRSS1_PHY_1032_DATA
-				DDRSS1_PHY_1033_DATA
-				DDRSS1_PHY_1034_DATA
-				DDRSS1_PHY_1035_DATA
-				DDRSS1_PHY_1036_DATA
-				DDRSS1_PHY_1037_DATA
-				DDRSS1_PHY_1038_DATA
-				DDRSS1_PHY_1039_DATA
-				DDRSS1_PHY_1040_DATA
-				DDRSS1_PHY_1041_DATA
-				DDRSS1_PHY_1042_DATA
-				DDRSS1_PHY_1043_DATA
-				DDRSS1_PHY_1044_DATA
-				DDRSS1_PHY_1045_DATA
-				DDRSS1_PHY_1046_DATA
-				DDRSS1_PHY_1047_DATA
-				DDRSS1_PHY_1048_DATA
-				DDRSS1_PHY_1049_DATA
-				DDRSS1_PHY_1050_DATA
-				DDRSS1_PHY_1051_DATA
-				DDRSS1_PHY_1052_DATA
-				DDRSS1_PHY_1053_DATA
-				DDRSS1_PHY_1054_DATA
-				DDRSS1_PHY_1055_DATA
-				DDRSS1_PHY_1056_DATA
-				DDRSS1_PHY_1057_DATA
-				DDRSS1_PHY_1058_DATA
-				DDRSS1_PHY_1059_DATA
-				DDRSS1_PHY_1060_DATA
-				DDRSS1_PHY_1061_DATA
-				DDRSS1_PHY_1062_DATA
-				DDRSS1_PHY_1063_DATA
-				DDRSS1_PHY_1064_DATA
-				DDRSS1_PHY_1065_DATA
-				DDRSS1_PHY_1066_DATA
-				DDRSS1_PHY_1067_DATA
-				DDRSS1_PHY_1068_DATA
-				DDRSS1_PHY_1069_DATA
-				DDRSS1_PHY_1070_DATA
-				DDRSS1_PHY_1071_DATA
-				DDRSS1_PHY_1072_DATA
-				DDRSS1_PHY_1073_DATA
-				DDRSS1_PHY_1074_DATA
-				DDRSS1_PHY_1075_DATA
-				DDRSS1_PHY_1076_DATA
-				DDRSS1_PHY_1077_DATA
-				DDRSS1_PHY_1078_DATA
-				DDRSS1_PHY_1079_DATA
-				DDRSS1_PHY_1080_DATA
-				DDRSS1_PHY_1081_DATA
-				DDRSS1_PHY_1082_DATA
-				DDRSS1_PHY_1083_DATA
-				DDRSS1_PHY_1084_DATA
-				DDRSS1_PHY_1085_DATA
-				DDRSS1_PHY_1086_DATA
-				DDRSS1_PHY_1087_DATA
-				DDRSS1_PHY_1088_DATA
-				DDRSS1_PHY_1089_DATA
-				DDRSS1_PHY_1090_DATA
-				DDRSS1_PHY_1091_DATA
-				DDRSS1_PHY_1092_DATA
-				DDRSS1_PHY_1093_DATA
-				DDRSS1_PHY_1094_DATA
-				DDRSS1_PHY_1095_DATA
-				DDRSS1_PHY_1096_DATA
-				DDRSS1_PHY_1097_DATA
-				DDRSS1_PHY_1098_DATA
-				DDRSS1_PHY_1099_DATA
-				DDRSS1_PHY_1100_DATA
-				DDRSS1_PHY_1101_DATA
-				DDRSS1_PHY_1102_DATA
-				DDRSS1_PHY_1103_DATA
-				DDRSS1_PHY_1104_DATA
-				DDRSS1_PHY_1105_DATA
-				DDRSS1_PHY_1106_DATA
-				DDRSS1_PHY_1107_DATA
-				DDRSS1_PHY_1108_DATA
-				DDRSS1_PHY_1109_DATA
-				DDRSS1_PHY_1110_DATA
-				DDRSS1_PHY_1111_DATA
-				DDRSS1_PHY_1112_DATA
-				DDRSS1_PHY_1113_DATA
-				DDRSS1_PHY_1114_DATA
-				DDRSS1_PHY_1115_DATA
-				DDRSS1_PHY_1116_DATA
-				DDRSS1_PHY_1117_DATA
-				DDRSS1_PHY_1118_DATA
-				DDRSS1_PHY_1119_DATA
-				DDRSS1_PHY_1120_DATA
-				DDRSS1_PHY_1121_DATA
-				DDRSS1_PHY_1122_DATA
-				DDRSS1_PHY_1123_DATA
-				DDRSS1_PHY_1124_DATA
-				DDRSS1_PHY_1125_DATA
-				DDRSS1_PHY_1126_DATA
-				DDRSS1_PHY_1127_DATA
-				DDRSS1_PHY_1128_DATA
-				DDRSS1_PHY_1129_DATA
-				DDRSS1_PHY_1130_DATA
-				DDRSS1_PHY_1131_DATA
-				DDRSS1_PHY_1132_DATA
-				DDRSS1_PHY_1133_DATA
-				DDRSS1_PHY_1134_DATA
-				DDRSS1_PHY_1135_DATA
-				DDRSS1_PHY_1136_DATA
-				DDRSS1_PHY_1137_DATA
-				DDRSS1_PHY_1138_DATA
-				DDRSS1_PHY_1139_DATA
-				DDRSS1_PHY_1140_DATA
-				DDRSS1_PHY_1141_DATA
-				DDRSS1_PHY_1142_DATA
-				DDRSS1_PHY_1143_DATA
-				DDRSS1_PHY_1144_DATA
-				DDRSS1_PHY_1145_DATA
-				DDRSS1_PHY_1146_DATA
-				DDRSS1_PHY_1147_DATA
-				DDRSS1_PHY_1148_DATA
-				DDRSS1_PHY_1149_DATA
-				DDRSS1_PHY_1150_DATA
-				DDRSS1_PHY_1151_DATA
-				DDRSS1_PHY_1152_DATA
-				DDRSS1_PHY_1153_DATA
-				DDRSS1_PHY_1154_DATA
-				DDRSS1_PHY_1155_DATA
-				DDRSS1_PHY_1156_DATA
-				DDRSS1_PHY_1157_DATA
-				DDRSS1_PHY_1158_DATA
-				DDRSS1_PHY_1159_DATA
-				DDRSS1_PHY_1160_DATA
-				DDRSS1_PHY_1161_DATA
-				DDRSS1_PHY_1162_DATA
-				DDRSS1_PHY_1163_DATA
-				DDRSS1_PHY_1164_DATA
-				DDRSS1_PHY_1165_DATA
-				DDRSS1_PHY_1166_DATA
-				DDRSS1_PHY_1167_DATA
-				DDRSS1_PHY_1168_DATA
-				DDRSS1_PHY_1169_DATA
-				DDRSS1_PHY_1170_DATA
-				DDRSS1_PHY_1171_DATA
-				DDRSS1_PHY_1172_DATA
-				DDRSS1_PHY_1173_DATA
-				DDRSS1_PHY_1174_DATA
-				DDRSS1_PHY_1175_DATA
-				DDRSS1_PHY_1176_DATA
-				DDRSS1_PHY_1177_DATA
-				DDRSS1_PHY_1178_DATA
-				DDRSS1_PHY_1179_DATA
-				DDRSS1_PHY_1180_DATA
-				DDRSS1_PHY_1181_DATA
-				DDRSS1_PHY_1182_DATA
-				DDRSS1_PHY_1183_DATA
-				DDRSS1_PHY_1184_DATA
-				DDRSS1_PHY_1185_DATA
-				DDRSS1_PHY_1186_DATA
-				DDRSS1_PHY_1187_DATA
-				DDRSS1_PHY_1188_DATA
-				DDRSS1_PHY_1189_DATA
-				DDRSS1_PHY_1190_DATA
-				DDRSS1_PHY_1191_DATA
-				DDRSS1_PHY_1192_DATA
-				DDRSS1_PHY_1193_DATA
-				DDRSS1_PHY_1194_DATA
-				DDRSS1_PHY_1195_DATA
-				DDRSS1_PHY_1196_DATA
-				DDRSS1_PHY_1197_DATA
-				DDRSS1_PHY_1198_DATA
-				DDRSS1_PHY_1199_DATA
-				DDRSS1_PHY_1200_DATA
-				DDRSS1_PHY_1201_DATA
-				DDRSS1_PHY_1202_DATA
-				DDRSS1_PHY_1203_DATA
-				DDRSS1_PHY_1204_DATA
-				DDRSS1_PHY_1205_DATA
-				DDRSS1_PHY_1206_DATA
-				DDRSS1_PHY_1207_DATA
-				DDRSS1_PHY_1208_DATA
-				DDRSS1_PHY_1209_DATA
-				DDRSS1_PHY_1210_DATA
-				DDRSS1_PHY_1211_DATA
-				DDRSS1_PHY_1212_DATA
-				DDRSS1_PHY_1213_DATA
-				DDRSS1_PHY_1214_DATA
-				DDRSS1_PHY_1215_DATA
-				DDRSS1_PHY_1216_DATA
-				DDRSS1_PHY_1217_DATA
-				DDRSS1_PHY_1218_DATA
-				DDRSS1_PHY_1219_DATA
-				DDRSS1_PHY_1220_DATA
-				DDRSS1_PHY_1221_DATA
-				DDRSS1_PHY_1222_DATA
-				DDRSS1_PHY_1223_DATA
-				DDRSS1_PHY_1224_DATA
-				DDRSS1_PHY_1225_DATA
-				DDRSS1_PHY_1226_DATA
-				DDRSS1_PHY_1227_DATA
-				DDRSS1_PHY_1228_DATA
-				DDRSS1_PHY_1229_DATA
-				DDRSS1_PHY_1230_DATA
-				DDRSS1_PHY_1231_DATA
-				DDRSS1_PHY_1232_DATA
-				DDRSS1_PHY_1233_DATA
-				DDRSS1_PHY_1234_DATA
-				DDRSS1_PHY_1235_DATA
-				DDRSS1_PHY_1236_DATA
-				DDRSS1_PHY_1237_DATA
-				DDRSS1_PHY_1238_DATA
-				DDRSS1_PHY_1239_DATA
-				DDRSS1_PHY_1240_DATA
-				DDRSS1_PHY_1241_DATA
-				DDRSS1_PHY_1242_DATA
-				DDRSS1_PHY_1243_DATA
-				DDRSS1_PHY_1244_DATA
-				DDRSS1_PHY_1245_DATA
-				DDRSS1_PHY_1246_DATA
-				DDRSS1_PHY_1247_DATA
-				DDRSS1_PHY_1248_DATA
-				DDRSS1_PHY_1249_DATA
-				DDRSS1_PHY_1250_DATA
-				DDRSS1_PHY_1251_DATA
-				DDRSS1_PHY_1252_DATA
-				DDRSS1_PHY_1253_DATA
-				DDRSS1_PHY_1254_DATA
-				DDRSS1_PHY_1255_DATA
-				DDRSS1_PHY_1256_DATA
-				DDRSS1_PHY_1257_DATA
-				DDRSS1_PHY_1258_DATA
-				DDRSS1_PHY_1259_DATA
-				DDRSS1_PHY_1260_DATA
-				DDRSS1_PHY_1261_DATA
-				DDRSS1_PHY_1262_DATA
-				DDRSS1_PHY_1263_DATA
-				DDRSS1_PHY_1264_DATA
-				DDRSS1_PHY_1265_DATA
-				DDRSS1_PHY_1266_DATA
-				DDRSS1_PHY_1267_DATA
-				DDRSS1_PHY_1268_DATA
-				DDRSS1_PHY_1269_DATA
-				DDRSS1_PHY_1270_DATA
-				DDRSS1_PHY_1271_DATA
-				DDRSS1_PHY_1272_DATA
-				DDRSS1_PHY_1273_DATA
-				DDRSS1_PHY_1274_DATA
-				DDRSS1_PHY_1275_DATA
-				DDRSS1_PHY_1276_DATA
-				DDRSS1_PHY_1277_DATA
-				DDRSS1_PHY_1278_DATA
-				DDRSS1_PHY_1279_DATA
-				DDRSS1_PHY_1280_DATA
-				DDRSS1_PHY_1281_DATA
-				DDRSS1_PHY_1282_DATA
-				DDRSS1_PHY_1283_DATA
-				DDRSS1_PHY_1284_DATA
-				DDRSS1_PHY_1285_DATA
-				DDRSS1_PHY_1286_DATA
-				DDRSS1_PHY_1287_DATA
-				DDRSS1_PHY_1288_DATA
-				DDRSS1_PHY_1289_DATA
-				DDRSS1_PHY_1290_DATA
-				DDRSS1_PHY_1291_DATA
-				DDRSS1_PHY_1292_DATA
-				DDRSS1_PHY_1293_DATA
-				DDRSS1_PHY_1294_DATA
-				DDRSS1_PHY_1295_DATA
-				DDRSS1_PHY_1296_DATA
-				DDRSS1_PHY_1297_DATA
-				DDRSS1_PHY_1298_DATA
-				DDRSS1_PHY_1299_DATA
-				DDRSS1_PHY_1300_DATA
-				DDRSS1_PHY_1301_DATA
-				DDRSS1_PHY_1302_DATA
-				DDRSS1_PHY_1303_DATA
-				DDRSS1_PHY_1304_DATA
-				DDRSS1_PHY_1305_DATA
-				DDRSS1_PHY_1306_DATA
-				DDRSS1_PHY_1307_DATA
-				DDRSS1_PHY_1308_DATA
-				DDRSS1_PHY_1309_DATA
-				DDRSS1_PHY_1310_DATA
-				DDRSS1_PHY_1311_DATA
-				DDRSS1_PHY_1312_DATA
-				DDRSS1_PHY_1313_DATA
-				DDRSS1_PHY_1314_DATA
-				DDRSS1_PHY_1315_DATA
-				DDRSS1_PHY_1316_DATA
-				DDRSS1_PHY_1317_DATA
-				DDRSS1_PHY_1318_DATA
-				DDRSS1_PHY_1319_DATA
-				DDRSS1_PHY_1320_DATA
-				DDRSS1_PHY_1321_DATA
-				DDRSS1_PHY_1322_DATA
-				DDRSS1_PHY_1323_DATA
-				DDRSS1_PHY_1324_DATA
-				DDRSS1_PHY_1325_DATA
-				DDRSS1_PHY_1326_DATA
-				DDRSS1_PHY_1327_DATA
-				DDRSS1_PHY_1328_DATA
-				DDRSS1_PHY_1329_DATA
-				DDRSS1_PHY_1330_DATA
-				DDRSS1_PHY_1331_DATA
-				DDRSS1_PHY_1332_DATA
-				DDRSS1_PHY_1333_DATA
-				DDRSS1_PHY_1334_DATA
-				DDRSS1_PHY_1335_DATA
-				DDRSS1_PHY_1336_DATA
-				DDRSS1_PHY_1337_DATA
-				DDRSS1_PHY_1338_DATA
-				DDRSS1_PHY_1339_DATA
-				DDRSS1_PHY_1340_DATA
-				DDRSS1_PHY_1341_DATA
-				DDRSS1_PHY_1342_DATA
-				DDRSS1_PHY_1343_DATA
-				DDRSS1_PHY_1344_DATA
-				DDRSS1_PHY_1345_DATA
-				DDRSS1_PHY_1346_DATA
-				DDRSS1_PHY_1347_DATA
-				DDRSS1_PHY_1348_DATA
-				DDRSS1_PHY_1349_DATA
-				DDRSS1_PHY_1350_DATA
-				DDRSS1_PHY_1351_DATA
-				DDRSS1_PHY_1352_DATA
-				DDRSS1_PHY_1353_DATA
-				DDRSS1_PHY_1354_DATA
-				DDRSS1_PHY_1355_DATA
-				DDRSS1_PHY_1356_DATA
-				DDRSS1_PHY_1357_DATA
-				DDRSS1_PHY_1358_DATA
-				DDRSS1_PHY_1359_DATA
-				DDRSS1_PHY_1360_DATA
-				DDRSS1_PHY_1361_DATA
-				DDRSS1_PHY_1362_DATA
-				DDRSS1_PHY_1363_DATA
-				DDRSS1_PHY_1364_DATA
-				DDRSS1_PHY_1365_DATA
-				DDRSS1_PHY_1366_DATA
-				DDRSS1_PHY_1367_DATA
-				DDRSS1_PHY_1368_DATA
-				DDRSS1_PHY_1369_DATA
-				DDRSS1_PHY_1370_DATA
-				DDRSS1_PHY_1371_DATA
-				DDRSS1_PHY_1372_DATA
-				DDRSS1_PHY_1373_DATA
-				DDRSS1_PHY_1374_DATA
-				DDRSS1_PHY_1375_DATA
-				DDRSS1_PHY_1376_DATA
-				DDRSS1_PHY_1377_DATA
-				DDRSS1_PHY_1378_DATA
-				DDRSS1_PHY_1379_DATA
-				DDRSS1_PHY_1380_DATA
-				DDRSS1_PHY_1381_DATA
-				DDRSS1_PHY_1382_DATA
-				DDRSS1_PHY_1383_DATA
-				DDRSS1_PHY_1384_DATA
-				DDRSS1_PHY_1385_DATA
-				DDRSS1_PHY_1386_DATA
-				DDRSS1_PHY_1387_DATA
-				DDRSS1_PHY_1388_DATA
-				DDRSS1_PHY_1389_DATA
-				DDRSS1_PHY_1390_DATA
-				DDRSS1_PHY_1391_DATA
-				DDRSS1_PHY_1392_DATA
-				DDRSS1_PHY_1393_DATA
-				DDRSS1_PHY_1394_DATA
-				DDRSS1_PHY_1395_DATA
-				DDRSS1_PHY_1396_DATA
-				DDRSS1_PHY_1397_DATA
-				DDRSS1_PHY_1398_DATA
-				DDRSS1_PHY_1399_DATA
-				DDRSS1_PHY_1400_DATA
-				DDRSS1_PHY_1401_DATA
-				DDRSS1_PHY_1402_DATA
-				DDRSS1_PHY_1403_DATA
-				DDRSS1_PHY_1404_DATA
-				DDRSS1_PHY_1405_DATA
-				DDRSS1_PHY_1406_DATA
-				DDRSS1_PHY_1407_DATA
-				DDRSS1_PHY_1408_DATA
-				DDRSS1_PHY_1409_DATA
-				DDRSS1_PHY_1410_DATA
-				DDRSS1_PHY_1411_DATA
-				DDRSS1_PHY_1412_DATA
-				DDRSS1_PHY_1413_DATA
-				DDRSS1_PHY_1414_DATA
-				DDRSS1_PHY_1415_DATA
-				DDRSS1_PHY_1416_DATA
-				DDRSS1_PHY_1417_DATA
-				DDRSS1_PHY_1418_DATA
-				DDRSS1_PHY_1419_DATA
-				DDRSS1_PHY_1420_DATA
-				DDRSS1_PHY_1421_DATA
-				DDRSS1_PHY_1422_DATA
-			>;
-		};
-
-		memorycontroller2: memorycontroller@29d0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029d0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x029c0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
-				<&k3_pds 133 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <2>;
-
-			bootph-pre-ram;
-
-			ti,ctl-data = <
-				DDRSS2_CTL_00_DATA
-				DDRSS2_CTL_01_DATA
-				DDRSS2_CTL_02_DATA
-				DDRSS2_CTL_03_DATA
-				DDRSS2_CTL_04_DATA
-				DDRSS2_CTL_05_DATA
-				DDRSS2_CTL_06_DATA
-				DDRSS2_CTL_07_DATA
-				DDRSS2_CTL_08_DATA
-				DDRSS2_CTL_09_DATA
-				DDRSS2_CTL_10_DATA
-				DDRSS2_CTL_11_DATA
-				DDRSS2_CTL_12_DATA
-				DDRSS2_CTL_13_DATA
-				DDRSS2_CTL_14_DATA
-				DDRSS2_CTL_15_DATA
-				DDRSS2_CTL_16_DATA
-				DDRSS2_CTL_17_DATA
-				DDRSS2_CTL_18_DATA
-				DDRSS2_CTL_19_DATA
-				DDRSS2_CTL_20_DATA
-				DDRSS2_CTL_21_DATA
-				DDRSS2_CTL_22_DATA
-				DDRSS2_CTL_23_DATA
-				DDRSS2_CTL_24_DATA
-				DDRSS2_CTL_25_DATA
-				DDRSS2_CTL_26_DATA
-				DDRSS2_CTL_27_DATA
-				DDRSS2_CTL_28_DATA
-				DDRSS2_CTL_29_DATA
-				DDRSS2_CTL_30_DATA
-				DDRSS2_CTL_31_DATA
-				DDRSS2_CTL_32_DATA
-				DDRSS2_CTL_33_DATA
-				DDRSS2_CTL_34_DATA
-				DDRSS2_CTL_35_DATA
-				DDRSS2_CTL_36_DATA
-				DDRSS2_CTL_37_DATA
-				DDRSS2_CTL_38_DATA
-				DDRSS2_CTL_39_DATA
-				DDRSS2_CTL_40_DATA
-				DDRSS2_CTL_41_DATA
-				DDRSS2_CTL_42_DATA
-				DDRSS2_CTL_43_DATA
-				DDRSS2_CTL_44_DATA
-				DDRSS2_CTL_45_DATA
-				DDRSS2_CTL_46_DATA
-				DDRSS2_CTL_47_DATA
-				DDRSS2_CTL_48_DATA
-				DDRSS2_CTL_49_DATA
-				DDRSS2_CTL_50_DATA
-				DDRSS2_CTL_51_DATA
-				DDRSS2_CTL_52_DATA
-				DDRSS2_CTL_53_DATA
-				DDRSS2_CTL_54_DATA
-				DDRSS2_CTL_55_DATA
-				DDRSS2_CTL_56_DATA
-				DDRSS2_CTL_57_DATA
-				DDRSS2_CTL_58_DATA
-				DDRSS2_CTL_59_DATA
-				DDRSS2_CTL_60_DATA
-				DDRSS2_CTL_61_DATA
-				DDRSS2_CTL_62_DATA
-				DDRSS2_CTL_63_DATA
-				DDRSS2_CTL_64_DATA
-				DDRSS2_CTL_65_DATA
-				DDRSS2_CTL_66_DATA
-				DDRSS2_CTL_67_DATA
-				DDRSS2_CTL_68_DATA
-				DDRSS2_CTL_69_DATA
-				DDRSS2_CTL_70_DATA
-				DDRSS2_CTL_71_DATA
-				DDRSS2_CTL_72_DATA
-				DDRSS2_CTL_73_DATA
-				DDRSS2_CTL_74_DATA
-				DDRSS2_CTL_75_DATA
-				DDRSS2_CTL_76_DATA
-				DDRSS2_CTL_77_DATA
-				DDRSS2_CTL_78_DATA
-				DDRSS2_CTL_79_DATA
-				DDRSS2_CTL_80_DATA
-				DDRSS2_CTL_81_DATA
-				DDRSS2_CTL_82_DATA
-				DDRSS2_CTL_83_DATA
-				DDRSS2_CTL_84_DATA
-				DDRSS2_CTL_85_DATA
-				DDRSS2_CTL_86_DATA
-				DDRSS2_CTL_87_DATA
-				DDRSS2_CTL_88_DATA
-				DDRSS2_CTL_89_DATA
-				DDRSS2_CTL_90_DATA
-				DDRSS2_CTL_91_DATA
-				DDRSS2_CTL_92_DATA
-				DDRSS2_CTL_93_DATA
-				DDRSS2_CTL_94_DATA
-				DDRSS2_CTL_95_DATA
-				DDRSS2_CTL_96_DATA
-				DDRSS2_CTL_97_DATA
-				DDRSS2_CTL_98_DATA
-				DDRSS2_CTL_99_DATA
-				DDRSS2_CTL_100_DATA
-				DDRSS2_CTL_101_DATA
-				DDRSS2_CTL_102_DATA
-				DDRSS2_CTL_103_DATA
-				DDRSS2_CTL_104_DATA
-				DDRSS2_CTL_105_DATA
-				DDRSS2_CTL_106_DATA
-				DDRSS2_CTL_107_DATA
-				DDRSS2_CTL_108_DATA
-				DDRSS2_CTL_109_DATA
-				DDRSS2_CTL_110_DATA
-				DDRSS2_CTL_111_DATA
-				DDRSS2_CTL_112_DATA
-				DDRSS2_CTL_113_DATA
-				DDRSS2_CTL_114_DATA
-				DDRSS2_CTL_115_DATA
-				DDRSS2_CTL_116_DATA
-				DDRSS2_CTL_117_DATA
-				DDRSS2_CTL_118_DATA
-				DDRSS2_CTL_119_DATA
-				DDRSS2_CTL_120_DATA
-				DDRSS2_CTL_121_DATA
-				DDRSS2_CTL_122_DATA
-				DDRSS2_CTL_123_DATA
-				DDRSS2_CTL_124_DATA
-				DDRSS2_CTL_125_DATA
-				DDRSS2_CTL_126_DATA
-				DDRSS2_CTL_127_DATA
-				DDRSS2_CTL_128_DATA
-				DDRSS2_CTL_129_DATA
-				DDRSS2_CTL_130_DATA
-				DDRSS2_CTL_131_DATA
-				DDRSS2_CTL_132_DATA
-				DDRSS2_CTL_133_DATA
-				DDRSS2_CTL_134_DATA
-				DDRSS2_CTL_135_DATA
-				DDRSS2_CTL_136_DATA
-				DDRSS2_CTL_137_DATA
-				DDRSS2_CTL_138_DATA
-				DDRSS2_CTL_139_DATA
-				DDRSS2_CTL_140_DATA
-				DDRSS2_CTL_141_DATA
-				DDRSS2_CTL_142_DATA
-				DDRSS2_CTL_143_DATA
-				DDRSS2_CTL_144_DATA
-				DDRSS2_CTL_145_DATA
-				DDRSS2_CTL_146_DATA
-				DDRSS2_CTL_147_DATA
-				DDRSS2_CTL_148_DATA
-				DDRSS2_CTL_149_DATA
-				DDRSS2_CTL_150_DATA
-				DDRSS2_CTL_151_DATA
-				DDRSS2_CTL_152_DATA
-				DDRSS2_CTL_153_DATA
-				DDRSS2_CTL_154_DATA
-				DDRSS2_CTL_155_DATA
-				DDRSS2_CTL_156_DATA
-				DDRSS2_CTL_157_DATA
-				DDRSS2_CTL_158_DATA
-				DDRSS2_CTL_159_DATA
-				DDRSS2_CTL_160_DATA
-				DDRSS2_CTL_161_DATA
-				DDRSS2_CTL_162_DATA
-				DDRSS2_CTL_163_DATA
-				DDRSS2_CTL_164_DATA
-				DDRSS2_CTL_165_DATA
-				DDRSS2_CTL_166_DATA
-				DDRSS2_CTL_167_DATA
-				DDRSS2_CTL_168_DATA
-				DDRSS2_CTL_169_DATA
-				DDRSS2_CTL_170_DATA
-				DDRSS2_CTL_171_DATA
-				DDRSS2_CTL_172_DATA
-				DDRSS2_CTL_173_DATA
-				DDRSS2_CTL_174_DATA
-				DDRSS2_CTL_175_DATA
-				DDRSS2_CTL_176_DATA
-				DDRSS2_CTL_177_DATA
-				DDRSS2_CTL_178_DATA
-				DDRSS2_CTL_179_DATA
-				DDRSS2_CTL_180_DATA
-				DDRSS2_CTL_181_DATA
-				DDRSS2_CTL_182_DATA
-				DDRSS2_CTL_183_DATA
-				DDRSS2_CTL_184_DATA
-				DDRSS2_CTL_185_DATA
-				DDRSS2_CTL_186_DATA
-				DDRSS2_CTL_187_DATA
-				DDRSS2_CTL_188_DATA
-				DDRSS2_CTL_189_DATA
-				DDRSS2_CTL_190_DATA
-				DDRSS2_CTL_191_DATA
-				DDRSS2_CTL_192_DATA
-				DDRSS2_CTL_193_DATA
-				DDRSS2_CTL_194_DATA
-				DDRSS2_CTL_195_DATA
-				DDRSS2_CTL_196_DATA
-				DDRSS2_CTL_197_DATA
-				DDRSS2_CTL_198_DATA
-				DDRSS2_CTL_199_DATA
-				DDRSS2_CTL_200_DATA
-				DDRSS2_CTL_201_DATA
-				DDRSS2_CTL_202_DATA
-				DDRSS2_CTL_203_DATA
-				DDRSS2_CTL_204_DATA
-				DDRSS2_CTL_205_DATA
-				DDRSS2_CTL_206_DATA
-				DDRSS2_CTL_207_DATA
-				DDRSS2_CTL_208_DATA
-				DDRSS2_CTL_209_DATA
-				DDRSS2_CTL_210_DATA
-				DDRSS2_CTL_211_DATA
-				DDRSS2_CTL_212_DATA
-				DDRSS2_CTL_213_DATA
-				DDRSS2_CTL_214_DATA
-				DDRSS2_CTL_215_DATA
-				DDRSS2_CTL_216_DATA
-				DDRSS2_CTL_217_DATA
-				DDRSS2_CTL_218_DATA
-				DDRSS2_CTL_219_DATA
-				DDRSS2_CTL_220_DATA
-				DDRSS2_CTL_221_DATA
-				DDRSS2_CTL_222_DATA
-				DDRSS2_CTL_223_DATA
-				DDRSS2_CTL_224_DATA
-				DDRSS2_CTL_225_DATA
-				DDRSS2_CTL_226_DATA
-				DDRSS2_CTL_227_DATA
-				DDRSS2_CTL_228_DATA
-				DDRSS2_CTL_229_DATA
-				DDRSS2_CTL_230_DATA
-				DDRSS2_CTL_231_DATA
-				DDRSS2_CTL_232_DATA
-				DDRSS2_CTL_233_DATA
-				DDRSS2_CTL_234_DATA
-				DDRSS2_CTL_235_DATA
-				DDRSS2_CTL_236_DATA
-				DDRSS2_CTL_237_DATA
-				DDRSS2_CTL_238_DATA
-				DDRSS2_CTL_239_DATA
-				DDRSS2_CTL_240_DATA
-				DDRSS2_CTL_241_DATA
-				DDRSS2_CTL_242_DATA
-				DDRSS2_CTL_243_DATA
-				DDRSS2_CTL_244_DATA
-				DDRSS2_CTL_245_DATA
-				DDRSS2_CTL_246_DATA
-				DDRSS2_CTL_247_DATA
-				DDRSS2_CTL_248_DATA
-				DDRSS2_CTL_249_DATA
-				DDRSS2_CTL_250_DATA
-				DDRSS2_CTL_251_DATA
-				DDRSS2_CTL_252_DATA
-				DDRSS2_CTL_253_DATA
-				DDRSS2_CTL_254_DATA
-				DDRSS2_CTL_255_DATA
-				DDRSS2_CTL_256_DATA
-				DDRSS2_CTL_257_DATA
-				DDRSS2_CTL_258_DATA
-				DDRSS2_CTL_259_DATA
-				DDRSS2_CTL_260_DATA
-				DDRSS2_CTL_261_DATA
-				DDRSS2_CTL_262_DATA
-				DDRSS2_CTL_263_DATA
-				DDRSS2_CTL_264_DATA
-				DDRSS2_CTL_265_DATA
-				DDRSS2_CTL_266_DATA
-				DDRSS2_CTL_267_DATA
-				DDRSS2_CTL_268_DATA
-				DDRSS2_CTL_269_DATA
-				DDRSS2_CTL_270_DATA
-				DDRSS2_CTL_271_DATA
-				DDRSS2_CTL_272_DATA
-				DDRSS2_CTL_273_DATA
-				DDRSS2_CTL_274_DATA
-				DDRSS2_CTL_275_DATA
-				DDRSS2_CTL_276_DATA
-				DDRSS2_CTL_277_DATA
-				DDRSS2_CTL_278_DATA
-				DDRSS2_CTL_279_DATA
-				DDRSS2_CTL_280_DATA
-				DDRSS2_CTL_281_DATA
-				DDRSS2_CTL_282_DATA
-				DDRSS2_CTL_283_DATA
-				DDRSS2_CTL_284_DATA
-				DDRSS2_CTL_285_DATA
-				DDRSS2_CTL_286_DATA
-				DDRSS2_CTL_287_DATA
-				DDRSS2_CTL_288_DATA
-				DDRSS2_CTL_289_DATA
-				DDRSS2_CTL_290_DATA
-				DDRSS2_CTL_291_DATA
-				DDRSS2_CTL_292_DATA
-				DDRSS2_CTL_293_DATA
-				DDRSS2_CTL_294_DATA
-				DDRSS2_CTL_295_DATA
-				DDRSS2_CTL_296_DATA
-				DDRSS2_CTL_297_DATA
-				DDRSS2_CTL_298_DATA
-				DDRSS2_CTL_299_DATA
-				DDRSS2_CTL_300_DATA
-				DDRSS2_CTL_301_DATA
-				DDRSS2_CTL_302_DATA
-				DDRSS2_CTL_303_DATA
-				DDRSS2_CTL_304_DATA
-				DDRSS2_CTL_305_DATA
-				DDRSS2_CTL_306_DATA
-				DDRSS2_CTL_307_DATA
-				DDRSS2_CTL_308_DATA
-				DDRSS2_CTL_309_DATA
-				DDRSS2_CTL_310_DATA
-				DDRSS2_CTL_311_DATA
-				DDRSS2_CTL_312_DATA
-				DDRSS2_CTL_313_DATA
-				DDRSS2_CTL_314_DATA
-				DDRSS2_CTL_315_DATA
-				DDRSS2_CTL_316_DATA
-				DDRSS2_CTL_317_DATA
-				DDRSS2_CTL_318_DATA
-				DDRSS2_CTL_319_DATA
-				DDRSS2_CTL_320_DATA
-				DDRSS2_CTL_321_DATA
-				DDRSS2_CTL_322_DATA
-				DDRSS2_CTL_323_DATA
-				DDRSS2_CTL_324_DATA
-				DDRSS2_CTL_325_DATA
-				DDRSS2_CTL_326_DATA
-				DDRSS2_CTL_327_DATA
-				DDRSS2_CTL_328_DATA
-				DDRSS2_CTL_329_DATA
-				DDRSS2_CTL_330_DATA
-				DDRSS2_CTL_331_DATA
-				DDRSS2_CTL_332_DATA
-				DDRSS2_CTL_333_DATA
-				DDRSS2_CTL_334_DATA
-				DDRSS2_CTL_335_DATA
-				DDRSS2_CTL_336_DATA
-				DDRSS2_CTL_337_DATA
-				DDRSS2_CTL_338_DATA
-				DDRSS2_CTL_339_DATA
-				DDRSS2_CTL_340_DATA
-				DDRSS2_CTL_341_DATA
-				DDRSS2_CTL_342_DATA
-				DDRSS2_CTL_343_DATA
-				DDRSS2_CTL_344_DATA
-				DDRSS2_CTL_345_DATA
-				DDRSS2_CTL_346_DATA
-				DDRSS2_CTL_347_DATA
-				DDRSS2_CTL_348_DATA
-				DDRSS2_CTL_349_DATA
-				DDRSS2_CTL_350_DATA
-				DDRSS2_CTL_351_DATA
-				DDRSS2_CTL_352_DATA
-				DDRSS2_CTL_353_DATA
-				DDRSS2_CTL_354_DATA
-				DDRSS2_CTL_355_DATA
-				DDRSS2_CTL_356_DATA
-				DDRSS2_CTL_357_DATA
-				DDRSS2_CTL_358_DATA
-				DDRSS2_CTL_359_DATA
-				DDRSS2_CTL_360_DATA
-				DDRSS2_CTL_361_DATA
-				DDRSS2_CTL_362_DATA
-				DDRSS2_CTL_363_DATA
-				DDRSS2_CTL_364_DATA
-				DDRSS2_CTL_365_DATA
-				DDRSS2_CTL_366_DATA
-				DDRSS2_CTL_367_DATA
-				DDRSS2_CTL_368_DATA
-				DDRSS2_CTL_369_DATA
-				DDRSS2_CTL_370_DATA
-				DDRSS2_CTL_371_DATA
-				DDRSS2_CTL_372_DATA
-				DDRSS2_CTL_373_DATA
-				DDRSS2_CTL_374_DATA
-				DDRSS2_CTL_375_DATA
-				DDRSS2_CTL_376_DATA
-				DDRSS2_CTL_377_DATA
-				DDRSS2_CTL_378_DATA
-				DDRSS2_CTL_379_DATA
-				DDRSS2_CTL_380_DATA
-				DDRSS2_CTL_381_DATA
-				DDRSS2_CTL_382_DATA
-				DDRSS2_CTL_383_DATA
-				DDRSS2_CTL_384_DATA
-				DDRSS2_CTL_385_DATA
-				DDRSS2_CTL_386_DATA
-				DDRSS2_CTL_387_DATA
-				DDRSS2_CTL_388_DATA
-				DDRSS2_CTL_389_DATA
-				DDRSS2_CTL_390_DATA
-				DDRSS2_CTL_391_DATA
-				DDRSS2_CTL_392_DATA
-				DDRSS2_CTL_393_DATA
-				DDRSS2_CTL_394_DATA
-				DDRSS2_CTL_395_DATA
-				DDRSS2_CTL_396_DATA
-				DDRSS2_CTL_397_DATA
-				DDRSS2_CTL_398_DATA
-				DDRSS2_CTL_399_DATA
-				DDRSS2_CTL_400_DATA
-				DDRSS2_CTL_401_DATA
-				DDRSS2_CTL_402_DATA
-				DDRSS2_CTL_403_DATA
-				DDRSS2_CTL_404_DATA
-				DDRSS2_CTL_405_DATA
-				DDRSS2_CTL_406_DATA
-				DDRSS2_CTL_407_DATA
-				DDRSS2_CTL_408_DATA
-				DDRSS2_CTL_409_DATA
-				DDRSS2_CTL_410_DATA
-				DDRSS2_CTL_411_DATA
-				DDRSS2_CTL_412_DATA
-				DDRSS2_CTL_413_DATA
-				DDRSS2_CTL_414_DATA
-				DDRSS2_CTL_415_DATA
-				DDRSS2_CTL_416_DATA
-				DDRSS2_CTL_417_DATA
-				DDRSS2_CTL_418_DATA
-				DDRSS2_CTL_419_DATA
-				DDRSS2_CTL_420_DATA
-				DDRSS2_CTL_421_DATA
-				DDRSS2_CTL_422_DATA
-				DDRSS2_CTL_423_DATA
-				DDRSS2_CTL_424_DATA
-				DDRSS2_CTL_425_DATA
-				DDRSS2_CTL_426_DATA
-				DDRSS2_CTL_427_DATA
-				DDRSS2_CTL_428_DATA
-				DDRSS2_CTL_429_DATA
-				DDRSS2_CTL_430_DATA
-				DDRSS2_CTL_431_DATA
-				DDRSS2_CTL_432_DATA
-				DDRSS2_CTL_433_DATA
-				DDRSS2_CTL_434_DATA
-				DDRSS2_CTL_435_DATA
-				DDRSS2_CTL_436_DATA
-				DDRSS2_CTL_437_DATA
-				DDRSS2_CTL_438_DATA
-				DDRSS2_CTL_439_DATA
-				DDRSS2_CTL_440_DATA
-				DDRSS2_CTL_441_DATA
-				DDRSS2_CTL_442_DATA
-				DDRSS2_CTL_443_DATA
-				DDRSS2_CTL_444_DATA
-				DDRSS2_CTL_445_DATA
-				DDRSS2_CTL_446_DATA
-				DDRSS2_CTL_447_DATA
-				DDRSS2_CTL_448_DATA
-				DDRSS2_CTL_449_DATA
-				DDRSS2_CTL_450_DATA
-				DDRSS2_CTL_451_DATA
-				DDRSS2_CTL_452_DATA
-				DDRSS2_CTL_453_DATA
-				DDRSS2_CTL_454_DATA
-				DDRSS2_CTL_455_DATA
-				DDRSS2_CTL_456_DATA
-				DDRSS2_CTL_457_DATA
-				DDRSS2_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS2_PI_00_DATA
-				DDRSS2_PI_01_DATA
-				DDRSS2_PI_02_DATA
-				DDRSS2_PI_03_DATA
-				DDRSS2_PI_04_DATA
-				DDRSS2_PI_05_DATA
-				DDRSS2_PI_06_DATA
-				DDRSS2_PI_07_DATA
-				DDRSS2_PI_08_DATA
-				DDRSS2_PI_09_DATA
-				DDRSS2_PI_10_DATA
-				DDRSS2_PI_11_DATA
-				DDRSS2_PI_12_DATA
-				DDRSS2_PI_13_DATA
-				DDRSS2_PI_14_DATA
-				DDRSS2_PI_15_DATA
-				DDRSS2_PI_16_DATA
-				DDRSS2_PI_17_DATA
-				DDRSS2_PI_18_DATA
-				DDRSS2_PI_19_DATA
-				DDRSS2_PI_20_DATA
-				DDRSS2_PI_21_DATA
-				DDRSS2_PI_22_DATA
-				DDRSS2_PI_23_DATA
-				DDRSS2_PI_24_DATA
-				DDRSS2_PI_25_DATA
-				DDRSS2_PI_26_DATA
-				DDRSS2_PI_27_DATA
-				DDRSS2_PI_28_DATA
-				DDRSS2_PI_29_DATA
-				DDRSS2_PI_30_DATA
-				DDRSS2_PI_31_DATA
-				DDRSS2_PI_32_DATA
-				DDRSS2_PI_33_DATA
-				DDRSS2_PI_34_DATA
-				DDRSS2_PI_35_DATA
-				DDRSS2_PI_36_DATA
-				DDRSS2_PI_37_DATA
-				DDRSS2_PI_38_DATA
-				DDRSS2_PI_39_DATA
-				DDRSS2_PI_40_DATA
-				DDRSS2_PI_41_DATA
-				DDRSS2_PI_42_DATA
-				DDRSS2_PI_43_DATA
-				DDRSS2_PI_44_DATA
-				DDRSS2_PI_45_DATA
-				DDRSS2_PI_46_DATA
-				DDRSS2_PI_47_DATA
-				DDRSS2_PI_48_DATA
-				DDRSS2_PI_49_DATA
-				DDRSS2_PI_50_DATA
-				DDRSS2_PI_51_DATA
-				DDRSS2_PI_52_DATA
-				DDRSS2_PI_53_DATA
-				DDRSS2_PI_54_DATA
-				DDRSS2_PI_55_DATA
-				DDRSS2_PI_56_DATA
-				DDRSS2_PI_57_DATA
-				DDRSS2_PI_58_DATA
-				DDRSS2_PI_59_DATA
-				DDRSS2_PI_60_DATA
-				DDRSS2_PI_61_DATA
-				DDRSS2_PI_62_DATA
-				DDRSS2_PI_63_DATA
-				DDRSS2_PI_64_DATA
-				DDRSS2_PI_65_DATA
-				DDRSS2_PI_66_DATA
-				DDRSS2_PI_67_DATA
-				DDRSS2_PI_68_DATA
-				DDRSS2_PI_69_DATA
-				DDRSS2_PI_70_DATA
-				DDRSS2_PI_71_DATA
-				DDRSS2_PI_72_DATA
-				DDRSS2_PI_73_DATA
-				DDRSS2_PI_74_DATA
-				DDRSS2_PI_75_DATA
-				DDRSS2_PI_76_DATA
-				DDRSS2_PI_77_DATA
-				DDRSS2_PI_78_DATA
-				DDRSS2_PI_79_DATA
-				DDRSS2_PI_80_DATA
-				DDRSS2_PI_81_DATA
-				DDRSS2_PI_82_DATA
-				DDRSS2_PI_83_DATA
-				DDRSS2_PI_84_DATA
-				DDRSS2_PI_85_DATA
-				DDRSS2_PI_86_DATA
-				DDRSS2_PI_87_DATA
-				DDRSS2_PI_88_DATA
-				DDRSS2_PI_89_DATA
-				DDRSS2_PI_90_DATA
-				DDRSS2_PI_91_DATA
-				DDRSS2_PI_92_DATA
-				DDRSS2_PI_93_DATA
-				DDRSS2_PI_94_DATA
-				DDRSS2_PI_95_DATA
-				DDRSS2_PI_96_DATA
-				DDRSS2_PI_97_DATA
-				DDRSS2_PI_98_DATA
-				DDRSS2_PI_99_DATA
-				DDRSS2_PI_100_DATA
-				DDRSS2_PI_101_DATA
-				DDRSS2_PI_102_DATA
-				DDRSS2_PI_103_DATA
-				DDRSS2_PI_104_DATA
-				DDRSS2_PI_105_DATA
-				DDRSS2_PI_106_DATA
-				DDRSS2_PI_107_DATA
-				DDRSS2_PI_108_DATA
-				DDRSS2_PI_109_DATA
-				DDRSS2_PI_110_DATA
-				DDRSS2_PI_111_DATA
-				DDRSS2_PI_112_DATA
-				DDRSS2_PI_113_DATA
-				DDRSS2_PI_114_DATA
-				DDRSS2_PI_115_DATA
-				DDRSS2_PI_116_DATA
-				DDRSS2_PI_117_DATA
-				DDRSS2_PI_118_DATA
-				DDRSS2_PI_119_DATA
-				DDRSS2_PI_120_DATA
-				DDRSS2_PI_121_DATA
-				DDRSS2_PI_122_DATA
-				DDRSS2_PI_123_DATA
-				DDRSS2_PI_124_DATA
-				DDRSS2_PI_125_DATA
-				DDRSS2_PI_126_DATA
-				DDRSS2_PI_127_DATA
-				DDRSS2_PI_128_DATA
-				DDRSS2_PI_129_DATA
-				DDRSS2_PI_130_DATA
-				DDRSS2_PI_131_DATA
-				DDRSS2_PI_132_DATA
-				DDRSS2_PI_133_DATA
-				DDRSS2_PI_134_DATA
-				DDRSS2_PI_135_DATA
-				DDRSS2_PI_136_DATA
-				DDRSS2_PI_137_DATA
-				DDRSS2_PI_138_DATA
-				DDRSS2_PI_139_DATA
-				DDRSS2_PI_140_DATA
-				DDRSS2_PI_141_DATA
-				DDRSS2_PI_142_DATA
-				DDRSS2_PI_143_DATA
-				DDRSS2_PI_144_DATA
-				DDRSS2_PI_145_DATA
-				DDRSS2_PI_146_DATA
-				DDRSS2_PI_147_DATA
-				DDRSS2_PI_148_DATA
-				DDRSS2_PI_149_DATA
-				DDRSS2_PI_150_DATA
-				DDRSS2_PI_151_DATA
-				DDRSS2_PI_152_DATA
-				DDRSS2_PI_153_DATA
-				DDRSS2_PI_154_DATA
-				DDRSS2_PI_155_DATA
-				DDRSS2_PI_156_DATA
-				DDRSS2_PI_157_DATA
-				DDRSS2_PI_158_DATA
-				DDRSS2_PI_159_DATA
-				DDRSS2_PI_160_DATA
-				DDRSS2_PI_161_DATA
-				DDRSS2_PI_162_DATA
-				DDRSS2_PI_163_DATA
-				DDRSS2_PI_164_DATA
-				DDRSS2_PI_165_DATA
-				DDRSS2_PI_166_DATA
-				DDRSS2_PI_167_DATA
-				DDRSS2_PI_168_DATA
-				DDRSS2_PI_169_DATA
-				DDRSS2_PI_170_DATA
-				DDRSS2_PI_171_DATA
-				DDRSS2_PI_172_DATA
-				DDRSS2_PI_173_DATA
-				DDRSS2_PI_174_DATA
-				DDRSS2_PI_175_DATA
-				DDRSS2_PI_176_DATA
-				DDRSS2_PI_177_DATA
-				DDRSS2_PI_178_DATA
-				DDRSS2_PI_179_DATA
-				DDRSS2_PI_180_DATA
-				DDRSS2_PI_181_DATA
-				DDRSS2_PI_182_DATA
-				DDRSS2_PI_183_DATA
-				DDRSS2_PI_184_DATA
-				DDRSS2_PI_185_DATA
-				DDRSS2_PI_186_DATA
-				DDRSS2_PI_187_DATA
-				DDRSS2_PI_188_DATA
-				DDRSS2_PI_189_DATA
-				DDRSS2_PI_190_DATA
-				DDRSS2_PI_191_DATA
-				DDRSS2_PI_192_DATA
-				DDRSS2_PI_193_DATA
-				DDRSS2_PI_194_DATA
-				DDRSS2_PI_195_DATA
-				DDRSS2_PI_196_DATA
-				DDRSS2_PI_197_DATA
-				DDRSS2_PI_198_DATA
-				DDRSS2_PI_199_DATA
-				DDRSS2_PI_200_DATA
-				DDRSS2_PI_201_DATA
-				DDRSS2_PI_202_DATA
-				DDRSS2_PI_203_DATA
-				DDRSS2_PI_204_DATA
-				DDRSS2_PI_205_DATA
-				DDRSS2_PI_206_DATA
-				DDRSS2_PI_207_DATA
-				DDRSS2_PI_208_DATA
-				DDRSS2_PI_209_DATA
-				DDRSS2_PI_210_DATA
-				DDRSS2_PI_211_DATA
-				DDRSS2_PI_212_DATA
-				DDRSS2_PI_213_DATA
-				DDRSS2_PI_214_DATA
-				DDRSS2_PI_215_DATA
-				DDRSS2_PI_216_DATA
-				DDRSS2_PI_217_DATA
-				DDRSS2_PI_218_DATA
-				DDRSS2_PI_219_DATA
-				DDRSS2_PI_220_DATA
-				DDRSS2_PI_221_DATA
-				DDRSS2_PI_222_DATA
-				DDRSS2_PI_223_DATA
-				DDRSS2_PI_224_DATA
-				DDRSS2_PI_225_DATA
-				DDRSS2_PI_226_DATA
-				DDRSS2_PI_227_DATA
-				DDRSS2_PI_228_DATA
-				DDRSS2_PI_229_DATA
-				DDRSS2_PI_230_DATA
-				DDRSS2_PI_231_DATA
-				DDRSS2_PI_232_DATA
-				DDRSS2_PI_233_DATA
-				DDRSS2_PI_234_DATA
-				DDRSS2_PI_235_DATA
-				DDRSS2_PI_236_DATA
-				DDRSS2_PI_237_DATA
-				DDRSS2_PI_238_DATA
-				DDRSS2_PI_239_DATA
-				DDRSS2_PI_240_DATA
-				DDRSS2_PI_241_DATA
-				DDRSS2_PI_242_DATA
-				DDRSS2_PI_243_DATA
-				DDRSS2_PI_244_DATA
-				DDRSS2_PI_245_DATA
-				DDRSS2_PI_246_DATA
-				DDRSS2_PI_247_DATA
-				DDRSS2_PI_248_DATA
-				DDRSS2_PI_249_DATA
-				DDRSS2_PI_250_DATA
-				DDRSS2_PI_251_DATA
-				DDRSS2_PI_252_DATA
-				DDRSS2_PI_253_DATA
-				DDRSS2_PI_254_DATA
-				DDRSS2_PI_255_DATA
-				DDRSS2_PI_256_DATA
-				DDRSS2_PI_257_DATA
-				DDRSS2_PI_258_DATA
-				DDRSS2_PI_259_DATA
-				DDRSS2_PI_260_DATA
-				DDRSS2_PI_261_DATA
-				DDRSS2_PI_262_DATA
-				DDRSS2_PI_263_DATA
-				DDRSS2_PI_264_DATA
-				DDRSS2_PI_265_DATA
-				DDRSS2_PI_266_DATA
-				DDRSS2_PI_267_DATA
-				DDRSS2_PI_268_DATA
-				DDRSS2_PI_269_DATA
-				DDRSS2_PI_270_DATA
-				DDRSS2_PI_271_DATA
-				DDRSS2_PI_272_DATA
-				DDRSS2_PI_273_DATA
-				DDRSS2_PI_274_DATA
-				DDRSS2_PI_275_DATA
-				DDRSS2_PI_276_DATA
-				DDRSS2_PI_277_DATA
-				DDRSS2_PI_278_DATA
-				DDRSS2_PI_279_DATA
-				DDRSS2_PI_280_DATA
-				DDRSS2_PI_281_DATA
-				DDRSS2_PI_282_DATA
-				DDRSS2_PI_283_DATA
-				DDRSS2_PI_284_DATA
-				DDRSS2_PI_285_DATA
-				DDRSS2_PI_286_DATA
-				DDRSS2_PI_287_DATA
-				DDRSS2_PI_288_DATA
-				DDRSS2_PI_289_DATA
-				DDRSS2_PI_290_DATA
-				DDRSS2_PI_291_DATA
-				DDRSS2_PI_292_DATA
-				DDRSS2_PI_293_DATA
-				DDRSS2_PI_294_DATA
-				DDRSS2_PI_295_DATA
-				DDRSS2_PI_296_DATA
-				DDRSS2_PI_297_DATA
-				DDRSS2_PI_298_DATA
-				DDRSS2_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS2_PHY_00_DATA
-				DDRSS2_PHY_01_DATA
-				DDRSS2_PHY_02_DATA
-				DDRSS2_PHY_03_DATA
-				DDRSS2_PHY_04_DATA
-				DDRSS2_PHY_05_DATA
-				DDRSS2_PHY_06_DATA
-				DDRSS2_PHY_07_DATA
-				DDRSS2_PHY_08_DATA
-				DDRSS2_PHY_09_DATA
-				DDRSS2_PHY_10_DATA
-				DDRSS2_PHY_11_DATA
-				DDRSS2_PHY_12_DATA
-				DDRSS2_PHY_13_DATA
-				DDRSS2_PHY_14_DATA
-				DDRSS2_PHY_15_DATA
-				DDRSS2_PHY_16_DATA
-				DDRSS2_PHY_17_DATA
-				DDRSS2_PHY_18_DATA
-				DDRSS2_PHY_19_DATA
-				DDRSS2_PHY_20_DATA
-				DDRSS2_PHY_21_DATA
-				DDRSS2_PHY_22_DATA
-				DDRSS2_PHY_23_DATA
-				DDRSS2_PHY_24_DATA
-				DDRSS2_PHY_25_DATA
-				DDRSS2_PHY_26_DATA
-				DDRSS2_PHY_27_DATA
-				DDRSS2_PHY_28_DATA
-				DDRSS2_PHY_29_DATA
-				DDRSS2_PHY_30_DATA
-				DDRSS2_PHY_31_DATA
-				DDRSS2_PHY_32_DATA
-				DDRSS2_PHY_33_DATA
-				DDRSS2_PHY_34_DATA
-				DDRSS2_PHY_35_DATA
-				DDRSS2_PHY_36_DATA
-				DDRSS2_PHY_37_DATA
-				DDRSS2_PHY_38_DATA
-				DDRSS2_PHY_39_DATA
-				DDRSS2_PHY_40_DATA
-				DDRSS2_PHY_41_DATA
-				DDRSS2_PHY_42_DATA
-				DDRSS2_PHY_43_DATA
-				DDRSS2_PHY_44_DATA
-				DDRSS2_PHY_45_DATA
-				DDRSS2_PHY_46_DATA
-				DDRSS2_PHY_47_DATA
-				DDRSS2_PHY_48_DATA
-				DDRSS2_PHY_49_DATA
-				DDRSS2_PHY_50_DATA
-				DDRSS2_PHY_51_DATA
-				DDRSS2_PHY_52_DATA
-				DDRSS2_PHY_53_DATA
-				DDRSS2_PHY_54_DATA
-				DDRSS2_PHY_55_DATA
-				DDRSS2_PHY_56_DATA
-				DDRSS2_PHY_57_DATA
-				DDRSS2_PHY_58_DATA
-				DDRSS2_PHY_59_DATA
-				DDRSS2_PHY_60_DATA
-				DDRSS2_PHY_61_DATA
-				DDRSS2_PHY_62_DATA
-				DDRSS2_PHY_63_DATA
-				DDRSS2_PHY_64_DATA
-				DDRSS2_PHY_65_DATA
-				DDRSS2_PHY_66_DATA
-				DDRSS2_PHY_67_DATA
-				DDRSS2_PHY_68_DATA
-				DDRSS2_PHY_69_DATA
-				DDRSS2_PHY_70_DATA
-				DDRSS2_PHY_71_DATA
-				DDRSS2_PHY_72_DATA
-				DDRSS2_PHY_73_DATA
-				DDRSS2_PHY_74_DATA
-				DDRSS2_PHY_75_DATA
-				DDRSS2_PHY_76_DATA
-				DDRSS2_PHY_77_DATA
-				DDRSS2_PHY_78_DATA
-				DDRSS2_PHY_79_DATA
-				DDRSS2_PHY_80_DATA
-				DDRSS2_PHY_81_DATA
-				DDRSS2_PHY_82_DATA
-				DDRSS2_PHY_83_DATA
-				DDRSS2_PHY_84_DATA
-				DDRSS2_PHY_85_DATA
-				DDRSS2_PHY_86_DATA
-				DDRSS2_PHY_87_DATA
-				DDRSS2_PHY_88_DATA
-				DDRSS2_PHY_89_DATA
-				DDRSS2_PHY_90_DATA
-				DDRSS2_PHY_91_DATA
-				DDRSS2_PHY_92_DATA
-				DDRSS2_PHY_93_DATA
-				DDRSS2_PHY_94_DATA
-				DDRSS2_PHY_95_DATA
-				DDRSS2_PHY_96_DATA
-				DDRSS2_PHY_97_DATA
-				DDRSS2_PHY_98_DATA
-				DDRSS2_PHY_99_DATA
-				DDRSS2_PHY_100_DATA
-				DDRSS2_PHY_101_DATA
-				DDRSS2_PHY_102_DATA
-				DDRSS2_PHY_103_DATA
-				DDRSS2_PHY_104_DATA
-				DDRSS2_PHY_105_DATA
-				DDRSS2_PHY_106_DATA
-				DDRSS2_PHY_107_DATA
-				DDRSS2_PHY_108_DATA
-				DDRSS2_PHY_109_DATA
-				DDRSS2_PHY_110_DATA
-				DDRSS2_PHY_111_DATA
-				DDRSS2_PHY_112_DATA
-				DDRSS2_PHY_113_DATA
-				DDRSS2_PHY_114_DATA
-				DDRSS2_PHY_115_DATA
-				DDRSS2_PHY_116_DATA
-				DDRSS2_PHY_117_DATA
-				DDRSS2_PHY_118_DATA
-				DDRSS2_PHY_119_DATA
-				DDRSS2_PHY_120_DATA
-				DDRSS2_PHY_121_DATA
-				DDRSS2_PHY_122_DATA
-				DDRSS2_PHY_123_DATA
-				DDRSS2_PHY_124_DATA
-				DDRSS2_PHY_125_DATA
-				DDRSS2_PHY_126_DATA
-				DDRSS2_PHY_127_DATA
-				DDRSS2_PHY_128_DATA
-				DDRSS2_PHY_129_DATA
-				DDRSS2_PHY_130_DATA
-				DDRSS2_PHY_131_DATA
-				DDRSS2_PHY_132_DATA
-				DDRSS2_PHY_133_DATA
-				DDRSS2_PHY_134_DATA
-				DDRSS2_PHY_135_DATA
-				DDRSS2_PHY_136_DATA
-				DDRSS2_PHY_137_DATA
-				DDRSS2_PHY_138_DATA
-				DDRSS2_PHY_139_DATA
-				DDRSS2_PHY_140_DATA
-				DDRSS2_PHY_141_DATA
-				DDRSS2_PHY_142_DATA
-				DDRSS2_PHY_143_DATA
-				DDRSS2_PHY_144_DATA
-				DDRSS2_PHY_145_DATA
-				DDRSS2_PHY_146_DATA
-				DDRSS2_PHY_147_DATA
-				DDRSS2_PHY_148_DATA
-				DDRSS2_PHY_149_DATA
-				DDRSS2_PHY_150_DATA
-				DDRSS2_PHY_151_DATA
-				DDRSS2_PHY_152_DATA
-				DDRSS2_PHY_153_DATA
-				DDRSS2_PHY_154_DATA
-				DDRSS2_PHY_155_DATA
-				DDRSS2_PHY_156_DATA
-				DDRSS2_PHY_157_DATA
-				DDRSS2_PHY_158_DATA
-				DDRSS2_PHY_159_DATA
-				DDRSS2_PHY_160_DATA
-				DDRSS2_PHY_161_DATA
-				DDRSS2_PHY_162_DATA
-				DDRSS2_PHY_163_DATA
-				DDRSS2_PHY_164_DATA
-				DDRSS2_PHY_165_DATA
-				DDRSS2_PHY_166_DATA
-				DDRSS2_PHY_167_DATA
-				DDRSS2_PHY_168_DATA
-				DDRSS2_PHY_169_DATA
-				DDRSS2_PHY_170_DATA
-				DDRSS2_PHY_171_DATA
-				DDRSS2_PHY_172_DATA
-				DDRSS2_PHY_173_DATA
-				DDRSS2_PHY_174_DATA
-				DDRSS2_PHY_175_DATA
-				DDRSS2_PHY_176_DATA
-				DDRSS2_PHY_177_DATA
-				DDRSS2_PHY_178_DATA
-				DDRSS2_PHY_179_DATA
-				DDRSS2_PHY_180_DATA
-				DDRSS2_PHY_181_DATA
-				DDRSS2_PHY_182_DATA
-				DDRSS2_PHY_183_DATA
-				DDRSS2_PHY_184_DATA
-				DDRSS2_PHY_185_DATA
-				DDRSS2_PHY_186_DATA
-				DDRSS2_PHY_187_DATA
-				DDRSS2_PHY_188_DATA
-				DDRSS2_PHY_189_DATA
-				DDRSS2_PHY_190_DATA
-				DDRSS2_PHY_191_DATA
-				DDRSS2_PHY_192_DATA
-				DDRSS2_PHY_193_DATA
-				DDRSS2_PHY_194_DATA
-				DDRSS2_PHY_195_DATA
-				DDRSS2_PHY_196_DATA
-				DDRSS2_PHY_197_DATA
-				DDRSS2_PHY_198_DATA
-				DDRSS2_PHY_199_DATA
-				DDRSS2_PHY_200_DATA
-				DDRSS2_PHY_201_DATA
-				DDRSS2_PHY_202_DATA
-				DDRSS2_PHY_203_DATA
-				DDRSS2_PHY_204_DATA
-				DDRSS2_PHY_205_DATA
-				DDRSS2_PHY_206_DATA
-				DDRSS2_PHY_207_DATA
-				DDRSS2_PHY_208_DATA
-				DDRSS2_PHY_209_DATA
-				DDRSS2_PHY_210_DATA
-				DDRSS2_PHY_211_DATA
-				DDRSS2_PHY_212_DATA
-				DDRSS2_PHY_213_DATA
-				DDRSS2_PHY_214_DATA
-				DDRSS2_PHY_215_DATA
-				DDRSS2_PHY_216_DATA
-				DDRSS2_PHY_217_DATA
-				DDRSS2_PHY_218_DATA
-				DDRSS2_PHY_219_DATA
-				DDRSS2_PHY_220_DATA
-				DDRSS2_PHY_221_DATA
-				DDRSS2_PHY_222_DATA
-				DDRSS2_PHY_223_DATA
-				DDRSS2_PHY_224_DATA
-				DDRSS2_PHY_225_DATA
-				DDRSS2_PHY_226_DATA
-				DDRSS2_PHY_227_DATA
-				DDRSS2_PHY_228_DATA
-				DDRSS2_PHY_229_DATA
-				DDRSS2_PHY_230_DATA
-				DDRSS2_PHY_231_DATA
-				DDRSS2_PHY_232_DATA
-				DDRSS2_PHY_233_DATA
-				DDRSS2_PHY_234_DATA
-				DDRSS2_PHY_235_DATA
-				DDRSS2_PHY_236_DATA
-				DDRSS2_PHY_237_DATA
-				DDRSS2_PHY_238_DATA
-				DDRSS2_PHY_239_DATA
-				DDRSS2_PHY_240_DATA
-				DDRSS2_PHY_241_DATA
-				DDRSS2_PHY_242_DATA
-				DDRSS2_PHY_243_DATA
-				DDRSS2_PHY_244_DATA
-				DDRSS2_PHY_245_DATA
-				DDRSS2_PHY_246_DATA
-				DDRSS2_PHY_247_DATA
-				DDRSS2_PHY_248_DATA
-				DDRSS2_PHY_249_DATA
-				DDRSS2_PHY_250_DATA
-				DDRSS2_PHY_251_DATA
-				DDRSS2_PHY_252_DATA
-				DDRSS2_PHY_253_DATA
-				DDRSS2_PHY_254_DATA
-				DDRSS2_PHY_255_DATA
-				DDRSS2_PHY_256_DATA
-				DDRSS2_PHY_257_DATA
-				DDRSS2_PHY_258_DATA
-				DDRSS2_PHY_259_DATA
-				DDRSS2_PHY_260_DATA
-				DDRSS2_PHY_261_DATA
-				DDRSS2_PHY_262_DATA
-				DDRSS2_PHY_263_DATA
-				DDRSS2_PHY_264_DATA
-				DDRSS2_PHY_265_DATA
-				DDRSS2_PHY_266_DATA
-				DDRSS2_PHY_267_DATA
-				DDRSS2_PHY_268_DATA
-				DDRSS2_PHY_269_DATA
-				DDRSS2_PHY_270_DATA
-				DDRSS2_PHY_271_DATA
-				DDRSS2_PHY_272_DATA
-				DDRSS2_PHY_273_DATA
-				DDRSS2_PHY_274_DATA
-				DDRSS2_PHY_275_DATA
-				DDRSS2_PHY_276_DATA
-				DDRSS2_PHY_277_DATA
-				DDRSS2_PHY_278_DATA
-				DDRSS2_PHY_279_DATA
-				DDRSS2_PHY_280_DATA
-				DDRSS2_PHY_281_DATA
-				DDRSS2_PHY_282_DATA
-				DDRSS2_PHY_283_DATA
-				DDRSS2_PHY_284_DATA
-				DDRSS2_PHY_285_DATA
-				DDRSS2_PHY_286_DATA
-				DDRSS2_PHY_287_DATA
-				DDRSS2_PHY_288_DATA
-				DDRSS2_PHY_289_DATA
-				DDRSS2_PHY_290_DATA
-				DDRSS2_PHY_291_DATA
-				DDRSS2_PHY_292_DATA
-				DDRSS2_PHY_293_DATA
-				DDRSS2_PHY_294_DATA
-				DDRSS2_PHY_295_DATA
-				DDRSS2_PHY_296_DATA
-				DDRSS2_PHY_297_DATA
-				DDRSS2_PHY_298_DATA
-				DDRSS2_PHY_299_DATA
-				DDRSS2_PHY_300_DATA
-				DDRSS2_PHY_301_DATA
-				DDRSS2_PHY_302_DATA
-				DDRSS2_PHY_303_DATA
-				DDRSS2_PHY_304_DATA
-				DDRSS2_PHY_305_DATA
-				DDRSS2_PHY_306_DATA
-				DDRSS2_PHY_307_DATA
-				DDRSS2_PHY_308_DATA
-				DDRSS2_PHY_309_DATA
-				DDRSS2_PHY_310_DATA
-				DDRSS2_PHY_311_DATA
-				DDRSS2_PHY_312_DATA
-				DDRSS2_PHY_313_DATA
-				DDRSS2_PHY_314_DATA
-				DDRSS2_PHY_315_DATA
-				DDRSS2_PHY_316_DATA
-				DDRSS2_PHY_317_DATA
-				DDRSS2_PHY_318_DATA
-				DDRSS2_PHY_319_DATA
-				DDRSS2_PHY_320_DATA
-				DDRSS2_PHY_321_DATA
-				DDRSS2_PHY_322_DATA
-				DDRSS2_PHY_323_DATA
-				DDRSS2_PHY_324_DATA
-				DDRSS2_PHY_325_DATA
-				DDRSS2_PHY_326_DATA
-				DDRSS2_PHY_327_DATA
-				DDRSS2_PHY_328_DATA
-				DDRSS2_PHY_329_DATA
-				DDRSS2_PHY_330_DATA
-				DDRSS2_PHY_331_DATA
-				DDRSS2_PHY_332_DATA
-				DDRSS2_PHY_333_DATA
-				DDRSS2_PHY_334_DATA
-				DDRSS2_PHY_335_DATA
-				DDRSS2_PHY_336_DATA
-				DDRSS2_PHY_337_DATA
-				DDRSS2_PHY_338_DATA
-				DDRSS2_PHY_339_DATA
-				DDRSS2_PHY_340_DATA
-				DDRSS2_PHY_341_DATA
-				DDRSS2_PHY_342_DATA
-				DDRSS2_PHY_343_DATA
-				DDRSS2_PHY_344_DATA
-				DDRSS2_PHY_345_DATA
-				DDRSS2_PHY_346_DATA
-				DDRSS2_PHY_347_DATA
-				DDRSS2_PHY_348_DATA
-				DDRSS2_PHY_349_DATA
-				DDRSS2_PHY_350_DATA
-				DDRSS2_PHY_351_DATA
-				DDRSS2_PHY_352_DATA
-				DDRSS2_PHY_353_DATA
-				DDRSS2_PHY_354_DATA
-				DDRSS2_PHY_355_DATA
-				DDRSS2_PHY_356_DATA
-				DDRSS2_PHY_357_DATA
-				DDRSS2_PHY_358_DATA
-				DDRSS2_PHY_359_DATA
-				DDRSS2_PHY_360_DATA
-				DDRSS2_PHY_361_DATA
-				DDRSS2_PHY_362_DATA
-				DDRSS2_PHY_363_DATA
-				DDRSS2_PHY_364_DATA
-				DDRSS2_PHY_365_DATA
-				DDRSS2_PHY_366_DATA
-				DDRSS2_PHY_367_DATA
-				DDRSS2_PHY_368_DATA
-				DDRSS2_PHY_369_DATA
-				DDRSS2_PHY_370_DATA
-				DDRSS2_PHY_371_DATA
-				DDRSS2_PHY_372_DATA
-				DDRSS2_PHY_373_DATA
-				DDRSS2_PHY_374_DATA
-				DDRSS2_PHY_375_DATA
-				DDRSS2_PHY_376_DATA
-				DDRSS2_PHY_377_DATA
-				DDRSS2_PHY_378_DATA
-				DDRSS2_PHY_379_DATA
-				DDRSS2_PHY_380_DATA
-				DDRSS2_PHY_381_DATA
-				DDRSS2_PHY_382_DATA
-				DDRSS2_PHY_383_DATA
-				DDRSS2_PHY_384_DATA
-				DDRSS2_PHY_385_DATA
-				DDRSS2_PHY_386_DATA
-				DDRSS2_PHY_387_DATA
-				DDRSS2_PHY_388_DATA
-				DDRSS2_PHY_389_DATA
-				DDRSS2_PHY_390_DATA
-				DDRSS2_PHY_391_DATA
-				DDRSS2_PHY_392_DATA
-				DDRSS2_PHY_393_DATA
-				DDRSS2_PHY_394_DATA
-				DDRSS2_PHY_395_DATA
-				DDRSS2_PHY_396_DATA
-				DDRSS2_PHY_397_DATA
-				DDRSS2_PHY_398_DATA
-				DDRSS2_PHY_399_DATA
-				DDRSS2_PHY_400_DATA
-				DDRSS2_PHY_401_DATA
-				DDRSS2_PHY_402_DATA
-				DDRSS2_PHY_403_DATA
-				DDRSS2_PHY_404_DATA
-				DDRSS2_PHY_405_DATA
-				DDRSS2_PHY_406_DATA
-				DDRSS2_PHY_407_DATA
-				DDRSS2_PHY_408_DATA
-				DDRSS2_PHY_409_DATA
-				DDRSS2_PHY_410_DATA
-				DDRSS2_PHY_411_DATA
-				DDRSS2_PHY_412_DATA
-				DDRSS2_PHY_413_DATA
-				DDRSS2_PHY_414_DATA
-				DDRSS2_PHY_415_DATA
-				DDRSS2_PHY_416_DATA
-				DDRSS2_PHY_417_DATA
-				DDRSS2_PHY_418_DATA
-				DDRSS2_PHY_419_DATA
-				DDRSS2_PHY_420_DATA
-				DDRSS2_PHY_421_DATA
-				DDRSS2_PHY_422_DATA
-				DDRSS2_PHY_423_DATA
-				DDRSS2_PHY_424_DATA
-				DDRSS2_PHY_425_DATA
-				DDRSS2_PHY_426_DATA
-				DDRSS2_PHY_427_DATA
-				DDRSS2_PHY_428_DATA
-				DDRSS2_PHY_429_DATA
-				DDRSS2_PHY_430_DATA
-				DDRSS2_PHY_431_DATA
-				DDRSS2_PHY_432_DATA
-				DDRSS2_PHY_433_DATA
-				DDRSS2_PHY_434_DATA
-				DDRSS2_PHY_435_DATA
-				DDRSS2_PHY_436_DATA
-				DDRSS2_PHY_437_DATA
-				DDRSS2_PHY_438_DATA
-				DDRSS2_PHY_439_DATA
-				DDRSS2_PHY_440_DATA
-				DDRSS2_PHY_441_DATA
-				DDRSS2_PHY_442_DATA
-				DDRSS2_PHY_443_DATA
-				DDRSS2_PHY_444_DATA
-				DDRSS2_PHY_445_DATA
-				DDRSS2_PHY_446_DATA
-				DDRSS2_PHY_447_DATA
-				DDRSS2_PHY_448_DATA
-				DDRSS2_PHY_449_DATA
-				DDRSS2_PHY_450_DATA
-				DDRSS2_PHY_451_DATA
-				DDRSS2_PHY_452_DATA
-				DDRSS2_PHY_453_DATA
-				DDRSS2_PHY_454_DATA
-				DDRSS2_PHY_455_DATA
-				DDRSS2_PHY_456_DATA
-				DDRSS2_PHY_457_DATA
-				DDRSS2_PHY_458_DATA
-				DDRSS2_PHY_459_DATA
-				DDRSS2_PHY_460_DATA
-				DDRSS2_PHY_461_DATA
-				DDRSS2_PHY_462_DATA
-				DDRSS2_PHY_463_DATA
-				DDRSS2_PHY_464_DATA
-				DDRSS2_PHY_465_DATA
-				DDRSS2_PHY_466_DATA
-				DDRSS2_PHY_467_DATA
-				DDRSS2_PHY_468_DATA
-				DDRSS2_PHY_469_DATA
-				DDRSS2_PHY_470_DATA
-				DDRSS2_PHY_471_DATA
-				DDRSS2_PHY_472_DATA
-				DDRSS2_PHY_473_DATA
-				DDRSS2_PHY_474_DATA
-				DDRSS2_PHY_475_DATA
-				DDRSS2_PHY_476_DATA
-				DDRSS2_PHY_477_DATA
-				DDRSS2_PHY_478_DATA
-				DDRSS2_PHY_479_DATA
-				DDRSS2_PHY_480_DATA
-				DDRSS2_PHY_481_DATA
-				DDRSS2_PHY_482_DATA
-				DDRSS2_PHY_483_DATA
-				DDRSS2_PHY_484_DATA
-				DDRSS2_PHY_485_DATA
-				DDRSS2_PHY_486_DATA
-				DDRSS2_PHY_487_DATA
-				DDRSS2_PHY_488_DATA
-				DDRSS2_PHY_489_DATA
-				DDRSS2_PHY_490_DATA
-				DDRSS2_PHY_491_DATA
-				DDRSS2_PHY_492_DATA
-				DDRSS2_PHY_493_DATA
-				DDRSS2_PHY_494_DATA
-				DDRSS2_PHY_495_DATA
-				DDRSS2_PHY_496_DATA
-				DDRSS2_PHY_497_DATA
-				DDRSS2_PHY_498_DATA
-				DDRSS2_PHY_499_DATA
-				DDRSS2_PHY_500_DATA
-				DDRSS2_PHY_501_DATA
-				DDRSS2_PHY_502_DATA
-				DDRSS2_PHY_503_DATA
-				DDRSS2_PHY_504_DATA
-				DDRSS2_PHY_505_DATA
-				DDRSS2_PHY_506_DATA
-				DDRSS2_PHY_507_DATA
-				DDRSS2_PHY_508_DATA
-				DDRSS2_PHY_509_DATA
-				DDRSS2_PHY_510_DATA
-				DDRSS2_PHY_511_DATA
-				DDRSS2_PHY_512_DATA
-				DDRSS2_PHY_513_DATA
-				DDRSS2_PHY_514_DATA
-				DDRSS2_PHY_515_DATA
-				DDRSS2_PHY_516_DATA
-				DDRSS2_PHY_517_DATA
-				DDRSS2_PHY_518_DATA
-				DDRSS2_PHY_519_DATA
-				DDRSS2_PHY_520_DATA
-				DDRSS2_PHY_521_DATA
-				DDRSS2_PHY_522_DATA
-				DDRSS2_PHY_523_DATA
-				DDRSS2_PHY_524_DATA
-				DDRSS2_PHY_525_DATA
-				DDRSS2_PHY_526_DATA
-				DDRSS2_PHY_527_DATA
-				DDRSS2_PHY_528_DATA
-				DDRSS2_PHY_529_DATA
-				DDRSS2_PHY_530_DATA
-				DDRSS2_PHY_531_DATA
-				DDRSS2_PHY_532_DATA
-				DDRSS2_PHY_533_DATA
-				DDRSS2_PHY_534_DATA
-				DDRSS2_PHY_535_DATA
-				DDRSS2_PHY_536_DATA
-				DDRSS2_PHY_537_DATA
-				DDRSS2_PHY_538_DATA
-				DDRSS2_PHY_539_DATA
-				DDRSS2_PHY_540_DATA
-				DDRSS2_PHY_541_DATA
-				DDRSS2_PHY_542_DATA
-				DDRSS2_PHY_543_DATA
-				DDRSS2_PHY_544_DATA
-				DDRSS2_PHY_545_DATA
-				DDRSS2_PHY_546_DATA
-				DDRSS2_PHY_547_DATA
-				DDRSS2_PHY_548_DATA
-				DDRSS2_PHY_549_DATA
-				DDRSS2_PHY_550_DATA
-				DDRSS2_PHY_551_DATA
-				DDRSS2_PHY_552_DATA
-				DDRSS2_PHY_553_DATA
-				DDRSS2_PHY_554_DATA
-				DDRSS2_PHY_555_DATA
-				DDRSS2_PHY_556_DATA
-				DDRSS2_PHY_557_DATA
-				DDRSS2_PHY_558_DATA
-				DDRSS2_PHY_559_DATA
-				DDRSS2_PHY_560_DATA
-				DDRSS2_PHY_561_DATA
-				DDRSS2_PHY_562_DATA
-				DDRSS2_PHY_563_DATA
-				DDRSS2_PHY_564_DATA
-				DDRSS2_PHY_565_DATA
-				DDRSS2_PHY_566_DATA
-				DDRSS2_PHY_567_DATA
-				DDRSS2_PHY_568_DATA
-				DDRSS2_PHY_569_DATA
-				DDRSS2_PHY_570_DATA
-				DDRSS2_PHY_571_DATA
-				DDRSS2_PHY_572_DATA
-				DDRSS2_PHY_573_DATA
-				DDRSS2_PHY_574_DATA
-				DDRSS2_PHY_575_DATA
-				DDRSS2_PHY_576_DATA
-				DDRSS2_PHY_577_DATA
-				DDRSS2_PHY_578_DATA
-				DDRSS2_PHY_579_DATA
-				DDRSS2_PHY_580_DATA
-				DDRSS2_PHY_581_DATA
-				DDRSS2_PHY_582_DATA
-				DDRSS2_PHY_583_DATA
-				DDRSS2_PHY_584_DATA
-				DDRSS2_PHY_585_DATA
-				DDRSS2_PHY_586_DATA
-				DDRSS2_PHY_587_DATA
-				DDRSS2_PHY_588_DATA
-				DDRSS2_PHY_589_DATA
-				DDRSS2_PHY_590_DATA
-				DDRSS2_PHY_591_DATA
-				DDRSS2_PHY_592_DATA
-				DDRSS2_PHY_593_DATA
-				DDRSS2_PHY_594_DATA
-				DDRSS2_PHY_595_DATA
-				DDRSS2_PHY_596_DATA
-				DDRSS2_PHY_597_DATA
-				DDRSS2_PHY_598_DATA
-				DDRSS2_PHY_599_DATA
-				DDRSS2_PHY_600_DATA
-				DDRSS2_PHY_601_DATA
-				DDRSS2_PHY_602_DATA
-				DDRSS2_PHY_603_DATA
-				DDRSS2_PHY_604_DATA
-				DDRSS2_PHY_605_DATA
-				DDRSS2_PHY_606_DATA
-				DDRSS2_PHY_607_DATA
-				DDRSS2_PHY_608_DATA
-				DDRSS2_PHY_609_DATA
-				DDRSS2_PHY_610_DATA
-				DDRSS2_PHY_611_DATA
-				DDRSS2_PHY_612_DATA
-				DDRSS2_PHY_613_DATA
-				DDRSS2_PHY_614_DATA
-				DDRSS2_PHY_615_DATA
-				DDRSS2_PHY_616_DATA
-				DDRSS2_PHY_617_DATA
-				DDRSS2_PHY_618_DATA
-				DDRSS2_PHY_619_DATA
-				DDRSS2_PHY_620_DATA
-				DDRSS2_PHY_621_DATA
-				DDRSS2_PHY_622_DATA
-				DDRSS2_PHY_623_DATA
-				DDRSS2_PHY_624_DATA
-				DDRSS2_PHY_625_DATA
-				DDRSS2_PHY_626_DATA
-				DDRSS2_PHY_627_DATA
-				DDRSS2_PHY_628_DATA
-				DDRSS2_PHY_629_DATA
-				DDRSS2_PHY_630_DATA
-				DDRSS2_PHY_631_DATA
-				DDRSS2_PHY_632_DATA
-				DDRSS2_PHY_633_DATA
-				DDRSS2_PHY_634_DATA
-				DDRSS2_PHY_635_DATA
-				DDRSS2_PHY_636_DATA
-				DDRSS2_PHY_637_DATA
-				DDRSS2_PHY_638_DATA
-				DDRSS2_PHY_639_DATA
-				DDRSS2_PHY_640_DATA
-				DDRSS2_PHY_641_DATA
-				DDRSS2_PHY_642_DATA
-				DDRSS2_PHY_643_DATA
-				DDRSS2_PHY_644_DATA
-				DDRSS2_PHY_645_DATA
-				DDRSS2_PHY_646_DATA
-				DDRSS2_PHY_647_DATA
-				DDRSS2_PHY_648_DATA
-				DDRSS2_PHY_649_DATA
-				DDRSS2_PHY_650_DATA
-				DDRSS2_PHY_651_DATA
-				DDRSS2_PHY_652_DATA
-				DDRSS2_PHY_653_DATA
-				DDRSS2_PHY_654_DATA
-				DDRSS2_PHY_655_DATA
-				DDRSS2_PHY_656_DATA
-				DDRSS2_PHY_657_DATA
-				DDRSS2_PHY_658_DATA
-				DDRSS2_PHY_659_DATA
-				DDRSS2_PHY_660_DATA
-				DDRSS2_PHY_661_DATA
-				DDRSS2_PHY_662_DATA
-				DDRSS2_PHY_663_DATA
-				DDRSS2_PHY_664_DATA
-				DDRSS2_PHY_665_DATA
-				DDRSS2_PHY_666_DATA
-				DDRSS2_PHY_667_DATA
-				DDRSS2_PHY_668_DATA
-				DDRSS2_PHY_669_DATA
-				DDRSS2_PHY_670_DATA
-				DDRSS2_PHY_671_DATA
-				DDRSS2_PHY_672_DATA
-				DDRSS2_PHY_673_DATA
-				DDRSS2_PHY_674_DATA
-				DDRSS2_PHY_675_DATA
-				DDRSS2_PHY_676_DATA
-				DDRSS2_PHY_677_DATA
-				DDRSS2_PHY_678_DATA
-				DDRSS2_PHY_679_DATA
-				DDRSS2_PHY_680_DATA
-				DDRSS2_PHY_681_DATA
-				DDRSS2_PHY_682_DATA
-				DDRSS2_PHY_683_DATA
-				DDRSS2_PHY_684_DATA
-				DDRSS2_PHY_685_DATA
-				DDRSS2_PHY_686_DATA
-				DDRSS2_PHY_687_DATA
-				DDRSS2_PHY_688_DATA
-				DDRSS2_PHY_689_DATA
-				DDRSS2_PHY_690_DATA
-				DDRSS2_PHY_691_DATA
-				DDRSS2_PHY_692_DATA
-				DDRSS2_PHY_693_DATA
-				DDRSS2_PHY_694_DATA
-				DDRSS2_PHY_695_DATA
-				DDRSS2_PHY_696_DATA
-				DDRSS2_PHY_697_DATA
-				DDRSS2_PHY_698_DATA
-				DDRSS2_PHY_699_DATA
-				DDRSS2_PHY_700_DATA
-				DDRSS2_PHY_701_DATA
-				DDRSS2_PHY_702_DATA
-				DDRSS2_PHY_703_DATA
-				DDRSS2_PHY_704_DATA
-				DDRSS2_PHY_705_DATA
-				DDRSS2_PHY_706_DATA
-				DDRSS2_PHY_707_DATA
-				DDRSS2_PHY_708_DATA
-				DDRSS2_PHY_709_DATA
-				DDRSS2_PHY_710_DATA
-				DDRSS2_PHY_711_DATA
-				DDRSS2_PHY_712_DATA
-				DDRSS2_PHY_713_DATA
-				DDRSS2_PHY_714_DATA
-				DDRSS2_PHY_715_DATA
-				DDRSS2_PHY_716_DATA
-				DDRSS2_PHY_717_DATA
-				DDRSS2_PHY_718_DATA
-				DDRSS2_PHY_719_DATA
-				DDRSS2_PHY_720_DATA
-				DDRSS2_PHY_721_DATA
-				DDRSS2_PHY_722_DATA
-				DDRSS2_PHY_723_DATA
-				DDRSS2_PHY_724_DATA
-				DDRSS2_PHY_725_DATA
-				DDRSS2_PHY_726_DATA
-				DDRSS2_PHY_727_DATA
-				DDRSS2_PHY_728_DATA
-				DDRSS2_PHY_729_DATA
-				DDRSS2_PHY_730_DATA
-				DDRSS2_PHY_731_DATA
-				DDRSS2_PHY_732_DATA
-				DDRSS2_PHY_733_DATA
-				DDRSS2_PHY_734_DATA
-				DDRSS2_PHY_735_DATA
-				DDRSS2_PHY_736_DATA
-				DDRSS2_PHY_737_DATA
-				DDRSS2_PHY_738_DATA
-				DDRSS2_PHY_739_DATA
-				DDRSS2_PHY_740_DATA
-				DDRSS2_PHY_741_DATA
-				DDRSS2_PHY_742_DATA
-				DDRSS2_PHY_743_DATA
-				DDRSS2_PHY_744_DATA
-				DDRSS2_PHY_745_DATA
-				DDRSS2_PHY_746_DATA
-				DDRSS2_PHY_747_DATA
-				DDRSS2_PHY_748_DATA
-				DDRSS2_PHY_749_DATA
-				DDRSS2_PHY_750_DATA
-				DDRSS2_PHY_751_DATA
-				DDRSS2_PHY_752_DATA
-				DDRSS2_PHY_753_DATA
-				DDRSS2_PHY_754_DATA
-				DDRSS2_PHY_755_DATA
-				DDRSS2_PHY_756_DATA
-				DDRSS2_PHY_757_DATA
-				DDRSS2_PHY_758_DATA
-				DDRSS2_PHY_759_DATA
-				DDRSS2_PHY_760_DATA
-				DDRSS2_PHY_761_DATA
-				DDRSS2_PHY_762_DATA
-				DDRSS2_PHY_763_DATA
-				DDRSS2_PHY_764_DATA
-				DDRSS2_PHY_765_DATA
-				DDRSS2_PHY_766_DATA
-				DDRSS2_PHY_767_DATA
-				DDRSS2_PHY_768_DATA
-				DDRSS2_PHY_769_DATA
-				DDRSS2_PHY_770_DATA
-				DDRSS2_PHY_771_DATA
-				DDRSS2_PHY_772_DATA
-				DDRSS2_PHY_773_DATA
-				DDRSS2_PHY_774_DATA
-				DDRSS2_PHY_775_DATA
-				DDRSS2_PHY_776_DATA
-				DDRSS2_PHY_777_DATA
-				DDRSS2_PHY_778_DATA
-				DDRSS2_PHY_779_DATA
-				DDRSS2_PHY_780_DATA
-				DDRSS2_PHY_781_DATA
-				DDRSS2_PHY_782_DATA
-				DDRSS2_PHY_783_DATA
-				DDRSS2_PHY_784_DATA
-				DDRSS2_PHY_785_DATA
-				DDRSS2_PHY_786_DATA
-				DDRSS2_PHY_787_DATA
-				DDRSS2_PHY_788_DATA
-				DDRSS2_PHY_789_DATA
-				DDRSS2_PHY_790_DATA
-				DDRSS2_PHY_791_DATA
-				DDRSS2_PHY_792_DATA
-				DDRSS2_PHY_793_DATA
-				DDRSS2_PHY_794_DATA
-				DDRSS2_PHY_795_DATA
-				DDRSS2_PHY_796_DATA
-				DDRSS2_PHY_797_DATA
-				DDRSS2_PHY_798_DATA
-				DDRSS2_PHY_799_DATA
-				DDRSS2_PHY_800_DATA
-				DDRSS2_PHY_801_DATA
-				DDRSS2_PHY_802_DATA
-				DDRSS2_PHY_803_DATA
-				DDRSS2_PHY_804_DATA
-				DDRSS2_PHY_805_DATA
-				DDRSS2_PHY_806_DATA
-				DDRSS2_PHY_807_DATA
-				DDRSS2_PHY_808_DATA
-				DDRSS2_PHY_809_DATA
-				DDRSS2_PHY_810_DATA
-				DDRSS2_PHY_811_DATA
-				DDRSS2_PHY_812_DATA
-				DDRSS2_PHY_813_DATA
-				DDRSS2_PHY_814_DATA
-				DDRSS2_PHY_815_DATA
-				DDRSS2_PHY_816_DATA
-				DDRSS2_PHY_817_DATA
-				DDRSS2_PHY_818_DATA
-				DDRSS2_PHY_819_DATA
-				DDRSS2_PHY_820_DATA
-				DDRSS2_PHY_821_DATA
-				DDRSS2_PHY_822_DATA
-				DDRSS2_PHY_823_DATA
-				DDRSS2_PHY_824_DATA
-				DDRSS2_PHY_825_DATA
-				DDRSS2_PHY_826_DATA
-				DDRSS2_PHY_827_DATA
-				DDRSS2_PHY_828_DATA
-				DDRSS2_PHY_829_DATA
-				DDRSS2_PHY_830_DATA
-				DDRSS2_PHY_831_DATA
-				DDRSS2_PHY_832_DATA
-				DDRSS2_PHY_833_DATA
-				DDRSS2_PHY_834_DATA
-				DDRSS2_PHY_835_DATA
-				DDRSS2_PHY_836_DATA
-				DDRSS2_PHY_837_DATA
-				DDRSS2_PHY_838_DATA
-				DDRSS2_PHY_839_DATA
-				DDRSS2_PHY_840_DATA
-				DDRSS2_PHY_841_DATA
-				DDRSS2_PHY_842_DATA
-				DDRSS2_PHY_843_DATA
-				DDRSS2_PHY_844_DATA
-				DDRSS2_PHY_845_DATA
-				DDRSS2_PHY_846_DATA
-				DDRSS2_PHY_847_DATA
-				DDRSS2_PHY_848_DATA
-				DDRSS2_PHY_849_DATA
-				DDRSS2_PHY_850_DATA
-				DDRSS2_PHY_851_DATA
-				DDRSS2_PHY_852_DATA
-				DDRSS2_PHY_853_DATA
-				DDRSS2_PHY_854_DATA
-				DDRSS2_PHY_855_DATA
-				DDRSS2_PHY_856_DATA
-				DDRSS2_PHY_857_DATA
-				DDRSS2_PHY_858_DATA
-				DDRSS2_PHY_859_DATA
-				DDRSS2_PHY_860_DATA
-				DDRSS2_PHY_861_DATA
-				DDRSS2_PHY_862_DATA
-				DDRSS2_PHY_863_DATA
-				DDRSS2_PHY_864_DATA
-				DDRSS2_PHY_865_DATA
-				DDRSS2_PHY_866_DATA
-				DDRSS2_PHY_867_DATA
-				DDRSS2_PHY_868_DATA
-				DDRSS2_PHY_869_DATA
-				DDRSS2_PHY_870_DATA
-				DDRSS2_PHY_871_DATA
-				DDRSS2_PHY_872_DATA
-				DDRSS2_PHY_873_DATA
-				DDRSS2_PHY_874_DATA
-				DDRSS2_PHY_875_DATA
-				DDRSS2_PHY_876_DATA
-				DDRSS2_PHY_877_DATA
-				DDRSS2_PHY_878_DATA
-				DDRSS2_PHY_879_DATA
-				DDRSS2_PHY_880_DATA
-				DDRSS2_PHY_881_DATA
-				DDRSS2_PHY_882_DATA
-				DDRSS2_PHY_883_DATA
-				DDRSS2_PHY_884_DATA
-				DDRSS2_PHY_885_DATA
-				DDRSS2_PHY_886_DATA
-				DDRSS2_PHY_887_DATA
-				DDRSS2_PHY_888_DATA
-				DDRSS2_PHY_889_DATA
-				DDRSS2_PHY_890_DATA
-				DDRSS2_PHY_891_DATA
-				DDRSS2_PHY_892_DATA
-				DDRSS2_PHY_893_DATA
-				DDRSS2_PHY_894_DATA
-				DDRSS2_PHY_895_DATA
-				DDRSS2_PHY_896_DATA
-				DDRSS2_PHY_897_DATA
-				DDRSS2_PHY_898_DATA
-				DDRSS2_PHY_899_DATA
-				DDRSS2_PHY_900_DATA
-				DDRSS2_PHY_901_DATA
-				DDRSS2_PHY_902_DATA
-				DDRSS2_PHY_903_DATA
-				DDRSS2_PHY_904_DATA
-				DDRSS2_PHY_905_DATA
-				DDRSS2_PHY_906_DATA
-				DDRSS2_PHY_907_DATA
-				DDRSS2_PHY_908_DATA
-				DDRSS2_PHY_909_DATA
-				DDRSS2_PHY_910_DATA
-				DDRSS2_PHY_911_DATA
-				DDRSS2_PHY_912_DATA
-				DDRSS2_PHY_913_DATA
-				DDRSS2_PHY_914_DATA
-				DDRSS2_PHY_915_DATA
-				DDRSS2_PHY_916_DATA
-				DDRSS2_PHY_917_DATA
-				DDRSS2_PHY_918_DATA
-				DDRSS2_PHY_919_DATA
-				DDRSS2_PHY_920_DATA
-				DDRSS2_PHY_921_DATA
-				DDRSS2_PHY_922_DATA
-				DDRSS2_PHY_923_DATA
-				DDRSS2_PHY_924_DATA
-				DDRSS2_PHY_925_DATA
-				DDRSS2_PHY_926_DATA
-				DDRSS2_PHY_927_DATA
-				DDRSS2_PHY_928_DATA
-				DDRSS2_PHY_929_DATA
-				DDRSS2_PHY_930_DATA
-				DDRSS2_PHY_931_DATA
-				DDRSS2_PHY_932_DATA
-				DDRSS2_PHY_933_DATA
-				DDRSS2_PHY_934_DATA
-				DDRSS2_PHY_935_DATA
-				DDRSS2_PHY_936_DATA
-				DDRSS2_PHY_937_DATA
-				DDRSS2_PHY_938_DATA
-				DDRSS2_PHY_939_DATA
-				DDRSS2_PHY_940_DATA
-				DDRSS2_PHY_941_DATA
-				DDRSS2_PHY_942_DATA
-				DDRSS2_PHY_943_DATA
-				DDRSS2_PHY_944_DATA
-				DDRSS2_PHY_945_DATA
-				DDRSS2_PHY_946_DATA
-				DDRSS2_PHY_947_DATA
-				DDRSS2_PHY_948_DATA
-				DDRSS2_PHY_949_DATA
-				DDRSS2_PHY_950_DATA
-				DDRSS2_PHY_951_DATA
-				DDRSS2_PHY_952_DATA
-				DDRSS2_PHY_953_DATA
-				DDRSS2_PHY_954_DATA
-				DDRSS2_PHY_955_DATA
-				DDRSS2_PHY_956_DATA
-				DDRSS2_PHY_957_DATA
-				DDRSS2_PHY_958_DATA
-				DDRSS2_PHY_959_DATA
-				DDRSS2_PHY_960_DATA
-				DDRSS2_PHY_961_DATA
-				DDRSS2_PHY_962_DATA
-				DDRSS2_PHY_963_DATA
-				DDRSS2_PHY_964_DATA
-				DDRSS2_PHY_965_DATA
-				DDRSS2_PHY_966_DATA
-				DDRSS2_PHY_967_DATA
-				DDRSS2_PHY_968_DATA
-				DDRSS2_PHY_969_DATA
-				DDRSS2_PHY_970_DATA
-				DDRSS2_PHY_971_DATA
-				DDRSS2_PHY_972_DATA
-				DDRSS2_PHY_973_DATA
-				DDRSS2_PHY_974_DATA
-				DDRSS2_PHY_975_DATA
-				DDRSS2_PHY_976_DATA
-				DDRSS2_PHY_977_DATA
-				DDRSS2_PHY_978_DATA
-				DDRSS2_PHY_979_DATA
-				DDRSS2_PHY_980_DATA
-				DDRSS2_PHY_981_DATA
-				DDRSS2_PHY_982_DATA
-				DDRSS2_PHY_983_DATA
-				DDRSS2_PHY_984_DATA
-				DDRSS2_PHY_985_DATA
-				DDRSS2_PHY_986_DATA
-				DDRSS2_PHY_987_DATA
-				DDRSS2_PHY_988_DATA
-				DDRSS2_PHY_989_DATA
-				DDRSS2_PHY_990_DATA
-				DDRSS2_PHY_991_DATA
-				DDRSS2_PHY_992_DATA
-				DDRSS2_PHY_993_DATA
-				DDRSS2_PHY_994_DATA
-				DDRSS2_PHY_995_DATA
-				DDRSS2_PHY_996_DATA
-				DDRSS2_PHY_997_DATA
-				DDRSS2_PHY_998_DATA
-				DDRSS2_PHY_999_DATA
-				DDRSS2_PHY_1000_DATA
-				DDRSS2_PHY_1001_DATA
-				DDRSS2_PHY_1002_DATA
-				DDRSS2_PHY_1003_DATA
-				DDRSS2_PHY_1004_DATA
-				DDRSS2_PHY_1005_DATA
-				DDRSS2_PHY_1006_DATA
-				DDRSS2_PHY_1007_DATA
-				DDRSS2_PHY_1008_DATA
-				DDRSS2_PHY_1009_DATA
-				DDRSS2_PHY_1010_DATA
-				DDRSS2_PHY_1011_DATA
-				DDRSS2_PHY_1012_DATA
-				DDRSS2_PHY_1013_DATA
-				DDRSS2_PHY_1014_DATA
-				DDRSS2_PHY_1015_DATA
-				DDRSS2_PHY_1016_DATA
-				DDRSS2_PHY_1017_DATA
-				DDRSS2_PHY_1018_DATA
-				DDRSS2_PHY_1019_DATA
-				DDRSS2_PHY_1020_DATA
-				DDRSS2_PHY_1021_DATA
-				DDRSS2_PHY_1022_DATA
-				DDRSS2_PHY_1023_DATA
-				DDRSS2_PHY_1024_DATA
-				DDRSS2_PHY_1025_DATA
-				DDRSS2_PHY_1026_DATA
-				DDRSS2_PHY_1027_DATA
-				DDRSS2_PHY_1028_DATA
-				DDRSS2_PHY_1029_DATA
-				DDRSS2_PHY_1030_DATA
-				DDRSS2_PHY_1031_DATA
-				DDRSS2_PHY_1032_DATA
-				DDRSS2_PHY_1033_DATA
-				DDRSS2_PHY_1034_DATA
-				DDRSS2_PHY_1035_DATA
-				DDRSS2_PHY_1036_DATA
-				DDRSS2_PHY_1037_DATA
-				DDRSS2_PHY_1038_DATA
-				DDRSS2_PHY_1039_DATA
-				DDRSS2_PHY_1040_DATA
-				DDRSS2_PHY_1041_DATA
-				DDRSS2_PHY_1042_DATA
-				DDRSS2_PHY_1043_DATA
-				DDRSS2_PHY_1044_DATA
-				DDRSS2_PHY_1045_DATA
-				DDRSS2_PHY_1046_DATA
-				DDRSS2_PHY_1047_DATA
-				DDRSS2_PHY_1048_DATA
-				DDRSS2_PHY_1049_DATA
-				DDRSS2_PHY_1050_DATA
-				DDRSS2_PHY_1051_DATA
-				DDRSS2_PHY_1052_DATA
-				DDRSS2_PHY_1053_DATA
-				DDRSS2_PHY_1054_DATA
-				DDRSS2_PHY_1055_DATA
-				DDRSS2_PHY_1056_DATA
-				DDRSS2_PHY_1057_DATA
-				DDRSS2_PHY_1058_DATA
-				DDRSS2_PHY_1059_DATA
-				DDRSS2_PHY_1060_DATA
-				DDRSS2_PHY_1061_DATA
-				DDRSS2_PHY_1062_DATA
-				DDRSS2_PHY_1063_DATA
-				DDRSS2_PHY_1064_DATA
-				DDRSS2_PHY_1065_DATA
-				DDRSS2_PHY_1066_DATA
-				DDRSS2_PHY_1067_DATA
-				DDRSS2_PHY_1068_DATA
-				DDRSS2_PHY_1069_DATA
-				DDRSS2_PHY_1070_DATA
-				DDRSS2_PHY_1071_DATA
-				DDRSS2_PHY_1072_DATA
-				DDRSS2_PHY_1073_DATA
-				DDRSS2_PHY_1074_DATA
-				DDRSS2_PHY_1075_DATA
-				DDRSS2_PHY_1076_DATA
-				DDRSS2_PHY_1077_DATA
-				DDRSS2_PHY_1078_DATA
-				DDRSS2_PHY_1079_DATA
-				DDRSS2_PHY_1080_DATA
-				DDRSS2_PHY_1081_DATA
-				DDRSS2_PHY_1082_DATA
-				DDRSS2_PHY_1083_DATA
-				DDRSS2_PHY_1084_DATA
-				DDRSS2_PHY_1085_DATA
-				DDRSS2_PHY_1086_DATA
-				DDRSS2_PHY_1087_DATA
-				DDRSS2_PHY_1088_DATA
-				DDRSS2_PHY_1089_DATA
-				DDRSS2_PHY_1090_DATA
-				DDRSS2_PHY_1091_DATA
-				DDRSS2_PHY_1092_DATA
-				DDRSS2_PHY_1093_DATA
-				DDRSS2_PHY_1094_DATA
-				DDRSS2_PHY_1095_DATA
-				DDRSS2_PHY_1096_DATA
-				DDRSS2_PHY_1097_DATA
-				DDRSS2_PHY_1098_DATA
-				DDRSS2_PHY_1099_DATA
-				DDRSS2_PHY_1100_DATA
-				DDRSS2_PHY_1101_DATA
-				DDRSS2_PHY_1102_DATA
-				DDRSS2_PHY_1103_DATA
-				DDRSS2_PHY_1104_DATA
-				DDRSS2_PHY_1105_DATA
-				DDRSS2_PHY_1106_DATA
-				DDRSS2_PHY_1107_DATA
-				DDRSS2_PHY_1108_DATA
-				DDRSS2_PHY_1109_DATA
-				DDRSS2_PHY_1110_DATA
-				DDRSS2_PHY_1111_DATA
-				DDRSS2_PHY_1112_DATA
-				DDRSS2_PHY_1113_DATA
-				DDRSS2_PHY_1114_DATA
-				DDRSS2_PHY_1115_DATA
-				DDRSS2_PHY_1116_DATA
-				DDRSS2_PHY_1117_DATA
-				DDRSS2_PHY_1118_DATA
-				DDRSS2_PHY_1119_DATA
-				DDRSS2_PHY_1120_DATA
-				DDRSS2_PHY_1121_DATA
-				DDRSS2_PHY_1122_DATA
-				DDRSS2_PHY_1123_DATA
-				DDRSS2_PHY_1124_DATA
-				DDRSS2_PHY_1125_DATA
-				DDRSS2_PHY_1126_DATA
-				DDRSS2_PHY_1127_DATA
-				DDRSS2_PHY_1128_DATA
-				DDRSS2_PHY_1129_DATA
-				DDRSS2_PHY_1130_DATA
-				DDRSS2_PHY_1131_DATA
-				DDRSS2_PHY_1132_DATA
-				DDRSS2_PHY_1133_DATA
-				DDRSS2_PHY_1134_DATA
-				DDRSS2_PHY_1135_DATA
-				DDRSS2_PHY_1136_DATA
-				DDRSS2_PHY_1137_DATA
-				DDRSS2_PHY_1138_DATA
-				DDRSS2_PHY_1139_DATA
-				DDRSS2_PHY_1140_DATA
-				DDRSS2_PHY_1141_DATA
-				DDRSS2_PHY_1142_DATA
-				DDRSS2_PHY_1143_DATA
-				DDRSS2_PHY_1144_DATA
-				DDRSS2_PHY_1145_DATA
-				DDRSS2_PHY_1146_DATA
-				DDRSS2_PHY_1147_DATA
-				DDRSS2_PHY_1148_DATA
-				DDRSS2_PHY_1149_DATA
-				DDRSS2_PHY_1150_DATA
-				DDRSS2_PHY_1151_DATA
-				DDRSS2_PHY_1152_DATA
-				DDRSS2_PHY_1153_DATA
-				DDRSS2_PHY_1154_DATA
-				DDRSS2_PHY_1155_DATA
-				DDRSS2_PHY_1156_DATA
-				DDRSS2_PHY_1157_DATA
-				DDRSS2_PHY_1158_DATA
-				DDRSS2_PHY_1159_DATA
-				DDRSS2_PHY_1160_DATA
-				DDRSS2_PHY_1161_DATA
-				DDRSS2_PHY_1162_DATA
-				DDRSS2_PHY_1163_DATA
-				DDRSS2_PHY_1164_DATA
-				DDRSS2_PHY_1165_DATA
-				DDRSS2_PHY_1166_DATA
-				DDRSS2_PHY_1167_DATA
-				DDRSS2_PHY_1168_DATA
-				DDRSS2_PHY_1169_DATA
-				DDRSS2_PHY_1170_DATA
-				DDRSS2_PHY_1171_DATA
-				DDRSS2_PHY_1172_DATA
-				DDRSS2_PHY_1173_DATA
-				DDRSS2_PHY_1174_DATA
-				DDRSS2_PHY_1175_DATA
-				DDRSS2_PHY_1176_DATA
-				DDRSS2_PHY_1177_DATA
-				DDRSS2_PHY_1178_DATA
-				DDRSS2_PHY_1179_DATA
-				DDRSS2_PHY_1180_DATA
-				DDRSS2_PHY_1181_DATA
-				DDRSS2_PHY_1182_DATA
-				DDRSS2_PHY_1183_DATA
-				DDRSS2_PHY_1184_DATA
-				DDRSS2_PHY_1185_DATA
-				DDRSS2_PHY_1186_DATA
-				DDRSS2_PHY_1187_DATA
-				DDRSS2_PHY_1188_DATA
-				DDRSS2_PHY_1189_DATA
-				DDRSS2_PHY_1190_DATA
-				DDRSS2_PHY_1191_DATA
-				DDRSS2_PHY_1192_DATA
-				DDRSS2_PHY_1193_DATA
-				DDRSS2_PHY_1194_DATA
-				DDRSS2_PHY_1195_DATA
-				DDRSS2_PHY_1196_DATA
-				DDRSS2_PHY_1197_DATA
-				DDRSS2_PHY_1198_DATA
-				DDRSS2_PHY_1199_DATA
-				DDRSS2_PHY_1200_DATA
-				DDRSS2_PHY_1201_DATA
-				DDRSS2_PHY_1202_DATA
-				DDRSS2_PHY_1203_DATA
-				DDRSS2_PHY_1204_DATA
-				DDRSS2_PHY_1205_DATA
-				DDRSS2_PHY_1206_DATA
-				DDRSS2_PHY_1207_DATA
-				DDRSS2_PHY_1208_DATA
-				DDRSS2_PHY_1209_DATA
-				DDRSS2_PHY_1210_DATA
-				DDRSS2_PHY_1211_DATA
-				DDRSS2_PHY_1212_DATA
-				DDRSS2_PHY_1213_DATA
-				DDRSS2_PHY_1214_DATA
-				DDRSS2_PHY_1215_DATA
-				DDRSS2_PHY_1216_DATA
-				DDRSS2_PHY_1217_DATA
-				DDRSS2_PHY_1218_DATA
-				DDRSS2_PHY_1219_DATA
-				DDRSS2_PHY_1220_DATA
-				DDRSS2_PHY_1221_DATA
-				DDRSS2_PHY_1222_DATA
-				DDRSS2_PHY_1223_DATA
-				DDRSS2_PHY_1224_DATA
-				DDRSS2_PHY_1225_DATA
-				DDRSS2_PHY_1226_DATA
-				DDRSS2_PHY_1227_DATA
-				DDRSS2_PHY_1228_DATA
-				DDRSS2_PHY_1229_DATA
-				DDRSS2_PHY_1230_DATA
-				DDRSS2_PHY_1231_DATA
-				DDRSS2_PHY_1232_DATA
-				DDRSS2_PHY_1233_DATA
-				DDRSS2_PHY_1234_DATA
-				DDRSS2_PHY_1235_DATA
-				DDRSS2_PHY_1236_DATA
-				DDRSS2_PHY_1237_DATA
-				DDRSS2_PHY_1238_DATA
-				DDRSS2_PHY_1239_DATA
-				DDRSS2_PHY_1240_DATA
-				DDRSS2_PHY_1241_DATA
-				DDRSS2_PHY_1242_DATA
-				DDRSS2_PHY_1243_DATA
-				DDRSS2_PHY_1244_DATA
-				DDRSS2_PHY_1245_DATA
-				DDRSS2_PHY_1246_DATA
-				DDRSS2_PHY_1247_DATA
-				DDRSS2_PHY_1248_DATA
-				DDRSS2_PHY_1249_DATA
-				DDRSS2_PHY_1250_DATA
-				DDRSS2_PHY_1251_DATA
-				DDRSS2_PHY_1252_DATA
-				DDRSS2_PHY_1253_DATA
-				DDRSS2_PHY_1254_DATA
-				DDRSS2_PHY_1255_DATA
-				DDRSS2_PHY_1256_DATA
-				DDRSS2_PHY_1257_DATA
-				DDRSS2_PHY_1258_DATA
-				DDRSS2_PHY_1259_DATA
-				DDRSS2_PHY_1260_DATA
-				DDRSS2_PHY_1261_DATA
-				DDRSS2_PHY_1262_DATA
-				DDRSS2_PHY_1263_DATA
-				DDRSS2_PHY_1264_DATA
-				DDRSS2_PHY_1265_DATA
-				DDRSS2_PHY_1266_DATA
-				DDRSS2_PHY_1267_DATA
-				DDRSS2_PHY_1268_DATA
-				DDRSS2_PHY_1269_DATA
-				DDRSS2_PHY_1270_DATA
-				DDRSS2_PHY_1271_DATA
-				DDRSS2_PHY_1272_DATA
-				DDRSS2_PHY_1273_DATA
-				DDRSS2_PHY_1274_DATA
-				DDRSS2_PHY_1275_DATA
-				DDRSS2_PHY_1276_DATA
-				DDRSS2_PHY_1277_DATA
-				DDRSS2_PHY_1278_DATA
-				DDRSS2_PHY_1279_DATA
-				DDRSS2_PHY_1280_DATA
-				DDRSS2_PHY_1281_DATA
-				DDRSS2_PHY_1282_DATA
-				DDRSS2_PHY_1283_DATA
-				DDRSS2_PHY_1284_DATA
-				DDRSS2_PHY_1285_DATA
-				DDRSS2_PHY_1286_DATA
-				DDRSS2_PHY_1287_DATA
-				DDRSS2_PHY_1288_DATA
-				DDRSS2_PHY_1289_DATA
-				DDRSS2_PHY_1290_DATA
-				DDRSS2_PHY_1291_DATA
-				DDRSS2_PHY_1292_DATA
-				DDRSS2_PHY_1293_DATA
-				DDRSS2_PHY_1294_DATA
-				DDRSS2_PHY_1295_DATA
-				DDRSS2_PHY_1296_DATA
-				DDRSS2_PHY_1297_DATA
-				DDRSS2_PHY_1298_DATA
-				DDRSS2_PHY_1299_DATA
-				DDRSS2_PHY_1300_DATA
-				DDRSS2_PHY_1301_DATA
-				DDRSS2_PHY_1302_DATA
-				DDRSS2_PHY_1303_DATA
-				DDRSS2_PHY_1304_DATA
-				DDRSS2_PHY_1305_DATA
-				DDRSS2_PHY_1306_DATA
-				DDRSS2_PHY_1307_DATA
-				DDRSS2_PHY_1308_DATA
-				DDRSS2_PHY_1309_DATA
-				DDRSS2_PHY_1310_DATA
-				DDRSS2_PHY_1311_DATA
-				DDRSS2_PHY_1312_DATA
-				DDRSS2_PHY_1313_DATA
-				DDRSS2_PHY_1314_DATA
-				DDRSS2_PHY_1315_DATA
-				DDRSS2_PHY_1316_DATA
-				DDRSS2_PHY_1317_DATA
-				DDRSS2_PHY_1318_DATA
-				DDRSS2_PHY_1319_DATA
-				DDRSS2_PHY_1320_DATA
-				DDRSS2_PHY_1321_DATA
-				DDRSS2_PHY_1322_DATA
-				DDRSS2_PHY_1323_DATA
-				DDRSS2_PHY_1324_DATA
-				DDRSS2_PHY_1325_DATA
-				DDRSS2_PHY_1326_DATA
-				DDRSS2_PHY_1327_DATA
-				DDRSS2_PHY_1328_DATA
-				DDRSS2_PHY_1329_DATA
-				DDRSS2_PHY_1330_DATA
-				DDRSS2_PHY_1331_DATA
-				DDRSS2_PHY_1332_DATA
-				DDRSS2_PHY_1333_DATA
-				DDRSS2_PHY_1334_DATA
-				DDRSS2_PHY_1335_DATA
-				DDRSS2_PHY_1336_DATA
-				DDRSS2_PHY_1337_DATA
-				DDRSS2_PHY_1338_DATA
-				DDRSS2_PHY_1339_DATA
-				DDRSS2_PHY_1340_DATA
-				DDRSS2_PHY_1341_DATA
-				DDRSS2_PHY_1342_DATA
-				DDRSS2_PHY_1343_DATA
-				DDRSS2_PHY_1344_DATA
-				DDRSS2_PHY_1345_DATA
-				DDRSS2_PHY_1346_DATA
-				DDRSS2_PHY_1347_DATA
-				DDRSS2_PHY_1348_DATA
-				DDRSS2_PHY_1349_DATA
-				DDRSS2_PHY_1350_DATA
-				DDRSS2_PHY_1351_DATA
-				DDRSS2_PHY_1352_DATA
-				DDRSS2_PHY_1353_DATA
-				DDRSS2_PHY_1354_DATA
-				DDRSS2_PHY_1355_DATA
-				DDRSS2_PHY_1356_DATA
-				DDRSS2_PHY_1357_DATA
-				DDRSS2_PHY_1358_DATA
-				DDRSS2_PHY_1359_DATA
-				DDRSS2_PHY_1360_DATA
-				DDRSS2_PHY_1361_DATA
-				DDRSS2_PHY_1362_DATA
-				DDRSS2_PHY_1363_DATA
-				DDRSS2_PHY_1364_DATA
-				DDRSS2_PHY_1365_DATA
-				DDRSS2_PHY_1366_DATA
-				DDRSS2_PHY_1367_DATA
-				DDRSS2_PHY_1368_DATA
-				DDRSS2_PHY_1369_DATA
-				DDRSS2_PHY_1370_DATA
-				DDRSS2_PHY_1371_DATA
-				DDRSS2_PHY_1372_DATA
-				DDRSS2_PHY_1373_DATA
-				DDRSS2_PHY_1374_DATA
-				DDRSS2_PHY_1375_DATA
-				DDRSS2_PHY_1376_DATA
-				DDRSS2_PHY_1377_DATA
-				DDRSS2_PHY_1378_DATA
-				DDRSS2_PHY_1379_DATA
-				DDRSS2_PHY_1380_DATA
-				DDRSS2_PHY_1381_DATA
-				DDRSS2_PHY_1382_DATA
-				DDRSS2_PHY_1383_DATA
-				DDRSS2_PHY_1384_DATA
-				DDRSS2_PHY_1385_DATA
-				DDRSS2_PHY_1386_DATA
-				DDRSS2_PHY_1387_DATA
-				DDRSS2_PHY_1388_DATA
-				DDRSS2_PHY_1389_DATA
-				DDRSS2_PHY_1390_DATA
-				DDRSS2_PHY_1391_DATA
-				DDRSS2_PHY_1392_DATA
-				DDRSS2_PHY_1393_DATA
-				DDRSS2_PHY_1394_DATA
-				DDRSS2_PHY_1395_DATA
-				DDRSS2_PHY_1396_DATA
-				DDRSS2_PHY_1397_DATA
-				DDRSS2_PHY_1398_DATA
-				DDRSS2_PHY_1399_DATA
-				DDRSS2_PHY_1400_DATA
-				DDRSS2_PHY_1401_DATA
-				DDRSS2_PHY_1402_DATA
-				DDRSS2_PHY_1403_DATA
-				DDRSS2_PHY_1404_DATA
-				DDRSS2_PHY_1405_DATA
-				DDRSS2_PHY_1406_DATA
-				DDRSS2_PHY_1407_DATA
-				DDRSS2_PHY_1408_DATA
-				DDRSS2_PHY_1409_DATA
-				DDRSS2_PHY_1410_DATA
-				DDRSS2_PHY_1411_DATA
-				DDRSS2_PHY_1412_DATA
-				DDRSS2_PHY_1413_DATA
-				DDRSS2_PHY_1414_DATA
-				DDRSS2_PHY_1415_DATA
-				DDRSS2_PHY_1416_DATA
-				DDRSS2_PHY_1417_DATA
-				DDRSS2_PHY_1418_DATA
-				DDRSS2_PHY_1419_DATA
-				DDRSS2_PHY_1420_DATA
-				DDRSS2_PHY_1421_DATA
-				DDRSS2_PHY_1422_DATA
-			>;
-		};
+		ti,phy-data = <
+			DDRSS2_PHY_00_DATA
+			DDRSS2_PHY_01_DATA
+			DDRSS2_PHY_02_DATA
+			DDRSS2_PHY_03_DATA
+			DDRSS2_PHY_04_DATA
+			DDRSS2_PHY_05_DATA
+			DDRSS2_PHY_06_DATA
+			DDRSS2_PHY_07_DATA
+			DDRSS2_PHY_08_DATA
+			DDRSS2_PHY_09_DATA
+			DDRSS2_PHY_10_DATA
+			DDRSS2_PHY_11_DATA
+			DDRSS2_PHY_12_DATA
+			DDRSS2_PHY_13_DATA
+			DDRSS2_PHY_14_DATA
+			DDRSS2_PHY_15_DATA
+			DDRSS2_PHY_16_DATA
+			DDRSS2_PHY_17_DATA
+			DDRSS2_PHY_18_DATA
+			DDRSS2_PHY_19_DATA
+			DDRSS2_PHY_20_DATA
+			DDRSS2_PHY_21_DATA
+			DDRSS2_PHY_22_DATA
+			DDRSS2_PHY_23_DATA
+			DDRSS2_PHY_24_DATA
+			DDRSS2_PHY_25_DATA
+			DDRSS2_PHY_26_DATA
+			DDRSS2_PHY_27_DATA
+			DDRSS2_PHY_28_DATA
+			DDRSS2_PHY_29_DATA
+			DDRSS2_PHY_30_DATA
+			DDRSS2_PHY_31_DATA
+			DDRSS2_PHY_32_DATA
+			DDRSS2_PHY_33_DATA
+			DDRSS2_PHY_34_DATA
+			DDRSS2_PHY_35_DATA
+			DDRSS2_PHY_36_DATA
+			DDRSS2_PHY_37_DATA
+			DDRSS2_PHY_38_DATA
+			DDRSS2_PHY_39_DATA
+			DDRSS2_PHY_40_DATA
+			DDRSS2_PHY_41_DATA
+			DDRSS2_PHY_42_DATA
+			DDRSS2_PHY_43_DATA
+			DDRSS2_PHY_44_DATA
+			DDRSS2_PHY_45_DATA
+			DDRSS2_PHY_46_DATA
+			DDRSS2_PHY_47_DATA
+			DDRSS2_PHY_48_DATA
+			DDRSS2_PHY_49_DATA
+			DDRSS2_PHY_50_DATA
+			DDRSS2_PHY_51_DATA
+			DDRSS2_PHY_52_DATA
+			DDRSS2_PHY_53_DATA
+			DDRSS2_PHY_54_DATA
+			DDRSS2_PHY_55_DATA
+			DDRSS2_PHY_56_DATA
+			DDRSS2_PHY_57_DATA
+			DDRSS2_PHY_58_DATA
+			DDRSS2_PHY_59_DATA
+			DDRSS2_PHY_60_DATA
+			DDRSS2_PHY_61_DATA
+			DDRSS2_PHY_62_DATA
+			DDRSS2_PHY_63_DATA
+			DDRSS2_PHY_64_DATA
+			DDRSS2_PHY_65_DATA
+			DDRSS2_PHY_66_DATA
+			DDRSS2_PHY_67_DATA
+			DDRSS2_PHY_68_DATA
+			DDRSS2_PHY_69_DATA
+			DDRSS2_PHY_70_DATA
+			DDRSS2_PHY_71_DATA
+			DDRSS2_PHY_72_DATA
+			DDRSS2_PHY_73_DATA
+			DDRSS2_PHY_74_DATA
+			DDRSS2_PHY_75_DATA
+			DDRSS2_PHY_76_DATA
+			DDRSS2_PHY_77_DATA
+			DDRSS2_PHY_78_DATA
+			DDRSS2_PHY_79_DATA
+			DDRSS2_PHY_80_DATA
+			DDRSS2_PHY_81_DATA
+			DDRSS2_PHY_82_DATA
+			DDRSS2_PHY_83_DATA
+			DDRSS2_PHY_84_DATA
+			DDRSS2_PHY_85_DATA
+			DDRSS2_PHY_86_DATA
+			DDRSS2_PHY_87_DATA
+			DDRSS2_PHY_88_DATA
+			DDRSS2_PHY_89_DATA
+			DDRSS2_PHY_90_DATA
+			DDRSS2_PHY_91_DATA
+			DDRSS2_PHY_92_DATA
+			DDRSS2_PHY_93_DATA
+			DDRSS2_PHY_94_DATA
+			DDRSS2_PHY_95_DATA
+			DDRSS2_PHY_96_DATA
+			DDRSS2_PHY_97_DATA
+			DDRSS2_PHY_98_DATA
+			DDRSS2_PHY_99_DATA
+			DDRSS2_PHY_100_DATA
+			DDRSS2_PHY_101_DATA
+			DDRSS2_PHY_102_DATA
+			DDRSS2_PHY_103_DATA
+			DDRSS2_PHY_104_DATA
+			DDRSS2_PHY_105_DATA
+			DDRSS2_PHY_106_DATA
+			DDRSS2_PHY_107_DATA
+			DDRSS2_PHY_108_DATA
+			DDRSS2_PHY_109_DATA
+			DDRSS2_PHY_110_DATA
+			DDRSS2_PHY_111_DATA
+			DDRSS2_PHY_112_DATA
+			DDRSS2_PHY_113_DATA
+			DDRSS2_PHY_114_DATA
+			DDRSS2_PHY_115_DATA
+			DDRSS2_PHY_116_DATA
+			DDRSS2_PHY_117_DATA
+			DDRSS2_PHY_118_DATA
+			DDRSS2_PHY_119_DATA
+			DDRSS2_PHY_120_DATA
+			DDRSS2_PHY_121_DATA
+			DDRSS2_PHY_122_DATA
+			DDRSS2_PHY_123_DATA
+			DDRSS2_PHY_124_DATA
+			DDRSS2_PHY_125_DATA
+			DDRSS2_PHY_126_DATA
+			DDRSS2_PHY_127_DATA
+			DDRSS2_PHY_128_DATA
+			DDRSS2_PHY_129_DATA
+			DDRSS2_PHY_130_DATA
+			DDRSS2_PHY_131_DATA
+			DDRSS2_PHY_132_DATA
+			DDRSS2_PHY_133_DATA
+			DDRSS2_PHY_134_DATA
+			DDRSS2_PHY_135_DATA
+			DDRSS2_PHY_136_DATA
+			DDRSS2_PHY_137_DATA
+			DDRSS2_PHY_138_DATA
+			DDRSS2_PHY_139_DATA
+			DDRSS2_PHY_140_DATA
+			DDRSS2_PHY_141_DATA
+			DDRSS2_PHY_142_DATA
+			DDRSS2_PHY_143_DATA
+			DDRSS2_PHY_144_DATA
+			DDRSS2_PHY_145_DATA
+			DDRSS2_PHY_146_DATA
+			DDRSS2_PHY_147_DATA
+			DDRSS2_PHY_148_DATA
+			DDRSS2_PHY_149_DATA
+			DDRSS2_PHY_150_DATA
+			DDRSS2_PHY_151_DATA
+			DDRSS2_PHY_152_DATA
+			DDRSS2_PHY_153_DATA
+			DDRSS2_PHY_154_DATA
+			DDRSS2_PHY_155_DATA
+			DDRSS2_PHY_156_DATA
+			DDRSS2_PHY_157_DATA
+			DDRSS2_PHY_158_DATA
+			DDRSS2_PHY_159_DATA
+			DDRSS2_PHY_160_DATA
+			DDRSS2_PHY_161_DATA
+			DDRSS2_PHY_162_DATA
+			DDRSS2_PHY_163_DATA
+			DDRSS2_PHY_164_DATA
+			DDRSS2_PHY_165_DATA
+			DDRSS2_PHY_166_DATA
+			DDRSS2_PHY_167_DATA
+			DDRSS2_PHY_168_DATA
+			DDRSS2_PHY_169_DATA
+			DDRSS2_PHY_170_DATA
+			DDRSS2_PHY_171_DATA
+			DDRSS2_PHY_172_DATA
+			DDRSS2_PHY_173_DATA
+			DDRSS2_PHY_174_DATA
+			DDRSS2_PHY_175_DATA
+			DDRSS2_PHY_176_DATA
+			DDRSS2_PHY_177_DATA
+			DDRSS2_PHY_178_DATA
+			DDRSS2_PHY_179_DATA
+			DDRSS2_PHY_180_DATA
+			DDRSS2_PHY_181_DATA
+			DDRSS2_PHY_182_DATA
+			DDRSS2_PHY_183_DATA
+			DDRSS2_PHY_184_DATA
+			DDRSS2_PHY_185_DATA
+			DDRSS2_PHY_186_DATA
+			DDRSS2_PHY_187_DATA
+			DDRSS2_PHY_188_DATA
+			DDRSS2_PHY_189_DATA
+			DDRSS2_PHY_190_DATA
+			DDRSS2_PHY_191_DATA
+			DDRSS2_PHY_192_DATA
+			DDRSS2_PHY_193_DATA
+			DDRSS2_PHY_194_DATA
+			DDRSS2_PHY_195_DATA
+			DDRSS2_PHY_196_DATA
+			DDRSS2_PHY_197_DATA
+			DDRSS2_PHY_198_DATA
+			DDRSS2_PHY_199_DATA
+			DDRSS2_PHY_200_DATA
+			DDRSS2_PHY_201_DATA
+			DDRSS2_PHY_202_DATA
+			DDRSS2_PHY_203_DATA
+			DDRSS2_PHY_204_DATA
+			DDRSS2_PHY_205_DATA
+			DDRSS2_PHY_206_DATA
+			DDRSS2_PHY_207_DATA
+			DDRSS2_PHY_208_DATA
+			DDRSS2_PHY_209_DATA
+			DDRSS2_PHY_210_DATA
+			DDRSS2_PHY_211_DATA
+			DDRSS2_PHY_212_DATA
+			DDRSS2_PHY_213_DATA
+			DDRSS2_PHY_214_DATA
+			DDRSS2_PHY_215_DATA
+			DDRSS2_PHY_216_DATA
+			DDRSS2_PHY_217_DATA
+			DDRSS2_PHY_218_DATA
+			DDRSS2_PHY_219_DATA
+			DDRSS2_PHY_220_DATA
+			DDRSS2_PHY_221_DATA
+			DDRSS2_PHY_222_DATA
+			DDRSS2_PHY_223_DATA
+			DDRSS2_PHY_224_DATA
+			DDRSS2_PHY_225_DATA
+			DDRSS2_PHY_226_DATA
+			DDRSS2_PHY_227_DATA
+			DDRSS2_PHY_228_DATA
+			DDRSS2_PHY_229_DATA
+			DDRSS2_PHY_230_DATA
+			DDRSS2_PHY_231_DATA
+			DDRSS2_PHY_232_DATA
+			DDRSS2_PHY_233_DATA
+			DDRSS2_PHY_234_DATA
+			DDRSS2_PHY_235_DATA
+			DDRSS2_PHY_236_DATA
+			DDRSS2_PHY_237_DATA
+			DDRSS2_PHY_238_DATA
+			DDRSS2_PHY_239_DATA
+			DDRSS2_PHY_240_DATA
+			DDRSS2_PHY_241_DATA
+			DDRSS2_PHY_242_DATA
+			DDRSS2_PHY_243_DATA
+			DDRSS2_PHY_244_DATA
+			DDRSS2_PHY_245_DATA
+			DDRSS2_PHY_246_DATA
+			DDRSS2_PHY_247_DATA
+			DDRSS2_PHY_248_DATA
+			DDRSS2_PHY_249_DATA
+			DDRSS2_PHY_250_DATA
+			DDRSS2_PHY_251_DATA
+			DDRSS2_PHY_252_DATA
+			DDRSS2_PHY_253_DATA
+			DDRSS2_PHY_254_DATA
+			DDRSS2_PHY_255_DATA
+			DDRSS2_PHY_256_DATA
+			DDRSS2_PHY_257_DATA
+			DDRSS2_PHY_258_DATA
+			DDRSS2_PHY_259_DATA
+			DDRSS2_PHY_260_DATA
+			DDRSS2_PHY_261_DATA
+			DDRSS2_PHY_262_DATA
+			DDRSS2_PHY_263_DATA
+			DDRSS2_PHY_264_DATA
+			DDRSS2_PHY_265_DATA
+			DDRSS2_PHY_266_DATA
+			DDRSS2_PHY_267_DATA
+			DDRSS2_PHY_268_DATA
+			DDRSS2_PHY_269_DATA
+			DDRSS2_PHY_270_DATA
+			DDRSS2_PHY_271_DATA
+			DDRSS2_PHY_272_DATA
+			DDRSS2_PHY_273_DATA
+			DDRSS2_PHY_274_DATA
+			DDRSS2_PHY_275_DATA
+			DDRSS2_PHY_276_DATA
+			DDRSS2_PHY_277_DATA
+			DDRSS2_PHY_278_DATA
+			DDRSS2_PHY_279_DATA
+			DDRSS2_PHY_280_DATA
+			DDRSS2_PHY_281_DATA
+			DDRSS2_PHY_282_DATA
+			DDRSS2_PHY_283_DATA
+			DDRSS2_PHY_284_DATA
+			DDRSS2_PHY_285_DATA
+			DDRSS2_PHY_286_DATA
+			DDRSS2_PHY_287_DATA
+			DDRSS2_PHY_288_DATA
+			DDRSS2_PHY_289_DATA
+			DDRSS2_PHY_290_DATA
+			DDRSS2_PHY_291_DATA
+			DDRSS2_PHY_292_DATA
+			DDRSS2_PHY_293_DATA
+			DDRSS2_PHY_294_DATA
+			DDRSS2_PHY_295_DATA
+			DDRSS2_PHY_296_DATA
+			DDRSS2_PHY_297_DATA
+			DDRSS2_PHY_298_DATA
+			DDRSS2_PHY_299_DATA
+			DDRSS2_PHY_300_DATA
+			DDRSS2_PHY_301_DATA
+			DDRSS2_PHY_302_DATA
+			DDRSS2_PHY_303_DATA
+			DDRSS2_PHY_304_DATA
+			DDRSS2_PHY_305_DATA
+			DDRSS2_PHY_306_DATA
+			DDRSS2_PHY_307_DATA
+			DDRSS2_PHY_308_DATA
+			DDRSS2_PHY_309_DATA
+			DDRSS2_PHY_310_DATA
+			DDRSS2_PHY_311_DATA
+			DDRSS2_PHY_312_DATA
+			DDRSS2_PHY_313_DATA
+			DDRSS2_PHY_314_DATA
+			DDRSS2_PHY_315_DATA
+			DDRSS2_PHY_316_DATA
+			DDRSS2_PHY_317_DATA
+			DDRSS2_PHY_318_DATA
+			DDRSS2_PHY_319_DATA
+			DDRSS2_PHY_320_DATA
+			DDRSS2_PHY_321_DATA
+			DDRSS2_PHY_322_DATA
+			DDRSS2_PHY_323_DATA
+			DDRSS2_PHY_324_DATA
+			DDRSS2_PHY_325_DATA
+			DDRSS2_PHY_326_DATA
+			DDRSS2_PHY_327_DATA
+			DDRSS2_PHY_328_DATA
+			DDRSS2_PHY_329_DATA
+			DDRSS2_PHY_330_DATA
+			DDRSS2_PHY_331_DATA
+			DDRSS2_PHY_332_DATA
+			DDRSS2_PHY_333_DATA
+			DDRSS2_PHY_334_DATA
+			DDRSS2_PHY_335_DATA
+			DDRSS2_PHY_336_DATA
+			DDRSS2_PHY_337_DATA
+			DDRSS2_PHY_338_DATA
+			DDRSS2_PHY_339_DATA
+			DDRSS2_PHY_340_DATA
+			DDRSS2_PHY_341_DATA
+			DDRSS2_PHY_342_DATA
+			DDRSS2_PHY_343_DATA
+			DDRSS2_PHY_344_DATA
+			DDRSS2_PHY_345_DATA
+			DDRSS2_PHY_346_DATA
+			DDRSS2_PHY_347_DATA
+			DDRSS2_PHY_348_DATA
+			DDRSS2_PHY_349_DATA
+			DDRSS2_PHY_350_DATA
+			DDRSS2_PHY_351_DATA
+			DDRSS2_PHY_352_DATA
+			DDRSS2_PHY_353_DATA
+			DDRSS2_PHY_354_DATA
+			DDRSS2_PHY_355_DATA
+			DDRSS2_PHY_356_DATA
+			DDRSS2_PHY_357_DATA
+			DDRSS2_PHY_358_DATA
+			DDRSS2_PHY_359_DATA
+			DDRSS2_PHY_360_DATA
+			DDRSS2_PHY_361_DATA
+			DDRSS2_PHY_362_DATA
+			DDRSS2_PHY_363_DATA
+			DDRSS2_PHY_364_DATA
+			DDRSS2_PHY_365_DATA
+			DDRSS2_PHY_366_DATA
+			DDRSS2_PHY_367_DATA
+			DDRSS2_PHY_368_DATA
+			DDRSS2_PHY_369_DATA
+			DDRSS2_PHY_370_DATA
+			DDRSS2_PHY_371_DATA
+			DDRSS2_PHY_372_DATA
+			DDRSS2_PHY_373_DATA
+			DDRSS2_PHY_374_DATA
+			DDRSS2_PHY_375_DATA
+			DDRSS2_PHY_376_DATA
+			DDRSS2_PHY_377_DATA
+			DDRSS2_PHY_378_DATA
+			DDRSS2_PHY_379_DATA
+			DDRSS2_PHY_380_DATA
+			DDRSS2_PHY_381_DATA
+			DDRSS2_PHY_382_DATA
+			DDRSS2_PHY_383_DATA
+			DDRSS2_PHY_384_DATA
+			DDRSS2_PHY_385_DATA
+			DDRSS2_PHY_386_DATA
+			DDRSS2_PHY_387_DATA
+			DDRSS2_PHY_388_DATA
+			DDRSS2_PHY_389_DATA
+			DDRSS2_PHY_390_DATA
+			DDRSS2_PHY_391_DATA
+			DDRSS2_PHY_392_DATA
+			DDRSS2_PHY_393_DATA
+			DDRSS2_PHY_394_DATA
+			DDRSS2_PHY_395_DATA
+			DDRSS2_PHY_396_DATA
+			DDRSS2_PHY_397_DATA
+			DDRSS2_PHY_398_DATA
+			DDRSS2_PHY_399_DATA
+			DDRSS2_PHY_400_DATA
+			DDRSS2_PHY_401_DATA
+			DDRSS2_PHY_402_DATA
+			DDRSS2_PHY_403_DATA
+			DDRSS2_PHY_404_DATA
+			DDRSS2_PHY_405_DATA
+			DDRSS2_PHY_406_DATA
+			DDRSS2_PHY_407_DATA
+			DDRSS2_PHY_408_DATA
+			DDRSS2_PHY_409_DATA
+			DDRSS2_PHY_410_DATA
+			DDRSS2_PHY_411_DATA
+			DDRSS2_PHY_412_DATA
+			DDRSS2_PHY_413_DATA
+			DDRSS2_PHY_414_DATA
+			DDRSS2_PHY_415_DATA
+			DDRSS2_PHY_416_DATA
+			DDRSS2_PHY_417_DATA
+			DDRSS2_PHY_418_DATA
+			DDRSS2_PHY_419_DATA
+			DDRSS2_PHY_420_DATA
+			DDRSS2_PHY_421_DATA
+			DDRSS2_PHY_422_DATA
+			DDRSS2_PHY_423_DATA
+			DDRSS2_PHY_424_DATA
+			DDRSS2_PHY_425_DATA
+			DDRSS2_PHY_426_DATA
+			DDRSS2_PHY_427_DATA
+			DDRSS2_PHY_428_DATA
+			DDRSS2_PHY_429_DATA
+			DDRSS2_PHY_430_DATA
+			DDRSS2_PHY_431_DATA
+			DDRSS2_PHY_432_DATA
+			DDRSS2_PHY_433_DATA
+			DDRSS2_PHY_434_DATA
+			DDRSS2_PHY_435_DATA
+			DDRSS2_PHY_436_DATA
+			DDRSS2_PHY_437_DATA
+			DDRSS2_PHY_438_DATA
+			DDRSS2_PHY_439_DATA
+			DDRSS2_PHY_440_DATA
+			DDRSS2_PHY_441_DATA
+			DDRSS2_PHY_442_DATA
+			DDRSS2_PHY_443_DATA
+			DDRSS2_PHY_444_DATA
+			DDRSS2_PHY_445_DATA
+			DDRSS2_PHY_446_DATA
+			DDRSS2_PHY_447_DATA
+			DDRSS2_PHY_448_DATA
+			DDRSS2_PHY_449_DATA
+			DDRSS2_PHY_450_DATA
+			DDRSS2_PHY_451_DATA
+			DDRSS2_PHY_452_DATA
+			DDRSS2_PHY_453_DATA
+			DDRSS2_PHY_454_DATA
+			DDRSS2_PHY_455_DATA
+			DDRSS2_PHY_456_DATA
+			DDRSS2_PHY_457_DATA
+			DDRSS2_PHY_458_DATA
+			DDRSS2_PHY_459_DATA
+			DDRSS2_PHY_460_DATA
+			DDRSS2_PHY_461_DATA
+			DDRSS2_PHY_462_DATA
+			DDRSS2_PHY_463_DATA
+			DDRSS2_PHY_464_DATA
+			DDRSS2_PHY_465_DATA
+			DDRSS2_PHY_466_DATA
+			DDRSS2_PHY_467_DATA
+			DDRSS2_PHY_468_DATA
+			DDRSS2_PHY_469_DATA
+			DDRSS2_PHY_470_DATA
+			DDRSS2_PHY_471_DATA
+			DDRSS2_PHY_472_DATA
+			DDRSS2_PHY_473_DATA
+			DDRSS2_PHY_474_DATA
+			DDRSS2_PHY_475_DATA
+			DDRSS2_PHY_476_DATA
+			DDRSS2_PHY_477_DATA
+			DDRSS2_PHY_478_DATA
+			DDRSS2_PHY_479_DATA
+			DDRSS2_PHY_480_DATA
+			DDRSS2_PHY_481_DATA
+			DDRSS2_PHY_482_DATA
+			DDRSS2_PHY_483_DATA
+			DDRSS2_PHY_484_DATA
+			DDRSS2_PHY_485_DATA
+			DDRSS2_PHY_486_DATA
+			DDRSS2_PHY_487_DATA
+			DDRSS2_PHY_488_DATA
+			DDRSS2_PHY_489_DATA
+			DDRSS2_PHY_490_DATA
+			DDRSS2_PHY_491_DATA
+			DDRSS2_PHY_492_DATA
+			DDRSS2_PHY_493_DATA
+			DDRSS2_PHY_494_DATA
+			DDRSS2_PHY_495_DATA
+			DDRSS2_PHY_496_DATA
+			DDRSS2_PHY_497_DATA
+			DDRSS2_PHY_498_DATA
+			DDRSS2_PHY_499_DATA
+			DDRSS2_PHY_500_DATA
+			DDRSS2_PHY_501_DATA
+			DDRSS2_PHY_502_DATA
+			DDRSS2_PHY_503_DATA
+			DDRSS2_PHY_504_DATA
+			DDRSS2_PHY_505_DATA
+			DDRSS2_PHY_506_DATA
+			DDRSS2_PHY_507_DATA
+			DDRSS2_PHY_508_DATA
+			DDRSS2_PHY_509_DATA
+			DDRSS2_PHY_510_DATA
+			DDRSS2_PHY_511_DATA
+			DDRSS2_PHY_512_DATA
+			DDRSS2_PHY_513_DATA
+			DDRSS2_PHY_514_DATA
+			DDRSS2_PHY_515_DATA
+			DDRSS2_PHY_516_DATA
+			DDRSS2_PHY_517_DATA
+			DDRSS2_PHY_518_DATA
+			DDRSS2_PHY_519_DATA
+			DDRSS2_PHY_520_DATA
+			DDRSS2_PHY_521_DATA
+			DDRSS2_PHY_522_DATA
+			DDRSS2_PHY_523_DATA
+			DDRSS2_PHY_524_DATA
+			DDRSS2_PHY_525_DATA
+			DDRSS2_PHY_526_DATA
+			DDRSS2_PHY_527_DATA
+			DDRSS2_PHY_528_DATA
+			DDRSS2_PHY_529_DATA
+			DDRSS2_PHY_530_DATA
+			DDRSS2_PHY_531_DATA
+			DDRSS2_PHY_532_DATA
+			DDRSS2_PHY_533_DATA
+			DDRSS2_PHY_534_DATA
+			DDRSS2_PHY_535_DATA
+			DDRSS2_PHY_536_DATA
+			DDRSS2_PHY_537_DATA
+			DDRSS2_PHY_538_DATA
+			DDRSS2_PHY_539_DATA
+			DDRSS2_PHY_540_DATA
+			DDRSS2_PHY_541_DATA
+			DDRSS2_PHY_542_DATA
+			DDRSS2_PHY_543_DATA
+			DDRSS2_PHY_544_DATA
+			DDRSS2_PHY_545_DATA
+			DDRSS2_PHY_546_DATA
+			DDRSS2_PHY_547_DATA
+			DDRSS2_PHY_548_DATA
+			DDRSS2_PHY_549_DATA
+			DDRSS2_PHY_550_DATA
+			DDRSS2_PHY_551_DATA
+			DDRSS2_PHY_552_DATA
+			DDRSS2_PHY_553_DATA
+			DDRSS2_PHY_554_DATA
+			DDRSS2_PHY_555_DATA
+			DDRSS2_PHY_556_DATA
+			DDRSS2_PHY_557_DATA
+			DDRSS2_PHY_558_DATA
+			DDRSS2_PHY_559_DATA
+			DDRSS2_PHY_560_DATA
+			DDRSS2_PHY_561_DATA
+			DDRSS2_PHY_562_DATA
+			DDRSS2_PHY_563_DATA
+			DDRSS2_PHY_564_DATA
+			DDRSS2_PHY_565_DATA
+			DDRSS2_PHY_566_DATA
+			DDRSS2_PHY_567_DATA
+			DDRSS2_PHY_568_DATA
+			DDRSS2_PHY_569_DATA
+			DDRSS2_PHY_570_DATA
+			DDRSS2_PHY_571_DATA
+			DDRSS2_PHY_572_DATA
+			DDRSS2_PHY_573_DATA
+			DDRSS2_PHY_574_DATA
+			DDRSS2_PHY_575_DATA
+			DDRSS2_PHY_576_DATA
+			DDRSS2_PHY_577_DATA
+			DDRSS2_PHY_578_DATA
+			DDRSS2_PHY_579_DATA
+			DDRSS2_PHY_580_DATA
+			DDRSS2_PHY_581_DATA
+			DDRSS2_PHY_582_DATA
+			DDRSS2_PHY_583_DATA
+			DDRSS2_PHY_584_DATA
+			DDRSS2_PHY_585_DATA
+			DDRSS2_PHY_586_DATA
+			DDRSS2_PHY_587_DATA
+			DDRSS2_PHY_588_DATA
+			DDRSS2_PHY_589_DATA
+			DDRSS2_PHY_590_DATA
+			DDRSS2_PHY_591_DATA
+			DDRSS2_PHY_592_DATA
+			DDRSS2_PHY_593_DATA
+			DDRSS2_PHY_594_DATA
+			DDRSS2_PHY_595_DATA
+			DDRSS2_PHY_596_DATA
+			DDRSS2_PHY_597_DATA
+			DDRSS2_PHY_598_DATA
+			DDRSS2_PHY_599_DATA
+			DDRSS2_PHY_600_DATA
+			DDRSS2_PHY_601_DATA
+			DDRSS2_PHY_602_DATA
+			DDRSS2_PHY_603_DATA
+			DDRSS2_PHY_604_DATA
+			DDRSS2_PHY_605_DATA
+			DDRSS2_PHY_606_DATA
+			DDRSS2_PHY_607_DATA
+			DDRSS2_PHY_608_DATA
+			DDRSS2_PHY_609_DATA
+			DDRSS2_PHY_610_DATA
+			DDRSS2_PHY_611_DATA
+			DDRSS2_PHY_612_DATA
+			DDRSS2_PHY_613_DATA
+			DDRSS2_PHY_614_DATA
+			DDRSS2_PHY_615_DATA
+			DDRSS2_PHY_616_DATA
+			DDRSS2_PHY_617_DATA
+			DDRSS2_PHY_618_DATA
+			DDRSS2_PHY_619_DATA
+			DDRSS2_PHY_620_DATA
+			DDRSS2_PHY_621_DATA
+			DDRSS2_PHY_622_DATA
+			DDRSS2_PHY_623_DATA
+			DDRSS2_PHY_624_DATA
+			DDRSS2_PHY_625_DATA
+			DDRSS2_PHY_626_DATA
+			DDRSS2_PHY_627_DATA
+			DDRSS2_PHY_628_DATA
+			DDRSS2_PHY_629_DATA
+			DDRSS2_PHY_630_DATA
+			DDRSS2_PHY_631_DATA
+			DDRSS2_PHY_632_DATA
+			DDRSS2_PHY_633_DATA
+			DDRSS2_PHY_634_DATA
+			DDRSS2_PHY_635_DATA
+			DDRSS2_PHY_636_DATA
+			DDRSS2_PHY_637_DATA
+			DDRSS2_PHY_638_DATA
+			DDRSS2_PHY_639_DATA
+			DDRSS2_PHY_640_DATA
+			DDRSS2_PHY_641_DATA
+			DDRSS2_PHY_642_DATA
+			DDRSS2_PHY_643_DATA
+			DDRSS2_PHY_644_DATA
+			DDRSS2_PHY_645_DATA
+			DDRSS2_PHY_646_DATA
+			DDRSS2_PHY_647_DATA
+			DDRSS2_PHY_648_DATA
+			DDRSS2_PHY_649_DATA
+			DDRSS2_PHY_650_DATA
+			DDRSS2_PHY_651_DATA
+			DDRSS2_PHY_652_DATA
+			DDRSS2_PHY_653_DATA
+			DDRSS2_PHY_654_DATA
+			DDRSS2_PHY_655_DATA
+			DDRSS2_PHY_656_DATA
+			DDRSS2_PHY_657_DATA
+			DDRSS2_PHY_658_DATA
+			DDRSS2_PHY_659_DATA
+			DDRSS2_PHY_660_DATA
+			DDRSS2_PHY_661_DATA
+			DDRSS2_PHY_662_DATA
+			DDRSS2_PHY_663_DATA
+			DDRSS2_PHY_664_DATA
+			DDRSS2_PHY_665_DATA
+			DDRSS2_PHY_666_DATA
+			DDRSS2_PHY_667_DATA
+			DDRSS2_PHY_668_DATA
+			DDRSS2_PHY_669_DATA
+			DDRSS2_PHY_670_DATA
+			DDRSS2_PHY_671_DATA
+			DDRSS2_PHY_672_DATA
+			DDRSS2_PHY_673_DATA
+			DDRSS2_PHY_674_DATA
+			DDRSS2_PHY_675_DATA
+			DDRSS2_PHY_676_DATA
+			DDRSS2_PHY_677_DATA
+			DDRSS2_PHY_678_DATA
+			DDRSS2_PHY_679_DATA
+			DDRSS2_PHY_680_DATA
+			DDRSS2_PHY_681_DATA
+			DDRSS2_PHY_682_DATA
+			DDRSS2_PHY_683_DATA
+			DDRSS2_PHY_684_DATA
+			DDRSS2_PHY_685_DATA
+			DDRSS2_PHY_686_DATA
+			DDRSS2_PHY_687_DATA
+			DDRSS2_PHY_688_DATA
+			DDRSS2_PHY_689_DATA
+			DDRSS2_PHY_690_DATA
+			DDRSS2_PHY_691_DATA
+			DDRSS2_PHY_692_DATA
+			DDRSS2_PHY_693_DATA
+			DDRSS2_PHY_694_DATA
+			DDRSS2_PHY_695_DATA
+			DDRSS2_PHY_696_DATA
+			DDRSS2_PHY_697_DATA
+			DDRSS2_PHY_698_DATA
+			DDRSS2_PHY_699_DATA
+			DDRSS2_PHY_700_DATA
+			DDRSS2_PHY_701_DATA
+			DDRSS2_PHY_702_DATA
+			DDRSS2_PHY_703_DATA
+			DDRSS2_PHY_704_DATA
+			DDRSS2_PHY_705_DATA
+			DDRSS2_PHY_706_DATA
+			DDRSS2_PHY_707_DATA
+			DDRSS2_PHY_708_DATA
+			DDRSS2_PHY_709_DATA
+			DDRSS2_PHY_710_DATA
+			DDRSS2_PHY_711_DATA
+			DDRSS2_PHY_712_DATA
+			DDRSS2_PHY_713_DATA
+			DDRSS2_PHY_714_DATA
+			DDRSS2_PHY_715_DATA
+			DDRSS2_PHY_716_DATA
+			DDRSS2_PHY_717_DATA
+			DDRSS2_PHY_718_DATA
+			DDRSS2_PHY_719_DATA
+			DDRSS2_PHY_720_DATA
+			DDRSS2_PHY_721_DATA
+			DDRSS2_PHY_722_DATA
+			DDRSS2_PHY_723_DATA
+			DDRSS2_PHY_724_DATA
+			DDRSS2_PHY_725_DATA
+			DDRSS2_PHY_726_DATA
+			DDRSS2_PHY_727_DATA
+			DDRSS2_PHY_728_DATA
+			DDRSS2_PHY_729_DATA
+			DDRSS2_PHY_730_DATA
+			DDRSS2_PHY_731_DATA
+			DDRSS2_PHY_732_DATA
+			DDRSS2_PHY_733_DATA
+			DDRSS2_PHY_734_DATA
+			DDRSS2_PHY_735_DATA
+			DDRSS2_PHY_736_DATA
+			DDRSS2_PHY_737_DATA
+			DDRSS2_PHY_738_DATA
+			DDRSS2_PHY_739_DATA
+			DDRSS2_PHY_740_DATA
+			DDRSS2_PHY_741_DATA
+			DDRSS2_PHY_742_DATA
+			DDRSS2_PHY_743_DATA
+			DDRSS2_PHY_744_DATA
+			DDRSS2_PHY_745_DATA
+			DDRSS2_PHY_746_DATA
+			DDRSS2_PHY_747_DATA
+			DDRSS2_PHY_748_DATA
+			DDRSS2_PHY_749_DATA
+			DDRSS2_PHY_750_DATA
+			DDRSS2_PHY_751_DATA
+			DDRSS2_PHY_752_DATA
+			DDRSS2_PHY_753_DATA
+			DDRSS2_PHY_754_DATA
+			DDRSS2_PHY_755_DATA
+			DDRSS2_PHY_756_DATA
+			DDRSS2_PHY_757_DATA
+			DDRSS2_PHY_758_DATA
+			DDRSS2_PHY_759_DATA
+			DDRSS2_PHY_760_DATA
+			DDRSS2_PHY_761_DATA
+			DDRSS2_PHY_762_DATA
+			DDRSS2_PHY_763_DATA
+			DDRSS2_PHY_764_DATA
+			DDRSS2_PHY_765_DATA
+			DDRSS2_PHY_766_DATA
+			DDRSS2_PHY_767_DATA
+			DDRSS2_PHY_768_DATA
+			DDRSS2_PHY_769_DATA
+			DDRSS2_PHY_770_DATA
+			DDRSS2_PHY_771_DATA
+			DDRSS2_PHY_772_DATA
+			DDRSS2_PHY_773_DATA
+			DDRSS2_PHY_774_DATA
+			DDRSS2_PHY_775_DATA
+			DDRSS2_PHY_776_DATA
+			DDRSS2_PHY_777_DATA
+			DDRSS2_PHY_778_DATA
+			DDRSS2_PHY_779_DATA
+			DDRSS2_PHY_780_DATA
+			DDRSS2_PHY_781_DATA
+			DDRSS2_PHY_782_DATA
+			DDRSS2_PHY_783_DATA
+			DDRSS2_PHY_784_DATA
+			DDRSS2_PHY_785_DATA
+			DDRSS2_PHY_786_DATA
+			DDRSS2_PHY_787_DATA
+			DDRSS2_PHY_788_DATA
+			DDRSS2_PHY_789_DATA
+			DDRSS2_PHY_790_DATA
+			DDRSS2_PHY_791_DATA
+			DDRSS2_PHY_792_DATA
+			DDRSS2_PHY_793_DATA
+			DDRSS2_PHY_794_DATA
+			DDRSS2_PHY_795_DATA
+			DDRSS2_PHY_796_DATA
+			DDRSS2_PHY_797_DATA
+			DDRSS2_PHY_798_DATA
+			DDRSS2_PHY_799_DATA
+			DDRSS2_PHY_800_DATA
+			DDRSS2_PHY_801_DATA
+			DDRSS2_PHY_802_DATA
+			DDRSS2_PHY_803_DATA
+			DDRSS2_PHY_804_DATA
+			DDRSS2_PHY_805_DATA
+			DDRSS2_PHY_806_DATA
+			DDRSS2_PHY_807_DATA
+			DDRSS2_PHY_808_DATA
+			DDRSS2_PHY_809_DATA
+			DDRSS2_PHY_810_DATA
+			DDRSS2_PHY_811_DATA
+			DDRSS2_PHY_812_DATA
+			DDRSS2_PHY_813_DATA
+			DDRSS2_PHY_814_DATA
+			DDRSS2_PHY_815_DATA
+			DDRSS2_PHY_816_DATA
+			DDRSS2_PHY_817_DATA
+			DDRSS2_PHY_818_DATA
+			DDRSS2_PHY_819_DATA
+			DDRSS2_PHY_820_DATA
+			DDRSS2_PHY_821_DATA
+			DDRSS2_PHY_822_DATA
+			DDRSS2_PHY_823_DATA
+			DDRSS2_PHY_824_DATA
+			DDRSS2_PHY_825_DATA
+			DDRSS2_PHY_826_DATA
+			DDRSS2_PHY_827_DATA
+			DDRSS2_PHY_828_DATA
+			DDRSS2_PHY_829_DATA
+			DDRSS2_PHY_830_DATA
+			DDRSS2_PHY_831_DATA
+			DDRSS2_PHY_832_DATA
+			DDRSS2_PHY_833_DATA
+			DDRSS2_PHY_834_DATA
+			DDRSS2_PHY_835_DATA
+			DDRSS2_PHY_836_DATA
+			DDRSS2_PHY_837_DATA
+			DDRSS2_PHY_838_DATA
+			DDRSS2_PHY_839_DATA
+			DDRSS2_PHY_840_DATA
+			DDRSS2_PHY_841_DATA
+			DDRSS2_PHY_842_DATA
+			DDRSS2_PHY_843_DATA
+			DDRSS2_PHY_844_DATA
+			DDRSS2_PHY_845_DATA
+			DDRSS2_PHY_846_DATA
+			DDRSS2_PHY_847_DATA
+			DDRSS2_PHY_848_DATA
+			DDRSS2_PHY_849_DATA
+			DDRSS2_PHY_850_DATA
+			DDRSS2_PHY_851_DATA
+			DDRSS2_PHY_852_DATA
+			DDRSS2_PHY_853_DATA
+			DDRSS2_PHY_854_DATA
+			DDRSS2_PHY_855_DATA
+			DDRSS2_PHY_856_DATA
+			DDRSS2_PHY_857_DATA
+			DDRSS2_PHY_858_DATA
+			DDRSS2_PHY_859_DATA
+			DDRSS2_PHY_860_DATA
+			DDRSS2_PHY_861_DATA
+			DDRSS2_PHY_862_DATA
+			DDRSS2_PHY_863_DATA
+			DDRSS2_PHY_864_DATA
+			DDRSS2_PHY_865_DATA
+			DDRSS2_PHY_866_DATA
+			DDRSS2_PHY_867_DATA
+			DDRSS2_PHY_868_DATA
+			DDRSS2_PHY_869_DATA
+			DDRSS2_PHY_870_DATA
+			DDRSS2_PHY_871_DATA
+			DDRSS2_PHY_872_DATA
+			DDRSS2_PHY_873_DATA
+			DDRSS2_PHY_874_DATA
+			DDRSS2_PHY_875_DATA
+			DDRSS2_PHY_876_DATA
+			DDRSS2_PHY_877_DATA
+			DDRSS2_PHY_878_DATA
+			DDRSS2_PHY_879_DATA
+			DDRSS2_PHY_880_DATA
+			DDRSS2_PHY_881_DATA
+			DDRSS2_PHY_882_DATA
+			DDRSS2_PHY_883_DATA
+			DDRSS2_PHY_884_DATA
+			DDRSS2_PHY_885_DATA
+			DDRSS2_PHY_886_DATA
+			DDRSS2_PHY_887_DATA
+			DDRSS2_PHY_888_DATA
+			DDRSS2_PHY_889_DATA
+			DDRSS2_PHY_890_DATA
+			DDRSS2_PHY_891_DATA
+			DDRSS2_PHY_892_DATA
+			DDRSS2_PHY_893_DATA
+			DDRSS2_PHY_894_DATA
+			DDRSS2_PHY_895_DATA
+			DDRSS2_PHY_896_DATA
+			DDRSS2_PHY_897_DATA
+			DDRSS2_PHY_898_DATA
+			DDRSS2_PHY_899_DATA
+			DDRSS2_PHY_900_DATA
+			DDRSS2_PHY_901_DATA
+			DDRSS2_PHY_902_DATA
+			DDRSS2_PHY_903_DATA
+			DDRSS2_PHY_904_DATA
+			DDRSS2_PHY_905_DATA
+			DDRSS2_PHY_906_DATA
+			DDRSS2_PHY_907_DATA
+			DDRSS2_PHY_908_DATA
+			DDRSS2_PHY_909_DATA
+			DDRSS2_PHY_910_DATA
+			DDRSS2_PHY_911_DATA
+			DDRSS2_PHY_912_DATA
+			DDRSS2_PHY_913_DATA
+			DDRSS2_PHY_914_DATA
+			DDRSS2_PHY_915_DATA
+			DDRSS2_PHY_916_DATA
+			DDRSS2_PHY_917_DATA
+			DDRSS2_PHY_918_DATA
+			DDRSS2_PHY_919_DATA
+			DDRSS2_PHY_920_DATA
+			DDRSS2_PHY_921_DATA
+			DDRSS2_PHY_922_DATA
+			DDRSS2_PHY_923_DATA
+			DDRSS2_PHY_924_DATA
+			DDRSS2_PHY_925_DATA
+			DDRSS2_PHY_926_DATA
+			DDRSS2_PHY_927_DATA
+			DDRSS2_PHY_928_DATA
+			DDRSS2_PHY_929_DATA
+			DDRSS2_PHY_930_DATA
+			DDRSS2_PHY_931_DATA
+			DDRSS2_PHY_932_DATA
+			DDRSS2_PHY_933_DATA
+			DDRSS2_PHY_934_DATA
+			DDRSS2_PHY_935_DATA
+			DDRSS2_PHY_936_DATA
+			DDRSS2_PHY_937_DATA
+			DDRSS2_PHY_938_DATA
+			DDRSS2_PHY_939_DATA
+			DDRSS2_PHY_940_DATA
+			DDRSS2_PHY_941_DATA
+			DDRSS2_PHY_942_DATA
+			DDRSS2_PHY_943_DATA
+			DDRSS2_PHY_944_DATA
+			DDRSS2_PHY_945_DATA
+			DDRSS2_PHY_946_DATA
+			DDRSS2_PHY_947_DATA
+			DDRSS2_PHY_948_DATA
+			DDRSS2_PHY_949_DATA
+			DDRSS2_PHY_950_DATA
+			DDRSS2_PHY_951_DATA
+			DDRSS2_PHY_952_DATA
+			DDRSS2_PHY_953_DATA
+			DDRSS2_PHY_954_DATA
+			DDRSS2_PHY_955_DATA
+			DDRSS2_PHY_956_DATA
+			DDRSS2_PHY_957_DATA
+			DDRSS2_PHY_958_DATA
+			DDRSS2_PHY_959_DATA
+			DDRSS2_PHY_960_DATA
+			DDRSS2_PHY_961_DATA
+			DDRSS2_PHY_962_DATA
+			DDRSS2_PHY_963_DATA
+			DDRSS2_PHY_964_DATA
+			DDRSS2_PHY_965_DATA
+			DDRSS2_PHY_966_DATA
+			DDRSS2_PHY_967_DATA
+			DDRSS2_PHY_968_DATA
+			DDRSS2_PHY_969_DATA
+			DDRSS2_PHY_970_DATA
+			DDRSS2_PHY_971_DATA
+			DDRSS2_PHY_972_DATA
+			DDRSS2_PHY_973_DATA
+			DDRSS2_PHY_974_DATA
+			DDRSS2_PHY_975_DATA
+			DDRSS2_PHY_976_DATA
+			DDRSS2_PHY_977_DATA
+			DDRSS2_PHY_978_DATA
+			DDRSS2_PHY_979_DATA
+			DDRSS2_PHY_980_DATA
+			DDRSS2_PHY_981_DATA
+			DDRSS2_PHY_982_DATA
+			DDRSS2_PHY_983_DATA
+			DDRSS2_PHY_984_DATA
+			DDRSS2_PHY_985_DATA
+			DDRSS2_PHY_986_DATA
+			DDRSS2_PHY_987_DATA
+			DDRSS2_PHY_988_DATA
+			DDRSS2_PHY_989_DATA
+			DDRSS2_PHY_990_DATA
+			DDRSS2_PHY_991_DATA
+			DDRSS2_PHY_992_DATA
+			DDRSS2_PHY_993_DATA
+			DDRSS2_PHY_994_DATA
+			DDRSS2_PHY_995_DATA
+			DDRSS2_PHY_996_DATA
+			DDRSS2_PHY_997_DATA
+			DDRSS2_PHY_998_DATA
+			DDRSS2_PHY_999_DATA
+			DDRSS2_PHY_1000_DATA
+			DDRSS2_PHY_1001_DATA
+			DDRSS2_PHY_1002_DATA
+			DDRSS2_PHY_1003_DATA
+			DDRSS2_PHY_1004_DATA
+			DDRSS2_PHY_1005_DATA
+			DDRSS2_PHY_1006_DATA
+			DDRSS2_PHY_1007_DATA
+			DDRSS2_PHY_1008_DATA
+			DDRSS2_PHY_1009_DATA
+			DDRSS2_PHY_1010_DATA
+			DDRSS2_PHY_1011_DATA
+			DDRSS2_PHY_1012_DATA
+			DDRSS2_PHY_1013_DATA
+			DDRSS2_PHY_1014_DATA
+			DDRSS2_PHY_1015_DATA
+			DDRSS2_PHY_1016_DATA
+			DDRSS2_PHY_1017_DATA
+			DDRSS2_PHY_1018_DATA
+			DDRSS2_PHY_1019_DATA
+			DDRSS2_PHY_1020_DATA
+			DDRSS2_PHY_1021_DATA
+			DDRSS2_PHY_1022_DATA
+			DDRSS2_PHY_1023_DATA
+			DDRSS2_PHY_1024_DATA
+			DDRSS2_PHY_1025_DATA
+			DDRSS2_PHY_1026_DATA
+			DDRSS2_PHY_1027_DATA
+			DDRSS2_PHY_1028_DATA
+			DDRSS2_PHY_1029_DATA
+			DDRSS2_PHY_1030_DATA
+			DDRSS2_PHY_1031_DATA
+			DDRSS2_PHY_1032_DATA
+			DDRSS2_PHY_1033_DATA
+			DDRSS2_PHY_1034_DATA
+			DDRSS2_PHY_1035_DATA
+			DDRSS2_PHY_1036_DATA
+			DDRSS2_PHY_1037_DATA
+			DDRSS2_PHY_1038_DATA
+			DDRSS2_PHY_1039_DATA
+			DDRSS2_PHY_1040_DATA
+			DDRSS2_PHY_1041_DATA
+			DDRSS2_PHY_1042_DATA
+			DDRSS2_PHY_1043_DATA
+			DDRSS2_PHY_1044_DATA
+			DDRSS2_PHY_1045_DATA
+			DDRSS2_PHY_1046_DATA
+			DDRSS2_PHY_1047_DATA
+			DDRSS2_PHY_1048_DATA
+			DDRSS2_PHY_1049_DATA
+			DDRSS2_PHY_1050_DATA
+			DDRSS2_PHY_1051_DATA
+			DDRSS2_PHY_1052_DATA
+			DDRSS2_PHY_1053_DATA
+			DDRSS2_PHY_1054_DATA
+			DDRSS2_PHY_1055_DATA
+			DDRSS2_PHY_1056_DATA
+			DDRSS2_PHY_1057_DATA
+			DDRSS2_PHY_1058_DATA
+			DDRSS2_PHY_1059_DATA
+			DDRSS2_PHY_1060_DATA
+			DDRSS2_PHY_1061_DATA
+			DDRSS2_PHY_1062_DATA
+			DDRSS2_PHY_1063_DATA
+			DDRSS2_PHY_1064_DATA
+			DDRSS2_PHY_1065_DATA
+			DDRSS2_PHY_1066_DATA
+			DDRSS2_PHY_1067_DATA
+			DDRSS2_PHY_1068_DATA
+			DDRSS2_PHY_1069_DATA
+			DDRSS2_PHY_1070_DATA
+			DDRSS2_PHY_1071_DATA
+			DDRSS2_PHY_1072_DATA
+			DDRSS2_PHY_1073_DATA
+			DDRSS2_PHY_1074_DATA
+			DDRSS2_PHY_1075_DATA
+			DDRSS2_PHY_1076_DATA
+			DDRSS2_PHY_1077_DATA
+			DDRSS2_PHY_1078_DATA
+			DDRSS2_PHY_1079_DATA
+			DDRSS2_PHY_1080_DATA
+			DDRSS2_PHY_1081_DATA
+			DDRSS2_PHY_1082_DATA
+			DDRSS2_PHY_1083_DATA
+			DDRSS2_PHY_1084_DATA
+			DDRSS2_PHY_1085_DATA
+			DDRSS2_PHY_1086_DATA
+			DDRSS2_PHY_1087_DATA
+			DDRSS2_PHY_1088_DATA
+			DDRSS2_PHY_1089_DATA
+			DDRSS2_PHY_1090_DATA
+			DDRSS2_PHY_1091_DATA
+			DDRSS2_PHY_1092_DATA
+			DDRSS2_PHY_1093_DATA
+			DDRSS2_PHY_1094_DATA
+			DDRSS2_PHY_1095_DATA
+			DDRSS2_PHY_1096_DATA
+			DDRSS2_PHY_1097_DATA
+			DDRSS2_PHY_1098_DATA
+			DDRSS2_PHY_1099_DATA
+			DDRSS2_PHY_1100_DATA
+			DDRSS2_PHY_1101_DATA
+			DDRSS2_PHY_1102_DATA
+			DDRSS2_PHY_1103_DATA
+			DDRSS2_PHY_1104_DATA
+			DDRSS2_PHY_1105_DATA
+			DDRSS2_PHY_1106_DATA
+			DDRSS2_PHY_1107_DATA
+			DDRSS2_PHY_1108_DATA
+			DDRSS2_PHY_1109_DATA
+			DDRSS2_PHY_1110_DATA
+			DDRSS2_PHY_1111_DATA
+			DDRSS2_PHY_1112_DATA
+			DDRSS2_PHY_1113_DATA
+			DDRSS2_PHY_1114_DATA
+			DDRSS2_PHY_1115_DATA
+			DDRSS2_PHY_1116_DATA
+			DDRSS2_PHY_1117_DATA
+			DDRSS2_PHY_1118_DATA
+			DDRSS2_PHY_1119_DATA
+			DDRSS2_PHY_1120_DATA
+			DDRSS2_PHY_1121_DATA
+			DDRSS2_PHY_1122_DATA
+			DDRSS2_PHY_1123_DATA
+			DDRSS2_PHY_1124_DATA
+			DDRSS2_PHY_1125_DATA
+			DDRSS2_PHY_1126_DATA
+			DDRSS2_PHY_1127_DATA
+			DDRSS2_PHY_1128_DATA
+			DDRSS2_PHY_1129_DATA
+			DDRSS2_PHY_1130_DATA
+			DDRSS2_PHY_1131_DATA
+			DDRSS2_PHY_1132_DATA
+			DDRSS2_PHY_1133_DATA
+			DDRSS2_PHY_1134_DATA
+			DDRSS2_PHY_1135_DATA
+			DDRSS2_PHY_1136_DATA
+			DDRSS2_PHY_1137_DATA
+			DDRSS2_PHY_1138_DATA
+			DDRSS2_PHY_1139_DATA
+			DDRSS2_PHY_1140_DATA
+			DDRSS2_PHY_1141_DATA
+			DDRSS2_PHY_1142_DATA
+			DDRSS2_PHY_1143_DATA
+			DDRSS2_PHY_1144_DATA
+			DDRSS2_PHY_1145_DATA
+			DDRSS2_PHY_1146_DATA
+			DDRSS2_PHY_1147_DATA
+			DDRSS2_PHY_1148_DATA
+			DDRSS2_PHY_1149_DATA
+			DDRSS2_PHY_1150_DATA
+			DDRSS2_PHY_1151_DATA
+			DDRSS2_PHY_1152_DATA
+			DDRSS2_PHY_1153_DATA
+			DDRSS2_PHY_1154_DATA
+			DDRSS2_PHY_1155_DATA
+			DDRSS2_PHY_1156_DATA
+			DDRSS2_PHY_1157_DATA
+			DDRSS2_PHY_1158_DATA
+			DDRSS2_PHY_1159_DATA
+			DDRSS2_PHY_1160_DATA
+			DDRSS2_PHY_1161_DATA
+			DDRSS2_PHY_1162_DATA
+			DDRSS2_PHY_1163_DATA
+			DDRSS2_PHY_1164_DATA
+			DDRSS2_PHY_1165_DATA
+			DDRSS2_PHY_1166_DATA
+			DDRSS2_PHY_1167_DATA
+			DDRSS2_PHY_1168_DATA
+			DDRSS2_PHY_1169_DATA
+			DDRSS2_PHY_1170_DATA
+			DDRSS2_PHY_1171_DATA
+			DDRSS2_PHY_1172_DATA
+			DDRSS2_PHY_1173_DATA
+			DDRSS2_PHY_1174_DATA
+			DDRSS2_PHY_1175_DATA
+			DDRSS2_PHY_1176_DATA
+			DDRSS2_PHY_1177_DATA
+			DDRSS2_PHY_1178_DATA
+			DDRSS2_PHY_1179_DATA
+			DDRSS2_PHY_1180_DATA
+			DDRSS2_PHY_1181_DATA
+			DDRSS2_PHY_1182_DATA
+			DDRSS2_PHY_1183_DATA
+			DDRSS2_PHY_1184_DATA
+			DDRSS2_PHY_1185_DATA
+			DDRSS2_PHY_1186_DATA
+			DDRSS2_PHY_1187_DATA
+			DDRSS2_PHY_1188_DATA
+			DDRSS2_PHY_1189_DATA
+			DDRSS2_PHY_1190_DATA
+			DDRSS2_PHY_1191_DATA
+			DDRSS2_PHY_1192_DATA
+			DDRSS2_PHY_1193_DATA
+			DDRSS2_PHY_1194_DATA
+			DDRSS2_PHY_1195_DATA
+			DDRSS2_PHY_1196_DATA
+			DDRSS2_PHY_1197_DATA
+			DDRSS2_PHY_1198_DATA
+			DDRSS2_PHY_1199_DATA
+			DDRSS2_PHY_1200_DATA
+			DDRSS2_PHY_1201_DATA
+			DDRSS2_PHY_1202_DATA
+			DDRSS2_PHY_1203_DATA
+			DDRSS2_PHY_1204_DATA
+			DDRSS2_PHY_1205_DATA
+			DDRSS2_PHY_1206_DATA
+			DDRSS2_PHY_1207_DATA
+			DDRSS2_PHY_1208_DATA
+			DDRSS2_PHY_1209_DATA
+			DDRSS2_PHY_1210_DATA
+			DDRSS2_PHY_1211_DATA
+			DDRSS2_PHY_1212_DATA
+			DDRSS2_PHY_1213_DATA
+			DDRSS2_PHY_1214_DATA
+			DDRSS2_PHY_1215_DATA
+			DDRSS2_PHY_1216_DATA
+			DDRSS2_PHY_1217_DATA
+			DDRSS2_PHY_1218_DATA
+			DDRSS2_PHY_1219_DATA
+			DDRSS2_PHY_1220_DATA
+			DDRSS2_PHY_1221_DATA
+			DDRSS2_PHY_1222_DATA
+			DDRSS2_PHY_1223_DATA
+			DDRSS2_PHY_1224_DATA
+			DDRSS2_PHY_1225_DATA
+			DDRSS2_PHY_1226_DATA
+			DDRSS2_PHY_1227_DATA
+			DDRSS2_PHY_1228_DATA
+			DDRSS2_PHY_1229_DATA
+			DDRSS2_PHY_1230_DATA
+			DDRSS2_PHY_1231_DATA
+			DDRSS2_PHY_1232_DATA
+			DDRSS2_PHY_1233_DATA
+			DDRSS2_PHY_1234_DATA
+			DDRSS2_PHY_1235_DATA
+			DDRSS2_PHY_1236_DATA
+			DDRSS2_PHY_1237_DATA
+			DDRSS2_PHY_1238_DATA
+			DDRSS2_PHY_1239_DATA
+			DDRSS2_PHY_1240_DATA
+			DDRSS2_PHY_1241_DATA
+			DDRSS2_PHY_1242_DATA
+			DDRSS2_PHY_1243_DATA
+			DDRSS2_PHY_1244_DATA
+			DDRSS2_PHY_1245_DATA
+			DDRSS2_PHY_1246_DATA
+			DDRSS2_PHY_1247_DATA
+			DDRSS2_PHY_1248_DATA
+			DDRSS2_PHY_1249_DATA
+			DDRSS2_PHY_1250_DATA
+			DDRSS2_PHY_1251_DATA
+			DDRSS2_PHY_1252_DATA
+			DDRSS2_PHY_1253_DATA
+			DDRSS2_PHY_1254_DATA
+			DDRSS2_PHY_1255_DATA
+			DDRSS2_PHY_1256_DATA
+			DDRSS2_PHY_1257_DATA
+			DDRSS2_PHY_1258_DATA
+			DDRSS2_PHY_1259_DATA
+			DDRSS2_PHY_1260_DATA
+			DDRSS2_PHY_1261_DATA
+			DDRSS2_PHY_1262_DATA
+			DDRSS2_PHY_1263_DATA
+			DDRSS2_PHY_1264_DATA
+			DDRSS2_PHY_1265_DATA
+			DDRSS2_PHY_1266_DATA
+			DDRSS2_PHY_1267_DATA
+			DDRSS2_PHY_1268_DATA
+			DDRSS2_PHY_1269_DATA
+			DDRSS2_PHY_1270_DATA
+			DDRSS2_PHY_1271_DATA
+			DDRSS2_PHY_1272_DATA
+			DDRSS2_PHY_1273_DATA
+			DDRSS2_PHY_1274_DATA
+			DDRSS2_PHY_1275_DATA
+			DDRSS2_PHY_1276_DATA
+			DDRSS2_PHY_1277_DATA
+			DDRSS2_PHY_1278_DATA
+			DDRSS2_PHY_1279_DATA
+			DDRSS2_PHY_1280_DATA
+			DDRSS2_PHY_1281_DATA
+			DDRSS2_PHY_1282_DATA
+			DDRSS2_PHY_1283_DATA
+			DDRSS2_PHY_1284_DATA
+			DDRSS2_PHY_1285_DATA
+			DDRSS2_PHY_1286_DATA
+			DDRSS2_PHY_1287_DATA
+			DDRSS2_PHY_1288_DATA
+			DDRSS2_PHY_1289_DATA
+			DDRSS2_PHY_1290_DATA
+			DDRSS2_PHY_1291_DATA
+			DDRSS2_PHY_1292_DATA
+			DDRSS2_PHY_1293_DATA
+			DDRSS2_PHY_1294_DATA
+			DDRSS2_PHY_1295_DATA
+			DDRSS2_PHY_1296_DATA
+			DDRSS2_PHY_1297_DATA
+			DDRSS2_PHY_1298_DATA
+			DDRSS2_PHY_1299_DATA
+			DDRSS2_PHY_1300_DATA
+			DDRSS2_PHY_1301_DATA
+			DDRSS2_PHY_1302_DATA
+			DDRSS2_PHY_1303_DATA
+			DDRSS2_PHY_1304_DATA
+			DDRSS2_PHY_1305_DATA
+			DDRSS2_PHY_1306_DATA
+			DDRSS2_PHY_1307_DATA
+			DDRSS2_PHY_1308_DATA
+			DDRSS2_PHY_1309_DATA
+			DDRSS2_PHY_1310_DATA
+			DDRSS2_PHY_1311_DATA
+			DDRSS2_PHY_1312_DATA
+			DDRSS2_PHY_1313_DATA
+			DDRSS2_PHY_1314_DATA
+			DDRSS2_PHY_1315_DATA
+			DDRSS2_PHY_1316_DATA
+			DDRSS2_PHY_1317_DATA
+			DDRSS2_PHY_1318_DATA
+			DDRSS2_PHY_1319_DATA
+			DDRSS2_PHY_1320_DATA
+			DDRSS2_PHY_1321_DATA
+			DDRSS2_PHY_1322_DATA
+			DDRSS2_PHY_1323_DATA
+			DDRSS2_PHY_1324_DATA
+			DDRSS2_PHY_1325_DATA
+			DDRSS2_PHY_1326_DATA
+			DDRSS2_PHY_1327_DATA
+			DDRSS2_PHY_1328_DATA
+			DDRSS2_PHY_1329_DATA
+			DDRSS2_PHY_1330_DATA
+			DDRSS2_PHY_1331_DATA
+			DDRSS2_PHY_1332_DATA
+			DDRSS2_PHY_1333_DATA
+			DDRSS2_PHY_1334_DATA
+			DDRSS2_PHY_1335_DATA
+			DDRSS2_PHY_1336_DATA
+			DDRSS2_PHY_1337_DATA
+			DDRSS2_PHY_1338_DATA
+			DDRSS2_PHY_1339_DATA
+			DDRSS2_PHY_1340_DATA
+			DDRSS2_PHY_1341_DATA
+			DDRSS2_PHY_1342_DATA
+			DDRSS2_PHY_1343_DATA
+			DDRSS2_PHY_1344_DATA
+			DDRSS2_PHY_1345_DATA
+			DDRSS2_PHY_1346_DATA
+			DDRSS2_PHY_1347_DATA
+			DDRSS2_PHY_1348_DATA
+			DDRSS2_PHY_1349_DATA
+			DDRSS2_PHY_1350_DATA
+			DDRSS2_PHY_1351_DATA
+			DDRSS2_PHY_1352_DATA
+			DDRSS2_PHY_1353_DATA
+			DDRSS2_PHY_1354_DATA
+			DDRSS2_PHY_1355_DATA
+			DDRSS2_PHY_1356_DATA
+			DDRSS2_PHY_1357_DATA
+			DDRSS2_PHY_1358_DATA
+			DDRSS2_PHY_1359_DATA
+			DDRSS2_PHY_1360_DATA
+			DDRSS2_PHY_1361_DATA
+			DDRSS2_PHY_1362_DATA
+			DDRSS2_PHY_1363_DATA
+			DDRSS2_PHY_1364_DATA
+			DDRSS2_PHY_1365_DATA
+			DDRSS2_PHY_1366_DATA
+			DDRSS2_PHY_1367_DATA
+			DDRSS2_PHY_1368_DATA
+			DDRSS2_PHY_1369_DATA
+			DDRSS2_PHY_1370_DATA
+			DDRSS2_PHY_1371_DATA
+			DDRSS2_PHY_1372_DATA
+			DDRSS2_PHY_1373_DATA
+			DDRSS2_PHY_1374_DATA
+			DDRSS2_PHY_1375_DATA
+			DDRSS2_PHY_1376_DATA
+			DDRSS2_PHY_1377_DATA
+			DDRSS2_PHY_1378_DATA
+			DDRSS2_PHY_1379_DATA
+			DDRSS2_PHY_1380_DATA
+			DDRSS2_PHY_1381_DATA
+			DDRSS2_PHY_1382_DATA
+			DDRSS2_PHY_1383_DATA
+			DDRSS2_PHY_1384_DATA
+			DDRSS2_PHY_1385_DATA
+			DDRSS2_PHY_1386_DATA
+			DDRSS2_PHY_1387_DATA
+			DDRSS2_PHY_1388_DATA
+			DDRSS2_PHY_1389_DATA
+			DDRSS2_PHY_1390_DATA
+			DDRSS2_PHY_1391_DATA
+			DDRSS2_PHY_1392_DATA
+			DDRSS2_PHY_1393_DATA
+			DDRSS2_PHY_1394_DATA
+			DDRSS2_PHY_1395_DATA
+			DDRSS2_PHY_1396_DATA
+			DDRSS2_PHY_1397_DATA
+			DDRSS2_PHY_1398_DATA
+			DDRSS2_PHY_1399_DATA
+			DDRSS2_PHY_1400_DATA
+			DDRSS2_PHY_1401_DATA
+			DDRSS2_PHY_1402_DATA
+			DDRSS2_PHY_1403_DATA
+			DDRSS2_PHY_1404_DATA
+			DDRSS2_PHY_1405_DATA
+			DDRSS2_PHY_1406_DATA
+			DDRSS2_PHY_1407_DATA
+			DDRSS2_PHY_1408_DATA
+			DDRSS2_PHY_1409_DATA
+			DDRSS2_PHY_1410_DATA
+			DDRSS2_PHY_1411_DATA
+			DDRSS2_PHY_1412_DATA
+			DDRSS2_PHY_1413_DATA
+			DDRSS2_PHY_1414_DATA
+			DDRSS2_PHY_1415_DATA
+			DDRSS2_PHY_1416_DATA
+			DDRSS2_PHY_1417_DATA
+			DDRSS2_PHY_1418_DATA
+			DDRSS2_PHY_1419_DATA
+			DDRSS2_PHY_1420_DATA
+			DDRSS2_PHY_1421_DATA
+			DDRSS2_PHY_1422_DATA
+		>;
+	};
 
-		memorycontroller3: memorycontroller@29f0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029f0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x29e0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
-				<&k3_pds 139 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <3>;
+	memorycontroller3: memorycontroller@29f0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029f0000 0x0 0x4000>,
+			  <0x0 0x0114000 0x0 0x100>,
+			  <0x0 0x29e0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+			<&k3_pds 139 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
+		ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+		instance = <3>;
 
-			bootph-pre-ram;
+		bootph-pre-ram;
 
-			ti,ctl-data = <
-				DDRSS3_CTL_00_DATA
-				DDRSS3_CTL_01_DATA
-				DDRSS3_CTL_02_DATA
-				DDRSS3_CTL_03_DATA
-				DDRSS3_CTL_04_DATA
-				DDRSS3_CTL_05_DATA
-				DDRSS3_CTL_06_DATA
-				DDRSS3_CTL_07_DATA
-				DDRSS3_CTL_08_DATA
-				DDRSS3_CTL_09_DATA
-				DDRSS3_CTL_10_DATA
-				DDRSS3_CTL_11_DATA
-				DDRSS3_CTL_12_DATA
-				DDRSS3_CTL_13_DATA
-				DDRSS3_CTL_14_DATA
-				DDRSS3_CTL_15_DATA
-				DDRSS3_CTL_16_DATA
-				DDRSS3_CTL_17_DATA
-				DDRSS3_CTL_18_DATA
-				DDRSS3_CTL_19_DATA
-				DDRSS3_CTL_20_DATA
-				DDRSS3_CTL_21_DATA
-				DDRSS3_CTL_22_DATA
-				DDRSS3_CTL_23_DATA
-				DDRSS3_CTL_24_DATA
-				DDRSS3_CTL_25_DATA
-				DDRSS3_CTL_26_DATA
-				DDRSS3_CTL_27_DATA
-				DDRSS3_CTL_28_DATA
-				DDRSS3_CTL_29_DATA
-				DDRSS3_CTL_30_DATA
-				DDRSS3_CTL_31_DATA
-				DDRSS3_CTL_32_DATA
-				DDRSS3_CTL_33_DATA
-				DDRSS3_CTL_34_DATA
-				DDRSS3_CTL_35_DATA
-				DDRSS3_CTL_36_DATA
-				DDRSS3_CTL_37_DATA
-				DDRSS3_CTL_38_DATA
-				DDRSS3_CTL_39_DATA
-				DDRSS3_CTL_40_DATA
-				DDRSS3_CTL_41_DATA
-				DDRSS3_CTL_42_DATA
-				DDRSS3_CTL_43_DATA
-				DDRSS3_CTL_44_DATA
-				DDRSS3_CTL_45_DATA
-				DDRSS3_CTL_46_DATA
-				DDRSS3_CTL_47_DATA
-				DDRSS3_CTL_48_DATA
-				DDRSS3_CTL_49_DATA
-				DDRSS3_CTL_50_DATA
-				DDRSS3_CTL_51_DATA
-				DDRSS3_CTL_52_DATA
-				DDRSS3_CTL_53_DATA
-				DDRSS3_CTL_54_DATA
-				DDRSS3_CTL_55_DATA
-				DDRSS3_CTL_56_DATA
-				DDRSS3_CTL_57_DATA
-				DDRSS3_CTL_58_DATA
-				DDRSS3_CTL_59_DATA
-				DDRSS3_CTL_60_DATA
-				DDRSS3_CTL_61_DATA
-				DDRSS3_CTL_62_DATA
-				DDRSS3_CTL_63_DATA
-				DDRSS3_CTL_64_DATA
-				DDRSS3_CTL_65_DATA
-				DDRSS3_CTL_66_DATA
-				DDRSS3_CTL_67_DATA
-				DDRSS3_CTL_68_DATA
-				DDRSS3_CTL_69_DATA
-				DDRSS3_CTL_70_DATA
-				DDRSS3_CTL_71_DATA
-				DDRSS3_CTL_72_DATA
-				DDRSS3_CTL_73_DATA
-				DDRSS3_CTL_74_DATA
-				DDRSS3_CTL_75_DATA
-				DDRSS3_CTL_76_DATA
-				DDRSS3_CTL_77_DATA
-				DDRSS3_CTL_78_DATA
-				DDRSS3_CTL_79_DATA
-				DDRSS3_CTL_80_DATA
-				DDRSS3_CTL_81_DATA
-				DDRSS3_CTL_82_DATA
-				DDRSS3_CTL_83_DATA
-				DDRSS3_CTL_84_DATA
-				DDRSS3_CTL_85_DATA
-				DDRSS3_CTL_86_DATA
-				DDRSS3_CTL_87_DATA
-				DDRSS3_CTL_88_DATA
-				DDRSS3_CTL_89_DATA
-				DDRSS3_CTL_90_DATA
-				DDRSS3_CTL_91_DATA
-				DDRSS3_CTL_92_DATA
-				DDRSS3_CTL_93_DATA
-				DDRSS3_CTL_94_DATA
-				DDRSS3_CTL_95_DATA
-				DDRSS3_CTL_96_DATA
-				DDRSS3_CTL_97_DATA
-				DDRSS3_CTL_98_DATA
-				DDRSS3_CTL_99_DATA
-				DDRSS3_CTL_100_DATA
-				DDRSS3_CTL_101_DATA
-				DDRSS3_CTL_102_DATA
-				DDRSS3_CTL_103_DATA
-				DDRSS3_CTL_104_DATA
-				DDRSS3_CTL_105_DATA
-				DDRSS3_CTL_106_DATA
-				DDRSS3_CTL_107_DATA
-				DDRSS3_CTL_108_DATA
-				DDRSS3_CTL_109_DATA
-				DDRSS3_CTL_110_DATA
-				DDRSS3_CTL_111_DATA
-				DDRSS3_CTL_112_DATA
-				DDRSS3_CTL_113_DATA
-				DDRSS3_CTL_114_DATA
-				DDRSS3_CTL_115_DATA
-				DDRSS3_CTL_116_DATA
-				DDRSS3_CTL_117_DATA
-				DDRSS3_CTL_118_DATA
-				DDRSS3_CTL_119_DATA
-				DDRSS3_CTL_120_DATA
-				DDRSS3_CTL_121_DATA
-				DDRSS3_CTL_122_DATA
-				DDRSS3_CTL_123_DATA
-				DDRSS3_CTL_124_DATA
-				DDRSS3_CTL_125_DATA
-				DDRSS3_CTL_126_DATA
-				DDRSS3_CTL_127_DATA
-				DDRSS3_CTL_128_DATA
-				DDRSS3_CTL_129_DATA
-				DDRSS3_CTL_130_DATA
-				DDRSS3_CTL_131_DATA
-				DDRSS3_CTL_132_DATA
-				DDRSS3_CTL_133_DATA
-				DDRSS3_CTL_134_DATA
-				DDRSS3_CTL_135_DATA
-				DDRSS3_CTL_136_DATA
-				DDRSS3_CTL_137_DATA
-				DDRSS3_CTL_138_DATA
-				DDRSS3_CTL_139_DATA
-				DDRSS3_CTL_140_DATA
-				DDRSS3_CTL_141_DATA
-				DDRSS3_CTL_142_DATA
-				DDRSS3_CTL_143_DATA
-				DDRSS3_CTL_144_DATA
-				DDRSS3_CTL_145_DATA
-				DDRSS3_CTL_146_DATA
-				DDRSS3_CTL_147_DATA
-				DDRSS3_CTL_148_DATA
-				DDRSS3_CTL_149_DATA
-				DDRSS3_CTL_150_DATA
-				DDRSS3_CTL_151_DATA
-				DDRSS3_CTL_152_DATA
-				DDRSS3_CTL_153_DATA
-				DDRSS3_CTL_154_DATA
-				DDRSS3_CTL_155_DATA
-				DDRSS3_CTL_156_DATA
-				DDRSS3_CTL_157_DATA
-				DDRSS3_CTL_158_DATA
-				DDRSS3_CTL_159_DATA
-				DDRSS3_CTL_160_DATA
-				DDRSS3_CTL_161_DATA
-				DDRSS3_CTL_162_DATA
-				DDRSS3_CTL_163_DATA
-				DDRSS3_CTL_164_DATA
-				DDRSS3_CTL_165_DATA
-				DDRSS3_CTL_166_DATA
-				DDRSS3_CTL_167_DATA
-				DDRSS3_CTL_168_DATA
-				DDRSS3_CTL_169_DATA
-				DDRSS3_CTL_170_DATA
-				DDRSS3_CTL_171_DATA
-				DDRSS3_CTL_172_DATA
-				DDRSS3_CTL_173_DATA
-				DDRSS3_CTL_174_DATA
-				DDRSS3_CTL_175_DATA
-				DDRSS3_CTL_176_DATA
-				DDRSS3_CTL_177_DATA
-				DDRSS3_CTL_178_DATA
-				DDRSS3_CTL_179_DATA
-				DDRSS3_CTL_180_DATA
-				DDRSS3_CTL_181_DATA
-				DDRSS3_CTL_182_DATA
-				DDRSS3_CTL_183_DATA
-				DDRSS3_CTL_184_DATA
-				DDRSS3_CTL_185_DATA
-				DDRSS3_CTL_186_DATA
-				DDRSS3_CTL_187_DATA
-				DDRSS3_CTL_188_DATA
-				DDRSS3_CTL_189_DATA
-				DDRSS3_CTL_190_DATA
-				DDRSS3_CTL_191_DATA
-				DDRSS3_CTL_192_DATA
-				DDRSS3_CTL_193_DATA
-				DDRSS3_CTL_194_DATA
-				DDRSS3_CTL_195_DATA
-				DDRSS3_CTL_196_DATA
-				DDRSS3_CTL_197_DATA
-				DDRSS3_CTL_198_DATA
-				DDRSS3_CTL_199_DATA
-				DDRSS3_CTL_200_DATA
-				DDRSS3_CTL_201_DATA
-				DDRSS3_CTL_202_DATA
-				DDRSS3_CTL_203_DATA
-				DDRSS3_CTL_204_DATA
-				DDRSS3_CTL_205_DATA
-				DDRSS3_CTL_206_DATA
-				DDRSS3_CTL_207_DATA
-				DDRSS3_CTL_208_DATA
-				DDRSS3_CTL_209_DATA
-				DDRSS3_CTL_210_DATA
-				DDRSS3_CTL_211_DATA
-				DDRSS3_CTL_212_DATA
-				DDRSS3_CTL_213_DATA
-				DDRSS3_CTL_214_DATA
-				DDRSS3_CTL_215_DATA
-				DDRSS3_CTL_216_DATA
-				DDRSS3_CTL_217_DATA
-				DDRSS3_CTL_218_DATA
-				DDRSS3_CTL_219_DATA
-				DDRSS3_CTL_220_DATA
-				DDRSS3_CTL_221_DATA
-				DDRSS3_CTL_222_DATA
-				DDRSS3_CTL_223_DATA
-				DDRSS3_CTL_224_DATA
-				DDRSS3_CTL_225_DATA
-				DDRSS3_CTL_226_DATA
-				DDRSS3_CTL_227_DATA
-				DDRSS3_CTL_228_DATA
-				DDRSS3_CTL_229_DATA
-				DDRSS3_CTL_230_DATA
-				DDRSS3_CTL_231_DATA
-				DDRSS3_CTL_232_DATA
-				DDRSS3_CTL_233_DATA
-				DDRSS3_CTL_234_DATA
-				DDRSS3_CTL_235_DATA
-				DDRSS3_CTL_236_DATA
-				DDRSS3_CTL_237_DATA
-				DDRSS3_CTL_238_DATA
-				DDRSS3_CTL_239_DATA
-				DDRSS3_CTL_240_DATA
-				DDRSS3_CTL_241_DATA
-				DDRSS3_CTL_242_DATA
-				DDRSS3_CTL_243_DATA
-				DDRSS3_CTL_244_DATA
-				DDRSS3_CTL_245_DATA
-				DDRSS3_CTL_246_DATA
-				DDRSS3_CTL_247_DATA
-				DDRSS3_CTL_248_DATA
-				DDRSS3_CTL_249_DATA
-				DDRSS3_CTL_250_DATA
-				DDRSS3_CTL_251_DATA
-				DDRSS3_CTL_252_DATA
-				DDRSS3_CTL_253_DATA
-				DDRSS3_CTL_254_DATA
-				DDRSS3_CTL_255_DATA
-				DDRSS3_CTL_256_DATA
-				DDRSS3_CTL_257_DATA
-				DDRSS3_CTL_258_DATA
-				DDRSS3_CTL_259_DATA
-				DDRSS3_CTL_260_DATA
-				DDRSS3_CTL_261_DATA
-				DDRSS3_CTL_262_DATA
-				DDRSS3_CTL_263_DATA
-				DDRSS3_CTL_264_DATA
-				DDRSS3_CTL_265_DATA
-				DDRSS3_CTL_266_DATA
-				DDRSS3_CTL_267_DATA
-				DDRSS3_CTL_268_DATA
-				DDRSS3_CTL_269_DATA
-				DDRSS3_CTL_270_DATA
-				DDRSS3_CTL_271_DATA
-				DDRSS3_CTL_272_DATA
-				DDRSS3_CTL_273_DATA
-				DDRSS3_CTL_274_DATA
-				DDRSS3_CTL_275_DATA
-				DDRSS3_CTL_276_DATA
-				DDRSS3_CTL_277_DATA
-				DDRSS3_CTL_278_DATA
-				DDRSS3_CTL_279_DATA
-				DDRSS3_CTL_280_DATA
-				DDRSS3_CTL_281_DATA
-				DDRSS3_CTL_282_DATA
-				DDRSS3_CTL_283_DATA
-				DDRSS3_CTL_284_DATA
-				DDRSS3_CTL_285_DATA
-				DDRSS3_CTL_286_DATA
-				DDRSS3_CTL_287_DATA
-				DDRSS3_CTL_288_DATA
-				DDRSS3_CTL_289_DATA
-				DDRSS3_CTL_290_DATA
-				DDRSS3_CTL_291_DATA
-				DDRSS3_CTL_292_DATA
-				DDRSS3_CTL_293_DATA
-				DDRSS3_CTL_294_DATA
-				DDRSS3_CTL_295_DATA
-				DDRSS3_CTL_296_DATA
-				DDRSS3_CTL_297_DATA
-				DDRSS3_CTL_298_DATA
-				DDRSS3_CTL_299_DATA
-				DDRSS3_CTL_300_DATA
-				DDRSS3_CTL_301_DATA
-				DDRSS3_CTL_302_DATA
-				DDRSS3_CTL_303_DATA
-				DDRSS3_CTL_304_DATA
-				DDRSS3_CTL_305_DATA
-				DDRSS3_CTL_306_DATA
-				DDRSS3_CTL_307_DATA
-				DDRSS3_CTL_308_DATA
-				DDRSS3_CTL_309_DATA
-				DDRSS3_CTL_310_DATA
-				DDRSS3_CTL_311_DATA
-				DDRSS3_CTL_312_DATA
-				DDRSS3_CTL_313_DATA
-				DDRSS3_CTL_314_DATA
-				DDRSS3_CTL_315_DATA
-				DDRSS3_CTL_316_DATA
-				DDRSS3_CTL_317_DATA
-				DDRSS3_CTL_318_DATA
-				DDRSS3_CTL_319_DATA
-				DDRSS3_CTL_320_DATA
-				DDRSS3_CTL_321_DATA
-				DDRSS3_CTL_322_DATA
-				DDRSS3_CTL_323_DATA
-				DDRSS3_CTL_324_DATA
-				DDRSS3_CTL_325_DATA
-				DDRSS3_CTL_326_DATA
-				DDRSS3_CTL_327_DATA
-				DDRSS3_CTL_328_DATA
-				DDRSS3_CTL_329_DATA
-				DDRSS3_CTL_330_DATA
-				DDRSS3_CTL_331_DATA
-				DDRSS3_CTL_332_DATA
-				DDRSS3_CTL_333_DATA
-				DDRSS3_CTL_334_DATA
-				DDRSS3_CTL_335_DATA
-				DDRSS3_CTL_336_DATA
-				DDRSS3_CTL_337_DATA
-				DDRSS3_CTL_338_DATA
-				DDRSS3_CTL_339_DATA
-				DDRSS3_CTL_340_DATA
-				DDRSS3_CTL_341_DATA
-				DDRSS3_CTL_342_DATA
-				DDRSS3_CTL_343_DATA
-				DDRSS3_CTL_344_DATA
-				DDRSS3_CTL_345_DATA
-				DDRSS3_CTL_346_DATA
-				DDRSS3_CTL_347_DATA
-				DDRSS3_CTL_348_DATA
-				DDRSS3_CTL_349_DATA
-				DDRSS3_CTL_350_DATA
-				DDRSS3_CTL_351_DATA
-				DDRSS3_CTL_352_DATA
-				DDRSS3_CTL_353_DATA
-				DDRSS3_CTL_354_DATA
-				DDRSS3_CTL_355_DATA
-				DDRSS3_CTL_356_DATA
-				DDRSS3_CTL_357_DATA
-				DDRSS3_CTL_358_DATA
-				DDRSS3_CTL_359_DATA
-				DDRSS3_CTL_360_DATA
-				DDRSS3_CTL_361_DATA
-				DDRSS3_CTL_362_DATA
-				DDRSS3_CTL_363_DATA
-				DDRSS3_CTL_364_DATA
-				DDRSS3_CTL_365_DATA
-				DDRSS3_CTL_366_DATA
-				DDRSS3_CTL_367_DATA
-				DDRSS3_CTL_368_DATA
-				DDRSS3_CTL_369_DATA
-				DDRSS3_CTL_370_DATA
-				DDRSS3_CTL_371_DATA
-				DDRSS3_CTL_372_DATA
-				DDRSS3_CTL_373_DATA
-				DDRSS3_CTL_374_DATA
-				DDRSS3_CTL_375_DATA
-				DDRSS3_CTL_376_DATA
-				DDRSS3_CTL_377_DATA
-				DDRSS3_CTL_378_DATA
-				DDRSS3_CTL_379_DATA
-				DDRSS3_CTL_380_DATA
-				DDRSS3_CTL_381_DATA
-				DDRSS3_CTL_382_DATA
-				DDRSS3_CTL_383_DATA
-				DDRSS3_CTL_384_DATA
-				DDRSS3_CTL_385_DATA
-				DDRSS3_CTL_386_DATA
-				DDRSS3_CTL_387_DATA
-				DDRSS3_CTL_388_DATA
-				DDRSS3_CTL_389_DATA
-				DDRSS3_CTL_390_DATA
-				DDRSS3_CTL_391_DATA
-				DDRSS3_CTL_392_DATA
-				DDRSS3_CTL_393_DATA
-				DDRSS3_CTL_394_DATA
-				DDRSS3_CTL_395_DATA
-				DDRSS3_CTL_396_DATA
-				DDRSS3_CTL_397_DATA
-				DDRSS3_CTL_398_DATA
-				DDRSS3_CTL_399_DATA
-				DDRSS3_CTL_400_DATA
-				DDRSS3_CTL_401_DATA
-				DDRSS3_CTL_402_DATA
-				DDRSS3_CTL_403_DATA
-				DDRSS3_CTL_404_DATA
-				DDRSS3_CTL_405_DATA
-				DDRSS3_CTL_406_DATA
-				DDRSS3_CTL_407_DATA
-				DDRSS3_CTL_408_DATA
-				DDRSS3_CTL_409_DATA
-				DDRSS3_CTL_410_DATA
-				DDRSS3_CTL_411_DATA
-				DDRSS3_CTL_412_DATA
-				DDRSS3_CTL_413_DATA
-				DDRSS3_CTL_414_DATA
-				DDRSS3_CTL_415_DATA
-				DDRSS3_CTL_416_DATA
-				DDRSS3_CTL_417_DATA
-				DDRSS3_CTL_418_DATA
-				DDRSS3_CTL_419_DATA
-				DDRSS3_CTL_420_DATA
-				DDRSS3_CTL_421_DATA
-				DDRSS3_CTL_422_DATA
-				DDRSS3_CTL_423_DATA
-				DDRSS3_CTL_424_DATA
-				DDRSS3_CTL_425_DATA
-				DDRSS3_CTL_426_DATA
-				DDRSS3_CTL_427_DATA
-				DDRSS3_CTL_428_DATA
-				DDRSS3_CTL_429_DATA
-				DDRSS3_CTL_430_DATA
-				DDRSS3_CTL_431_DATA
-				DDRSS3_CTL_432_DATA
-				DDRSS3_CTL_433_DATA
-				DDRSS3_CTL_434_DATA
-				DDRSS3_CTL_435_DATA
-				DDRSS3_CTL_436_DATA
-				DDRSS3_CTL_437_DATA
-				DDRSS3_CTL_438_DATA
-				DDRSS3_CTL_439_DATA
-				DDRSS3_CTL_440_DATA
-				DDRSS3_CTL_441_DATA
-				DDRSS3_CTL_442_DATA
-				DDRSS3_CTL_443_DATA
-				DDRSS3_CTL_444_DATA
-				DDRSS3_CTL_445_DATA
-				DDRSS3_CTL_446_DATA
-				DDRSS3_CTL_447_DATA
-				DDRSS3_CTL_448_DATA
-				DDRSS3_CTL_449_DATA
-				DDRSS3_CTL_450_DATA
-				DDRSS3_CTL_451_DATA
-				DDRSS3_CTL_452_DATA
-				DDRSS3_CTL_453_DATA
-				DDRSS3_CTL_454_DATA
-				DDRSS3_CTL_455_DATA
-				DDRSS3_CTL_456_DATA
-				DDRSS3_CTL_457_DATA
-				DDRSS3_CTL_458_DATA
-			>;
+		ti,ctl-data = <
+			DDRSS3_CTL_00_DATA
+			DDRSS3_CTL_01_DATA
+			DDRSS3_CTL_02_DATA
+			DDRSS3_CTL_03_DATA
+			DDRSS3_CTL_04_DATA
+			DDRSS3_CTL_05_DATA
+			DDRSS3_CTL_06_DATA
+			DDRSS3_CTL_07_DATA
+			DDRSS3_CTL_08_DATA
+			DDRSS3_CTL_09_DATA
+			DDRSS3_CTL_10_DATA
+			DDRSS3_CTL_11_DATA
+			DDRSS3_CTL_12_DATA
+			DDRSS3_CTL_13_DATA
+			DDRSS3_CTL_14_DATA
+			DDRSS3_CTL_15_DATA
+			DDRSS3_CTL_16_DATA
+			DDRSS3_CTL_17_DATA
+			DDRSS3_CTL_18_DATA
+			DDRSS3_CTL_19_DATA
+			DDRSS3_CTL_20_DATA
+			DDRSS3_CTL_21_DATA
+			DDRSS3_CTL_22_DATA
+			DDRSS3_CTL_23_DATA
+			DDRSS3_CTL_24_DATA
+			DDRSS3_CTL_25_DATA
+			DDRSS3_CTL_26_DATA
+			DDRSS3_CTL_27_DATA
+			DDRSS3_CTL_28_DATA
+			DDRSS3_CTL_29_DATA
+			DDRSS3_CTL_30_DATA
+			DDRSS3_CTL_31_DATA
+			DDRSS3_CTL_32_DATA
+			DDRSS3_CTL_33_DATA
+			DDRSS3_CTL_34_DATA
+			DDRSS3_CTL_35_DATA
+			DDRSS3_CTL_36_DATA
+			DDRSS3_CTL_37_DATA
+			DDRSS3_CTL_38_DATA
+			DDRSS3_CTL_39_DATA
+			DDRSS3_CTL_40_DATA
+			DDRSS3_CTL_41_DATA
+			DDRSS3_CTL_42_DATA
+			DDRSS3_CTL_43_DATA
+			DDRSS3_CTL_44_DATA
+			DDRSS3_CTL_45_DATA
+			DDRSS3_CTL_46_DATA
+			DDRSS3_CTL_47_DATA
+			DDRSS3_CTL_48_DATA
+			DDRSS3_CTL_49_DATA
+			DDRSS3_CTL_50_DATA
+			DDRSS3_CTL_51_DATA
+			DDRSS3_CTL_52_DATA
+			DDRSS3_CTL_53_DATA
+			DDRSS3_CTL_54_DATA
+			DDRSS3_CTL_55_DATA
+			DDRSS3_CTL_56_DATA
+			DDRSS3_CTL_57_DATA
+			DDRSS3_CTL_58_DATA
+			DDRSS3_CTL_59_DATA
+			DDRSS3_CTL_60_DATA
+			DDRSS3_CTL_61_DATA
+			DDRSS3_CTL_62_DATA
+			DDRSS3_CTL_63_DATA
+			DDRSS3_CTL_64_DATA
+			DDRSS3_CTL_65_DATA
+			DDRSS3_CTL_66_DATA
+			DDRSS3_CTL_67_DATA
+			DDRSS3_CTL_68_DATA
+			DDRSS3_CTL_69_DATA
+			DDRSS3_CTL_70_DATA
+			DDRSS3_CTL_71_DATA
+			DDRSS3_CTL_72_DATA
+			DDRSS3_CTL_73_DATA
+			DDRSS3_CTL_74_DATA
+			DDRSS3_CTL_75_DATA
+			DDRSS3_CTL_76_DATA
+			DDRSS3_CTL_77_DATA
+			DDRSS3_CTL_78_DATA
+			DDRSS3_CTL_79_DATA
+			DDRSS3_CTL_80_DATA
+			DDRSS3_CTL_81_DATA
+			DDRSS3_CTL_82_DATA
+			DDRSS3_CTL_83_DATA
+			DDRSS3_CTL_84_DATA
+			DDRSS3_CTL_85_DATA
+			DDRSS3_CTL_86_DATA
+			DDRSS3_CTL_87_DATA
+			DDRSS3_CTL_88_DATA
+			DDRSS3_CTL_89_DATA
+			DDRSS3_CTL_90_DATA
+			DDRSS3_CTL_91_DATA
+			DDRSS3_CTL_92_DATA
+			DDRSS3_CTL_93_DATA
+			DDRSS3_CTL_94_DATA
+			DDRSS3_CTL_95_DATA
+			DDRSS3_CTL_96_DATA
+			DDRSS3_CTL_97_DATA
+			DDRSS3_CTL_98_DATA
+			DDRSS3_CTL_99_DATA
+			DDRSS3_CTL_100_DATA
+			DDRSS3_CTL_101_DATA
+			DDRSS3_CTL_102_DATA
+			DDRSS3_CTL_103_DATA
+			DDRSS3_CTL_104_DATA
+			DDRSS3_CTL_105_DATA
+			DDRSS3_CTL_106_DATA
+			DDRSS3_CTL_107_DATA
+			DDRSS3_CTL_108_DATA
+			DDRSS3_CTL_109_DATA
+			DDRSS3_CTL_110_DATA
+			DDRSS3_CTL_111_DATA
+			DDRSS3_CTL_112_DATA
+			DDRSS3_CTL_113_DATA
+			DDRSS3_CTL_114_DATA
+			DDRSS3_CTL_115_DATA
+			DDRSS3_CTL_116_DATA
+			DDRSS3_CTL_117_DATA
+			DDRSS3_CTL_118_DATA
+			DDRSS3_CTL_119_DATA
+			DDRSS3_CTL_120_DATA
+			DDRSS3_CTL_121_DATA
+			DDRSS3_CTL_122_DATA
+			DDRSS3_CTL_123_DATA
+			DDRSS3_CTL_124_DATA
+			DDRSS3_CTL_125_DATA
+			DDRSS3_CTL_126_DATA
+			DDRSS3_CTL_127_DATA
+			DDRSS3_CTL_128_DATA
+			DDRSS3_CTL_129_DATA
+			DDRSS3_CTL_130_DATA
+			DDRSS3_CTL_131_DATA
+			DDRSS3_CTL_132_DATA
+			DDRSS3_CTL_133_DATA
+			DDRSS3_CTL_134_DATA
+			DDRSS3_CTL_135_DATA
+			DDRSS3_CTL_136_DATA
+			DDRSS3_CTL_137_DATA
+			DDRSS3_CTL_138_DATA
+			DDRSS3_CTL_139_DATA
+			DDRSS3_CTL_140_DATA
+			DDRSS3_CTL_141_DATA
+			DDRSS3_CTL_142_DATA
+			DDRSS3_CTL_143_DATA
+			DDRSS3_CTL_144_DATA
+			DDRSS3_CTL_145_DATA
+			DDRSS3_CTL_146_DATA
+			DDRSS3_CTL_147_DATA
+			DDRSS3_CTL_148_DATA
+			DDRSS3_CTL_149_DATA
+			DDRSS3_CTL_150_DATA
+			DDRSS3_CTL_151_DATA
+			DDRSS3_CTL_152_DATA
+			DDRSS3_CTL_153_DATA
+			DDRSS3_CTL_154_DATA
+			DDRSS3_CTL_155_DATA
+			DDRSS3_CTL_156_DATA
+			DDRSS3_CTL_157_DATA
+			DDRSS3_CTL_158_DATA
+			DDRSS3_CTL_159_DATA
+			DDRSS3_CTL_160_DATA
+			DDRSS3_CTL_161_DATA
+			DDRSS3_CTL_162_DATA
+			DDRSS3_CTL_163_DATA
+			DDRSS3_CTL_164_DATA
+			DDRSS3_CTL_165_DATA
+			DDRSS3_CTL_166_DATA
+			DDRSS3_CTL_167_DATA
+			DDRSS3_CTL_168_DATA
+			DDRSS3_CTL_169_DATA
+			DDRSS3_CTL_170_DATA
+			DDRSS3_CTL_171_DATA
+			DDRSS3_CTL_172_DATA
+			DDRSS3_CTL_173_DATA
+			DDRSS3_CTL_174_DATA
+			DDRSS3_CTL_175_DATA
+			DDRSS3_CTL_176_DATA
+			DDRSS3_CTL_177_DATA
+			DDRSS3_CTL_178_DATA
+			DDRSS3_CTL_179_DATA
+			DDRSS3_CTL_180_DATA
+			DDRSS3_CTL_181_DATA
+			DDRSS3_CTL_182_DATA
+			DDRSS3_CTL_183_DATA
+			DDRSS3_CTL_184_DATA
+			DDRSS3_CTL_185_DATA
+			DDRSS3_CTL_186_DATA
+			DDRSS3_CTL_187_DATA
+			DDRSS3_CTL_188_DATA
+			DDRSS3_CTL_189_DATA
+			DDRSS3_CTL_190_DATA
+			DDRSS3_CTL_191_DATA
+			DDRSS3_CTL_192_DATA
+			DDRSS3_CTL_193_DATA
+			DDRSS3_CTL_194_DATA
+			DDRSS3_CTL_195_DATA
+			DDRSS3_CTL_196_DATA
+			DDRSS3_CTL_197_DATA
+			DDRSS3_CTL_198_DATA
+			DDRSS3_CTL_199_DATA
+			DDRSS3_CTL_200_DATA
+			DDRSS3_CTL_201_DATA
+			DDRSS3_CTL_202_DATA
+			DDRSS3_CTL_203_DATA
+			DDRSS3_CTL_204_DATA
+			DDRSS3_CTL_205_DATA
+			DDRSS3_CTL_206_DATA
+			DDRSS3_CTL_207_DATA
+			DDRSS3_CTL_208_DATA
+			DDRSS3_CTL_209_DATA
+			DDRSS3_CTL_210_DATA
+			DDRSS3_CTL_211_DATA
+			DDRSS3_CTL_212_DATA
+			DDRSS3_CTL_213_DATA
+			DDRSS3_CTL_214_DATA
+			DDRSS3_CTL_215_DATA
+			DDRSS3_CTL_216_DATA
+			DDRSS3_CTL_217_DATA
+			DDRSS3_CTL_218_DATA
+			DDRSS3_CTL_219_DATA
+			DDRSS3_CTL_220_DATA
+			DDRSS3_CTL_221_DATA
+			DDRSS3_CTL_222_DATA
+			DDRSS3_CTL_223_DATA
+			DDRSS3_CTL_224_DATA
+			DDRSS3_CTL_225_DATA
+			DDRSS3_CTL_226_DATA
+			DDRSS3_CTL_227_DATA
+			DDRSS3_CTL_228_DATA
+			DDRSS3_CTL_229_DATA
+			DDRSS3_CTL_230_DATA
+			DDRSS3_CTL_231_DATA
+			DDRSS3_CTL_232_DATA
+			DDRSS3_CTL_233_DATA
+			DDRSS3_CTL_234_DATA
+			DDRSS3_CTL_235_DATA
+			DDRSS3_CTL_236_DATA
+			DDRSS3_CTL_237_DATA
+			DDRSS3_CTL_238_DATA
+			DDRSS3_CTL_239_DATA
+			DDRSS3_CTL_240_DATA
+			DDRSS3_CTL_241_DATA
+			DDRSS3_CTL_242_DATA
+			DDRSS3_CTL_243_DATA
+			DDRSS3_CTL_244_DATA
+			DDRSS3_CTL_245_DATA
+			DDRSS3_CTL_246_DATA
+			DDRSS3_CTL_247_DATA
+			DDRSS3_CTL_248_DATA
+			DDRSS3_CTL_249_DATA
+			DDRSS3_CTL_250_DATA
+			DDRSS3_CTL_251_DATA
+			DDRSS3_CTL_252_DATA
+			DDRSS3_CTL_253_DATA
+			DDRSS3_CTL_254_DATA
+			DDRSS3_CTL_255_DATA
+			DDRSS3_CTL_256_DATA
+			DDRSS3_CTL_257_DATA
+			DDRSS3_CTL_258_DATA
+			DDRSS3_CTL_259_DATA
+			DDRSS3_CTL_260_DATA
+			DDRSS3_CTL_261_DATA
+			DDRSS3_CTL_262_DATA
+			DDRSS3_CTL_263_DATA
+			DDRSS3_CTL_264_DATA
+			DDRSS3_CTL_265_DATA
+			DDRSS3_CTL_266_DATA
+			DDRSS3_CTL_267_DATA
+			DDRSS3_CTL_268_DATA
+			DDRSS3_CTL_269_DATA
+			DDRSS3_CTL_270_DATA
+			DDRSS3_CTL_271_DATA
+			DDRSS3_CTL_272_DATA
+			DDRSS3_CTL_273_DATA
+			DDRSS3_CTL_274_DATA
+			DDRSS3_CTL_275_DATA
+			DDRSS3_CTL_276_DATA
+			DDRSS3_CTL_277_DATA
+			DDRSS3_CTL_278_DATA
+			DDRSS3_CTL_279_DATA
+			DDRSS3_CTL_280_DATA
+			DDRSS3_CTL_281_DATA
+			DDRSS3_CTL_282_DATA
+			DDRSS3_CTL_283_DATA
+			DDRSS3_CTL_284_DATA
+			DDRSS3_CTL_285_DATA
+			DDRSS3_CTL_286_DATA
+			DDRSS3_CTL_287_DATA
+			DDRSS3_CTL_288_DATA
+			DDRSS3_CTL_289_DATA
+			DDRSS3_CTL_290_DATA
+			DDRSS3_CTL_291_DATA
+			DDRSS3_CTL_292_DATA
+			DDRSS3_CTL_293_DATA
+			DDRSS3_CTL_294_DATA
+			DDRSS3_CTL_295_DATA
+			DDRSS3_CTL_296_DATA
+			DDRSS3_CTL_297_DATA
+			DDRSS3_CTL_298_DATA
+			DDRSS3_CTL_299_DATA
+			DDRSS3_CTL_300_DATA
+			DDRSS3_CTL_301_DATA
+			DDRSS3_CTL_302_DATA
+			DDRSS3_CTL_303_DATA
+			DDRSS3_CTL_304_DATA
+			DDRSS3_CTL_305_DATA
+			DDRSS3_CTL_306_DATA
+			DDRSS3_CTL_307_DATA
+			DDRSS3_CTL_308_DATA
+			DDRSS3_CTL_309_DATA
+			DDRSS3_CTL_310_DATA
+			DDRSS3_CTL_311_DATA
+			DDRSS3_CTL_312_DATA
+			DDRSS3_CTL_313_DATA
+			DDRSS3_CTL_314_DATA
+			DDRSS3_CTL_315_DATA
+			DDRSS3_CTL_316_DATA
+			DDRSS3_CTL_317_DATA
+			DDRSS3_CTL_318_DATA
+			DDRSS3_CTL_319_DATA
+			DDRSS3_CTL_320_DATA
+			DDRSS3_CTL_321_DATA
+			DDRSS3_CTL_322_DATA
+			DDRSS3_CTL_323_DATA
+			DDRSS3_CTL_324_DATA
+			DDRSS3_CTL_325_DATA
+			DDRSS3_CTL_326_DATA
+			DDRSS3_CTL_327_DATA
+			DDRSS3_CTL_328_DATA
+			DDRSS3_CTL_329_DATA
+			DDRSS3_CTL_330_DATA
+			DDRSS3_CTL_331_DATA
+			DDRSS3_CTL_332_DATA
+			DDRSS3_CTL_333_DATA
+			DDRSS3_CTL_334_DATA
+			DDRSS3_CTL_335_DATA
+			DDRSS3_CTL_336_DATA
+			DDRSS3_CTL_337_DATA
+			DDRSS3_CTL_338_DATA
+			DDRSS3_CTL_339_DATA
+			DDRSS3_CTL_340_DATA
+			DDRSS3_CTL_341_DATA
+			DDRSS3_CTL_342_DATA
+			DDRSS3_CTL_343_DATA
+			DDRSS3_CTL_344_DATA
+			DDRSS3_CTL_345_DATA
+			DDRSS3_CTL_346_DATA
+			DDRSS3_CTL_347_DATA
+			DDRSS3_CTL_348_DATA
+			DDRSS3_CTL_349_DATA
+			DDRSS3_CTL_350_DATA
+			DDRSS3_CTL_351_DATA
+			DDRSS3_CTL_352_DATA
+			DDRSS3_CTL_353_DATA
+			DDRSS3_CTL_354_DATA
+			DDRSS3_CTL_355_DATA
+			DDRSS3_CTL_356_DATA
+			DDRSS3_CTL_357_DATA
+			DDRSS3_CTL_358_DATA
+			DDRSS3_CTL_359_DATA
+			DDRSS3_CTL_360_DATA
+			DDRSS3_CTL_361_DATA
+			DDRSS3_CTL_362_DATA
+			DDRSS3_CTL_363_DATA
+			DDRSS3_CTL_364_DATA
+			DDRSS3_CTL_365_DATA
+			DDRSS3_CTL_366_DATA
+			DDRSS3_CTL_367_DATA
+			DDRSS3_CTL_368_DATA
+			DDRSS3_CTL_369_DATA
+			DDRSS3_CTL_370_DATA
+			DDRSS3_CTL_371_DATA
+			DDRSS3_CTL_372_DATA
+			DDRSS3_CTL_373_DATA
+			DDRSS3_CTL_374_DATA
+			DDRSS3_CTL_375_DATA
+			DDRSS3_CTL_376_DATA
+			DDRSS3_CTL_377_DATA
+			DDRSS3_CTL_378_DATA
+			DDRSS3_CTL_379_DATA
+			DDRSS3_CTL_380_DATA
+			DDRSS3_CTL_381_DATA
+			DDRSS3_CTL_382_DATA
+			DDRSS3_CTL_383_DATA
+			DDRSS3_CTL_384_DATA
+			DDRSS3_CTL_385_DATA
+			DDRSS3_CTL_386_DATA
+			DDRSS3_CTL_387_DATA
+			DDRSS3_CTL_388_DATA
+			DDRSS3_CTL_389_DATA
+			DDRSS3_CTL_390_DATA
+			DDRSS3_CTL_391_DATA
+			DDRSS3_CTL_392_DATA
+			DDRSS3_CTL_393_DATA
+			DDRSS3_CTL_394_DATA
+			DDRSS3_CTL_395_DATA
+			DDRSS3_CTL_396_DATA
+			DDRSS3_CTL_397_DATA
+			DDRSS3_CTL_398_DATA
+			DDRSS3_CTL_399_DATA
+			DDRSS3_CTL_400_DATA
+			DDRSS3_CTL_401_DATA
+			DDRSS3_CTL_402_DATA
+			DDRSS3_CTL_403_DATA
+			DDRSS3_CTL_404_DATA
+			DDRSS3_CTL_405_DATA
+			DDRSS3_CTL_406_DATA
+			DDRSS3_CTL_407_DATA
+			DDRSS3_CTL_408_DATA
+			DDRSS3_CTL_409_DATA
+			DDRSS3_CTL_410_DATA
+			DDRSS3_CTL_411_DATA
+			DDRSS3_CTL_412_DATA
+			DDRSS3_CTL_413_DATA
+			DDRSS3_CTL_414_DATA
+			DDRSS3_CTL_415_DATA
+			DDRSS3_CTL_416_DATA
+			DDRSS3_CTL_417_DATA
+			DDRSS3_CTL_418_DATA
+			DDRSS3_CTL_419_DATA
+			DDRSS3_CTL_420_DATA
+			DDRSS3_CTL_421_DATA
+			DDRSS3_CTL_422_DATA
+			DDRSS3_CTL_423_DATA
+			DDRSS3_CTL_424_DATA
+			DDRSS3_CTL_425_DATA
+			DDRSS3_CTL_426_DATA
+			DDRSS3_CTL_427_DATA
+			DDRSS3_CTL_428_DATA
+			DDRSS3_CTL_429_DATA
+			DDRSS3_CTL_430_DATA
+			DDRSS3_CTL_431_DATA
+			DDRSS3_CTL_432_DATA
+			DDRSS3_CTL_433_DATA
+			DDRSS3_CTL_434_DATA
+			DDRSS3_CTL_435_DATA
+			DDRSS3_CTL_436_DATA
+			DDRSS3_CTL_437_DATA
+			DDRSS3_CTL_438_DATA
+			DDRSS3_CTL_439_DATA
+			DDRSS3_CTL_440_DATA
+			DDRSS3_CTL_441_DATA
+			DDRSS3_CTL_442_DATA
+			DDRSS3_CTL_443_DATA
+			DDRSS3_CTL_444_DATA
+			DDRSS3_CTL_445_DATA
+			DDRSS3_CTL_446_DATA
+			DDRSS3_CTL_447_DATA
+			DDRSS3_CTL_448_DATA
+			DDRSS3_CTL_449_DATA
+			DDRSS3_CTL_450_DATA
+			DDRSS3_CTL_451_DATA
+			DDRSS3_CTL_452_DATA
+			DDRSS3_CTL_453_DATA
+			DDRSS3_CTL_454_DATA
+			DDRSS3_CTL_455_DATA
+			DDRSS3_CTL_456_DATA
+			DDRSS3_CTL_457_DATA
+			DDRSS3_CTL_458_DATA
+		>;
 
-			ti,pi-data = <
-				DDRSS3_PI_00_DATA
-				DDRSS3_PI_01_DATA
-				DDRSS3_PI_02_DATA
-				DDRSS3_PI_03_DATA
-				DDRSS3_PI_04_DATA
-				DDRSS3_PI_05_DATA
-				DDRSS3_PI_06_DATA
-				DDRSS3_PI_07_DATA
-				DDRSS3_PI_08_DATA
-				DDRSS3_PI_09_DATA
-				DDRSS3_PI_10_DATA
-				DDRSS3_PI_11_DATA
-				DDRSS3_PI_12_DATA
-				DDRSS3_PI_13_DATA
-				DDRSS3_PI_14_DATA
-				DDRSS3_PI_15_DATA
-				DDRSS3_PI_16_DATA
-				DDRSS3_PI_17_DATA
-				DDRSS3_PI_18_DATA
-				DDRSS3_PI_19_DATA
-				DDRSS3_PI_20_DATA
-				DDRSS3_PI_21_DATA
-				DDRSS3_PI_22_DATA
-				DDRSS3_PI_23_DATA
-				DDRSS3_PI_24_DATA
-				DDRSS3_PI_25_DATA
-				DDRSS3_PI_26_DATA
-				DDRSS3_PI_27_DATA
-				DDRSS3_PI_28_DATA
-				DDRSS3_PI_29_DATA
-				DDRSS3_PI_30_DATA
-				DDRSS3_PI_31_DATA
-				DDRSS3_PI_32_DATA
-				DDRSS3_PI_33_DATA
-				DDRSS3_PI_34_DATA
-				DDRSS3_PI_35_DATA
-				DDRSS3_PI_36_DATA
-				DDRSS3_PI_37_DATA
-				DDRSS3_PI_38_DATA
-				DDRSS3_PI_39_DATA
-				DDRSS3_PI_40_DATA
-				DDRSS3_PI_41_DATA
-				DDRSS3_PI_42_DATA
-				DDRSS3_PI_43_DATA
-				DDRSS3_PI_44_DATA
-				DDRSS3_PI_45_DATA
-				DDRSS3_PI_46_DATA
-				DDRSS3_PI_47_DATA
-				DDRSS3_PI_48_DATA
-				DDRSS3_PI_49_DATA
-				DDRSS3_PI_50_DATA
-				DDRSS3_PI_51_DATA
-				DDRSS3_PI_52_DATA
-				DDRSS3_PI_53_DATA
-				DDRSS3_PI_54_DATA
-				DDRSS3_PI_55_DATA
-				DDRSS3_PI_56_DATA
-				DDRSS3_PI_57_DATA
-				DDRSS3_PI_58_DATA
-				DDRSS3_PI_59_DATA
-				DDRSS3_PI_60_DATA
-				DDRSS3_PI_61_DATA
-				DDRSS3_PI_62_DATA
-				DDRSS3_PI_63_DATA
-				DDRSS3_PI_64_DATA
-				DDRSS3_PI_65_DATA
-				DDRSS3_PI_66_DATA
-				DDRSS3_PI_67_DATA
-				DDRSS3_PI_68_DATA
-				DDRSS3_PI_69_DATA
-				DDRSS3_PI_70_DATA
-				DDRSS3_PI_71_DATA
-				DDRSS3_PI_72_DATA
-				DDRSS3_PI_73_DATA
-				DDRSS3_PI_74_DATA
-				DDRSS3_PI_75_DATA
-				DDRSS3_PI_76_DATA
-				DDRSS3_PI_77_DATA
-				DDRSS3_PI_78_DATA
-				DDRSS3_PI_79_DATA
-				DDRSS3_PI_80_DATA
-				DDRSS3_PI_81_DATA
-				DDRSS3_PI_82_DATA
-				DDRSS3_PI_83_DATA
-				DDRSS3_PI_84_DATA
-				DDRSS3_PI_85_DATA
-				DDRSS3_PI_86_DATA
-				DDRSS3_PI_87_DATA
-				DDRSS3_PI_88_DATA
-				DDRSS3_PI_89_DATA
-				DDRSS3_PI_90_DATA
-				DDRSS3_PI_91_DATA
-				DDRSS3_PI_92_DATA
-				DDRSS3_PI_93_DATA
-				DDRSS3_PI_94_DATA
-				DDRSS3_PI_95_DATA
-				DDRSS3_PI_96_DATA
-				DDRSS3_PI_97_DATA
-				DDRSS3_PI_98_DATA
-				DDRSS3_PI_99_DATA
-				DDRSS3_PI_100_DATA
-				DDRSS3_PI_101_DATA
-				DDRSS3_PI_102_DATA
-				DDRSS3_PI_103_DATA
-				DDRSS3_PI_104_DATA
-				DDRSS3_PI_105_DATA
-				DDRSS3_PI_106_DATA
-				DDRSS3_PI_107_DATA
-				DDRSS3_PI_108_DATA
-				DDRSS3_PI_109_DATA
-				DDRSS3_PI_110_DATA
-				DDRSS3_PI_111_DATA
-				DDRSS3_PI_112_DATA
-				DDRSS3_PI_113_DATA
-				DDRSS3_PI_114_DATA
-				DDRSS3_PI_115_DATA
-				DDRSS3_PI_116_DATA
-				DDRSS3_PI_117_DATA
-				DDRSS3_PI_118_DATA
-				DDRSS3_PI_119_DATA
-				DDRSS3_PI_120_DATA
-				DDRSS3_PI_121_DATA
-				DDRSS3_PI_122_DATA
-				DDRSS3_PI_123_DATA
-				DDRSS3_PI_124_DATA
-				DDRSS3_PI_125_DATA
-				DDRSS3_PI_126_DATA
-				DDRSS3_PI_127_DATA
-				DDRSS3_PI_128_DATA
-				DDRSS3_PI_129_DATA
-				DDRSS3_PI_130_DATA
-				DDRSS3_PI_131_DATA
-				DDRSS3_PI_132_DATA
-				DDRSS3_PI_133_DATA
-				DDRSS3_PI_134_DATA
-				DDRSS3_PI_135_DATA
-				DDRSS3_PI_136_DATA
-				DDRSS3_PI_137_DATA
-				DDRSS3_PI_138_DATA
-				DDRSS3_PI_139_DATA
-				DDRSS3_PI_140_DATA
-				DDRSS3_PI_141_DATA
-				DDRSS3_PI_142_DATA
-				DDRSS3_PI_143_DATA
-				DDRSS3_PI_144_DATA
-				DDRSS3_PI_145_DATA
-				DDRSS3_PI_146_DATA
-				DDRSS3_PI_147_DATA
-				DDRSS3_PI_148_DATA
-				DDRSS3_PI_149_DATA
-				DDRSS3_PI_150_DATA
-				DDRSS3_PI_151_DATA
-				DDRSS3_PI_152_DATA
-				DDRSS3_PI_153_DATA
-				DDRSS3_PI_154_DATA
-				DDRSS3_PI_155_DATA
-				DDRSS3_PI_156_DATA
-				DDRSS3_PI_157_DATA
-				DDRSS3_PI_158_DATA
-				DDRSS3_PI_159_DATA
-				DDRSS3_PI_160_DATA
-				DDRSS3_PI_161_DATA
-				DDRSS3_PI_162_DATA
-				DDRSS3_PI_163_DATA
-				DDRSS3_PI_164_DATA
-				DDRSS3_PI_165_DATA
-				DDRSS3_PI_166_DATA
-				DDRSS3_PI_167_DATA
-				DDRSS3_PI_168_DATA
-				DDRSS3_PI_169_DATA
-				DDRSS3_PI_170_DATA
-				DDRSS3_PI_171_DATA
-				DDRSS3_PI_172_DATA
-				DDRSS3_PI_173_DATA
-				DDRSS3_PI_174_DATA
-				DDRSS3_PI_175_DATA
-				DDRSS3_PI_176_DATA
-				DDRSS3_PI_177_DATA
-				DDRSS3_PI_178_DATA
-				DDRSS3_PI_179_DATA
-				DDRSS3_PI_180_DATA
-				DDRSS3_PI_181_DATA
-				DDRSS3_PI_182_DATA
-				DDRSS3_PI_183_DATA
-				DDRSS3_PI_184_DATA
-				DDRSS3_PI_185_DATA
-				DDRSS3_PI_186_DATA
-				DDRSS3_PI_187_DATA
-				DDRSS3_PI_188_DATA
-				DDRSS3_PI_189_DATA
-				DDRSS3_PI_190_DATA
-				DDRSS3_PI_191_DATA
-				DDRSS3_PI_192_DATA
-				DDRSS3_PI_193_DATA
-				DDRSS3_PI_194_DATA
-				DDRSS3_PI_195_DATA
-				DDRSS3_PI_196_DATA
-				DDRSS3_PI_197_DATA
-				DDRSS3_PI_198_DATA
-				DDRSS3_PI_199_DATA
-				DDRSS3_PI_200_DATA
-				DDRSS3_PI_201_DATA
-				DDRSS3_PI_202_DATA
-				DDRSS3_PI_203_DATA
-				DDRSS3_PI_204_DATA
-				DDRSS3_PI_205_DATA
-				DDRSS3_PI_206_DATA
-				DDRSS3_PI_207_DATA
-				DDRSS3_PI_208_DATA
-				DDRSS3_PI_209_DATA
-				DDRSS3_PI_210_DATA
-				DDRSS3_PI_211_DATA
-				DDRSS3_PI_212_DATA
-				DDRSS3_PI_213_DATA
-				DDRSS3_PI_214_DATA
-				DDRSS3_PI_215_DATA
-				DDRSS3_PI_216_DATA
-				DDRSS3_PI_217_DATA
-				DDRSS3_PI_218_DATA
-				DDRSS3_PI_219_DATA
-				DDRSS3_PI_220_DATA
-				DDRSS3_PI_221_DATA
-				DDRSS3_PI_222_DATA
-				DDRSS3_PI_223_DATA
-				DDRSS3_PI_224_DATA
-				DDRSS3_PI_225_DATA
-				DDRSS3_PI_226_DATA
-				DDRSS3_PI_227_DATA
-				DDRSS3_PI_228_DATA
-				DDRSS3_PI_229_DATA
-				DDRSS3_PI_230_DATA
-				DDRSS3_PI_231_DATA
-				DDRSS3_PI_232_DATA
-				DDRSS3_PI_233_DATA
-				DDRSS3_PI_234_DATA
-				DDRSS3_PI_235_DATA
-				DDRSS3_PI_236_DATA
-				DDRSS3_PI_237_DATA
-				DDRSS3_PI_238_DATA
-				DDRSS3_PI_239_DATA
-				DDRSS3_PI_240_DATA
-				DDRSS3_PI_241_DATA
-				DDRSS3_PI_242_DATA
-				DDRSS3_PI_243_DATA
-				DDRSS3_PI_244_DATA
-				DDRSS3_PI_245_DATA
-				DDRSS3_PI_246_DATA
-				DDRSS3_PI_247_DATA
-				DDRSS3_PI_248_DATA
-				DDRSS3_PI_249_DATA
-				DDRSS3_PI_250_DATA
-				DDRSS3_PI_251_DATA
-				DDRSS3_PI_252_DATA
-				DDRSS3_PI_253_DATA
-				DDRSS3_PI_254_DATA
-				DDRSS3_PI_255_DATA
-				DDRSS3_PI_256_DATA
-				DDRSS3_PI_257_DATA
-				DDRSS3_PI_258_DATA
-				DDRSS3_PI_259_DATA
-				DDRSS3_PI_260_DATA
-				DDRSS3_PI_261_DATA
-				DDRSS3_PI_262_DATA
-				DDRSS3_PI_263_DATA
-				DDRSS3_PI_264_DATA
-				DDRSS3_PI_265_DATA
-				DDRSS3_PI_266_DATA
-				DDRSS3_PI_267_DATA
-				DDRSS3_PI_268_DATA
-				DDRSS3_PI_269_DATA
-				DDRSS3_PI_270_DATA
-				DDRSS3_PI_271_DATA
-				DDRSS3_PI_272_DATA
-				DDRSS3_PI_273_DATA
-				DDRSS3_PI_274_DATA
-				DDRSS3_PI_275_DATA
-				DDRSS3_PI_276_DATA
-				DDRSS3_PI_277_DATA
-				DDRSS3_PI_278_DATA
-				DDRSS3_PI_279_DATA
-				DDRSS3_PI_280_DATA
-				DDRSS3_PI_281_DATA
-				DDRSS3_PI_282_DATA
-				DDRSS3_PI_283_DATA
-				DDRSS3_PI_284_DATA
-				DDRSS3_PI_285_DATA
-				DDRSS3_PI_286_DATA
-				DDRSS3_PI_287_DATA
-				DDRSS3_PI_288_DATA
-				DDRSS3_PI_289_DATA
-				DDRSS3_PI_290_DATA
-				DDRSS3_PI_291_DATA
-				DDRSS3_PI_292_DATA
-				DDRSS3_PI_293_DATA
-				DDRSS3_PI_294_DATA
-				DDRSS3_PI_295_DATA
-				DDRSS3_PI_296_DATA
-				DDRSS3_PI_297_DATA
-				DDRSS3_PI_298_DATA
-				DDRSS3_PI_299_DATA
-			>;
+		ti,pi-data = <
+			DDRSS3_PI_00_DATA
+			DDRSS3_PI_01_DATA
+			DDRSS3_PI_02_DATA
+			DDRSS3_PI_03_DATA
+			DDRSS3_PI_04_DATA
+			DDRSS3_PI_05_DATA
+			DDRSS3_PI_06_DATA
+			DDRSS3_PI_07_DATA
+			DDRSS3_PI_08_DATA
+			DDRSS3_PI_09_DATA
+			DDRSS3_PI_10_DATA
+			DDRSS3_PI_11_DATA
+			DDRSS3_PI_12_DATA
+			DDRSS3_PI_13_DATA
+			DDRSS3_PI_14_DATA
+			DDRSS3_PI_15_DATA
+			DDRSS3_PI_16_DATA
+			DDRSS3_PI_17_DATA
+			DDRSS3_PI_18_DATA
+			DDRSS3_PI_19_DATA
+			DDRSS3_PI_20_DATA
+			DDRSS3_PI_21_DATA
+			DDRSS3_PI_22_DATA
+			DDRSS3_PI_23_DATA
+			DDRSS3_PI_24_DATA
+			DDRSS3_PI_25_DATA
+			DDRSS3_PI_26_DATA
+			DDRSS3_PI_27_DATA
+			DDRSS3_PI_28_DATA
+			DDRSS3_PI_29_DATA
+			DDRSS3_PI_30_DATA
+			DDRSS3_PI_31_DATA
+			DDRSS3_PI_32_DATA
+			DDRSS3_PI_33_DATA
+			DDRSS3_PI_34_DATA
+			DDRSS3_PI_35_DATA
+			DDRSS3_PI_36_DATA
+			DDRSS3_PI_37_DATA
+			DDRSS3_PI_38_DATA
+			DDRSS3_PI_39_DATA
+			DDRSS3_PI_40_DATA
+			DDRSS3_PI_41_DATA
+			DDRSS3_PI_42_DATA
+			DDRSS3_PI_43_DATA
+			DDRSS3_PI_44_DATA
+			DDRSS3_PI_45_DATA
+			DDRSS3_PI_46_DATA
+			DDRSS3_PI_47_DATA
+			DDRSS3_PI_48_DATA
+			DDRSS3_PI_49_DATA
+			DDRSS3_PI_50_DATA
+			DDRSS3_PI_51_DATA
+			DDRSS3_PI_52_DATA
+			DDRSS3_PI_53_DATA
+			DDRSS3_PI_54_DATA
+			DDRSS3_PI_55_DATA
+			DDRSS3_PI_56_DATA
+			DDRSS3_PI_57_DATA
+			DDRSS3_PI_58_DATA
+			DDRSS3_PI_59_DATA
+			DDRSS3_PI_60_DATA
+			DDRSS3_PI_61_DATA
+			DDRSS3_PI_62_DATA
+			DDRSS3_PI_63_DATA
+			DDRSS3_PI_64_DATA
+			DDRSS3_PI_65_DATA
+			DDRSS3_PI_66_DATA
+			DDRSS3_PI_67_DATA
+			DDRSS3_PI_68_DATA
+			DDRSS3_PI_69_DATA
+			DDRSS3_PI_70_DATA
+			DDRSS3_PI_71_DATA
+			DDRSS3_PI_72_DATA
+			DDRSS3_PI_73_DATA
+			DDRSS3_PI_74_DATA
+			DDRSS3_PI_75_DATA
+			DDRSS3_PI_76_DATA
+			DDRSS3_PI_77_DATA
+			DDRSS3_PI_78_DATA
+			DDRSS3_PI_79_DATA
+			DDRSS3_PI_80_DATA
+			DDRSS3_PI_81_DATA
+			DDRSS3_PI_82_DATA
+			DDRSS3_PI_83_DATA
+			DDRSS3_PI_84_DATA
+			DDRSS3_PI_85_DATA
+			DDRSS3_PI_86_DATA
+			DDRSS3_PI_87_DATA
+			DDRSS3_PI_88_DATA
+			DDRSS3_PI_89_DATA
+			DDRSS3_PI_90_DATA
+			DDRSS3_PI_91_DATA
+			DDRSS3_PI_92_DATA
+			DDRSS3_PI_93_DATA
+			DDRSS3_PI_94_DATA
+			DDRSS3_PI_95_DATA
+			DDRSS3_PI_96_DATA
+			DDRSS3_PI_97_DATA
+			DDRSS3_PI_98_DATA
+			DDRSS3_PI_99_DATA
+			DDRSS3_PI_100_DATA
+			DDRSS3_PI_101_DATA
+			DDRSS3_PI_102_DATA
+			DDRSS3_PI_103_DATA
+			DDRSS3_PI_104_DATA
+			DDRSS3_PI_105_DATA
+			DDRSS3_PI_106_DATA
+			DDRSS3_PI_107_DATA
+			DDRSS3_PI_108_DATA
+			DDRSS3_PI_109_DATA
+			DDRSS3_PI_110_DATA
+			DDRSS3_PI_111_DATA
+			DDRSS3_PI_112_DATA
+			DDRSS3_PI_113_DATA
+			DDRSS3_PI_114_DATA
+			DDRSS3_PI_115_DATA
+			DDRSS3_PI_116_DATA
+			DDRSS3_PI_117_DATA
+			DDRSS3_PI_118_DATA
+			DDRSS3_PI_119_DATA
+			DDRSS3_PI_120_DATA
+			DDRSS3_PI_121_DATA
+			DDRSS3_PI_122_DATA
+			DDRSS3_PI_123_DATA
+			DDRSS3_PI_124_DATA
+			DDRSS3_PI_125_DATA
+			DDRSS3_PI_126_DATA
+			DDRSS3_PI_127_DATA
+			DDRSS3_PI_128_DATA
+			DDRSS3_PI_129_DATA
+			DDRSS3_PI_130_DATA
+			DDRSS3_PI_131_DATA
+			DDRSS3_PI_132_DATA
+			DDRSS3_PI_133_DATA
+			DDRSS3_PI_134_DATA
+			DDRSS3_PI_135_DATA
+			DDRSS3_PI_136_DATA
+			DDRSS3_PI_137_DATA
+			DDRSS3_PI_138_DATA
+			DDRSS3_PI_139_DATA
+			DDRSS3_PI_140_DATA
+			DDRSS3_PI_141_DATA
+			DDRSS3_PI_142_DATA
+			DDRSS3_PI_143_DATA
+			DDRSS3_PI_144_DATA
+			DDRSS3_PI_145_DATA
+			DDRSS3_PI_146_DATA
+			DDRSS3_PI_147_DATA
+			DDRSS3_PI_148_DATA
+			DDRSS3_PI_149_DATA
+			DDRSS3_PI_150_DATA
+			DDRSS3_PI_151_DATA
+			DDRSS3_PI_152_DATA
+			DDRSS3_PI_153_DATA
+			DDRSS3_PI_154_DATA
+			DDRSS3_PI_155_DATA
+			DDRSS3_PI_156_DATA
+			DDRSS3_PI_157_DATA
+			DDRSS3_PI_158_DATA
+			DDRSS3_PI_159_DATA
+			DDRSS3_PI_160_DATA
+			DDRSS3_PI_161_DATA
+			DDRSS3_PI_162_DATA
+			DDRSS3_PI_163_DATA
+			DDRSS3_PI_164_DATA
+			DDRSS3_PI_165_DATA
+			DDRSS3_PI_166_DATA
+			DDRSS3_PI_167_DATA
+			DDRSS3_PI_168_DATA
+			DDRSS3_PI_169_DATA
+			DDRSS3_PI_170_DATA
+			DDRSS3_PI_171_DATA
+			DDRSS3_PI_172_DATA
+			DDRSS3_PI_173_DATA
+			DDRSS3_PI_174_DATA
+			DDRSS3_PI_175_DATA
+			DDRSS3_PI_176_DATA
+			DDRSS3_PI_177_DATA
+			DDRSS3_PI_178_DATA
+			DDRSS3_PI_179_DATA
+			DDRSS3_PI_180_DATA
+			DDRSS3_PI_181_DATA
+			DDRSS3_PI_182_DATA
+			DDRSS3_PI_183_DATA
+			DDRSS3_PI_184_DATA
+			DDRSS3_PI_185_DATA
+			DDRSS3_PI_186_DATA
+			DDRSS3_PI_187_DATA
+			DDRSS3_PI_188_DATA
+			DDRSS3_PI_189_DATA
+			DDRSS3_PI_190_DATA
+			DDRSS3_PI_191_DATA
+			DDRSS3_PI_192_DATA
+			DDRSS3_PI_193_DATA
+			DDRSS3_PI_194_DATA
+			DDRSS3_PI_195_DATA
+			DDRSS3_PI_196_DATA
+			DDRSS3_PI_197_DATA
+			DDRSS3_PI_198_DATA
+			DDRSS3_PI_199_DATA
+			DDRSS3_PI_200_DATA
+			DDRSS3_PI_201_DATA
+			DDRSS3_PI_202_DATA
+			DDRSS3_PI_203_DATA
+			DDRSS3_PI_204_DATA
+			DDRSS3_PI_205_DATA
+			DDRSS3_PI_206_DATA
+			DDRSS3_PI_207_DATA
+			DDRSS3_PI_208_DATA
+			DDRSS3_PI_209_DATA
+			DDRSS3_PI_210_DATA
+			DDRSS3_PI_211_DATA
+			DDRSS3_PI_212_DATA
+			DDRSS3_PI_213_DATA
+			DDRSS3_PI_214_DATA
+			DDRSS3_PI_215_DATA
+			DDRSS3_PI_216_DATA
+			DDRSS3_PI_217_DATA
+			DDRSS3_PI_218_DATA
+			DDRSS3_PI_219_DATA
+			DDRSS3_PI_220_DATA
+			DDRSS3_PI_221_DATA
+			DDRSS3_PI_222_DATA
+			DDRSS3_PI_223_DATA
+			DDRSS3_PI_224_DATA
+			DDRSS3_PI_225_DATA
+			DDRSS3_PI_226_DATA
+			DDRSS3_PI_227_DATA
+			DDRSS3_PI_228_DATA
+			DDRSS3_PI_229_DATA
+			DDRSS3_PI_230_DATA
+			DDRSS3_PI_231_DATA
+			DDRSS3_PI_232_DATA
+			DDRSS3_PI_233_DATA
+			DDRSS3_PI_234_DATA
+			DDRSS3_PI_235_DATA
+			DDRSS3_PI_236_DATA
+			DDRSS3_PI_237_DATA
+			DDRSS3_PI_238_DATA
+			DDRSS3_PI_239_DATA
+			DDRSS3_PI_240_DATA
+			DDRSS3_PI_241_DATA
+			DDRSS3_PI_242_DATA
+			DDRSS3_PI_243_DATA
+			DDRSS3_PI_244_DATA
+			DDRSS3_PI_245_DATA
+			DDRSS3_PI_246_DATA
+			DDRSS3_PI_247_DATA
+			DDRSS3_PI_248_DATA
+			DDRSS3_PI_249_DATA
+			DDRSS3_PI_250_DATA
+			DDRSS3_PI_251_DATA
+			DDRSS3_PI_252_DATA
+			DDRSS3_PI_253_DATA
+			DDRSS3_PI_254_DATA
+			DDRSS3_PI_255_DATA
+			DDRSS3_PI_256_DATA
+			DDRSS3_PI_257_DATA
+			DDRSS3_PI_258_DATA
+			DDRSS3_PI_259_DATA
+			DDRSS3_PI_260_DATA
+			DDRSS3_PI_261_DATA
+			DDRSS3_PI_262_DATA
+			DDRSS3_PI_263_DATA
+			DDRSS3_PI_264_DATA
+			DDRSS3_PI_265_DATA
+			DDRSS3_PI_266_DATA
+			DDRSS3_PI_267_DATA
+			DDRSS3_PI_268_DATA
+			DDRSS3_PI_269_DATA
+			DDRSS3_PI_270_DATA
+			DDRSS3_PI_271_DATA
+			DDRSS3_PI_272_DATA
+			DDRSS3_PI_273_DATA
+			DDRSS3_PI_274_DATA
+			DDRSS3_PI_275_DATA
+			DDRSS3_PI_276_DATA
+			DDRSS3_PI_277_DATA
+			DDRSS3_PI_278_DATA
+			DDRSS3_PI_279_DATA
+			DDRSS3_PI_280_DATA
+			DDRSS3_PI_281_DATA
+			DDRSS3_PI_282_DATA
+			DDRSS3_PI_283_DATA
+			DDRSS3_PI_284_DATA
+			DDRSS3_PI_285_DATA
+			DDRSS3_PI_286_DATA
+			DDRSS3_PI_287_DATA
+			DDRSS3_PI_288_DATA
+			DDRSS3_PI_289_DATA
+			DDRSS3_PI_290_DATA
+			DDRSS3_PI_291_DATA
+			DDRSS3_PI_292_DATA
+			DDRSS3_PI_293_DATA
+			DDRSS3_PI_294_DATA
+			DDRSS3_PI_295_DATA
+			DDRSS3_PI_296_DATA
+			DDRSS3_PI_297_DATA
+			DDRSS3_PI_298_DATA
+			DDRSS3_PI_299_DATA
+		>;
 
-			ti,phy-data = <
-				DDRSS3_PHY_00_DATA
-				DDRSS3_PHY_01_DATA
-				DDRSS3_PHY_02_DATA
-				DDRSS3_PHY_03_DATA
-				DDRSS3_PHY_04_DATA
-				DDRSS3_PHY_05_DATA
-				DDRSS3_PHY_06_DATA
-				DDRSS3_PHY_07_DATA
-				DDRSS3_PHY_08_DATA
-				DDRSS3_PHY_09_DATA
-				DDRSS3_PHY_10_DATA
-				DDRSS3_PHY_11_DATA
-				DDRSS3_PHY_12_DATA
-				DDRSS3_PHY_13_DATA
-				DDRSS3_PHY_14_DATA
-				DDRSS3_PHY_15_DATA
-				DDRSS3_PHY_16_DATA
-				DDRSS3_PHY_17_DATA
-				DDRSS3_PHY_18_DATA
-				DDRSS3_PHY_19_DATA
-				DDRSS3_PHY_20_DATA
-				DDRSS3_PHY_21_DATA
-				DDRSS3_PHY_22_DATA
-				DDRSS3_PHY_23_DATA
-				DDRSS3_PHY_24_DATA
-				DDRSS3_PHY_25_DATA
-				DDRSS3_PHY_26_DATA
-				DDRSS3_PHY_27_DATA
-				DDRSS3_PHY_28_DATA
-				DDRSS3_PHY_29_DATA
-				DDRSS3_PHY_30_DATA
-				DDRSS3_PHY_31_DATA
-				DDRSS3_PHY_32_DATA
-				DDRSS3_PHY_33_DATA
-				DDRSS3_PHY_34_DATA
-				DDRSS3_PHY_35_DATA
-				DDRSS3_PHY_36_DATA
-				DDRSS3_PHY_37_DATA
-				DDRSS3_PHY_38_DATA
-				DDRSS3_PHY_39_DATA
-				DDRSS3_PHY_40_DATA
-				DDRSS3_PHY_41_DATA
-				DDRSS3_PHY_42_DATA
-				DDRSS3_PHY_43_DATA
-				DDRSS3_PHY_44_DATA
-				DDRSS3_PHY_45_DATA
-				DDRSS3_PHY_46_DATA
-				DDRSS3_PHY_47_DATA
-				DDRSS3_PHY_48_DATA
-				DDRSS3_PHY_49_DATA
-				DDRSS3_PHY_50_DATA
-				DDRSS3_PHY_51_DATA
-				DDRSS3_PHY_52_DATA
-				DDRSS3_PHY_53_DATA
-				DDRSS3_PHY_54_DATA
-				DDRSS3_PHY_55_DATA
-				DDRSS3_PHY_56_DATA
-				DDRSS3_PHY_57_DATA
-				DDRSS3_PHY_58_DATA
-				DDRSS3_PHY_59_DATA
-				DDRSS3_PHY_60_DATA
-				DDRSS3_PHY_61_DATA
-				DDRSS3_PHY_62_DATA
-				DDRSS3_PHY_63_DATA
-				DDRSS3_PHY_64_DATA
-				DDRSS3_PHY_65_DATA
-				DDRSS3_PHY_66_DATA
-				DDRSS3_PHY_67_DATA
-				DDRSS3_PHY_68_DATA
-				DDRSS3_PHY_69_DATA
-				DDRSS3_PHY_70_DATA
-				DDRSS3_PHY_71_DATA
-				DDRSS3_PHY_72_DATA
-				DDRSS3_PHY_73_DATA
-				DDRSS3_PHY_74_DATA
-				DDRSS3_PHY_75_DATA
-				DDRSS3_PHY_76_DATA
-				DDRSS3_PHY_77_DATA
-				DDRSS3_PHY_78_DATA
-				DDRSS3_PHY_79_DATA
-				DDRSS3_PHY_80_DATA
-				DDRSS3_PHY_81_DATA
-				DDRSS3_PHY_82_DATA
-				DDRSS3_PHY_83_DATA
-				DDRSS3_PHY_84_DATA
-				DDRSS3_PHY_85_DATA
-				DDRSS3_PHY_86_DATA
-				DDRSS3_PHY_87_DATA
-				DDRSS3_PHY_88_DATA
-				DDRSS3_PHY_89_DATA
-				DDRSS3_PHY_90_DATA
-				DDRSS3_PHY_91_DATA
-				DDRSS3_PHY_92_DATA
-				DDRSS3_PHY_93_DATA
-				DDRSS3_PHY_94_DATA
-				DDRSS3_PHY_95_DATA
-				DDRSS3_PHY_96_DATA
-				DDRSS3_PHY_97_DATA
-				DDRSS3_PHY_98_DATA
-				DDRSS3_PHY_99_DATA
-				DDRSS3_PHY_100_DATA
-				DDRSS3_PHY_101_DATA
-				DDRSS3_PHY_102_DATA
-				DDRSS3_PHY_103_DATA
-				DDRSS3_PHY_104_DATA
-				DDRSS3_PHY_105_DATA
-				DDRSS3_PHY_106_DATA
-				DDRSS3_PHY_107_DATA
-				DDRSS3_PHY_108_DATA
-				DDRSS3_PHY_109_DATA
-				DDRSS3_PHY_110_DATA
-				DDRSS3_PHY_111_DATA
-				DDRSS3_PHY_112_DATA
-				DDRSS3_PHY_113_DATA
-				DDRSS3_PHY_114_DATA
-				DDRSS3_PHY_115_DATA
-				DDRSS3_PHY_116_DATA
-				DDRSS3_PHY_117_DATA
-				DDRSS3_PHY_118_DATA
-				DDRSS3_PHY_119_DATA
-				DDRSS3_PHY_120_DATA
-				DDRSS3_PHY_121_DATA
-				DDRSS3_PHY_122_DATA
-				DDRSS3_PHY_123_DATA
-				DDRSS3_PHY_124_DATA
-				DDRSS3_PHY_125_DATA
-				DDRSS3_PHY_126_DATA
-				DDRSS3_PHY_127_DATA
-				DDRSS3_PHY_128_DATA
-				DDRSS3_PHY_129_DATA
-				DDRSS3_PHY_130_DATA
-				DDRSS3_PHY_131_DATA
-				DDRSS3_PHY_132_DATA
-				DDRSS3_PHY_133_DATA
-				DDRSS3_PHY_134_DATA
-				DDRSS3_PHY_135_DATA
-				DDRSS3_PHY_136_DATA
-				DDRSS3_PHY_137_DATA
-				DDRSS3_PHY_138_DATA
-				DDRSS3_PHY_139_DATA
-				DDRSS3_PHY_140_DATA
-				DDRSS3_PHY_141_DATA
-				DDRSS3_PHY_142_DATA
-				DDRSS3_PHY_143_DATA
-				DDRSS3_PHY_144_DATA
-				DDRSS3_PHY_145_DATA
-				DDRSS3_PHY_146_DATA
-				DDRSS3_PHY_147_DATA
-				DDRSS3_PHY_148_DATA
-				DDRSS3_PHY_149_DATA
-				DDRSS3_PHY_150_DATA
-				DDRSS3_PHY_151_DATA
-				DDRSS3_PHY_152_DATA
-				DDRSS3_PHY_153_DATA
-				DDRSS3_PHY_154_DATA
-				DDRSS3_PHY_155_DATA
-				DDRSS3_PHY_156_DATA
-				DDRSS3_PHY_157_DATA
-				DDRSS3_PHY_158_DATA
-				DDRSS3_PHY_159_DATA
-				DDRSS3_PHY_160_DATA
-				DDRSS3_PHY_161_DATA
-				DDRSS3_PHY_162_DATA
-				DDRSS3_PHY_163_DATA
-				DDRSS3_PHY_164_DATA
-				DDRSS3_PHY_165_DATA
-				DDRSS3_PHY_166_DATA
-				DDRSS3_PHY_167_DATA
-				DDRSS3_PHY_168_DATA
-				DDRSS3_PHY_169_DATA
-				DDRSS3_PHY_170_DATA
-				DDRSS3_PHY_171_DATA
-				DDRSS3_PHY_172_DATA
-				DDRSS3_PHY_173_DATA
-				DDRSS3_PHY_174_DATA
-				DDRSS3_PHY_175_DATA
-				DDRSS3_PHY_176_DATA
-				DDRSS3_PHY_177_DATA
-				DDRSS3_PHY_178_DATA
-				DDRSS3_PHY_179_DATA
-				DDRSS3_PHY_180_DATA
-				DDRSS3_PHY_181_DATA
-				DDRSS3_PHY_182_DATA
-				DDRSS3_PHY_183_DATA
-				DDRSS3_PHY_184_DATA
-				DDRSS3_PHY_185_DATA
-				DDRSS3_PHY_186_DATA
-				DDRSS3_PHY_187_DATA
-				DDRSS3_PHY_188_DATA
-				DDRSS3_PHY_189_DATA
-				DDRSS3_PHY_190_DATA
-				DDRSS3_PHY_191_DATA
-				DDRSS3_PHY_192_DATA
-				DDRSS3_PHY_193_DATA
-				DDRSS3_PHY_194_DATA
-				DDRSS3_PHY_195_DATA
-				DDRSS3_PHY_196_DATA
-				DDRSS3_PHY_197_DATA
-				DDRSS3_PHY_198_DATA
-				DDRSS3_PHY_199_DATA
-				DDRSS3_PHY_200_DATA
-				DDRSS3_PHY_201_DATA
-				DDRSS3_PHY_202_DATA
-				DDRSS3_PHY_203_DATA
-				DDRSS3_PHY_204_DATA
-				DDRSS3_PHY_205_DATA
-				DDRSS3_PHY_206_DATA
-				DDRSS3_PHY_207_DATA
-				DDRSS3_PHY_208_DATA
-				DDRSS3_PHY_209_DATA
-				DDRSS3_PHY_210_DATA
-				DDRSS3_PHY_211_DATA
-				DDRSS3_PHY_212_DATA
-				DDRSS3_PHY_213_DATA
-				DDRSS3_PHY_214_DATA
-				DDRSS3_PHY_215_DATA
-				DDRSS3_PHY_216_DATA
-				DDRSS3_PHY_217_DATA
-				DDRSS3_PHY_218_DATA
-				DDRSS3_PHY_219_DATA
-				DDRSS3_PHY_220_DATA
-				DDRSS3_PHY_221_DATA
-				DDRSS3_PHY_222_DATA
-				DDRSS3_PHY_223_DATA
-				DDRSS3_PHY_224_DATA
-				DDRSS3_PHY_225_DATA
-				DDRSS3_PHY_226_DATA
-				DDRSS3_PHY_227_DATA
-				DDRSS3_PHY_228_DATA
-				DDRSS3_PHY_229_DATA
-				DDRSS3_PHY_230_DATA
-				DDRSS3_PHY_231_DATA
-				DDRSS3_PHY_232_DATA
-				DDRSS3_PHY_233_DATA
-				DDRSS3_PHY_234_DATA
-				DDRSS3_PHY_235_DATA
-				DDRSS3_PHY_236_DATA
-				DDRSS3_PHY_237_DATA
-				DDRSS3_PHY_238_DATA
-				DDRSS3_PHY_239_DATA
-				DDRSS3_PHY_240_DATA
-				DDRSS3_PHY_241_DATA
-				DDRSS3_PHY_242_DATA
-				DDRSS3_PHY_243_DATA
-				DDRSS3_PHY_244_DATA
-				DDRSS3_PHY_245_DATA
-				DDRSS3_PHY_246_DATA
-				DDRSS3_PHY_247_DATA
-				DDRSS3_PHY_248_DATA
-				DDRSS3_PHY_249_DATA
-				DDRSS3_PHY_250_DATA
-				DDRSS3_PHY_251_DATA
-				DDRSS3_PHY_252_DATA
-				DDRSS3_PHY_253_DATA
-				DDRSS3_PHY_254_DATA
-				DDRSS3_PHY_255_DATA
-				DDRSS3_PHY_256_DATA
-				DDRSS3_PHY_257_DATA
-				DDRSS3_PHY_258_DATA
-				DDRSS3_PHY_259_DATA
-				DDRSS3_PHY_260_DATA
-				DDRSS3_PHY_261_DATA
-				DDRSS3_PHY_262_DATA
-				DDRSS3_PHY_263_DATA
-				DDRSS3_PHY_264_DATA
-				DDRSS3_PHY_265_DATA
-				DDRSS3_PHY_266_DATA
-				DDRSS3_PHY_267_DATA
-				DDRSS3_PHY_268_DATA
-				DDRSS3_PHY_269_DATA
-				DDRSS3_PHY_270_DATA
-				DDRSS3_PHY_271_DATA
-				DDRSS3_PHY_272_DATA
-				DDRSS3_PHY_273_DATA
-				DDRSS3_PHY_274_DATA
-				DDRSS3_PHY_275_DATA
-				DDRSS3_PHY_276_DATA
-				DDRSS3_PHY_277_DATA
-				DDRSS3_PHY_278_DATA
-				DDRSS3_PHY_279_DATA
-				DDRSS3_PHY_280_DATA
-				DDRSS3_PHY_281_DATA
-				DDRSS3_PHY_282_DATA
-				DDRSS3_PHY_283_DATA
-				DDRSS3_PHY_284_DATA
-				DDRSS3_PHY_285_DATA
-				DDRSS3_PHY_286_DATA
-				DDRSS3_PHY_287_DATA
-				DDRSS3_PHY_288_DATA
-				DDRSS3_PHY_289_DATA
-				DDRSS3_PHY_290_DATA
-				DDRSS3_PHY_291_DATA
-				DDRSS3_PHY_292_DATA
-				DDRSS3_PHY_293_DATA
-				DDRSS3_PHY_294_DATA
-				DDRSS3_PHY_295_DATA
-				DDRSS3_PHY_296_DATA
-				DDRSS3_PHY_297_DATA
-				DDRSS3_PHY_298_DATA
-				DDRSS3_PHY_299_DATA
-				DDRSS3_PHY_300_DATA
-				DDRSS3_PHY_301_DATA
-				DDRSS3_PHY_302_DATA
-				DDRSS3_PHY_303_DATA
-				DDRSS3_PHY_304_DATA
-				DDRSS3_PHY_305_DATA
-				DDRSS3_PHY_306_DATA
-				DDRSS3_PHY_307_DATA
-				DDRSS3_PHY_308_DATA
-				DDRSS3_PHY_309_DATA
-				DDRSS3_PHY_310_DATA
-				DDRSS3_PHY_311_DATA
-				DDRSS3_PHY_312_DATA
-				DDRSS3_PHY_313_DATA
-				DDRSS3_PHY_314_DATA
-				DDRSS3_PHY_315_DATA
-				DDRSS3_PHY_316_DATA
-				DDRSS3_PHY_317_DATA
-				DDRSS3_PHY_318_DATA
-				DDRSS3_PHY_319_DATA
-				DDRSS3_PHY_320_DATA
-				DDRSS3_PHY_321_DATA
-				DDRSS3_PHY_322_DATA
-				DDRSS3_PHY_323_DATA
-				DDRSS3_PHY_324_DATA
-				DDRSS3_PHY_325_DATA
-				DDRSS3_PHY_326_DATA
-				DDRSS3_PHY_327_DATA
-				DDRSS3_PHY_328_DATA
-				DDRSS3_PHY_329_DATA
-				DDRSS3_PHY_330_DATA
-				DDRSS3_PHY_331_DATA
-				DDRSS3_PHY_332_DATA
-				DDRSS3_PHY_333_DATA
-				DDRSS3_PHY_334_DATA
-				DDRSS3_PHY_335_DATA
-				DDRSS3_PHY_336_DATA
-				DDRSS3_PHY_337_DATA
-				DDRSS3_PHY_338_DATA
-				DDRSS3_PHY_339_DATA
-				DDRSS3_PHY_340_DATA
-				DDRSS3_PHY_341_DATA
-				DDRSS3_PHY_342_DATA
-				DDRSS3_PHY_343_DATA
-				DDRSS3_PHY_344_DATA
-				DDRSS3_PHY_345_DATA
-				DDRSS3_PHY_346_DATA
-				DDRSS3_PHY_347_DATA
-				DDRSS3_PHY_348_DATA
-				DDRSS3_PHY_349_DATA
-				DDRSS3_PHY_350_DATA
-				DDRSS3_PHY_351_DATA
-				DDRSS3_PHY_352_DATA
-				DDRSS3_PHY_353_DATA
-				DDRSS3_PHY_354_DATA
-				DDRSS3_PHY_355_DATA
-				DDRSS3_PHY_356_DATA
-				DDRSS3_PHY_357_DATA
-				DDRSS3_PHY_358_DATA
-				DDRSS3_PHY_359_DATA
-				DDRSS3_PHY_360_DATA
-				DDRSS3_PHY_361_DATA
-				DDRSS3_PHY_362_DATA
-				DDRSS3_PHY_363_DATA
-				DDRSS3_PHY_364_DATA
-				DDRSS3_PHY_365_DATA
-				DDRSS3_PHY_366_DATA
-				DDRSS3_PHY_367_DATA
-				DDRSS3_PHY_368_DATA
-				DDRSS3_PHY_369_DATA
-				DDRSS3_PHY_370_DATA
-				DDRSS3_PHY_371_DATA
-				DDRSS3_PHY_372_DATA
-				DDRSS3_PHY_373_DATA
-				DDRSS3_PHY_374_DATA
-				DDRSS3_PHY_375_DATA
-				DDRSS3_PHY_376_DATA
-				DDRSS3_PHY_377_DATA
-				DDRSS3_PHY_378_DATA
-				DDRSS3_PHY_379_DATA
-				DDRSS3_PHY_380_DATA
-				DDRSS3_PHY_381_DATA
-				DDRSS3_PHY_382_DATA
-				DDRSS3_PHY_383_DATA
-				DDRSS3_PHY_384_DATA
-				DDRSS3_PHY_385_DATA
-				DDRSS3_PHY_386_DATA
-				DDRSS3_PHY_387_DATA
-				DDRSS3_PHY_388_DATA
-				DDRSS3_PHY_389_DATA
-				DDRSS3_PHY_390_DATA
-				DDRSS3_PHY_391_DATA
-				DDRSS3_PHY_392_DATA
-				DDRSS3_PHY_393_DATA
-				DDRSS3_PHY_394_DATA
-				DDRSS3_PHY_395_DATA
-				DDRSS3_PHY_396_DATA
-				DDRSS3_PHY_397_DATA
-				DDRSS3_PHY_398_DATA
-				DDRSS3_PHY_399_DATA
-				DDRSS3_PHY_400_DATA
-				DDRSS3_PHY_401_DATA
-				DDRSS3_PHY_402_DATA
-				DDRSS3_PHY_403_DATA
-				DDRSS3_PHY_404_DATA
-				DDRSS3_PHY_405_DATA
-				DDRSS3_PHY_406_DATA
-				DDRSS3_PHY_407_DATA
-				DDRSS3_PHY_408_DATA
-				DDRSS3_PHY_409_DATA
-				DDRSS3_PHY_410_DATA
-				DDRSS3_PHY_411_DATA
-				DDRSS3_PHY_412_DATA
-				DDRSS3_PHY_413_DATA
-				DDRSS3_PHY_414_DATA
-				DDRSS3_PHY_415_DATA
-				DDRSS3_PHY_416_DATA
-				DDRSS3_PHY_417_DATA
-				DDRSS3_PHY_418_DATA
-				DDRSS3_PHY_419_DATA
-				DDRSS3_PHY_420_DATA
-				DDRSS3_PHY_421_DATA
-				DDRSS3_PHY_422_DATA
-				DDRSS3_PHY_423_DATA
-				DDRSS3_PHY_424_DATA
-				DDRSS3_PHY_425_DATA
-				DDRSS3_PHY_426_DATA
-				DDRSS3_PHY_427_DATA
-				DDRSS3_PHY_428_DATA
-				DDRSS3_PHY_429_DATA
-				DDRSS3_PHY_430_DATA
-				DDRSS3_PHY_431_DATA
-				DDRSS3_PHY_432_DATA
-				DDRSS3_PHY_433_DATA
-				DDRSS3_PHY_434_DATA
-				DDRSS3_PHY_435_DATA
-				DDRSS3_PHY_436_DATA
-				DDRSS3_PHY_437_DATA
-				DDRSS3_PHY_438_DATA
-				DDRSS3_PHY_439_DATA
-				DDRSS3_PHY_440_DATA
-				DDRSS3_PHY_441_DATA
-				DDRSS3_PHY_442_DATA
-				DDRSS3_PHY_443_DATA
-				DDRSS3_PHY_444_DATA
-				DDRSS3_PHY_445_DATA
-				DDRSS3_PHY_446_DATA
-				DDRSS3_PHY_447_DATA
-				DDRSS3_PHY_448_DATA
-				DDRSS3_PHY_449_DATA
-				DDRSS3_PHY_450_DATA
-				DDRSS3_PHY_451_DATA
-				DDRSS3_PHY_452_DATA
-				DDRSS3_PHY_453_DATA
-				DDRSS3_PHY_454_DATA
-				DDRSS3_PHY_455_DATA
-				DDRSS3_PHY_456_DATA
-				DDRSS3_PHY_457_DATA
-				DDRSS3_PHY_458_DATA
-				DDRSS3_PHY_459_DATA
-				DDRSS3_PHY_460_DATA
-				DDRSS3_PHY_461_DATA
-				DDRSS3_PHY_462_DATA
-				DDRSS3_PHY_463_DATA
-				DDRSS3_PHY_464_DATA
-				DDRSS3_PHY_465_DATA
-				DDRSS3_PHY_466_DATA
-				DDRSS3_PHY_467_DATA
-				DDRSS3_PHY_468_DATA
-				DDRSS3_PHY_469_DATA
-				DDRSS3_PHY_470_DATA
-				DDRSS3_PHY_471_DATA
-				DDRSS3_PHY_472_DATA
-				DDRSS3_PHY_473_DATA
-				DDRSS3_PHY_474_DATA
-				DDRSS3_PHY_475_DATA
-				DDRSS3_PHY_476_DATA
-				DDRSS3_PHY_477_DATA
-				DDRSS3_PHY_478_DATA
-				DDRSS3_PHY_479_DATA
-				DDRSS3_PHY_480_DATA
-				DDRSS3_PHY_481_DATA
-				DDRSS3_PHY_482_DATA
-				DDRSS3_PHY_483_DATA
-				DDRSS3_PHY_484_DATA
-				DDRSS3_PHY_485_DATA
-				DDRSS3_PHY_486_DATA
-				DDRSS3_PHY_487_DATA
-				DDRSS3_PHY_488_DATA
-				DDRSS3_PHY_489_DATA
-				DDRSS3_PHY_490_DATA
-				DDRSS3_PHY_491_DATA
-				DDRSS3_PHY_492_DATA
-				DDRSS3_PHY_493_DATA
-				DDRSS3_PHY_494_DATA
-				DDRSS3_PHY_495_DATA
-				DDRSS3_PHY_496_DATA
-				DDRSS3_PHY_497_DATA
-				DDRSS3_PHY_498_DATA
-				DDRSS3_PHY_499_DATA
-				DDRSS3_PHY_500_DATA
-				DDRSS3_PHY_501_DATA
-				DDRSS3_PHY_502_DATA
-				DDRSS3_PHY_503_DATA
-				DDRSS3_PHY_504_DATA
-				DDRSS3_PHY_505_DATA
-				DDRSS3_PHY_506_DATA
-				DDRSS3_PHY_507_DATA
-				DDRSS3_PHY_508_DATA
-				DDRSS3_PHY_509_DATA
-				DDRSS3_PHY_510_DATA
-				DDRSS3_PHY_511_DATA
-				DDRSS3_PHY_512_DATA
-				DDRSS3_PHY_513_DATA
-				DDRSS3_PHY_514_DATA
-				DDRSS3_PHY_515_DATA
-				DDRSS3_PHY_516_DATA
-				DDRSS3_PHY_517_DATA
-				DDRSS3_PHY_518_DATA
-				DDRSS3_PHY_519_DATA
-				DDRSS3_PHY_520_DATA
-				DDRSS3_PHY_521_DATA
-				DDRSS3_PHY_522_DATA
-				DDRSS3_PHY_523_DATA
-				DDRSS3_PHY_524_DATA
-				DDRSS3_PHY_525_DATA
-				DDRSS3_PHY_526_DATA
-				DDRSS3_PHY_527_DATA
-				DDRSS3_PHY_528_DATA
-				DDRSS3_PHY_529_DATA
-				DDRSS3_PHY_530_DATA
-				DDRSS3_PHY_531_DATA
-				DDRSS3_PHY_532_DATA
-				DDRSS3_PHY_533_DATA
-				DDRSS3_PHY_534_DATA
-				DDRSS3_PHY_535_DATA
-				DDRSS3_PHY_536_DATA
-				DDRSS3_PHY_537_DATA
-				DDRSS3_PHY_538_DATA
-				DDRSS3_PHY_539_DATA
-				DDRSS3_PHY_540_DATA
-				DDRSS3_PHY_541_DATA
-				DDRSS3_PHY_542_DATA
-				DDRSS3_PHY_543_DATA
-				DDRSS3_PHY_544_DATA
-				DDRSS3_PHY_545_DATA
-				DDRSS3_PHY_546_DATA
-				DDRSS3_PHY_547_DATA
-				DDRSS3_PHY_548_DATA
-				DDRSS3_PHY_549_DATA
-				DDRSS3_PHY_550_DATA
-				DDRSS3_PHY_551_DATA
-				DDRSS3_PHY_552_DATA
-				DDRSS3_PHY_553_DATA
-				DDRSS3_PHY_554_DATA
-				DDRSS3_PHY_555_DATA
-				DDRSS3_PHY_556_DATA
-				DDRSS3_PHY_557_DATA
-				DDRSS3_PHY_558_DATA
-				DDRSS3_PHY_559_DATA
-				DDRSS3_PHY_560_DATA
-				DDRSS3_PHY_561_DATA
-				DDRSS3_PHY_562_DATA
-				DDRSS3_PHY_563_DATA
-				DDRSS3_PHY_564_DATA
-				DDRSS3_PHY_565_DATA
-				DDRSS3_PHY_566_DATA
-				DDRSS3_PHY_567_DATA
-				DDRSS3_PHY_568_DATA
-				DDRSS3_PHY_569_DATA
-				DDRSS3_PHY_570_DATA
-				DDRSS3_PHY_571_DATA
-				DDRSS3_PHY_572_DATA
-				DDRSS3_PHY_573_DATA
-				DDRSS3_PHY_574_DATA
-				DDRSS3_PHY_575_DATA
-				DDRSS3_PHY_576_DATA
-				DDRSS3_PHY_577_DATA
-				DDRSS3_PHY_578_DATA
-				DDRSS3_PHY_579_DATA
-				DDRSS3_PHY_580_DATA
-				DDRSS3_PHY_581_DATA
-				DDRSS3_PHY_582_DATA
-				DDRSS3_PHY_583_DATA
-				DDRSS3_PHY_584_DATA
-				DDRSS3_PHY_585_DATA
-				DDRSS3_PHY_586_DATA
-				DDRSS3_PHY_587_DATA
-				DDRSS3_PHY_588_DATA
-				DDRSS3_PHY_589_DATA
-				DDRSS3_PHY_590_DATA
-				DDRSS3_PHY_591_DATA
-				DDRSS3_PHY_592_DATA
-				DDRSS3_PHY_593_DATA
-				DDRSS3_PHY_594_DATA
-				DDRSS3_PHY_595_DATA
-				DDRSS3_PHY_596_DATA
-				DDRSS3_PHY_597_DATA
-				DDRSS3_PHY_598_DATA
-				DDRSS3_PHY_599_DATA
-				DDRSS3_PHY_600_DATA
-				DDRSS3_PHY_601_DATA
-				DDRSS3_PHY_602_DATA
-				DDRSS3_PHY_603_DATA
-				DDRSS3_PHY_604_DATA
-				DDRSS3_PHY_605_DATA
-				DDRSS3_PHY_606_DATA
-				DDRSS3_PHY_607_DATA
-				DDRSS3_PHY_608_DATA
-				DDRSS3_PHY_609_DATA
-				DDRSS3_PHY_610_DATA
-				DDRSS3_PHY_611_DATA
-				DDRSS3_PHY_612_DATA
-				DDRSS3_PHY_613_DATA
-				DDRSS3_PHY_614_DATA
-				DDRSS3_PHY_615_DATA
-				DDRSS3_PHY_616_DATA
-				DDRSS3_PHY_617_DATA
-				DDRSS3_PHY_618_DATA
-				DDRSS3_PHY_619_DATA
-				DDRSS3_PHY_620_DATA
-				DDRSS3_PHY_621_DATA
-				DDRSS3_PHY_622_DATA
-				DDRSS3_PHY_623_DATA
-				DDRSS3_PHY_624_DATA
-				DDRSS3_PHY_625_DATA
-				DDRSS3_PHY_626_DATA
-				DDRSS3_PHY_627_DATA
-				DDRSS3_PHY_628_DATA
-				DDRSS3_PHY_629_DATA
-				DDRSS3_PHY_630_DATA
-				DDRSS3_PHY_631_DATA
-				DDRSS3_PHY_632_DATA
-				DDRSS3_PHY_633_DATA
-				DDRSS3_PHY_634_DATA
-				DDRSS3_PHY_635_DATA
-				DDRSS3_PHY_636_DATA
-				DDRSS3_PHY_637_DATA
-				DDRSS3_PHY_638_DATA
-				DDRSS3_PHY_639_DATA
-				DDRSS3_PHY_640_DATA
-				DDRSS3_PHY_641_DATA
-				DDRSS3_PHY_642_DATA
-				DDRSS3_PHY_643_DATA
-				DDRSS3_PHY_644_DATA
-				DDRSS3_PHY_645_DATA
-				DDRSS3_PHY_646_DATA
-				DDRSS3_PHY_647_DATA
-				DDRSS3_PHY_648_DATA
-				DDRSS3_PHY_649_DATA
-				DDRSS3_PHY_650_DATA
-				DDRSS3_PHY_651_DATA
-				DDRSS3_PHY_652_DATA
-				DDRSS3_PHY_653_DATA
-				DDRSS3_PHY_654_DATA
-				DDRSS3_PHY_655_DATA
-				DDRSS3_PHY_656_DATA
-				DDRSS3_PHY_657_DATA
-				DDRSS3_PHY_658_DATA
-				DDRSS3_PHY_659_DATA
-				DDRSS3_PHY_660_DATA
-				DDRSS3_PHY_661_DATA
-				DDRSS3_PHY_662_DATA
-				DDRSS3_PHY_663_DATA
-				DDRSS3_PHY_664_DATA
-				DDRSS3_PHY_665_DATA
-				DDRSS3_PHY_666_DATA
-				DDRSS3_PHY_667_DATA
-				DDRSS3_PHY_668_DATA
-				DDRSS3_PHY_669_DATA
-				DDRSS3_PHY_670_DATA
-				DDRSS3_PHY_671_DATA
-				DDRSS3_PHY_672_DATA
-				DDRSS3_PHY_673_DATA
-				DDRSS3_PHY_674_DATA
-				DDRSS3_PHY_675_DATA
-				DDRSS3_PHY_676_DATA
-				DDRSS3_PHY_677_DATA
-				DDRSS3_PHY_678_DATA
-				DDRSS3_PHY_679_DATA
-				DDRSS3_PHY_680_DATA
-				DDRSS3_PHY_681_DATA
-				DDRSS3_PHY_682_DATA
-				DDRSS3_PHY_683_DATA
-				DDRSS3_PHY_684_DATA
-				DDRSS3_PHY_685_DATA
-				DDRSS3_PHY_686_DATA
-				DDRSS3_PHY_687_DATA
-				DDRSS3_PHY_688_DATA
-				DDRSS3_PHY_689_DATA
-				DDRSS3_PHY_690_DATA
-				DDRSS3_PHY_691_DATA
-				DDRSS3_PHY_692_DATA
-				DDRSS3_PHY_693_DATA
-				DDRSS3_PHY_694_DATA
-				DDRSS3_PHY_695_DATA
-				DDRSS3_PHY_696_DATA
-				DDRSS3_PHY_697_DATA
-				DDRSS3_PHY_698_DATA
-				DDRSS3_PHY_699_DATA
-				DDRSS3_PHY_700_DATA
-				DDRSS3_PHY_701_DATA
-				DDRSS3_PHY_702_DATA
-				DDRSS3_PHY_703_DATA
-				DDRSS3_PHY_704_DATA
-				DDRSS3_PHY_705_DATA
-				DDRSS3_PHY_706_DATA
-				DDRSS3_PHY_707_DATA
-				DDRSS3_PHY_708_DATA
-				DDRSS3_PHY_709_DATA
-				DDRSS3_PHY_710_DATA
-				DDRSS3_PHY_711_DATA
-				DDRSS3_PHY_712_DATA
-				DDRSS3_PHY_713_DATA
-				DDRSS3_PHY_714_DATA
-				DDRSS3_PHY_715_DATA
-				DDRSS3_PHY_716_DATA
-				DDRSS3_PHY_717_DATA
-				DDRSS3_PHY_718_DATA
-				DDRSS3_PHY_719_DATA
-				DDRSS3_PHY_720_DATA
-				DDRSS3_PHY_721_DATA
-				DDRSS3_PHY_722_DATA
-				DDRSS3_PHY_723_DATA
-				DDRSS3_PHY_724_DATA
-				DDRSS3_PHY_725_DATA
-				DDRSS3_PHY_726_DATA
-				DDRSS3_PHY_727_DATA
-				DDRSS3_PHY_728_DATA
-				DDRSS3_PHY_729_DATA
-				DDRSS3_PHY_730_DATA
-				DDRSS3_PHY_731_DATA
-				DDRSS3_PHY_732_DATA
-				DDRSS3_PHY_733_DATA
-				DDRSS3_PHY_734_DATA
-				DDRSS3_PHY_735_DATA
-				DDRSS3_PHY_736_DATA
-				DDRSS3_PHY_737_DATA
-				DDRSS3_PHY_738_DATA
-				DDRSS3_PHY_739_DATA
-				DDRSS3_PHY_740_DATA
-				DDRSS3_PHY_741_DATA
-				DDRSS3_PHY_742_DATA
-				DDRSS3_PHY_743_DATA
-				DDRSS3_PHY_744_DATA
-				DDRSS3_PHY_745_DATA
-				DDRSS3_PHY_746_DATA
-				DDRSS3_PHY_747_DATA
-				DDRSS3_PHY_748_DATA
-				DDRSS3_PHY_749_DATA
-				DDRSS3_PHY_750_DATA
-				DDRSS3_PHY_751_DATA
-				DDRSS3_PHY_752_DATA
-				DDRSS3_PHY_753_DATA
-				DDRSS3_PHY_754_DATA
-				DDRSS3_PHY_755_DATA
-				DDRSS3_PHY_756_DATA
-				DDRSS3_PHY_757_DATA
-				DDRSS3_PHY_758_DATA
-				DDRSS3_PHY_759_DATA
-				DDRSS3_PHY_760_DATA
-				DDRSS3_PHY_761_DATA
-				DDRSS3_PHY_762_DATA
-				DDRSS3_PHY_763_DATA
-				DDRSS3_PHY_764_DATA
-				DDRSS3_PHY_765_DATA
-				DDRSS3_PHY_766_DATA
-				DDRSS3_PHY_767_DATA
-				DDRSS3_PHY_768_DATA
-				DDRSS3_PHY_769_DATA
-				DDRSS3_PHY_770_DATA
-				DDRSS3_PHY_771_DATA
-				DDRSS3_PHY_772_DATA
-				DDRSS3_PHY_773_DATA
-				DDRSS3_PHY_774_DATA
-				DDRSS3_PHY_775_DATA
-				DDRSS3_PHY_776_DATA
-				DDRSS3_PHY_777_DATA
-				DDRSS3_PHY_778_DATA
-				DDRSS3_PHY_779_DATA
-				DDRSS3_PHY_780_DATA
-				DDRSS3_PHY_781_DATA
-				DDRSS3_PHY_782_DATA
-				DDRSS3_PHY_783_DATA
-				DDRSS3_PHY_784_DATA
-				DDRSS3_PHY_785_DATA
-				DDRSS3_PHY_786_DATA
-				DDRSS3_PHY_787_DATA
-				DDRSS3_PHY_788_DATA
-				DDRSS3_PHY_789_DATA
-				DDRSS3_PHY_790_DATA
-				DDRSS3_PHY_791_DATA
-				DDRSS3_PHY_792_DATA
-				DDRSS3_PHY_793_DATA
-				DDRSS3_PHY_794_DATA
-				DDRSS3_PHY_795_DATA
-				DDRSS3_PHY_796_DATA
-				DDRSS3_PHY_797_DATA
-				DDRSS3_PHY_798_DATA
-				DDRSS3_PHY_799_DATA
-				DDRSS3_PHY_800_DATA
-				DDRSS3_PHY_801_DATA
-				DDRSS3_PHY_802_DATA
-				DDRSS3_PHY_803_DATA
-				DDRSS3_PHY_804_DATA
-				DDRSS3_PHY_805_DATA
-				DDRSS3_PHY_806_DATA
-				DDRSS3_PHY_807_DATA
-				DDRSS3_PHY_808_DATA
-				DDRSS3_PHY_809_DATA
-				DDRSS3_PHY_810_DATA
-				DDRSS3_PHY_811_DATA
-				DDRSS3_PHY_812_DATA
-				DDRSS3_PHY_813_DATA
-				DDRSS3_PHY_814_DATA
-				DDRSS3_PHY_815_DATA
-				DDRSS3_PHY_816_DATA
-				DDRSS3_PHY_817_DATA
-				DDRSS3_PHY_818_DATA
-				DDRSS3_PHY_819_DATA
-				DDRSS3_PHY_820_DATA
-				DDRSS3_PHY_821_DATA
-				DDRSS3_PHY_822_DATA
-				DDRSS3_PHY_823_DATA
-				DDRSS3_PHY_824_DATA
-				DDRSS3_PHY_825_DATA
-				DDRSS3_PHY_826_DATA
-				DDRSS3_PHY_827_DATA
-				DDRSS3_PHY_828_DATA
-				DDRSS3_PHY_829_DATA
-				DDRSS3_PHY_830_DATA
-				DDRSS3_PHY_831_DATA
-				DDRSS3_PHY_832_DATA
-				DDRSS3_PHY_833_DATA
-				DDRSS3_PHY_834_DATA
-				DDRSS3_PHY_835_DATA
-				DDRSS3_PHY_836_DATA
-				DDRSS3_PHY_837_DATA
-				DDRSS3_PHY_838_DATA
-				DDRSS3_PHY_839_DATA
-				DDRSS3_PHY_840_DATA
-				DDRSS3_PHY_841_DATA
-				DDRSS3_PHY_842_DATA
-				DDRSS3_PHY_843_DATA
-				DDRSS3_PHY_844_DATA
-				DDRSS3_PHY_845_DATA
-				DDRSS3_PHY_846_DATA
-				DDRSS3_PHY_847_DATA
-				DDRSS3_PHY_848_DATA
-				DDRSS3_PHY_849_DATA
-				DDRSS3_PHY_850_DATA
-				DDRSS3_PHY_851_DATA
-				DDRSS3_PHY_852_DATA
-				DDRSS3_PHY_853_DATA
-				DDRSS3_PHY_854_DATA
-				DDRSS3_PHY_855_DATA
-				DDRSS3_PHY_856_DATA
-				DDRSS3_PHY_857_DATA
-				DDRSS3_PHY_858_DATA
-				DDRSS3_PHY_859_DATA
-				DDRSS3_PHY_860_DATA
-				DDRSS3_PHY_861_DATA
-				DDRSS3_PHY_862_DATA
-				DDRSS3_PHY_863_DATA
-				DDRSS3_PHY_864_DATA
-				DDRSS3_PHY_865_DATA
-				DDRSS3_PHY_866_DATA
-				DDRSS3_PHY_867_DATA
-				DDRSS3_PHY_868_DATA
-				DDRSS3_PHY_869_DATA
-				DDRSS3_PHY_870_DATA
-				DDRSS3_PHY_871_DATA
-				DDRSS3_PHY_872_DATA
-				DDRSS3_PHY_873_DATA
-				DDRSS3_PHY_874_DATA
-				DDRSS3_PHY_875_DATA
-				DDRSS3_PHY_876_DATA
-				DDRSS3_PHY_877_DATA
-				DDRSS3_PHY_878_DATA
-				DDRSS3_PHY_879_DATA
-				DDRSS3_PHY_880_DATA
-				DDRSS3_PHY_881_DATA
-				DDRSS3_PHY_882_DATA
-				DDRSS3_PHY_883_DATA
-				DDRSS3_PHY_884_DATA
-				DDRSS3_PHY_885_DATA
-				DDRSS3_PHY_886_DATA
-				DDRSS3_PHY_887_DATA
-				DDRSS3_PHY_888_DATA
-				DDRSS3_PHY_889_DATA
-				DDRSS3_PHY_890_DATA
-				DDRSS3_PHY_891_DATA
-				DDRSS3_PHY_892_DATA
-				DDRSS3_PHY_893_DATA
-				DDRSS3_PHY_894_DATA
-				DDRSS3_PHY_895_DATA
-				DDRSS3_PHY_896_DATA
-				DDRSS3_PHY_897_DATA
-				DDRSS3_PHY_898_DATA
-				DDRSS3_PHY_899_DATA
-				DDRSS3_PHY_900_DATA
-				DDRSS3_PHY_901_DATA
-				DDRSS3_PHY_902_DATA
-				DDRSS3_PHY_903_DATA
-				DDRSS3_PHY_904_DATA
-				DDRSS3_PHY_905_DATA
-				DDRSS3_PHY_906_DATA
-				DDRSS3_PHY_907_DATA
-				DDRSS3_PHY_908_DATA
-				DDRSS3_PHY_909_DATA
-				DDRSS3_PHY_910_DATA
-				DDRSS3_PHY_911_DATA
-				DDRSS3_PHY_912_DATA
-				DDRSS3_PHY_913_DATA
-				DDRSS3_PHY_914_DATA
-				DDRSS3_PHY_915_DATA
-				DDRSS3_PHY_916_DATA
-				DDRSS3_PHY_917_DATA
-				DDRSS3_PHY_918_DATA
-				DDRSS3_PHY_919_DATA
-				DDRSS3_PHY_920_DATA
-				DDRSS3_PHY_921_DATA
-				DDRSS3_PHY_922_DATA
-				DDRSS3_PHY_923_DATA
-				DDRSS3_PHY_924_DATA
-				DDRSS3_PHY_925_DATA
-				DDRSS3_PHY_926_DATA
-				DDRSS3_PHY_927_DATA
-				DDRSS3_PHY_928_DATA
-				DDRSS3_PHY_929_DATA
-				DDRSS3_PHY_930_DATA
-				DDRSS3_PHY_931_DATA
-				DDRSS3_PHY_932_DATA
-				DDRSS3_PHY_933_DATA
-				DDRSS3_PHY_934_DATA
-				DDRSS3_PHY_935_DATA
-				DDRSS3_PHY_936_DATA
-				DDRSS3_PHY_937_DATA
-				DDRSS3_PHY_938_DATA
-				DDRSS3_PHY_939_DATA
-				DDRSS3_PHY_940_DATA
-				DDRSS3_PHY_941_DATA
-				DDRSS3_PHY_942_DATA
-				DDRSS3_PHY_943_DATA
-				DDRSS3_PHY_944_DATA
-				DDRSS3_PHY_945_DATA
-				DDRSS3_PHY_946_DATA
-				DDRSS3_PHY_947_DATA
-				DDRSS3_PHY_948_DATA
-				DDRSS3_PHY_949_DATA
-				DDRSS3_PHY_950_DATA
-				DDRSS3_PHY_951_DATA
-				DDRSS3_PHY_952_DATA
-				DDRSS3_PHY_953_DATA
-				DDRSS3_PHY_954_DATA
-				DDRSS3_PHY_955_DATA
-				DDRSS3_PHY_956_DATA
-				DDRSS3_PHY_957_DATA
-				DDRSS3_PHY_958_DATA
-				DDRSS3_PHY_959_DATA
-				DDRSS3_PHY_960_DATA
-				DDRSS3_PHY_961_DATA
-				DDRSS3_PHY_962_DATA
-				DDRSS3_PHY_963_DATA
-				DDRSS3_PHY_964_DATA
-				DDRSS3_PHY_965_DATA
-				DDRSS3_PHY_966_DATA
-				DDRSS3_PHY_967_DATA
-				DDRSS3_PHY_968_DATA
-				DDRSS3_PHY_969_DATA
-				DDRSS3_PHY_970_DATA
-				DDRSS3_PHY_971_DATA
-				DDRSS3_PHY_972_DATA
-				DDRSS3_PHY_973_DATA
-				DDRSS3_PHY_974_DATA
-				DDRSS3_PHY_975_DATA
-				DDRSS3_PHY_976_DATA
-				DDRSS3_PHY_977_DATA
-				DDRSS3_PHY_978_DATA
-				DDRSS3_PHY_979_DATA
-				DDRSS3_PHY_980_DATA
-				DDRSS3_PHY_981_DATA
-				DDRSS3_PHY_982_DATA
-				DDRSS3_PHY_983_DATA
-				DDRSS3_PHY_984_DATA
-				DDRSS3_PHY_985_DATA
-				DDRSS3_PHY_986_DATA
-				DDRSS3_PHY_987_DATA
-				DDRSS3_PHY_988_DATA
-				DDRSS3_PHY_989_DATA
-				DDRSS3_PHY_990_DATA
-				DDRSS3_PHY_991_DATA
-				DDRSS3_PHY_992_DATA
-				DDRSS3_PHY_993_DATA
-				DDRSS3_PHY_994_DATA
-				DDRSS3_PHY_995_DATA
-				DDRSS3_PHY_996_DATA
-				DDRSS3_PHY_997_DATA
-				DDRSS3_PHY_998_DATA
-				DDRSS3_PHY_999_DATA
-				DDRSS3_PHY_1000_DATA
-				DDRSS3_PHY_1001_DATA
-				DDRSS3_PHY_1002_DATA
-				DDRSS3_PHY_1003_DATA
-				DDRSS3_PHY_1004_DATA
-				DDRSS3_PHY_1005_DATA
-				DDRSS3_PHY_1006_DATA
-				DDRSS3_PHY_1007_DATA
-				DDRSS3_PHY_1008_DATA
-				DDRSS3_PHY_1009_DATA
-				DDRSS3_PHY_1010_DATA
-				DDRSS3_PHY_1011_DATA
-				DDRSS3_PHY_1012_DATA
-				DDRSS3_PHY_1013_DATA
-				DDRSS3_PHY_1014_DATA
-				DDRSS3_PHY_1015_DATA
-				DDRSS3_PHY_1016_DATA
-				DDRSS3_PHY_1017_DATA
-				DDRSS3_PHY_1018_DATA
-				DDRSS3_PHY_1019_DATA
-				DDRSS3_PHY_1020_DATA
-				DDRSS3_PHY_1021_DATA
-				DDRSS3_PHY_1022_DATA
-				DDRSS3_PHY_1023_DATA
-				DDRSS3_PHY_1024_DATA
-				DDRSS3_PHY_1025_DATA
-				DDRSS3_PHY_1026_DATA
-				DDRSS3_PHY_1027_DATA
-				DDRSS3_PHY_1028_DATA
-				DDRSS3_PHY_1029_DATA
-				DDRSS3_PHY_1030_DATA
-				DDRSS3_PHY_1031_DATA
-				DDRSS3_PHY_1032_DATA
-				DDRSS3_PHY_1033_DATA
-				DDRSS3_PHY_1034_DATA
-				DDRSS3_PHY_1035_DATA
-				DDRSS3_PHY_1036_DATA
-				DDRSS3_PHY_1037_DATA
-				DDRSS3_PHY_1038_DATA
-				DDRSS3_PHY_1039_DATA
-				DDRSS3_PHY_1040_DATA
-				DDRSS3_PHY_1041_DATA
-				DDRSS3_PHY_1042_DATA
-				DDRSS3_PHY_1043_DATA
-				DDRSS3_PHY_1044_DATA
-				DDRSS3_PHY_1045_DATA
-				DDRSS3_PHY_1046_DATA
-				DDRSS3_PHY_1047_DATA
-				DDRSS3_PHY_1048_DATA
-				DDRSS3_PHY_1049_DATA
-				DDRSS3_PHY_1050_DATA
-				DDRSS3_PHY_1051_DATA
-				DDRSS3_PHY_1052_DATA
-				DDRSS3_PHY_1053_DATA
-				DDRSS3_PHY_1054_DATA
-				DDRSS3_PHY_1055_DATA
-				DDRSS3_PHY_1056_DATA
-				DDRSS3_PHY_1057_DATA
-				DDRSS3_PHY_1058_DATA
-				DDRSS3_PHY_1059_DATA
-				DDRSS3_PHY_1060_DATA
-				DDRSS3_PHY_1061_DATA
-				DDRSS3_PHY_1062_DATA
-				DDRSS3_PHY_1063_DATA
-				DDRSS3_PHY_1064_DATA
-				DDRSS3_PHY_1065_DATA
-				DDRSS3_PHY_1066_DATA
-				DDRSS3_PHY_1067_DATA
-				DDRSS3_PHY_1068_DATA
-				DDRSS3_PHY_1069_DATA
-				DDRSS3_PHY_1070_DATA
-				DDRSS3_PHY_1071_DATA
-				DDRSS3_PHY_1072_DATA
-				DDRSS3_PHY_1073_DATA
-				DDRSS3_PHY_1074_DATA
-				DDRSS3_PHY_1075_DATA
-				DDRSS3_PHY_1076_DATA
-				DDRSS3_PHY_1077_DATA
-				DDRSS3_PHY_1078_DATA
-				DDRSS3_PHY_1079_DATA
-				DDRSS3_PHY_1080_DATA
-				DDRSS3_PHY_1081_DATA
-				DDRSS3_PHY_1082_DATA
-				DDRSS3_PHY_1083_DATA
-				DDRSS3_PHY_1084_DATA
-				DDRSS3_PHY_1085_DATA
-				DDRSS3_PHY_1086_DATA
-				DDRSS3_PHY_1087_DATA
-				DDRSS3_PHY_1088_DATA
-				DDRSS3_PHY_1089_DATA
-				DDRSS3_PHY_1090_DATA
-				DDRSS3_PHY_1091_DATA
-				DDRSS3_PHY_1092_DATA
-				DDRSS3_PHY_1093_DATA
-				DDRSS3_PHY_1094_DATA
-				DDRSS3_PHY_1095_DATA
-				DDRSS3_PHY_1096_DATA
-				DDRSS3_PHY_1097_DATA
-				DDRSS3_PHY_1098_DATA
-				DDRSS3_PHY_1099_DATA
-				DDRSS3_PHY_1100_DATA
-				DDRSS3_PHY_1101_DATA
-				DDRSS3_PHY_1102_DATA
-				DDRSS3_PHY_1103_DATA
-				DDRSS3_PHY_1104_DATA
-				DDRSS3_PHY_1105_DATA
-				DDRSS3_PHY_1106_DATA
-				DDRSS3_PHY_1107_DATA
-				DDRSS3_PHY_1108_DATA
-				DDRSS3_PHY_1109_DATA
-				DDRSS3_PHY_1110_DATA
-				DDRSS3_PHY_1111_DATA
-				DDRSS3_PHY_1112_DATA
-				DDRSS3_PHY_1113_DATA
-				DDRSS3_PHY_1114_DATA
-				DDRSS3_PHY_1115_DATA
-				DDRSS3_PHY_1116_DATA
-				DDRSS3_PHY_1117_DATA
-				DDRSS3_PHY_1118_DATA
-				DDRSS3_PHY_1119_DATA
-				DDRSS3_PHY_1120_DATA
-				DDRSS3_PHY_1121_DATA
-				DDRSS3_PHY_1122_DATA
-				DDRSS3_PHY_1123_DATA
-				DDRSS3_PHY_1124_DATA
-				DDRSS3_PHY_1125_DATA
-				DDRSS3_PHY_1126_DATA
-				DDRSS3_PHY_1127_DATA
-				DDRSS3_PHY_1128_DATA
-				DDRSS3_PHY_1129_DATA
-				DDRSS3_PHY_1130_DATA
-				DDRSS3_PHY_1131_DATA
-				DDRSS3_PHY_1132_DATA
-				DDRSS3_PHY_1133_DATA
-				DDRSS3_PHY_1134_DATA
-				DDRSS3_PHY_1135_DATA
-				DDRSS3_PHY_1136_DATA
-				DDRSS3_PHY_1137_DATA
-				DDRSS3_PHY_1138_DATA
-				DDRSS3_PHY_1139_DATA
-				DDRSS3_PHY_1140_DATA
-				DDRSS3_PHY_1141_DATA
-				DDRSS3_PHY_1142_DATA
-				DDRSS3_PHY_1143_DATA
-				DDRSS3_PHY_1144_DATA
-				DDRSS3_PHY_1145_DATA
-				DDRSS3_PHY_1146_DATA
-				DDRSS3_PHY_1147_DATA
-				DDRSS3_PHY_1148_DATA
-				DDRSS3_PHY_1149_DATA
-				DDRSS3_PHY_1150_DATA
-				DDRSS3_PHY_1151_DATA
-				DDRSS3_PHY_1152_DATA
-				DDRSS3_PHY_1153_DATA
-				DDRSS3_PHY_1154_DATA
-				DDRSS3_PHY_1155_DATA
-				DDRSS3_PHY_1156_DATA
-				DDRSS3_PHY_1157_DATA
-				DDRSS3_PHY_1158_DATA
-				DDRSS3_PHY_1159_DATA
-				DDRSS3_PHY_1160_DATA
-				DDRSS3_PHY_1161_DATA
-				DDRSS3_PHY_1162_DATA
-				DDRSS3_PHY_1163_DATA
-				DDRSS3_PHY_1164_DATA
-				DDRSS3_PHY_1165_DATA
-				DDRSS3_PHY_1166_DATA
-				DDRSS3_PHY_1167_DATA
-				DDRSS3_PHY_1168_DATA
-				DDRSS3_PHY_1169_DATA
-				DDRSS3_PHY_1170_DATA
-				DDRSS3_PHY_1171_DATA
-				DDRSS3_PHY_1172_DATA
-				DDRSS3_PHY_1173_DATA
-				DDRSS3_PHY_1174_DATA
-				DDRSS3_PHY_1175_DATA
-				DDRSS3_PHY_1176_DATA
-				DDRSS3_PHY_1177_DATA
-				DDRSS3_PHY_1178_DATA
-				DDRSS3_PHY_1179_DATA
-				DDRSS3_PHY_1180_DATA
-				DDRSS3_PHY_1181_DATA
-				DDRSS3_PHY_1182_DATA
-				DDRSS3_PHY_1183_DATA
-				DDRSS3_PHY_1184_DATA
-				DDRSS3_PHY_1185_DATA
-				DDRSS3_PHY_1186_DATA
-				DDRSS3_PHY_1187_DATA
-				DDRSS3_PHY_1188_DATA
-				DDRSS3_PHY_1189_DATA
-				DDRSS3_PHY_1190_DATA
-				DDRSS3_PHY_1191_DATA
-				DDRSS3_PHY_1192_DATA
-				DDRSS3_PHY_1193_DATA
-				DDRSS3_PHY_1194_DATA
-				DDRSS3_PHY_1195_DATA
-				DDRSS3_PHY_1196_DATA
-				DDRSS3_PHY_1197_DATA
-				DDRSS3_PHY_1198_DATA
-				DDRSS3_PHY_1199_DATA
-				DDRSS3_PHY_1200_DATA
-				DDRSS3_PHY_1201_DATA
-				DDRSS3_PHY_1202_DATA
-				DDRSS3_PHY_1203_DATA
-				DDRSS3_PHY_1204_DATA
-				DDRSS3_PHY_1205_DATA
-				DDRSS3_PHY_1206_DATA
-				DDRSS3_PHY_1207_DATA
-				DDRSS3_PHY_1208_DATA
-				DDRSS3_PHY_1209_DATA
-				DDRSS3_PHY_1210_DATA
-				DDRSS3_PHY_1211_DATA
-				DDRSS3_PHY_1212_DATA
-				DDRSS3_PHY_1213_DATA
-				DDRSS3_PHY_1214_DATA
-				DDRSS3_PHY_1215_DATA
-				DDRSS3_PHY_1216_DATA
-				DDRSS3_PHY_1217_DATA
-				DDRSS3_PHY_1218_DATA
-				DDRSS3_PHY_1219_DATA
-				DDRSS3_PHY_1220_DATA
-				DDRSS3_PHY_1221_DATA
-				DDRSS3_PHY_1222_DATA
-				DDRSS3_PHY_1223_DATA
-				DDRSS3_PHY_1224_DATA
-				DDRSS3_PHY_1225_DATA
-				DDRSS3_PHY_1226_DATA
-				DDRSS3_PHY_1227_DATA
-				DDRSS3_PHY_1228_DATA
-				DDRSS3_PHY_1229_DATA
-				DDRSS3_PHY_1230_DATA
-				DDRSS3_PHY_1231_DATA
-				DDRSS3_PHY_1232_DATA
-				DDRSS3_PHY_1233_DATA
-				DDRSS3_PHY_1234_DATA
-				DDRSS3_PHY_1235_DATA
-				DDRSS3_PHY_1236_DATA
-				DDRSS3_PHY_1237_DATA
-				DDRSS3_PHY_1238_DATA
-				DDRSS3_PHY_1239_DATA
-				DDRSS3_PHY_1240_DATA
-				DDRSS3_PHY_1241_DATA
-				DDRSS3_PHY_1242_DATA
-				DDRSS3_PHY_1243_DATA
-				DDRSS3_PHY_1244_DATA
-				DDRSS3_PHY_1245_DATA
-				DDRSS3_PHY_1246_DATA
-				DDRSS3_PHY_1247_DATA
-				DDRSS3_PHY_1248_DATA
-				DDRSS3_PHY_1249_DATA
-				DDRSS3_PHY_1250_DATA
-				DDRSS3_PHY_1251_DATA
-				DDRSS3_PHY_1252_DATA
-				DDRSS3_PHY_1253_DATA
-				DDRSS3_PHY_1254_DATA
-				DDRSS3_PHY_1255_DATA
-				DDRSS3_PHY_1256_DATA
-				DDRSS3_PHY_1257_DATA
-				DDRSS3_PHY_1258_DATA
-				DDRSS3_PHY_1259_DATA
-				DDRSS3_PHY_1260_DATA
-				DDRSS3_PHY_1261_DATA
-				DDRSS3_PHY_1262_DATA
-				DDRSS3_PHY_1263_DATA
-				DDRSS3_PHY_1264_DATA
-				DDRSS3_PHY_1265_DATA
-				DDRSS3_PHY_1266_DATA
-				DDRSS3_PHY_1267_DATA
-				DDRSS3_PHY_1268_DATA
-				DDRSS3_PHY_1269_DATA
-				DDRSS3_PHY_1270_DATA
-				DDRSS3_PHY_1271_DATA
-				DDRSS3_PHY_1272_DATA
-				DDRSS3_PHY_1273_DATA
-				DDRSS3_PHY_1274_DATA
-				DDRSS3_PHY_1275_DATA
-				DDRSS3_PHY_1276_DATA
-				DDRSS3_PHY_1277_DATA
-				DDRSS3_PHY_1278_DATA
-				DDRSS3_PHY_1279_DATA
-				DDRSS3_PHY_1280_DATA
-				DDRSS3_PHY_1281_DATA
-				DDRSS3_PHY_1282_DATA
-				DDRSS3_PHY_1283_DATA
-				DDRSS3_PHY_1284_DATA
-				DDRSS3_PHY_1285_DATA
-				DDRSS3_PHY_1286_DATA
-				DDRSS3_PHY_1287_DATA
-				DDRSS3_PHY_1288_DATA
-				DDRSS3_PHY_1289_DATA
-				DDRSS3_PHY_1290_DATA
-				DDRSS3_PHY_1291_DATA
-				DDRSS3_PHY_1292_DATA
-				DDRSS3_PHY_1293_DATA
-				DDRSS3_PHY_1294_DATA
-				DDRSS3_PHY_1295_DATA
-				DDRSS3_PHY_1296_DATA
-				DDRSS3_PHY_1297_DATA
-				DDRSS3_PHY_1298_DATA
-				DDRSS3_PHY_1299_DATA
-				DDRSS3_PHY_1300_DATA
-				DDRSS3_PHY_1301_DATA
-				DDRSS3_PHY_1302_DATA
-				DDRSS3_PHY_1303_DATA
-				DDRSS3_PHY_1304_DATA
-				DDRSS3_PHY_1305_DATA
-				DDRSS3_PHY_1306_DATA
-				DDRSS3_PHY_1307_DATA
-				DDRSS3_PHY_1308_DATA
-				DDRSS3_PHY_1309_DATA
-				DDRSS3_PHY_1310_DATA
-				DDRSS3_PHY_1311_DATA
-				DDRSS3_PHY_1312_DATA
-				DDRSS3_PHY_1313_DATA
-				DDRSS3_PHY_1314_DATA
-				DDRSS3_PHY_1315_DATA
-				DDRSS3_PHY_1316_DATA
-				DDRSS3_PHY_1317_DATA
-				DDRSS3_PHY_1318_DATA
-				DDRSS3_PHY_1319_DATA
-				DDRSS3_PHY_1320_DATA
-				DDRSS3_PHY_1321_DATA
-				DDRSS3_PHY_1322_DATA
-				DDRSS3_PHY_1323_DATA
-				DDRSS3_PHY_1324_DATA
-				DDRSS3_PHY_1325_DATA
-				DDRSS3_PHY_1326_DATA
-				DDRSS3_PHY_1327_DATA
-				DDRSS3_PHY_1328_DATA
-				DDRSS3_PHY_1329_DATA
-				DDRSS3_PHY_1330_DATA
-				DDRSS3_PHY_1331_DATA
-				DDRSS3_PHY_1332_DATA
-				DDRSS3_PHY_1333_DATA
-				DDRSS3_PHY_1334_DATA
-				DDRSS3_PHY_1335_DATA
-				DDRSS3_PHY_1336_DATA
-				DDRSS3_PHY_1337_DATA
-				DDRSS3_PHY_1338_DATA
-				DDRSS3_PHY_1339_DATA
-				DDRSS3_PHY_1340_DATA
-				DDRSS3_PHY_1341_DATA
-				DDRSS3_PHY_1342_DATA
-				DDRSS3_PHY_1343_DATA
-				DDRSS3_PHY_1344_DATA
-				DDRSS3_PHY_1345_DATA
-				DDRSS3_PHY_1346_DATA
-				DDRSS3_PHY_1347_DATA
-				DDRSS3_PHY_1348_DATA
-				DDRSS3_PHY_1349_DATA
-				DDRSS3_PHY_1350_DATA
-				DDRSS3_PHY_1351_DATA
-				DDRSS3_PHY_1352_DATA
-				DDRSS3_PHY_1353_DATA
-				DDRSS3_PHY_1354_DATA
-				DDRSS3_PHY_1355_DATA
-				DDRSS3_PHY_1356_DATA
-				DDRSS3_PHY_1357_DATA
-				DDRSS3_PHY_1358_DATA
-				DDRSS3_PHY_1359_DATA
-				DDRSS3_PHY_1360_DATA
-				DDRSS3_PHY_1361_DATA
-				DDRSS3_PHY_1362_DATA
-				DDRSS3_PHY_1363_DATA
-				DDRSS3_PHY_1364_DATA
-				DDRSS3_PHY_1365_DATA
-				DDRSS3_PHY_1366_DATA
-				DDRSS3_PHY_1367_DATA
-				DDRSS3_PHY_1368_DATA
-				DDRSS3_PHY_1369_DATA
-				DDRSS3_PHY_1370_DATA
-				DDRSS3_PHY_1371_DATA
-				DDRSS3_PHY_1372_DATA
-				DDRSS3_PHY_1373_DATA
-				DDRSS3_PHY_1374_DATA
-				DDRSS3_PHY_1375_DATA
-				DDRSS3_PHY_1376_DATA
-				DDRSS3_PHY_1377_DATA
-				DDRSS3_PHY_1378_DATA
-				DDRSS3_PHY_1379_DATA
-				DDRSS3_PHY_1380_DATA
-				DDRSS3_PHY_1381_DATA
-				DDRSS3_PHY_1382_DATA
-				DDRSS3_PHY_1383_DATA
-				DDRSS3_PHY_1384_DATA
-				DDRSS3_PHY_1385_DATA
-				DDRSS3_PHY_1386_DATA
-				DDRSS3_PHY_1387_DATA
-				DDRSS3_PHY_1388_DATA
-				DDRSS3_PHY_1389_DATA
-				DDRSS3_PHY_1390_DATA
-				DDRSS3_PHY_1391_DATA
-				DDRSS3_PHY_1392_DATA
-				DDRSS3_PHY_1393_DATA
-				DDRSS3_PHY_1394_DATA
-				DDRSS3_PHY_1395_DATA
-				DDRSS3_PHY_1396_DATA
-				DDRSS3_PHY_1397_DATA
-				DDRSS3_PHY_1398_DATA
-				DDRSS3_PHY_1399_DATA
-				DDRSS3_PHY_1400_DATA
-				DDRSS3_PHY_1401_DATA
-				DDRSS3_PHY_1402_DATA
-				DDRSS3_PHY_1403_DATA
-				DDRSS3_PHY_1404_DATA
-				DDRSS3_PHY_1405_DATA
-				DDRSS3_PHY_1406_DATA
-				DDRSS3_PHY_1407_DATA
-				DDRSS3_PHY_1408_DATA
-				DDRSS3_PHY_1409_DATA
-				DDRSS3_PHY_1410_DATA
-				DDRSS3_PHY_1411_DATA
-				DDRSS3_PHY_1412_DATA
-				DDRSS3_PHY_1413_DATA
-				DDRSS3_PHY_1414_DATA
-				DDRSS3_PHY_1415_DATA
-				DDRSS3_PHY_1416_DATA
-				DDRSS3_PHY_1417_DATA
-				DDRSS3_PHY_1418_DATA
-				DDRSS3_PHY_1419_DATA
-				DDRSS3_PHY_1420_DATA
-				DDRSS3_PHY_1421_DATA
-				DDRSS3_PHY_1422_DATA
-			>;
-		};
+		ti,phy-data = <
+			DDRSS3_PHY_00_DATA
+			DDRSS3_PHY_01_DATA
+			DDRSS3_PHY_02_DATA
+			DDRSS3_PHY_03_DATA
+			DDRSS3_PHY_04_DATA
+			DDRSS3_PHY_05_DATA
+			DDRSS3_PHY_06_DATA
+			DDRSS3_PHY_07_DATA
+			DDRSS3_PHY_08_DATA
+			DDRSS3_PHY_09_DATA
+			DDRSS3_PHY_10_DATA
+			DDRSS3_PHY_11_DATA
+			DDRSS3_PHY_12_DATA
+			DDRSS3_PHY_13_DATA
+			DDRSS3_PHY_14_DATA
+			DDRSS3_PHY_15_DATA
+			DDRSS3_PHY_16_DATA
+			DDRSS3_PHY_17_DATA
+			DDRSS3_PHY_18_DATA
+			DDRSS3_PHY_19_DATA
+			DDRSS3_PHY_20_DATA
+			DDRSS3_PHY_21_DATA
+			DDRSS3_PHY_22_DATA
+			DDRSS3_PHY_23_DATA
+			DDRSS3_PHY_24_DATA
+			DDRSS3_PHY_25_DATA
+			DDRSS3_PHY_26_DATA
+			DDRSS3_PHY_27_DATA
+			DDRSS3_PHY_28_DATA
+			DDRSS3_PHY_29_DATA
+			DDRSS3_PHY_30_DATA
+			DDRSS3_PHY_31_DATA
+			DDRSS3_PHY_32_DATA
+			DDRSS3_PHY_33_DATA
+			DDRSS3_PHY_34_DATA
+			DDRSS3_PHY_35_DATA
+			DDRSS3_PHY_36_DATA
+			DDRSS3_PHY_37_DATA
+			DDRSS3_PHY_38_DATA
+			DDRSS3_PHY_39_DATA
+			DDRSS3_PHY_40_DATA
+			DDRSS3_PHY_41_DATA
+			DDRSS3_PHY_42_DATA
+			DDRSS3_PHY_43_DATA
+			DDRSS3_PHY_44_DATA
+			DDRSS3_PHY_45_DATA
+			DDRSS3_PHY_46_DATA
+			DDRSS3_PHY_47_DATA
+			DDRSS3_PHY_48_DATA
+			DDRSS3_PHY_49_DATA
+			DDRSS3_PHY_50_DATA
+			DDRSS3_PHY_51_DATA
+			DDRSS3_PHY_52_DATA
+			DDRSS3_PHY_53_DATA
+			DDRSS3_PHY_54_DATA
+			DDRSS3_PHY_55_DATA
+			DDRSS3_PHY_56_DATA
+			DDRSS3_PHY_57_DATA
+			DDRSS3_PHY_58_DATA
+			DDRSS3_PHY_59_DATA
+			DDRSS3_PHY_60_DATA
+			DDRSS3_PHY_61_DATA
+			DDRSS3_PHY_62_DATA
+			DDRSS3_PHY_63_DATA
+			DDRSS3_PHY_64_DATA
+			DDRSS3_PHY_65_DATA
+			DDRSS3_PHY_66_DATA
+			DDRSS3_PHY_67_DATA
+			DDRSS3_PHY_68_DATA
+			DDRSS3_PHY_69_DATA
+			DDRSS3_PHY_70_DATA
+			DDRSS3_PHY_71_DATA
+			DDRSS3_PHY_72_DATA
+			DDRSS3_PHY_73_DATA
+			DDRSS3_PHY_74_DATA
+			DDRSS3_PHY_75_DATA
+			DDRSS3_PHY_76_DATA
+			DDRSS3_PHY_77_DATA
+			DDRSS3_PHY_78_DATA
+			DDRSS3_PHY_79_DATA
+			DDRSS3_PHY_80_DATA
+			DDRSS3_PHY_81_DATA
+			DDRSS3_PHY_82_DATA
+			DDRSS3_PHY_83_DATA
+			DDRSS3_PHY_84_DATA
+			DDRSS3_PHY_85_DATA
+			DDRSS3_PHY_86_DATA
+			DDRSS3_PHY_87_DATA
+			DDRSS3_PHY_88_DATA
+			DDRSS3_PHY_89_DATA
+			DDRSS3_PHY_90_DATA
+			DDRSS3_PHY_91_DATA
+			DDRSS3_PHY_92_DATA
+			DDRSS3_PHY_93_DATA
+			DDRSS3_PHY_94_DATA
+			DDRSS3_PHY_95_DATA
+			DDRSS3_PHY_96_DATA
+			DDRSS3_PHY_97_DATA
+			DDRSS3_PHY_98_DATA
+			DDRSS3_PHY_99_DATA
+			DDRSS3_PHY_100_DATA
+			DDRSS3_PHY_101_DATA
+			DDRSS3_PHY_102_DATA
+			DDRSS3_PHY_103_DATA
+			DDRSS3_PHY_104_DATA
+			DDRSS3_PHY_105_DATA
+			DDRSS3_PHY_106_DATA
+			DDRSS3_PHY_107_DATA
+			DDRSS3_PHY_108_DATA
+			DDRSS3_PHY_109_DATA
+			DDRSS3_PHY_110_DATA
+			DDRSS3_PHY_111_DATA
+			DDRSS3_PHY_112_DATA
+			DDRSS3_PHY_113_DATA
+			DDRSS3_PHY_114_DATA
+			DDRSS3_PHY_115_DATA
+			DDRSS3_PHY_116_DATA
+			DDRSS3_PHY_117_DATA
+			DDRSS3_PHY_118_DATA
+			DDRSS3_PHY_119_DATA
+			DDRSS3_PHY_120_DATA
+			DDRSS3_PHY_121_DATA
+			DDRSS3_PHY_122_DATA
+			DDRSS3_PHY_123_DATA
+			DDRSS3_PHY_124_DATA
+			DDRSS3_PHY_125_DATA
+			DDRSS3_PHY_126_DATA
+			DDRSS3_PHY_127_DATA
+			DDRSS3_PHY_128_DATA
+			DDRSS3_PHY_129_DATA
+			DDRSS3_PHY_130_DATA
+			DDRSS3_PHY_131_DATA
+			DDRSS3_PHY_132_DATA
+			DDRSS3_PHY_133_DATA
+			DDRSS3_PHY_134_DATA
+			DDRSS3_PHY_135_DATA
+			DDRSS3_PHY_136_DATA
+			DDRSS3_PHY_137_DATA
+			DDRSS3_PHY_138_DATA
+			DDRSS3_PHY_139_DATA
+			DDRSS3_PHY_140_DATA
+			DDRSS3_PHY_141_DATA
+			DDRSS3_PHY_142_DATA
+			DDRSS3_PHY_143_DATA
+			DDRSS3_PHY_144_DATA
+			DDRSS3_PHY_145_DATA
+			DDRSS3_PHY_146_DATA
+			DDRSS3_PHY_147_DATA
+			DDRSS3_PHY_148_DATA
+			DDRSS3_PHY_149_DATA
+			DDRSS3_PHY_150_DATA
+			DDRSS3_PHY_151_DATA
+			DDRSS3_PHY_152_DATA
+			DDRSS3_PHY_153_DATA
+			DDRSS3_PHY_154_DATA
+			DDRSS3_PHY_155_DATA
+			DDRSS3_PHY_156_DATA
+			DDRSS3_PHY_157_DATA
+			DDRSS3_PHY_158_DATA
+			DDRSS3_PHY_159_DATA
+			DDRSS3_PHY_160_DATA
+			DDRSS3_PHY_161_DATA
+			DDRSS3_PHY_162_DATA
+			DDRSS3_PHY_163_DATA
+			DDRSS3_PHY_164_DATA
+			DDRSS3_PHY_165_DATA
+			DDRSS3_PHY_166_DATA
+			DDRSS3_PHY_167_DATA
+			DDRSS3_PHY_168_DATA
+			DDRSS3_PHY_169_DATA
+			DDRSS3_PHY_170_DATA
+			DDRSS3_PHY_171_DATA
+			DDRSS3_PHY_172_DATA
+			DDRSS3_PHY_173_DATA
+			DDRSS3_PHY_174_DATA
+			DDRSS3_PHY_175_DATA
+			DDRSS3_PHY_176_DATA
+			DDRSS3_PHY_177_DATA
+			DDRSS3_PHY_178_DATA
+			DDRSS3_PHY_179_DATA
+			DDRSS3_PHY_180_DATA
+			DDRSS3_PHY_181_DATA
+			DDRSS3_PHY_182_DATA
+			DDRSS3_PHY_183_DATA
+			DDRSS3_PHY_184_DATA
+			DDRSS3_PHY_185_DATA
+			DDRSS3_PHY_186_DATA
+			DDRSS3_PHY_187_DATA
+			DDRSS3_PHY_188_DATA
+			DDRSS3_PHY_189_DATA
+			DDRSS3_PHY_190_DATA
+			DDRSS3_PHY_191_DATA
+			DDRSS3_PHY_192_DATA
+			DDRSS3_PHY_193_DATA
+			DDRSS3_PHY_194_DATA
+			DDRSS3_PHY_195_DATA
+			DDRSS3_PHY_196_DATA
+			DDRSS3_PHY_197_DATA
+			DDRSS3_PHY_198_DATA
+			DDRSS3_PHY_199_DATA
+			DDRSS3_PHY_200_DATA
+			DDRSS3_PHY_201_DATA
+			DDRSS3_PHY_202_DATA
+			DDRSS3_PHY_203_DATA
+			DDRSS3_PHY_204_DATA
+			DDRSS3_PHY_205_DATA
+			DDRSS3_PHY_206_DATA
+			DDRSS3_PHY_207_DATA
+			DDRSS3_PHY_208_DATA
+			DDRSS3_PHY_209_DATA
+			DDRSS3_PHY_210_DATA
+			DDRSS3_PHY_211_DATA
+			DDRSS3_PHY_212_DATA
+			DDRSS3_PHY_213_DATA
+			DDRSS3_PHY_214_DATA
+			DDRSS3_PHY_215_DATA
+			DDRSS3_PHY_216_DATA
+			DDRSS3_PHY_217_DATA
+			DDRSS3_PHY_218_DATA
+			DDRSS3_PHY_219_DATA
+			DDRSS3_PHY_220_DATA
+			DDRSS3_PHY_221_DATA
+			DDRSS3_PHY_222_DATA
+			DDRSS3_PHY_223_DATA
+			DDRSS3_PHY_224_DATA
+			DDRSS3_PHY_225_DATA
+			DDRSS3_PHY_226_DATA
+			DDRSS3_PHY_227_DATA
+			DDRSS3_PHY_228_DATA
+			DDRSS3_PHY_229_DATA
+			DDRSS3_PHY_230_DATA
+			DDRSS3_PHY_231_DATA
+			DDRSS3_PHY_232_DATA
+			DDRSS3_PHY_233_DATA
+			DDRSS3_PHY_234_DATA
+			DDRSS3_PHY_235_DATA
+			DDRSS3_PHY_236_DATA
+			DDRSS3_PHY_237_DATA
+			DDRSS3_PHY_238_DATA
+			DDRSS3_PHY_239_DATA
+			DDRSS3_PHY_240_DATA
+			DDRSS3_PHY_241_DATA
+			DDRSS3_PHY_242_DATA
+			DDRSS3_PHY_243_DATA
+			DDRSS3_PHY_244_DATA
+			DDRSS3_PHY_245_DATA
+			DDRSS3_PHY_246_DATA
+			DDRSS3_PHY_247_DATA
+			DDRSS3_PHY_248_DATA
+			DDRSS3_PHY_249_DATA
+			DDRSS3_PHY_250_DATA
+			DDRSS3_PHY_251_DATA
+			DDRSS3_PHY_252_DATA
+			DDRSS3_PHY_253_DATA
+			DDRSS3_PHY_254_DATA
+			DDRSS3_PHY_255_DATA
+			DDRSS3_PHY_256_DATA
+			DDRSS3_PHY_257_DATA
+			DDRSS3_PHY_258_DATA
+			DDRSS3_PHY_259_DATA
+			DDRSS3_PHY_260_DATA
+			DDRSS3_PHY_261_DATA
+			DDRSS3_PHY_262_DATA
+			DDRSS3_PHY_263_DATA
+			DDRSS3_PHY_264_DATA
+			DDRSS3_PHY_265_DATA
+			DDRSS3_PHY_266_DATA
+			DDRSS3_PHY_267_DATA
+			DDRSS3_PHY_268_DATA
+			DDRSS3_PHY_269_DATA
+			DDRSS3_PHY_270_DATA
+			DDRSS3_PHY_271_DATA
+			DDRSS3_PHY_272_DATA
+			DDRSS3_PHY_273_DATA
+			DDRSS3_PHY_274_DATA
+			DDRSS3_PHY_275_DATA
+			DDRSS3_PHY_276_DATA
+			DDRSS3_PHY_277_DATA
+			DDRSS3_PHY_278_DATA
+			DDRSS3_PHY_279_DATA
+			DDRSS3_PHY_280_DATA
+			DDRSS3_PHY_281_DATA
+			DDRSS3_PHY_282_DATA
+			DDRSS3_PHY_283_DATA
+			DDRSS3_PHY_284_DATA
+			DDRSS3_PHY_285_DATA
+			DDRSS3_PHY_286_DATA
+			DDRSS3_PHY_287_DATA
+			DDRSS3_PHY_288_DATA
+			DDRSS3_PHY_289_DATA
+			DDRSS3_PHY_290_DATA
+			DDRSS3_PHY_291_DATA
+			DDRSS3_PHY_292_DATA
+			DDRSS3_PHY_293_DATA
+			DDRSS3_PHY_294_DATA
+			DDRSS3_PHY_295_DATA
+			DDRSS3_PHY_296_DATA
+			DDRSS3_PHY_297_DATA
+			DDRSS3_PHY_298_DATA
+			DDRSS3_PHY_299_DATA
+			DDRSS3_PHY_300_DATA
+			DDRSS3_PHY_301_DATA
+			DDRSS3_PHY_302_DATA
+			DDRSS3_PHY_303_DATA
+			DDRSS3_PHY_304_DATA
+			DDRSS3_PHY_305_DATA
+			DDRSS3_PHY_306_DATA
+			DDRSS3_PHY_307_DATA
+			DDRSS3_PHY_308_DATA
+			DDRSS3_PHY_309_DATA
+			DDRSS3_PHY_310_DATA
+			DDRSS3_PHY_311_DATA
+			DDRSS3_PHY_312_DATA
+			DDRSS3_PHY_313_DATA
+			DDRSS3_PHY_314_DATA
+			DDRSS3_PHY_315_DATA
+			DDRSS3_PHY_316_DATA
+			DDRSS3_PHY_317_DATA
+			DDRSS3_PHY_318_DATA
+			DDRSS3_PHY_319_DATA
+			DDRSS3_PHY_320_DATA
+			DDRSS3_PHY_321_DATA
+			DDRSS3_PHY_322_DATA
+			DDRSS3_PHY_323_DATA
+			DDRSS3_PHY_324_DATA
+			DDRSS3_PHY_325_DATA
+			DDRSS3_PHY_326_DATA
+			DDRSS3_PHY_327_DATA
+			DDRSS3_PHY_328_DATA
+			DDRSS3_PHY_329_DATA
+			DDRSS3_PHY_330_DATA
+			DDRSS3_PHY_331_DATA
+			DDRSS3_PHY_332_DATA
+			DDRSS3_PHY_333_DATA
+			DDRSS3_PHY_334_DATA
+			DDRSS3_PHY_335_DATA
+			DDRSS3_PHY_336_DATA
+			DDRSS3_PHY_337_DATA
+			DDRSS3_PHY_338_DATA
+			DDRSS3_PHY_339_DATA
+			DDRSS3_PHY_340_DATA
+			DDRSS3_PHY_341_DATA
+			DDRSS3_PHY_342_DATA
+			DDRSS3_PHY_343_DATA
+			DDRSS3_PHY_344_DATA
+			DDRSS3_PHY_345_DATA
+			DDRSS3_PHY_346_DATA
+			DDRSS3_PHY_347_DATA
+			DDRSS3_PHY_348_DATA
+			DDRSS3_PHY_349_DATA
+			DDRSS3_PHY_350_DATA
+			DDRSS3_PHY_351_DATA
+			DDRSS3_PHY_352_DATA
+			DDRSS3_PHY_353_DATA
+			DDRSS3_PHY_354_DATA
+			DDRSS3_PHY_355_DATA
+			DDRSS3_PHY_356_DATA
+			DDRSS3_PHY_357_DATA
+			DDRSS3_PHY_358_DATA
+			DDRSS3_PHY_359_DATA
+			DDRSS3_PHY_360_DATA
+			DDRSS3_PHY_361_DATA
+			DDRSS3_PHY_362_DATA
+			DDRSS3_PHY_363_DATA
+			DDRSS3_PHY_364_DATA
+			DDRSS3_PHY_365_DATA
+			DDRSS3_PHY_366_DATA
+			DDRSS3_PHY_367_DATA
+			DDRSS3_PHY_368_DATA
+			DDRSS3_PHY_369_DATA
+			DDRSS3_PHY_370_DATA
+			DDRSS3_PHY_371_DATA
+			DDRSS3_PHY_372_DATA
+			DDRSS3_PHY_373_DATA
+			DDRSS3_PHY_374_DATA
+			DDRSS3_PHY_375_DATA
+			DDRSS3_PHY_376_DATA
+			DDRSS3_PHY_377_DATA
+			DDRSS3_PHY_378_DATA
+			DDRSS3_PHY_379_DATA
+			DDRSS3_PHY_380_DATA
+			DDRSS3_PHY_381_DATA
+			DDRSS3_PHY_382_DATA
+			DDRSS3_PHY_383_DATA
+			DDRSS3_PHY_384_DATA
+			DDRSS3_PHY_385_DATA
+			DDRSS3_PHY_386_DATA
+			DDRSS3_PHY_387_DATA
+			DDRSS3_PHY_388_DATA
+			DDRSS3_PHY_389_DATA
+			DDRSS3_PHY_390_DATA
+			DDRSS3_PHY_391_DATA
+			DDRSS3_PHY_392_DATA
+			DDRSS3_PHY_393_DATA
+			DDRSS3_PHY_394_DATA
+			DDRSS3_PHY_395_DATA
+			DDRSS3_PHY_396_DATA
+			DDRSS3_PHY_397_DATA
+			DDRSS3_PHY_398_DATA
+			DDRSS3_PHY_399_DATA
+			DDRSS3_PHY_400_DATA
+			DDRSS3_PHY_401_DATA
+			DDRSS3_PHY_402_DATA
+			DDRSS3_PHY_403_DATA
+			DDRSS3_PHY_404_DATA
+			DDRSS3_PHY_405_DATA
+			DDRSS3_PHY_406_DATA
+			DDRSS3_PHY_407_DATA
+			DDRSS3_PHY_408_DATA
+			DDRSS3_PHY_409_DATA
+			DDRSS3_PHY_410_DATA
+			DDRSS3_PHY_411_DATA
+			DDRSS3_PHY_412_DATA
+			DDRSS3_PHY_413_DATA
+			DDRSS3_PHY_414_DATA
+			DDRSS3_PHY_415_DATA
+			DDRSS3_PHY_416_DATA
+			DDRSS3_PHY_417_DATA
+			DDRSS3_PHY_418_DATA
+			DDRSS3_PHY_419_DATA
+			DDRSS3_PHY_420_DATA
+			DDRSS3_PHY_421_DATA
+			DDRSS3_PHY_422_DATA
+			DDRSS3_PHY_423_DATA
+			DDRSS3_PHY_424_DATA
+			DDRSS3_PHY_425_DATA
+			DDRSS3_PHY_426_DATA
+			DDRSS3_PHY_427_DATA
+			DDRSS3_PHY_428_DATA
+			DDRSS3_PHY_429_DATA
+			DDRSS3_PHY_430_DATA
+			DDRSS3_PHY_431_DATA
+			DDRSS3_PHY_432_DATA
+			DDRSS3_PHY_433_DATA
+			DDRSS3_PHY_434_DATA
+			DDRSS3_PHY_435_DATA
+			DDRSS3_PHY_436_DATA
+			DDRSS3_PHY_437_DATA
+			DDRSS3_PHY_438_DATA
+			DDRSS3_PHY_439_DATA
+			DDRSS3_PHY_440_DATA
+			DDRSS3_PHY_441_DATA
+			DDRSS3_PHY_442_DATA
+			DDRSS3_PHY_443_DATA
+			DDRSS3_PHY_444_DATA
+			DDRSS3_PHY_445_DATA
+			DDRSS3_PHY_446_DATA
+			DDRSS3_PHY_447_DATA
+			DDRSS3_PHY_448_DATA
+			DDRSS3_PHY_449_DATA
+			DDRSS3_PHY_450_DATA
+			DDRSS3_PHY_451_DATA
+			DDRSS3_PHY_452_DATA
+			DDRSS3_PHY_453_DATA
+			DDRSS3_PHY_454_DATA
+			DDRSS3_PHY_455_DATA
+			DDRSS3_PHY_456_DATA
+			DDRSS3_PHY_457_DATA
+			DDRSS3_PHY_458_DATA
+			DDRSS3_PHY_459_DATA
+			DDRSS3_PHY_460_DATA
+			DDRSS3_PHY_461_DATA
+			DDRSS3_PHY_462_DATA
+			DDRSS3_PHY_463_DATA
+			DDRSS3_PHY_464_DATA
+			DDRSS3_PHY_465_DATA
+			DDRSS3_PHY_466_DATA
+			DDRSS3_PHY_467_DATA
+			DDRSS3_PHY_468_DATA
+			DDRSS3_PHY_469_DATA
+			DDRSS3_PHY_470_DATA
+			DDRSS3_PHY_471_DATA
+			DDRSS3_PHY_472_DATA
+			DDRSS3_PHY_473_DATA
+			DDRSS3_PHY_474_DATA
+			DDRSS3_PHY_475_DATA
+			DDRSS3_PHY_476_DATA
+			DDRSS3_PHY_477_DATA
+			DDRSS3_PHY_478_DATA
+			DDRSS3_PHY_479_DATA
+			DDRSS3_PHY_480_DATA
+			DDRSS3_PHY_481_DATA
+			DDRSS3_PHY_482_DATA
+			DDRSS3_PHY_483_DATA
+			DDRSS3_PHY_484_DATA
+			DDRSS3_PHY_485_DATA
+			DDRSS3_PHY_486_DATA
+			DDRSS3_PHY_487_DATA
+			DDRSS3_PHY_488_DATA
+			DDRSS3_PHY_489_DATA
+			DDRSS3_PHY_490_DATA
+			DDRSS3_PHY_491_DATA
+			DDRSS3_PHY_492_DATA
+			DDRSS3_PHY_493_DATA
+			DDRSS3_PHY_494_DATA
+			DDRSS3_PHY_495_DATA
+			DDRSS3_PHY_496_DATA
+			DDRSS3_PHY_497_DATA
+			DDRSS3_PHY_498_DATA
+			DDRSS3_PHY_499_DATA
+			DDRSS3_PHY_500_DATA
+			DDRSS3_PHY_501_DATA
+			DDRSS3_PHY_502_DATA
+			DDRSS3_PHY_503_DATA
+			DDRSS3_PHY_504_DATA
+			DDRSS3_PHY_505_DATA
+			DDRSS3_PHY_506_DATA
+			DDRSS3_PHY_507_DATA
+			DDRSS3_PHY_508_DATA
+			DDRSS3_PHY_509_DATA
+			DDRSS3_PHY_510_DATA
+			DDRSS3_PHY_511_DATA
+			DDRSS3_PHY_512_DATA
+			DDRSS3_PHY_513_DATA
+			DDRSS3_PHY_514_DATA
+			DDRSS3_PHY_515_DATA
+			DDRSS3_PHY_516_DATA
+			DDRSS3_PHY_517_DATA
+			DDRSS3_PHY_518_DATA
+			DDRSS3_PHY_519_DATA
+			DDRSS3_PHY_520_DATA
+			DDRSS3_PHY_521_DATA
+			DDRSS3_PHY_522_DATA
+			DDRSS3_PHY_523_DATA
+			DDRSS3_PHY_524_DATA
+			DDRSS3_PHY_525_DATA
+			DDRSS3_PHY_526_DATA
+			DDRSS3_PHY_527_DATA
+			DDRSS3_PHY_528_DATA
+			DDRSS3_PHY_529_DATA
+			DDRSS3_PHY_530_DATA
+			DDRSS3_PHY_531_DATA
+			DDRSS3_PHY_532_DATA
+			DDRSS3_PHY_533_DATA
+			DDRSS3_PHY_534_DATA
+			DDRSS3_PHY_535_DATA
+			DDRSS3_PHY_536_DATA
+			DDRSS3_PHY_537_DATA
+			DDRSS3_PHY_538_DATA
+			DDRSS3_PHY_539_DATA
+			DDRSS3_PHY_540_DATA
+			DDRSS3_PHY_541_DATA
+			DDRSS3_PHY_542_DATA
+			DDRSS3_PHY_543_DATA
+			DDRSS3_PHY_544_DATA
+			DDRSS3_PHY_545_DATA
+			DDRSS3_PHY_546_DATA
+			DDRSS3_PHY_547_DATA
+			DDRSS3_PHY_548_DATA
+			DDRSS3_PHY_549_DATA
+			DDRSS3_PHY_550_DATA
+			DDRSS3_PHY_551_DATA
+			DDRSS3_PHY_552_DATA
+			DDRSS3_PHY_553_DATA
+			DDRSS3_PHY_554_DATA
+			DDRSS3_PHY_555_DATA
+			DDRSS3_PHY_556_DATA
+			DDRSS3_PHY_557_DATA
+			DDRSS3_PHY_558_DATA
+			DDRSS3_PHY_559_DATA
+			DDRSS3_PHY_560_DATA
+			DDRSS3_PHY_561_DATA
+			DDRSS3_PHY_562_DATA
+			DDRSS3_PHY_563_DATA
+			DDRSS3_PHY_564_DATA
+			DDRSS3_PHY_565_DATA
+			DDRSS3_PHY_566_DATA
+			DDRSS3_PHY_567_DATA
+			DDRSS3_PHY_568_DATA
+			DDRSS3_PHY_569_DATA
+			DDRSS3_PHY_570_DATA
+			DDRSS3_PHY_571_DATA
+			DDRSS3_PHY_572_DATA
+			DDRSS3_PHY_573_DATA
+			DDRSS3_PHY_574_DATA
+			DDRSS3_PHY_575_DATA
+			DDRSS3_PHY_576_DATA
+			DDRSS3_PHY_577_DATA
+			DDRSS3_PHY_578_DATA
+			DDRSS3_PHY_579_DATA
+			DDRSS3_PHY_580_DATA
+			DDRSS3_PHY_581_DATA
+			DDRSS3_PHY_582_DATA
+			DDRSS3_PHY_583_DATA
+			DDRSS3_PHY_584_DATA
+			DDRSS3_PHY_585_DATA
+			DDRSS3_PHY_586_DATA
+			DDRSS3_PHY_587_DATA
+			DDRSS3_PHY_588_DATA
+			DDRSS3_PHY_589_DATA
+			DDRSS3_PHY_590_DATA
+			DDRSS3_PHY_591_DATA
+			DDRSS3_PHY_592_DATA
+			DDRSS3_PHY_593_DATA
+			DDRSS3_PHY_594_DATA
+			DDRSS3_PHY_595_DATA
+			DDRSS3_PHY_596_DATA
+			DDRSS3_PHY_597_DATA
+			DDRSS3_PHY_598_DATA
+			DDRSS3_PHY_599_DATA
+			DDRSS3_PHY_600_DATA
+			DDRSS3_PHY_601_DATA
+			DDRSS3_PHY_602_DATA
+			DDRSS3_PHY_603_DATA
+			DDRSS3_PHY_604_DATA
+			DDRSS3_PHY_605_DATA
+			DDRSS3_PHY_606_DATA
+			DDRSS3_PHY_607_DATA
+			DDRSS3_PHY_608_DATA
+			DDRSS3_PHY_609_DATA
+			DDRSS3_PHY_610_DATA
+			DDRSS3_PHY_611_DATA
+			DDRSS3_PHY_612_DATA
+			DDRSS3_PHY_613_DATA
+			DDRSS3_PHY_614_DATA
+			DDRSS3_PHY_615_DATA
+			DDRSS3_PHY_616_DATA
+			DDRSS3_PHY_617_DATA
+			DDRSS3_PHY_618_DATA
+			DDRSS3_PHY_619_DATA
+			DDRSS3_PHY_620_DATA
+			DDRSS3_PHY_621_DATA
+			DDRSS3_PHY_622_DATA
+			DDRSS3_PHY_623_DATA
+			DDRSS3_PHY_624_DATA
+			DDRSS3_PHY_625_DATA
+			DDRSS3_PHY_626_DATA
+			DDRSS3_PHY_627_DATA
+			DDRSS3_PHY_628_DATA
+			DDRSS3_PHY_629_DATA
+			DDRSS3_PHY_630_DATA
+			DDRSS3_PHY_631_DATA
+			DDRSS3_PHY_632_DATA
+			DDRSS3_PHY_633_DATA
+			DDRSS3_PHY_634_DATA
+			DDRSS3_PHY_635_DATA
+			DDRSS3_PHY_636_DATA
+			DDRSS3_PHY_637_DATA
+			DDRSS3_PHY_638_DATA
+			DDRSS3_PHY_639_DATA
+			DDRSS3_PHY_640_DATA
+			DDRSS3_PHY_641_DATA
+			DDRSS3_PHY_642_DATA
+			DDRSS3_PHY_643_DATA
+			DDRSS3_PHY_644_DATA
+			DDRSS3_PHY_645_DATA
+			DDRSS3_PHY_646_DATA
+			DDRSS3_PHY_647_DATA
+			DDRSS3_PHY_648_DATA
+			DDRSS3_PHY_649_DATA
+			DDRSS3_PHY_650_DATA
+			DDRSS3_PHY_651_DATA
+			DDRSS3_PHY_652_DATA
+			DDRSS3_PHY_653_DATA
+			DDRSS3_PHY_654_DATA
+			DDRSS3_PHY_655_DATA
+			DDRSS3_PHY_656_DATA
+			DDRSS3_PHY_657_DATA
+			DDRSS3_PHY_658_DATA
+			DDRSS3_PHY_659_DATA
+			DDRSS3_PHY_660_DATA
+			DDRSS3_PHY_661_DATA
+			DDRSS3_PHY_662_DATA
+			DDRSS3_PHY_663_DATA
+			DDRSS3_PHY_664_DATA
+			DDRSS3_PHY_665_DATA
+			DDRSS3_PHY_666_DATA
+			DDRSS3_PHY_667_DATA
+			DDRSS3_PHY_668_DATA
+			DDRSS3_PHY_669_DATA
+			DDRSS3_PHY_670_DATA
+			DDRSS3_PHY_671_DATA
+			DDRSS3_PHY_672_DATA
+			DDRSS3_PHY_673_DATA
+			DDRSS3_PHY_674_DATA
+			DDRSS3_PHY_675_DATA
+			DDRSS3_PHY_676_DATA
+			DDRSS3_PHY_677_DATA
+			DDRSS3_PHY_678_DATA
+			DDRSS3_PHY_679_DATA
+			DDRSS3_PHY_680_DATA
+			DDRSS3_PHY_681_DATA
+			DDRSS3_PHY_682_DATA
+			DDRSS3_PHY_683_DATA
+			DDRSS3_PHY_684_DATA
+			DDRSS3_PHY_685_DATA
+			DDRSS3_PHY_686_DATA
+			DDRSS3_PHY_687_DATA
+			DDRSS3_PHY_688_DATA
+			DDRSS3_PHY_689_DATA
+			DDRSS3_PHY_690_DATA
+			DDRSS3_PHY_691_DATA
+			DDRSS3_PHY_692_DATA
+			DDRSS3_PHY_693_DATA
+			DDRSS3_PHY_694_DATA
+			DDRSS3_PHY_695_DATA
+			DDRSS3_PHY_696_DATA
+			DDRSS3_PHY_697_DATA
+			DDRSS3_PHY_698_DATA
+			DDRSS3_PHY_699_DATA
+			DDRSS3_PHY_700_DATA
+			DDRSS3_PHY_701_DATA
+			DDRSS3_PHY_702_DATA
+			DDRSS3_PHY_703_DATA
+			DDRSS3_PHY_704_DATA
+			DDRSS3_PHY_705_DATA
+			DDRSS3_PHY_706_DATA
+			DDRSS3_PHY_707_DATA
+			DDRSS3_PHY_708_DATA
+			DDRSS3_PHY_709_DATA
+			DDRSS3_PHY_710_DATA
+			DDRSS3_PHY_711_DATA
+			DDRSS3_PHY_712_DATA
+			DDRSS3_PHY_713_DATA
+			DDRSS3_PHY_714_DATA
+			DDRSS3_PHY_715_DATA
+			DDRSS3_PHY_716_DATA
+			DDRSS3_PHY_717_DATA
+			DDRSS3_PHY_718_DATA
+			DDRSS3_PHY_719_DATA
+			DDRSS3_PHY_720_DATA
+			DDRSS3_PHY_721_DATA
+			DDRSS3_PHY_722_DATA
+			DDRSS3_PHY_723_DATA
+			DDRSS3_PHY_724_DATA
+			DDRSS3_PHY_725_DATA
+			DDRSS3_PHY_726_DATA
+			DDRSS3_PHY_727_DATA
+			DDRSS3_PHY_728_DATA
+			DDRSS3_PHY_729_DATA
+			DDRSS3_PHY_730_DATA
+			DDRSS3_PHY_731_DATA
+			DDRSS3_PHY_732_DATA
+			DDRSS3_PHY_733_DATA
+			DDRSS3_PHY_734_DATA
+			DDRSS3_PHY_735_DATA
+			DDRSS3_PHY_736_DATA
+			DDRSS3_PHY_737_DATA
+			DDRSS3_PHY_738_DATA
+			DDRSS3_PHY_739_DATA
+			DDRSS3_PHY_740_DATA
+			DDRSS3_PHY_741_DATA
+			DDRSS3_PHY_742_DATA
+			DDRSS3_PHY_743_DATA
+			DDRSS3_PHY_744_DATA
+			DDRSS3_PHY_745_DATA
+			DDRSS3_PHY_746_DATA
+			DDRSS3_PHY_747_DATA
+			DDRSS3_PHY_748_DATA
+			DDRSS3_PHY_749_DATA
+			DDRSS3_PHY_750_DATA
+			DDRSS3_PHY_751_DATA
+			DDRSS3_PHY_752_DATA
+			DDRSS3_PHY_753_DATA
+			DDRSS3_PHY_754_DATA
+			DDRSS3_PHY_755_DATA
+			DDRSS3_PHY_756_DATA
+			DDRSS3_PHY_757_DATA
+			DDRSS3_PHY_758_DATA
+			DDRSS3_PHY_759_DATA
+			DDRSS3_PHY_760_DATA
+			DDRSS3_PHY_761_DATA
+			DDRSS3_PHY_762_DATA
+			DDRSS3_PHY_763_DATA
+			DDRSS3_PHY_764_DATA
+			DDRSS3_PHY_765_DATA
+			DDRSS3_PHY_766_DATA
+			DDRSS3_PHY_767_DATA
+			DDRSS3_PHY_768_DATA
+			DDRSS3_PHY_769_DATA
+			DDRSS3_PHY_770_DATA
+			DDRSS3_PHY_771_DATA
+			DDRSS3_PHY_772_DATA
+			DDRSS3_PHY_773_DATA
+			DDRSS3_PHY_774_DATA
+			DDRSS3_PHY_775_DATA
+			DDRSS3_PHY_776_DATA
+			DDRSS3_PHY_777_DATA
+			DDRSS3_PHY_778_DATA
+			DDRSS3_PHY_779_DATA
+			DDRSS3_PHY_780_DATA
+			DDRSS3_PHY_781_DATA
+			DDRSS3_PHY_782_DATA
+			DDRSS3_PHY_783_DATA
+			DDRSS3_PHY_784_DATA
+			DDRSS3_PHY_785_DATA
+			DDRSS3_PHY_786_DATA
+			DDRSS3_PHY_787_DATA
+			DDRSS3_PHY_788_DATA
+			DDRSS3_PHY_789_DATA
+			DDRSS3_PHY_790_DATA
+			DDRSS3_PHY_791_DATA
+			DDRSS3_PHY_792_DATA
+			DDRSS3_PHY_793_DATA
+			DDRSS3_PHY_794_DATA
+			DDRSS3_PHY_795_DATA
+			DDRSS3_PHY_796_DATA
+			DDRSS3_PHY_797_DATA
+			DDRSS3_PHY_798_DATA
+			DDRSS3_PHY_799_DATA
+			DDRSS3_PHY_800_DATA
+			DDRSS3_PHY_801_DATA
+			DDRSS3_PHY_802_DATA
+			DDRSS3_PHY_803_DATA
+			DDRSS3_PHY_804_DATA
+			DDRSS3_PHY_805_DATA
+			DDRSS3_PHY_806_DATA
+			DDRSS3_PHY_807_DATA
+			DDRSS3_PHY_808_DATA
+			DDRSS3_PHY_809_DATA
+			DDRSS3_PHY_810_DATA
+			DDRSS3_PHY_811_DATA
+			DDRSS3_PHY_812_DATA
+			DDRSS3_PHY_813_DATA
+			DDRSS3_PHY_814_DATA
+			DDRSS3_PHY_815_DATA
+			DDRSS3_PHY_816_DATA
+			DDRSS3_PHY_817_DATA
+			DDRSS3_PHY_818_DATA
+			DDRSS3_PHY_819_DATA
+			DDRSS3_PHY_820_DATA
+			DDRSS3_PHY_821_DATA
+			DDRSS3_PHY_822_DATA
+			DDRSS3_PHY_823_DATA
+			DDRSS3_PHY_824_DATA
+			DDRSS3_PHY_825_DATA
+			DDRSS3_PHY_826_DATA
+			DDRSS3_PHY_827_DATA
+			DDRSS3_PHY_828_DATA
+			DDRSS3_PHY_829_DATA
+			DDRSS3_PHY_830_DATA
+			DDRSS3_PHY_831_DATA
+			DDRSS3_PHY_832_DATA
+			DDRSS3_PHY_833_DATA
+			DDRSS3_PHY_834_DATA
+			DDRSS3_PHY_835_DATA
+			DDRSS3_PHY_836_DATA
+			DDRSS3_PHY_837_DATA
+			DDRSS3_PHY_838_DATA
+			DDRSS3_PHY_839_DATA
+			DDRSS3_PHY_840_DATA
+			DDRSS3_PHY_841_DATA
+			DDRSS3_PHY_842_DATA
+			DDRSS3_PHY_843_DATA
+			DDRSS3_PHY_844_DATA
+			DDRSS3_PHY_845_DATA
+			DDRSS3_PHY_846_DATA
+			DDRSS3_PHY_847_DATA
+			DDRSS3_PHY_848_DATA
+			DDRSS3_PHY_849_DATA
+			DDRSS3_PHY_850_DATA
+			DDRSS3_PHY_851_DATA
+			DDRSS3_PHY_852_DATA
+			DDRSS3_PHY_853_DATA
+			DDRSS3_PHY_854_DATA
+			DDRSS3_PHY_855_DATA
+			DDRSS3_PHY_856_DATA
+			DDRSS3_PHY_857_DATA
+			DDRSS3_PHY_858_DATA
+			DDRSS3_PHY_859_DATA
+			DDRSS3_PHY_860_DATA
+			DDRSS3_PHY_861_DATA
+			DDRSS3_PHY_862_DATA
+			DDRSS3_PHY_863_DATA
+			DDRSS3_PHY_864_DATA
+			DDRSS3_PHY_865_DATA
+			DDRSS3_PHY_866_DATA
+			DDRSS3_PHY_867_DATA
+			DDRSS3_PHY_868_DATA
+			DDRSS3_PHY_869_DATA
+			DDRSS3_PHY_870_DATA
+			DDRSS3_PHY_871_DATA
+			DDRSS3_PHY_872_DATA
+			DDRSS3_PHY_873_DATA
+			DDRSS3_PHY_874_DATA
+			DDRSS3_PHY_875_DATA
+			DDRSS3_PHY_876_DATA
+			DDRSS3_PHY_877_DATA
+			DDRSS3_PHY_878_DATA
+			DDRSS3_PHY_879_DATA
+			DDRSS3_PHY_880_DATA
+			DDRSS3_PHY_881_DATA
+			DDRSS3_PHY_882_DATA
+			DDRSS3_PHY_883_DATA
+			DDRSS3_PHY_884_DATA
+			DDRSS3_PHY_885_DATA
+			DDRSS3_PHY_886_DATA
+			DDRSS3_PHY_887_DATA
+			DDRSS3_PHY_888_DATA
+			DDRSS3_PHY_889_DATA
+			DDRSS3_PHY_890_DATA
+			DDRSS3_PHY_891_DATA
+			DDRSS3_PHY_892_DATA
+			DDRSS3_PHY_893_DATA
+			DDRSS3_PHY_894_DATA
+			DDRSS3_PHY_895_DATA
+			DDRSS3_PHY_896_DATA
+			DDRSS3_PHY_897_DATA
+			DDRSS3_PHY_898_DATA
+			DDRSS3_PHY_899_DATA
+			DDRSS3_PHY_900_DATA
+			DDRSS3_PHY_901_DATA
+			DDRSS3_PHY_902_DATA
+			DDRSS3_PHY_903_DATA
+			DDRSS3_PHY_904_DATA
+			DDRSS3_PHY_905_DATA
+			DDRSS3_PHY_906_DATA
+			DDRSS3_PHY_907_DATA
+			DDRSS3_PHY_908_DATA
+			DDRSS3_PHY_909_DATA
+			DDRSS3_PHY_910_DATA
+			DDRSS3_PHY_911_DATA
+			DDRSS3_PHY_912_DATA
+			DDRSS3_PHY_913_DATA
+			DDRSS3_PHY_914_DATA
+			DDRSS3_PHY_915_DATA
+			DDRSS3_PHY_916_DATA
+			DDRSS3_PHY_917_DATA
+			DDRSS3_PHY_918_DATA
+			DDRSS3_PHY_919_DATA
+			DDRSS3_PHY_920_DATA
+			DDRSS3_PHY_921_DATA
+			DDRSS3_PHY_922_DATA
+			DDRSS3_PHY_923_DATA
+			DDRSS3_PHY_924_DATA
+			DDRSS3_PHY_925_DATA
+			DDRSS3_PHY_926_DATA
+			DDRSS3_PHY_927_DATA
+			DDRSS3_PHY_928_DATA
+			DDRSS3_PHY_929_DATA
+			DDRSS3_PHY_930_DATA
+			DDRSS3_PHY_931_DATA
+			DDRSS3_PHY_932_DATA
+			DDRSS3_PHY_933_DATA
+			DDRSS3_PHY_934_DATA
+			DDRSS3_PHY_935_DATA
+			DDRSS3_PHY_936_DATA
+			DDRSS3_PHY_937_DATA
+			DDRSS3_PHY_938_DATA
+			DDRSS3_PHY_939_DATA
+			DDRSS3_PHY_940_DATA
+			DDRSS3_PHY_941_DATA
+			DDRSS3_PHY_942_DATA
+			DDRSS3_PHY_943_DATA
+			DDRSS3_PHY_944_DATA
+			DDRSS3_PHY_945_DATA
+			DDRSS3_PHY_946_DATA
+			DDRSS3_PHY_947_DATA
+			DDRSS3_PHY_948_DATA
+			DDRSS3_PHY_949_DATA
+			DDRSS3_PHY_950_DATA
+			DDRSS3_PHY_951_DATA
+			DDRSS3_PHY_952_DATA
+			DDRSS3_PHY_953_DATA
+			DDRSS3_PHY_954_DATA
+			DDRSS3_PHY_955_DATA
+			DDRSS3_PHY_956_DATA
+			DDRSS3_PHY_957_DATA
+			DDRSS3_PHY_958_DATA
+			DDRSS3_PHY_959_DATA
+			DDRSS3_PHY_960_DATA
+			DDRSS3_PHY_961_DATA
+			DDRSS3_PHY_962_DATA
+			DDRSS3_PHY_963_DATA
+			DDRSS3_PHY_964_DATA
+			DDRSS3_PHY_965_DATA
+			DDRSS3_PHY_966_DATA
+			DDRSS3_PHY_967_DATA
+			DDRSS3_PHY_968_DATA
+			DDRSS3_PHY_969_DATA
+			DDRSS3_PHY_970_DATA
+			DDRSS3_PHY_971_DATA
+			DDRSS3_PHY_972_DATA
+			DDRSS3_PHY_973_DATA
+			DDRSS3_PHY_974_DATA
+			DDRSS3_PHY_975_DATA
+			DDRSS3_PHY_976_DATA
+			DDRSS3_PHY_977_DATA
+			DDRSS3_PHY_978_DATA
+			DDRSS3_PHY_979_DATA
+			DDRSS3_PHY_980_DATA
+			DDRSS3_PHY_981_DATA
+			DDRSS3_PHY_982_DATA
+			DDRSS3_PHY_983_DATA
+			DDRSS3_PHY_984_DATA
+			DDRSS3_PHY_985_DATA
+			DDRSS3_PHY_986_DATA
+			DDRSS3_PHY_987_DATA
+			DDRSS3_PHY_988_DATA
+			DDRSS3_PHY_989_DATA
+			DDRSS3_PHY_990_DATA
+			DDRSS3_PHY_991_DATA
+			DDRSS3_PHY_992_DATA
+			DDRSS3_PHY_993_DATA
+			DDRSS3_PHY_994_DATA
+			DDRSS3_PHY_995_DATA
+			DDRSS3_PHY_996_DATA
+			DDRSS3_PHY_997_DATA
+			DDRSS3_PHY_998_DATA
+			DDRSS3_PHY_999_DATA
+			DDRSS3_PHY_1000_DATA
+			DDRSS3_PHY_1001_DATA
+			DDRSS3_PHY_1002_DATA
+			DDRSS3_PHY_1003_DATA
+			DDRSS3_PHY_1004_DATA
+			DDRSS3_PHY_1005_DATA
+			DDRSS3_PHY_1006_DATA
+			DDRSS3_PHY_1007_DATA
+			DDRSS3_PHY_1008_DATA
+			DDRSS3_PHY_1009_DATA
+			DDRSS3_PHY_1010_DATA
+			DDRSS3_PHY_1011_DATA
+			DDRSS3_PHY_1012_DATA
+			DDRSS3_PHY_1013_DATA
+			DDRSS3_PHY_1014_DATA
+			DDRSS3_PHY_1015_DATA
+			DDRSS3_PHY_1016_DATA
+			DDRSS3_PHY_1017_DATA
+			DDRSS3_PHY_1018_DATA
+			DDRSS3_PHY_1019_DATA
+			DDRSS3_PHY_1020_DATA
+			DDRSS3_PHY_1021_DATA
+			DDRSS3_PHY_1022_DATA
+			DDRSS3_PHY_1023_DATA
+			DDRSS3_PHY_1024_DATA
+			DDRSS3_PHY_1025_DATA
+			DDRSS3_PHY_1026_DATA
+			DDRSS3_PHY_1027_DATA
+			DDRSS3_PHY_1028_DATA
+			DDRSS3_PHY_1029_DATA
+			DDRSS3_PHY_1030_DATA
+			DDRSS3_PHY_1031_DATA
+			DDRSS3_PHY_1032_DATA
+			DDRSS3_PHY_1033_DATA
+			DDRSS3_PHY_1034_DATA
+			DDRSS3_PHY_1035_DATA
+			DDRSS3_PHY_1036_DATA
+			DDRSS3_PHY_1037_DATA
+			DDRSS3_PHY_1038_DATA
+			DDRSS3_PHY_1039_DATA
+			DDRSS3_PHY_1040_DATA
+			DDRSS3_PHY_1041_DATA
+			DDRSS3_PHY_1042_DATA
+			DDRSS3_PHY_1043_DATA
+			DDRSS3_PHY_1044_DATA
+			DDRSS3_PHY_1045_DATA
+			DDRSS3_PHY_1046_DATA
+			DDRSS3_PHY_1047_DATA
+			DDRSS3_PHY_1048_DATA
+			DDRSS3_PHY_1049_DATA
+			DDRSS3_PHY_1050_DATA
+			DDRSS3_PHY_1051_DATA
+			DDRSS3_PHY_1052_DATA
+			DDRSS3_PHY_1053_DATA
+			DDRSS3_PHY_1054_DATA
+			DDRSS3_PHY_1055_DATA
+			DDRSS3_PHY_1056_DATA
+			DDRSS3_PHY_1057_DATA
+			DDRSS3_PHY_1058_DATA
+			DDRSS3_PHY_1059_DATA
+			DDRSS3_PHY_1060_DATA
+			DDRSS3_PHY_1061_DATA
+			DDRSS3_PHY_1062_DATA
+			DDRSS3_PHY_1063_DATA
+			DDRSS3_PHY_1064_DATA
+			DDRSS3_PHY_1065_DATA
+			DDRSS3_PHY_1066_DATA
+			DDRSS3_PHY_1067_DATA
+			DDRSS3_PHY_1068_DATA
+			DDRSS3_PHY_1069_DATA
+			DDRSS3_PHY_1070_DATA
+			DDRSS3_PHY_1071_DATA
+			DDRSS3_PHY_1072_DATA
+			DDRSS3_PHY_1073_DATA
+			DDRSS3_PHY_1074_DATA
+			DDRSS3_PHY_1075_DATA
+			DDRSS3_PHY_1076_DATA
+			DDRSS3_PHY_1077_DATA
+			DDRSS3_PHY_1078_DATA
+			DDRSS3_PHY_1079_DATA
+			DDRSS3_PHY_1080_DATA
+			DDRSS3_PHY_1081_DATA
+			DDRSS3_PHY_1082_DATA
+			DDRSS3_PHY_1083_DATA
+			DDRSS3_PHY_1084_DATA
+			DDRSS3_PHY_1085_DATA
+			DDRSS3_PHY_1086_DATA
+			DDRSS3_PHY_1087_DATA
+			DDRSS3_PHY_1088_DATA
+			DDRSS3_PHY_1089_DATA
+			DDRSS3_PHY_1090_DATA
+			DDRSS3_PHY_1091_DATA
+			DDRSS3_PHY_1092_DATA
+			DDRSS3_PHY_1093_DATA
+			DDRSS3_PHY_1094_DATA
+			DDRSS3_PHY_1095_DATA
+			DDRSS3_PHY_1096_DATA
+			DDRSS3_PHY_1097_DATA
+			DDRSS3_PHY_1098_DATA
+			DDRSS3_PHY_1099_DATA
+			DDRSS3_PHY_1100_DATA
+			DDRSS3_PHY_1101_DATA
+			DDRSS3_PHY_1102_DATA
+			DDRSS3_PHY_1103_DATA
+			DDRSS3_PHY_1104_DATA
+			DDRSS3_PHY_1105_DATA
+			DDRSS3_PHY_1106_DATA
+			DDRSS3_PHY_1107_DATA
+			DDRSS3_PHY_1108_DATA
+			DDRSS3_PHY_1109_DATA
+			DDRSS3_PHY_1110_DATA
+			DDRSS3_PHY_1111_DATA
+			DDRSS3_PHY_1112_DATA
+			DDRSS3_PHY_1113_DATA
+			DDRSS3_PHY_1114_DATA
+			DDRSS3_PHY_1115_DATA
+			DDRSS3_PHY_1116_DATA
+			DDRSS3_PHY_1117_DATA
+			DDRSS3_PHY_1118_DATA
+			DDRSS3_PHY_1119_DATA
+			DDRSS3_PHY_1120_DATA
+			DDRSS3_PHY_1121_DATA
+			DDRSS3_PHY_1122_DATA
+			DDRSS3_PHY_1123_DATA
+			DDRSS3_PHY_1124_DATA
+			DDRSS3_PHY_1125_DATA
+			DDRSS3_PHY_1126_DATA
+			DDRSS3_PHY_1127_DATA
+			DDRSS3_PHY_1128_DATA
+			DDRSS3_PHY_1129_DATA
+			DDRSS3_PHY_1130_DATA
+			DDRSS3_PHY_1131_DATA
+			DDRSS3_PHY_1132_DATA
+			DDRSS3_PHY_1133_DATA
+			DDRSS3_PHY_1134_DATA
+			DDRSS3_PHY_1135_DATA
+			DDRSS3_PHY_1136_DATA
+			DDRSS3_PHY_1137_DATA
+			DDRSS3_PHY_1138_DATA
+			DDRSS3_PHY_1139_DATA
+			DDRSS3_PHY_1140_DATA
+			DDRSS3_PHY_1141_DATA
+			DDRSS3_PHY_1142_DATA
+			DDRSS3_PHY_1143_DATA
+			DDRSS3_PHY_1144_DATA
+			DDRSS3_PHY_1145_DATA
+			DDRSS3_PHY_1146_DATA
+			DDRSS3_PHY_1147_DATA
+			DDRSS3_PHY_1148_DATA
+			DDRSS3_PHY_1149_DATA
+			DDRSS3_PHY_1150_DATA
+			DDRSS3_PHY_1151_DATA
+			DDRSS3_PHY_1152_DATA
+			DDRSS3_PHY_1153_DATA
+			DDRSS3_PHY_1154_DATA
+			DDRSS3_PHY_1155_DATA
+			DDRSS3_PHY_1156_DATA
+			DDRSS3_PHY_1157_DATA
+			DDRSS3_PHY_1158_DATA
+			DDRSS3_PHY_1159_DATA
+			DDRSS3_PHY_1160_DATA
+			DDRSS3_PHY_1161_DATA
+			DDRSS3_PHY_1162_DATA
+			DDRSS3_PHY_1163_DATA
+			DDRSS3_PHY_1164_DATA
+			DDRSS3_PHY_1165_DATA
+			DDRSS3_PHY_1166_DATA
+			DDRSS3_PHY_1167_DATA
+			DDRSS3_PHY_1168_DATA
+			DDRSS3_PHY_1169_DATA
+			DDRSS3_PHY_1170_DATA
+			DDRSS3_PHY_1171_DATA
+			DDRSS3_PHY_1172_DATA
+			DDRSS3_PHY_1173_DATA
+			DDRSS3_PHY_1174_DATA
+			DDRSS3_PHY_1175_DATA
+			DDRSS3_PHY_1176_DATA
+			DDRSS3_PHY_1177_DATA
+			DDRSS3_PHY_1178_DATA
+			DDRSS3_PHY_1179_DATA
+			DDRSS3_PHY_1180_DATA
+			DDRSS3_PHY_1181_DATA
+			DDRSS3_PHY_1182_DATA
+			DDRSS3_PHY_1183_DATA
+			DDRSS3_PHY_1184_DATA
+			DDRSS3_PHY_1185_DATA
+			DDRSS3_PHY_1186_DATA
+			DDRSS3_PHY_1187_DATA
+			DDRSS3_PHY_1188_DATA
+			DDRSS3_PHY_1189_DATA
+			DDRSS3_PHY_1190_DATA
+			DDRSS3_PHY_1191_DATA
+			DDRSS3_PHY_1192_DATA
+			DDRSS3_PHY_1193_DATA
+			DDRSS3_PHY_1194_DATA
+			DDRSS3_PHY_1195_DATA
+			DDRSS3_PHY_1196_DATA
+			DDRSS3_PHY_1197_DATA
+			DDRSS3_PHY_1198_DATA
+			DDRSS3_PHY_1199_DATA
+			DDRSS3_PHY_1200_DATA
+			DDRSS3_PHY_1201_DATA
+			DDRSS3_PHY_1202_DATA
+			DDRSS3_PHY_1203_DATA
+			DDRSS3_PHY_1204_DATA
+			DDRSS3_PHY_1205_DATA
+			DDRSS3_PHY_1206_DATA
+			DDRSS3_PHY_1207_DATA
+			DDRSS3_PHY_1208_DATA
+			DDRSS3_PHY_1209_DATA
+			DDRSS3_PHY_1210_DATA
+			DDRSS3_PHY_1211_DATA
+			DDRSS3_PHY_1212_DATA
+			DDRSS3_PHY_1213_DATA
+			DDRSS3_PHY_1214_DATA
+			DDRSS3_PHY_1215_DATA
+			DDRSS3_PHY_1216_DATA
+			DDRSS3_PHY_1217_DATA
+			DDRSS3_PHY_1218_DATA
+			DDRSS3_PHY_1219_DATA
+			DDRSS3_PHY_1220_DATA
+			DDRSS3_PHY_1221_DATA
+			DDRSS3_PHY_1222_DATA
+			DDRSS3_PHY_1223_DATA
+			DDRSS3_PHY_1224_DATA
+			DDRSS3_PHY_1225_DATA
+			DDRSS3_PHY_1226_DATA
+			DDRSS3_PHY_1227_DATA
+			DDRSS3_PHY_1228_DATA
+			DDRSS3_PHY_1229_DATA
+			DDRSS3_PHY_1230_DATA
+			DDRSS3_PHY_1231_DATA
+			DDRSS3_PHY_1232_DATA
+			DDRSS3_PHY_1233_DATA
+			DDRSS3_PHY_1234_DATA
+			DDRSS3_PHY_1235_DATA
+			DDRSS3_PHY_1236_DATA
+			DDRSS3_PHY_1237_DATA
+			DDRSS3_PHY_1238_DATA
+			DDRSS3_PHY_1239_DATA
+			DDRSS3_PHY_1240_DATA
+			DDRSS3_PHY_1241_DATA
+			DDRSS3_PHY_1242_DATA
+			DDRSS3_PHY_1243_DATA
+			DDRSS3_PHY_1244_DATA
+			DDRSS3_PHY_1245_DATA
+			DDRSS3_PHY_1246_DATA
+			DDRSS3_PHY_1247_DATA
+			DDRSS3_PHY_1248_DATA
+			DDRSS3_PHY_1249_DATA
+			DDRSS3_PHY_1250_DATA
+			DDRSS3_PHY_1251_DATA
+			DDRSS3_PHY_1252_DATA
+			DDRSS3_PHY_1253_DATA
+			DDRSS3_PHY_1254_DATA
+			DDRSS3_PHY_1255_DATA
+			DDRSS3_PHY_1256_DATA
+			DDRSS3_PHY_1257_DATA
+			DDRSS3_PHY_1258_DATA
+			DDRSS3_PHY_1259_DATA
+			DDRSS3_PHY_1260_DATA
+			DDRSS3_PHY_1261_DATA
+			DDRSS3_PHY_1262_DATA
+			DDRSS3_PHY_1263_DATA
+			DDRSS3_PHY_1264_DATA
+			DDRSS3_PHY_1265_DATA
+			DDRSS3_PHY_1266_DATA
+			DDRSS3_PHY_1267_DATA
+			DDRSS3_PHY_1268_DATA
+			DDRSS3_PHY_1269_DATA
+			DDRSS3_PHY_1270_DATA
+			DDRSS3_PHY_1271_DATA
+			DDRSS3_PHY_1272_DATA
+			DDRSS3_PHY_1273_DATA
+			DDRSS3_PHY_1274_DATA
+			DDRSS3_PHY_1275_DATA
+			DDRSS3_PHY_1276_DATA
+			DDRSS3_PHY_1277_DATA
+			DDRSS3_PHY_1278_DATA
+			DDRSS3_PHY_1279_DATA
+			DDRSS3_PHY_1280_DATA
+			DDRSS3_PHY_1281_DATA
+			DDRSS3_PHY_1282_DATA
+			DDRSS3_PHY_1283_DATA
+			DDRSS3_PHY_1284_DATA
+			DDRSS3_PHY_1285_DATA
+			DDRSS3_PHY_1286_DATA
+			DDRSS3_PHY_1287_DATA
+			DDRSS3_PHY_1288_DATA
+			DDRSS3_PHY_1289_DATA
+			DDRSS3_PHY_1290_DATA
+			DDRSS3_PHY_1291_DATA
+			DDRSS3_PHY_1292_DATA
+			DDRSS3_PHY_1293_DATA
+			DDRSS3_PHY_1294_DATA
+			DDRSS3_PHY_1295_DATA
+			DDRSS3_PHY_1296_DATA
+			DDRSS3_PHY_1297_DATA
+			DDRSS3_PHY_1298_DATA
+			DDRSS3_PHY_1299_DATA
+			DDRSS3_PHY_1300_DATA
+			DDRSS3_PHY_1301_DATA
+			DDRSS3_PHY_1302_DATA
+			DDRSS3_PHY_1303_DATA
+			DDRSS3_PHY_1304_DATA
+			DDRSS3_PHY_1305_DATA
+			DDRSS3_PHY_1306_DATA
+			DDRSS3_PHY_1307_DATA
+			DDRSS3_PHY_1308_DATA
+			DDRSS3_PHY_1309_DATA
+			DDRSS3_PHY_1310_DATA
+			DDRSS3_PHY_1311_DATA
+			DDRSS3_PHY_1312_DATA
+			DDRSS3_PHY_1313_DATA
+			DDRSS3_PHY_1314_DATA
+			DDRSS3_PHY_1315_DATA
+			DDRSS3_PHY_1316_DATA
+			DDRSS3_PHY_1317_DATA
+			DDRSS3_PHY_1318_DATA
+			DDRSS3_PHY_1319_DATA
+			DDRSS3_PHY_1320_DATA
+			DDRSS3_PHY_1321_DATA
+			DDRSS3_PHY_1322_DATA
+			DDRSS3_PHY_1323_DATA
+			DDRSS3_PHY_1324_DATA
+			DDRSS3_PHY_1325_DATA
+			DDRSS3_PHY_1326_DATA
+			DDRSS3_PHY_1327_DATA
+			DDRSS3_PHY_1328_DATA
+			DDRSS3_PHY_1329_DATA
+			DDRSS3_PHY_1330_DATA
+			DDRSS3_PHY_1331_DATA
+			DDRSS3_PHY_1332_DATA
+			DDRSS3_PHY_1333_DATA
+			DDRSS3_PHY_1334_DATA
+			DDRSS3_PHY_1335_DATA
+			DDRSS3_PHY_1336_DATA
+			DDRSS3_PHY_1337_DATA
+			DDRSS3_PHY_1338_DATA
+			DDRSS3_PHY_1339_DATA
+			DDRSS3_PHY_1340_DATA
+			DDRSS3_PHY_1341_DATA
+			DDRSS3_PHY_1342_DATA
+			DDRSS3_PHY_1343_DATA
+			DDRSS3_PHY_1344_DATA
+			DDRSS3_PHY_1345_DATA
+			DDRSS3_PHY_1346_DATA
+			DDRSS3_PHY_1347_DATA
+			DDRSS3_PHY_1348_DATA
+			DDRSS3_PHY_1349_DATA
+			DDRSS3_PHY_1350_DATA
+			DDRSS3_PHY_1351_DATA
+			DDRSS3_PHY_1352_DATA
+			DDRSS3_PHY_1353_DATA
+			DDRSS3_PHY_1354_DATA
+			DDRSS3_PHY_1355_DATA
+			DDRSS3_PHY_1356_DATA
+			DDRSS3_PHY_1357_DATA
+			DDRSS3_PHY_1358_DATA
+			DDRSS3_PHY_1359_DATA
+			DDRSS3_PHY_1360_DATA
+			DDRSS3_PHY_1361_DATA
+			DDRSS3_PHY_1362_DATA
+			DDRSS3_PHY_1363_DATA
+			DDRSS3_PHY_1364_DATA
+			DDRSS3_PHY_1365_DATA
+			DDRSS3_PHY_1366_DATA
+			DDRSS3_PHY_1367_DATA
+			DDRSS3_PHY_1368_DATA
+			DDRSS3_PHY_1369_DATA
+			DDRSS3_PHY_1370_DATA
+			DDRSS3_PHY_1371_DATA
+			DDRSS3_PHY_1372_DATA
+			DDRSS3_PHY_1373_DATA
+			DDRSS3_PHY_1374_DATA
+			DDRSS3_PHY_1375_DATA
+			DDRSS3_PHY_1376_DATA
+			DDRSS3_PHY_1377_DATA
+			DDRSS3_PHY_1378_DATA
+			DDRSS3_PHY_1379_DATA
+			DDRSS3_PHY_1380_DATA
+			DDRSS3_PHY_1381_DATA
+			DDRSS3_PHY_1382_DATA
+			DDRSS3_PHY_1383_DATA
+			DDRSS3_PHY_1384_DATA
+			DDRSS3_PHY_1385_DATA
+			DDRSS3_PHY_1386_DATA
+			DDRSS3_PHY_1387_DATA
+			DDRSS3_PHY_1388_DATA
+			DDRSS3_PHY_1389_DATA
+			DDRSS3_PHY_1390_DATA
+			DDRSS3_PHY_1391_DATA
+			DDRSS3_PHY_1392_DATA
+			DDRSS3_PHY_1393_DATA
+			DDRSS3_PHY_1394_DATA
+			DDRSS3_PHY_1395_DATA
+			DDRSS3_PHY_1396_DATA
+			DDRSS3_PHY_1397_DATA
+			DDRSS3_PHY_1398_DATA
+			DDRSS3_PHY_1399_DATA
+			DDRSS3_PHY_1400_DATA
+			DDRSS3_PHY_1401_DATA
+			DDRSS3_PHY_1402_DATA
+			DDRSS3_PHY_1403_DATA
+			DDRSS3_PHY_1404_DATA
+			DDRSS3_PHY_1405_DATA
+			DDRSS3_PHY_1406_DATA
+			DDRSS3_PHY_1407_DATA
+			DDRSS3_PHY_1408_DATA
+			DDRSS3_PHY_1409_DATA
+			DDRSS3_PHY_1410_DATA
+			DDRSS3_PHY_1411_DATA
+			DDRSS3_PHY_1412_DATA
+			DDRSS3_PHY_1413_DATA
+			DDRSS3_PHY_1414_DATA
+			DDRSS3_PHY_1415_DATA
+			DDRSS3_PHY_1416_DATA
+			DDRSS3_PHY_1417_DATA
+			DDRSS3_PHY_1418_DATA
+			DDRSS3_PHY_1419_DATA
+			DDRSS3_PHY_1420_DATA
+			DDRSS3_PHY_1421_DATA
+			DDRSS3_PHY_1422_DATA
+		>;
 	};
 };
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 8f0307321e8..8a60d7c6107 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -3,8 +3,83 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#define SPL_BOARD_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
+#define BOARD_DESCRIPTION "k3-j784s4-evm"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for J784S4 board"
+
 #include "k3-j784s4-binman.dtsi"
 
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-j784s4-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j784s4-hs-evm.bin";
+	};
+
+	tiboot3-j784s4-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j784s4-hs-fs-evm.bin";
+	};
+
+	tiboot3-j784s4-gp {
+		insert-template = <&tiboot3_j784s4_gp>;
+		filename = "tiboot3-j784s4-gp-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_gp {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
+
 / {
 	memory@80000000 {
 		bootph-all;
diff --git a/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
new file mode 100644
index 00000000000..c03eddcb560
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
@@ -0,0 +1,4448 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&main_navss {
+	ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+		 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
+		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
+		 <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
+		 <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
+		 <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
+		 <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
+		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+
+	msmc0: msmc {
+		compatible = "ti,j721s2-msmc";
+		intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
+		intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
+		ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
+		emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
+		emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		bootph-pre-ram;
+
+		memorycontroller0: memorycontroller@2990000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x02990000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+				  <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+				<&k3_pds 131 TI_SCI_PD_SHARED>;
+			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
+			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+			instance = <0>;
+
+			bootph-pre-ram;
+
+			ti,ctl-data = <
+				DDRSS0_CTL_00_DATA
+				DDRSS0_CTL_01_DATA
+				DDRSS0_CTL_02_DATA
+				DDRSS0_CTL_03_DATA
+				DDRSS0_CTL_04_DATA
+				DDRSS0_CTL_05_DATA
+				DDRSS0_CTL_06_DATA
+				DDRSS0_CTL_07_DATA
+				DDRSS0_CTL_08_DATA
+				DDRSS0_CTL_09_DATA
+				DDRSS0_CTL_10_DATA
+				DDRSS0_CTL_11_DATA
+				DDRSS0_CTL_12_DATA
+				DDRSS0_CTL_13_DATA
+				DDRSS0_CTL_14_DATA
+				DDRSS0_CTL_15_DATA
+				DDRSS0_CTL_16_DATA
+				DDRSS0_CTL_17_DATA
+				DDRSS0_CTL_18_DATA
+				DDRSS0_CTL_19_DATA
+				DDRSS0_CTL_20_DATA
+				DDRSS0_CTL_21_DATA
+				DDRSS0_CTL_22_DATA
+				DDRSS0_CTL_23_DATA
+				DDRSS0_CTL_24_DATA
+				DDRSS0_CTL_25_DATA
+				DDRSS0_CTL_26_DATA
+				DDRSS0_CTL_27_DATA
+				DDRSS0_CTL_28_DATA
+				DDRSS0_CTL_29_DATA
+				DDRSS0_CTL_30_DATA
+				DDRSS0_CTL_31_DATA
+				DDRSS0_CTL_32_DATA
+				DDRSS0_CTL_33_DATA
+				DDRSS0_CTL_34_DATA
+				DDRSS0_CTL_35_DATA
+				DDRSS0_CTL_36_DATA
+				DDRSS0_CTL_37_DATA
+				DDRSS0_CTL_38_DATA
+				DDRSS0_CTL_39_DATA
+				DDRSS0_CTL_40_DATA
+				DDRSS0_CTL_41_DATA
+				DDRSS0_CTL_42_DATA
+				DDRSS0_CTL_43_DATA
+				DDRSS0_CTL_44_DATA
+				DDRSS0_CTL_45_DATA
+				DDRSS0_CTL_46_DATA
+				DDRSS0_CTL_47_DATA
+				DDRSS0_CTL_48_DATA
+				DDRSS0_CTL_49_DATA
+				DDRSS0_CTL_50_DATA
+				DDRSS0_CTL_51_DATA
+				DDRSS0_CTL_52_DATA
+				DDRSS0_CTL_53_DATA
+				DDRSS0_CTL_54_DATA
+				DDRSS0_CTL_55_DATA
+				DDRSS0_CTL_56_DATA
+				DDRSS0_CTL_57_DATA
+				DDRSS0_CTL_58_DATA
+				DDRSS0_CTL_59_DATA
+				DDRSS0_CTL_60_DATA
+				DDRSS0_CTL_61_DATA
+				DDRSS0_CTL_62_DATA
+				DDRSS0_CTL_63_DATA
+				DDRSS0_CTL_64_DATA
+				DDRSS0_CTL_65_DATA
+				DDRSS0_CTL_66_DATA
+				DDRSS0_CTL_67_DATA
+				DDRSS0_CTL_68_DATA
+				DDRSS0_CTL_69_DATA
+				DDRSS0_CTL_70_DATA
+				DDRSS0_CTL_71_DATA
+				DDRSS0_CTL_72_DATA
+				DDRSS0_CTL_73_DATA
+				DDRSS0_CTL_74_DATA
+				DDRSS0_CTL_75_DATA
+				DDRSS0_CTL_76_DATA
+				DDRSS0_CTL_77_DATA
+				DDRSS0_CTL_78_DATA
+				DDRSS0_CTL_79_DATA
+				DDRSS0_CTL_80_DATA
+				DDRSS0_CTL_81_DATA
+				DDRSS0_CTL_82_DATA
+				DDRSS0_CTL_83_DATA
+				DDRSS0_CTL_84_DATA
+				DDRSS0_CTL_85_DATA
+				DDRSS0_CTL_86_DATA
+				DDRSS0_CTL_87_DATA
+				DDRSS0_CTL_88_DATA
+				DDRSS0_CTL_89_DATA
+				DDRSS0_CTL_90_DATA
+				DDRSS0_CTL_91_DATA
+				DDRSS0_CTL_92_DATA
+				DDRSS0_CTL_93_DATA
+				DDRSS0_CTL_94_DATA
+				DDRSS0_CTL_95_DATA
+				DDRSS0_CTL_96_DATA
+				DDRSS0_CTL_97_DATA
+				DDRSS0_CTL_98_DATA
+				DDRSS0_CTL_99_DATA
+				DDRSS0_CTL_100_DATA
+				DDRSS0_CTL_101_DATA
+				DDRSS0_CTL_102_DATA
+				DDRSS0_CTL_103_DATA
+				DDRSS0_CTL_104_DATA
+				DDRSS0_CTL_105_DATA
+				DDRSS0_CTL_106_DATA
+				DDRSS0_CTL_107_DATA
+				DDRSS0_CTL_108_DATA
+				DDRSS0_CTL_109_DATA
+				DDRSS0_CTL_110_DATA
+				DDRSS0_CTL_111_DATA
+				DDRSS0_CTL_112_DATA
+				DDRSS0_CTL_113_DATA
+				DDRSS0_CTL_114_DATA
+				DDRSS0_CTL_115_DATA
+				DDRSS0_CTL_116_DATA
+				DDRSS0_CTL_117_DATA
+				DDRSS0_CTL_118_DATA
+				DDRSS0_CTL_119_DATA
+				DDRSS0_CTL_120_DATA
+				DDRSS0_CTL_121_DATA
+				DDRSS0_CTL_122_DATA
+				DDRSS0_CTL_123_DATA
+				DDRSS0_CTL_124_DATA
+				DDRSS0_CTL_125_DATA
+				DDRSS0_CTL_126_DATA
+				DDRSS0_CTL_127_DATA
+				DDRSS0_CTL_128_DATA
+				DDRSS0_CTL_129_DATA
+				DDRSS0_CTL_130_DATA
+				DDRSS0_CTL_131_DATA
+				DDRSS0_CTL_132_DATA
+				DDRSS0_CTL_133_DATA
+				DDRSS0_CTL_134_DATA
+				DDRSS0_CTL_135_DATA
+				DDRSS0_CTL_136_DATA
+				DDRSS0_CTL_137_DATA
+				DDRSS0_CTL_138_DATA
+				DDRSS0_CTL_139_DATA
+				DDRSS0_CTL_140_DATA
+				DDRSS0_CTL_141_DATA
+				DDRSS0_CTL_142_DATA
+				DDRSS0_CTL_143_DATA
+				DDRSS0_CTL_144_DATA
+				DDRSS0_CTL_145_DATA
+				DDRSS0_CTL_146_DATA
+				DDRSS0_CTL_147_DATA
+				DDRSS0_CTL_148_DATA
+				DDRSS0_CTL_149_DATA
+				DDRSS0_CTL_150_DATA
+				DDRSS0_CTL_151_DATA
+				DDRSS0_CTL_152_DATA
+				DDRSS0_CTL_153_DATA
+				DDRSS0_CTL_154_DATA
+				DDRSS0_CTL_155_DATA
+				DDRSS0_CTL_156_DATA
+				DDRSS0_CTL_157_DATA
+				DDRSS0_CTL_158_DATA
+				DDRSS0_CTL_159_DATA
+				DDRSS0_CTL_160_DATA
+				DDRSS0_CTL_161_DATA
+				DDRSS0_CTL_162_DATA
+				DDRSS0_CTL_163_DATA
+				DDRSS0_CTL_164_DATA
+				DDRSS0_CTL_165_DATA
+				DDRSS0_CTL_166_DATA
+				DDRSS0_CTL_167_DATA
+				DDRSS0_CTL_168_DATA
+				DDRSS0_CTL_169_DATA
+				DDRSS0_CTL_170_DATA
+				DDRSS0_CTL_171_DATA
+				DDRSS0_CTL_172_DATA
+				DDRSS0_CTL_173_DATA
+				DDRSS0_CTL_174_DATA
+				DDRSS0_CTL_175_DATA
+				DDRSS0_CTL_176_DATA
+				DDRSS0_CTL_177_DATA
+				DDRSS0_CTL_178_DATA
+				DDRSS0_CTL_179_DATA
+				DDRSS0_CTL_180_DATA
+				DDRSS0_CTL_181_DATA
+				DDRSS0_CTL_182_DATA
+				DDRSS0_CTL_183_DATA
+				DDRSS0_CTL_184_DATA
+				DDRSS0_CTL_185_DATA
+				DDRSS0_CTL_186_DATA
+				DDRSS0_CTL_187_DATA
+				DDRSS0_CTL_188_DATA
+				DDRSS0_CTL_189_DATA
+				DDRSS0_CTL_190_DATA
+				DDRSS0_CTL_191_DATA
+				DDRSS0_CTL_192_DATA
+				DDRSS0_CTL_193_DATA
+				DDRSS0_CTL_194_DATA
+				DDRSS0_CTL_195_DATA
+				DDRSS0_CTL_196_DATA
+				DDRSS0_CTL_197_DATA
+				DDRSS0_CTL_198_DATA
+				DDRSS0_CTL_199_DATA
+				DDRSS0_CTL_200_DATA
+				DDRSS0_CTL_201_DATA
+				DDRSS0_CTL_202_DATA
+				DDRSS0_CTL_203_DATA
+				DDRSS0_CTL_204_DATA
+				DDRSS0_CTL_205_DATA
+				DDRSS0_CTL_206_DATA
+				DDRSS0_CTL_207_DATA
+				DDRSS0_CTL_208_DATA
+				DDRSS0_CTL_209_DATA
+				DDRSS0_CTL_210_DATA
+				DDRSS0_CTL_211_DATA
+				DDRSS0_CTL_212_DATA
+				DDRSS0_CTL_213_DATA
+				DDRSS0_CTL_214_DATA
+				DDRSS0_CTL_215_DATA
+				DDRSS0_CTL_216_DATA
+				DDRSS0_CTL_217_DATA
+				DDRSS0_CTL_218_DATA
+				DDRSS0_CTL_219_DATA
+				DDRSS0_CTL_220_DATA
+				DDRSS0_CTL_221_DATA
+				DDRSS0_CTL_222_DATA
+				DDRSS0_CTL_223_DATA
+				DDRSS0_CTL_224_DATA
+				DDRSS0_CTL_225_DATA
+				DDRSS0_CTL_226_DATA
+				DDRSS0_CTL_227_DATA
+				DDRSS0_CTL_228_DATA
+				DDRSS0_CTL_229_DATA
+				DDRSS0_CTL_230_DATA
+				DDRSS0_CTL_231_DATA
+				DDRSS0_CTL_232_DATA
+				DDRSS0_CTL_233_DATA
+				DDRSS0_CTL_234_DATA
+				DDRSS0_CTL_235_DATA
+				DDRSS0_CTL_236_DATA
+				DDRSS0_CTL_237_DATA
+				DDRSS0_CTL_238_DATA
+				DDRSS0_CTL_239_DATA
+				DDRSS0_CTL_240_DATA
+				DDRSS0_CTL_241_DATA
+				DDRSS0_CTL_242_DATA
+				DDRSS0_CTL_243_DATA
+				DDRSS0_CTL_244_DATA
+				DDRSS0_CTL_245_DATA
+				DDRSS0_CTL_246_DATA
+				DDRSS0_CTL_247_DATA
+				DDRSS0_CTL_248_DATA
+				DDRSS0_CTL_249_DATA
+				DDRSS0_CTL_250_DATA
+				DDRSS0_CTL_251_DATA
+				DDRSS0_CTL_252_DATA
+				DDRSS0_CTL_253_DATA
+				DDRSS0_CTL_254_DATA
+				DDRSS0_CTL_255_DATA
+				DDRSS0_CTL_256_DATA
+				DDRSS0_CTL_257_DATA
+				DDRSS0_CTL_258_DATA
+				DDRSS0_CTL_259_DATA
+				DDRSS0_CTL_260_DATA
+				DDRSS0_CTL_261_DATA
+				DDRSS0_CTL_262_DATA
+				DDRSS0_CTL_263_DATA
+				DDRSS0_CTL_264_DATA
+				DDRSS0_CTL_265_DATA
+				DDRSS0_CTL_266_DATA
+				DDRSS0_CTL_267_DATA
+				DDRSS0_CTL_268_DATA
+				DDRSS0_CTL_269_DATA
+				DDRSS0_CTL_270_DATA
+				DDRSS0_CTL_271_DATA
+				DDRSS0_CTL_272_DATA
+				DDRSS0_CTL_273_DATA
+				DDRSS0_CTL_274_DATA
+				DDRSS0_CTL_275_DATA
+				DDRSS0_CTL_276_DATA
+				DDRSS0_CTL_277_DATA
+				DDRSS0_CTL_278_DATA
+				DDRSS0_CTL_279_DATA
+				DDRSS0_CTL_280_DATA
+				DDRSS0_CTL_281_DATA
+				DDRSS0_CTL_282_DATA
+				DDRSS0_CTL_283_DATA
+				DDRSS0_CTL_284_DATA
+				DDRSS0_CTL_285_DATA
+				DDRSS0_CTL_286_DATA
+				DDRSS0_CTL_287_DATA
+				DDRSS0_CTL_288_DATA
+				DDRSS0_CTL_289_DATA
+				DDRSS0_CTL_290_DATA
+				DDRSS0_CTL_291_DATA
+				DDRSS0_CTL_292_DATA
+				DDRSS0_CTL_293_DATA
+				DDRSS0_CTL_294_DATA
+				DDRSS0_CTL_295_DATA
+				DDRSS0_CTL_296_DATA
+				DDRSS0_CTL_297_DATA
+				DDRSS0_CTL_298_DATA
+				DDRSS0_CTL_299_DATA
+				DDRSS0_CTL_300_DATA
+				DDRSS0_CTL_301_DATA
+				DDRSS0_CTL_302_DATA
+				DDRSS0_CTL_303_DATA
+				DDRSS0_CTL_304_DATA
+				DDRSS0_CTL_305_DATA
+				DDRSS0_CTL_306_DATA
+				DDRSS0_CTL_307_DATA
+				DDRSS0_CTL_308_DATA
+				DDRSS0_CTL_309_DATA
+				DDRSS0_CTL_310_DATA
+				DDRSS0_CTL_311_DATA
+				DDRSS0_CTL_312_DATA
+				DDRSS0_CTL_313_DATA
+				DDRSS0_CTL_314_DATA
+				DDRSS0_CTL_315_DATA
+				DDRSS0_CTL_316_DATA
+				DDRSS0_CTL_317_DATA
+				DDRSS0_CTL_318_DATA
+				DDRSS0_CTL_319_DATA
+				DDRSS0_CTL_320_DATA
+				DDRSS0_CTL_321_DATA
+				DDRSS0_CTL_322_DATA
+				DDRSS0_CTL_323_DATA
+				DDRSS0_CTL_324_DATA
+				DDRSS0_CTL_325_DATA
+				DDRSS0_CTL_326_DATA
+				DDRSS0_CTL_327_DATA
+				DDRSS0_CTL_328_DATA
+				DDRSS0_CTL_329_DATA
+				DDRSS0_CTL_330_DATA
+				DDRSS0_CTL_331_DATA
+				DDRSS0_CTL_332_DATA
+				DDRSS0_CTL_333_DATA
+				DDRSS0_CTL_334_DATA
+				DDRSS0_CTL_335_DATA
+				DDRSS0_CTL_336_DATA
+				DDRSS0_CTL_337_DATA
+				DDRSS0_CTL_338_DATA
+				DDRSS0_CTL_339_DATA
+				DDRSS0_CTL_340_DATA
+				DDRSS0_CTL_341_DATA
+				DDRSS0_CTL_342_DATA
+				DDRSS0_CTL_343_DATA
+				DDRSS0_CTL_344_DATA
+				DDRSS0_CTL_345_DATA
+				DDRSS0_CTL_346_DATA
+				DDRSS0_CTL_347_DATA
+				DDRSS0_CTL_348_DATA
+				DDRSS0_CTL_349_DATA
+				DDRSS0_CTL_350_DATA
+				DDRSS0_CTL_351_DATA
+				DDRSS0_CTL_352_DATA
+				DDRSS0_CTL_353_DATA
+				DDRSS0_CTL_354_DATA
+				DDRSS0_CTL_355_DATA
+				DDRSS0_CTL_356_DATA
+				DDRSS0_CTL_357_DATA
+				DDRSS0_CTL_358_DATA
+				DDRSS0_CTL_359_DATA
+				DDRSS0_CTL_360_DATA
+				DDRSS0_CTL_361_DATA
+				DDRSS0_CTL_362_DATA
+				DDRSS0_CTL_363_DATA
+				DDRSS0_CTL_364_DATA
+				DDRSS0_CTL_365_DATA
+				DDRSS0_CTL_366_DATA
+				DDRSS0_CTL_367_DATA
+				DDRSS0_CTL_368_DATA
+				DDRSS0_CTL_369_DATA
+				DDRSS0_CTL_370_DATA
+				DDRSS0_CTL_371_DATA
+				DDRSS0_CTL_372_DATA
+				DDRSS0_CTL_373_DATA
+				DDRSS0_CTL_374_DATA
+				DDRSS0_CTL_375_DATA
+				DDRSS0_CTL_376_DATA
+				DDRSS0_CTL_377_DATA
+				DDRSS0_CTL_378_DATA
+				DDRSS0_CTL_379_DATA
+				DDRSS0_CTL_380_DATA
+				DDRSS0_CTL_381_DATA
+				DDRSS0_CTL_382_DATA
+				DDRSS0_CTL_383_DATA
+				DDRSS0_CTL_384_DATA
+				DDRSS0_CTL_385_DATA
+				DDRSS0_CTL_386_DATA
+				DDRSS0_CTL_387_DATA
+				DDRSS0_CTL_388_DATA
+				DDRSS0_CTL_389_DATA
+				DDRSS0_CTL_390_DATA
+				DDRSS0_CTL_391_DATA
+				DDRSS0_CTL_392_DATA
+				DDRSS0_CTL_393_DATA
+				DDRSS0_CTL_394_DATA
+				DDRSS0_CTL_395_DATA
+				DDRSS0_CTL_396_DATA
+				DDRSS0_CTL_397_DATA
+				DDRSS0_CTL_398_DATA
+				DDRSS0_CTL_399_DATA
+				DDRSS0_CTL_400_DATA
+				DDRSS0_CTL_401_DATA
+				DDRSS0_CTL_402_DATA
+				DDRSS0_CTL_403_DATA
+				DDRSS0_CTL_404_DATA
+				DDRSS0_CTL_405_DATA
+				DDRSS0_CTL_406_DATA
+				DDRSS0_CTL_407_DATA
+				DDRSS0_CTL_408_DATA
+				DDRSS0_CTL_409_DATA
+				DDRSS0_CTL_410_DATA
+				DDRSS0_CTL_411_DATA
+				DDRSS0_CTL_412_DATA
+				DDRSS0_CTL_413_DATA
+				DDRSS0_CTL_414_DATA
+				DDRSS0_CTL_415_DATA
+				DDRSS0_CTL_416_DATA
+				DDRSS0_CTL_417_DATA
+				DDRSS0_CTL_418_DATA
+				DDRSS0_CTL_419_DATA
+				DDRSS0_CTL_420_DATA
+				DDRSS0_CTL_421_DATA
+				DDRSS0_CTL_422_DATA
+				DDRSS0_CTL_423_DATA
+				DDRSS0_CTL_424_DATA
+				DDRSS0_CTL_425_DATA
+				DDRSS0_CTL_426_DATA
+				DDRSS0_CTL_427_DATA
+				DDRSS0_CTL_428_DATA
+				DDRSS0_CTL_429_DATA
+				DDRSS0_CTL_430_DATA
+				DDRSS0_CTL_431_DATA
+				DDRSS0_CTL_432_DATA
+				DDRSS0_CTL_433_DATA
+				DDRSS0_CTL_434_DATA
+				DDRSS0_CTL_435_DATA
+				DDRSS0_CTL_436_DATA
+				DDRSS0_CTL_437_DATA
+				DDRSS0_CTL_438_DATA
+				DDRSS0_CTL_439_DATA
+				DDRSS0_CTL_440_DATA
+				DDRSS0_CTL_441_DATA
+				DDRSS0_CTL_442_DATA
+				DDRSS0_CTL_443_DATA
+				DDRSS0_CTL_444_DATA
+				DDRSS0_CTL_445_DATA
+				DDRSS0_CTL_446_DATA
+				DDRSS0_CTL_447_DATA
+				DDRSS0_CTL_448_DATA
+				DDRSS0_CTL_449_DATA
+				DDRSS0_CTL_450_DATA
+				DDRSS0_CTL_451_DATA
+				DDRSS0_CTL_452_DATA
+				DDRSS0_CTL_453_DATA
+				DDRSS0_CTL_454_DATA
+				DDRSS0_CTL_455_DATA
+				DDRSS0_CTL_456_DATA
+				DDRSS0_CTL_457_DATA
+				DDRSS0_CTL_458_DATA
+			>;
+
+			ti,pi-data = <
+				DDRSS0_PI_00_DATA
+				DDRSS0_PI_01_DATA
+				DDRSS0_PI_02_DATA
+				DDRSS0_PI_03_DATA
+				DDRSS0_PI_04_DATA
+				DDRSS0_PI_05_DATA
+				DDRSS0_PI_06_DATA
+				DDRSS0_PI_07_DATA
+				DDRSS0_PI_08_DATA
+				DDRSS0_PI_09_DATA
+				DDRSS0_PI_10_DATA
+				DDRSS0_PI_11_DATA
+				DDRSS0_PI_12_DATA
+				DDRSS0_PI_13_DATA
+				DDRSS0_PI_14_DATA
+				DDRSS0_PI_15_DATA
+				DDRSS0_PI_16_DATA
+				DDRSS0_PI_17_DATA
+				DDRSS0_PI_18_DATA
+				DDRSS0_PI_19_DATA
+				DDRSS0_PI_20_DATA
+				DDRSS0_PI_21_DATA
+				DDRSS0_PI_22_DATA
+				DDRSS0_PI_23_DATA
+				DDRSS0_PI_24_DATA
+				DDRSS0_PI_25_DATA
+				DDRSS0_PI_26_DATA
+				DDRSS0_PI_27_DATA
+				DDRSS0_PI_28_DATA
+				DDRSS0_PI_29_DATA
+				DDRSS0_PI_30_DATA
+				DDRSS0_PI_31_DATA
+				DDRSS0_PI_32_DATA
+				DDRSS0_PI_33_DATA
+				DDRSS0_PI_34_DATA
+				DDRSS0_PI_35_DATA
+				DDRSS0_PI_36_DATA
+				DDRSS0_PI_37_DATA
+				DDRSS0_PI_38_DATA
+				DDRSS0_PI_39_DATA
+				DDRSS0_PI_40_DATA
+				DDRSS0_PI_41_DATA
+				DDRSS0_PI_42_DATA
+				DDRSS0_PI_43_DATA
+				DDRSS0_PI_44_DATA
+				DDRSS0_PI_45_DATA
+				DDRSS0_PI_46_DATA
+				DDRSS0_PI_47_DATA
+				DDRSS0_PI_48_DATA
+				DDRSS0_PI_49_DATA
+				DDRSS0_PI_50_DATA
+				DDRSS0_PI_51_DATA
+				DDRSS0_PI_52_DATA
+				DDRSS0_PI_53_DATA
+				DDRSS0_PI_54_DATA
+				DDRSS0_PI_55_DATA
+				DDRSS0_PI_56_DATA
+				DDRSS0_PI_57_DATA
+				DDRSS0_PI_58_DATA
+				DDRSS0_PI_59_DATA
+				DDRSS0_PI_60_DATA
+				DDRSS0_PI_61_DATA
+				DDRSS0_PI_62_DATA
+				DDRSS0_PI_63_DATA
+				DDRSS0_PI_64_DATA
+				DDRSS0_PI_65_DATA
+				DDRSS0_PI_66_DATA
+				DDRSS0_PI_67_DATA
+				DDRSS0_PI_68_DATA
+				DDRSS0_PI_69_DATA
+				DDRSS0_PI_70_DATA
+				DDRSS0_PI_71_DATA
+				DDRSS0_PI_72_DATA
+				DDRSS0_PI_73_DATA
+				DDRSS0_PI_74_DATA
+				DDRSS0_PI_75_DATA
+				DDRSS0_PI_76_DATA
+				DDRSS0_PI_77_DATA
+				DDRSS0_PI_78_DATA
+				DDRSS0_PI_79_DATA
+				DDRSS0_PI_80_DATA
+				DDRSS0_PI_81_DATA
+				DDRSS0_PI_82_DATA
+				DDRSS0_PI_83_DATA
+				DDRSS0_PI_84_DATA
+				DDRSS0_PI_85_DATA
+				DDRSS0_PI_86_DATA
+				DDRSS0_PI_87_DATA
+				DDRSS0_PI_88_DATA
+				DDRSS0_PI_89_DATA
+				DDRSS0_PI_90_DATA
+				DDRSS0_PI_91_DATA
+				DDRSS0_PI_92_DATA
+				DDRSS0_PI_93_DATA
+				DDRSS0_PI_94_DATA
+				DDRSS0_PI_95_DATA
+				DDRSS0_PI_96_DATA
+				DDRSS0_PI_97_DATA
+				DDRSS0_PI_98_DATA
+				DDRSS0_PI_99_DATA
+				DDRSS0_PI_100_DATA
+				DDRSS0_PI_101_DATA
+				DDRSS0_PI_102_DATA
+				DDRSS0_PI_103_DATA
+				DDRSS0_PI_104_DATA
+				DDRSS0_PI_105_DATA
+				DDRSS0_PI_106_DATA
+				DDRSS0_PI_107_DATA
+				DDRSS0_PI_108_DATA
+				DDRSS0_PI_109_DATA
+				DDRSS0_PI_110_DATA
+				DDRSS0_PI_111_DATA
+				DDRSS0_PI_112_DATA
+				DDRSS0_PI_113_DATA
+				DDRSS0_PI_114_DATA
+				DDRSS0_PI_115_DATA
+				DDRSS0_PI_116_DATA
+				DDRSS0_PI_117_DATA
+				DDRSS0_PI_118_DATA
+				DDRSS0_PI_119_DATA
+				DDRSS0_PI_120_DATA
+				DDRSS0_PI_121_DATA
+				DDRSS0_PI_122_DATA
+				DDRSS0_PI_123_DATA
+				DDRSS0_PI_124_DATA
+				DDRSS0_PI_125_DATA
+				DDRSS0_PI_126_DATA
+				DDRSS0_PI_127_DATA
+				DDRSS0_PI_128_DATA
+				DDRSS0_PI_129_DATA
+				DDRSS0_PI_130_DATA
+				DDRSS0_PI_131_DATA
+				DDRSS0_PI_132_DATA
+				DDRSS0_PI_133_DATA
+				DDRSS0_PI_134_DATA
+				DDRSS0_PI_135_DATA
+				DDRSS0_PI_136_DATA
+				DDRSS0_PI_137_DATA
+				DDRSS0_PI_138_DATA
+				DDRSS0_PI_139_DATA
+				DDRSS0_PI_140_DATA
+				DDRSS0_PI_141_DATA
+				DDRSS0_PI_142_DATA
+				DDRSS0_PI_143_DATA
+				DDRSS0_PI_144_DATA
+				DDRSS0_PI_145_DATA
+				DDRSS0_PI_146_DATA
+				DDRSS0_PI_147_DATA
+				DDRSS0_PI_148_DATA
+				DDRSS0_PI_149_DATA
+				DDRSS0_PI_150_DATA
+				DDRSS0_PI_151_DATA
+				DDRSS0_PI_152_DATA
+				DDRSS0_PI_153_DATA
+				DDRSS0_PI_154_DATA
+				DDRSS0_PI_155_DATA
+				DDRSS0_PI_156_DATA
+				DDRSS0_PI_157_DATA
+				DDRSS0_PI_158_DATA
+				DDRSS0_PI_159_DATA
+				DDRSS0_PI_160_DATA
+				DDRSS0_PI_161_DATA
+				DDRSS0_PI_162_DATA
+				DDRSS0_PI_163_DATA
+				DDRSS0_PI_164_DATA
+				DDRSS0_PI_165_DATA
+				DDRSS0_PI_166_DATA
+				DDRSS0_PI_167_DATA
+				DDRSS0_PI_168_DATA
+				DDRSS0_PI_169_DATA
+				DDRSS0_PI_170_DATA
+				DDRSS0_PI_171_DATA
+				DDRSS0_PI_172_DATA
+				DDRSS0_PI_173_DATA
+				DDRSS0_PI_174_DATA
+				DDRSS0_PI_175_DATA
+				DDRSS0_PI_176_DATA
+				DDRSS0_PI_177_DATA
+				DDRSS0_PI_178_DATA
+				DDRSS0_PI_179_DATA
+				DDRSS0_PI_180_DATA
+				DDRSS0_PI_181_DATA
+				DDRSS0_PI_182_DATA
+				DDRSS0_PI_183_DATA
+				DDRSS0_PI_184_DATA
+				DDRSS0_PI_185_DATA
+				DDRSS0_PI_186_DATA
+				DDRSS0_PI_187_DATA
+				DDRSS0_PI_188_DATA
+				DDRSS0_PI_189_DATA
+				DDRSS0_PI_190_DATA
+				DDRSS0_PI_191_DATA
+				DDRSS0_PI_192_DATA
+				DDRSS0_PI_193_DATA
+				DDRSS0_PI_194_DATA
+				DDRSS0_PI_195_DATA
+				DDRSS0_PI_196_DATA
+				DDRSS0_PI_197_DATA
+				DDRSS0_PI_198_DATA
+				DDRSS0_PI_199_DATA
+				DDRSS0_PI_200_DATA
+				DDRSS0_PI_201_DATA
+				DDRSS0_PI_202_DATA
+				DDRSS0_PI_203_DATA
+				DDRSS0_PI_204_DATA
+				DDRSS0_PI_205_DATA
+				DDRSS0_PI_206_DATA
+				DDRSS0_PI_207_DATA
+				DDRSS0_PI_208_DATA
+				DDRSS0_PI_209_DATA
+				DDRSS0_PI_210_DATA
+				DDRSS0_PI_211_DATA
+				DDRSS0_PI_212_DATA
+				DDRSS0_PI_213_DATA
+				DDRSS0_PI_214_DATA
+				DDRSS0_PI_215_DATA
+				DDRSS0_PI_216_DATA
+				DDRSS0_PI_217_DATA
+				DDRSS0_PI_218_DATA
+				DDRSS0_PI_219_DATA
+				DDRSS0_PI_220_DATA
+				DDRSS0_PI_221_DATA
+				DDRSS0_PI_222_DATA
+				DDRSS0_PI_223_DATA
+				DDRSS0_PI_224_DATA
+				DDRSS0_PI_225_DATA
+				DDRSS0_PI_226_DATA
+				DDRSS0_PI_227_DATA
+				DDRSS0_PI_228_DATA
+				DDRSS0_PI_229_DATA
+				DDRSS0_PI_230_DATA
+				DDRSS0_PI_231_DATA
+				DDRSS0_PI_232_DATA
+				DDRSS0_PI_233_DATA
+				DDRSS0_PI_234_DATA
+				DDRSS0_PI_235_DATA
+				DDRSS0_PI_236_DATA
+				DDRSS0_PI_237_DATA
+				DDRSS0_PI_238_DATA
+				DDRSS0_PI_239_DATA
+				DDRSS0_PI_240_DATA
+				DDRSS0_PI_241_DATA
+				DDRSS0_PI_242_DATA
+				DDRSS0_PI_243_DATA
+				DDRSS0_PI_244_DATA
+				DDRSS0_PI_245_DATA
+				DDRSS0_PI_246_DATA
+				DDRSS0_PI_247_DATA
+				DDRSS0_PI_248_DATA
+				DDRSS0_PI_249_DATA
+				DDRSS0_PI_250_DATA
+				DDRSS0_PI_251_DATA
+				DDRSS0_PI_252_DATA
+				DDRSS0_PI_253_DATA
+				DDRSS0_PI_254_DATA
+				DDRSS0_PI_255_DATA
+				DDRSS0_PI_256_DATA
+				DDRSS0_PI_257_DATA
+				DDRSS0_PI_258_DATA
+				DDRSS0_PI_259_DATA
+				DDRSS0_PI_260_DATA
+				DDRSS0_PI_261_DATA
+				DDRSS0_PI_262_DATA
+				DDRSS0_PI_263_DATA
+				DDRSS0_PI_264_DATA
+				DDRSS0_PI_265_DATA
+				DDRSS0_PI_266_DATA
+				DDRSS0_PI_267_DATA
+				DDRSS0_PI_268_DATA
+				DDRSS0_PI_269_DATA
+				DDRSS0_PI_270_DATA
+				DDRSS0_PI_271_DATA
+				DDRSS0_PI_272_DATA
+				DDRSS0_PI_273_DATA
+				DDRSS0_PI_274_DATA
+				DDRSS0_PI_275_DATA
+				DDRSS0_PI_276_DATA
+				DDRSS0_PI_277_DATA
+				DDRSS0_PI_278_DATA
+				DDRSS0_PI_279_DATA
+				DDRSS0_PI_280_DATA
+				DDRSS0_PI_281_DATA
+				DDRSS0_PI_282_DATA
+				DDRSS0_PI_283_DATA
+				DDRSS0_PI_284_DATA
+				DDRSS0_PI_285_DATA
+				DDRSS0_PI_286_DATA
+				DDRSS0_PI_287_DATA
+				DDRSS0_PI_288_DATA
+				DDRSS0_PI_289_DATA
+				DDRSS0_PI_290_DATA
+				DDRSS0_PI_291_DATA
+				DDRSS0_PI_292_DATA
+				DDRSS0_PI_293_DATA
+				DDRSS0_PI_294_DATA
+				DDRSS0_PI_295_DATA
+				DDRSS0_PI_296_DATA
+				DDRSS0_PI_297_DATA
+				DDRSS0_PI_298_DATA
+				DDRSS0_PI_299_DATA
+			>;
+
+			ti,phy-data = <
+				DDRSS0_PHY_00_DATA
+				DDRSS0_PHY_01_DATA
+				DDRSS0_PHY_02_DATA
+				DDRSS0_PHY_03_DATA
+				DDRSS0_PHY_04_DATA
+				DDRSS0_PHY_05_DATA
+				DDRSS0_PHY_06_DATA
+				DDRSS0_PHY_07_DATA
+				DDRSS0_PHY_08_DATA
+				DDRSS0_PHY_09_DATA
+				DDRSS0_PHY_10_DATA
+				DDRSS0_PHY_11_DATA
+				DDRSS0_PHY_12_DATA
+				DDRSS0_PHY_13_DATA
+				DDRSS0_PHY_14_DATA
+				DDRSS0_PHY_15_DATA
+				DDRSS0_PHY_16_DATA
+				DDRSS0_PHY_17_DATA
+				DDRSS0_PHY_18_DATA
+				DDRSS0_PHY_19_DATA
+				DDRSS0_PHY_20_DATA
+				DDRSS0_PHY_21_DATA
+				DDRSS0_PHY_22_DATA
+				DDRSS0_PHY_23_DATA
+				DDRSS0_PHY_24_DATA
+				DDRSS0_PHY_25_DATA
+				DDRSS0_PHY_26_DATA
+				DDRSS0_PHY_27_DATA
+				DDRSS0_PHY_28_DATA
+				DDRSS0_PHY_29_DATA
+				DDRSS0_PHY_30_DATA
+				DDRSS0_PHY_31_DATA
+				DDRSS0_PHY_32_DATA
+				DDRSS0_PHY_33_DATA
+				DDRSS0_PHY_34_DATA
+				DDRSS0_PHY_35_DATA
+				DDRSS0_PHY_36_DATA
+				DDRSS0_PHY_37_DATA
+				DDRSS0_PHY_38_DATA
+				DDRSS0_PHY_39_DATA
+				DDRSS0_PHY_40_DATA
+				DDRSS0_PHY_41_DATA
+				DDRSS0_PHY_42_DATA
+				DDRSS0_PHY_43_DATA
+				DDRSS0_PHY_44_DATA
+				DDRSS0_PHY_45_DATA
+				DDRSS0_PHY_46_DATA
+				DDRSS0_PHY_47_DATA
+				DDRSS0_PHY_48_DATA
+				DDRSS0_PHY_49_DATA
+				DDRSS0_PHY_50_DATA
+				DDRSS0_PHY_51_DATA
+				DDRSS0_PHY_52_DATA
+				DDRSS0_PHY_53_DATA
+				DDRSS0_PHY_54_DATA
+				DDRSS0_PHY_55_DATA
+				DDRSS0_PHY_56_DATA
+				DDRSS0_PHY_57_DATA
+				DDRSS0_PHY_58_DATA
+				DDRSS0_PHY_59_DATA
+				DDRSS0_PHY_60_DATA
+				DDRSS0_PHY_61_DATA
+				DDRSS0_PHY_62_DATA
+				DDRSS0_PHY_63_DATA
+				DDRSS0_PHY_64_DATA
+				DDRSS0_PHY_65_DATA
+				DDRSS0_PHY_66_DATA
+				DDRSS0_PHY_67_DATA
+				DDRSS0_PHY_68_DATA
+				DDRSS0_PHY_69_DATA
+				DDRSS0_PHY_70_DATA
+				DDRSS0_PHY_71_DATA
+				DDRSS0_PHY_72_DATA
+				DDRSS0_PHY_73_DATA
+				DDRSS0_PHY_74_DATA
+				DDRSS0_PHY_75_DATA
+				DDRSS0_PHY_76_DATA
+				DDRSS0_PHY_77_DATA
+				DDRSS0_PHY_78_DATA
+				DDRSS0_PHY_79_DATA
+				DDRSS0_PHY_80_DATA
+				DDRSS0_PHY_81_DATA
+				DDRSS0_PHY_82_DATA
+				DDRSS0_PHY_83_DATA
+				DDRSS0_PHY_84_DATA
+				DDRSS0_PHY_85_DATA
+				DDRSS0_PHY_86_DATA
+				DDRSS0_PHY_87_DATA
+				DDRSS0_PHY_88_DATA
+				DDRSS0_PHY_89_DATA
+				DDRSS0_PHY_90_DATA
+				DDRSS0_PHY_91_DATA
+				DDRSS0_PHY_92_DATA
+				DDRSS0_PHY_93_DATA
+				DDRSS0_PHY_94_DATA
+				DDRSS0_PHY_95_DATA
+				DDRSS0_PHY_96_DATA
+				DDRSS0_PHY_97_DATA
+				DDRSS0_PHY_98_DATA
+				DDRSS0_PHY_99_DATA
+				DDRSS0_PHY_100_DATA
+				DDRSS0_PHY_101_DATA
+				DDRSS0_PHY_102_DATA
+				DDRSS0_PHY_103_DATA
+				DDRSS0_PHY_104_DATA
+				DDRSS0_PHY_105_DATA
+				DDRSS0_PHY_106_DATA
+				DDRSS0_PHY_107_DATA
+				DDRSS0_PHY_108_DATA
+				DDRSS0_PHY_109_DATA
+				DDRSS0_PHY_110_DATA
+				DDRSS0_PHY_111_DATA
+				DDRSS0_PHY_112_DATA
+				DDRSS0_PHY_113_DATA
+				DDRSS0_PHY_114_DATA
+				DDRSS0_PHY_115_DATA
+				DDRSS0_PHY_116_DATA
+				DDRSS0_PHY_117_DATA
+				DDRSS0_PHY_118_DATA
+				DDRSS0_PHY_119_DATA
+				DDRSS0_PHY_120_DATA
+				DDRSS0_PHY_121_DATA
+				DDRSS0_PHY_122_DATA
+				DDRSS0_PHY_123_DATA
+				DDRSS0_PHY_124_DATA
+				DDRSS0_PHY_125_DATA
+				DDRSS0_PHY_126_DATA
+				DDRSS0_PHY_127_DATA
+				DDRSS0_PHY_128_DATA
+				DDRSS0_PHY_129_DATA
+				DDRSS0_PHY_130_DATA
+				DDRSS0_PHY_131_DATA
+				DDRSS0_PHY_132_DATA
+				DDRSS0_PHY_133_DATA
+				DDRSS0_PHY_134_DATA
+				DDRSS0_PHY_135_DATA
+				DDRSS0_PHY_136_DATA
+				DDRSS0_PHY_137_DATA
+				DDRSS0_PHY_138_DATA
+				DDRSS0_PHY_139_DATA
+				DDRSS0_PHY_140_DATA
+				DDRSS0_PHY_141_DATA
+				DDRSS0_PHY_142_DATA
+				DDRSS0_PHY_143_DATA
+				DDRSS0_PHY_144_DATA
+				DDRSS0_PHY_145_DATA
+				DDRSS0_PHY_146_DATA
+				DDRSS0_PHY_147_DATA
+				DDRSS0_PHY_148_DATA
+				DDRSS0_PHY_149_DATA
+				DDRSS0_PHY_150_DATA
+				DDRSS0_PHY_151_DATA
+				DDRSS0_PHY_152_DATA
+				DDRSS0_PHY_153_DATA
+				DDRSS0_PHY_154_DATA
+				DDRSS0_PHY_155_DATA
+				DDRSS0_PHY_156_DATA
+				DDRSS0_PHY_157_DATA
+				DDRSS0_PHY_158_DATA
+				DDRSS0_PHY_159_DATA
+				DDRSS0_PHY_160_DATA
+				DDRSS0_PHY_161_DATA
+				DDRSS0_PHY_162_DATA
+				DDRSS0_PHY_163_DATA
+				DDRSS0_PHY_164_DATA
+				DDRSS0_PHY_165_DATA
+				DDRSS0_PHY_166_DATA
+				DDRSS0_PHY_167_DATA
+				DDRSS0_PHY_168_DATA
+				DDRSS0_PHY_169_DATA
+				DDRSS0_PHY_170_DATA
+				DDRSS0_PHY_171_DATA
+				DDRSS0_PHY_172_DATA
+				DDRSS0_PHY_173_DATA
+				DDRSS0_PHY_174_DATA
+				DDRSS0_PHY_175_DATA
+				DDRSS0_PHY_176_DATA
+				DDRSS0_PHY_177_DATA
+				DDRSS0_PHY_178_DATA
+				DDRSS0_PHY_179_DATA
+				DDRSS0_PHY_180_DATA
+				DDRSS0_PHY_181_DATA
+				DDRSS0_PHY_182_DATA
+				DDRSS0_PHY_183_DATA
+				DDRSS0_PHY_184_DATA
+				DDRSS0_PHY_185_DATA
+				DDRSS0_PHY_186_DATA
+				DDRSS0_PHY_187_DATA
+				DDRSS0_PHY_188_DATA
+				DDRSS0_PHY_189_DATA
+				DDRSS0_PHY_190_DATA
+				DDRSS0_PHY_191_DATA
+				DDRSS0_PHY_192_DATA
+				DDRSS0_PHY_193_DATA
+				DDRSS0_PHY_194_DATA
+				DDRSS0_PHY_195_DATA
+				DDRSS0_PHY_196_DATA
+				DDRSS0_PHY_197_DATA
+				DDRSS0_PHY_198_DATA
+				DDRSS0_PHY_199_DATA
+				DDRSS0_PHY_200_DATA
+				DDRSS0_PHY_201_DATA
+				DDRSS0_PHY_202_DATA
+				DDRSS0_PHY_203_DATA
+				DDRSS0_PHY_204_DATA
+				DDRSS0_PHY_205_DATA
+				DDRSS0_PHY_206_DATA
+				DDRSS0_PHY_207_DATA
+				DDRSS0_PHY_208_DATA
+				DDRSS0_PHY_209_DATA
+				DDRSS0_PHY_210_DATA
+				DDRSS0_PHY_211_DATA
+				DDRSS0_PHY_212_DATA
+				DDRSS0_PHY_213_DATA
+				DDRSS0_PHY_214_DATA
+				DDRSS0_PHY_215_DATA
+				DDRSS0_PHY_216_DATA
+				DDRSS0_PHY_217_DATA
+				DDRSS0_PHY_218_DATA
+				DDRSS0_PHY_219_DATA
+				DDRSS0_PHY_220_DATA
+				DDRSS0_PHY_221_DATA
+				DDRSS0_PHY_222_DATA
+				DDRSS0_PHY_223_DATA
+				DDRSS0_PHY_224_DATA
+				DDRSS0_PHY_225_DATA
+				DDRSS0_PHY_226_DATA
+				DDRSS0_PHY_227_DATA
+				DDRSS0_PHY_228_DATA
+				DDRSS0_PHY_229_DATA
+				DDRSS0_PHY_230_DATA
+				DDRSS0_PHY_231_DATA
+				DDRSS0_PHY_232_DATA
+				DDRSS0_PHY_233_DATA
+				DDRSS0_PHY_234_DATA
+				DDRSS0_PHY_235_DATA
+				DDRSS0_PHY_236_DATA
+				DDRSS0_PHY_237_DATA
+				DDRSS0_PHY_238_DATA
+				DDRSS0_PHY_239_DATA
+				DDRSS0_PHY_240_DATA
+				DDRSS0_PHY_241_DATA
+				DDRSS0_PHY_242_DATA
+				DDRSS0_PHY_243_DATA
+				DDRSS0_PHY_244_DATA
+				DDRSS0_PHY_245_DATA
+				DDRSS0_PHY_246_DATA
+				DDRSS0_PHY_247_DATA
+				DDRSS0_PHY_248_DATA
+				DDRSS0_PHY_249_DATA
+				DDRSS0_PHY_250_DATA
+				DDRSS0_PHY_251_DATA
+				DDRSS0_PHY_252_DATA
+				DDRSS0_PHY_253_DATA
+				DDRSS0_PHY_254_DATA
+				DDRSS0_PHY_255_DATA
+				DDRSS0_PHY_256_DATA
+				DDRSS0_PHY_257_DATA
+				DDRSS0_PHY_258_DATA
+				DDRSS0_PHY_259_DATA
+				DDRSS0_PHY_260_DATA
+				DDRSS0_PHY_261_DATA
+				DDRSS0_PHY_262_DATA
+				DDRSS0_PHY_263_DATA
+				DDRSS0_PHY_264_DATA
+				DDRSS0_PHY_265_DATA
+				DDRSS0_PHY_266_DATA
+				DDRSS0_PHY_267_DATA
+				DDRSS0_PHY_268_DATA
+				DDRSS0_PHY_269_DATA
+				DDRSS0_PHY_270_DATA
+				DDRSS0_PHY_271_DATA
+				DDRSS0_PHY_272_DATA
+				DDRSS0_PHY_273_DATA
+				DDRSS0_PHY_274_DATA
+				DDRSS0_PHY_275_DATA
+				DDRSS0_PHY_276_DATA
+				DDRSS0_PHY_277_DATA
+				DDRSS0_PHY_278_DATA
+				DDRSS0_PHY_279_DATA
+				DDRSS0_PHY_280_DATA
+				DDRSS0_PHY_281_DATA
+				DDRSS0_PHY_282_DATA
+				DDRSS0_PHY_283_DATA
+				DDRSS0_PHY_284_DATA
+				DDRSS0_PHY_285_DATA
+				DDRSS0_PHY_286_DATA
+				DDRSS0_PHY_287_DATA
+				DDRSS0_PHY_288_DATA
+				DDRSS0_PHY_289_DATA
+				DDRSS0_PHY_290_DATA
+				DDRSS0_PHY_291_DATA
+				DDRSS0_PHY_292_DATA
+				DDRSS0_PHY_293_DATA
+				DDRSS0_PHY_294_DATA
+				DDRSS0_PHY_295_DATA
+				DDRSS0_PHY_296_DATA
+				DDRSS0_PHY_297_DATA
+				DDRSS0_PHY_298_DATA
+				DDRSS0_PHY_299_DATA
+				DDRSS0_PHY_300_DATA
+				DDRSS0_PHY_301_DATA
+				DDRSS0_PHY_302_DATA
+				DDRSS0_PHY_303_DATA
+				DDRSS0_PHY_304_DATA
+				DDRSS0_PHY_305_DATA
+				DDRSS0_PHY_306_DATA
+				DDRSS0_PHY_307_DATA
+				DDRSS0_PHY_308_DATA
+				DDRSS0_PHY_309_DATA
+				DDRSS0_PHY_310_DATA
+				DDRSS0_PHY_311_DATA
+				DDRSS0_PHY_312_DATA
+				DDRSS0_PHY_313_DATA
+				DDRSS0_PHY_314_DATA
+				DDRSS0_PHY_315_DATA
+				DDRSS0_PHY_316_DATA
+				DDRSS0_PHY_317_DATA
+				DDRSS0_PHY_318_DATA
+				DDRSS0_PHY_319_DATA
+				DDRSS0_PHY_320_DATA
+				DDRSS0_PHY_321_DATA
+				DDRSS0_PHY_322_DATA
+				DDRSS0_PHY_323_DATA
+				DDRSS0_PHY_324_DATA
+				DDRSS0_PHY_325_DATA
+				DDRSS0_PHY_326_DATA
+				DDRSS0_PHY_327_DATA
+				DDRSS0_PHY_328_DATA
+				DDRSS0_PHY_329_DATA
+				DDRSS0_PHY_330_DATA
+				DDRSS0_PHY_331_DATA
+				DDRSS0_PHY_332_DATA
+				DDRSS0_PHY_333_DATA
+				DDRSS0_PHY_334_DATA
+				DDRSS0_PHY_335_DATA
+				DDRSS0_PHY_336_DATA
+				DDRSS0_PHY_337_DATA
+				DDRSS0_PHY_338_DATA
+				DDRSS0_PHY_339_DATA
+				DDRSS0_PHY_340_DATA
+				DDRSS0_PHY_341_DATA
+				DDRSS0_PHY_342_DATA
+				DDRSS0_PHY_343_DATA
+				DDRSS0_PHY_344_DATA
+				DDRSS0_PHY_345_DATA
+				DDRSS0_PHY_346_DATA
+				DDRSS0_PHY_347_DATA
+				DDRSS0_PHY_348_DATA
+				DDRSS0_PHY_349_DATA
+				DDRSS0_PHY_350_DATA
+				DDRSS0_PHY_351_DATA
+				DDRSS0_PHY_352_DATA
+				DDRSS0_PHY_353_DATA
+				DDRSS0_PHY_354_DATA
+				DDRSS0_PHY_355_DATA
+				DDRSS0_PHY_356_DATA
+				DDRSS0_PHY_357_DATA
+				DDRSS0_PHY_358_DATA
+				DDRSS0_PHY_359_DATA
+				DDRSS0_PHY_360_DATA
+				DDRSS0_PHY_361_DATA
+				DDRSS0_PHY_362_DATA
+				DDRSS0_PHY_363_DATA
+				DDRSS0_PHY_364_DATA
+				DDRSS0_PHY_365_DATA
+				DDRSS0_PHY_366_DATA
+				DDRSS0_PHY_367_DATA
+				DDRSS0_PHY_368_DATA
+				DDRSS0_PHY_369_DATA
+				DDRSS0_PHY_370_DATA
+				DDRSS0_PHY_371_DATA
+				DDRSS0_PHY_372_DATA
+				DDRSS0_PHY_373_DATA
+				DDRSS0_PHY_374_DATA
+				DDRSS0_PHY_375_DATA
+				DDRSS0_PHY_376_DATA
+				DDRSS0_PHY_377_DATA
+				DDRSS0_PHY_378_DATA
+				DDRSS0_PHY_379_DATA
+				DDRSS0_PHY_380_DATA
+				DDRSS0_PHY_381_DATA
+				DDRSS0_PHY_382_DATA
+				DDRSS0_PHY_383_DATA
+				DDRSS0_PHY_384_DATA
+				DDRSS0_PHY_385_DATA
+				DDRSS0_PHY_386_DATA
+				DDRSS0_PHY_387_DATA
+				DDRSS0_PHY_388_DATA
+				DDRSS0_PHY_389_DATA
+				DDRSS0_PHY_390_DATA
+				DDRSS0_PHY_391_DATA
+				DDRSS0_PHY_392_DATA
+				DDRSS0_PHY_393_DATA
+				DDRSS0_PHY_394_DATA
+				DDRSS0_PHY_395_DATA
+				DDRSS0_PHY_396_DATA
+				DDRSS0_PHY_397_DATA
+				DDRSS0_PHY_398_DATA
+				DDRSS0_PHY_399_DATA
+				DDRSS0_PHY_400_DATA
+				DDRSS0_PHY_401_DATA
+				DDRSS0_PHY_402_DATA
+				DDRSS0_PHY_403_DATA
+				DDRSS0_PHY_404_DATA
+				DDRSS0_PHY_405_DATA
+				DDRSS0_PHY_406_DATA
+				DDRSS0_PHY_407_DATA
+				DDRSS0_PHY_408_DATA
+				DDRSS0_PHY_409_DATA
+				DDRSS0_PHY_410_DATA
+				DDRSS0_PHY_411_DATA
+				DDRSS0_PHY_412_DATA
+				DDRSS0_PHY_413_DATA
+				DDRSS0_PHY_414_DATA
+				DDRSS0_PHY_415_DATA
+				DDRSS0_PHY_416_DATA
+				DDRSS0_PHY_417_DATA
+				DDRSS0_PHY_418_DATA
+				DDRSS0_PHY_419_DATA
+				DDRSS0_PHY_420_DATA
+				DDRSS0_PHY_421_DATA
+				DDRSS0_PHY_422_DATA
+				DDRSS0_PHY_423_DATA
+				DDRSS0_PHY_424_DATA
+				DDRSS0_PHY_425_DATA
+				DDRSS0_PHY_426_DATA
+				DDRSS0_PHY_427_DATA
+				DDRSS0_PHY_428_DATA
+				DDRSS0_PHY_429_DATA
+				DDRSS0_PHY_430_DATA
+				DDRSS0_PHY_431_DATA
+				DDRSS0_PHY_432_DATA
+				DDRSS0_PHY_433_DATA
+				DDRSS0_PHY_434_DATA
+				DDRSS0_PHY_435_DATA
+				DDRSS0_PHY_436_DATA
+				DDRSS0_PHY_437_DATA
+				DDRSS0_PHY_438_DATA
+				DDRSS0_PHY_439_DATA
+				DDRSS0_PHY_440_DATA
+				DDRSS0_PHY_441_DATA
+				DDRSS0_PHY_442_DATA
+				DDRSS0_PHY_443_DATA
+				DDRSS0_PHY_444_DATA
+				DDRSS0_PHY_445_DATA
+				DDRSS0_PHY_446_DATA
+				DDRSS0_PHY_447_DATA
+				DDRSS0_PHY_448_DATA
+				DDRSS0_PHY_449_DATA
+				DDRSS0_PHY_450_DATA
+				DDRSS0_PHY_451_DATA
+				DDRSS0_PHY_452_DATA
+				DDRSS0_PHY_453_DATA
+				DDRSS0_PHY_454_DATA
+				DDRSS0_PHY_455_DATA
+				DDRSS0_PHY_456_DATA
+				DDRSS0_PHY_457_DATA
+				DDRSS0_PHY_458_DATA
+				DDRSS0_PHY_459_DATA
+				DDRSS0_PHY_460_DATA
+				DDRSS0_PHY_461_DATA
+				DDRSS0_PHY_462_DATA
+				DDRSS0_PHY_463_DATA
+				DDRSS0_PHY_464_DATA
+				DDRSS0_PHY_465_DATA
+				DDRSS0_PHY_466_DATA
+				DDRSS0_PHY_467_DATA
+				DDRSS0_PHY_468_DATA
+				DDRSS0_PHY_469_DATA
+				DDRSS0_PHY_470_DATA
+				DDRSS0_PHY_471_DATA
+				DDRSS0_PHY_472_DATA
+				DDRSS0_PHY_473_DATA
+				DDRSS0_PHY_474_DATA
+				DDRSS0_PHY_475_DATA
+				DDRSS0_PHY_476_DATA
+				DDRSS0_PHY_477_DATA
+				DDRSS0_PHY_478_DATA
+				DDRSS0_PHY_479_DATA
+				DDRSS0_PHY_480_DATA
+				DDRSS0_PHY_481_DATA
+				DDRSS0_PHY_482_DATA
+				DDRSS0_PHY_483_DATA
+				DDRSS0_PHY_484_DATA
+				DDRSS0_PHY_485_DATA
+				DDRSS0_PHY_486_DATA
+				DDRSS0_PHY_487_DATA
+				DDRSS0_PHY_488_DATA
+				DDRSS0_PHY_489_DATA
+				DDRSS0_PHY_490_DATA
+				DDRSS0_PHY_491_DATA
+				DDRSS0_PHY_492_DATA
+				DDRSS0_PHY_493_DATA
+				DDRSS0_PHY_494_DATA
+				DDRSS0_PHY_495_DATA
+				DDRSS0_PHY_496_DATA
+				DDRSS0_PHY_497_DATA
+				DDRSS0_PHY_498_DATA
+				DDRSS0_PHY_499_DATA
+				DDRSS0_PHY_500_DATA
+				DDRSS0_PHY_501_DATA
+				DDRSS0_PHY_502_DATA
+				DDRSS0_PHY_503_DATA
+				DDRSS0_PHY_504_DATA
+				DDRSS0_PHY_505_DATA
+				DDRSS0_PHY_506_DATA
+				DDRSS0_PHY_507_DATA
+				DDRSS0_PHY_508_DATA
+				DDRSS0_PHY_509_DATA
+				DDRSS0_PHY_510_DATA
+				DDRSS0_PHY_511_DATA
+				DDRSS0_PHY_512_DATA
+				DDRSS0_PHY_513_DATA
+				DDRSS0_PHY_514_DATA
+				DDRSS0_PHY_515_DATA
+				DDRSS0_PHY_516_DATA
+				DDRSS0_PHY_517_DATA
+				DDRSS0_PHY_518_DATA
+				DDRSS0_PHY_519_DATA
+				DDRSS0_PHY_520_DATA
+				DDRSS0_PHY_521_DATA
+				DDRSS0_PHY_522_DATA
+				DDRSS0_PHY_523_DATA
+				DDRSS0_PHY_524_DATA
+				DDRSS0_PHY_525_DATA
+				DDRSS0_PHY_526_DATA
+				DDRSS0_PHY_527_DATA
+				DDRSS0_PHY_528_DATA
+				DDRSS0_PHY_529_DATA
+				DDRSS0_PHY_530_DATA
+				DDRSS0_PHY_531_DATA
+				DDRSS0_PHY_532_DATA
+				DDRSS0_PHY_533_DATA
+				DDRSS0_PHY_534_DATA
+				DDRSS0_PHY_535_DATA
+				DDRSS0_PHY_536_DATA
+				DDRSS0_PHY_537_DATA
+				DDRSS0_PHY_538_DATA
+				DDRSS0_PHY_539_DATA
+				DDRSS0_PHY_540_DATA
+				DDRSS0_PHY_541_DATA
+				DDRSS0_PHY_542_DATA
+				DDRSS0_PHY_543_DATA
+				DDRSS0_PHY_544_DATA
+				DDRSS0_PHY_545_DATA
+				DDRSS0_PHY_546_DATA
+				DDRSS0_PHY_547_DATA
+				DDRSS0_PHY_548_DATA
+				DDRSS0_PHY_549_DATA
+				DDRSS0_PHY_550_DATA
+				DDRSS0_PHY_551_DATA
+				DDRSS0_PHY_552_DATA
+				DDRSS0_PHY_553_DATA
+				DDRSS0_PHY_554_DATA
+				DDRSS0_PHY_555_DATA
+				DDRSS0_PHY_556_DATA
+				DDRSS0_PHY_557_DATA
+				DDRSS0_PHY_558_DATA
+				DDRSS0_PHY_559_DATA
+				DDRSS0_PHY_560_DATA
+				DDRSS0_PHY_561_DATA
+				DDRSS0_PHY_562_DATA
+				DDRSS0_PHY_563_DATA
+				DDRSS0_PHY_564_DATA
+				DDRSS0_PHY_565_DATA
+				DDRSS0_PHY_566_DATA
+				DDRSS0_PHY_567_DATA
+				DDRSS0_PHY_568_DATA
+				DDRSS0_PHY_569_DATA
+				DDRSS0_PHY_570_DATA
+				DDRSS0_PHY_571_DATA
+				DDRSS0_PHY_572_DATA
+				DDRSS0_PHY_573_DATA
+				DDRSS0_PHY_574_DATA
+				DDRSS0_PHY_575_DATA
+				DDRSS0_PHY_576_DATA
+				DDRSS0_PHY_577_DATA
+				DDRSS0_PHY_578_DATA
+				DDRSS0_PHY_579_DATA
+				DDRSS0_PHY_580_DATA
+				DDRSS0_PHY_581_DATA
+				DDRSS0_PHY_582_DATA
+				DDRSS0_PHY_583_DATA
+				DDRSS0_PHY_584_DATA
+				DDRSS0_PHY_585_DATA
+				DDRSS0_PHY_586_DATA
+				DDRSS0_PHY_587_DATA
+				DDRSS0_PHY_588_DATA
+				DDRSS0_PHY_589_DATA
+				DDRSS0_PHY_590_DATA
+				DDRSS0_PHY_591_DATA
+				DDRSS0_PHY_592_DATA
+				DDRSS0_PHY_593_DATA
+				DDRSS0_PHY_594_DATA
+				DDRSS0_PHY_595_DATA
+				DDRSS0_PHY_596_DATA
+				DDRSS0_PHY_597_DATA
+				DDRSS0_PHY_598_DATA
+				DDRSS0_PHY_599_DATA
+				DDRSS0_PHY_600_DATA
+				DDRSS0_PHY_601_DATA
+				DDRSS0_PHY_602_DATA
+				DDRSS0_PHY_603_DATA
+				DDRSS0_PHY_604_DATA
+				DDRSS0_PHY_605_DATA
+				DDRSS0_PHY_606_DATA
+				DDRSS0_PHY_607_DATA
+				DDRSS0_PHY_608_DATA
+				DDRSS0_PHY_609_DATA
+				DDRSS0_PHY_610_DATA
+				DDRSS0_PHY_611_DATA
+				DDRSS0_PHY_612_DATA
+				DDRSS0_PHY_613_DATA
+				DDRSS0_PHY_614_DATA
+				DDRSS0_PHY_615_DATA
+				DDRSS0_PHY_616_DATA
+				DDRSS0_PHY_617_DATA
+				DDRSS0_PHY_618_DATA
+				DDRSS0_PHY_619_DATA
+				DDRSS0_PHY_620_DATA
+				DDRSS0_PHY_621_DATA
+				DDRSS0_PHY_622_DATA
+				DDRSS0_PHY_623_DATA
+				DDRSS0_PHY_624_DATA
+				DDRSS0_PHY_625_DATA
+				DDRSS0_PHY_626_DATA
+				DDRSS0_PHY_627_DATA
+				DDRSS0_PHY_628_DATA
+				DDRSS0_PHY_629_DATA
+				DDRSS0_PHY_630_DATA
+				DDRSS0_PHY_631_DATA
+				DDRSS0_PHY_632_DATA
+				DDRSS0_PHY_633_DATA
+				DDRSS0_PHY_634_DATA
+				DDRSS0_PHY_635_DATA
+				DDRSS0_PHY_636_DATA
+				DDRSS0_PHY_637_DATA
+				DDRSS0_PHY_638_DATA
+				DDRSS0_PHY_639_DATA
+				DDRSS0_PHY_640_DATA
+				DDRSS0_PHY_641_DATA
+				DDRSS0_PHY_642_DATA
+				DDRSS0_PHY_643_DATA
+				DDRSS0_PHY_644_DATA
+				DDRSS0_PHY_645_DATA
+				DDRSS0_PHY_646_DATA
+				DDRSS0_PHY_647_DATA
+				DDRSS0_PHY_648_DATA
+				DDRSS0_PHY_649_DATA
+				DDRSS0_PHY_650_DATA
+				DDRSS0_PHY_651_DATA
+				DDRSS0_PHY_652_DATA
+				DDRSS0_PHY_653_DATA
+				DDRSS0_PHY_654_DATA
+				DDRSS0_PHY_655_DATA
+				DDRSS0_PHY_656_DATA
+				DDRSS0_PHY_657_DATA
+				DDRSS0_PHY_658_DATA
+				DDRSS0_PHY_659_DATA
+				DDRSS0_PHY_660_DATA
+				DDRSS0_PHY_661_DATA
+				DDRSS0_PHY_662_DATA
+				DDRSS0_PHY_663_DATA
+				DDRSS0_PHY_664_DATA
+				DDRSS0_PHY_665_DATA
+				DDRSS0_PHY_666_DATA
+				DDRSS0_PHY_667_DATA
+				DDRSS0_PHY_668_DATA
+				DDRSS0_PHY_669_DATA
+				DDRSS0_PHY_670_DATA
+				DDRSS0_PHY_671_DATA
+				DDRSS0_PHY_672_DATA
+				DDRSS0_PHY_673_DATA
+				DDRSS0_PHY_674_DATA
+				DDRSS0_PHY_675_DATA
+				DDRSS0_PHY_676_DATA
+				DDRSS0_PHY_677_DATA
+				DDRSS0_PHY_678_DATA
+				DDRSS0_PHY_679_DATA
+				DDRSS0_PHY_680_DATA
+				DDRSS0_PHY_681_DATA
+				DDRSS0_PHY_682_DATA
+				DDRSS0_PHY_683_DATA
+				DDRSS0_PHY_684_DATA
+				DDRSS0_PHY_685_DATA
+				DDRSS0_PHY_686_DATA
+				DDRSS0_PHY_687_DATA
+				DDRSS0_PHY_688_DATA
+				DDRSS0_PHY_689_DATA
+				DDRSS0_PHY_690_DATA
+				DDRSS0_PHY_691_DATA
+				DDRSS0_PHY_692_DATA
+				DDRSS0_PHY_693_DATA
+				DDRSS0_PHY_694_DATA
+				DDRSS0_PHY_695_DATA
+				DDRSS0_PHY_696_DATA
+				DDRSS0_PHY_697_DATA
+				DDRSS0_PHY_698_DATA
+				DDRSS0_PHY_699_DATA
+				DDRSS0_PHY_700_DATA
+				DDRSS0_PHY_701_DATA
+				DDRSS0_PHY_702_DATA
+				DDRSS0_PHY_703_DATA
+				DDRSS0_PHY_704_DATA
+				DDRSS0_PHY_705_DATA
+				DDRSS0_PHY_706_DATA
+				DDRSS0_PHY_707_DATA
+				DDRSS0_PHY_708_DATA
+				DDRSS0_PHY_709_DATA
+				DDRSS0_PHY_710_DATA
+				DDRSS0_PHY_711_DATA
+				DDRSS0_PHY_712_DATA
+				DDRSS0_PHY_713_DATA
+				DDRSS0_PHY_714_DATA
+				DDRSS0_PHY_715_DATA
+				DDRSS0_PHY_716_DATA
+				DDRSS0_PHY_717_DATA
+				DDRSS0_PHY_718_DATA
+				DDRSS0_PHY_719_DATA
+				DDRSS0_PHY_720_DATA
+				DDRSS0_PHY_721_DATA
+				DDRSS0_PHY_722_DATA
+				DDRSS0_PHY_723_DATA
+				DDRSS0_PHY_724_DATA
+				DDRSS0_PHY_725_DATA
+				DDRSS0_PHY_726_DATA
+				DDRSS0_PHY_727_DATA
+				DDRSS0_PHY_728_DATA
+				DDRSS0_PHY_729_DATA
+				DDRSS0_PHY_730_DATA
+				DDRSS0_PHY_731_DATA
+				DDRSS0_PHY_732_DATA
+				DDRSS0_PHY_733_DATA
+				DDRSS0_PHY_734_DATA
+				DDRSS0_PHY_735_DATA
+				DDRSS0_PHY_736_DATA
+				DDRSS0_PHY_737_DATA
+				DDRSS0_PHY_738_DATA
+				DDRSS0_PHY_739_DATA
+				DDRSS0_PHY_740_DATA
+				DDRSS0_PHY_741_DATA
+				DDRSS0_PHY_742_DATA
+				DDRSS0_PHY_743_DATA
+				DDRSS0_PHY_744_DATA
+				DDRSS0_PHY_745_DATA
+				DDRSS0_PHY_746_DATA
+				DDRSS0_PHY_747_DATA
+				DDRSS0_PHY_748_DATA
+				DDRSS0_PHY_749_DATA
+				DDRSS0_PHY_750_DATA
+				DDRSS0_PHY_751_DATA
+				DDRSS0_PHY_752_DATA
+				DDRSS0_PHY_753_DATA
+				DDRSS0_PHY_754_DATA
+				DDRSS0_PHY_755_DATA
+				DDRSS0_PHY_756_DATA
+				DDRSS0_PHY_757_DATA
+				DDRSS0_PHY_758_DATA
+				DDRSS0_PHY_759_DATA
+				DDRSS0_PHY_760_DATA
+				DDRSS0_PHY_761_DATA
+				DDRSS0_PHY_762_DATA
+				DDRSS0_PHY_763_DATA
+				DDRSS0_PHY_764_DATA
+				DDRSS0_PHY_765_DATA
+				DDRSS0_PHY_766_DATA
+				DDRSS0_PHY_767_DATA
+				DDRSS0_PHY_768_DATA
+				DDRSS0_PHY_769_DATA
+				DDRSS0_PHY_770_DATA
+				DDRSS0_PHY_771_DATA
+				DDRSS0_PHY_772_DATA
+				DDRSS0_PHY_773_DATA
+				DDRSS0_PHY_774_DATA
+				DDRSS0_PHY_775_DATA
+				DDRSS0_PHY_776_DATA
+				DDRSS0_PHY_777_DATA
+				DDRSS0_PHY_778_DATA
+				DDRSS0_PHY_779_DATA
+				DDRSS0_PHY_780_DATA
+				DDRSS0_PHY_781_DATA
+				DDRSS0_PHY_782_DATA
+				DDRSS0_PHY_783_DATA
+				DDRSS0_PHY_784_DATA
+				DDRSS0_PHY_785_DATA
+				DDRSS0_PHY_786_DATA
+				DDRSS0_PHY_787_DATA
+				DDRSS0_PHY_788_DATA
+				DDRSS0_PHY_789_DATA
+				DDRSS0_PHY_790_DATA
+				DDRSS0_PHY_791_DATA
+				DDRSS0_PHY_792_DATA
+				DDRSS0_PHY_793_DATA
+				DDRSS0_PHY_794_DATA
+				DDRSS0_PHY_795_DATA
+				DDRSS0_PHY_796_DATA
+				DDRSS0_PHY_797_DATA
+				DDRSS0_PHY_798_DATA
+				DDRSS0_PHY_799_DATA
+				DDRSS0_PHY_800_DATA
+				DDRSS0_PHY_801_DATA
+				DDRSS0_PHY_802_DATA
+				DDRSS0_PHY_803_DATA
+				DDRSS0_PHY_804_DATA
+				DDRSS0_PHY_805_DATA
+				DDRSS0_PHY_806_DATA
+				DDRSS0_PHY_807_DATA
+				DDRSS0_PHY_808_DATA
+				DDRSS0_PHY_809_DATA
+				DDRSS0_PHY_810_DATA
+				DDRSS0_PHY_811_DATA
+				DDRSS0_PHY_812_DATA
+				DDRSS0_PHY_813_DATA
+				DDRSS0_PHY_814_DATA
+				DDRSS0_PHY_815_DATA
+				DDRSS0_PHY_816_DATA
+				DDRSS0_PHY_817_DATA
+				DDRSS0_PHY_818_DATA
+				DDRSS0_PHY_819_DATA
+				DDRSS0_PHY_820_DATA
+				DDRSS0_PHY_821_DATA
+				DDRSS0_PHY_822_DATA
+				DDRSS0_PHY_823_DATA
+				DDRSS0_PHY_824_DATA
+				DDRSS0_PHY_825_DATA
+				DDRSS0_PHY_826_DATA
+				DDRSS0_PHY_827_DATA
+				DDRSS0_PHY_828_DATA
+				DDRSS0_PHY_829_DATA
+				DDRSS0_PHY_830_DATA
+				DDRSS0_PHY_831_DATA
+				DDRSS0_PHY_832_DATA
+				DDRSS0_PHY_833_DATA
+				DDRSS0_PHY_834_DATA
+				DDRSS0_PHY_835_DATA
+				DDRSS0_PHY_836_DATA
+				DDRSS0_PHY_837_DATA
+				DDRSS0_PHY_838_DATA
+				DDRSS0_PHY_839_DATA
+				DDRSS0_PHY_840_DATA
+				DDRSS0_PHY_841_DATA
+				DDRSS0_PHY_842_DATA
+				DDRSS0_PHY_843_DATA
+				DDRSS0_PHY_844_DATA
+				DDRSS0_PHY_845_DATA
+				DDRSS0_PHY_846_DATA
+				DDRSS0_PHY_847_DATA
+				DDRSS0_PHY_848_DATA
+				DDRSS0_PHY_849_DATA
+				DDRSS0_PHY_850_DATA
+				DDRSS0_PHY_851_DATA
+				DDRSS0_PHY_852_DATA
+				DDRSS0_PHY_853_DATA
+				DDRSS0_PHY_854_DATA
+				DDRSS0_PHY_855_DATA
+				DDRSS0_PHY_856_DATA
+				DDRSS0_PHY_857_DATA
+				DDRSS0_PHY_858_DATA
+				DDRSS0_PHY_859_DATA
+				DDRSS0_PHY_860_DATA
+				DDRSS0_PHY_861_DATA
+				DDRSS0_PHY_862_DATA
+				DDRSS0_PHY_863_DATA
+				DDRSS0_PHY_864_DATA
+				DDRSS0_PHY_865_DATA
+				DDRSS0_PHY_866_DATA
+				DDRSS0_PHY_867_DATA
+				DDRSS0_PHY_868_DATA
+				DDRSS0_PHY_869_DATA
+				DDRSS0_PHY_870_DATA
+				DDRSS0_PHY_871_DATA
+				DDRSS0_PHY_872_DATA
+				DDRSS0_PHY_873_DATA
+				DDRSS0_PHY_874_DATA
+				DDRSS0_PHY_875_DATA
+				DDRSS0_PHY_876_DATA
+				DDRSS0_PHY_877_DATA
+				DDRSS0_PHY_878_DATA
+				DDRSS0_PHY_879_DATA
+				DDRSS0_PHY_880_DATA
+				DDRSS0_PHY_881_DATA
+				DDRSS0_PHY_882_DATA
+				DDRSS0_PHY_883_DATA
+				DDRSS0_PHY_884_DATA
+				DDRSS0_PHY_885_DATA
+				DDRSS0_PHY_886_DATA
+				DDRSS0_PHY_887_DATA
+				DDRSS0_PHY_888_DATA
+				DDRSS0_PHY_889_DATA
+				DDRSS0_PHY_890_DATA
+				DDRSS0_PHY_891_DATA
+				DDRSS0_PHY_892_DATA
+				DDRSS0_PHY_893_DATA
+				DDRSS0_PHY_894_DATA
+				DDRSS0_PHY_895_DATA
+				DDRSS0_PHY_896_DATA
+				DDRSS0_PHY_897_DATA
+				DDRSS0_PHY_898_DATA
+				DDRSS0_PHY_899_DATA
+				DDRSS0_PHY_900_DATA
+				DDRSS0_PHY_901_DATA
+				DDRSS0_PHY_902_DATA
+				DDRSS0_PHY_903_DATA
+				DDRSS0_PHY_904_DATA
+				DDRSS0_PHY_905_DATA
+				DDRSS0_PHY_906_DATA
+				DDRSS0_PHY_907_DATA
+				DDRSS0_PHY_908_DATA
+				DDRSS0_PHY_909_DATA
+				DDRSS0_PHY_910_DATA
+				DDRSS0_PHY_911_DATA
+				DDRSS0_PHY_912_DATA
+				DDRSS0_PHY_913_DATA
+				DDRSS0_PHY_914_DATA
+				DDRSS0_PHY_915_DATA
+				DDRSS0_PHY_916_DATA
+				DDRSS0_PHY_917_DATA
+				DDRSS0_PHY_918_DATA
+				DDRSS0_PHY_919_DATA
+				DDRSS0_PHY_920_DATA
+				DDRSS0_PHY_921_DATA
+				DDRSS0_PHY_922_DATA
+				DDRSS0_PHY_923_DATA
+				DDRSS0_PHY_924_DATA
+				DDRSS0_PHY_925_DATA
+				DDRSS0_PHY_926_DATA
+				DDRSS0_PHY_927_DATA
+				DDRSS0_PHY_928_DATA
+				DDRSS0_PHY_929_DATA
+				DDRSS0_PHY_930_DATA
+				DDRSS0_PHY_931_DATA
+				DDRSS0_PHY_932_DATA
+				DDRSS0_PHY_933_DATA
+				DDRSS0_PHY_934_DATA
+				DDRSS0_PHY_935_DATA
+				DDRSS0_PHY_936_DATA
+				DDRSS0_PHY_937_DATA
+				DDRSS0_PHY_938_DATA
+				DDRSS0_PHY_939_DATA
+				DDRSS0_PHY_940_DATA
+				DDRSS0_PHY_941_DATA
+				DDRSS0_PHY_942_DATA
+				DDRSS0_PHY_943_DATA
+				DDRSS0_PHY_944_DATA
+				DDRSS0_PHY_945_DATA
+				DDRSS0_PHY_946_DATA
+				DDRSS0_PHY_947_DATA
+				DDRSS0_PHY_948_DATA
+				DDRSS0_PHY_949_DATA
+				DDRSS0_PHY_950_DATA
+				DDRSS0_PHY_951_DATA
+				DDRSS0_PHY_952_DATA
+				DDRSS0_PHY_953_DATA
+				DDRSS0_PHY_954_DATA
+				DDRSS0_PHY_955_DATA
+				DDRSS0_PHY_956_DATA
+				DDRSS0_PHY_957_DATA
+				DDRSS0_PHY_958_DATA
+				DDRSS0_PHY_959_DATA
+				DDRSS0_PHY_960_DATA
+				DDRSS0_PHY_961_DATA
+				DDRSS0_PHY_962_DATA
+				DDRSS0_PHY_963_DATA
+				DDRSS0_PHY_964_DATA
+				DDRSS0_PHY_965_DATA
+				DDRSS0_PHY_966_DATA
+				DDRSS0_PHY_967_DATA
+				DDRSS0_PHY_968_DATA
+				DDRSS0_PHY_969_DATA
+				DDRSS0_PHY_970_DATA
+				DDRSS0_PHY_971_DATA
+				DDRSS0_PHY_972_DATA
+				DDRSS0_PHY_973_DATA
+				DDRSS0_PHY_974_DATA
+				DDRSS0_PHY_975_DATA
+				DDRSS0_PHY_976_DATA
+				DDRSS0_PHY_977_DATA
+				DDRSS0_PHY_978_DATA
+				DDRSS0_PHY_979_DATA
+				DDRSS0_PHY_980_DATA
+				DDRSS0_PHY_981_DATA
+				DDRSS0_PHY_982_DATA
+				DDRSS0_PHY_983_DATA
+				DDRSS0_PHY_984_DATA
+				DDRSS0_PHY_985_DATA
+				DDRSS0_PHY_986_DATA
+				DDRSS0_PHY_987_DATA
+				DDRSS0_PHY_988_DATA
+				DDRSS0_PHY_989_DATA
+				DDRSS0_PHY_990_DATA
+				DDRSS0_PHY_991_DATA
+				DDRSS0_PHY_992_DATA
+				DDRSS0_PHY_993_DATA
+				DDRSS0_PHY_994_DATA
+				DDRSS0_PHY_995_DATA
+				DDRSS0_PHY_996_DATA
+				DDRSS0_PHY_997_DATA
+				DDRSS0_PHY_998_DATA
+				DDRSS0_PHY_999_DATA
+				DDRSS0_PHY_1000_DATA
+				DDRSS0_PHY_1001_DATA
+				DDRSS0_PHY_1002_DATA
+				DDRSS0_PHY_1003_DATA
+				DDRSS0_PHY_1004_DATA
+				DDRSS0_PHY_1005_DATA
+				DDRSS0_PHY_1006_DATA
+				DDRSS0_PHY_1007_DATA
+				DDRSS0_PHY_1008_DATA
+				DDRSS0_PHY_1009_DATA
+				DDRSS0_PHY_1010_DATA
+				DDRSS0_PHY_1011_DATA
+				DDRSS0_PHY_1012_DATA
+				DDRSS0_PHY_1013_DATA
+				DDRSS0_PHY_1014_DATA
+				DDRSS0_PHY_1015_DATA
+				DDRSS0_PHY_1016_DATA
+				DDRSS0_PHY_1017_DATA
+				DDRSS0_PHY_1018_DATA
+				DDRSS0_PHY_1019_DATA
+				DDRSS0_PHY_1020_DATA
+				DDRSS0_PHY_1021_DATA
+				DDRSS0_PHY_1022_DATA
+				DDRSS0_PHY_1023_DATA
+				DDRSS0_PHY_1024_DATA
+				DDRSS0_PHY_1025_DATA
+				DDRSS0_PHY_1026_DATA
+				DDRSS0_PHY_1027_DATA
+				DDRSS0_PHY_1028_DATA
+				DDRSS0_PHY_1029_DATA
+				DDRSS0_PHY_1030_DATA
+				DDRSS0_PHY_1031_DATA
+				DDRSS0_PHY_1032_DATA
+				DDRSS0_PHY_1033_DATA
+				DDRSS0_PHY_1034_DATA
+				DDRSS0_PHY_1035_DATA
+				DDRSS0_PHY_1036_DATA
+				DDRSS0_PHY_1037_DATA
+				DDRSS0_PHY_1038_DATA
+				DDRSS0_PHY_1039_DATA
+				DDRSS0_PHY_1040_DATA
+				DDRSS0_PHY_1041_DATA
+				DDRSS0_PHY_1042_DATA
+				DDRSS0_PHY_1043_DATA
+				DDRSS0_PHY_1044_DATA
+				DDRSS0_PHY_1045_DATA
+				DDRSS0_PHY_1046_DATA
+				DDRSS0_PHY_1047_DATA
+				DDRSS0_PHY_1048_DATA
+				DDRSS0_PHY_1049_DATA
+				DDRSS0_PHY_1050_DATA
+				DDRSS0_PHY_1051_DATA
+				DDRSS0_PHY_1052_DATA
+				DDRSS0_PHY_1053_DATA
+				DDRSS0_PHY_1054_DATA
+				DDRSS0_PHY_1055_DATA
+				DDRSS0_PHY_1056_DATA
+				DDRSS0_PHY_1057_DATA
+				DDRSS0_PHY_1058_DATA
+				DDRSS0_PHY_1059_DATA
+				DDRSS0_PHY_1060_DATA
+				DDRSS0_PHY_1061_DATA
+				DDRSS0_PHY_1062_DATA
+				DDRSS0_PHY_1063_DATA
+				DDRSS0_PHY_1064_DATA
+				DDRSS0_PHY_1065_DATA
+				DDRSS0_PHY_1066_DATA
+				DDRSS0_PHY_1067_DATA
+				DDRSS0_PHY_1068_DATA
+				DDRSS0_PHY_1069_DATA
+				DDRSS0_PHY_1070_DATA
+				DDRSS0_PHY_1071_DATA
+				DDRSS0_PHY_1072_DATA
+				DDRSS0_PHY_1073_DATA
+				DDRSS0_PHY_1074_DATA
+				DDRSS0_PHY_1075_DATA
+				DDRSS0_PHY_1076_DATA
+				DDRSS0_PHY_1077_DATA
+				DDRSS0_PHY_1078_DATA
+				DDRSS0_PHY_1079_DATA
+				DDRSS0_PHY_1080_DATA
+				DDRSS0_PHY_1081_DATA
+				DDRSS0_PHY_1082_DATA
+				DDRSS0_PHY_1083_DATA
+				DDRSS0_PHY_1084_DATA
+				DDRSS0_PHY_1085_DATA
+				DDRSS0_PHY_1086_DATA
+				DDRSS0_PHY_1087_DATA
+				DDRSS0_PHY_1088_DATA
+				DDRSS0_PHY_1089_DATA
+				DDRSS0_PHY_1090_DATA
+				DDRSS0_PHY_1091_DATA
+				DDRSS0_PHY_1092_DATA
+				DDRSS0_PHY_1093_DATA
+				DDRSS0_PHY_1094_DATA
+				DDRSS0_PHY_1095_DATA
+				DDRSS0_PHY_1096_DATA
+				DDRSS0_PHY_1097_DATA
+				DDRSS0_PHY_1098_DATA
+				DDRSS0_PHY_1099_DATA
+				DDRSS0_PHY_1100_DATA
+				DDRSS0_PHY_1101_DATA
+				DDRSS0_PHY_1102_DATA
+				DDRSS0_PHY_1103_DATA
+				DDRSS0_PHY_1104_DATA
+				DDRSS0_PHY_1105_DATA
+				DDRSS0_PHY_1106_DATA
+				DDRSS0_PHY_1107_DATA
+				DDRSS0_PHY_1108_DATA
+				DDRSS0_PHY_1109_DATA
+				DDRSS0_PHY_1110_DATA
+				DDRSS0_PHY_1111_DATA
+				DDRSS0_PHY_1112_DATA
+				DDRSS0_PHY_1113_DATA
+				DDRSS0_PHY_1114_DATA
+				DDRSS0_PHY_1115_DATA
+				DDRSS0_PHY_1116_DATA
+				DDRSS0_PHY_1117_DATA
+				DDRSS0_PHY_1118_DATA
+				DDRSS0_PHY_1119_DATA
+				DDRSS0_PHY_1120_DATA
+				DDRSS0_PHY_1121_DATA
+				DDRSS0_PHY_1122_DATA
+				DDRSS0_PHY_1123_DATA
+				DDRSS0_PHY_1124_DATA
+				DDRSS0_PHY_1125_DATA
+				DDRSS0_PHY_1126_DATA
+				DDRSS0_PHY_1127_DATA
+				DDRSS0_PHY_1128_DATA
+				DDRSS0_PHY_1129_DATA
+				DDRSS0_PHY_1130_DATA
+				DDRSS0_PHY_1131_DATA
+				DDRSS0_PHY_1132_DATA
+				DDRSS0_PHY_1133_DATA
+				DDRSS0_PHY_1134_DATA
+				DDRSS0_PHY_1135_DATA
+				DDRSS0_PHY_1136_DATA
+				DDRSS0_PHY_1137_DATA
+				DDRSS0_PHY_1138_DATA
+				DDRSS0_PHY_1139_DATA
+				DDRSS0_PHY_1140_DATA
+				DDRSS0_PHY_1141_DATA
+				DDRSS0_PHY_1142_DATA
+				DDRSS0_PHY_1143_DATA
+				DDRSS0_PHY_1144_DATA
+				DDRSS0_PHY_1145_DATA
+				DDRSS0_PHY_1146_DATA
+				DDRSS0_PHY_1147_DATA
+				DDRSS0_PHY_1148_DATA
+				DDRSS0_PHY_1149_DATA
+				DDRSS0_PHY_1150_DATA
+				DDRSS0_PHY_1151_DATA
+				DDRSS0_PHY_1152_DATA
+				DDRSS0_PHY_1153_DATA
+				DDRSS0_PHY_1154_DATA
+				DDRSS0_PHY_1155_DATA
+				DDRSS0_PHY_1156_DATA
+				DDRSS0_PHY_1157_DATA
+				DDRSS0_PHY_1158_DATA
+				DDRSS0_PHY_1159_DATA
+				DDRSS0_PHY_1160_DATA
+				DDRSS0_PHY_1161_DATA
+				DDRSS0_PHY_1162_DATA
+				DDRSS0_PHY_1163_DATA
+				DDRSS0_PHY_1164_DATA
+				DDRSS0_PHY_1165_DATA
+				DDRSS0_PHY_1166_DATA
+				DDRSS0_PHY_1167_DATA
+				DDRSS0_PHY_1168_DATA
+				DDRSS0_PHY_1169_DATA
+				DDRSS0_PHY_1170_DATA
+				DDRSS0_PHY_1171_DATA
+				DDRSS0_PHY_1172_DATA
+				DDRSS0_PHY_1173_DATA
+				DDRSS0_PHY_1174_DATA
+				DDRSS0_PHY_1175_DATA
+				DDRSS0_PHY_1176_DATA
+				DDRSS0_PHY_1177_DATA
+				DDRSS0_PHY_1178_DATA
+				DDRSS0_PHY_1179_DATA
+				DDRSS0_PHY_1180_DATA
+				DDRSS0_PHY_1181_DATA
+				DDRSS0_PHY_1182_DATA
+				DDRSS0_PHY_1183_DATA
+				DDRSS0_PHY_1184_DATA
+				DDRSS0_PHY_1185_DATA
+				DDRSS0_PHY_1186_DATA
+				DDRSS0_PHY_1187_DATA
+				DDRSS0_PHY_1188_DATA
+				DDRSS0_PHY_1189_DATA
+				DDRSS0_PHY_1190_DATA
+				DDRSS0_PHY_1191_DATA
+				DDRSS0_PHY_1192_DATA
+				DDRSS0_PHY_1193_DATA
+				DDRSS0_PHY_1194_DATA
+				DDRSS0_PHY_1195_DATA
+				DDRSS0_PHY_1196_DATA
+				DDRSS0_PHY_1197_DATA
+				DDRSS0_PHY_1198_DATA
+				DDRSS0_PHY_1199_DATA
+				DDRSS0_PHY_1200_DATA
+				DDRSS0_PHY_1201_DATA
+				DDRSS0_PHY_1202_DATA
+				DDRSS0_PHY_1203_DATA
+				DDRSS0_PHY_1204_DATA
+				DDRSS0_PHY_1205_DATA
+				DDRSS0_PHY_1206_DATA
+				DDRSS0_PHY_1207_DATA
+				DDRSS0_PHY_1208_DATA
+				DDRSS0_PHY_1209_DATA
+				DDRSS0_PHY_1210_DATA
+				DDRSS0_PHY_1211_DATA
+				DDRSS0_PHY_1212_DATA
+				DDRSS0_PHY_1213_DATA
+				DDRSS0_PHY_1214_DATA
+				DDRSS0_PHY_1215_DATA
+				DDRSS0_PHY_1216_DATA
+				DDRSS0_PHY_1217_DATA
+				DDRSS0_PHY_1218_DATA
+				DDRSS0_PHY_1219_DATA
+				DDRSS0_PHY_1220_DATA
+				DDRSS0_PHY_1221_DATA
+				DDRSS0_PHY_1222_DATA
+				DDRSS0_PHY_1223_DATA
+				DDRSS0_PHY_1224_DATA
+				DDRSS0_PHY_1225_DATA
+				DDRSS0_PHY_1226_DATA
+				DDRSS0_PHY_1227_DATA
+				DDRSS0_PHY_1228_DATA
+				DDRSS0_PHY_1229_DATA
+				DDRSS0_PHY_1230_DATA
+				DDRSS0_PHY_1231_DATA
+				DDRSS0_PHY_1232_DATA
+				DDRSS0_PHY_1233_DATA
+				DDRSS0_PHY_1234_DATA
+				DDRSS0_PHY_1235_DATA
+				DDRSS0_PHY_1236_DATA
+				DDRSS0_PHY_1237_DATA
+				DDRSS0_PHY_1238_DATA
+				DDRSS0_PHY_1239_DATA
+				DDRSS0_PHY_1240_DATA
+				DDRSS0_PHY_1241_DATA
+				DDRSS0_PHY_1242_DATA
+				DDRSS0_PHY_1243_DATA
+				DDRSS0_PHY_1244_DATA
+				DDRSS0_PHY_1245_DATA
+				DDRSS0_PHY_1246_DATA
+				DDRSS0_PHY_1247_DATA
+				DDRSS0_PHY_1248_DATA
+				DDRSS0_PHY_1249_DATA
+				DDRSS0_PHY_1250_DATA
+				DDRSS0_PHY_1251_DATA
+				DDRSS0_PHY_1252_DATA
+				DDRSS0_PHY_1253_DATA
+				DDRSS0_PHY_1254_DATA
+				DDRSS0_PHY_1255_DATA
+				DDRSS0_PHY_1256_DATA
+				DDRSS0_PHY_1257_DATA
+				DDRSS0_PHY_1258_DATA
+				DDRSS0_PHY_1259_DATA
+				DDRSS0_PHY_1260_DATA
+				DDRSS0_PHY_1261_DATA
+				DDRSS0_PHY_1262_DATA
+				DDRSS0_PHY_1263_DATA
+				DDRSS0_PHY_1264_DATA
+				DDRSS0_PHY_1265_DATA
+				DDRSS0_PHY_1266_DATA
+				DDRSS0_PHY_1267_DATA
+				DDRSS0_PHY_1268_DATA
+				DDRSS0_PHY_1269_DATA
+				DDRSS0_PHY_1270_DATA
+				DDRSS0_PHY_1271_DATA
+				DDRSS0_PHY_1272_DATA
+				DDRSS0_PHY_1273_DATA
+				DDRSS0_PHY_1274_DATA
+				DDRSS0_PHY_1275_DATA
+				DDRSS0_PHY_1276_DATA
+				DDRSS0_PHY_1277_DATA
+				DDRSS0_PHY_1278_DATA
+				DDRSS0_PHY_1279_DATA
+				DDRSS0_PHY_1280_DATA
+				DDRSS0_PHY_1281_DATA
+				DDRSS0_PHY_1282_DATA
+				DDRSS0_PHY_1283_DATA
+				DDRSS0_PHY_1284_DATA
+				DDRSS0_PHY_1285_DATA
+				DDRSS0_PHY_1286_DATA
+				DDRSS0_PHY_1287_DATA
+				DDRSS0_PHY_1288_DATA
+				DDRSS0_PHY_1289_DATA
+				DDRSS0_PHY_1290_DATA
+				DDRSS0_PHY_1291_DATA
+				DDRSS0_PHY_1292_DATA
+				DDRSS0_PHY_1293_DATA
+				DDRSS0_PHY_1294_DATA
+				DDRSS0_PHY_1295_DATA
+				DDRSS0_PHY_1296_DATA
+				DDRSS0_PHY_1297_DATA
+				DDRSS0_PHY_1298_DATA
+				DDRSS0_PHY_1299_DATA
+				DDRSS0_PHY_1300_DATA
+				DDRSS0_PHY_1301_DATA
+				DDRSS0_PHY_1302_DATA
+				DDRSS0_PHY_1303_DATA
+				DDRSS0_PHY_1304_DATA
+				DDRSS0_PHY_1305_DATA
+				DDRSS0_PHY_1306_DATA
+				DDRSS0_PHY_1307_DATA
+				DDRSS0_PHY_1308_DATA
+				DDRSS0_PHY_1309_DATA
+				DDRSS0_PHY_1310_DATA
+				DDRSS0_PHY_1311_DATA
+				DDRSS0_PHY_1312_DATA
+				DDRSS0_PHY_1313_DATA
+				DDRSS0_PHY_1314_DATA
+				DDRSS0_PHY_1315_DATA
+				DDRSS0_PHY_1316_DATA
+				DDRSS0_PHY_1317_DATA
+				DDRSS0_PHY_1318_DATA
+				DDRSS0_PHY_1319_DATA
+				DDRSS0_PHY_1320_DATA
+				DDRSS0_PHY_1321_DATA
+				DDRSS0_PHY_1322_DATA
+				DDRSS0_PHY_1323_DATA
+				DDRSS0_PHY_1324_DATA
+				DDRSS0_PHY_1325_DATA
+				DDRSS0_PHY_1326_DATA
+				DDRSS0_PHY_1327_DATA
+				DDRSS0_PHY_1328_DATA
+				DDRSS0_PHY_1329_DATA
+				DDRSS0_PHY_1330_DATA
+				DDRSS0_PHY_1331_DATA
+				DDRSS0_PHY_1332_DATA
+				DDRSS0_PHY_1333_DATA
+				DDRSS0_PHY_1334_DATA
+				DDRSS0_PHY_1335_DATA
+				DDRSS0_PHY_1336_DATA
+				DDRSS0_PHY_1337_DATA
+				DDRSS0_PHY_1338_DATA
+				DDRSS0_PHY_1339_DATA
+				DDRSS0_PHY_1340_DATA
+				DDRSS0_PHY_1341_DATA
+				DDRSS0_PHY_1342_DATA
+				DDRSS0_PHY_1343_DATA
+				DDRSS0_PHY_1344_DATA
+				DDRSS0_PHY_1345_DATA
+				DDRSS0_PHY_1346_DATA
+				DDRSS0_PHY_1347_DATA
+				DDRSS0_PHY_1348_DATA
+				DDRSS0_PHY_1349_DATA
+				DDRSS0_PHY_1350_DATA
+				DDRSS0_PHY_1351_DATA
+				DDRSS0_PHY_1352_DATA
+				DDRSS0_PHY_1353_DATA
+				DDRSS0_PHY_1354_DATA
+				DDRSS0_PHY_1355_DATA
+				DDRSS0_PHY_1356_DATA
+				DDRSS0_PHY_1357_DATA
+				DDRSS0_PHY_1358_DATA
+				DDRSS0_PHY_1359_DATA
+				DDRSS0_PHY_1360_DATA
+				DDRSS0_PHY_1361_DATA
+				DDRSS0_PHY_1362_DATA
+				DDRSS0_PHY_1363_DATA
+				DDRSS0_PHY_1364_DATA
+				DDRSS0_PHY_1365_DATA
+				DDRSS0_PHY_1366_DATA
+				DDRSS0_PHY_1367_DATA
+				DDRSS0_PHY_1368_DATA
+				DDRSS0_PHY_1369_DATA
+				DDRSS0_PHY_1370_DATA
+				DDRSS0_PHY_1371_DATA
+				DDRSS0_PHY_1372_DATA
+				DDRSS0_PHY_1373_DATA
+				DDRSS0_PHY_1374_DATA
+				DDRSS0_PHY_1375_DATA
+				DDRSS0_PHY_1376_DATA
+				DDRSS0_PHY_1377_DATA
+				DDRSS0_PHY_1378_DATA
+				DDRSS0_PHY_1379_DATA
+				DDRSS0_PHY_1380_DATA
+				DDRSS0_PHY_1381_DATA
+				DDRSS0_PHY_1382_DATA
+				DDRSS0_PHY_1383_DATA
+				DDRSS0_PHY_1384_DATA
+				DDRSS0_PHY_1385_DATA
+				DDRSS0_PHY_1386_DATA
+				DDRSS0_PHY_1387_DATA
+				DDRSS0_PHY_1388_DATA
+				DDRSS0_PHY_1389_DATA
+				DDRSS0_PHY_1390_DATA
+				DDRSS0_PHY_1391_DATA
+				DDRSS0_PHY_1392_DATA
+				DDRSS0_PHY_1393_DATA
+				DDRSS0_PHY_1394_DATA
+				DDRSS0_PHY_1395_DATA
+				DDRSS0_PHY_1396_DATA
+				DDRSS0_PHY_1397_DATA
+				DDRSS0_PHY_1398_DATA
+				DDRSS0_PHY_1399_DATA
+				DDRSS0_PHY_1400_DATA
+				DDRSS0_PHY_1401_DATA
+				DDRSS0_PHY_1402_DATA
+				DDRSS0_PHY_1403_DATA
+				DDRSS0_PHY_1404_DATA
+				DDRSS0_PHY_1405_DATA
+				DDRSS0_PHY_1406_DATA
+				DDRSS0_PHY_1407_DATA
+				DDRSS0_PHY_1408_DATA
+				DDRSS0_PHY_1409_DATA
+				DDRSS0_PHY_1410_DATA
+				DDRSS0_PHY_1411_DATA
+				DDRSS0_PHY_1412_DATA
+				DDRSS0_PHY_1413_DATA
+				DDRSS0_PHY_1414_DATA
+				DDRSS0_PHY_1415_DATA
+				DDRSS0_PHY_1416_DATA
+				DDRSS0_PHY_1417_DATA
+				DDRSS0_PHY_1418_DATA
+				DDRSS0_PHY_1419_DATA
+				DDRSS0_PHY_1420_DATA
+				DDRSS0_PHY_1421_DATA
+				DDRSS0_PHY_1422_DATA
+			>;
+		};
+
+		memorycontroller1: memorycontroller@29b0000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x029b0000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+				  <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+				<&k3_pds 132 TI_SCI_PD_SHARED>;
+			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
+			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+			instance = <1>;
+
+			bootph-pre-ram;
+
+			ti,ctl-data = <
+				DDRSS1_CTL_00_DATA
+				DDRSS1_CTL_01_DATA
+				DDRSS1_CTL_02_DATA
+				DDRSS1_CTL_03_DATA
+				DDRSS1_CTL_04_DATA
+				DDRSS1_CTL_05_DATA
+				DDRSS1_CTL_06_DATA
+				DDRSS1_CTL_07_DATA
+				DDRSS1_CTL_08_DATA
+				DDRSS1_CTL_09_DATA
+				DDRSS1_CTL_10_DATA
+				DDRSS1_CTL_11_DATA
+				DDRSS1_CTL_12_DATA
+				DDRSS1_CTL_13_DATA
+				DDRSS1_CTL_14_DATA
+				DDRSS1_CTL_15_DATA
+				DDRSS1_CTL_16_DATA
+				DDRSS1_CTL_17_DATA
+				DDRSS1_CTL_18_DATA
+				DDRSS1_CTL_19_DATA
+				DDRSS1_CTL_20_DATA
+				DDRSS1_CTL_21_DATA
+				DDRSS1_CTL_22_DATA
+				DDRSS1_CTL_23_DATA
+				DDRSS1_CTL_24_DATA
+				DDRSS1_CTL_25_DATA
+				DDRSS1_CTL_26_DATA
+				DDRSS1_CTL_27_DATA
+				DDRSS1_CTL_28_DATA
+				DDRSS1_CTL_29_DATA
+				DDRSS1_CTL_30_DATA
+				DDRSS1_CTL_31_DATA
+				DDRSS1_CTL_32_DATA
+				DDRSS1_CTL_33_DATA
+				DDRSS1_CTL_34_DATA
+				DDRSS1_CTL_35_DATA
+				DDRSS1_CTL_36_DATA
+				DDRSS1_CTL_37_DATA
+				DDRSS1_CTL_38_DATA
+				DDRSS1_CTL_39_DATA
+				DDRSS1_CTL_40_DATA
+				DDRSS1_CTL_41_DATA
+				DDRSS1_CTL_42_DATA
+				DDRSS1_CTL_43_DATA
+				DDRSS1_CTL_44_DATA
+				DDRSS1_CTL_45_DATA
+				DDRSS1_CTL_46_DATA
+				DDRSS1_CTL_47_DATA
+				DDRSS1_CTL_48_DATA
+				DDRSS1_CTL_49_DATA
+				DDRSS1_CTL_50_DATA
+				DDRSS1_CTL_51_DATA
+				DDRSS1_CTL_52_DATA
+				DDRSS1_CTL_53_DATA
+				DDRSS1_CTL_54_DATA
+				DDRSS1_CTL_55_DATA
+				DDRSS1_CTL_56_DATA
+				DDRSS1_CTL_57_DATA
+				DDRSS1_CTL_58_DATA
+				DDRSS1_CTL_59_DATA
+				DDRSS1_CTL_60_DATA
+				DDRSS1_CTL_61_DATA
+				DDRSS1_CTL_62_DATA
+				DDRSS1_CTL_63_DATA
+				DDRSS1_CTL_64_DATA
+				DDRSS1_CTL_65_DATA
+				DDRSS1_CTL_66_DATA
+				DDRSS1_CTL_67_DATA
+				DDRSS1_CTL_68_DATA
+				DDRSS1_CTL_69_DATA
+				DDRSS1_CTL_70_DATA
+				DDRSS1_CTL_71_DATA
+				DDRSS1_CTL_72_DATA
+				DDRSS1_CTL_73_DATA
+				DDRSS1_CTL_74_DATA
+				DDRSS1_CTL_75_DATA
+				DDRSS1_CTL_76_DATA
+				DDRSS1_CTL_77_DATA
+				DDRSS1_CTL_78_DATA
+				DDRSS1_CTL_79_DATA
+				DDRSS1_CTL_80_DATA
+				DDRSS1_CTL_81_DATA
+				DDRSS1_CTL_82_DATA
+				DDRSS1_CTL_83_DATA
+				DDRSS1_CTL_84_DATA
+				DDRSS1_CTL_85_DATA
+				DDRSS1_CTL_86_DATA
+				DDRSS1_CTL_87_DATA
+				DDRSS1_CTL_88_DATA
+				DDRSS1_CTL_89_DATA
+				DDRSS1_CTL_90_DATA
+				DDRSS1_CTL_91_DATA
+				DDRSS1_CTL_92_DATA
+				DDRSS1_CTL_93_DATA
+				DDRSS1_CTL_94_DATA
+				DDRSS1_CTL_95_DATA
+				DDRSS1_CTL_96_DATA
+				DDRSS1_CTL_97_DATA
+				DDRSS1_CTL_98_DATA
+				DDRSS1_CTL_99_DATA
+				DDRSS1_CTL_100_DATA
+				DDRSS1_CTL_101_DATA
+				DDRSS1_CTL_102_DATA
+				DDRSS1_CTL_103_DATA
+				DDRSS1_CTL_104_DATA
+				DDRSS1_CTL_105_DATA
+				DDRSS1_CTL_106_DATA
+				DDRSS1_CTL_107_DATA
+				DDRSS1_CTL_108_DATA
+				DDRSS1_CTL_109_DATA
+				DDRSS1_CTL_110_DATA
+				DDRSS1_CTL_111_DATA
+				DDRSS1_CTL_112_DATA
+				DDRSS1_CTL_113_DATA
+				DDRSS1_CTL_114_DATA
+				DDRSS1_CTL_115_DATA
+				DDRSS1_CTL_116_DATA
+				DDRSS1_CTL_117_DATA
+				DDRSS1_CTL_118_DATA
+				DDRSS1_CTL_119_DATA
+				DDRSS1_CTL_120_DATA
+				DDRSS1_CTL_121_DATA
+				DDRSS1_CTL_122_DATA
+				DDRSS1_CTL_123_DATA
+				DDRSS1_CTL_124_DATA
+				DDRSS1_CTL_125_DATA
+				DDRSS1_CTL_126_DATA
+				DDRSS1_CTL_127_DATA
+				DDRSS1_CTL_128_DATA
+				DDRSS1_CTL_129_DATA
+				DDRSS1_CTL_130_DATA
+				DDRSS1_CTL_131_DATA
+				DDRSS1_CTL_132_DATA
+				DDRSS1_CTL_133_DATA
+				DDRSS1_CTL_134_DATA
+				DDRSS1_CTL_135_DATA
+				DDRSS1_CTL_136_DATA
+				DDRSS1_CTL_137_DATA
+				DDRSS1_CTL_138_DATA
+				DDRSS1_CTL_139_DATA
+				DDRSS1_CTL_140_DATA
+				DDRSS1_CTL_141_DATA
+				DDRSS1_CTL_142_DATA
+				DDRSS1_CTL_143_DATA
+				DDRSS1_CTL_144_DATA
+				DDRSS1_CTL_145_DATA
+				DDRSS1_CTL_146_DATA
+				DDRSS1_CTL_147_DATA
+				DDRSS1_CTL_148_DATA
+				DDRSS1_CTL_149_DATA
+				DDRSS1_CTL_150_DATA
+				DDRSS1_CTL_151_DATA
+				DDRSS1_CTL_152_DATA
+				DDRSS1_CTL_153_DATA
+				DDRSS1_CTL_154_DATA
+				DDRSS1_CTL_155_DATA
+				DDRSS1_CTL_156_DATA
+				DDRSS1_CTL_157_DATA
+				DDRSS1_CTL_158_DATA
+				DDRSS1_CTL_159_DATA
+				DDRSS1_CTL_160_DATA
+				DDRSS1_CTL_161_DATA
+				DDRSS1_CTL_162_DATA
+				DDRSS1_CTL_163_DATA
+				DDRSS1_CTL_164_DATA
+				DDRSS1_CTL_165_DATA
+				DDRSS1_CTL_166_DATA
+				DDRSS1_CTL_167_DATA
+				DDRSS1_CTL_168_DATA
+				DDRSS1_CTL_169_DATA
+				DDRSS1_CTL_170_DATA
+				DDRSS1_CTL_171_DATA
+				DDRSS1_CTL_172_DATA
+				DDRSS1_CTL_173_DATA
+				DDRSS1_CTL_174_DATA
+				DDRSS1_CTL_175_DATA
+				DDRSS1_CTL_176_DATA
+				DDRSS1_CTL_177_DATA
+				DDRSS1_CTL_178_DATA
+				DDRSS1_CTL_179_DATA
+				DDRSS1_CTL_180_DATA
+				DDRSS1_CTL_181_DATA
+				DDRSS1_CTL_182_DATA
+				DDRSS1_CTL_183_DATA
+				DDRSS1_CTL_184_DATA
+				DDRSS1_CTL_185_DATA
+				DDRSS1_CTL_186_DATA
+				DDRSS1_CTL_187_DATA
+				DDRSS1_CTL_188_DATA
+				DDRSS1_CTL_189_DATA
+				DDRSS1_CTL_190_DATA
+				DDRSS1_CTL_191_DATA
+				DDRSS1_CTL_192_DATA
+				DDRSS1_CTL_193_DATA
+				DDRSS1_CTL_194_DATA
+				DDRSS1_CTL_195_DATA
+				DDRSS1_CTL_196_DATA
+				DDRSS1_CTL_197_DATA
+				DDRSS1_CTL_198_DATA
+				DDRSS1_CTL_199_DATA
+				DDRSS1_CTL_200_DATA
+				DDRSS1_CTL_201_DATA
+				DDRSS1_CTL_202_DATA
+				DDRSS1_CTL_203_DATA
+				DDRSS1_CTL_204_DATA
+				DDRSS1_CTL_205_DATA
+				DDRSS1_CTL_206_DATA
+				DDRSS1_CTL_207_DATA
+				DDRSS1_CTL_208_DATA
+				DDRSS1_CTL_209_DATA
+				DDRSS1_CTL_210_DATA
+				DDRSS1_CTL_211_DATA
+				DDRSS1_CTL_212_DATA
+				DDRSS1_CTL_213_DATA
+				DDRSS1_CTL_214_DATA
+				DDRSS1_CTL_215_DATA
+				DDRSS1_CTL_216_DATA
+				DDRSS1_CTL_217_DATA
+				DDRSS1_CTL_218_DATA
+				DDRSS1_CTL_219_DATA
+				DDRSS1_CTL_220_DATA
+				DDRSS1_CTL_221_DATA
+				DDRSS1_CTL_222_DATA
+				DDRSS1_CTL_223_DATA
+				DDRSS1_CTL_224_DATA
+				DDRSS1_CTL_225_DATA
+				DDRSS1_CTL_226_DATA
+				DDRSS1_CTL_227_DATA
+				DDRSS1_CTL_228_DATA
+				DDRSS1_CTL_229_DATA
+				DDRSS1_CTL_230_DATA
+				DDRSS1_CTL_231_DATA
+				DDRSS1_CTL_232_DATA
+				DDRSS1_CTL_233_DATA
+				DDRSS1_CTL_234_DATA
+				DDRSS1_CTL_235_DATA
+				DDRSS1_CTL_236_DATA
+				DDRSS1_CTL_237_DATA
+				DDRSS1_CTL_238_DATA
+				DDRSS1_CTL_239_DATA
+				DDRSS1_CTL_240_DATA
+				DDRSS1_CTL_241_DATA
+				DDRSS1_CTL_242_DATA
+				DDRSS1_CTL_243_DATA
+				DDRSS1_CTL_244_DATA
+				DDRSS1_CTL_245_DATA
+				DDRSS1_CTL_246_DATA
+				DDRSS1_CTL_247_DATA
+				DDRSS1_CTL_248_DATA
+				DDRSS1_CTL_249_DATA
+				DDRSS1_CTL_250_DATA
+				DDRSS1_CTL_251_DATA
+				DDRSS1_CTL_252_DATA
+				DDRSS1_CTL_253_DATA
+				DDRSS1_CTL_254_DATA
+				DDRSS1_CTL_255_DATA
+				DDRSS1_CTL_256_DATA
+				DDRSS1_CTL_257_DATA
+				DDRSS1_CTL_258_DATA
+				DDRSS1_CTL_259_DATA
+				DDRSS1_CTL_260_DATA
+				DDRSS1_CTL_261_DATA
+				DDRSS1_CTL_262_DATA
+				DDRSS1_CTL_263_DATA
+				DDRSS1_CTL_264_DATA
+				DDRSS1_CTL_265_DATA
+				DDRSS1_CTL_266_DATA
+				DDRSS1_CTL_267_DATA
+				DDRSS1_CTL_268_DATA
+				DDRSS1_CTL_269_DATA
+				DDRSS1_CTL_270_DATA
+				DDRSS1_CTL_271_DATA
+				DDRSS1_CTL_272_DATA
+				DDRSS1_CTL_273_DATA
+				DDRSS1_CTL_274_DATA
+				DDRSS1_CTL_275_DATA
+				DDRSS1_CTL_276_DATA
+				DDRSS1_CTL_277_DATA
+				DDRSS1_CTL_278_DATA
+				DDRSS1_CTL_279_DATA
+				DDRSS1_CTL_280_DATA
+				DDRSS1_CTL_281_DATA
+				DDRSS1_CTL_282_DATA
+				DDRSS1_CTL_283_DATA
+				DDRSS1_CTL_284_DATA
+				DDRSS1_CTL_285_DATA
+				DDRSS1_CTL_286_DATA
+				DDRSS1_CTL_287_DATA
+				DDRSS1_CTL_288_DATA
+				DDRSS1_CTL_289_DATA
+				DDRSS1_CTL_290_DATA
+				DDRSS1_CTL_291_DATA
+				DDRSS1_CTL_292_DATA
+				DDRSS1_CTL_293_DATA
+				DDRSS1_CTL_294_DATA
+				DDRSS1_CTL_295_DATA
+				DDRSS1_CTL_296_DATA
+				DDRSS1_CTL_297_DATA
+				DDRSS1_CTL_298_DATA
+				DDRSS1_CTL_299_DATA
+				DDRSS1_CTL_300_DATA
+				DDRSS1_CTL_301_DATA
+				DDRSS1_CTL_302_DATA
+				DDRSS1_CTL_303_DATA
+				DDRSS1_CTL_304_DATA
+				DDRSS1_CTL_305_DATA
+				DDRSS1_CTL_306_DATA
+				DDRSS1_CTL_307_DATA
+				DDRSS1_CTL_308_DATA
+				DDRSS1_CTL_309_DATA
+				DDRSS1_CTL_310_DATA
+				DDRSS1_CTL_311_DATA
+				DDRSS1_CTL_312_DATA
+				DDRSS1_CTL_313_DATA
+				DDRSS1_CTL_314_DATA
+				DDRSS1_CTL_315_DATA
+				DDRSS1_CTL_316_DATA
+				DDRSS1_CTL_317_DATA
+				DDRSS1_CTL_318_DATA
+				DDRSS1_CTL_319_DATA
+				DDRSS1_CTL_320_DATA
+				DDRSS1_CTL_321_DATA
+				DDRSS1_CTL_322_DATA
+				DDRSS1_CTL_323_DATA
+				DDRSS1_CTL_324_DATA
+				DDRSS1_CTL_325_DATA
+				DDRSS1_CTL_326_DATA
+				DDRSS1_CTL_327_DATA
+				DDRSS1_CTL_328_DATA
+				DDRSS1_CTL_329_DATA
+				DDRSS1_CTL_330_DATA
+				DDRSS1_CTL_331_DATA
+				DDRSS1_CTL_332_DATA
+				DDRSS1_CTL_333_DATA
+				DDRSS1_CTL_334_DATA
+				DDRSS1_CTL_335_DATA
+				DDRSS1_CTL_336_DATA
+				DDRSS1_CTL_337_DATA
+				DDRSS1_CTL_338_DATA
+				DDRSS1_CTL_339_DATA
+				DDRSS1_CTL_340_DATA
+				DDRSS1_CTL_341_DATA
+				DDRSS1_CTL_342_DATA
+				DDRSS1_CTL_343_DATA
+				DDRSS1_CTL_344_DATA
+				DDRSS1_CTL_345_DATA
+				DDRSS1_CTL_346_DATA
+				DDRSS1_CTL_347_DATA
+				DDRSS1_CTL_348_DATA
+				DDRSS1_CTL_349_DATA
+				DDRSS1_CTL_350_DATA
+				DDRSS1_CTL_351_DATA
+				DDRSS1_CTL_352_DATA
+				DDRSS1_CTL_353_DATA
+				DDRSS1_CTL_354_DATA
+				DDRSS1_CTL_355_DATA
+				DDRSS1_CTL_356_DATA
+				DDRSS1_CTL_357_DATA
+				DDRSS1_CTL_358_DATA
+				DDRSS1_CTL_359_DATA
+				DDRSS1_CTL_360_DATA
+				DDRSS1_CTL_361_DATA
+				DDRSS1_CTL_362_DATA
+				DDRSS1_CTL_363_DATA
+				DDRSS1_CTL_364_DATA
+				DDRSS1_CTL_365_DATA
+				DDRSS1_CTL_366_DATA
+				DDRSS1_CTL_367_DATA
+				DDRSS1_CTL_368_DATA
+				DDRSS1_CTL_369_DATA
+				DDRSS1_CTL_370_DATA
+				DDRSS1_CTL_371_DATA
+				DDRSS1_CTL_372_DATA
+				DDRSS1_CTL_373_DATA
+				DDRSS1_CTL_374_DATA
+				DDRSS1_CTL_375_DATA
+				DDRSS1_CTL_376_DATA
+				DDRSS1_CTL_377_DATA
+				DDRSS1_CTL_378_DATA
+				DDRSS1_CTL_379_DATA
+				DDRSS1_CTL_380_DATA
+				DDRSS1_CTL_381_DATA
+				DDRSS1_CTL_382_DATA
+				DDRSS1_CTL_383_DATA
+				DDRSS1_CTL_384_DATA
+				DDRSS1_CTL_385_DATA
+				DDRSS1_CTL_386_DATA
+				DDRSS1_CTL_387_DATA
+				DDRSS1_CTL_388_DATA
+				DDRSS1_CTL_389_DATA
+				DDRSS1_CTL_390_DATA
+				DDRSS1_CTL_391_DATA
+				DDRSS1_CTL_392_DATA
+				DDRSS1_CTL_393_DATA
+				DDRSS1_CTL_394_DATA
+				DDRSS1_CTL_395_DATA
+				DDRSS1_CTL_396_DATA
+				DDRSS1_CTL_397_DATA
+				DDRSS1_CTL_398_DATA
+				DDRSS1_CTL_399_DATA
+				DDRSS1_CTL_400_DATA
+				DDRSS1_CTL_401_DATA
+				DDRSS1_CTL_402_DATA
+				DDRSS1_CTL_403_DATA
+				DDRSS1_CTL_404_DATA
+				DDRSS1_CTL_405_DATA
+				DDRSS1_CTL_406_DATA
+				DDRSS1_CTL_407_DATA
+				DDRSS1_CTL_408_DATA
+				DDRSS1_CTL_409_DATA
+				DDRSS1_CTL_410_DATA
+				DDRSS1_CTL_411_DATA
+				DDRSS1_CTL_412_DATA
+				DDRSS1_CTL_413_DATA
+				DDRSS1_CTL_414_DATA
+				DDRSS1_CTL_415_DATA
+				DDRSS1_CTL_416_DATA
+				DDRSS1_CTL_417_DATA
+				DDRSS1_CTL_418_DATA
+				DDRSS1_CTL_419_DATA
+				DDRSS1_CTL_420_DATA
+				DDRSS1_CTL_421_DATA
+				DDRSS1_CTL_422_DATA
+				DDRSS1_CTL_423_DATA
+				DDRSS1_CTL_424_DATA
+				DDRSS1_CTL_425_DATA
+				DDRSS1_CTL_426_DATA
+				DDRSS1_CTL_427_DATA
+				DDRSS1_CTL_428_DATA
+				DDRSS1_CTL_429_DATA
+				DDRSS1_CTL_430_DATA
+				DDRSS1_CTL_431_DATA
+				DDRSS1_CTL_432_DATA
+				DDRSS1_CTL_433_DATA
+				DDRSS1_CTL_434_DATA
+				DDRSS1_CTL_435_DATA
+				DDRSS1_CTL_436_DATA
+				DDRSS1_CTL_437_DATA
+				DDRSS1_CTL_438_DATA
+				DDRSS1_CTL_439_DATA
+				DDRSS1_CTL_440_DATA
+				DDRSS1_CTL_441_DATA
+				DDRSS1_CTL_442_DATA
+				DDRSS1_CTL_443_DATA
+				DDRSS1_CTL_444_DATA
+				DDRSS1_CTL_445_DATA
+				DDRSS1_CTL_446_DATA
+				DDRSS1_CTL_447_DATA
+				DDRSS1_CTL_448_DATA
+				DDRSS1_CTL_449_DATA
+				DDRSS1_CTL_450_DATA
+				DDRSS1_CTL_451_DATA
+				DDRSS1_CTL_452_DATA
+				DDRSS1_CTL_453_DATA
+				DDRSS1_CTL_454_DATA
+				DDRSS1_CTL_455_DATA
+				DDRSS1_CTL_456_DATA
+				DDRSS1_CTL_457_DATA
+				DDRSS1_CTL_458_DATA
+			>;
+
+			ti,pi-data = <
+				DDRSS1_PI_00_DATA
+				DDRSS1_PI_01_DATA
+				DDRSS1_PI_02_DATA
+				DDRSS1_PI_03_DATA
+				DDRSS1_PI_04_DATA
+				DDRSS1_PI_05_DATA
+				DDRSS1_PI_06_DATA
+				DDRSS1_PI_07_DATA
+				DDRSS1_PI_08_DATA
+				DDRSS1_PI_09_DATA
+				DDRSS1_PI_10_DATA
+				DDRSS1_PI_11_DATA
+				DDRSS1_PI_12_DATA
+				DDRSS1_PI_13_DATA
+				DDRSS1_PI_14_DATA
+				DDRSS1_PI_15_DATA
+				DDRSS1_PI_16_DATA
+				DDRSS1_PI_17_DATA
+				DDRSS1_PI_18_DATA
+				DDRSS1_PI_19_DATA
+				DDRSS1_PI_20_DATA
+				DDRSS1_PI_21_DATA
+				DDRSS1_PI_22_DATA
+				DDRSS1_PI_23_DATA
+				DDRSS1_PI_24_DATA
+				DDRSS1_PI_25_DATA
+				DDRSS1_PI_26_DATA
+				DDRSS1_PI_27_DATA
+				DDRSS1_PI_28_DATA
+				DDRSS1_PI_29_DATA
+				DDRSS1_PI_30_DATA
+				DDRSS1_PI_31_DATA
+				DDRSS1_PI_32_DATA
+				DDRSS1_PI_33_DATA
+				DDRSS1_PI_34_DATA
+				DDRSS1_PI_35_DATA
+				DDRSS1_PI_36_DATA
+				DDRSS1_PI_37_DATA
+				DDRSS1_PI_38_DATA
+				DDRSS1_PI_39_DATA
+				DDRSS1_PI_40_DATA
+				DDRSS1_PI_41_DATA
+				DDRSS1_PI_42_DATA
+				DDRSS1_PI_43_DATA
+				DDRSS1_PI_44_DATA
+				DDRSS1_PI_45_DATA
+				DDRSS1_PI_46_DATA
+				DDRSS1_PI_47_DATA
+				DDRSS1_PI_48_DATA
+				DDRSS1_PI_49_DATA
+				DDRSS1_PI_50_DATA
+				DDRSS1_PI_51_DATA
+				DDRSS1_PI_52_DATA
+				DDRSS1_PI_53_DATA
+				DDRSS1_PI_54_DATA
+				DDRSS1_PI_55_DATA
+				DDRSS1_PI_56_DATA
+				DDRSS1_PI_57_DATA
+				DDRSS1_PI_58_DATA
+				DDRSS1_PI_59_DATA
+				DDRSS1_PI_60_DATA
+				DDRSS1_PI_61_DATA
+				DDRSS1_PI_62_DATA
+				DDRSS1_PI_63_DATA
+				DDRSS1_PI_64_DATA
+				DDRSS1_PI_65_DATA
+				DDRSS1_PI_66_DATA
+				DDRSS1_PI_67_DATA
+				DDRSS1_PI_68_DATA
+				DDRSS1_PI_69_DATA
+				DDRSS1_PI_70_DATA
+				DDRSS1_PI_71_DATA
+				DDRSS1_PI_72_DATA
+				DDRSS1_PI_73_DATA
+				DDRSS1_PI_74_DATA
+				DDRSS1_PI_75_DATA
+				DDRSS1_PI_76_DATA
+				DDRSS1_PI_77_DATA
+				DDRSS1_PI_78_DATA
+				DDRSS1_PI_79_DATA
+				DDRSS1_PI_80_DATA
+				DDRSS1_PI_81_DATA
+				DDRSS1_PI_82_DATA
+				DDRSS1_PI_83_DATA
+				DDRSS1_PI_84_DATA
+				DDRSS1_PI_85_DATA
+				DDRSS1_PI_86_DATA
+				DDRSS1_PI_87_DATA
+				DDRSS1_PI_88_DATA
+				DDRSS1_PI_89_DATA
+				DDRSS1_PI_90_DATA
+				DDRSS1_PI_91_DATA
+				DDRSS1_PI_92_DATA
+				DDRSS1_PI_93_DATA
+				DDRSS1_PI_94_DATA
+				DDRSS1_PI_95_DATA
+				DDRSS1_PI_96_DATA
+				DDRSS1_PI_97_DATA
+				DDRSS1_PI_98_DATA
+				DDRSS1_PI_99_DATA
+				DDRSS1_PI_100_DATA
+				DDRSS1_PI_101_DATA
+				DDRSS1_PI_102_DATA
+				DDRSS1_PI_103_DATA
+				DDRSS1_PI_104_DATA
+				DDRSS1_PI_105_DATA
+				DDRSS1_PI_106_DATA
+				DDRSS1_PI_107_DATA
+				DDRSS1_PI_108_DATA
+				DDRSS1_PI_109_DATA
+				DDRSS1_PI_110_DATA
+				DDRSS1_PI_111_DATA
+				DDRSS1_PI_112_DATA
+				DDRSS1_PI_113_DATA
+				DDRSS1_PI_114_DATA
+				DDRSS1_PI_115_DATA
+				DDRSS1_PI_116_DATA
+				DDRSS1_PI_117_DATA
+				DDRSS1_PI_118_DATA
+				DDRSS1_PI_119_DATA
+				DDRSS1_PI_120_DATA
+				DDRSS1_PI_121_DATA
+				DDRSS1_PI_122_DATA
+				DDRSS1_PI_123_DATA
+				DDRSS1_PI_124_DATA
+				DDRSS1_PI_125_DATA
+				DDRSS1_PI_126_DATA
+				DDRSS1_PI_127_DATA
+				DDRSS1_PI_128_DATA
+				DDRSS1_PI_129_DATA
+				DDRSS1_PI_130_DATA
+				DDRSS1_PI_131_DATA
+				DDRSS1_PI_132_DATA
+				DDRSS1_PI_133_DATA
+				DDRSS1_PI_134_DATA
+				DDRSS1_PI_135_DATA
+				DDRSS1_PI_136_DATA
+				DDRSS1_PI_137_DATA
+				DDRSS1_PI_138_DATA
+				DDRSS1_PI_139_DATA
+				DDRSS1_PI_140_DATA
+				DDRSS1_PI_141_DATA
+				DDRSS1_PI_142_DATA
+				DDRSS1_PI_143_DATA
+				DDRSS1_PI_144_DATA
+				DDRSS1_PI_145_DATA
+				DDRSS1_PI_146_DATA
+				DDRSS1_PI_147_DATA
+				DDRSS1_PI_148_DATA
+				DDRSS1_PI_149_DATA
+				DDRSS1_PI_150_DATA
+				DDRSS1_PI_151_DATA
+				DDRSS1_PI_152_DATA
+				DDRSS1_PI_153_DATA
+				DDRSS1_PI_154_DATA
+				DDRSS1_PI_155_DATA
+				DDRSS1_PI_156_DATA
+				DDRSS1_PI_157_DATA
+				DDRSS1_PI_158_DATA
+				DDRSS1_PI_159_DATA
+				DDRSS1_PI_160_DATA
+				DDRSS1_PI_161_DATA
+				DDRSS1_PI_162_DATA
+				DDRSS1_PI_163_DATA
+				DDRSS1_PI_164_DATA
+				DDRSS1_PI_165_DATA
+				DDRSS1_PI_166_DATA
+				DDRSS1_PI_167_DATA
+				DDRSS1_PI_168_DATA
+				DDRSS1_PI_169_DATA
+				DDRSS1_PI_170_DATA
+				DDRSS1_PI_171_DATA
+				DDRSS1_PI_172_DATA
+				DDRSS1_PI_173_DATA
+				DDRSS1_PI_174_DATA
+				DDRSS1_PI_175_DATA
+				DDRSS1_PI_176_DATA
+				DDRSS1_PI_177_DATA
+				DDRSS1_PI_178_DATA
+				DDRSS1_PI_179_DATA
+				DDRSS1_PI_180_DATA
+				DDRSS1_PI_181_DATA
+				DDRSS1_PI_182_DATA
+				DDRSS1_PI_183_DATA
+				DDRSS1_PI_184_DATA
+				DDRSS1_PI_185_DATA
+				DDRSS1_PI_186_DATA
+				DDRSS1_PI_187_DATA
+				DDRSS1_PI_188_DATA
+				DDRSS1_PI_189_DATA
+				DDRSS1_PI_190_DATA
+				DDRSS1_PI_191_DATA
+				DDRSS1_PI_192_DATA
+				DDRSS1_PI_193_DATA
+				DDRSS1_PI_194_DATA
+				DDRSS1_PI_195_DATA
+				DDRSS1_PI_196_DATA
+				DDRSS1_PI_197_DATA
+				DDRSS1_PI_198_DATA
+				DDRSS1_PI_199_DATA
+				DDRSS1_PI_200_DATA
+				DDRSS1_PI_201_DATA
+				DDRSS1_PI_202_DATA
+				DDRSS1_PI_203_DATA
+				DDRSS1_PI_204_DATA
+				DDRSS1_PI_205_DATA
+				DDRSS1_PI_206_DATA
+				DDRSS1_PI_207_DATA
+				DDRSS1_PI_208_DATA
+				DDRSS1_PI_209_DATA
+				DDRSS1_PI_210_DATA
+				DDRSS1_PI_211_DATA
+				DDRSS1_PI_212_DATA
+				DDRSS1_PI_213_DATA
+				DDRSS1_PI_214_DATA
+				DDRSS1_PI_215_DATA
+				DDRSS1_PI_216_DATA
+				DDRSS1_PI_217_DATA
+				DDRSS1_PI_218_DATA
+				DDRSS1_PI_219_DATA
+				DDRSS1_PI_220_DATA
+				DDRSS1_PI_221_DATA
+				DDRSS1_PI_222_DATA
+				DDRSS1_PI_223_DATA
+				DDRSS1_PI_224_DATA
+				DDRSS1_PI_225_DATA
+				DDRSS1_PI_226_DATA
+				DDRSS1_PI_227_DATA
+				DDRSS1_PI_228_DATA
+				DDRSS1_PI_229_DATA
+				DDRSS1_PI_230_DATA
+				DDRSS1_PI_231_DATA
+				DDRSS1_PI_232_DATA
+				DDRSS1_PI_233_DATA
+				DDRSS1_PI_234_DATA
+				DDRSS1_PI_235_DATA
+				DDRSS1_PI_236_DATA
+				DDRSS1_PI_237_DATA
+				DDRSS1_PI_238_DATA
+				DDRSS1_PI_239_DATA
+				DDRSS1_PI_240_DATA
+				DDRSS1_PI_241_DATA
+				DDRSS1_PI_242_DATA
+				DDRSS1_PI_243_DATA
+				DDRSS1_PI_244_DATA
+				DDRSS1_PI_245_DATA
+				DDRSS1_PI_246_DATA
+				DDRSS1_PI_247_DATA
+				DDRSS1_PI_248_DATA
+				DDRSS1_PI_249_DATA
+				DDRSS1_PI_250_DATA
+				DDRSS1_PI_251_DATA
+				DDRSS1_PI_252_DATA
+				DDRSS1_PI_253_DATA
+				DDRSS1_PI_254_DATA
+				DDRSS1_PI_255_DATA
+				DDRSS1_PI_256_DATA
+				DDRSS1_PI_257_DATA
+				DDRSS1_PI_258_DATA
+				DDRSS1_PI_259_DATA
+				DDRSS1_PI_260_DATA
+				DDRSS1_PI_261_DATA
+				DDRSS1_PI_262_DATA
+				DDRSS1_PI_263_DATA
+				DDRSS1_PI_264_DATA
+				DDRSS1_PI_265_DATA
+				DDRSS1_PI_266_DATA
+				DDRSS1_PI_267_DATA
+				DDRSS1_PI_268_DATA
+				DDRSS1_PI_269_DATA
+				DDRSS1_PI_270_DATA
+				DDRSS1_PI_271_DATA
+				DDRSS1_PI_272_DATA
+				DDRSS1_PI_273_DATA
+				DDRSS1_PI_274_DATA
+				DDRSS1_PI_275_DATA
+				DDRSS1_PI_276_DATA
+				DDRSS1_PI_277_DATA
+				DDRSS1_PI_278_DATA
+				DDRSS1_PI_279_DATA
+				DDRSS1_PI_280_DATA
+				DDRSS1_PI_281_DATA
+				DDRSS1_PI_282_DATA
+				DDRSS1_PI_283_DATA
+				DDRSS1_PI_284_DATA
+				DDRSS1_PI_285_DATA
+				DDRSS1_PI_286_DATA
+				DDRSS1_PI_287_DATA
+				DDRSS1_PI_288_DATA
+				DDRSS1_PI_289_DATA
+				DDRSS1_PI_290_DATA
+				DDRSS1_PI_291_DATA
+				DDRSS1_PI_292_DATA
+				DDRSS1_PI_293_DATA
+				DDRSS1_PI_294_DATA
+				DDRSS1_PI_295_DATA
+				DDRSS1_PI_296_DATA
+				DDRSS1_PI_297_DATA
+				DDRSS1_PI_298_DATA
+				DDRSS1_PI_299_DATA
+			>;
+
+			ti,phy-data = <
+				DDRSS1_PHY_00_DATA
+				DDRSS1_PHY_01_DATA
+				DDRSS1_PHY_02_DATA
+				DDRSS1_PHY_03_DATA
+				DDRSS1_PHY_04_DATA
+				DDRSS1_PHY_05_DATA
+				DDRSS1_PHY_06_DATA
+				DDRSS1_PHY_07_DATA
+				DDRSS1_PHY_08_DATA
+				DDRSS1_PHY_09_DATA
+				DDRSS1_PHY_10_DATA
+				DDRSS1_PHY_11_DATA
+				DDRSS1_PHY_12_DATA
+				DDRSS1_PHY_13_DATA
+				DDRSS1_PHY_14_DATA
+				DDRSS1_PHY_15_DATA
+				DDRSS1_PHY_16_DATA
+				DDRSS1_PHY_17_DATA
+				DDRSS1_PHY_18_DATA
+				DDRSS1_PHY_19_DATA
+				DDRSS1_PHY_20_DATA
+				DDRSS1_PHY_21_DATA
+				DDRSS1_PHY_22_DATA
+				DDRSS1_PHY_23_DATA
+				DDRSS1_PHY_24_DATA
+				DDRSS1_PHY_25_DATA
+				DDRSS1_PHY_26_DATA
+				DDRSS1_PHY_27_DATA
+				DDRSS1_PHY_28_DATA
+				DDRSS1_PHY_29_DATA
+				DDRSS1_PHY_30_DATA
+				DDRSS1_PHY_31_DATA
+				DDRSS1_PHY_32_DATA
+				DDRSS1_PHY_33_DATA
+				DDRSS1_PHY_34_DATA
+				DDRSS1_PHY_35_DATA
+				DDRSS1_PHY_36_DATA
+				DDRSS1_PHY_37_DATA
+				DDRSS1_PHY_38_DATA
+				DDRSS1_PHY_39_DATA
+				DDRSS1_PHY_40_DATA
+				DDRSS1_PHY_41_DATA
+				DDRSS1_PHY_42_DATA
+				DDRSS1_PHY_43_DATA
+				DDRSS1_PHY_44_DATA
+				DDRSS1_PHY_45_DATA
+				DDRSS1_PHY_46_DATA
+				DDRSS1_PHY_47_DATA
+				DDRSS1_PHY_48_DATA
+				DDRSS1_PHY_49_DATA
+				DDRSS1_PHY_50_DATA
+				DDRSS1_PHY_51_DATA
+				DDRSS1_PHY_52_DATA
+				DDRSS1_PHY_53_DATA
+				DDRSS1_PHY_54_DATA
+				DDRSS1_PHY_55_DATA
+				DDRSS1_PHY_56_DATA
+				DDRSS1_PHY_57_DATA
+				DDRSS1_PHY_58_DATA
+				DDRSS1_PHY_59_DATA
+				DDRSS1_PHY_60_DATA
+				DDRSS1_PHY_61_DATA
+				DDRSS1_PHY_62_DATA
+				DDRSS1_PHY_63_DATA
+				DDRSS1_PHY_64_DATA
+				DDRSS1_PHY_65_DATA
+				DDRSS1_PHY_66_DATA
+				DDRSS1_PHY_67_DATA
+				DDRSS1_PHY_68_DATA
+				DDRSS1_PHY_69_DATA
+				DDRSS1_PHY_70_DATA
+				DDRSS1_PHY_71_DATA
+				DDRSS1_PHY_72_DATA
+				DDRSS1_PHY_73_DATA
+				DDRSS1_PHY_74_DATA
+				DDRSS1_PHY_75_DATA
+				DDRSS1_PHY_76_DATA
+				DDRSS1_PHY_77_DATA
+				DDRSS1_PHY_78_DATA
+				DDRSS1_PHY_79_DATA
+				DDRSS1_PHY_80_DATA
+				DDRSS1_PHY_81_DATA
+				DDRSS1_PHY_82_DATA
+				DDRSS1_PHY_83_DATA
+				DDRSS1_PHY_84_DATA
+				DDRSS1_PHY_85_DATA
+				DDRSS1_PHY_86_DATA
+				DDRSS1_PHY_87_DATA
+				DDRSS1_PHY_88_DATA
+				DDRSS1_PHY_89_DATA
+				DDRSS1_PHY_90_DATA
+				DDRSS1_PHY_91_DATA
+				DDRSS1_PHY_92_DATA
+				DDRSS1_PHY_93_DATA
+				DDRSS1_PHY_94_DATA
+				DDRSS1_PHY_95_DATA
+				DDRSS1_PHY_96_DATA
+				DDRSS1_PHY_97_DATA
+				DDRSS1_PHY_98_DATA
+				DDRSS1_PHY_99_DATA
+				DDRSS1_PHY_100_DATA
+				DDRSS1_PHY_101_DATA
+				DDRSS1_PHY_102_DATA
+				DDRSS1_PHY_103_DATA
+				DDRSS1_PHY_104_DATA
+				DDRSS1_PHY_105_DATA
+				DDRSS1_PHY_106_DATA
+				DDRSS1_PHY_107_DATA
+				DDRSS1_PHY_108_DATA
+				DDRSS1_PHY_109_DATA
+				DDRSS1_PHY_110_DATA
+				DDRSS1_PHY_111_DATA
+				DDRSS1_PHY_112_DATA
+				DDRSS1_PHY_113_DATA
+				DDRSS1_PHY_114_DATA
+				DDRSS1_PHY_115_DATA
+				DDRSS1_PHY_116_DATA
+				DDRSS1_PHY_117_DATA
+				DDRSS1_PHY_118_DATA
+				DDRSS1_PHY_119_DATA
+				DDRSS1_PHY_120_DATA
+				DDRSS1_PHY_121_DATA
+				DDRSS1_PHY_122_DATA
+				DDRSS1_PHY_123_DATA
+				DDRSS1_PHY_124_DATA
+				DDRSS1_PHY_125_DATA
+				DDRSS1_PHY_126_DATA
+				DDRSS1_PHY_127_DATA
+				DDRSS1_PHY_128_DATA
+				DDRSS1_PHY_129_DATA
+				DDRSS1_PHY_130_DATA
+				DDRSS1_PHY_131_DATA
+				DDRSS1_PHY_132_DATA
+				DDRSS1_PHY_133_DATA
+				DDRSS1_PHY_134_DATA
+				DDRSS1_PHY_135_DATA
+				DDRSS1_PHY_136_DATA
+				DDRSS1_PHY_137_DATA
+				DDRSS1_PHY_138_DATA
+				DDRSS1_PHY_139_DATA
+				DDRSS1_PHY_140_DATA
+				DDRSS1_PHY_141_DATA
+				DDRSS1_PHY_142_DATA
+				DDRSS1_PHY_143_DATA
+				DDRSS1_PHY_144_DATA
+				DDRSS1_PHY_145_DATA
+				DDRSS1_PHY_146_DATA
+				DDRSS1_PHY_147_DATA
+				DDRSS1_PHY_148_DATA
+				DDRSS1_PHY_149_DATA
+				DDRSS1_PHY_150_DATA
+				DDRSS1_PHY_151_DATA
+				DDRSS1_PHY_152_DATA
+				DDRSS1_PHY_153_DATA
+				DDRSS1_PHY_154_DATA
+				DDRSS1_PHY_155_DATA
+				DDRSS1_PHY_156_DATA
+				DDRSS1_PHY_157_DATA
+				DDRSS1_PHY_158_DATA
+				DDRSS1_PHY_159_DATA
+				DDRSS1_PHY_160_DATA
+				DDRSS1_PHY_161_DATA
+				DDRSS1_PHY_162_DATA
+				DDRSS1_PHY_163_DATA
+				DDRSS1_PHY_164_DATA
+				DDRSS1_PHY_165_DATA
+				DDRSS1_PHY_166_DATA
+				DDRSS1_PHY_167_DATA
+				DDRSS1_PHY_168_DATA
+				DDRSS1_PHY_169_DATA
+				DDRSS1_PHY_170_DATA
+				DDRSS1_PHY_171_DATA
+				DDRSS1_PHY_172_DATA
+				DDRSS1_PHY_173_DATA
+				DDRSS1_PHY_174_DATA
+				DDRSS1_PHY_175_DATA
+				DDRSS1_PHY_176_DATA
+				DDRSS1_PHY_177_DATA
+				DDRSS1_PHY_178_DATA
+				DDRSS1_PHY_179_DATA
+				DDRSS1_PHY_180_DATA
+				DDRSS1_PHY_181_DATA
+				DDRSS1_PHY_182_DATA
+				DDRSS1_PHY_183_DATA
+				DDRSS1_PHY_184_DATA
+				DDRSS1_PHY_185_DATA
+				DDRSS1_PHY_186_DATA
+				DDRSS1_PHY_187_DATA
+				DDRSS1_PHY_188_DATA
+				DDRSS1_PHY_189_DATA
+				DDRSS1_PHY_190_DATA
+				DDRSS1_PHY_191_DATA
+				DDRSS1_PHY_192_DATA
+				DDRSS1_PHY_193_DATA
+				DDRSS1_PHY_194_DATA
+				DDRSS1_PHY_195_DATA
+				DDRSS1_PHY_196_DATA
+				DDRSS1_PHY_197_DATA
+				DDRSS1_PHY_198_DATA
+				DDRSS1_PHY_199_DATA
+				DDRSS1_PHY_200_DATA
+				DDRSS1_PHY_201_DATA
+				DDRSS1_PHY_202_DATA
+				DDRSS1_PHY_203_DATA
+				DDRSS1_PHY_204_DATA
+				DDRSS1_PHY_205_DATA
+				DDRSS1_PHY_206_DATA
+				DDRSS1_PHY_207_DATA
+				DDRSS1_PHY_208_DATA
+				DDRSS1_PHY_209_DATA
+				DDRSS1_PHY_210_DATA
+				DDRSS1_PHY_211_DATA
+				DDRSS1_PHY_212_DATA
+				DDRSS1_PHY_213_DATA
+				DDRSS1_PHY_214_DATA
+				DDRSS1_PHY_215_DATA
+				DDRSS1_PHY_216_DATA
+				DDRSS1_PHY_217_DATA
+				DDRSS1_PHY_218_DATA
+				DDRSS1_PHY_219_DATA
+				DDRSS1_PHY_220_DATA
+				DDRSS1_PHY_221_DATA
+				DDRSS1_PHY_222_DATA
+				DDRSS1_PHY_223_DATA
+				DDRSS1_PHY_224_DATA
+				DDRSS1_PHY_225_DATA
+				DDRSS1_PHY_226_DATA
+				DDRSS1_PHY_227_DATA
+				DDRSS1_PHY_228_DATA
+				DDRSS1_PHY_229_DATA
+				DDRSS1_PHY_230_DATA
+				DDRSS1_PHY_231_DATA
+				DDRSS1_PHY_232_DATA
+				DDRSS1_PHY_233_DATA
+				DDRSS1_PHY_234_DATA
+				DDRSS1_PHY_235_DATA
+				DDRSS1_PHY_236_DATA
+				DDRSS1_PHY_237_DATA
+				DDRSS1_PHY_238_DATA
+				DDRSS1_PHY_239_DATA
+				DDRSS1_PHY_240_DATA
+				DDRSS1_PHY_241_DATA
+				DDRSS1_PHY_242_DATA
+				DDRSS1_PHY_243_DATA
+				DDRSS1_PHY_244_DATA
+				DDRSS1_PHY_245_DATA
+				DDRSS1_PHY_246_DATA
+				DDRSS1_PHY_247_DATA
+				DDRSS1_PHY_248_DATA
+				DDRSS1_PHY_249_DATA
+				DDRSS1_PHY_250_DATA
+				DDRSS1_PHY_251_DATA
+				DDRSS1_PHY_252_DATA
+				DDRSS1_PHY_253_DATA
+				DDRSS1_PHY_254_DATA
+				DDRSS1_PHY_255_DATA
+				DDRSS1_PHY_256_DATA
+				DDRSS1_PHY_257_DATA
+				DDRSS1_PHY_258_DATA
+				DDRSS1_PHY_259_DATA
+				DDRSS1_PHY_260_DATA
+				DDRSS1_PHY_261_DATA
+				DDRSS1_PHY_262_DATA
+				DDRSS1_PHY_263_DATA
+				DDRSS1_PHY_264_DATA
+				DDRSS1_PHY_265_DATA
+				DDRSS1_PHY_266_DATA
+				DDRSS1_PHY_267_DATA
+				DDRSS1_PHY_268_DATA
+				DDRSS1_PHY_269_DATA
+				DDRSS1_PHY_270_DATA
+				DDRSS1_PHY_271_DATA
+				DDRSS1_PHY_272_DATA
+				DDRSS1_PHY_273_DATA
+				DDRSS1_PHY_274_DATA
+				DDRSS1_PHY_275_DATA
+				DDRSS1_PHY_276_DATA
+				DDRSS1_PHY_277_DATA
+				DDRSS1_PHY_278_DATA
+				DDRSS1_PHY_279_DATA
+				DDRSS1_PHY_280_DATA
+				DDRSS1_PHY_281_DATA
+				DDRSS1_PHY_282_DATA
+				DDRSS1_PHY_283_DATA
+				DDRSS1_PHY_284_DATA
+				DDRSS1_PHY_285_DATA
+				DDRSS1_PHY_286_DATA
+				DDRSS1_PHY_287_DATA
+				DDRSS1_PHY_288_DATA
+				DDRSS1_PHY_289_DATA
+				DDRSS1_PHY_290_DATA
+				DDRSS1_PHY_291_DATA
+				DDRSS1_PHY_292_DATA
+				DDRSS1_PHY_293_DATA
+				DDRSS1_PHY_294_DATA
+				DDRSS1_PHY_295_DATA
+				DDRSS1_PHY_296_DATA
+				DDRSS1_PHY_297_DATA
+				DDRSS1_PHY_298_DATA
+				DDRSS1_PHY_299_DATA
+				DDRSS1_PHY_300_DATA
+				DDRSS1_PHY_301_DATA
+				DDRSS1_PHY_302_DATA
+				DDRSS1_PHY_303_DATA
+				DDRSS1_PHY_304_DATA
+				DDRSS1_PHY_305_DATA
+				DDRSS1_PHY_306_DATA
+				DDRSS1_PHY_307_DATA
+				DDRSS1_PHY_308_DATA
+				DDRSS1_PHY_309_DATA
+				DDRSS1_PHY_310_DATA
+				DDRSS1_PHY_311_DATA
+				DDRSS1_PHY_312_DATA
+				DDRSS1_PHY_313_DATA
+				DDRSS1_PHY_314_DATA
+				DDRSS1_PHY_315_DATA
+				DDRSS1_PHY_316_DATA
+				DDRSS1_PHY_317_DATA
+				DDRSS1_PHY_318_DATA
+				DDRSS1_PHY_319_DATA
+				DDRSS1_PHY_320_DATA
+				DDRSS1_PHY_321_DATA
+				DDRSS1_PHY_322_DATA
+				DDRSS1_PHY_323_DATA
+				DDRSS1_PHY_324_DATA
+				DDRSS1_PHY_325_DATA
+				DDRSS1_PHY_326_DATA
+				DDRSS1_PHY_327_DATA
+				DDRSS1_PHY_328_DATA
+				DDRSS1_PHY_329_DATA
+				DDRSS1_PHY_330_DATA
+				DDRSS1_PHY_331_DATA
+				DDRSS1_PHY_332_DATA
+				DDRSS1_PHY_333_DATA
+				DDRSS1_PHY_334_DATA
+				DDRSS1_PHY_335_DATA
+				DDRSS1_PHY_336_DATA
+				DDRSS1_PHY_337_DATA
+				DDRSS1_PHY_338_DATA
+				DDRSS1_PHY_339_DATA
+				DDRSS1_PHY_340_DATA
+				DDRSS1_PHY_341_DATA
+				DDRSS1_PHY_342_DATA
+				DDRSS1_PHY_343_DATA
+				DDRSS1_PHY_344_DATA
+				DDRSS1_PHY_345_DATA
+				DDRSS1_PHY_346_DATA
+				DDRSS1_PHY_347_DATA
+				DDRSS1_PHY_348_DATA
+				DDRSS1_PHY_349_DATA
+				DDRSS1_PHY_350_DATA
+				DDRSS1_PHY_351_DATA
+				DDRSS1_PHY_352_DATA
+				DDRSS1_PHY_353_DATA
+				DDRSS1_PHY_354_DATA
+				DDRSS1_PHY_355_DATA
+				DDRSS1_PHY_356_DATA
+				DDRSS1_PHY_357_DATA
+				DDRSS1_PHY_358_DATA
+				DDRSS1_PHY_359_DATA
+				DDRSS1_PHY_360_DATA
+				DDRSS1_PHY_361_DATA
+				DDRSS1_PHY_362_DATA
+				DDRSS1_PHY_363_DATA
+				DDRSS1_PHY_364_DATA
+				DDRSS1_PHY_365_DATA
+				DDRSS1_PHY_366_DATA
+				DDRSS1_PHY_367_DATA
+				DDRSS1_PHY_368_DATA
+				DDRSS1_PHY_369_DATA
+				DDRSS1_PHY_370_DATA
+				DDRSS1_PHY_371_DATA
+				DDRSS1_PHY_372_DATA
+				DDRSS1_PHY_373_DATA
+				DDRSS1_PHY_374_DATA
+				DDRSS1_PHY_375_DATA
+				DDRSS1_PHY_376_DATA
+				DDRSS1_PHY_377_DATA
+				DDRSS1_PHY_378_DATA
+				DDRSS1_PHY_379_DATA
+				DDRSS1_PHY_380_DATA
+				DDRSS1_PHY_381_DATA
+				DDRSS1_PHY_382_DATA
+				DDRSS1_PHY_383_DATA
+				DDRSS1_PHY_384_DATA
+				DDRSS1_PHY_385_DATA
+				DDRSS1_PHY_386_DATA
+				DDRSS1_PHY_387_DATA
+				DDRSS1_PHY_388_DATA
+				DDRSS1_PHY_389_DATA
+				DDRSS1_PHY_390_DATA
+				DDRSS1_PHY_391_DATA
+				DDRSS1_PHY_392_DATA
+				DDRSS1_PHY_393_DATA
+				DDRSS1_PHY_394_DATA
+				DDRSS1_PHY_395_DATA
+				DDRSS1_PHY_396_DATA
+				DDRSS1_PHY_397_DATA
+				DDRSS1_PHY_398_DATA
+				DDRSS1_PHY_399_DATA
+				DDRSS1_PHY_400_DATA
+				DDRSS1_PHY_401_DATA
+				DDRSS1_PHY_402_DATA
+				DDRSS1_PHY_403_DATA
+				DDRSS1_PHY_404_DATA
+				DDRSS1_PHY_405_DATA
+				DDRSS1_PHY_406_DATA
+				DDRSS1_PHY_407_DATA
+				DDRSS1_PHY_408_DATA
+				DDRSS1_PHY_409_DATA
+				DDRSS1_PHY_410_DATA
+				DDRSS1_PHY_411_DATA
+				DDRSS1_PHY_412_DATA
+				DDRSS1_PHY_413_DATA
+				DDRSS1_PHY_414_DATA
+				DDRSS1_PHY_415_DATA
+				DDRSS1_PHY_416_DATA
+				DDRSS1_PHY_417_DATA
+				DDRSS1_PHY_418_DATA
+				DDRSS1_PHY_419_DATA
+				DDRSS1_PHY_420_DATA
+				DDRSS1_PHY_421_DATA
+				DDRSS1_PHY_422_DATA
+				DDRSS1_PHY_423_DATA
+				DDRSS1_PHY_424_DATA
+				DDRSS1_PHY_425_DATA
+				DDRSS1_PHY_426_DATA
+				DDRSS1_PHY_427_DATA
+				DDRSS1_PHY_428_DATA
+				DDRSS1_PHY_429_DATA
+				DDRSS1_PHY_430_DATA
+				DDRSS1_PHY_431_DATA
+				DDRSS1_PHY_432_DATA
+				DDRSS1_PHY_433_DATA
+				DDRSS1_PHY_434_DATA
+				DDRSS1_PHY_435_DATA
+				DDRSS1_PHY_436_DATA
+				DDRSS1_PHY_437_DATA
+				DDRSS1_PHY_438_DATA
+				DDRSS1_PHY_439_DATA
+				DDRSS1_PHY_440_DATA
+				DDRSS1_PHY_441_DATA
+				DDRSS1_PHY_442_DATA
+				DDRSS1_PHY_443_DATA
+				DDRSS1_PHY_444_DATA
+				DDRSS1_PHY_445_DATA
+				DDRSS1_PHY_446_DATA
+				DDRSS1_PHY_447_DATA
+				DDRSS1_PHY_448_DATA
+				DDRSS1_PHY_449_DATA
+				DDRSS1_PHY_450_DATA
+				DDRSS1_PHY_451_DATA
+				DDRSS1_PHY_452_DATA
+				DDRSS1_PHY_453_DATA
+				DDRSS1_PHY_454_DATA
+				DDRSS1_PHY_455_DATA
+				DDRSS1_PHY_456_DATA
+				DDRSS1_PHY_457_DATA
+				DDRSS1_PHY_458_DATA
+				DDRSS1_PHY_459_DATA
+				DDRSS1_PHY_460_DATA
+				DDRSS1_PHY_461_DATA
+				DDRSS1_PHY_462_DATA
+				DDRSS1_PHY_463_DATA
+				DDRSS1_PHY_464_DATA
+				DDRSS1_PHY_465_DATA
+				DDRSS1_PHY_466_DATA
+				DDRSS1_PHY_467_DATA
+				DDRSS1_PHY_468_DATA
+				DDRSS1_PHY_469_DATA
+				DDRSS1_PHY_470_DATA
+				DDRSS1_PHY_471_DATA
+				DDRSS1_PHY_472_DATA
+				DDRSS1_PHY_473_DATA
+				DDRSS1_PHY_474_DATA
+				DDRSS1_PHY_475_DATA
+				DDRSS1_PHY_476_DATA
+				DDRSS1_PHY_477_DATA
+				DDRSS1_PHY_478_DATA
+				DDRSS1_PHY_479_DATA
+				DDRSS1_PHY_480_DATA
+				DDRSS1_PHY_481_DATA
+				DDRSS1_PHY_482_DATA
+				DDRSS1_PHY_483_DATA
+				DDRSS1_PHY_484_DATA
+				DDRSS1_PHY_485_DATA
+				DDRSS1_PHY_486_DATA
+				DDRSS1_PHY_487_DATA
+				DDRSS1_PHY_488_DATA
+				DDRSS1_PHY_489_DATA
+				DDRSS1_PHY_490_DATA
+				DDRSS1_PHY_491_DATA
+				DDRSS1_PHY_492_DATA
+				DDRSS1_PHY_493_DATA
+				DDRSS1_PHY_494_DATA
+				DDRSS1_PHY_495_DATA
+				DDRSS1_PHY_496_DATA
+				DDRSS1_PHY_497_DATA
+				DDRSS1_PHY_498_DATA
+				DDRSS1_PHY_499_DATA
+				DDRSS1_PHY_500_DATA
+				DDRSS1_PHY_501_DATA
+				DDRSS1_PHY_502_DATA
+				DDRSS1_PHY_503_DATA
+				DDRSS1_PHY_504_DATA
+				DDRSS1_PHY_505_DATA
+				DDRSS1_PHY_506_DATA
+				DDRSS1_PHY_507_DATA
+				DDRSS1_PHY_508_DATA
+				DDRSS1_PHY_509_DATA
+				DDRSS1_PHY_510_DATA
+				DDRSS1_PHY_511_DATA
+				DDRSS1_PHY_512_DATA
+				DDRSS1_PHY_513_DATA
+				DDRSS1_PHY_514_DATA
+				DDRSS1_PHY_515_DATA
+				DDRSS1_PHY_516_DATA
+				DDRSS1_PHY_517_DATA
+				DDRSS1_PHY_518_DATA
+				DDRSS1_PHY_519_DATA
+				DDRSS1_PHY_520_DATA
+				DDRSS1_PHY_521_DATA
+				DDRSS1_PHY_522_DATA
+				DDRSS1_PHY_523_DATA
+				DDRSS1_PHY_524_DATA
+				DDRSS1_PHY_525_DATA
+				DDRSS1_PHY_526_DATA
+				DDRSS1_PHY_527_DATA
+				DDRSS1_PHY_528_DATA
+				DDRSS1_PHY_529_DATA
+				DDRSS1_PHY_530_DATA
+				DDRSS1_PHY_531_DATA
+				DDRSS1_PHY_532_DATA
+				DDRSS1_PHY_533_DATA
+				DDRSS1_PHY_534_DATA
+				DDRSS1_PHY_535_DATA
+				DDRSS1_PHY_536_DATA
+				DDRSS1_PHY_537_DATA
+				DDRSS1_PHY_538_DATA
+				DDRSS1_PHY_539_DATA
+				DDRSS1_PHY_540_DATA
+				DDRSS1_PHY_541_DATA
+				DDRSS1_PHY_542_DATA
+				DDRSS1_PHY_543_DATA
+				DDRSS1_PHY_544_DATA
+				DDRSS1_PHY_545_DATA
+				DDRSS1_PHY_546_DATA
+				DDRSS1_PHY_547_DATA
+				DDRSS1_PHY_548_DATA
+				DDRSS1_PHY_549_DATA
+				DDRSS1_PHY_550_DATA
+				DDRSS1_PHY_551_DATA
+				DDRSS1_PHY_552_DATA
+				DDRSS1_PHY_553_DATA
+				DDRSS1_PHY_554_DATA
+				DDRSS1_PHY_555_DATA
+				DDRSS1_PHY_556_DATA
+				DDRSS1_PHY_557_DATA
+				DDRSS1_PHY_558_DATA
+				DDRSS1_PHY_559_DATA
+				DDRSS1_PHY_560_DATA
+				DDRSS1_PHY_561_DATA
+				DDRSS1_PHY_562_DATA
+				DDRSS1_PHY_563_DATA
+				DDRSS1_PHY_564_DATA
+				DDRSS1_PHY_565_DATA
+				DDRSS1_PHY_566_DATA
+				DDRSS1_PHY_567_DATA
+				DDRSS1_PHY_568_DATA
+				DDRSS1_PHY_569_DATA
+				DDRSS1_PHY_570_DATA
+				DDRSS1_PHY_571_DATA
+				DDRSS1_PHY_572_DATA
+				DDRSS1_PHY_573_DATA
+				DDRSS1_PHY_574_DATA
+				DDRSS1_PHY_575_DATA
+				DDRSS1_PHY_576_DATA
+				DDRSS1_PHY_577_DATA
+				DDRSS1_PHY_578_DATA
+				DDRSS1_PHY_579_DATA
+				DDRSS1_PHY_580_DATA
+				DDRSS1_PHY_581_DATA
+				DDRSS1_PHY_582_DATA
+				DDRSS1_PHY_583_DATA
+				DDRSS1_PHY_584_DATA
+				DDRSS1_PHY_585_DATA
+				DDRSS1_PHY_586_DATA
+				DDRSS1_PHY_587_DATA
+				DDRSS1_PHY_588_DATA
+				DDRSS1_PHY_589_DATA
+				DDRSS1_PHY_590_DATA
+				DDRSS1_PHY_591_DATA
+				DDRSS1_PHY_592_DATA
+				DDRSS1_PHY_593_DATA
+				DDRSS1_PHY_594_DATA
+				DDRSS1_PHY_595_DATA
+				DDRSS1_PHY_596_DATA
+				DDRSS1_PHY_597_DATA
+				DDRSS1_PHY_598_DATA
+				DDRSS1_PHY_599_DATA
+				DDRSS1_PHY_600_DATA
+				DDRSS1_PHY_601_DATA
+				DDRSS1_PHY_602_DATA
+				DDRSS1_PHY_603_DATA
+				DDRSS1_PHY_604_DATA
+				DDRSS1_PHY_605_DATA
+				DDRSS1_PHY_606_DATA
+				DDRSS1_PHY_607_DATA
+				DDRSS1_PHY_608_DATA
+				DDRSS1_PHY_609_DATA
+				DDRSS1_PHY_610_DATA
+				DDRSS1_PHY_611_DATA
+				DDRSS1_PHY_612_DATA
+				DDRSS1_PHY_613_DATA
+				DDRSS1_PHY_614_DATA
+				DDRSS1_PHY_615_DATA
+				DDRSS1_PHY_616_DATA
+				DDRSS1_PHY_617_DATA
+				DDRSS1_PHY_618_DATA
+				DDRSS1_PHY_619_DATA
+				DDRSS1_PHY_620_DATA
+				DDRSS1_PHY_621_DATA
+				DDRSS1_PHY_622_DATA
+				DDRSS1_PHY_623_DATA
+				DDRSS1_PHY_624_DATA
+				DDRSS1_PHY_625_DATA
+				DDRSS1_PHY_626_DATA
+				DDRSS1_PHY_627_DATA
+				DDRSS1_PHY_628_DATA
+				DDRSS1_PHY_629_DATA
+				DDRSS1_PHY_630_DATA
+				DDRSS1_PHY_631_DATA
+				DDRSS1_PHY_632_DATA
+				DDRSS1_PHY_633_DATA
+				DDRSS1_PHY_634_DATA
+				DDRSS1_PHY_635_DATA
+				DDRSS1_PHY_636_DATA
+				DDRSS1_PHY_637_DATA
+				DDRSS1_PHY_638_DATA
+				DDRSS1_PHY_639_DATA
+				DDRSS1_PHY_640_DATA
+				DDRSS1_PHY_641_DATA
+				DDRSS1_PHY_642_DATA
+				DDRSS1_PHY_643_DATA
+				DDRSS1_PHY_644_DATA
+				DDRSS1_PHY_645_DATA
+				DDRSS1_PHY_646_DATA
+				DDRSS1_PHY_647_DATA
+				DDRSS1_PHY_648_DATA
+				DDRSS1_PHY_649_DATA
+				DDRSS1_PHY_650_DATA
+				DDRSS1_PHY_651_DATA
+				DDRSS1_PHY_652_DATA
+				DDRSS1_PHY_653_DATA
+				DDRSS1_PHY_654_DATA
+				DDRSS1_PHY_655_DATA
+				DDRSS1_PHY_656_DATA
+				DDRSS1_PHY_657_DATA
+				DDRSS1_PHY_658_DATA
+				DDRSS1_PHY_659_DATA
+				DDRSS1_PHY_660_DATA
+				DDRSS1_PHY_661_DATA
+				DDRSS1_PHY_662_DATA
+				DDRSS1_PHY_663_DATA
+				DDRSS1_PHY_664_DATA
+				DDRSS1_PHY_665_DATA
+				DDRSS1_PHY_666_DATA
+				DDRSS1_PHY_667_DATA
+				DDRSS1_PHY_668_DATA
+				DDRSS1_PHY_669_DATA
+				DDRSS1_PHY_670_DATA
+				DDRSS1_PHY_671_DATA
+				DDRSS1_PHY_672_DATA
+				DDRSS1_PHY_673_DATA
+				DDRSS1_PHY_674_DATA
+				DDRSS1_PHY_675_DATA
+				DDRSS1_PHY_676_DATA
+				DDRSS1_PHY_677_DATA
+				DDRSS1_PHY_678_DATA
+				DDRSS1_PHY_679_DATA
+				DDRSS1_PHY_680_DATA
+				DDRSS1_PHY_681_DATA
+				DDRSS1_PHY_682_DATA
+				DDRSS1_PHY_683_DATA
+				DDRSS1_PHY_684_DATA
+				DDRSS1_PHY_685_DATA
+				DDRSS1_PHY_686_DATA
+				DDRSS1_PHY_687_DATA
+				DDRSS1_PHY_688_DATA
+				DDRSS1_PHY_689_DATA
+				DDRSS1_PHY_690_DATA
+				DDRSS1_PHY_691_DATA
+				DDRSS1_PHY_692_DATA
+				DDRSS1_PHY_693_DATA
+				DDRSS1_PHY_694_DATA
+				DDRSS1_PHY_695_DATA
+				DDRSS1_PHY_696_DATA
+				DDRSS1_PHY_697_DATA
+				DDRSS1_PHY_698_DATA
+				DDRSS1_PHY_699_DATA
+				DDRSS1_PHY_700_DATA
+				DDRSS1_PHY_701_DATA
+				DDRSS1_PHY_702_DATA
+				DDRSS1_PHY_703_DATA
+				DDRSS1_PHY_704_DATA
+				DDRSS1_PHY_705_DATA
+				DDRSS1_PHY_706_DATA
+				DDRSS1_PHY_707_DATA
+				DDRSS1_PHY_708_DATA
+				DDRSS1_PHY_709_DATA
+				DDRSS1_PHY_710_DATA
+				DDRSS1_PHY_711_DATA
+				DDRSS1_PHY_712_DATA
+				DDRSS1_PHY_713_DATA
+				DDRSS1_PHY_714_DATA
+				DDRSS1_PHY_715_DATA
+				DDRSS1_PHY_716_DATA
+				DDRSS1_PHY_717_DATA
+				DDRSS1_PHY_718_DATA
+				DDRSS1_PHY_719_DATA
+				DDRSS1_PHY_720_DATA
+				DDRSS1_PHY_721_DATA
+				DDRSS1_PHY_722_DATA
+				DDRSS1_PHY_723_DATA
+				DDRSS1_PHY_724_DATA
+				DDRSS1_PHY_725_DATA
+				DDRSS1_PHY_726_DATA
+				DDRSS1_PHY_727_DATA
+				DDRSS1_PHY_728_DATA
+				DDRSS1_PHY_729_DATA
+				DDRSS1_PHY_730_DATA
+				DDRSS1_PHY_731_DATA
+				DDRSS1_PHY_732_DATA
+				DDRSS1_PHY_733_DATA
+				DDRSS1_PHY_734_DATA
+				DDRSS1_PHY_735_DATA
+				DDRSS1_PHY_736_DATA
+				DDRSS1_PHY_737_DATA
+				DDRSS1_PHY_738_DATA
+				DDRSS1_PHY_739_DATA
+				DDRSS1_PHY_740_DATA
+				DDRSS1_PHY_741_DATA
+				DDRSS1_PHY_742_DATA
+				DDRSS1_PHY_743_DATA
+				DDRSS1_PHY_744_DATA
+				DDRSS1_PHY_745_DATA
+				DDRSS1_PHY_746_DATA
+				DDRSS1_PHY_747_DATA
+				DDRSS1_PHY_748_DATA
+				DDRSS1_PHY_749_DATA
+				DDRSS1_PHY_750_DATA
+				DDRSS1_PHY_751_DATA
+				DDRSS1_PHY_752_DATA
+				DDRSS1_PHY_753_DATA
+				DDRSS1_PHY_754_DATA
+				DDRSS1_PHY_755_DATA
+				DDRSS1_PHY_756_DATA
+				DDRSS1_PHY_757_DATA
+				DDRSS1_PHY_758_DATA
+				DDRSS1_PHY_759_DATA
+				DDRSS1_PHY_760_DATA
+				DDRSS1_PHY_761_DATA
+				DDRSS1_PHY_762_DATA
+				DDRSS1_PHY_763_DATA
+				DDRSS1_PHY_764_DATA
+				DDRSS1_PHY_765_DATA
+				DDRSS1_PHY_766_DATA
+				DDRSS1_PHY_767_DATA
+				DDRSS1_PHY_768_DATA
+				DDRSS1_PHY_769_DATA
+				DDRSS1_PHY_770_DATA
+				DDRSS1_PHY_771_DATA
+				DDRSS1_PHY_772_DATA
+				DDRSS1_PHY_773_DATA
+				DDRSS1_PHY_774_DATA
+				DDRSS1_PHY_775_DATA
+				DDRSS1_PHY_776_DATA
+				DDRSS1_PHY_777_DATA
+				DDRSS1_PHY_778_DATA
+				DDRSS1_PHY_779_DATA
+				DDRSS1_PHY_780_DATA
+				DDRSS1_PHY_781_DATA
+				DDRSS1_PHY_782_DATA
+				DDRSS1_PHY_783_DATA
+				DDRSS1_PHY_784_DATA
+				DDRSS1_PHY_785_DATA
+				DDRSS1_PHY_786_DATA
+				DDRSS1_PHY_787_DATA
+				DDRSS1_PHY_788_DATA
+				DDRSS1_PHY_789_DATA
+				DDRSS1_PHY_790_DATA
+				DDRSS1_PHY_791_DATA
+				DDRSS1_PHY_792_DATA
+				DDRSS1_PHY_793_DATA
+				DDRSS1_PHY_794_DATA
+				DDRSS1_PHY_795_DATA
+				DDRSS1_PHY_796_DATA
+				DDRSS1_PHY_797_DATA
+				DDRSS1_PHY_798_DATA
+				DDRSS1_PHY_799_DATA
+				DDRSS1_PHY_800_DATA
+				DDRSS1_PHY_801_DATA
+				DDRSS1_PHY_802_DATA
+				DDRSS1_PHY_803_DATA
+				DDRSS1_PHY_804_DATA
+				DDRSS1_PHY_805_DATA
+				DDRSS1_PHY_806_DATA
+				DDRSS1_PHY_807_DATA
+				DDRSS1_PHY_808_DATA
+				DDRSS1_PHY_809_DATA
+				DDRSS1_PHY_810_DATA
+				DDRSS1_PHY_811_DATA
+				DDRSS1_PHY_812_DATA
+				DDRSS1_PHY_813_DATA
+				DDRSS1_PHY_814_DATA
+				DDRSS1_PHY_815_DATA
+				DDRSS1_PHY_816_DATA
+				DDRSS1_PHY_817_DATA
+				DDRSS1_PHY_818_DATA
+				DDRSS1_PHY_819_DATA
+				DDRSS1_PHY_820_DATA
+				DDRSS1_PHY_821_DATA
+				DDRSS1_PHY_822_DATA
+				DDRSS1_PHY_823_DATA
+				DDRSS1_PHY_824_DATA
+				DDRSS1_PHY_825_DATA
+				DDRSS1_PHY_826_DATA
+				DDRSS1_PHY_827_DATA
+				DDRSS1_PHY_828_DATA
+				DDRSS1_PHY_829_DATA
+				DDRSS1_PHY_830_DATA
+				DDRSS1_PHY_831_DATA
+				DDRSS1_PHY_832_DATA
+				DDRSS1_PHY_833_DATA
+				DDRSS1_PHY_834_DATA
+				DDRSS1_PHY_835_DATA
+				DDRSS1_PHY_836_DATA
+				DDRSS1_PHY_837_DATA
+				DDRSS1_PHY_838_DATA
+				DDRSS1_PHY_839_DATA
+				DDRSS1_PHY_840_DATA
+				DDRSS1_PHY_841_DATA
+				DDRSS1_PHY_842_DATA
+				DDRSS1_PHY_843_DATA
+				DDRSS1_PHY_844_DATA
+				DDRSS1_PHY_845_DATA
+				DDRSS1_PHY_846_DATA
+				DDRSS1_PHY_847_DATA
+				DDRSS1_PHY_848_DATA
+				DDRSS1_PHY_849_DATA
+				DDRSS1_PHY_850_DATA
+				DDRSS1_PHY_851_DATA
+				DDRSS1_PHY_852_DATA
+				DDRSS1_PHY_853_DATA
+				DDRSS1_PHY_854_DATA
+				DDRSS1_PHY_855_DATA
+				DDRSS1_PHY_856_DATA
+				DDRSS1_PHY_857_DATA
+				DDRSS1_PHY_858_DATA
+				DDRSS1_PHY_859_DATA
+				DDRSS1_PHY_860_DATA
+				DDRSS1_PHY_861_DATA
+				DDRSS1_PHY_862_DATA
+				DDRSS1_PHY_863_DATA
+				DDRSS1_PHY_864_DATA
+				DDRSS1_PHY_865_DATA
+				DDRSS1_PHY_866_DATA
+				DDRSS1_PHY_867_DATA
+				DDRSS1_PHY_868_DATA
+				DDRSS1_PHY_869_DATA
+				DDRSS1_PHY_870_DATA
+				DDRSS1_PHY_871_DATA
+				DDRSS1_PHY_872_DATA
+				DDRSS1_PHY_873_DATA
+				DDRSS1_PHY_874_DATA
+				DDRSS1_PHY_875_DATA
+				DDRSS1_PHY_876_DATA
+				DDRSS1_PHY_877_DATA
+				DDRSS1_PHY_878_DATA
+				DDRSS1_PHY_879_DATA
+				DDRSS1_PHY_880_DATA
+				DDRSS1_PHY_881_DATA
+				DDRSS1_PHY_882_DATA
+				DDRSS1_PHY_883_DATA
+				DDRSS1_PHY_884_DATA
+				DDRSS1_PHY_885_DATA
+				DDRSS1_PHY_886_DATA
+				DDRSS1_PHY_887_DATA
+				DDRSS1_PHY_888_DATA
+				DDRSS1_PHY_889_DATA
+				DDRSS1_PHY_890_DATA
+				DDRSS1_PHY_891_DATA
+				DDRSS1_PHY_892_DATA
+				DDRSS1_PHY_893_DATA
+				DDRSS1_PHY_894_DATA
+				DDRSS1_PHY_895_DATA
+				DDRSS1_PHY_896_DATA
+				DDRSS1_PHY_897_DATA
+				DDRSS1_PHY_898_DATA
+				DDRSS1_PHY_899_DATA
+				DDRSS1_PHY_900_DATA
+				DDRSS1_PHY_901_DATA
+				DDRSS1_PHY_902_DATA
+				DDRSS1_PHY_903_DATA
+				DDRSS1_PHY_904_DATA
+				DDRSS1_PHY_905_DATA
+				DDRSS1_PHY_906_DATA
+				DDRSS1_PHY_907_DATA
+				DDRSS1_PHY_908_DATA
+				DDRSS1_PHY_909_DATA
+				DDRSS1_PHY_910_DATA
+				DDRSS1_PHY_911_DATA
+				DDRSS1_PHY_912_DATA
+				DDRSS1_PHY_913_DATA
+				DDRSS1_PHY_914_DATA
+				DDRSS1_PHY_915_DATA
+				DDRSS1_PHY_916_DATA
+				DDRSS1_PHY_917_DATA
+				DDRSS1_PHY_918_DATA
+				DDRSS1_PHY_919_DATA
+				DDRSS1_PHY_920_DATA
+				DDRSS1_PHY_921_DATA
+				DDRSS1_PHY_922_DATA
+				DDRSS1_PHY_923_DATA
+				DDRSS1_PHY_924_DATA
+				DDRSS1_PHY_925_DATA
+				DDRSS1_PHY_926_DATA
+				DDRSS1_PHY_927_DATA
+				DDRSS1_PHY_928_DATA
+				DDRSS1_PHY_929_DATA
+				DDRSS1_PHY_930_DATA
+				DDRSS1_PHY_931_DATA
+				DDRSS1_PHY_932_DATA
+				DDRSS1_PHY_933_DATA
+				DDRSS1_PHY_934_DATA
+				DDRSS1_PHY_935_DATA
+				DDRSS1_PHY_936_DATA
+				DDRSS1_PHY_937_DATA
+				DDRSS1_PHY_938_DATA
+				DDRSS1_PHY_939_DATA
+				DDRSS1_PHY_940_DATA
+				DDRSS1_PHY_941_DATA
+				DDRSS1_PHY_942_DATA
+				DDRSS1_PHY_943_DATA
+				DDRSS1_PHY_944_DATA
+				DDRSS1_PHY_945_DATA
+				DDRSS1_PHY_946_DATA
+				DDRSS1_PHY_947_DATA
+				DDRSS1_PHY_948_DATA
+				DDRSS1_PHY_949_DATA
+				DDRSS1_PHY_950_DATA
+				DDRSS1_PHY_951_DATA
+				DDRSS1_PHY_952_DATA
+				DDRSS1_PHY_953_DATA
+				DDRSS1_PHY_954_DATA
+				DDRSS1_PHY_955_DATA
+				DDRSS1_PHY_956_DATA
+				DDRSS1_PHY_957_DATA
+				DDRSS1_PHY_958_DATA
+				DDRSS1_PHY_959_DATA
+				DDRSS1_PHY_960_DATA
+				DDRSS1_PHY_961_DATA
+				DDRSS1_PHY_962_DATA
+				DDRSS1_PHY_963_DATA
+				DDRSS1_PHY_964_DATA
+				DDRSS1_PHY_965_DATA
+				DDRSS1_PHY_966_DATA
+				DDRSS1_PHY_967_DATA
+				DDRSS1_PHY_968_DATA
+				DDRSS1_PHY_969_DATA
+				DDRSS1_PHY_970_DATA
+				DDRSS1_PHY_971_DATA
+				DDRSS1_PHY_972_DATA
+				DDRSS1_PHY_973_DATA
+				DDRSS1_PHY_974_DATA
+				DDRSS1_PHY_975_DATA
+				DDRSS1_PHY_976_DATA
+				DDRSS1_PHY_977_DATA
+				DDRSS1_PHY_978_DATA
+				DDRSS1_PHY_979_DATA
+				DDRSS1_PHY_980_DATA
+				DDRSS1_PHY_981_DATA
+				DDRSS1_PHY_982_DATA
+				DDRSS1_PHY_983_DATA
+				DDRSS1_PHY_984_DATA
+				DDRSS1_PHY_985_DATA
+				DDRSS1_PHY_986_DATA
+				DDRSS1_PHY_987_DATA
+				DDRSS1_PHY_988_DATA
+				DDRSS1_PHY_989_DATA
+				DDRSS1_PHY_990_DATA
+				DDRSS1_PHY_991_DATA
+				DDRSS1_PHY_992_DATA
+				DDRSS1_PHY_993_DATA
+				DDRSS1_PHY_994_DATA
+				DDRSS1_PHY_995_DATA
+				DDRSS1_PHY_996_DATA
+				DDRSS1_PHY_997_DATA
+				DDRSS1_PHY_998_DATA
+				DDRSS1_PHY_999_DATA
+				DDRSS1_PHY_1000_DATA
+				DDRSS1_PHY_1001_DATA
+				DDRSS1_PHY_1002_DATA
+				DDRSS1_PHY_1003_DATA
+				DDRSS1_PHY_1004_DATA
+				DDRSS1_PHY_1005_DATA
+				DDRSS1_PHY_1006_DATA
+				DDRSS1_PHY_1007_DATA
+				DDRSS1_PHY_1008_DATA
+				DDRSS1_PHY_1009_DATA
+				DDRSS1_PHY_1010_DATA
+				DDRSS1_PHY_1011_DATA
+				DDRSS1_PHY_1012_DATA
+				DDRSS1_PHY_1013_DATA
+				DDRSS1_PHY_1014_DATA
+				DDRSS1_PHY_1015_DATA
+				DDRSS1_PHY_1016_DATA
+				DDRSS1_PHY_1017_DATA
+				DDRSS1_PHY_1018_DATA
+				DDRSS1_PHY_1019_DATA
+				DDRSS1_PHY_1020_DATA
+				DDRSS1_PHY_1021_DATA
+				DDRSS1_PHY_1022_DATA
+				DDRSS1_PHY_1023_DATA
+				DDRSS1_PHY_1024_DATA
+				DDRSS1_PHY_1025_DATA
+				DDRSS1_PHY_1026_DATA
+				DDRSS1_PHY_1027_DATA
+				DDRSS1_PHY_1028_DATA
+				DDRSS1_PHY_1029_DATA
+				DDRSS1_PHY_1030_DATA
+				DDRSS1_PHY_1031_DATA
+				DDRSS1_PHY_1032_DATA
+				DDRSS1_PHY_1033_DATA
+				DDRSS1_PHY_1034_DATA
+				DDRSS1_PHY_1035_DATA
+				DDRSS1_PHY_1036_DATA
+				DDRSS1_PHY_1037_DATA
+				DDRSS1_PHY_1038_DATA
+				DDRSS1_PHY_1039_DATA
+				DDRSS1_PHY_1040_DATA
+				DDRSS1_PHY_1041_DATA
+				DDRSS1_PHY_1042_DATA
+				DDRSS1_PHY_1043_DATA
+				DDRSS1_PHY_1044_DATA
+				DDRSS1_PHY_1045_DATA
+				DDRSS1_PHY_1046_DATA
+				DDRSS1_PHY_1047_DATA
+				DDRSS1_PHY_1048_DATA
+				DDRSS1_PHY_1049_DATA
+				DDRSS1_PHY_1050_DATA
+				DDRSS1_PHY_1051_DATA
+				DDRSS1_PHY_1052_DATA
+				DDRSS1_PHY_1053_DATA
+				DDRSS1_PHY_1054_DATA
+				DDRSS1_PHY_1055_DATA
+				DDRSS1_PHY_1056_DATA
+				DDRSS1_PHY_1057_DATA
+				DDRSS1_PHY_1058_DATA
+				DDRSS1_PHY_1059_DATA
+				DDRSS1_PHY_1060_DATA
+				DDRSS1_PHY_1061_DATA
+				DDRSS1_PHY_1062_DATA
+				DDRSS1_PHY_1063_DATA
+				DDRSS1_PHY_1064_DATA
+				DDRSS1_PHY_1065_DATA
+				DDRSS1_PHY_1066_DATA
+				DDRSS1_PHY_1067_DATA
+				DDRSS1_PHY_1068_DATA
+				DDRSS1_PHY_1069_DATA
+				DDRSS1_PHY_1070_DATA
+				DDRSS1_PHY_1071_DATA
+				DDRSS1_PHY_1072_DATA
+				DDRSS1_PHY_1073_DATA
+				DDRSS1_PHY_1074_DATA
+				DDRSS1_PHY_1075_DATA
+				DDRSS1_PHY_1076_DATA
+				DDRSS1_PHY_1077_DATA
+				DDRSS1_PHY_1078_DATA
+				DDRSS1_PHY_1079_DATA
+				DDRSS1_PHY_1080_DATA
+				DDRSS1_PHY_1081_DATA
+				DDRSS1_PHY_1082_DATA
+				DDRSS1_PHY_1083_DATA
+				DDRSS1_PHY_1084_DATA
+				DDRSS1_PHY_1085_DATA
+				DDRSS1_PHY_1086_DATA
+				DDRSS1_PHY_1087_DATA
+				DDRSS1_PHY_1088_DATA
+				DDRSS1_PHY_1089_DATA
+				DDRSS1_PHY_1090_DATA
+				DDRSS1_PHY_1091_DATA
+				DDRSS1_PHY_1092_DATA
+				DDRSS1_PHY_1093_DATA
+				DDRSS1_PHY_1094_DATA
+				DDRSS1_PHY_1095_DATA
+				DDRSS1_PHY_1096_DATA
+				DDRSS1_PHY_1097_DATA
+				DDRSS1_PHY_1098_DATA
+				DDRSS1_PHY_1099_DATA
+				DDRSS1_PHY_1100_DATA
+				DDRSS1_PHY_1101_DATA
+				DDRSS1_PHY_1102_DATA
+				DDRSS1_PHY_1103_DATA
+				DDRSS1_PHY_1104_DATA
+				DDRSS1_PHY_1105_DATA
+				DDRSS1_PHY_1106_DATA
+				DDRSS1_PHY_1107_DATA
+				DDRSS1_PHY_1108_DATA
+				DDRSS1_PHY_1109_DATA
+				DDRSS1_PHY_1110_DATA
+				DDRSS1_PHY_1111_DATA
+				DDRSS1_PHY_1112_DATA
+				DDRSS1_PHY_1113_DATA
+				DDRSS1_PHY_1114_DATA
+				DDRSS1_PHY_1115_DATA
+				DDRSS1_PHY_1116_DATA
+				DDRSS1_PHY_1117_DATA
+				DDRSS1_PHY_1118_DATA
+				DDRSS1_PHY_1119_DATA
+				DDRSS1_PHY_1120_DATA
+				DDRSS1_PHY_1121_DATA
+				DDRSS1_PHY_1122_DATA
+				DDRSS1_PHY_1123_DATA
+				DDRSS1_PHY_1124_DATA
+				DDRSS1_PHY_1125_DATA
+				DDRSS1_PHY_1126_DATA
+				DDRSS1_PHY_1127_DATA
+				DDRSS1_PHY_1128_DATA
+				DDRSS1_PHY_1129_DATA
+				DDRSS1_PHY_1130_DATA
+				DDRSS1_PHY_1131_DATA
+				DDRSS1_PHY_1132_DATA
+				DDRSS1_PHY_1133_DATA
+				DDRSS1_PHY_1134_DATA
+				DDRSS1_PHY_1135_DATA
+				DDRSS1_PHY_1136_DATA
+				DDRSS1_PHY_1137_DATA
+				DDRSS1_PHY_1138_DATA
+				DDRSS1_PHY_1139_DATA
+				DDRSS1_PHY_1140_DATA
+				DDRSS1_PHY_1141_DATA
+				DDRSS1_PHY_1142_DATA
+				DDRSS1_PHY_1143_DATA
+				DDRSS1_PHY_1144_DATA
+				DDRSS1_PHY_1145_DATA
+				DDRSS1_PHY_1146_DATA
+				DDRSS1_PHY_1147_DATA
+				DDRSS1_PHY_1148_DATA
+				DDRSS1_PHY_1149_DATA
+				DDRSS1_PHY_1150_DATA
+				DDRSS1_PHY_1151_DATA
+				DDRSS1_PHY_1152_DATA
+				DDRSS1_PHY_1153_DATA
+				DDRSS1_PHY_1154_DATA
+				DDRSS1_PHY_1155_DATA
+				DDRSS1_PHY_1156_DATA
+				DDRSS1_PHY_1157_DATA
+				DDRSS1_PHY_1158_DATA
+				DDRSS1_PHY_1159_DATA
+				DDRSS1_PHY_1160_DATA
+				DDRSS1_PHY_1161_DATA
+				DDRSS1_PHY_1162_DATA
+				DDRSS1_PHY_1163_DATA
+				DDRSS1_PHY_1164_DATA
+				DDRSS1_PHY_1165_DATA
+				DDRSS1_PHY_1166_DATA
+				DDRSS1_PHY_1167_DATA
+				DDRSS1_PHY_1168_DATA
+				DDRSS1_PHY_1169_DATA
+				DDRSS1_PHY_1170_DATA
+				DDRSS1_PHY_1171_DATA
+				DDRSS1_PHY_1172_DATA
+				DDRSS1_PHY_1173_DATA
+				DDRSS1_PHY_1174_DATA
+				DDRSS1_PHY_1175_DATA
+				DDRSS1_PHY_1176_DATA
+				DDRSS1_PHY_1177_DATA
+				DDRSS1_PHY_1178_DATA
+				DDRSS1_PHY_1179_DATA
+				DDRSS1_PHY_1180_DATA
+				DDRSS1_PHY_1181_DATA
+				DDRSS1_PHY_1182_DATA
+				DDRSS1_PHY_1183_DATA
+				DDRSS1_PHY_1184_DATA
+				DDRSS1_PHY_1185_DATA
+				DDRSS1_PHY_1186_DATA
+				DDRSS1_PHY_1187_DATA
+				DDRSS1_PHY_1188_DATA
+				DDRSS1_PHY_1189_DATA
+				DDRSS1_PHY_1190_DATA
+				DDRSS1_PHY_1191_DATA
+				DDRSS1_PHY_1192_DATA
+				DDRSS1_PHY_1193_DATA
+				DDRSS1_PHY_1194_DATA
+				DDRSS1_PHY_1195_DATA
+				DDRSS1_PHY_1196_DATA
+				DDRSS1_PHY_1197_DATA
+				DDRSS1_PHY_1198_DATA
+				DDRSS1_PHY_1199_DATA
+				DDRSS1_PHY_1200_DATA
+				DDRSS1_PHY_1201_DATA
+				DDRSS1_PHY_1202_DATA
+				DDRSS1_PHY_1203_DATA
+				DDRSS1_PHY_1204_DATA
+				DDRSS1_PHY_1205_DATA
+				DDRSS1_PHY_1206_DATA
+				DDRSS1_PHY_1207_DATA
+				DDRSS1_PHY_1208_DATA
+				DDRSS1_PHY_1209_DATA
+				DDRSS1_PHY_1210_DATA
+				DDRSS1_PHY_1211_DATA
+				DDRSS1_PHY_1212_DATA
+				DDRSS1_PHY_1213_DATA
+				DDRSS1_PHY_1214_DATA
+				DDRSS1_PHY_1215_DATA
+				DDRSS1_PHY_1216_DATA
+				DDRSS1_PHY_1217_DATA
+				DDRSS1_PHY_1218_DATA
+				DDRSS1_PHY_1219_DATA
+				DDRSS1_PHY_1220_DATA
+				DDRSS1_PHY_1221_DATA
+				DDRSS1_PHY_1222_DATA
+				DDRSS1_PHY_1223_DATA
+				DDRSS1_PHY_1224_DATA
+				DDRSS1_PHY_1225_DATA
+				DDRSS1_PHY_1226_DATA
+				DDRSS1_PHY_1227_DATA
+				DDRSS1_PHY_1228_DATA
+				DDRSS1_PHY_1229_DATA
+				DDRSS1_PHY_1230_DATA
+				DDRSS1_PHY_1231_DATA
+				DDRSS1_PHY_1232_DATA
+				DDRSS1_PHY_1233_DATA
+				DDRSS1_PHY_1234_DATA
+				DDRSS1_PHY_1235_DATA
+				DDRSS1_PHY_1236_DATA
+				DDRSS1_PHY_1237_DATA
+				DDRSS1_PHY_1238_DATA
+				DDRSS1_PHY_1239_DATA
+				DDRSS1_PHY_1240_DATA
+				DDRSS1_PHY_1241_DATA
+				DDRSS1_PHY_1242_DATA
+				DDRSS1_PHY_1243_DATA
+				DDRSS1_PHY_1244_DATA
+				DDRSS1_PHY_1245_DATA
+				DDRSS1_PHY_1246_DATA
+				DDRSS1_PHY_1247_DATA
+				DDRSS1_PHY_1248_DATA
+				DDRSS1_PHY_1249_DATA
+				DDRSS1_PHY_1250_DATA
+				DDRSS1_PHY_1251_DATA
+				DDRSS1_PHY_1252_DATA
+				DDRSS1_PHY_1253_DATA
+				DDRSS1_PHY_1254_DATA
+				DDRSS1_PHY_1255_DATA
+				DDRSS1_PHY_1256_DATA
+				DDRSS1_PHY_1257_DATA
+				DDRSS1_PHY_1258_DATA
+				DDRSS1_PHY_1259_DATA
+				DDRSS1_PHY_1260_DATA
+				DDRSS1_PHY_1261_DATA
+				DDRSS1_PHY_1262_DATA
+				DDRSS1_PHY_1263_DATA
+				DDRSS1_PHY_1264_DATA
+				DDRSS1_PHY_1265_DATA
+				DDRSS1_PHY_1266_DATA
+				DDRSS1_PHY_1267_DATA
+				DDRSS1_PHY_1268_DATA
+				DDRSS1_PHY_1269_DATA
+				DDRSS1_PHY_1270_DATA
+				DDRSS1_PHY_1271_DATA
+				DDRSS1_PHY_1272_DATA
+				DDRSS1_PHY_1273_DATA
+				DDRSS1_PHY_1274_DATA
+				DDRSS1_PHY_1275_DATA
+				DDRSS1_PHY_1276_DATA
+				DDRSS1_PHY_1277_DATA
+				DDRSS1_PHY_1278_DATA
+				DDRSS1_PHY_1279_DATA
+				DDRSS1_PHY_1280_DATA
+				DDRSS1_PHY_1281_DATA
+				DDRSS1_PHY_1282_DATA
+				DDRSS1_PHY_1283_DATA
+				DDRSS1_PHY_1284_DATA
+				DDRSS1_PHY_1285_DATA
+				DDRSS1_PHY_1286_DATA
+				DDRSS1_PHY_1287_DATA
+				DDRSS1_PHY_1288_DATA
+				DDRSS1_PHY_1289_DATA
+				DDRSS1_PHY_1290_DATA
+				DDRSS1_PHY_1291_DATA
+				DDRSS1_PHY_1292_DATA
+				DDRSS1_PHY_1293_DATA
+				DDRSS1_PHY_1294_DATA
+				DDRSS1_PHY_1295_DATA
+				DDRSS1_PHY_1296_DATA
+				DDRSS1_PHY_1297_DATA
+				DDRSS1_PHY_1298_DATA
+				DDRSS1_PHY_1299_DATA
+				DDRSS1_PHY_1300_DATA
+				DDRSS1_PHY_1301_DATA
+				DDRSS1_PHY_1302_DATA
+				DDRSS1_PHY_1303_DATA
+				DDRSS1_PHY_1304_DATA
+				DDRSS1_PHY_1305_DATA
+				DDRSS1_PHY_1306_DATA
+				DDRSS1_PHY_1307_DATA
+				DDRSS1_PHY_1308_DATA
+				DDRSS1_PHY_1309_DATA
+				DDRSS1_PHY_1310_DATA
+				DDRSS1_PHY_1311_DATA
+				DDRSS1_PHY_1312_DATA
+				DDRSS1_PHY_1313_DATA
+				DDRSS1_PHY_1314_DATA
+				DDRSS1_PHY_1315_DATA
+				DDRSS1_PHY_1316_DATA
+				DDRSS1_PHY_1317_DATA
+				DDRSS1_PHY_1318_DATA
+				DDRSS1_PHY_1319_DATA
+				DDRSS1_PHY_1320_DATA
+				DDRSS1_PHY_1321_DATA
+				DDRSS1_PHY_1322_DATA
+				DDRSS1_PHY_1323_DATA
+				DDRSS1_PHY_1324_DATA
+				DDRSS1_PHY_1325_DATA
+				DDRSS1_PHY_1326_DATA
+				DDRSS1_PHY_1327_DATA
+				DDRSS1_PHY_1328_DATA
+				DDRSS1_PHY_1329_DATA
+				DDRSS1_PHY_1330_DATA
+				DDRSS1_PHY_1331_DATA
+				DDRSS1_PHY_1332_DATA
+				DDRSS1_PHY_1333_DATA
+				DDRSS1_PHY_1334_DATA
+				DDRSS1_PHY_1335_DATA
+				DDRSS1_PHY_1336_DATA
+				DDRSS1_PHY_1337_DATA
+				DDRSS1_PHY_1338_DATA
+				DDRSS1_PHY_1339_DATA
+				DDRSS1_PHY_1340_DATA
+				DDRSS1_PHY_1341_DATA
+				DDRSS1_PHY_1342_DATA
+				DDRSS1_PHY_1343_DATA
+				DDRSS1_PHY_1344_DATA
+				DDRSS1_PHY_1345_DATA
+				DDRSS1_PHY_1346_DATA
+				DDRSS1_PHY_1347_DATA
+				DDRSS1_PHY_1348_DATA
+				DDRSS1_PHY_1349_DATA
+				DDRSS1_PHY_1350_DATA
+				DDRSS1_PHY_1351_DATA
+				DDRSS1_PHY_1352_DATA
+				DDRSS1_PHY_1353_DATA
+				DDRSS1_PHY_1354_DATA
+				DDRSS1_PHY_1355_DATA
+				DDRSS1_PHY_1356_DATA
+				DDRSS1_PHY_1357_DATA
+				DDRSS1_PHY_1358_DATA
+				DDRSS1_PHY_1359_DATA
+				DDRSS1_PHY_1360_DATA
+				DDRSS1_PHY_1361_DATA
+				DDRSS1_PHY_1362_DATA
+				DDRSS1_PHY_1363_DATA
+				DDRSS1_PHY_1364_DATA
+				DDRSS1_PHY_1365_DATA
+				DDRSS1_PHY_1366_DATA
+				DDRSS1_PHY_1367_DATA
+				DDRSS1_PHY_1368_DATA
+				DDRSS1_PHY_1369_DATA
+				DDRSS1_PHY_1370_DATA
+				DDRSS1_PHY_1371_DATA
+				DDRSS1_PHY_1372_DATA
+				DDRSS1_PHY_1373_DATA
+				DDRSS1_PHY_1374_DATA
+				DDRSS1_PHY_1375_DATA
+				DDRSS1_PHY_1376_DATA
+				DDRSS1_PHY_1377_DATA
+				DDRSS1_PHY_1378_DATA
+				DDRSS1_PHY_1379_DATA
+				DDRSS1_PHY_1380_DATA
+				DDRSS1_PHY_1381_DATA
+				DDRSS1_PHY_1382_DATA
+				DDRSS1_PHY_1383_DATA
+				DDRSS1_PHY_1384_DATA
+				DDRSS1_PHY_1385_DATA
+				DDRSS1_PHY_1386_DATA
+				DDRSS1_PHY_1387_DATA
+				DDRSS1_PHY_1388_DATA
+				DDRSS1_PHY_1389_DATA
+				DDRSS1_PHY_1390_DATA
+				DDRSS1_PHY_1391_DATA
+				DDRSS1_PHY_1392_DATA
+				DDRSS1_PHY_1393_DATA
+				DDRSS1_PHY_1394_DATA
+				DDRSS1_PHY_1395_DATA
+				DDRSS1_PHY_1396_DATA
+				DDRSS1_PHY_1397_DATA
+				DDRSS1_PHY_1398_DATA
+				DDRSS1_PHY_1399_DATA
+				DDRSS1_PHY_1400_DATA
+				DDRSS1_PHY_1401_DATA
+				DDRSS1_PHY_1402_DATA
+				DDRSS1_PHY_1403_DATA
+				DDRSS1_PHY_1404_DATA
+				DDRSS1_PHY_1405_DATA
+				DDRSS1_PHY_1406_DATA
+				DDRSS1_PHY_1407_DATA
+				DDRSS1_PHY_1408_DATA
+				DDRSS1_PHY_1409_DATA
+				DDRSS1_PHY_1410_DATA
+				DDRSS1_PHY_1411_DATA
+				DDRSS1_PHY_1412_DATA
+				DDRSS1_PHY_1413_DATA
+				DDRSS1_PHY_1414_DATA
+				DDRSS1_PHY_1415_DATA
+				DDRSS1_PHY_1416_DATA
+				DDRSS1_PHY_1417_DATA
+				DDRSS1_PHY_1418_DATA
+				DDRSS1_PHY_1419_DATA
+				DDRSS1_PHY_1420_DATA
+				DDRSS1_PHY_1421_DATA
+				DDRSS1_PHY_1422_DATA
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi
index b5e643feffe..dfde21235b1 100644
--- a/arch/arm/dts/mt7987-pinctrl.dtsi
+++ b/arch/arm/dts/mt7987-pinctrl.dtsi
@@ -191,6 +191,20 @@
 		};
 	};
 
+	pwm_pins: pwm-pins {
+		mux {
+			/*
+			 * - pwm0   : PWM0@PIN13
+			 * - pwm1_0 : PWM1@PIN7  (share with JTAG)
+			 *   pwm1_1 : PWM1@PIN43 (share with i2c0)
+			 * - pwm2_0 : PWM2@PIN12 (share with PCM)
+			 *   pwm2_1 : PWM2@PIN44 (share with i2c0)
+			 */
+			function = "pwm";
+			groups = "pwm0";
+		};
+	};
+
 	uart1_pins: uart1-pins {
 		mux {
 			function = "uart";
diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi
index fd1585f658d..4c1d597499c 100644
--- a/arch/arm/dts/mt7987.dtsi
+++ b/arch/arm/dts/mt7987.dtsi
@@ -389,21 +389,15 @@
 		};
 
 		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
+			compatible = "mediatek,mt7987-pwm";
 			reg = <0 0x10048000 0 0x1000>;
 			#pwm-cells = <2>;
 			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
 				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>;
+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/dts/mt7987a-u-boot.dtsi b/arch/arm/dts/mt7987a-u-boot.dtsi
index ec0a6389d8b..a1cb42a9675 100644
--- a/arch/arm/dts/mt7987a-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-u-boot.dtsi
@@ -24,6 +24,10 @@
 			mediatek,hwver = <&hwver>;
 		};
 	};
+
+	reserved-memory {
+		/delete-node/ wmcpu-reserved@50000000;
+	};
 };
 
 &i2c0 {
diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi
index 028f563fb39..365fefdbe17 100644
--- a/arch/arm/dts/mt7987a.dtsi
+++ b/arch/arm/dts/mt7987a.dtsi
@@ -29,7 +29,7 @@
 
 &fan {
 	pwms = <&pwm 0 50000 0>;
-	status = "okay";
+	status = "disabled";
 };
 
 &i2c0 {
@@ -59,6 +59,8 @@
 };
 
 &pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 10051c9dbfe..cc9d99b0f34 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -147,6 +147,10 @@
 	bootph-all;
 };
 
+&otp {
+	bootph-all;
+};
+
 &pfc {
 	bootph-all;
 };
diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts
index 6cb1781566f..64386f2b7b7 100644
--- a/arch/arm/dts/tegra124-xiaomi-mocha.dts
+++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts
@@ -215,8 +215,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,open-drain = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -225,8 +225,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,open-drain = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -235,8 +235,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,open-drain = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -253,7 +253,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,open-drain = <1>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 			};
 
 			dsi-b {
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
index 243ff2bda26..58f1499cb92 100644
--- a/arch/arm/dts/tegra30-asus-p1801-t.dts
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -34,20 +34,10 @@
 
 	host1x@50000000 {
 		dc@54200000 {
-			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
-			rgb {
-				status = "okay";
-
-				nvidia,panel = <&hdmi>;
-			};
+			status = "disabled";
 		};
 
 		hdmi: hdmi@54280000 {
-			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
 			status = "okay";
 
 			hdmi-supply = <&hdmi_5v0_sys>;
@@ -118,8 +108,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -203,7 +193,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2_i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -213,7 +203,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam_i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -223,7 +213,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc_i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -232,7 +222,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr_i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -242,7 +232,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hotplug_i2c {
 				nvidia,pins = "pu4";
@@ -260,7 +250,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hdmi_hpd {
 				nvidia,pins = "hdmi_int_pn7";
@@ -632,8 +622,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -718,8 +708,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_d10_pt2 {
 				nvidia,pins = "vi_d10_pt2",
@@ -838,8 +828,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_mclk_pt1 {
 				nvidia,pins = "vi_mclk_pt1";
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
index 3ddd78b3df6..1b5729c65f4 100644
--- a/arch/arm/dts/tegra30-asus-tf600t.dts
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -90,8 +90,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC2 pinmux */
@@ -107,8 +107,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -142,8 +142,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4_cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -159,8 +159,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4_rst_n {
 				nvidia,pins = "sdmmc4_rst_n_pcc3";
@@ -186,7 +186,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2_i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -196,7 +196,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam_i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -206,7 +206,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc_i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -215,7 +215,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr_i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -225,7 +225,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hotplug_i2c {
 				nvidia,pins = "pu4";
@@ -243,7 +243,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hdmi_hpd {
 				nvidia,pins = "hdmi_int_pn7";
@@ -613,8 +613,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -701,8 +701,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			pbb0 {
 				nvidia,pins = "pbb0";
@@ -827,8 +827,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_mclk_pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -836,8 +836,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			jtag {
diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts
index 6dc760b90d6..47606ede9d6 100644
--- a/arch/arm/dts/tegra30-asus-tf700t.dts
+++ b/arch/arm/dts/tegra30-asus-tf700t.dts
@@ -15,7 +15,14 @@
 			rgb {
 				status = "okay";
 
-				nvidia,panel = <&tc358768>;
+				/delete-property/ nvidia,panel;
+
+				port {
+					dpi_output: endpoint {
+						remote-endpoint = <&bridge_input>;
+						bus-width = <24>;
+					};
+				};
 			};
 		};
 	};
@@ -118,38 +125,69 @@
 				vddio-supply = <&vdd_1v8_vio>;
 				vddmipi-supply = <&vdd_1v2_mipi>;
 
-				panel = <&panel>;
+				/*
+				 * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
+				 * LCD SuperIPS+ Full HD panel.
+				 */
+				panel@1 {
+					compatible = "panasonic,vvx10f004b00";
+					reg = <1>;
+
+					power-supply = <&vdd_pnl_reg>;
+					backlight = <&backlight>;
+
+					display-timings {
+						timing@0 {
+							/* 1920x1200@60Hz */
+							clock-frequency = <154000000>;
+
+							hactive = <1920>;
+							hfront-porch = <48>;
+							hback-porch = <80>;
+							hsync-len = <32>;
+							hsync-active = <1>;
+
+							vactive = <1200>;
+							vfront-porch = <3>;
+							vback-porch = <26>;
+							vsync-len = <6>;
+							vsync-active = <1>;
+						};
+					};
+
+					port {
+						panel_input: endpoint {
+							remote-endpoint = <&bridge_output>;
+						};
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						bridge_input: endpoint {
+							remote-endpoint = <&dpi_output>;
+							bus-width = <24>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						bridge_output: endpoint {
+							remote-endpoint = <&panel_input>;
+						};
+					};
+				};
 			};
 		};
 	};
 
-	panel: panel {
-		compatible = "panasonic,vvx10f004b00";
-
-		power-supply = <&vdd_pnl_reg>;
-		backlight = <&backlight>;
-
-		/delete-property/ enable-gpios;
-
-		display-timings {
-			timing@0 {
-				/* 1920x1200@60Hz */
-				clock-frequency = <154000000>;
-
-				hactive = <1920>;
-				hfront-porch = <48>;
-				hback-porch = <80>;
-				hsync-len = <32>;
-				hsync-active = <1>;
-
-				vactive = <1200>;
-				vfront-porch = <3>;
-				vback-porch = <26>;
-				vsync-len = <6>;
-				vsync-active = <1>;
-			};
-		};
-	};
+	/delete-node/ panel;
 
 	vdd_1v2_mipi: regulator-mipi {
 		compatible = "regulator-fixed";
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
index 03ba8fb9604..032fb3d00ac 100644
--- a/arch/arm/dts/tegra30-asus-transformer.dtsi
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -99,8 +99,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -189,7 +189,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			gen2_i2c {
@@ -200,7 +200,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			cam_i2c {
@@ -211,7 +211,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			ddc_i2c {
@@ -221,7 +221,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			pwr_i2c {
@@ -232,7 +232,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			hotplug_i2c {
@@ -647,8 +647,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -741,8 +741,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			vi_d10_pt2 {
@@ -879,8 +879,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			vi_mclk_pt1 {
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
index 8a0ba3c07cc..db8ac457880 100644
--- a/arch/arm/dts/tegra30-htc-endeavoru.dts
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -33,13 +33,11 @@
 
 	host1x@50000000 {
 		dc@54200000 {
-			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+			backlight: backlight {
+				compatible = "nvidia,tegra-pwm-backlight";
 
-			rgb {
-				status = "okay";
-
-				nvidia,panel = <&dsia>;
+				nvidia,pwm-source = <1>;
+				nvidia,default-brightness = <0x8E>;
 			};
 		};
 
@@ -1265,13 +1263,6 @@
 		nvidia,xcvr-lsrslew = <2>;
 	};
 
-	backlight: backlight {
-		compatible = "nvidia,tegra-pwm-backlight";
-
-		nvidia,pwm-source = <1>;
-		nvidia,default-brightness = <0x8E>;
-	};
-
 	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
 	clk32k_in: clock-32k {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
index 9a1e8c0601e..876fac7b661 100644
--- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
+++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
@@ -109,8 +109,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4-cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -127,8 +127,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			cam-mclk {
 				nvidia,pins = "cam_mclk_pcc0";
@@ -147,7 +147,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -157,7 +157,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -167,7 +167,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -176,7 +176,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -186,7 +186,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
@@ -724,8 +724,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-vsync-pd6 {
 				nvidia,pins = "vi_vsync_pd6",
@@ -736,8 +736,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <2>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_ENABLE>;
 			};
 			vi-hsync-pd7 {
 				nvidia,pins = "vi_hsync_pd7",
@@ -749,8 +749,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d2-pl0 {
 				nvidia,pins = "vi_d2_pl0",
@@ -760,8 +760,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-mclk-pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -769,8 +769,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <2>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_ENABLE>;
 			};
 			vi-d11-pt3 {
 				nvidia,pins = "vi_d11_pt3";
@@ -778,8 +778,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d5-pl3 {
 				nvidia,pins = "vi_d5_pl3";
@@ -787,8 +787,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* PORT U */
diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts
index 1d5ca1459bc..ab5993150b2 100644
--- a/arch/arm/dts/tegra30-lg-p880.dts
+++ b/arch/arm/dts/tegra30-lg-p880.dts
@@ -101,6 +101,31 @@
 		};
 	};
 
+	spi@7000dc00 {
+		bridge-spi@2 {
+			/*
+			 * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
+			 */
+			panel@0 {
+				compatible = "jdi,dx12d100vm0eaa";
+				reg = <0>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				vdd-supply = <&vcc_3v0_lcd>;
+				vddio-supply = <&iovcc_1v8_lcd>;
+
+				backlight = <&backlight>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
+		};
+	};
+
 	sdmmc3: sdhci@78000400  {
 		status = "okay";
 		bus-width = <4>;
@@ -118,13 +143,4 @@
 			linux,code = <KEY_UP>;
 		};
 	};
-
-	panel: panel {
-		compatible = "jdi,dx12d100vm0eaa";
-
-		enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
-
-		backlight = <&backlight>;
-	};
 };
diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts
index 43bb373a164..988e772172c 100644
--- a/arch/arm/dts/tegra30-lg-p895.dts
+++ b/arch/arm/dts/tegra30-lg-p895.dts
@@ -108,36 +108,37 @@
 		};
 	};
 
-	panel: panel {
-		compatible = "hitachi,tx13d100vm0eaa";
-
-		reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
-
-		renesas,gamma = <3>;
-		renesas,inversion;
-		renesas,contrast;
-
-		vcc-supply = <&vcc_3v0_lcd>;
-		iovcc-supply = <&iovcc_1v8_lcd>;
-
-		backlight = <&backlight>;
+	spi@7000dc00 {
+		bridge-spi@2 {
+			/*
+			 * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
+			 */
+			panel@0 {
+				compatible = "koe,tx13d100vm0eaa";
+				reg = <0>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				renesas,gamma = <3>;
+				renesas,inversion;
+				renesas,contrast;
+
+				vcc-supply = <&vcc_3v0_lcd>;
+				iovcc-supply = <&iovcc_1v8_lcd>;
+
+				backlight = <&backlight>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
+		};
 	};
 
-	vcc_3v0_lcd: regulator-lcd {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v0_lcd";
-		regulator-min-microvolt = <3000000>;
-		regulator-max-microvolt = <3000000>;
+	regulator-lcd3v {
 		gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
-
-	iovcc_1v8_lcd: regulator-lcdvio {
-		compatible = "regulator-fixed";
-		regulator-name = "iovcc_1v8_lcd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
 };
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
index 30d6dcb6548..40b0ee07787 100644
--- a/arch/arm/dts/tegra30-lg-x3.dtsi
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -32,7 +32,12 @@
 			rgb {
 				status = "okay";
 
-				nvidia,panel = <&bridge>;
+				port {
+					dpi_output: endpoint {
+						remote-endpoint = <&bridge_input>;
+						bus-width = <24>;
+					};
+				};
 			};
 		};
 	};
@@ -890,12 +895,22 @@
 		status = "okay";
 		clock-frequency = <400000>;
 
-		backlight: lm3533@36 {
+		backlight: led-controller@36 {
 			compatible = "ti,lm3533";
 			reg = <0x36>;
 
 			enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
-			default-brightness-level = <128>;
+
+			ti,boost-ovp-microvolt = <24000000>;
+			ti,boost-freq-hz = <500000>;
+
+			backlight-0 {
+				compatible = "ti,lm3533-backlight";
+
+				ti,max-current-microamp = <23400>;
+				ti,linear-mapping-mode;
+				ti,hardware-controlled;
+			};
 		};
 
 		muic@44 {
@@ -969,18 +984,46 @@
 			compatible = "solomon,ssd2825";
 			reg = <2>;
 
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			spi-cpol;
 			spi-cpha;
 
 			spi-max-frequency = <1000000>;
 
-			power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
-			reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
+			reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
+
+			dvdd-supply = <&vdd_1v2_rgb>;
+			avdd-supply = <&vdd_1v2_rgb>;
+			vddio-supply = <&vdd_1v8_vio>;
+
+			solomon,hs-zero-delay-ns = <300>;
+			solomon,hs-prep-delay-ns = <65>;
 
 			clocks = <&ssd2825_refclk>;
-			clock-names = "tx_clk";
 
-			panel = <&panel>;
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					bridge_input: endpoint {
+						remote-endpoint = <&dpi_output>;
+						bus-width = <24>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					bridge_output: endpoint {
+						remote-endpoint = <&panel_input>;
+					};
+				};
+			};
 		};
 	};
 
@@ -1036,4 +1079,29 @@
 			linux,code = <KEY_DOWN>;
 		};
 	};
+
+	vdd_1v2_rgb: regulator-rgb1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_1v2_rgb";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vcc_3v0_lcd: regulator-lcd3v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v0_lcd";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+	};
+
+	iovcc_1v8_lcd: regulator-lcd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "iovcc_1v8_lcd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
index 6810350a90b..2d22d3e0bb1 100644
--- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts
+++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
@@ -103,8 +103,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4-cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -121,8 +121,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			cam-mclk {
 				nvidia,pins = "cam_mclk_pcc0";
@@ -141,7 +141,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -151,7 +151,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -161,7 +161,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -170,7 +170,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -180,7 +180,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
@@ -703,8 +703,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d3-pl1 {
 				nvidia,pins = "vi_d3_pl1";
@@ -712,8 +712,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-hsync-pd7 {
 				nvidia,pins = "vi_hsync_pd7",
@@ -724,8 +724,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-mclk-pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -733,8 +733,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d11-pt3 {
 				nvidia,pins = "vi_d11_pt3";
@@ -742,8 +742,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* PORT U */
diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts
new file mode 100644
index 00000000000..04453eb2432
--- /dev/null
+++ b/arch/arm/dts/tegra30-ouya.dts
@@ -0,0 +1,2063 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/ {
+	model = "Ouya Game Console";
+	compatible = "ouya,ouya", "nvidia,tegra30";
+
+	chosen {
+		stdout-path = &uartd;
+	};
+
+	aliases {
+		i2c0 = &pwr_i2c;
+		i2c1 = &hdmi_ddc;
+
+		mmc0 = &sdmmc4;
+
+		rtc0 = &pmic;
+		rtc1 = "/rtc@7000e000";
+
+		usb0 = &micro_usb;
+		usb1 = &ethernet_usb;
+		usb2 = &fullsize_usb;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	host1x@50000000 {
+		dc@54200000 {
+			status = "disabled";
+		};
+
+		hdmi: hdmi@54280000 {
+			status = "okay";
+
+			hdmi-supply = <&sys_3v3_reg>;
+			pll-supply = <&ldo7_reg>;
+			vdd-supply = <&vdd_vid_reg>;
+
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+		};
+	};
+
+	gpio@6000d000 {
+		fan-en-hog {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
+	};
+
+	pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			clk_32k_out_pa0 {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "blink";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart3_cts_n_pa1 {
+				nvidia,pins = "uart3_cts_n_pa1";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_fs_pa2 {
+				nvidia,pins = "dap2_fs_pa2";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_sclk_pa3 {
+				nvidia,pins = "dap2_sclk_pa3";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_a17_pb0 {
+				nvidia,pins = "gmi_a17_pb0";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_a18_pb1 {
+				nvidia,pins = "gmi_a18_pb1";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr0_pb2 {
+				nvidia,pins = "lcd_pwr0_pb2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pclk_pb3 {
+				nvidia,pins = "lcd_pclk_pb3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat3_pb4 {
+				nvidia,pins = "sdmmc3_dat3_pb4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat2_pb5 {
+				nvidia,pins = "sdmmc3_dat2_pb5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat1_pb6 {
+				nvidia,pins = "sdmmc3_dat1_pb6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat0_pb7 {
+				nvidia,pins = "sdmmc3_dat0_pb7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			uart3_rts_n_pc0 {
+				nvidia,pins = "uart3_rts_n_pc0";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr1_pc1 {
+				nvidia,pins = "lcd_pwr1_pc1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_txd_pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rxd_pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen1_i2c_scl_pc4 {
+				nvidia,pins = "gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen1_i2c_sda_pc5 {
+				nvidia,pins = "gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr2_pc6 {
+				nvidia,pins = "lcd_pwr2_pc6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wp_n_pc7 {
+				nvidia,pins = "gmi_wp_n_pc7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat5_pd0 {
+				nvidia,pins = "sdmmc3_dat5_pd0";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat4_pd1 {
+				nvidia,pins = "sdmmc3_dat4_pd1";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_dc1_pd2 {
+				nvidia,pins = "lcd_dc1_pd2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat6_pd3 {
+				nvidia,pins = "sdmmc3_dat6_pd3";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat7_pd4 {
+				nvidia,pins = "sdmmc3_dat7_pd4";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d1_pd5 {
+				nvidia,pins = "vi_d1_pd5";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_vsync_pd6 {
+				nvidia,pins = "vi_vsync_pd6";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_hsync_pd7 {
+				nvidia,pins = "vi_hsync_pd7";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_d0_pe0 {
+				nvidia,pins = "lcd_d0_pe0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d1_pe1 {
+				nvidia,pins = "lcd_d1_pe1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d2_pe2 {
+				nvidia,pins = "lcd_d2_pe2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d3_pe3 {
+				nvidia,pins = "lcd_d3_pe3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d4_pe4 {
+				nvidia,pins = "lcd_d4_pe4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d5_pe5 {
+				nvidia,pins = "lcd_d5_pe5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d6_pe6 {
+				nvidia,pins = "lcd_d6_pe6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d7_pe7 {
+				nvidia,pins = "lcd_d7_pe7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d8_pf0 {
+				nvidia,pins = "lcd_d8_pf0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d9_pf1 {
+				nvidia,pins = "lcd_d9_pf1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d10_pf2 {
+				nvidia,pins = "lcd_d10_pf2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d11_pf3 {
+				nvidia,pins = "lcd_d11_pf3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d12_pf4 {
+				nvidia,pins = "lcd_d12_pf4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d13_pf5 {
+				nvidia,pins = "lcd_d13_pf5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d14_pf6 {
+				nvidia,pins = "lcd_d14_pf6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d15_pf7 {
+				nvidia,pins = "lcd_d15_pf7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad0_pg0 {
+				nvidia,pins = "gmi_ad0_pg0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad1_pg1 {
+				nvidia,pins = "gmi_ad1_pg1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad2_pg2 {
+				nvidia,pins = "gmi_ad2_pg2";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad3_pg3 {
+				nvidia,pins = "gmi_ad3_pg3";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad4_pg4 {
+				nvidia,pins = "gmi_ad4_pg4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad5_pg5 {
+				nvidia,pins = "gmi_ad5_pg5";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad6_pg6 {
+				nvidia,pins = "gmi_ad6_pg6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad7_pg7 {
+				nvidia,pins = "gmi_ad7_pg7";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad8_ph0 {
+				nvidia,pins = "gmi_ad8_ph0";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad9_ph1 {
+				nvidia,pins = "gmi_ad9_ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad10_ph2 {
+				nvidia,pins = "gmi_ad10_ph2";
+				nvidia,function = "pwm2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad11_ph3 {
+				nvidia,pins = "gmi_ad11_ph3";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad12_ph4 {
+				nvidia,pins = "gmi_ad12_ph4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad13_ph5 {
+				nvidia,pins = "gmi_ad13_ph5";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad14_ph6 {
+				nvidia,pins = "gmi_ad14_ph6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wr_n_pi0 {
+				nvidia,pins = "gmi_wr_n_pi0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_oe_n_pi1 {
+				nvidia,pins = "gmi_oe_n_pi1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_dqs_pi2 {
+				nvidia,pins = "gmi_dqs_pi2";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_iordy_pi5 {
+				nvidia,pins = "gmi_iordy_pi5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs7_n_pi6 {
+				nvidia,pins = "gmi_cs7_n_pi6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wait_pi7 {
+				nvidia,pins = "gmi_wait_pi7";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_de_pj1 {
+				nvidia,pins = "lcd_de_pj1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs1_n_pj2 {
+				nvidia,pins = "gmi_cs1_n_pj2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_hsync_pj3 {
+				nvidia,pins = "lcd_hsync_pj3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_vsync_pj4 {
+				nvidia,pins = "lcd_vsync_pj4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_cts_n_pj5 {
+				nvidia,pins = "uart2_cts_n_pj5";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rts_n_pj6 {
+				nvidia,pins = "uart2_rts_n_pj6";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_a16_pj7 {
+				nvidia,pins = "gmi_a16_pj7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_adv_n_pk0 {
+				nvidia,pins = "gmi_adv_n_pk0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_clk_pk1 {
+				nvidia,pins = "gmi_clk_pk1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs2_n_pk3 {
+				nvidia,pins = "gmi_cs2_n_pk3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs3_n_pk4 {
+				nvidia,pins = "gmi_cs3_n_pk4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spdif_out_pk5 {
+				nvidia,pins = "spdif_out_pk5";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spdif_in_pk6 {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_a19_pk7 {
+				nvidia,pins = "gmi_a19_pk7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d2_pl0 {
+				nvidia,pins = "vi_d2_pl0";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d3_pl1 {
+				nvidia,pins = "vi_d3_pl1";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d4_pl2 {
+				nvidia,pins = "vi_d4_pl2";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d5_pl3 {
+				nvidia,pins = "vi_d5_pl3";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d6_pl4 {
+				nvidia,pins = "vi_d6_pl4";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d7_pl5 {
+				nvidia,pins = "vi_d7_pl5";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d8_pl6 {
+				nvidia,pins = "vi_d8_pl6";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d9_pl7 {
+				nvidia,pins = "vi_d9_pl7";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d16_pm0 {
+				nvidia,pins = "lcd_d16_pm0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d17_pm1 {
+				nvidia,pins = "lcd_d17_pm1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d18_pm2 {
+				nvidia,pins = "lcd_d18_pm2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d19_pm3 {
+				nvidia,pins = "lcd_d19_pm3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d20_pm4 {
+				nvidia,pins = "lcd_d20_pm4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d21_pm5 {
+				nvidia,pins = "lcd_d21_pm5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d22_pm6 {
+				nvidia,pins = "lcd_d22_pm6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d23_pm7 {
+				nvidia,pins = "lcd_d23_pm7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap1_fs_pn0 {
+				nvidia,pins = "dap1_fs_pn0";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_din_pn1 {
+				nvidia,pins = "dap1_din_pn1";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_dout_pn2 {
+				nvidia,pins = "dap1_dout_pn2";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_sclk_pn3 {
+				nvidia,pins = "dap1_sclk_pn3";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_cs0_n_pn4 {
+				nvidia,pins = "lcd_cs0_n_pn4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sdout_pn5 {
+				nvidia,pins = "lcd_sdout_pn5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_dc0_pn6 {
+				nvidia,pins = "lcd_dc0_pn6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "hdmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_data7_po0 {
+				nvidia,pins = "ulpi_data7_po0";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data0_po1 {
+				nvidia,pins = "ulpi_data0_po1";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data1_po2 {
+				nvidia,pins = "ulpi_data1_po2";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data2_po3 {
+				nvidia,pins = "ulpi_data2_po3";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data3_po4 {
+				nvidia,pins = "ulpi_data3_po4";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_data4_po5 {
+				nvidia,pins = "ulpi_data4_po5";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data5_po6 {
+				nvidia,pins = "ulpi_data5_po6";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data6_po7 {
+				nvidia,pins = "ulpi_data6_po7";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap3_fs_pp0 {
+				nvidia,pins = "dap3_fs_pp0";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_din_pp1 {
+				nvidia,pins = "dap3_din_pp1";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_dout_pp2 {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_sclk_pp3 {
+				nvidia,pins = "dap3_sclk_pp3";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_fs_pp4 {
+				nvidia,pins = "dap4_fs_pp4";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_din_pp5 {
+				nvidia,pins = "dap4_din_pp5";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_dout_pp6 {
+				nvidia,pins = "dap4_dout_pp6";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_sclk_pp7 {
+				nvidia,pins = "dap4_sclk_pp7";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			kb_col0_pq0 {
+				nvidia,pins = "kb_col0_pq0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col1_pq1 {
+				nvidia,pins = "kb_col1_pq1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col2_pq2 {
+				nvidia,pins = "kb_col2_pq2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col3_pq3 {
+				nvidia,pins = "kb_col3_pq3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col4_pq4 {
+				nvidia,pins = "kb_col4_pq4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col5_pq5 {
+				nvidia,pins = "kb_col5_pq5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col6_pq6 {
+				nvidia,pins = "kb_col6_pq6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col7_pq7 {
+				nvidia,pins = "kb_col7_pq7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row0_pr0 {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row1_pr1 {
+				nvidia,pins = "kb_row1_pr1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row2_pr2 {
+				nvidia,pins = "kb_row2_pr2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row3_pr3 {
+				nvidia,pins = "kb_row3_pr3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row4_pr4 {
+				nvidia,pins = "kb_row4_pr4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row5_pr5 {
+				nvidia,pins = "kb_row5_pr5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row6_pr6 {
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row7_pr7 {
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			kb_row8_ps0 {
+				nvidia,pins = "kb_row8_ps0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row9_ps1 {
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row11_ps3 {
+				nvidia,pins = "kb_row11_ps3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row12_ps4 {
+				nvidia,pins = "kb_row12_ps4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row13_ps5 {
+				nvidia,pins = "kb_row13_ps5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row14_ps6 {
+				nvidia,pins = "kb_row14_ps6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row15_ps7 {
+				nvidia,pins = "kb_row15_ps7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_pclk_pt0 {
+				nvidia,pins = "vi_pclk_pt0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_mclk_pt1 {
+				nvidia,pins = "vi_mclk_pt1";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d10_pt2 {
+				nvidia,pins = "vi_d10_pt2";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_d11_pt3 {
+				nvidia,pins = "vi_d11_pt3";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_d0_pt4 {
+				nvidia,pins = "vi_d0_pt4";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen2_i2c_sda_pt6 {
+				nvidia,pins = "gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu0 {
+				nvidia,pins = "pu0";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu1 {
+				nvidia,pins = "pu1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu2 {
+				nvidia,pins = "pu2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu3 {
+				nvidia,pins = "pu3";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu5 {
+				nvidia,pins = "pu5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu6 {
+				nvidia,pins = "pu6";
+				nvidia,function = "pwm3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			jtag_rtck_pu7 {
+				nvidia,pins = "jtag_rtck_pu7";
+				nvidia,function = "rtck";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv0 {
+				nvidia,pins = "pv0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			pv1 {
+				nvidia,pins = "pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv2 {
+				nvidia,pins = "pv2";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv3 {
+				nvidia,pins = "pv3";
+				nvidia,function = "clk_12m_out";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ddc_sda_pv5 {
+				nvidia,pins = "ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			crt_hsync_pv6 {
+				nvidia,pins = "crt_hsync_pv6";
+				nvidia,function = "crt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			crt_vsync_pv7 {
+				nvidia,pins = "crt_vsync_pv7";
+				nvidia,function = "crt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_cs1_n_pw0 {
+				nvidia,pins = "lcd_cs1_n_pw0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_m1_pw1 {
+				nvidia,pins = "lcd_m1_pw1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi2_cs1_n_pw2 {
+				nvidia,pins = "spi2_cs1_n_pw2";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk1_out_pw4 {
+				nvidia,pins = "clk1_out_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk2_out_pw5 {
+				nvidia,pins = "clk2_out_pw5";
+				nvidia,function = "extperiph2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			uart3_txd_pw6 {
+				nvidia,pins = "uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart3_rxd_pw7 {
+				nvidia,pins = "uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			spi2_sck_px2 {
+				nvidia,pins = "spi2_sck_px2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_mosi_px4 {
+				nvidia,pins = "spi1_mosi_px4";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_sck_px5 {
+				nvidia,pins = "spi1_sck_px5";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs0_n_px6 {
+				nvidia,pins = "spi1_cs0_n_px6";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_miso_px7 {
+				nvidia,pins = "spi1_miso_px7";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_nxt_py2 {
+				nvidia,pins = "ulpi_nxt_py2";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_stp_py3 {
+				nvidia,pins = "ulpi_stp_py3";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat3_py4 {
+				nvidia,pins = "sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat2_py5 {
+				nvidia,pins = "sdmmc1_dat2_py5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat1_py6 {
+				nvidia,pins = "sdmmc1_dat1_py6";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat0_py7 {
+				nvidia,pins = "sdmmc1_dat0_py7";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sdin_pz2 {
+				nvidia,pins = "lcd_sdin_pz2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_wr_n_pz3 {
+				nvidia,pins = "lcd_wr_n_pz3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sck_pz4 {
+				nvidia,pins = "lcd_sck_pz4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sys_clk_req_pz5 {
+				nvidia,pins = "sys_clk_req_pz5";
+				nvidia,function = "sysclk";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			pwr_i2c_sda_pz7 {
+				nvidia,pins = "pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			pbb0 {
+				nvidia,pins = "pbb0";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_i2c_sda_pbb2 {
+				nvidia,pins = "cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb3 {
+				nvidia,pins = "pbb3";
+				nvidia,function = "vgp3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb4 {
+				nvidia,pins = "pbb4";
+				nvidia,function = "vgp4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb5 {
+				nvidia,pins = "pbb5";
+				nvidia,function = "vgp5";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb6 {
+				nvidia,pins = "pbb6";
+				nvidia,function = "vgp6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb7 {
+				nvidia,pins = "pbb7";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pcc1 {
+				nvidia,pins = "pcc1";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			pcc2 {
+				nvidia,pins = "pcc2";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk2_req_pcc5 {
+				nvidia,pins = "clk2_req_pcc5";
+				nvidia,function = "dap";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_rst_n_pcc6 {
+				nvidia,pins = "pex_l2_rst_n_pcc6";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_clkreq_n_pcc7 {
+				nvidia,pins = "pex_l2_clkreq_n_pcc7";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_prsnt_n_pdd0 {
+				nvidia,pins = "pex_l0_prsnt_n_pdd0";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_rst_n_pdd1 {
+				nvidia,pins = "pex_l0_rst_n_pdd1";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_clkreq_n_pdd2 {
+				nvidia,pins = "pex_l0_clkreq_n_pdd2";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_wake_n_pdd3 {
+				nvidia,pins = "pex_wake_n_pdd3";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_prsnt_n_pdd4 {
+				nvidia,pins = "pex_l1_prsnt_n_pdd4";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_rst_n_pdd5 {
+				nvidia,pins = "pex_l1_rst_n_pdd5";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_clkreq_n_pdd6 {
+				nvidia,pins = "pex_l1_clkreq_n_pdd6";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_prsnt_n_pdd7 {
+				nvidia,pins = "pex_l2_prsnt_n_pdd7";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk3_req_pee1 {
+				nvidia,pins = "clk3_req_pee1";
+				nvidia,function = "dev3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk1_req_pee2 {
+				nvidia,pins = "clk1_req_pee2";
+				nvidia,function = "dap";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			owr {
+				nvidia,pins = "owr";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC4 pinmux */
+			sdmmc4_clk {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_cmd {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+						"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_rst_n {
+				nvidia,pins = "sdmmc4_rst_n_pcc3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			cam_mclk {
+				nvidia,pins = "cam_mclk_pcc0";
+				nvidia,function = "vi_alt3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			drive_groups {
+				nvidia,pins = "drive_gma",
+					      "drive_gmb",
+					      "drive_gmc",
+					      "drive_gmd";
+				nvidia,pull-down-strength = <9>;
+				nvidia,pull-up-strength = <9>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+	};
+
+	uartd: serial@70006300 {
+		status = "okay";
+	};
+
+	hdmi_ddc: i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	pwr_i2c: i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: pmic@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			wakeup-source;
+
+			ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
+			ti,system-power-controller;
+			ti,sleep-keep-ck32k;
+			ti,sleep-enable;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			regulators {
+				vdd_1v8: vddio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-name = "vdd_pllm,x,u,a_p_c_s";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+
+	sdmmc4: sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vmmc-supply = <&sys_3v3_reg>;
+		vqmmc-supply = <&vdd_1v8>;
+	};
+
+	micro_usb: usb@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb-phy@7d000000 {
+		status = "okay";
+	};
+
+	ethernet_usb: usb@7d004000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* SMSC 10/100T Ethernet Controller */
+		ethernet@2 {
+			compatible = "usb424,9e00";
+			reg = <2>;
+			local-mac-address = [00 11 22 33 44 55];
+		};
+	};
+
+	usb-phy@7d004000 {
+		status = "okay";
+	};
+
+	fullsize_usb: usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+	};
+
+	usb-phy@7d008000 {
+		status = "okay";
+	};
+
+	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
+	clk32k_in: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic-oscillator";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-power {
+			label = "power-led";
+			gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+			retain-state-suspended;
+		};
+	};
+
+	sys_3v3_reg: regulator-sys-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "sys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_vid_reg: regulator-vdd-vid {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio_vid";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts
index 87c2a4072e1..b376b91a7fa 100644
--- a/arch/arm/dts/tegra30-wexler-qc750.dts
+++ b/arch/arm/dts/tegra30-wexler-qc750.dts
@@ -157,7 +157,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -167,7 +167,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -177,7 +177,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -186,7 +186,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -196,7 +196,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6b2bb5a4586..24c81391d58 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,10 +16,11 @@
  */
 	tst     x0, x0                  // this is "b #0x84" in ARM
 	b       reset
-	.space  0x7c
+	.space  0x78
+	.word	fel_stash - .
 
-	.word	0xe28f0070	// add     r0, pc, #112	 // @(fel_stash - .)
-	.word	0xe59f106c	// ldr     r1, [pc, #108] // fel_stash - .
+	.word	0xe24f000c	// sub     r0, pc, #12  // @(fel_stash - .)
+	.word	0xe51f1010	// ldr     r1, [pc, #-16] // fel_stash - .
 	.word	0xe0800001	// add     r0, r0, r1
 	.word	0xe580d000	// str     sp, [r0]
 	.word	0xe580e004	// str     lr, [r0, #4]
@@ -54,7 +55,6 @@
 #else
 	.word   CONFIG_TEXT_BASE
 #endif
-	.word	fel_stash - .
 #else
 /* normal execution */
 	b	reset
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index ca3718411ab..2fd07403bdf 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -448,6 +448,11 @@ enum win_color_depth_id {
 #define LVS_OUTPUT_POLARITY_LOW		BIT(28)
 #define LSC0_OUTPUT_POLARITY_LOW	BIT(24)
 
+/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
+#define H_PULSE0_ENABLE		BIT(8)
+#define H_PULSE1_ENABLE		BIT(10)
+#define H_PULSE2_ENABLE		BIT(12)
+
 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */
 #define	CURSOR_ENABLE		BIT(16)
 #define	SOR_ENABLE		BIT(25)
@@ -504,6 +509,22 @@ enum {
 	DATA_ORDER_BLUE_RED,
 };
 
+/* DC_DISP_DISP_COLOR_CONTROL 0x430 */
+#define DITHER_CONTROL_DISABLE	(0 << 8)
+#define DITHER_CONTROL_ORDERED	(2 << 8)
+#define DITHER_CONTROL_ERRDIFF	(3 << 8)
+enum {
+	BASE_COLOR_SIZE_666,
+	BASE_COLOR_SIZE_111,
+	BASE_COLOR_SIZE_222,
+	BASE_COLOR_SIZE_333,
+	BASE_COLOR_SIZE_444,
+	BASE_COLOR_SIZE_555,
+	BASE_COLOR_SIZE_565,
+	BASE_COLOR_SIZE_332,
+	BASE_COLOR_SIZE_888,
+};
+
 /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
 #define DE_SELECT_SHIFT		0
 #define DE_SELECT_MASK		(0x3 << DE_SELECT_SHIFT)
@@ -570,8 +591,27 @@ enum {
 #define V_DDA_INC_SHIFT		16
 #define V_DDA_INC_MASK		(0xFFFF << V_DDA_INC_SHIFT)
 
-#define DC_POLL_TIMEOUT_MS		50
-#define DC_N_WINDOWS			5
-#define DC_REG_SAVE_SPACE		(DC_N_WINDOWS + 5)
+#define DC_POLL_TIMEOUT_MS	50
+#define DC_N_WINDOWS		5
+#define DC_REG_SAVE_SPACE	(DC_N_WINDOWS + 5)
+
+#define PULSE_MODE_NORMAL	(0 << 3)
+#define PULSE_MODE_ONE_CLOCK	(1 << 3)
+#define PULSE_POLARITY_HIGH	(0 << 4)
+#define PULSE_POLARITY_LOW	(1 << 4)
+#define PULSE_QUAL_ALWAYS	(0 << 6)
+#define PULSE_QUAL_VACTIVE	(2 << 6)
+#define PULSE_QUAL_VACTIVE1	(3 << 6)
+#define PULSE_LAST_START_A	(0 << 8)
+#define PULSE_LAST_END_A	(1 << 8)
+#define PULSE_LAST_START_B	(2 << 8)
+#define PULSE_LAST_END_B	(3 << 8)
+#define PULSE_LAST_START_C	(4 << 8)
+#define PULSE_LAST_END_C	(5 << 8)
+#define PULSE_LAST_START_D	(6 << 8)
+#define PULSE_LAST_END_D	(7 << 8)
+
+#define PULSE_START(x)		(((x) & 0xfff) <<  0)
+#define PULSE_END(x)		(((x) & 0xfff) << 16)
 
 #endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 4b6e8419504..9a5cc93884c 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -34,41 +34,41 @@ enum pmux_pin_io {
 
 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 enum pmux_pin_lock {
-	PMUX_PIN_LOCK_DEFAULT = 0,
-	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_DISABLE = 0,
 	PMUX_PIN_LOCK_ENABLE,
+	PMUX_PIN_LOCK_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_OD
 enum pmux_pin_od {
-	PMUX_PIN_OD_DEFAULT = 0,
-	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_DISABLE = 0,
 	PMUX_PIN_OD_ENABLE,
+	PMUX_PIN_OD_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 enum pmux_pin_ioreset {
-	PMUX_PIN_IO_RESET_DEFAULT = 0,
-	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_DISABLE = 0,
 	PMUX_PIN_IO_RESET_ENABLE,
+	PMUX_PIN_IO_RESET_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 enum pmux_pin_rcv_sel {
-	PMUX_PIN_RCV_SEL_DEFAULT = 0,
-	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_NORMAL = 0,
 	PMUX_PIN_RCV_SEL_HIGH,
+	PMUX_PIN_RCV_SEL_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
 enum pmux_pin_e_io_hv {
-	PMUX_PIN_E_IO_HV_DEFAULT = 0,
-	PMUX_PIN_E_IO_HV_NORMAL,
+	PMUX_PIN_E_IO_HV_NORMAL = 0,
 	PMUX_PIN_E_IO_HV_HIGH,
+	PMUX_PIN_E_IO_HV_DEFAULT,
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 8c8579e87e3..9598851b100 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -467,14 +467,14 @@ static const char * const tegra_pinctrl_to_func[] = {
 	[PMUX_FUNC_DAP3] = "dap3",
 	[PMUX_FUNC_DAP4] = "dap4",
 	[PMUX_FUNC_DAP5] = "dap5",
-	[PMUX_FUNC_DISPA] = "dispa",
-	[PMUX_FUNC_DISPB] = "dispb",
+	[PMUX_FUNC_DISPA] = "displaya",
+	[PMUX_FUNC_DISPB] = "displayb",
 	[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
 	[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
 	[PMUX_FUNC_GMI] = "gmi",
 	[PMUX_FUNC_GMI_INT] = "gmi_int",
 	[PMUX_FUNC_HDMI] = "hdmi",
-	[PMUX_FUNC_I2C] = "i2c",
+	[PMUX_FUNC_I2C] = "i2c1",
 	[PMUX_FUNC_I2C2] = "i2c2",
 	[PMUX_FUNC_I2C3] = "i2c3",
 	[PMUX_FUNC_IDE] = "ide",
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
index 4dbb589aab8..e906fdf1bf1 100644
--- a/arch/arm/include/asm/armv8/cpu.h
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -5,8 +5,11 @@
 
 #define MIDR_PARTNUM_CORTEX_A35		0xD04
 #define MIDR_PARTNUM_CORTEX_A53		0xD03
+#define MIDR_PARTNUM_CORTEX_A55		0xD05
 #define MIDR_PARTNUM_CORTEX_A57		0xD07
 #define MIDR_PARTNUM_CORTEX_A72		0xD08
+#define MIDR_PARTNUM_CORTEX_A73		0xD09
+#define MIDR_PARTNUM_CORTEX_A75		0xD0A
 #define MIDR_PARTNUM_CORTEX_A76		0xD0B
 #define MIDR_PARTNUM_SHIFT		0x4
 #define MIDR_PARTNUM_MASK		(0xFFF << MIDR_PARTNUM_SHIFT)
@@ -31,6 +34,9 @@ static inline unsigned int read_midr(void)
 
 is_cortex_a(35)
 is_cortex_a(53)
+is_cortex_a(55)
 is_cortex_a(57)
 is_cortex_a(72)
+is_cortex_a(73)
+is_cortex_a(75)
 is_cortex_a(76)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 1c95dd6fed2..74cd5051552 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
+CFLAGS_REMOVE_eabi_compat.o := $(LTO_CFLAGS)
 endif
 
 # some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S
index e21b54fdbcb..003d5f83041 100644
--- a/arch/arm/lib/crt0_aarch64_efi.S
+++ b/arch/arm/lib/crt0_aarch64_efi.S
@@ -144,6 +144,7 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	stp		x29, x30, [sp, #-32]!
 	mov		x29, sp
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 91b0fe12c51..593ee1e194a 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -143,13 +143,15 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	stmfd		sp!, {r0-r2, lr}
 
 	adr		r1, .L_DYNAMIC
 	ldr		r0, [r1]
 	add		r1, r0, r1
-	adrl		r0, image_base
+	sub		r0, pc, #((.+8-image_base) & 0xff)
+	sub		r0, r0, #((.+4-image_base) & 0xff00)
 	bl		_relocate
 	teq		r0, #0
 	bne		0f
diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c
index 602efe04c04..e6cafcc5f2b 100644
--- a/arch/arm/lib/eabi_compat.c
+++ b/arch/arm/lib/eabi_compat.c
@@ -33,7 +33,24 @@ void __aeabi_memcpy(void *dest, const void *src, size_t n)
 	(void) memcpy(dest, src, n);
 }
 
+void __aeabi_memcpy4(void *dest, const void *src, size_t n) __alias(__aeabi_memcpy);
+
+void __aeabi_memcpy8(void *dest, const void *src, size_t n) __alias(__aeabi_memcpy);
+
 void __aeabi_memset(void *dest, size_t n, int c)
 {
 	(void) memset(dest, c, n);
 }
+
+void __aeabi_memset4(void *dest, size_t n, int c) __alias(__aeabi_memset);
+
+void __aeabi_memset8(void *dest, size_t n, int c) __alias(__aeabi_memset);
+
+void __aeabi_memclr(void *dest, size_t n)
+{
+	(void) memset(dest, 0, n);
+}
+
+void __aeabi_memclr4(void *dest, size_t n) __alias(__aeabi_memclr);
+
+void __aeabi_memclr8(void *dest, size_t n) __alias(__aeabi_memclr);
diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c
index d78d704cb58..1f672eee2c8 100644
--- a/arch/arm/lib/image.c
+++ b/arch/arm/lib/image.c
@@ -28,13 +28,6 @@ struct Image_header {
 	uint32_t	res5;
 };
 
-bool booti_is_valid(const void *img)
-{
-	const struct Image_header *ih = img;
-
-	return ih->magic == le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC);
-}
-
 int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 		bool force_reloc)
 {
@@ -46,7 +39,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 
 	ih = (struct Image_header *)map_sysmem(image, 0);
 
-	if (!booti_is_valid(ih)) {
+	if (ih->magic != le32_to_cpu(LINUX_ARM64_IMAGE_MAGIC)) {
 		puts("Bad Linux ARM64 Image magic!\n");
 		return 1;
 	}
diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig
new file mode 100644
index 00000000000..be3562ae3ff
--- /dev/null
+++ b/arch/arm/mach-airoha/Kconfig
@@ -0,0 +1,32 @@
+if ARCH_AIROHA
+
+config SYS_VENDOR
+	default "airoha"
+
+choice
+	prompt "Airoha board select"
+
+config TARGET_AN7581
+	bool "Airoha AN7581 SoC"
+	select ARM64
+	help
+	  The Airoha EN7581 is a ARM-based SoC with a quad-core Cortex-A7
+	  including NEON and GPU, Mali-450 graphics, several DDR3 options,
+	  crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
+	  video interfaces supporting HDMI and MIPI, and video codec support.
+	  Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
+	  I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
+
+endchoice
+
+config SYS_SOC
+	default "an7581" if TARGET_AN7581
+
+config SYS_BOARD
+	default "an7581" if TARGET_AN7581
+
+config SYS_CONFIG_NAME
+	default "an7581" if TARGET_AN7581
+
+endif
+
diff --git a/arch/arm/mach-airoha/Makefile b/arch/arm/mach-airoha/Makefile
new file mode 100644
index 00000000000..215a300373b
--- /dev/null
+++ b/arch/arm/mach-airoha/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= cpu.o
+
+obj-$(CONFIG_TARGET_AN7581) += an7581/
diff --git a/arch/arm/mach-airoha/an7581/Makefile b/arch/arm/mach-airoha/an7581/Makefile
new file mode 100644
index 00000000000..886ab7e4eb9
--- /dev/null
+++ b/arch/arm/mach-airoha/an7581/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c
new file mode 100644
index 00000000000..cefe9c6db9e
--- /dev/null
+++ b/arch/arm/mach-airoha/an7581/init.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Airoha AN7581\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+static struct mm_region an7581_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+struct mm_region *mem_map = an7581_mem_map;
diff --git a/arch/arm/mach-airoha/cpu.c b/arch/arm/mach-airoha/cpu.c
new file mode 100644
index 00000000000..a578e964664
--- /dev/null
+++ b/arch/arm/mach-airoha/cpu.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <wdt.h>
+#include <dm/uclass-internal.h>
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9a43beda6fa..257c14e61b6 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -9,6 +9,8 @@ config AHAB_BOOT
 config IMX8
 	bool
 	select HAS_CAAM
+	imply CPU
+	imply CPU_IMX
 
 config MU_BASE_SPL
 	hex "MU base address used in SPL"
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 89f2b50c8a2..31f2f003d35 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,9 @@ config IMX8M
 	select LTO
 	select ROM_UNIFIED_SECTIONS
 	select ARMV8_CRYPTO
+	imply CPU
+	imply CPU_IMX
+	imply IMX_TMU
 
 config IMX8MQ
 	bool
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 49220c0955e..1ccdb1cf64f 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -8,8 +8,11 @@ config AHAB_BOOT
 config IMX9
 	bool
 	select BINMAN
+	select CPU
+	select CPU_IMX
 	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
+	imply IMX_TMU
 
 config IMX93
 	bool
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 1f8cb8e3822..1b8c0b1eb96 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -22,6 +22,9 @@ config SOC_K3_AM654
 config SOC_K3_J721E
 	bool "TI's K3 based J721E SoC Family Support"
 
+config SOC_K3_J7200
+	bool "TI's K3 based J7200 SoC Family Support"
+
 config SOC_K3_J721S2
 	bool "TI's K3 based J721S2 SoC Family Support"
 
@@ -33,18 +36,13 @@ config SOC_K3_J784S4
 
 endchoice
 
-if SOC_K3_J721E
-config SOC_K3_J721E_J7200
-	bool "TI's K3 based J7200 SoC variant Family Support"
-endif
-
 config SYS_SOC
 	default "k3"
 
 config SYS_K3_NON_SECURE_MSRAM_SIZE
 	hex
 	default 0x80000 if SOC_K3_AM654
-	default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x100000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x1c0000 if SOC_K3_AM642
 	default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
 	help
@@ -56,7 +54,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
 config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 	hex
 	default 0x58000 if SOC_K3_AM654
-	default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0xc0000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x180000 if SOC_K3_AM642
 	default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7
 	help
@@ -66,21 +64,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 config SYS_K3_MCU_SCRATCHPAD_BASE
 	hex
 	default 0x40280000 if SOC_K3_AM654
-	default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	help
 	  Describes the base address of MCU Scratchpad RAM.
 
 config SYS_K3_MCU_SCRATCHPAD_SIZE
 	hex
 	default 0x200 if SOC_K3_AM654
-	default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x200 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	help
 	  Describes the size of MCU Scratchpad RAM.
 
 config SYS_K3_BOOT_PARAM_TABLE_INDEX
 	hex
 	default 0x41c7fbfc if SOC_K3_AM654
-	default 0x41cffbfc if SOC_K3_J721E
+	default 0x41cffbfc if SOC_K3_J721E || SOC_K3_J7200
 	default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x701bebfc if SOC_K3_AM642
 	default 0x43c3f290 if SOC_K3_AM625
@@ -193,6 +191,7 @@ source "arch/arm/mach-k3/am62x/Kconfig"
 source "arch/arm/mach-k3/am62ax/Kconfig"
 source "arch/arm/mach-k3/am62px/Kconfig"
 source "arch/arm/mach-k3/j721e/Kconfig"
+source "arch/arm/mach-k3/j7200/Kconfig"
 source "arch/arm/mach-k3/j721s2/Kconfig"
 source "arch/arm/mach-k3/j722s/Kconfig"
 source "arch/arm/mach-k3/j784s4/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 5ce7fc62d80..b2fd5810b67 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_SOC_K3_AM642) += am64x/
 obj-$(CONFIG_SOC_K3_AM654) += am65x/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J7200) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
 obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index b191d53a0f5..fc7bee4d00b 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -32,6 +32,10 @@
 #include "j721e_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J7200
+#include "j721e_hardware.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J721S2
 #include "j721s2_hardware.h"
 #endif
@@ -62,6 +66,12 @@
 #define JTAG_ID_PARTNO_J722S	0xbba0
 #define JTAG_ID_PARTNO_J784S4	0xbb80
 
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID		(WKUP_CTRL_MMR0_BASE + 0x18)
+#define JTAG_DEV_J742S2_PKG_MASK		GENMASK(2, 0)
+#define JTAG_DEV_J742S2_PKG_SHIFT		0
+
+#define JTAG_ID_PKG_J742S2	0x7
+
 #define K3_SOC_ID(id, ID) \
 static inline bool soc_is_##id(void) \
 { \
diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h
index 95496e1c59d..39e6725bb9b 100644
--- a/arch/arm/mach-k3/include/mach/k3-ddr.h
+++ b/arch/arm/mach-k3/include/mach/k3-ddr.h
@@ -6,6 +6,8 @@
 #ifndef _K3_DDR_H_
 #define _K3_DDR_H_
 
+#include <spl.h>
+
 int dram_init(void);
 int dram_init_banksize(void);
 
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index ac1a34502ed..a47441ae6a5 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -14,6 +14,10 @@
 #include "j721e_spl.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J7200
+#include "j721e_spl.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J721S2
 #include "j721s2_spl.h"
 #endif
diff --git a/arch/arm/mach-k3/j7200/Kconfig b/arch/arm/mach-k3/j7200/Kconfig
new file mode 100644
index 00000000000..399daad8767
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Kconfig
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#	Andrew Davis <afd@ti.com>
+
+if SOC_K3_J7200
+
+choice
+	prompt "K3 J7200 based boards"
+	optional
+
+config TARGET_J7200_A72_EVM
+	bool "TI K3 based J7200 EVM running on A72"
+	select ARM64
+	select BOARD_LATE_INIT
+	imply TI_I2C_BOARD_DETECT
+	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
+
+config TARGET_J7200_R5_EVM
+	bool "TI K3 based J7200 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/j7200/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00000000000..6d3ff36e363
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#	Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += ../j721e/j721e_fdt.o
+obj-$(CONFIG_XPL_BUILD) += ../j721e/j721e_init.o
diff --git a/arch/arm/mach-k3/j721e/Kconfig b/arch/arm/mach-k3/j721e/Kconfig
index 0761b82b15a..4d01f2c8af2 100644
--- a/arch/arm/mach-k3/j721e/Kconfig
+++ b/arch/arm/mach-k3/j721e/Kconfig
@@ -29,27 +29,6 @@ config TARGET_J721E_R5_EVM
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
-config TARGET_J7200_A72_EVM
-	bool "TI K3 based J7200 EVM running on A72"
-	select ARM64
-	select SOC_K3_J721E_J7200
-	select BOARD_LATE_INIT
-	imply TI_I2C_BOARD_DETECT
-	select SYS_DISABLE_DCACHE_OPS
-	select BINMAN
-
-config TARGET_J7200_R5_EVM
-	bool "TI K3 based J7200 EVM running on R5"
-	select CPU_V7R
-	select SYS_THUMB_BUILD
-	select K3_LOAD_SYSFW
-	select RAM
-	select SPL_RAM
-	select K3_DDRSS
-	select BINMAN
-	imply SYS_K3_SPL_ATF
-	imply TI_I2C_BOARD_DETECT
-
 endchoice
 
 source "board/beagle/beagleboneai64/Kconfig"
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
index 7e2d2c16b45..f31c20f7ed6 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -48,7 +48,7 @@
 
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
-#if defined(CONFIG_TARGET_J721E_R5_EVM)
+#if defined(CONFIG_SOC_K3_J721E)
 	{ "PCIE0_CFG", 2560, 8 },
 	{ "PCIE1_CFG", 2561, 8 },
 	{ "USB3SS0_CORE", 2568, 4 },
@@ -57,11 +57,11 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
 	{ "UFS_HCI0_CFG", 2580, 4 },
 	{ "SERDES0", 2584, 1 },
 	{ "SERDES1", 2585, 1 },
-#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+#elif defined(CONFIG_SOC_K3_J7200)
 	{ "PCIE1_CFG", 2561, 7 },
 #endif
 }, cbass_hc0_fwls[] = {
-#if defined(CONFIG_TARGET_J721E_R5_EVM)
+#if defined(CONFIG_SOC_K3_J721E)
 	{ "PCIE0_HP", 2528, 24 },
 	{ "PCIE0_LP", 2529, 24 },
 	{ "PCIE1_HP", 2530, 24 },
diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig
index 1eadfb346a3..84194f6efa8 100644
--- a/arch/arm/mach-k3/j784s4/Kconfig
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -27,6 +27,24 @@ config TARGET_J784S4_R5_EVM
 	select BINMAN
 	imply SYS_K3_SPL_ATF
 
+config TARGET_J742S2_A72_EVM
+	bool "TI K3 based J742S2 EVM running on A72"
+	select ARM64
+	select BOARD_LATE_INIT
+	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
+
+config TARGET_J742S2_R5_EVM
+	bool "TI K3 based J742S2 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+
 endchoice
 
 source "board/ti/j784s4/Kconfig"
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index f533c5e7743..074e3b61a26 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
-obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J7200) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
 obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig
index 16324e15206..b43dd5a5c25 100644
--- a/arch/arm/mach-nexell/Kconfig
+++ b/arch/arm/mach-nexell/Kconfig
@@ -4,7 +4,6 @@ config ARCH_S5P4418
 	bool "Nexell S5P4418 SoC"
 	select CPU_V7A
 	select OF_CONTROL
-	select OF_SEPARATE
 	select NX_GPIO
 	select DM_SERIAL
 	select PL01X_SERIAL
diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index 1ab9472e198..5541a4714ac 100644
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -176,10 +176,10 @@ ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash ip register */
 	mov	ip, lr		/* save link reg across call */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+#if !defined(CONFIG_SYS_NAND_BOOT)
 /*
  * No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
+ * in NAND Boot.
  */
 	ldr	r1, =SRAM_CLK_CODE
 	bl	cpy_clk_code
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 2ef936aab75..deae4d32378 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -88,7 +88,29 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-static void qcom_parse_memory(const void *fdt)
+/**
+ * The generic memory parsing code in U-Boot lacks a few things that we
+ * need on Qualcomm:
+ *
+ * 1. It sets gd->ram_size and gd->ram_base to represent a single memory block
+ * 2. setup_dest_addr() later relocates U-Boot to ram_base + ram_size, the end
+ *    of that first memory block.
+ *
+ * This results in all memory beyond U-Boot being unusable in Linux when booting
+ * with EFI.
+ *
+ * Since the ranges in the memory node may be out of order, the only way for us
+ * to correctly determine the relocation address for U-Boot is to parse all
+ * memory regions and find the highest valid address.
+ *
+ * We can't use fdtdec_setup_memory_banksize() since it stores the result in
+ * gd->bd, which is not yet allocated.
+ *
+ * @fdt: FDT blob to parse /memory node from
+ *
+ * Return: 0 on success or -ENODATA if /memory node is missing or incomplete
+ */
+static int qcom_parse_memory(const void *fdt)
 {
 	int offset;
 	const fdt64_t *memory;
@@ -97,16 +119,12 @@ static void qcom_parse_memory(const void *fdt)
 	int i, j, banks;
 
 	offset = fdt_path_offset(fdt, "/memory");
-	if (offset < 0) {
-		log_err("No memory node found in device tree!\n");
-		return;
-	}
+	if (offset < 0)
+		return -ENODATA;
 
 	memory = fdt_getprop(fdt, offset, "reg", &memsize);
-	if (!memory) {
-		log_err("No memory configuration was provided by the previous bootloader!\n");
-		return;
-	}
+	if (!memory)
+		return -ENODATA;
 
 	banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
 
@@ -119,7 +137,6 @@ static void qcom_parse_memory(const void *fdt)
 	for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
 		prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
 		prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
-		/* SM8650 boards sometimes have empty regions! */
 		if (!prevbl_ddr_banks[j].size) {
 			j--;
 			continue;
@@ -127,13 +144,16 @@ static void qcom_parse_memory(const void *fdt)
 		ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size);
 	}
 
+	if (!banks || !prevbl_ddr_banks[0].size)
+		return -ENODATA;
+
 	/* Sort our RAM banks -_- */
 	qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp);
 
 	gd->ram_base = prevbl_ddr_banks[0].start;
 	gd->ram_size = ram_end - gd->ram_base;
-	debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n",
-	      gd->ram_base, gd->ram_size, ram_end);
+
+	return 0;
 }
 
 static void show_psci_version(void)
@@ -142,24 +162,56 @@ static void show_psci_version(void)
 
 	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
 
+	/* Some older SoCs like MSM8916 don't always support PSCI */
+	if ((int)res.a0 == PSCI_RET_NOT_SUPPORTED)
+		return;
+
 	debug("PSCI:  v%ld.%ld\n",
 	      PSCI_VERSION_MAJOR(res.a0),
 	      PSCI_VERSION_MINOR(res.a0));
 }
 
+/**
+ * Most MSM8916 devices in the wild shipped without PSCI support, but the
+ * upstream DTs pretend that PSCI exists. If that situation is detected here,
+ * the /psci node is deleted. This is done very early to ensure the PSCI
+ * firmware driver doesn't bind (which then binds a sysreset driver that won't
+ * work).
+ */
+static void qcom_psci_fixup(void *fdt)
+{
+	int offset, ret;
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	if ((int)res.a0 != PSCI_RET_NOT_SUPPORTED)
+		return;
+
+	offset = fdt_path_offset(fdt, "/psci");
+	if (offset < 0)
+		return;
+
+	debug("Found /psci DT node on device with no PSCI. Deleting.\n");
+	ret = fdt_del_node(fdt, offset);
+	if (ret)
+		log_err("Failed to delete /psci node: %d\n", ret);
+}
+
 /* We support booting U-Boot with an internal DT when running as a first-stage bootloader
  * or for supporting quirky devices where it's easier to leave the downstream DT in place
  * to improve ABL compatibility. Otherwise, we use the DT provided by ABL.
  */
 int board_fdt_blob_setup(void **fdtp)
 {
-	struct fdt_header *fdt;
+	struct fdt_header *external_fdt, *internal_fdt;
 	bool internal_valid, external_valid;
-	int ret = 0;
+	int ret = -ENODATA;
 
-	fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
-	external_valid = fdt && !fdt_check_header(fdt);
-	internal_valid = !fdt_check_header(*fdtp);
+	internal_fdt = (struct fdt_header *)*fdtp;
+	external_fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
+	external_valid = external_fdt && !fdt_check_header(external_fdt);
+	internal_valid = !fdt_check_header(internal_fdt);
 
 	/*
 	 * There is no point returning an error here, U-Boot can't do anything useful in this situation.
@@ -167,31 +219,42 @@ int board_fdt_blob_setup(void **fdtp)
 	 */
 	if (!internal_valid && !external_valid)
 		panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
-		      (phys_addr_t)fdt);
+		      (phys_addr_t)external_fdt);
+
+	/* Prefer memory information from internal DT if it's present */
+	if (internal_valid)
+		ret = qcom_parse_memory(internal_fdt);
+
+	if (ret < 0 && external_valid) {
+		/* No internal FDT or it lacks a proper /memory node.
+		 * The previous bootloader handed us something, let's try that.
+		 */
+		if (internal_valid)
+			debug("No memory info in internal FDT, falling back to external\n");
+
+		ret = qcom_parse_memory(external_fdt);
+	}
+
+	if (ret < 0)
+		panic("No valid memory ranges found!\n");
+
+	debug("ram_base = %#011lx, ram_size = %#011llx\n",
+	      gd->ram_base, gd->ram_size);
 
 	if (internal_valid) {
 		debug("Using built in FDT\n");
 		ret = -EEXIST;
 	} else {
 		debug("Using external FDT\n");
-		/* So we can use it before returning */
-		*fdtp = fdt;
+		*fdtp = external_fdt;
+		ret = 0;
 	}
 
-	/*
-	 * Parse the /memory node while we're here,
-	 * this makes it easy to do other things early.
-	 */
-	qcom_parse_memory(*fdtp);
+	qcom_psci_fixup(*fdtp);
 
 	return ret;
 }
 
-void reset_cpu(void)
-{
-	psci_system_reset();
-}
-
 /*
  * Some Qualcomm boards require GPIO configuration when switching USB modes.
  * Support setting this configuration via pinctrl state.
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ba1b1541437..ab432390d3c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -457,6 +457,9 @@ config MACH_SUN50I_H616
 	select SUN50I_GEN_H6
 	imply OF_UPSTREAM
 
+config MACH_SUN50I_A133
+	bool "sun50i (Allwinner A133)"
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -713,16 +716,10 @@ endif
 
 config SYS_CLK_FREQ
 	default 408000000 if MACH_SUNIV
-	default 1008000000 if MACH_SUN4I
-	default 1008000000 if MACH_SUN5I
-	default 1008000000 if MACH_SUN6I
-	default 912000000 if MACH_SUN7I
 	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
-	default 1008000000 if MACH_SUN8I
-	default 1008000000 if MACH_SUN9I
 	default 888000000 if MACH_SUN50I_H6
-	default 1008000000 if MACH_SUN50I_H616
-	default 1008000000 if MACH_SUN8I_R528
+	default 912000000 if MACH_SUN7I
+	default 1008000000
 
 config SYS_CONFIG_NAME
 	default "suniv" if MACH_SUNIV
@@ -1131,10 +1128,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP
 	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
 	  flipped elsewise.
 
-source "board/sunxi/Kconfig"
-
-endif
-
 config CHIP_DIP_SCAN
 	bool "Enable DIPs detection for CHIP board"
 	select SUPPORT_EXTENSION_SCAN
@@ -1143,3 +1136,7 @@ config CHIP_DIP_SCAN
 	select W1_EEPROM
 	select W1_EEPROM_DS24XXX
 	select CMD_EXTENSION
+
+source "board/sunxi/Kconfig"
+
+endif
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index b424a7893ea..359513d1669 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -147,15 +147,20 @@ unsigned int clock_get_pll6(void)
 	if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
 		div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
 			CCM_PLL6_CTRL_P0_SHIFT) + 1;
-		m = 1;
 	} else {
 		div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
 			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
-		if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
-			m = 4;
-		else
-			m = 2;
 	}
 
+	/*
+	 * The factors encoded in the register describe the doubled clock
+	 * frequency, expect for the H6, where it's the quadrupled frequency.
+	 * Compensate for that here.
+	 */
+	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+		m = 4;
+	else
+		m = 2;
+
 	return 24000000U * n / m / div1 / div2;
 }
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index b3554cc64bf..cd9d321a018 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1360,36 +1360,94 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para,
 	panic("This DRAM setup is currently not supported.\n");
 }
 
+static void mctl_write_pattern(void)
+{
+	unsigned int i;
+	u32 *ptr, val;
+
+	ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+	for (i = 0; i < 16; ptr++, i++) {
+		if (i & 1)
+			val = ~(ulong)ptr;
+		else
+			val = (ulong)ptr;
+		writel(val, ptr);
+	}
+}
+
+static bool mctl_check_pattern(ulong offset)
+{
+	unsigned int i;
+	u32 *ptr, val;
+
+	ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+	for (i = 0; i < 16; ptr++, i++) {
+		if (i & 1)
+			val = ~(ulong)ptr;
+		else
+			val = (ulong)ptr;
+		if (val != *(ptr + offset / 4))
+			return false;
+	}
+
+	return true;
+}
+
 static void mctl_auto_detect_dram_size(const struct dram_para *para,
 				       struct dram_config *config)
 {
-	unsigned int shift;
+	unsigned int shift, cols, rows;
+	u32 buffer[16];
 
 	/* max. config for columns, but not rows */
 	config->cols = 11;
 	config->rows = 13;
 	mctl_core_init(para, config);
 
+	/*
+	 * Store content so it can be restored later. This is important
+	 * if controller was already initialized and holds any data
+	 * which is important for restoring system.
+	 */
+	memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+	mctl_write_pattern();
+
 	shift = config->bus_full_width + 1;
 
 	/* detect column address bits */
-	for (config->cols = 8; config->cols < 11; config->cols++) {
-		if (mctl_mem_matches(1ULL << (config->cols + shift)))
+	for (cols = 8; cols < 11; cols++) {
+		if (mctl_check_pattern(1ULL << (cols + shift)))
 			break;
 	}
-	debug("detected %u columns\n", config->cols);
+	debug("detected %u columns\n", cols);
+
+	/* restore data */
+	memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
 
 	/* reconfigure to make sure that all active rows are accessible */
-	config->rows = 18;
+	config->cols = 8;
+	config->rows = 17;
 	mctl_core_init(para, config);
 
+	/* store data again as it might be moved */
+	memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+	mctl_write_pattern();
+
 	/* detect row address bits */
 	shift = config->bus_full_width + 4 + config->cols;
-	for (config->rows = 13; config->rows < 18; config->rows++) {
-		if (mctl_mem_matches(1ULL << (config->rows + shift)))
+	for (rows = 13; rows < 17; rows++) {
+		if (mctl_check_pattern(1ULL << (rows + shift)))
 			break;
 	}
-	debug("detected %u rows\n", config->rows);
+	debug("detected %u rows\n", rows);
+
+	/* restore data again */
+	memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+	config->cols = cols;
+	config->rows = rows;
 }
 
 static unsigned long mctl_calc_size(const struct dram_config *config)
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 8e19324c8ac..c77dc538456 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -16,33 +16,10 @@
 #include <power/pmic.h>
 #include <asm/arch/pmic_bus.h>
 
-#define AXP152_I2C_ADDR			0x30
-
-#define AXP209_I2C_ADDR			0x34
-#define AXP717_I2C_ADDR			0x34
-
-#define AXP305_I2C_ADDR			0x36
-#define AXP313_I2C_ADDR			0x36
-
 #define AXP221_CHIP_ADDR		0x68
 
 #if CONFIG_IS_ENABLED(PMIC_AXP)
 static struct udevice *pmic;
-#else
-static int pmic_i2c_address(void)
-{
-	if (IS_ENABLED(CONFIG_AXP152_POWER))
-		return AXP152_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP305_POWER))
-		return AXP305_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP313_POWER))
-		return AXP313_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP717_POWER))
-		return AXP717_I2C_ADDR;
-
-	/* Other AXP2xx and AXP8xx variants */
-	return AXP209_I2C_ADDR;
-}
 #endif
 
 int pmic_bus_init(void)
@@ -88,7 +65,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
 		return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
 
-	return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
+	return i2c_read(CONFIG_AXP_I2C_ADDRESS, reg, 1, data, 1);
 #endif
 }
 
@@ -102,7 +79,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
 		return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
 
-	return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
+	return i2c_write(CONFIG_AXP_I2C_ADDRESS, reg, 1, &data, 1);
 #endif
 }
 
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index 33e55d49686..422007c985b 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -16,7 +16,9 @@
 @ the machine code must be inserted as verbatim .word statements into the
 @ beginning of the AArch64 U-Boot code.
 @ To get the encoded bytes, use:
-@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}gcc -c -Iinclude -Iarch/arm/include	\
+@   -D__ASSEMBLY__ -DCONFIG_ARM64			\
+@   -o rmr_switch.o arch/arm/mach-sunxi/rmr_switch.S
 @ ${CROSS_COMPILE}objdump -d rmr_switch.o
 @
 @ The resulting words should be inserted into the U-Boot file at
@@ -29,14 +31,40 @@
 #include <config.h>
 
 .text
+	b	start32			// this is "tst x0, x0" in AArch64
+	.word	0x14000047		// this is "b   reset"  in AArch64
 
-#ifndef CONFIG_SUN50I_GEN_H6
-	ldr	r1, =0x017000a0		@ MMIO mapped RVBAR[0] register
+	.space  0x78			// gap distance set by the common
+					// encoding of the first instruction
+fel_stash_addr:
+	.word	fel_stash - .		// distance to fel_stash buffer
+
+start32:
+	adr	r0, fel_stash_addr	// absolute location of fel_stash_addr
+	ldr	r1, fel_stash_addr	// distance to actual fel_stash
+	add	r0, r0, r1		// real address of fel_stash
+
+	/* save the current state as needed by the BROM for a later return */
+	str	sp, [r0]
+	str	lr, [r0, #4]
+	mrs	lr, CPSR
+	str	lr, [r0, #8]
+	mrc	p15, 0, lr, cr1, cr0, 0		// SCTLR
+	str	lr, [r0, #12]
+	mrc	p15, 0, lr, cr12, cr0, 0	// VBAR
+	str	lr, [r0, #16]
+
+	ldr	r1, =CONFIG_SUNXI_RVBAR_ADDRESS
+	ldr	r0, =SUNXI_SRAMC_BASE
+	ldr	r0, [r0, #36]			// SRAM_VER_REG
+	ands	r0, r0, #0xff
+	ldrne	r1, =CONFIG_SUNXI_RVBAR_ALTERNATIVE
+#ifdef CONFIG_XPL_BUILD
+	ldr	r0, =CONFIG_SPL_TEXT_BASE
 #else
-	ldr	r1, =0x09010040		@ MMIO mapped RVBAR[0] register
+	ldr	r0, =CONFIG_TEXT_BASE
 #endif
-	ldr	r0, =0x57aA7add		@ start address, to be replaced
-	str	r0, [r1]
+	str	r0, [r1]			// store start address in RVBAR
 	dsb	sy
 	isb	sy
 	mrc	15, 0, r0, cr12, cr0, 2	@ read RMR register
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index e0f054af8e0..b5099ce67fc 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -32,6 +32,10 @@ config TARGET_IDEAPAD_YOGA_11
 	bool "Lenovo Ideapad Yoga 11 board"
 	select BOARD_LATE_INIT
 
+config TARGET_OUYA
+	bool "Ouya Game Console board"
+	select BOARD_LATE_INIT
+
 config TARGET_QC750
 	bool "Wexler QC750 board"
 	select BOARD_LATE_INIT
@@ -64,6 +68,7 @@ source "board/toradex/colibri_t30/Kconfig"
 source "board/htc/endeavoru/Kconfig"
 source "board/asus/grouper/Kconfig"
 source "board/lenovo/ideapad-yoga-11/Kconfig"
+source "board/ouya/ouya/Kconfig"
 source "board/wexler/qc750/Kconfig"
 source "board/microsoft/surface-rt/Kconfig"
 source "board/avionic-design/tec-ng/Kconfig"
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig
index d9cd8dce964..14201df80f2 100644
--- a/arch/riscv/cpu/k1/Kconfig
+++ b/arch/riscv/cpu/k1/Kconfig
@@ -13,6 +13,7 @@ config SPACEMIT_K1
 	imply RISCV_ACLINT if RISCV_MMODE
 	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
 	imply CMD_CPU
+	imply DM_RESET
 	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405faca574..ceb916b74a7 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -82,8 +82,9 @@
 					};
 				};
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 				@fdt-SEQ {
+					fit,operation = "gen-fdt-nodes";
 					description = "NAME";
 					type = "flat_dt";
 					compression = "none";
@@ -92,9 +93,12 @@
 			};
 
 			configurations {
+
+#ifndef CONFIG_MULTI_DTB_FIT
 				default = "conf-1";
+#endif
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 				@conf-SEQ {
 #else
 				conf-1 {
@@ -115,7 +119,7 @@
 #endif
 #endif /* CONFIG_OPTEE */
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 					fdt = "fdt-SEQ";
 #endif
 				};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 8a7386b76e6..6fac247e7ac 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -46,20 +46,6 @@
 		#clock-cells = <0>;
 	};
 
-	eth_csrclk: eth-csrclk {
-		compatible = "fixed-clock";
-		clock-frequency = <250000000>;
-		clock-output-names = "eth_csrclk";
-		#clock-cells = <0x0>;
-	};
-
-	eth_ptpclk: eth-ptpclk {
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "eth_ptpclk";
-		#clock-cells = <0x0>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 514be453dba..7c0f1b928e2 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -327,7 +327,7 @@
 		ranges;
 
 		uart0: serial@d4017000 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017000 0x0 0x100>;
 			interrupts = <42>;
 			clock-frequency = <14857000>;
@@ -337,7 +337,7 @@
 		};
 
 		uart2: serial@d4017100 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017100 0x0 0x100>;
 			interrupts = <44>;
 			clock-frequency = <14857000>;
@@ -347,7 +347,7 @@
 		};
 
 		uart3: serial@d4017200 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017200 0x0 0x100>;
 			interrupts = <45>;
 			clock-frequency = <14857000>;
@@ -357,7 +357,7 @@
 		};
 
 		uart4: serial@d4017300 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017300 0x0 0x100>;
 			interrupts = <46>;
 			clock-frequency = <14857000>;
@@ -367,7 +367,7 @@
 		};
 
 		uart5: serial@d4017400 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017400 0x0 0x100>;
 			interrupts = <47>;
 			clock-frequency = <14857000>;
@@ -377,7 +377,7 @@
 		};
 
 		uart6: serial@d4017500 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017500 0x0 0x100>;
 			interrupts = <48>;
 			clock-frequency = <14857000>;
@@ -387,7 +387,7 @@
 		};
 
 		uart7: serial@d4017600 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017600 0x0 0x100>;
 			interrupts = <49>;
 			clock-frequency = <14857000>;
@@ -397,7 +397,7 @@
 		};
 
 		uart8: serial@d4017700 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017700 0x0 0x100>;
 			interrupts = <50>;
 			clock-frequency = <14857000>;
@@ -407,7 +407,7 @@
 		};
 
 		uart9: serial@d4017800 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017800 0x0 0x100>;
 			interrupts = <51>;
 			clock-frequency = <14857000>;
@@ -447,7 +447,7 @@
 		};
 
 		sec_uart1: serial@f0612000 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xf0612000 0x0 0x100>;
 			interrupts = <43>;
 			clock-frequency = <14857000>;
@@ -455,5 +455,20 @@
 			reg-io-width = <4>;
 			status = "reserved"; /* for TEE usage */
 		};
+
+		reset: reset-controller@d4050000 {
+			compatible = "spacemit,k1-reset";
+			reg = <0x0 0xd4050000 0x0 0x209c>,
+				<0x0 0xd4282800 0x0 0x400>,
+				<0x0 0xd4015000 0x0 0x1000>,
+				<0x0 0xd4090000 0x0 0x1000>,
+				<0x0 0xd4282c00 0x0 0x400>,
+				<0x0 0xd8440000 0x0 0x98>,
+				<0x0 0xc0000000 0x0 0x4280>,
+				<0x0 0xf0610000 0x0 0x20>;
+			reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+			#reset-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
\ No newline at end of file
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 4cce001e80d..05787bdb92d 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -13,82 +13,6 @@
 };
 
 &binman {
-	itb {
-		fit {
-			images {
-				fdt-jh7110-milkv-mars {
-					description = "jh7110-milkv-mars";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
-					};
-				};
-
-				fdt-jh7110-pine64-star64 {
-					description = "jh7110-pine64-star64";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
-					};
-				};
-
-				fdt-jh7110-starfive-visionfive-2-v1.2a {
-					description = "jh7110-starfive-visionfive-2-v1.2a";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
-					};
-				};
-
-				fdt-jh7110-starfive-visionfive-2-v1.3b {
-					description = "jh7110-starfive-visionfive-2-v1.3b";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
-					};
-				};
-			};
-
-			configurations {
-				conf-jh7110-milkv-mars {
-					description = "jh7110-milkv-mars";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-milkv-mars";
-				};
-
-				conf-jh7110-pine64-star64 {
-					description = "jh7110-pine64-star64";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-pine64-star64";
-				};
-
-				conf-jh7110-starfive-visionfive-2-v1.2a {
-					description = "jh7110-starfive-visionfive-2-v1.2a";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
-				};
-
-				conf-jh7110-starfive-visionfive-2-v1.3b {
-					description = "jh7110-starfive-visionfive-2-v1.3b";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
-				};
-			};
-		};
-	};
-
 	spl-img {
 		filename = "spl/u-boot-spl.bin.normal.out";
 
diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index 9eacbe4a859..f170e4b26d6 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -179,6 +179,7 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	addi		sp, sp, -(SIZE_LONG * 3)
 	SAVE_LONG(a0, 0)
diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c
index 859326cbac8..a82f48e9a50 100644
--- a/arch/riscv/lib/image.c
+++ b/arch/riscv/lib/image.c
@@ -32,13 +32,6 @@ struct linux_image_h {
 	uint32_t	res4;		/* reserved */
 };
 
-bool booti_is_valid(const void *img)
-{
-	const struct linux_image_h *lhdr = img;
-
-	return lhdr->magic == LINUX_RISCV_IMAGE_MAGIC;
-}
-
 int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 		bool force_reloc)
 {
@@ -46,7 +39,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 
 	lhdr = (struct linux_image_h *)map_sysmem(image, 0);
 
-	if (!booti_is_valid(lhdr)) {
+	if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) {
 		puts("Bad Linux RISCV Image magic!\n");
 		return -EINVAL;
 	}
diff --git a/arch/sandbox/include/asm/serial.h b/arch/sandbox/include/asm/serial.h
index 16589a1b219..41506341816 100644
--- a/arch/sandbox/include/asm/serial.h
+++ b/arch/sandbox/include/asm/serial.h
@@ -44,7 +44,7 @@ void sandbox_serial_endisable(bool enabled);
  * @buf: holds input characters available to be read by this driver
  */
 struct sandbox_serial_priv {
-	struct membuff buf;
+	struct membuf buf;
 	char serial_buf[16];
 	bool start_of_line;
 };
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index 8ed923750f4..44ba8b52e13 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -89,8 +89,3 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
 
 	return 1;
 }
-
-bool booti_is_valid(const void *img)
-{
-	return false;
-}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 006a59d6fa6..dc9483ad723 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -30,7 +30,7 @@ config X86_RUN_32BIT
 	  arch_phys_memset() can be used for basic access to other memory.
 
 config X86_RUN_64BIT
-	bool "64-bit"
+	bool "32-bit SPL followed by 64-bit U-Boot"
 	select X86_64
 	select SPL if !EFI_APP
 	select SPL_SEPARATE_BSS if !EFI_APP
@@ -40,6 +40,14 @@ config X86_RUN_64BIT
 	  runs through the 16-bit and 32-bit init, then switches to 64-bit
 	  mode and jumps to U-Boot proper.
 
+config X86_RUN_64BIT_NO_SPL
+	bool "64-bit"
+	select X86_64
+	help
+          Build U-Boot as a 64-bit binary without SPL. As U-Boot enters
+          in 64-bit mode, the assumption is that the silicon is fully
+          initialized (MP, page tables, etc.).
+
 endchoice
 
 config X86_64
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 085302c0482..66f25533b97 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -26,7 +26,7 @@ config SYS_COREBOOT
 	imply CBMEM_CONSOLE
 	imply X86_TSC_READ_BASE
 	imply USE_PREBOOT
-	select BINMAN if X86_64
+	select BINMAN if X86_RUN_64BIT
 	select SYSINFO
 	imply SYSINFO_EXTRA
 
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index fa7430b436f..d0719d1a405 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -22,7 +22,7 @@ int arch_cpu_init(void)
 {
 	int ret;
 
-	ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+	ret = IS_ENABLED(CONFIG_X86_64) ? x86_cpu_reinit_f() :
 		x86_cpu_init_f();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a8b21406ac0..c373b14df30 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -364,3 +364,27 @@ long locate_coreboot_table(void)
 
 	return addr;
 }
+
+static bool has_cpuid(void)
+{
+	return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static uint cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+	if (!has_cpuid())
+		return 32;
+
+	if (cpu_cpuid_extended_level() >= 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+
+	return 32;
+}
diff --git a/arch/x86/cpu/i386/call64.S b/arch/x86/cpu/i386/call64.S
index d81bcc6f8f4..a9d3f16a6ad 100644
--- a/arch/x86/cpu/i386/call64.S
+++ b/arch/x86/cpu/i386/call64.S
@@ -7,10 +7,11 @@
  */
 
 #include <asm/msr-index.h>
+#include <asm/processor.h>
 #include <asm/processor-flags.h>
 
 .code32
-.section .text_call64
+.section .text_call64, "ax"
 .globl cpu_call64
 cpu_call64:
 	/*
@@ -21,17 +22,19 @@ cpu_call64:
 	 * ecx - target
 	 */
 	cli
+	pushl	$0		/* top 64-bits of target */
 	push	%ecx		/* arg2 = target */
 	push	%edx		/* arg1 = setup_base */
 	mov	%eax, %ebx
 
-	/* Load new GDT with the 64bit segments using 32bit descriptor */
-	leal	gdt, %eax
-	movl	%eax, gdt+2
-	lgdt	gdt
+	# disable paging
+	movl	%cr0, %eax
+	andl	$~X86_CR0_PG, %eax
+	movl	%eax, %cr0
 
 	/* Enable PAE mode */
-	movl	$(X86_CR4_PAE), %eax
+	movl	%cr4, %eax
+	orl	$X86_CR4_PAE, %eax
 	movl	%eax, %cr4
 
 	/* Enable the boot page tables */
@@ -44,12 +47,6 @@ cpu_call64:
 	btsl	$_EFER_LME, %eax
 	wrmsr
 
-	/* After gdt is loaded */
-	xorl	%eax, %eax
-	lldt	%ax
-	movl    $0x20, %eax
-	ltr	%ax
-
 	/*
 	 * Setup for the jump to 64bit mode
 	 *
@@ -62,22 +59,18 @@ cpu_call64:
 	 */
 	pop	%esi			/* setup_base */
 
-	pushl	$0x10
-	leal	lret_target, %eax
-	pushl	%eax
-
 	/* Enter paged protected Mode, activating Long Mode */
-	movl	$(X86_CR0_PG | X86_CR0_PE), %eax
+	movl	%cr0, %eax
+	orl	$X86_CR0_PG, %eax
 	movl	%eax, %cr0
 
 	/* Jump from 32bit compatibility mode into 64bit mode. */
-	lret
+	ljmp	$(X86_GDT_ENTRY_64BIT_CS * X86_GDT_ENTRY_SIZE), $lret_target
 
-code64:
+.code64
 lret_target:
-	pop	%eax			/* target */
-	mov	%eax, %eax		/* Clear bits 63:32 */
-	jmp	*%eax			/* Jump to the 64-bit target */
+	pop	%rax			/* target */
+	jmp	*%rax			/* Jump to the 64-bit target */
 
 .globl call64_stub_size
 call64_stub_size:
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index a51a24498a7..ee6dbeb5c48 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -35,10 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPUID_FEATURE_PAE	BIT(6)
-#define CPUID_FEATURE_PSE36	BIT(17)
-#define CPUID_FEAURE_HTT	BIT(28)
-
 /*
  * Constructor for a conventional segment GDT (or LDT) entry
  * This is a macro so it can be used in initialisers
@@ -160,6 +156,9 @@ void arch_setup_gd(gd_t *new_gd)
 
 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_CS] = GDT_ENTRY(0xaf9b, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_TS1] = GDT_ENTRY(0x8980, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_TS2] = 0;
 
 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
 	load_ds(X86_GDT_ENTRY_32BIT_DS);
@@ -409,25 +408,6 @@ static void setup_identity(void)
 	}
 }
 
-static uint cpu_cpuid_extended_level(void)
-{
-	return cpuid_eax(0x80000000);
-}
-
-int cpu_phys_address_size(void)
-{
-	if (!has_cpuid())
-		return 32;
-
-	if (cpu_cpuid_extended_level() >= 0x80000008)
-		return cpuid_eax(0x80000008) & 0xff;
-
-	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
-		return 36;
-
-	return 32;
-}
-
 static void setup_mtrr(void)
 {
 	u64 mtrr_cap;
@@ -589,6 +569,13 @@ int cpu_has_64bit(void)
 #define PAGETABLE_BASE		0x80000
 #define PAGETABLE_SIZE		(6 * 4096)
 
+#define _PRES BIT(0)	/* present */
+#define _RW   BIT(1)	/* write allowed */
+#define _US   BIT(2)	/* user-access allowed */
+#define _A    BIT(5)	/* has been accessed */
+#define _DT   BIT(6)	/* has been written to */
+#define _PS   BIT(7)	/* indicates 2MB page size here */
+
 /**
  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
  *
@@ -601,15 +588,17 @@ static void build_pagetable(uint32_t *pgtable)
 	memset(pgtable, '\0', PAGETABLE_SIZE);
 
 	/* Level 4 needs a single entry */
-	pgtable[0] = (ulong)&pgtable[1024] + 7;
+	pgtable[0] = (ulong)&pgtable[1024] + _PRES + _RW + _US + _A;
 
 	/* Level 3 has one 64-bit entry for each GiB of memory */
 	for (i = 0; i < 4; i++)
-		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
+		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i +
+			_PRES + _RW + _US + _A;
 
 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
 	for (i = 0; i < 2048; i++)
-		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+		pgtable[2048 + i * 2] = _PRES + _RW + _US + _PS + _A +  _DT +
+					 (i << 21UL);
 }
 
 int cpu_jump_to_64bit(ulong setup_base, ulong target)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 07ea89162de..7a0f00b9b8f 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 Google, Inc
+ * Portions added from coreboot
  *
  * Memory Type Range Regsters - these are used to tell the CPU whether
  * memory is cacheable and if so the cache write mode to use.
@@ -16,6 +17,7 @@
  * since the MTRR registers are sometimes in flux.
  */
 
+#include <cpu.h>
 #include <cpu_func.h>
 #include <log.h>
 #include <sort.h>
@@ -39,6 +41,27 @@ static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
 	"Back",
 };
 
+u64 mtrr_to_size(u64 mask)
+{
+	u64 size;
+
+	size = ~mask & ((1ULL << cpu_phys_address_size()) - 1);
+	size |= (1 << 12) - 1;
+	size += 1;
+
+	return size;
+}
+
+u64 mtrr_to_mask(u64 size)
+{
+	u64 mask;
+
+	mask = ~(size - 1);
+	mask &= (1ull << cpu_phys_address_size()) - 1;
+
+	return mask;
+}
+
 /* Prepare to adjust MTRRs */
 void mtrr_open(struct mtrr_state *state, bool do_caches)
 {
@@ -68,11 +91,9 @@ void mtrr_close(struct mtrr_state *state, bool do_caches)
 
 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
 {
-	u64 mask;
+	u64 mask = mtrr_to_mask(size);
 
 	wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
-	mask = ~(size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
 	wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
 }
 
@@ -184,30 +205,80 @@ int mtrr_commit(bool do_caches)
 	return 0;
 }
 
-int mtrr_add_request(int type, uint64_t start, uint64_t size)
+/* fms: find most significant bit set (from Linux)  */
+static inline uint fms(uint val)
+{
+	uint ret;
+
+	__asm__("bsrl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $0,%0\n"
+		"1:" : "=r" (ret) : "mr" (val));
+
+	return ret;
+}
+
+/*
+ * fms64: find most significant bit set in a 64-bit word
+ * As samples, fms64(0x0) = 0; fms64(0x4400) = 14;
+ * fms64(0x40400000000) = 42.
+ */
+static uint fms64(uint64_t val)
+{
+	u32 hi = (u32)(val >> 32);
+
+	if (!hi)
+		return fms((u32)val);
+
+	return fms(hi) + 32;
+}
+
+int mtrr_add_request(int type, u64 base, uint64_t size)
 {
 	struct mtrr_request *req;
-	uint64_t mask;
+	u64 mask;
 
 	debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
 	if (!gd->arch.has_mtrr)
 		return -ENOSYS;
 
-	if (!is_power_of_2(size))
-		return -EINVAL;
-
-	if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
-		return -ENOSPC;
-	req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
-	req->type = type;
-	req->start = start;
-	req->size = size;
-	debug("%d: type=%d, %08llx  %08llx\n", gd->arch.mtrr_req_count - 1,
-	      req->type, req->start, req->size);
-	mask = ~(req->size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
-	mask |= MTRR_PHYS_MASK_VALID;
-	debug("   %016llx %016llx\n", req->start | req->type, mask);
+	while (size) {
+		uint addr_lsb;
+		uint size_msb;
+		u64 mtrr_size;
+
+		addr_lsb = fls64(base);
+		size_msb = fms64(size);
+
+		/*
+		 * All MTRR entries need to have their base aligned to the
+		 * mask size. The maximum size is calculated by a function of
+		 * the min base bit set and maximum size bit set.
+		 * Algorithm is from coreboot
+		 */
+		if (!addr_lsb || addr_lsb > size_msb)
+			mtrr_size = 1ull << size_msb;
+		else
+			mtrr_size = 1ull << addr_lsb;
+		log_debug("addr_lsb %x size_msb %x mtrr_size %llx\n",
+			  addr_lsb, size_msb, mtrr_size);
+
+		if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
+			return -ENOSPC;
+		req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
+		req->type = type;
+		req->start = base;
+		req->size = mtrr_size;
+		log_debug("%d: type=%d, %08llx  %08llx ",
+			  gd->arch.mtrr_req_count - 1, req->type, req->start,
+			  req->size);
+		mask = mtrr_to_mask(req->size);
+		mask |= MTRR_PHYS_MASK_VALID;
+		log_debug("   %016llx %016llx\n", req->start | req->type, mask);
+
+		size -= mtrr_size;
+		base += mtrr_size;
+	}
 
 	return 0;
 }
@@ -360,9 +431,7 @@ int mtrr_list(int reg_count, int cpu_select)
 
 		base = info.mtrr[i].base;
 		mask = info.mtrr[i].mask;
-		size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
-		size |= (1 << 12) - 1;
-		size += 1;
+		size = mtrr_to_size(mask);
 		valid = mask & MTRR_PHYS_MASK_VALID;
 		type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
 		printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index 62a301c0fd3..ba3638e6acc 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -4,7 +4,9 @@
  */
 
 #include <init.h>
+#include <spl.h>
 #include <asm/global_data.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/arch/qemu.h>
 #include <linux/sizes.h>
@@ -44,6 +46,22 @@ int dram_init(void)
 	gd->ram_size += qemu_get_high_memory_size();
 	post_code(POST_DRAM);
 
+	if (xpl_phase() == PHASE_BOARD_F) {
+		u64 total = gd->ram_size;
+		int ret;
+
+		if (total > SZ_2G + SZ_1G)
+			total += SZ_1G;
+		ret = mtrr_add_request(MTRR_TYPE_WRBACK, 0, total);
+		if (ret != -ENOSYS) {
+			if (ret)
+				return log_msg_ret("mta", ret);
+			ret = mtrr_commit(false);
+			if (ret)
+				return log_msg_ret("mtc", ret);
+		}
+	}
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
index 17a04f86479..078d1d86b02 100644
--- a/arch/x86/cpu/qemu/e820.c
+++ b/arch/x86/cpu/qemu/e820.c
@@ -6,6 +6,7 @@
  * (C) Copyright 2019 Bin Meng <bmeng.cn@gmail.com>
  */
 
+#include <bloblist.h>
 #include <env_internal.h>
 #include <malloc.h>
 #include <asm/e820.h>
@@ -19,51 +20,34 @@ unsigned int install_e820_map(unsigned int max_entries,
 			      struct e820_entry *entries)
 {
 	u64 high_mem_size;
-	int n = 0;
+	struct e820_ctx ctx;
 
-	entries[n].addr = 0;
-	entries[n].size = ISA_START_ADDRESS;
-	entries[n].type = E820_RAM;
-	n++;
+	e820_init(&ctx, entries, max_entries);
 
-	entries[n].addr = ISA_START_ADDRESS;
-	entries[n].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[n].type = E820_RESERVED;
-	n++;
+	e820_next(&ctx, E820_RAM, ISA_START_ADDRESS);
+	e820_next(&ctx, E820_RESERVED, ISA_END_ADDRESS);
 
 	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
+	 * if we use bloblist to allocate high memory for storing ACPI tables,
+	 * we need to reserve that region in e820 tables, otherwise the kernel
+	 * will reclaim them and data will be corrupted. The ACPI tables may not
+	 * have been written yet, so use the whole bloblist size
 	 */
-	entries[n].addr = ISA_END_ADDRESS;
-	entries[n].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[n].type = E820_RAM;
-	n++;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[n].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[n].size = TOTAL_MALLOC_LEN;
-	entries[n].type = E820_RESERVED;
-	n++;
-
-	entries[n].addr = gd->relocaddr;
-	entries[n].size = qemu_get_low_memory_size() - gd->relocaddr;
-	entries[n].type = E820_RESERVED;
-	n++;
-
-	entries[n].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[n].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[n].type = E820_RESERVED;
-	n++;
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+		e820_to_addr(&ctx, E820_RAM, (ulong)gd->bloblist);
+		e820_next(&ctx, E820_ACPI, bloblist_get_total_size());
+	} else {
+		/* If using memalign() reserve that whole region instead */
+		e820_to_addr(&ctx, E820_RAM, gd->relocaddr - TOTAL_MALLOC_LEN);
+		e820_next(&ctx, E820_ACPI, TOTAL_MALLOC_LEN);
+	}
+	e820_to_addr(&ctx, E820_RAM, qemu_get_low_memory_size());
+	e820_add(&ctx, E820_RESERVED, CONFIG_PCIE_ECAM_BASE,
+		 CONFIG_PCIE_ECAM_SIZE);
 
 	high_mem_size = qemu_get_high_memory_size();
-	if (high_mem_size) {
-		entries[n].addr = SZ_4G;
-		entries[n].size = high_mem_size;
-		entries[n].type = E820_RAM;
-		n++;
-	}
+	if (high_mem_size)
+		e820_add(&ctx, E820_RAM, SZ_4G, high_mem_size);
 
-	return n;
+	return e820_finish(&ctx);
 }
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 563f63e2bc8..e846ccd44aa 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,14 +15,21 @@
 #include <asm/arch/qemu.h>
 #include <asm/u-boot-x86.h>
 
-static bool i440fx;
-
 #if CONFIG_IS_ENABLED(QFW_PIO)
 U_BOOT_DRVINFO(x86_qfw_pio) = {
 	.name = "qfw_pio",
 };
 #endif
 
+static bool is_i440fx(void)
+{
+	u16 device;
+
+	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
+
+	return device == PCI_DEVICE_ID_INTEL_82441;
+}
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -50,16 +57,17 @@ static void enable_pm_ich9(void)
 
 void qemu_chipset_init(void)
 {
-	u16 device, xbcs;
+	bool i440fx;
+	u16 xbcs;
 	int pam, i;
 
+	i440fx = is_i440fx();
+
 	/*
 	 * i440FX and Q35 chipset have different PAM register offset, but with
 	 * the same bitfield layout. Here we determine the offset based on its
 	 * PCI device ID.
 	 */
-	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
-	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
 	pam = i440fx ? I440FX_PAM : Q35_PAM;
 
 	/*
@@ -123,7 +131,7 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
 {
 	u8 irq;
 
-	if (i440fx) {
+	if (is_i440fx()) {
 		/*
 		 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
 		 * connected to I/O APIC INTPIN#16-19. Instead they are routed
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 0ef27cc5a00..385a691265e 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -254,7 +254,7 @@ multiboot_header:
 	 * GDT is setup in a safe location in RAM
 	 */
 gdt_ptr2:
-	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.word	gdt2_end - gdt_ptr2 - 1
 	.long	gdt_rom2	/* base */
 
 	/* Some CPUs are picky about GDT alignment... */
@@ -313,4 +313,6 @@ gdt_rom2:
 	.byte	0x93		/* access */
 	.byte	0xcf		/* flags + limit_high */
 	.byte	0x00		/* base_high */
+gdt2_end:
+
 #endif
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 865a49731e5..8d9acb193e0 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -61,7 +61,7 @@ idt_ptr:
 	 * GDT is setup in a safe location in RAM
 	 */
 gdt_ptr:
-	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.word	gdt_end - gdt_rom - 1
 	.long	BOOT_SEG + gdt_rom	/* base */
 
 	/* Some CPUs are picky about GDT alignment... */
@@ -120,3 +120,4 @@ gdt_rom:
 	.byte	0x93		/* access */
 	.byte	0xcf		/* flags + limit_high */
 	.byte	0x00		/* base_high */
+gdt_end:
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 71bc07f872a..25ae92c702f 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -59,11 +59,6 @@ int x86_cpu_reinit_f(void)
 	return 0;
 }
 
-int cpu_phys_address_size(void)
-{
-	return CONFIG_CPU_ADDR_BITS;
-}
-
 int x86_cpu_init_f(void)
 {
 	return 0;
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index ac4865300f1..657d920b14f 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -122,6 +122,14 @@ struct efi_info {
 	__u32 efi_memmap_hi;
 };
 
+/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */
+struct olpc_ofw_header {
+	__u32 ofw_magic;	/* OFW signature */
+	__u32 ofw_version;
+	__u32 cif_handler;	/* callback into OFW */
+	__u32 irq_desc_table;
+} __attribute__((packed));
+
 /* The so-called "zeropage" */
 struct boot_params {
 	struct screen_info screen_info;			/* 0x000 */
@@ -134,7 +142,12 @@ struct boot_params {
 	__u8  hd0_info[16];	/* obsolete! */		/* 0x080 */
 	__u8  hd1_info[16];	/* obsolete! */		/* 0x090 */
 	struct sys_desc_table sys_desc_table;		/* 0x0a0 */
-	__u8  _pad4[144];				/* 0x0b0 */
+	struct olpc_ofw_header olpc_ofw_header;		/* 0x0b0 */
+	__u32 ext_ramdisk_image;			/* 0x0c0 */
+	__u32 ext_ramdisk_size;				/* 0x0c4 */
+	__u32 ext_cmd_line_ptr;				/* 0x0c8 */
+	__u8  _pad4[112];				/* 0x0cc */
+	__u32 cc_blob_address;				/* 0x13c */
 	struct edid_info edid_info;			/* 0x140 */
 	struct efi_info efi_info;			/* 0x1c0 */
 	__u32 alt_mem_k;				/* 0x1e0 */
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index fd389d4024c..5d24c17f8a3 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -58,6 +58,10 @@ enum {
 	X86_SYSCON_PUNIT,	/* Power unit */
 };
 
+#define CPUID_FEATURE_PAE	BIT(6)
+#define CPUID_FEATURE_PSE36	BIT(17)
+#define CPUID_FEAURE_HTT	BIT(28)
+
 struct cpuid_result {
 	uint32_t eax;
 	uint32_t ebx;
@@ -105,68 +109,47 @@ static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
 	return result;
 }
 
-/*
- * CPUID functions returning a single datum
- */
-static inline unsigned int cpuid_eax(unsigned int op)
+static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
+				unsigned int *ecx, unsigned int *edx)
 {
-	unsigned int eax;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax)
-		: "0" (op)
-		: "ecx", "edx", "edi");
-	return eax;
+	/* ecx is often an input as well as an output. */
+	asm volatile("cpuid"
+	    : "=a" (*eax),
+	      "=b" (*ebx),
+	      "=c" (*ecx),
+	      "=d" (*edx)
+	    : "0" (*eax), "2" (*ecx)
+	    : "memory");
 }
 
-static inline unsigned int cpuid_ebx(unsigned int op)
-{
-	unsigned int eax, ebx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%ebx, %%esi;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=S" (ebx)
-		: "0" (op)
-		: "ecx", "edx", "edi");
-	return ebx;
+#define native_cpuid_reg(reg)					\
+static inline unsigned int cpuid_##reg(unsigned int op)	\
+{								\
+	unsigned int eax = op, ebx, ecx = 0, edx;		\
+								\
+	native_cpuid(&eax, &ebx, &ecx, &edx);			\
+								\
+	return reg;						\
 }
 
-static inline unsigned int cpuid_ecx(unsigned int op)
-{
-	unsigned int eax, ecx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=c" (ecx)
-		: "0" (op)
-		: "edx", "edi");
-	return ecx;
-}
+/*
+ * Native CPUID functions returning a single datum.
+ */
+native_cpuid_reg(eax)
+native_cpuid_reg(ebx)
+native_cpuid_reg(ecx)
+native_cpuid_reg(edx)
 
-static inline unsigned int cpuid_edx(unsigned int op)
+#if CONFIG_IS_ENABLED(X86_64)
+static inline int flag_is_changeable_p(u32 flag)
 {
-	unsigned int eax, edx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=d" (edx)
-		: "0" (op)
-		: "ecx", "edi");
-	return edx;
+	return 1;
 }
-
-#if !CONFIG_IS_ENABLED(X86_64)
-
+#else
 /* Standard macro to see if a specific flag is changeable */
-static inline int flag_is_changeable_p(uint32_t flag)
+static inline int flag_is_changeable_p(u32 flag)
 {
-	uint32_t f1, f2;
+	u32 f1, f2;
 
 	asm(
 		"pushfl\n\t"
@@ -181,9 +164,9 @@ static inline int flag_is_changeable_p(uint32_t flag)
 		"popfl\n\t"
 		: "=&r" (f1), "=&r" (f2)
 		: "ir" (flag));
-	return ((f1^f2) & flag) != 0;
+	return ((f1 ^ f2) & flag) != 0;
 }
-#endif
+#endif /* X86_64 */
 
 /**
  * cpu_enable_paging_pae() - Enable PAE-paging
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 1ab709abfc8..a535818b2d5 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -3,6 +3,8 @@
 
 #define E820MAX		128	/* number of entries in E820MAP */
 
+#ifdef __ASSEMBLY__
+
 #define E820_RAM	1
 #define E820_RESERVED	2
 #define E820_ACPI	3
@@ -10,9 +12,21 @@
 #define E820_UNUSABLE	5
 #define E820_COUNT	6	/* Number of types */
 
-#ifndef __ASSEMBLY__
+#else
+
 #include <linux/types.h>
 
+/* Available e820 memory-region types */
+enum e820_type {
+	E820_RAM	= 1,
+	E820_RESERVED,
+	E820_ACPI,
+	E820_NVS,
+	E820_UNUSABLE,
+
+	E820_COUNT,
+};
+
 struct e820_entry {
 	__u64 addr;	/* start of memory segment */
 	__u64 size;	/* size of memory segment */
@@ -22,11 +36,82 @@ struct e820_entry {
 #define ISA_START_ADDRESS	0xa0000
 #define ISA_END_ADDRESS		0x100000
 
+/**
+ * Context to use for e820_add()
+ *
+ * @entries: Table being filled in
+ * @addr: Current address we are up to
+ * @count: Number of entries added to @entries so far
+ * @max_entries: Maximum number of entries allowed
+ */
+struct e820_ctx {
+	struct e820_entry *entries;
+	u64 addr;
+	int count;
+	int max_entries;
+};
+
+/**
+ * e820_init() - Start setting up an e820 table
+ *
+ * @ctx: Context to set up
+ * @entries: Place to put entries
+ * @max_entries: Maximum size of @entries
+ */
+void e820_init(struct e820_ctx *ctx, struct e820_entry *entries,
+	       int max_entries);
+
+/**
+ * e820_add() - Add an entry to the table
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @addr: Start address of entry
+ * @size Size of entry
+ */
+void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size);
+
+/**
+ * e820_to_addr() - Add an entry that covers the space up to a given address
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @end_addr: Address where the entry should finish
+ */
+void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 end_addr);
+
+/**
+ * e820_next() - Add an entry that carries on from the last one
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @size Size of entry
+ */
+void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size);
+
+/**
+ * e820_finish() - Finish the table
+ *
+ * Checks the table is not too large, panics if so
+ *
+ * @ctx: Context
+ * Returns: Number of entries
+ */
+int e820_finish(struct e820_ctx *ctx);
+
 /* Implementation-defined function to install an e820 map */
 unsigned int install_e820_map(unsigned int max_entries,
 			      struct e820_entry *);
 
 /**
+ * e820_dump() - Dump the e820 table
+ *
+ * @entries: Pointer to start of table
+ * @count: Number of entries in the table
+ */
+void e820_dump(struct e820_entry *entries, uint count);
+
+/**
  * cb_install_e820_map() - Install e820 map provided by coreboot sysinfo
  *
  * This should be used when booting from coreboot, since in that case the
@@ -39,6 +124,14 @@ unsigned int install_e820_map(unsigned int max_entries,
 unsigned int cb_install_e820_map(unsigned int max_entries,
 				 struct e820_entry *entries);
 
+/**
+ * e820_dump() - Dump an e820 table
+ *
+ * @entries: Pointer to first entry
+ * @count: Number of entries in the table
+ */
+void e820_dump(struct e820_entry *entries, uint count);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_X86_E820_H */
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index e23fb2c8e72..c689fc23d08 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -10,6 +10,7 @@
 #ifndef __ASM_INTERRUPT_H_
 #define __ASM_INTERRUPT_H_ 1
 
+#include <stdbool.h>
 #include <asm/types.h>
 
 #define SYS_NUM_IRQS	16
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index af5f9a11980..39dc7b33aa0 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -59,15 +59,14 @@ static inline unsigned long long native_read_tscp(unsigned int *aux)
  * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
  * it means rax *or* rdx.
  */
-#ifdef CONFIG_X86_64
-#define DECLARE_ARGS(val, low, high)	unsigned low, high
-#define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
-#define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
+#if CONFIG_IS_ENABLED(X86_64)
+/* Using 64-bit values saves one instruction clearing the high half of low */
+#define DECLARE_ARGS(val, low, high)	unsigned long low, high
+#define EAX_EDX_VAL(val, low, high)	((low) | (high) << 32)
 #define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
 #else
 #define DECLARE_ARGS(val, low, high)	unsigned long long val
 #define EAX_EDX_VAL(val, low, high)	(val)
-#define EAX_EDX_ARGS(val, low, high)	"A" (val)
 #define EAX_EDX_RET(val, low, high)	"=A" (val)
 #endif
 
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 2e995f54061..67e897daa25 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -91,6 +91,22 @@ struct mtrr_info {
 };
 
 /**
+ * mtrr_to_size() - Convert a mask to a size value
+ *
+ * @mask: Value of the mask register
+ * Return: associated size
+ */
+u64 mtrr_to_size(u64 mask);
+
+/**
+ * mtrr_to_mask() - Convert a size to a mask value
+ *
+ * @size: Value of the size register
+ * Return: associated mask, without MTRR_PHYS_MASK_VALID
+ */
+u64 mtrr_to_mask(u64 size);
+
+/**
  * mtrr_open() - Prepare to adjust MTRRs
  *
  * Use mtrr_open() passing in a structure - this function will init it. Then
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index d7b68367861..ad8240be387 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -18,7 +18,10 @@
 #define X86_GDT_ENTRY_16BIT_DS		6
 #define X86_GDT_ENTRY_16BIT_FLAT_CS	7
 #define X86_GDT_ENTRY_16BIT_FLAT_DS	8
-#define X86_GDT_NUM_ENTRIES		9
+#define X86_GDT_ENTRY_64BIT_CS		9
+#define X86_GDT_ENTRY_64BIT_TS1		10
+#define X86_GDT_ENTRY_64BIT_TS2		11
+#define X86_GDT_NUM_ENTRIES		12
 
 #define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
 
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 4ed6d8d5cc2..8b542605170 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -10,8 +10,6 @@
 #include <asm/bootparam.h>
 #include <asm/e820.h>
 
-struct bootm_info;
-
 /* linux i386 zImage/bzImage header. Offsets relative to
  * the start of the image */
 
@@ -45,27 +43,64 @@ enum {
 };
 
 /**
+ * struct zboot_state - Current state of the boot
+ *
+ * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already
+ *	been loaded and does not exist (as a cohesive whole) in memory
+ * @bzimage_size: Size of the bzImage, or 0 to detect this
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @load_address: Address where the bzImage is moved before booting, either
+ *	BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ *	This is set up when loading the zimage
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ *	DEFAULT_SETUP_BASE
+ *	This is set up when loading the zimage
+ * @cmdline: Environment variable containing the 'override' command line, or
+ *	NULL to use the one in the setup block
+ */
+struct zboot_state {
+	ulong bzimage_addr;
+	ulong bzimage_size;
+	ulong initrd_addr;
+	ulong initrd_size;
+	ulong load_address;
+	struct boot_params *base_ptr;
+	const char *cmdline;
+};
+
+extern struct zboot_state state;
+
+/**
+ * zimage_dump() - Dump information about a zimage
+ *
+ * @base_ptr: Pointer to the boot parameters
+ * @show_cmdline: true to show the kernel command line
+ */
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
+
+/**
  * zboot_load() - Load a zimage
  *
  * Load the zimage into the correct place
  *
  * Return: 0 if OK, -ve on error
  */
-int zboot_load(struct bootm_info *bmi);
+int zboot_load(void);
 
 /**
  * zboot_setup() - Set up the zboot image reeady for booting
  *
  * Return: 0 if OK, -ve on error
  */
-int zboot_setup(struct bootm_info *bmi);
+int zboot_setup(void);
 
 /**
  * zboot_go() - Start the image
  *
  * Return: 0 if OK, -ve on error
  */
-int zboot_go(struct bootm_info *bmi);
+int zboot_go(void);
 
 /**
  * load_zimage() - Load a zImage or bzImage
@@ -104,7 +139,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
  *
  * Record information about a zimage so it can be booted
  *
- * @bmi: Bootm information
  * @bzimage_addr: Address of the bzImage to boot
  * @bzimage_size: Size of the bzImage, or 0 to detect this
  * @initrd_addr: Address of the initial ramdisk, or 0 if none
@@ -115,17 +149,14 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
  * @cmdline: Environment variable containing the 'override' command line, or
  *	NULL to use the one in the setup block
  */
-void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size,
-		 ulong initrd_addr, ulong initrd_size, ulong base_addr,
-		 const char *cmdline);
+void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
+		 ulong initrd_size, ulong base_addr, const char *cmdline);
 
 /**
  * zboot_info() - Show simple info about a zimage
  *
- * Shows where the kernel was loaded and also the setup base
- *
- * @bmi: Bootm information
+ * Shows wherer the kernel was loaded and also the setup base
  */
-void zboot_info(struct bootm_info *bmi);
+void zboot_info(void);
 
 #endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 43e6a1de77d..a908356e8a6 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -26,7 +26,9 @@ obj-y	+= e820.o
 obj-y	+= init_helpers.o
 obj-y	+= interrupts.o
 obj-y	+= lpc-uclass.o
+ifndef CONFIG_XPL_BUILD
 obj-y	+= mpspec.o
+endif
 obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_nhlt.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 03f7360032c..de4578666fb 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -5,6 +5,9 @@
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  * Copyright (C) 2009-2010 coresystems GmbH
  */
+
+#define LOG_CATEGRORY	LOGC_ARCH
+
 #include <compiler.h>
 #include <bios_emul.h>
 #include <irq_func.h>
@@ -228,7 +231,11 @@ static void vbe_set_graphics(int vesa_mode, struct vesa_state *mode_info)
 {
 	unsigned char *framebuffer;
 
-	mode_info->video_mode = (1 << 14) | vesa_mode;
+	/*
+	 * bit 14 is linear-framebuffer mode
+	 * bit 15 means don't clear the display
+	 */
+	mode_info->video_mode = (1 << 14) | (1 << 15) | vesa_mode;
 	vbe_get_mode_info(mode_info);
 
 	framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr;
@@ -298,16 +305,14 @@ asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses,
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-#ifdef CONFIG_REALMODE_DEBUG
-	debug("oprom: INT# 0x%x\n", intnumber);
-	debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
-	      eax, ebx, ecx, edx);
-	debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
-	      ebp, esp, edi, esi);
-	debug("oprom:  ip: %04x      cs: %04x   flags: %08x\n",
-	      ip, cs, flags);
-	debug("oprom: stackflags = %04x\n", stackflags);
-#endif
+	log_debug("oprom: INT# 0x%x\n", intnumber);
+	log_debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+		  eax, ebx, ecx, edx);
+	log_debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
+		  ebp, esp, edi, esi);
+	log_debug("oprom:  ip: %04x      cs: %04x   flags: %08x\n",
+		  ip, cs, flags);
+	log_debug("oprom: stackflags = %04x\n", stackflags);
 
 	/*
 	 * Fetch arguments from the stack and put them to a place
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
index b2cf1527b1c..e0c2284a901 100644
--- a/arch/x86/lib/bios_interrupts.c
+++ b/arch/x86/lib/bios_interrupts.c
@@ -7,6 +7,8 @@
  * Copyright (C) 2007-2009 coresystems GmbH
  */
 
+#define LOG_CATEGRORY	LOGC_ARCH
+
 #include <log.h>
 #include <asm/pci.h>
 #include "bios_emul.h"
@@ -198,10 +200,8 @@ int int1a_handler(void)
 			dm_pci_write_config32(dev, reg, dword);
 			break;
 		}
-#ifdef CONFIG_REALMODE_DEBUG
-		debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
-		      bus, devfn, reg, M.x86.R_ECX);
-#endif
+		log_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
+			  bus, devfn, reg, M.x86.R_ECX);
 		M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
 		M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
 		retval = 1;
diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c
index d478b7486e3..bcc5f6f3044 100644
--- a/arch/x86/lib/e820.c
+++ b/arch/x86/lib/e820.c
@@ -3,13 +3,39 @@
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
 
+#define LOG_CATEGORY	LOGC_ARCH
+
 #include <efi_loader.h>
 #include <lmb.h>
+#include <log.h>
 #include <asm/e820.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *const e820_type_name[E820_COUNT] = {
+	[E820_RAM] = "RAM",
+	[E820_RESERVED] = "Reserved",
+	[E820_ACPI] = "ACPI",
+	[E820_NVS] = "ACPI NVS",
+	[E820_UNUSABLE] = "Unusable",
+};
+
+void e820_dump(struct e820_entry *entries, uint count)
+{
+	int i;
+
+	printf("%12s  %10s  %s\n", "Addr", "Size", "Type");
+	for (i = 0; i < count; i++) {
+		struct e820_entry *entry = &entries[i];
+
+		printf("%12llx  %10llx  %s\n", entry->addr, entry->size,
+		       entry->type < E820_COUNT ?
+		       e820_type_name[entry->type] :
+		       simple_itoa(entry->type));
+	}
+}
+
 /*
  * Install a default e820 table with 4 entries as follows:
  *
@@ -37,6 +63,50 @@ __weak unsigned int install_e820_map(unsigned int max_entries,
 	return 4;
 }
 
+void e820_init(struct e820_ctx *ctx, struct e820_entry *entries,
+	       int max_entries)
+{
+	memset(ctx, '\0', sizeof(*ctx));
+	ctx->entries = entries;
+	ctx->max_entries = max_entries;
+}
+
+void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size)
+{
+	struct e820_entry *entry = &ctx->entries[ctx->count++];
+
+	if (ctx->count <= ctx->max_entries) {
+		entry->addr = addr;
+		entry->size = size;
+		entry->type = type;
+	}
+	ctx->addr = addr + size;
+}
+
+void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size)
+{
+	e820_add(ctx, type, ctx->addr, size);
+}
+
+void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 addr)
+{
+	e820_next(ctx, type, addr - ctx->addr);
+}
+
+int e820_finish(struct e820_ctx *ctx)
+{
+	if (ctx->count > ctx->max_entries) {
+		printf("e820 has %d entries but room for only %d\n", ctx->count,
+		       ctx->max_entries);
+		panic("e820 table too large");
+	}
+	log_debug("e820 map installed, n=%d\n", ctx->count);
+	if (_DEBUG)
+		e820_dump(ctx->entries, ctx->count);
+
+	return ctx->count;
+}
+
 #if CONFIG_IS_ENABLED(EFI_LOADER)
 void efi_add_known_memory(void)
 {
diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c
index 465ff70146f..088f78f4661 100644
--- a/arch/x86/lib/i8259.c
+++ b/arch/x86/lib/i8259.c
@@ -13,6 +13,8 @@
  * Programmable Interrupt Controllers.
  */
 
+#define LOG_CATEGORY	UCLASS_IRQ
+
 #include <log.h>
 #include <asm/io.h>
 #include <asm/i8259.h>
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 7a033505101..0a6a761987e 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -84,8 +84,6 @@ static int x86_spl_init(void)
 	log_debug("x86 spl starting\n");
 	if (IS_ENABLED(TPL))
 		ret = x86_cpu_reinit_f();
-	else
-		ret = x86_cpu_init_f();
 	ret = spl_init();
 	if (ret) {
 		log_debug("spl_init() failed (err=%d)\n", ret);
@@ -283,7 +281,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	int ret;
 
-	printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
+	log_debug("Jumping to 64-bit U-Boot\n");
 	ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
 	debug("ret=%d\n", ret);
 	hang();
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 44fe80c5224..ec52992209f 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -45,6 +45,13 @@ struct table_info {
 	int align;
 };
 
+/* QEMU's tables include quite a bit of empty space */
+#ifdef CONFIG_QEMU
+#define ACPI_SIZE	(192 << 10)
+#else
+#define ACPI_SIZE	SZ_64K
+#endif
+
 static struct table_info table_list[] = {
 #ifdef CONFIG_GENERATE_PIRQ_TABLE
 	{ "pirq", write_pirq_routing_table },
@@ -60,7 +67,7 @@ static struct table_info table_list[] = {
 	 * that the calculation of gd->table_end works properly
 	 */
 #ifdef CONFIG_GENERATE_ACPI_TABLE
-	{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, SZ_64K, SZ_4K},
+	{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, ACPI_SIZE, SZ_4K},
 #endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
 	/*
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index ba7a008fec7..2ea9bcf59c2 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -55,6 +55,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define COMMAND_LINE_SIZE	2048
 
+/* Current state of the boot */
+struct zboot_state state;
+
 static void build_command_line(char *command_line, int auto_boot)
 {
 	char *env_command_line;
@@ -222,7 +225,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 	else
 		*load_addressp = ZIMAGE_LOAD_ADDR;
 
-	printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
+	printf("Building boot_params at %lx\n", (ulong)setup_base);
 	memset(setup_base, 0, sizeof(*setup_base));
 	setup_base->hdr = params->hdr;
 
@@ -298,10 +301,13 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		hdr->type_of_loader = 0x80;	/* U-Boot version 0 */
 		if (initrd_addr) {
 			printf("Initial RAM disk at linear address "
-			       "0x%08lx, size %ld bytes\n",
-			       initrd_addr, initrd_size);
+			       "%lx, size %lx (%ld bytes)\n",
+			       initrd_addr, initrd_size, initrd_size);
 
 			hdr->ramdisk_image = initrd_addr;
+			setup_base->ext_ramdisk_image = 0;
+			setup_base->ext_ramdisk_size = 0;
+			setup_base->ext_cmd_line_ptr = 0;
 			hdr->ramdisk_size = initrd_size;
 		}
 	}
@@ -363,55 +369,54 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 	return 0;
 }
 
-int zboot_load(struct bootm_info *bmi)
+int zboot_load(void)
 {
 	struct boot_params *base_ptr;
 	int ret;
 
-	if (bmi->base_ptr) {
-		struct boot_params *from = (struct boot_params *)bmi->base_ptr;
+	if (state.base_ptr) {
+		struct boot_params *from = (struct boot_params *)state.base_ptr;
 
 		base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE;
-		log_debug("Building boot_params at 0x%8.8lx\n",
-			  (ulong)base_ptr);
+		log_debug("Building boot_params at %lx\n", (ulong)base_ptr);
 		memset(base_ptr, '\0', sizeof(*base_ptr));
 		base_ptr->hdr = from->hdr;
 	} else {
-		base_ptr = load_zimage((void *)bmi->bzimage_addr,
-				       bmi->bzimage_size, &bmi->load_address);
+		base_ptr = load_zimage((void *)state.bzimage_addr, state.bzimage_size,
+				       &state.load_address);
 		if (!base_ptr) {
 			puts("## Kernel loading failed ...\n");
 			return -EINVAL;
 		}
 	}
-	bmi->base_ptr = base_ptr;
+	state.base_ptr = base_ptr;
 
-	ret = env_set_hex("zbootbase", map_to_sysmem(bmi->base_ptr));
+	ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr));
 	if (!ret)
-		ret = env_set_hex("zbootaddr", bmi->load_address);
+		ret = env_set_hex("zbootaddr", state.load_address);
 	if (ret)
 		return ret;
 
 	return 0;
 }
 
-int zboot_setup(struct bootm_info *bmi)
+int zboot_setup(void)
 {
-	struct boot_params *base_ptr = bmi->base_ptr;
+	struct boot_params *base_ptr = state.base_ptr;
 	int ret;
 
 	ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
-			   0, bmi->initrd_addr, bmi->initrd_size,
-			   (ulong)bmi->cmdline);
+			   0, state.initrd_addr, state.initrd_size,
+			   (ulong)state.cmdline);
 	if (ret)
 		return -EINVAL;
 
 	return 0;
 }
 
-int zboot_go(struct bootm_info *bmi)
+int zboot_go(void)
 {
-	struct boot_params *params = bmi->base_ptr;
+	struct boot_params *params = state.base_ptr;
 	struct setup_header *hdr = &params->hdr;
 	bool image_64bit;
 	ulong entry;
@@ -419,51 +424,38 @@ int zboot_go(struct bootm_info *bmi)
 
 	disable_interrupts();
 
-	entry = bmi->load_address;
+	entry = state.load_address;
 	image_64bit = false;
-	if (IS_ENABLED(CONFIG_X86_RUN_64BIT) &&
+	if (IS_ENABLED(CONFIG_X86_64) &&
 	    (hdr->xloadflags & XLF_KERNEL_64)) {
 		image_64bit = true;
 	}
 
 	/* we assume that the kernel is in place */
-	ret = boot_linux_kernel((ulong)bmi->base_ptr, entry, image_64bit);
+	ret = boot_linux_kernel((ulong)state.base_ptr, entry, image_64bit);
 
 	return ret;
 }
 
-int zboot_run(struct bootm_info *bmi)
+int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+	      ulong base, char *cmdline)
 {
 	int ret;
 
-	ret = zboot_load(bmi);
+	zboot_start(addr, size, initrd, initrd_size, base, cmdline);
+	ret = zboot_load();
 	if (ret)
 		return log_msg_ret("ld", ret);
-	ret = zboot_setup(bmi);
+	ret = zboot_setup();
 	if (ret)
 		return log_msg_ret("set", ret);
-	ret = zboot_go(bmi);
+	ret = zboot_go();
 	if (ret)
 		return log_msg_ret("go", ret);
 
 	return -EFAULT;
 }
 
-int zboot_run_args(ulong addr, ulong size, ulong initrd, ulong initrd_size,
-		   ulong base, char *cmdline)
-{
-	struct bootm_info bmi;
-	int ret;
-
-	bootm_init(&bmi);
-	zboot_start(&bmi, addr, size, initrd, initrd_size, base, cmdline);
-	ret = zboot_run(&bmi);
-	if (ret)
-		return log_msg_ret("zra", ret);
-
-	return 0;
-}
-
 static void print_num(const char *name, ulong value)
 {
 	printf("%-20s: %lx\n", name, value);
@@ -474,14 +466,6 @@ static void print_num64(const char *name, u64 value)
 	printf("%-20s: %llx\n", name, value);
 }
 
-static const char *const e820_type_name[E820_COUNT] = {
-	[E820_RAM] = "RAM",
-	[E820_RESERVED] = "Reserved",
-	[E820_ACPI] = "ACPI",
-	[E820_NVS] = "ACPI NVS",
-	[E820_UNUSABLE] = "Unusable",
-};
-
 static const char *const bootloader_id[] = {
 	"LILO",
 	"Loadlin",
@@ -565,28 +549,17 @@ static void show_loader(struct setup_header *hdr)
 	printf("\n");
 }
 
-void zimage_dump(struct bootm_info *bmi, bool show_cmdline)
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline)
 {
-	struct boot_params *base_ptr;
 	struct setup_header *hdr;
-	int i;
+	const char *version;
 
-	base_ptr = bmi->base_ptr;
 	printf("Setup located at %p:\n\n", base_ptr);
 	print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
 
 	printf("E820: %d entries\n", base_ptr->e820_entries);
-	if (base_ptr->e820_entries) {
-		printf("%12s  %10s  %s\n", "Addr", "Size", "Type");
-		for (i = 0; i < base_ptr->e820_entries; i++) {
-			struct e820_entry *entry = &base_ptr->e820_map[i];
-
-			printf("%12llx  %10llx  %s\n", entry->addr, entry->size,
-			       entry->type < E820_COUNT ?
-			       e820_type_name[entry->type] :
-			       simple_itoa(entry->type));
-		}
-	}
+	if (base_ptr->e820_entries)
+		e820_dump(base_ptr->e820_map, base_ptr->e820_entries);
 
 	hdr = &base_ptr->hdr;
 	print_num("Setup sectors", hdr->setup_sects);
@@ -606,14 +579,10 @@ void zimage_dump(struct bootm_info *bmi, bool show_cmdline)
 	print_num("Real mode switch", hdr->realmode_swtch);
 	print_num("Start sys seg", hdr->start_sys_seg);
 	print_num("Kernel version", hdr->kernel_version);
-	if (bmi->bzimage_addr) {
-		const char *version;
-
-		version = zimage_get_kernel_version(base_ptr,
-						    (void *)bmi->bzimage_addr);
-		if (version)
-			printf("   @%p: %s\n", version, version);
-	}
+	version = zimage_get_kernel_version(base_ptr,
+					    (void *)state.bzimage_addr);
+	if (version)
+		printf("   @%p: %s\n", version, version);
 	print_num("Type of loader", hdr->type_of_loader);
 	show_loader(hdr);
 	print_num("Load flags", hdr->loadflags);
@@ -654,24 +623,25 @@ void zimage_dump(struct bootm_info *bmi, bool show_cmdline)
 		print_num("Kernel info offset", hdr->kernel_info_offset);
 }
 
-void zboot_start(struct bootm_info *bmi, ulong bzimage_addr, ulong bzimage_size,
-		 ulong initrd_addr, ulong initrd_size, ulong base_addr,
-		 const char *cmdline)
+void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
+		 ulong initrd_size, ulong base_addr, const char *cmdline)
 {
-	bmi->bzimage_size = bzimage_size;
-	bmi->initrd_addr = initrd_addr;
-	bmi->initrd_size = initrd_size;
+	memset(&state, '\0', sizeof(state));
+
+	state.bzimage_size = bzimage_size;
+	state.initrd_addr = initrd_addr;
+	state.initrd_size = initrd_size;
 	if (base_addr) {
-		bmi->base_ptr = map_sysmem(base_addr, 0);
-		bmi->load_address = bzimage_addr;
+		state.base_ptr = map_sysmem(base_addr, 0);
+		state.load_address = bzimage_addr;
 	} else {
-		bmi->bzimage_addr = bzimage_addr;
+		state.bzimage_addr = bzimage_addr;
 	}
-	bmi->cmdline = cmdline;
+	state.cmdline = cmdline;
 }
 
-void zboot_info(struct bootm_info *bmi)
+void zboot_info(void)
 {
 	printf("Kernel loaded at %08lx, setup_base=%p\n",
-	       bmi->load_address, bmi->base_ptr);
+	       state.load_address, state.base_ptr);
 }
diff --git a/board/airoha/an7581/MAINTAINERS b/board/airoha/an7581/MAINTAINERS
new file mode 100644
index 00000000000..28ec2fbf2ea
--- /dev/null
+++ b/board/airoha/an7581/MAINTAINERS
@@ -0,0 +1,5 @@
+AN7581
+M:	Christian Marangi <ansuelsmth@gmail.com>
+S:	Maintained
+N:      airoha
+N:      an7581
diff --git a/board/airoha/an7581/Makefile b/board/airoha/an7581/Makefile
new file mode 100644
index 00000000000..70f8db7bce9
--- /dev/null
+++ b/board/airoha/an7581/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= an7581_rfb.o
diff --git a/board/airoha/an7581/an7581_rfb.c b/board/airoha/an7581/an7581_rfb.c
new file mode 100644
index 00000000000..aa73679d929
--- /dev/null
+++ b/board/airoha/an7581/an7581_rfb.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12013aa5a4d..93ee5b7ee0c 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -100,9 +100,6 @@ void board_init_f(ulong dummy)
 	int ret;
 
 	arch_cpu_init();
-
-	init_uart_clk(1);
-
 	timer_init();
 
 	/* Clear the BSS. */
@@ -114,8 +111,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	preloader_console_init();
-
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
@@ -124,6 +119,7 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
 	enable_tzc380();
 
 	power_init_board();
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index f03841e5a01..e91d3fdcf5e 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -111,8 +111,6 @@ int board_early_init_f(void)
 	/* Claiming pwm pins prevents LCD flicker during startup*/
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
-	init_uart_clk(1);
-
 	return 0;
 }
 
diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 30d577f7e0e..027fae38278 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -50,7 +50,7 @@ void spl_board_init(void)
 	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
 	 * set by ROM for ND VDD_SOC
 	 */
-	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
+	if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
 		clock_enable(CCGR_GIC, 0);
 		clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
 		clock_enable(CCGR_GIC, 1);
@@ -112,8 +112,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	init_uart_clk(1);
-
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index d97383c030c..5166e7a762d 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -8,3 +8,8 @@ COREBOOT64 BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	configs/coreboot64_defconfig
+
+COREBOOT64 NO SPL
+M:	Jeremy Compostella <jeremy.compostella@intel.com>
+S:	Maintained
+F:	configs/coreboot64-no-spl_defconfig
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 4af3cbe9fe2..4275436b128 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -186,5 +186,7 @@ int board_late_init(void)
 
 enum env_location env_get_location(enum env_operation op, int prio)
 {
-	return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
+	return prio ? ENVL_UNKNOWN : CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH,
+						       (ENVL_SPI_FLASH),
+						       (ENVL_NOWHERE));
 }
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 012ac14a123..134dbfd7151 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -62,6 +62,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply VIDEO_SIMPLE
 	imply PCIE_ECAM_GENERIC
 	imply DM_RNG
+	imply RNG_RISCV_ZKR
 	imply DM_RTC
 	imply RTC_GOLDFISH
 	imply SCSI
diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig
index 728cecae6b3..9ea6303ec9c 100644
--- a/board/emulation/qemu-sbsa/Kconfig
+++ b/board/emulation/qemu-sbsa/Kconfig
@@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAS_ROM
 	select MTD
 	select OF_LIBFDT_OVERLAY
-	select OF_SEPARATE
 	select PCI
 	select PCIE_ECAM_GENERIC
 	select SYS_PCI_64BIT
diff --git a/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
index e45cfd5d8a3..294f78858a7 100644
--- a/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
+++ b/board/libre-computer/aml-a311d-cc/aml-a311d-cc.c
@@ -29,7 +29,7 @@ struct efi_capsule_update_info update_info = {
 #if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
 void set_dfu_alt_info(char *interface, char *devstr)
 {
-	if (strcmp(interface, "ram") == 0)
+	if (interface && strcmp(interface, "ram") == 0)
 		env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
 	else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
 		env_set("dfu_alt_info", update_info.dfu_string);
diff --git a/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
index 94cf5b4361f..1ec9a5b401e 100644
--- a/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
+++ b/board/libre-computer/aml-s805x-ac/aml-s805x-ac.c
@@ -36,7 +36,7 @@ struct efi_capsule_update_info update_info = {
 #if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
 void set_dfu_alt_info(char *interface, char *devstr)
 {
-	if (strcmp(interface, "ram") == 0)
+	if (interface && strcmp(interface, "ram") == 0)
 		env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
 	else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
 		env_set("dfu_alt_info", update_info.dfu_string);
diff --git a/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
index f641db5a494..b552035ee03 100644
--- a/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
+++ b/board/libre-computer/aml-s905d3-cc/aml-s905d3-cc.c
@@ -29,7 +29,7 @@ struct efi_capsule_update_info update_info = {
 #if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
 void set_dfu_alt_info(char *interface, char *devstr)
 {
-	if (strcmp(interface, "ram") == 0)
+	if (interface && strcmp(interface, "ram") == 0)
 		env_set("dfu_alt_info", "fitimage ram 0x08080000 0x4000000");
 	else if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
 		env_set("dfu_alt_info", update_info.dfu_string);
diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig
index 21da1dc346d..e4bd8903aab 100644
--- a/board/openpiton/riscv64/Kconfig
+++ b/board/openpiton/riscv64/Kconfig
@@ -35,6 +35,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply SPL_SMP
 	imply SPL_MMC
 	imply SMP
-	imply SPL_RISCV_MMODE
 
 endif
diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig
new file mode 100644
index 00000000000..6bab40ce933
--- /dev/null
+++ b/board/ouya/ouya/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OUYA
+
+config SYS_BOARD
+	default "ouya"
+
+config SYS_VENDOR
+	default "ouya"
+
+config SYS_CONFIG_NAME
+	default "ouya"
+
+endif
diff --git a/board/ouya/ouya/MAINTAINERS b/board/ouya/ouya/MAINTAINERS
new file mode 100644
index 00000000000..7f664b2e65f
--- /dev/null
+++ b/board/ouya/ouya/MAINTAINERS
@@ -0,0 +1,8 @@
+OUYA BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+M:	Peter Geis <pgwipeout@gmail.com>
+S:	Maintained
+F:	board/ouya/ouya/
+F:	configs/ouya_defconfig
+F:	doc/board/ouya/ouya.rst
+F:	include/configs/ouya.h
diff --git a/board/ouya/ouya/Makefile b/board/ouya/ouya/Makefile
new file mode 100644
index 00000000000..d479ec83e5e
--- /dev/null
+++ b/board/ouya/ouya/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#  (C) Copyright 2021
+#  Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_XPL_BUILD) += ouya-spl.o
+
+obj-y += ouya.o
diff --git a/board/ouya/ouya/ouya-spl.c b/board/ouya/ouya/ouya-spl.c
new file mode 100644
index 00000000000..1f45853c8be
--- /dev/null
+++ b/board/ouya/ouya/ouya-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  T30 Ouya SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR		(0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR		(0x60 << 1)
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/ouya/ouya/ouya.c b/board/ouya/ouya/ouya.c
new file mode 100644
index 00000000000..6d6eb54afe2
--- /dev/null
+++ b/board/ouya/ouya/ouya.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <fdt_support.h>
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Remove TrustZone nodes */
+	fdt_del_node_and_alias(blob, "/firmware");
+	fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+	return 0;
+}
+#endif
diff --git a/board/ouya/ouya/ouya.env b/board/ouya/ouya/ouya.env
new file mode 100644
index 00000000000..6ec881b910a
--- /dev/null
+++ b/board/ouya/ouya/ouya.env
@@ -0,0 +1,12 @@
+#include <env/nvidia/prod_upd.env>
+
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_interface=usb
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index bdf9e97beaa..caf9cb0c3c3 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -45,7 +45,6 @@ config PHYCORE_IMX8MP_RAM_SIZE_4GB
 
 config PHYCORE_IMX8MP_RAM_SIZE_8GB
 	bool "8GB RAM"
-	select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
 	help
 	  Set RAM size fix to 8GB for phyCORE-i.MX8MP.
 	  Only 2GHz RAMs are supported.
@@ -54,7 +53,6 @@ endchoice
 
 config PHYCORE_IMX8MP_RAM_FREQ_FIX
 	bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
-	default false
 	help
 	  RAM frequency is automatic being detected with the help of
 	  the EEPROM introspection data. Set RAM frequency to a fix value
diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile
index 347be5cc93c..5e51b691178 100644
--- a/board/renesas/common/Makefile
+++ b/board/renesas/common/Makefile
@@ -1,6 +1,4 @@
 #
-# board/renesas/whitehawk/Makefile
-#
 # Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
 #
 # SPDX-License-Identifier: GPL-2.0+
diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c
index 52a0639073b..f7d129be4c8 100644
--- a/board/renesas/common/gen4-common.c
+++ b/board/renesas/common/gen4-common.c
@@ -7,11 +7,13 @@
 
 #include <asm/arch/renesas.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/processor.h>
 #include <asm/system.h>
+#include <image.h>
 #include <linux/errno.h>
 
 #define RST_BASE	0xE6160000 /* Domain0 */
@@ -88,3 +90,127 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	return 0;
 }
+
+/* R-Car Gen4 TFA BL31 handoff structure and handling. */
+struct param_header {
+	u8			type;
+	u8			version;
+	u16			size;
+	u32			attr;
+};
+
+struct tfa_image_info {
+	struct param_header	h;
+	uintptr_t		image_base;
+	u32			image_size;
+	u32			image_max_size;
+};
+
+struct aapcs64_params {
+	u64			arg0;
+	u64			arg1;
+	u64			arg2;
+	u64			arg3;
+	u64			arg4;
+	u64			arg5;
+	u64			arg6;
+	u64			arg7;
+};
+
+struct entry_point_info {
+	struct param_header	h;
+	uintptr_t		pc;
+	u32			spsr;
+	struct aapcs64_params	args;
+};
+
+struct bl2_to_bl31_params_mem {
+	struct tfa_image_info	bl32_image_info;
+	struct tfa_image_info	bl33_image_info;
+	struct entry_point_info	bl33_ep_info;
+	struct entry_point_info	bl32_ep_info;
+};
+
+/* Default jump address, return to U-Boot */
+#define BL33_BASE	0x44100000
+/* Custom parameters address passed to TFA by ICUMXA loader */
+#define PARAMS_BASE	0x46422200
+
+/* Usually such a structure is produced by ICUMXA and passed in at 0x46422200 */
+static const struct bl2_to_bl31_params_mem blinfo_template = {
+	.bl33_ep_info.h.type = 1,	/* PARAM_EP */
+	.bl33_ep_info.h.version = 2,	/* Version 2 */
+	.bl33_ep_info.h.size = sizeof(struct entry_point_info),
+	.bl33_ep_info.h.attr = 0x81,	/* Executable | Non-Secure */
+	.bl33_ep_info.spsr = 0x2c9,	/* Mode=EL2, SP=ELX, Exceptions=OFF */
+	.bl33_ep_info.pc = BL33_BASE,
+
+	.bl33_image_info.h.type = 1,	/* PARAM_EP */
+	.bl33_image_info.h.version = 2,	/* Version 2 */
+	.bl33_image_info.h.size = sizeof(struct image_info),
+	.bl33_image_info.h.attr = 0,
+	.bl33_image_info.image_base = BL33_BASE,
+};
+
+static bool tfa_bl31_image_loaded;
+static ulong tfa_bl31_image_addr;
+
+static void tfa_bl31_image_process(ulong image, size_t size)
+{
+	/* Custom parameters address passed to TFA by ICUMXA loader */
+	struct bl2_to_bl31_params_mem *blinfo = (struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+	/* Not in EL3, do nothing. */
+	if (current_el() != 3)
+		return;
+
+	/* Clear a page and copy template */
+	memset((void *)PARAMS_BASE, 0, PAGE_SIZE);
+	memcpy(blinfo, &blinfo_template, sizeof(*blinfo));
+	tfa_bl31_image_addr = image;
+	tfa_bl31_image_loaded = true;
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TFA_BL31, tfa_bl31_image_process);
+
+void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr,
+			      u64 arg4, u64 entry_point, u64 es_flag)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)(void *)tfa_bl31_image_addr;
+	struct bl2_to_bl31_params_mem *blinfo =
+		(struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+	/* Not in EL3, do nothing. */
+	if (current_el() != 3)
+		return;
+
+	/*
+	 * Destination address in arch/arm/cpu/armv8/transition.S
+	 * right past the first bl in armv8_switch_to_el2() to let
+	 * the rest of U-Boot pre-Linux code run. The code does run
+	 * without stack pointer!
+	 */
+	const u64 ep = ((u64)(uintptr_t)&armv8_switch_to_el2) + 4;
+
+	/* If TFA BL31 was not part of the fitImage, do regular boot. */
+	if (!tfa_bl31_image_loaded)
+		return;
+
+	/*
+	 * Set up kernel entry point and parameters:
+	 * x0 is FDT address, x1..x3 must be 0
+	 */
+	blinfo->bl33_ep_info.pc = ep;
+	blinfo->bl33_ep_info.args.arg0 = args;
+	blinfo->bl33_ep_info.args.arg1 = mach_nr;
+	blinfo->bl33_ep_info.args.arg2 = fdt_addr;
+	blinfo->bl33_ep_info.args.arg3 = arg4;
+	blinfo->bl33_ep_info.args.arg4 = entry_point;
+	blinfo->bl33_ep_info.args.arg5 = es_flag;
+	blinfo->bl33_image_info.image_base = ep;
+
+	/* Jump to TFA BL31 */
+	image_entry();
+}
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c
index e46ef0a3075..ebfefab7253 100644
--- a/board/renesas/common/gen4-spl.c
+++ b/board/renesas/common/gen4-spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R-Car Gen4 Cortex-R52 SPL
+ * R-Car Gen4 SPL
  *
  * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
  */
diff --git a/board/starfive/visionfive2/Kconfig b/board/starfive/visionfive2/Kconfig
index d7e8a7a7d78..2186a939646 100644
--- a/board/starfive/visionfive2/Kconfig
+++ b/board/starfive/visionfive2/Kconfig
@@ -50,13 +50,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply PHY_LIB
 	imply PHY_MSCC
 
-config STARFIVE_NO_EMMC
-	bool "Report eMMC size as zero"
-	help
-	  The serial number string in the EEPROM is meant to report the
-	  size of onboard eMMC. Unfortunately some Milk-V Mars CM Lite
-	  modules without eMMC show a non-zero size here.
-
-	  Set to 'Y' if you have a Mars CM Lite module.
-
 endif
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 1538d6aec73..3e4d3e21988 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -121,6 +121,10 @@ int board_fit_config_name_match(const char *name)
 
 	product_id = get_product_id_from_eeprom();
 
+	/* Strip off prefix */
+	if (strncmp(name, "starfive/", 9))
+		return -EINVAL;
+	name += 9;
 	if (!strncmp(product_id, "VF7110", 6)) {
 		version = get_pcb_revision_from_eeprom();
 		if ((version == 'b' || version == 'B') &&
@@ -133,14 +137,6 @@ int board_fit_config_name_match(const char *name)
 	} else if (!strncmp(product_id, "MARS", 4) &&
 		   !strcmp(name, "jh7110-milkv-mars")) {
 		return 0;
-	} else if (!strncmp(product_id, "MARC", 4)) {
-		if (!get_mmc_size_from_eeprom()) {
-			if (!strcmp(name, "jh7110-milkv-mars-cm-lite"))
-				return 0;
-		} else {
-			if (!strcmp(name, "jh7110-milkv-mars-cm"))
-				return 0;
-		}
 	} else if (!strncmp(product_id, "STAR64", 6) &&
 		   !strcmp(name, "jh7110-pine64-star64")) {
 		return 0;
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 3940d45b13f..b8cd509bc89 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define JH7110_L2_PREFETCHER_HART_OFFSET	0x2000
 #define FDTFILE_MILK_V_MARS \
 	"starfive/jh7110-milkv-mars.dtb"
-#define FDTFILE_MILK_V_MARS_CM \
-	"starfive/jh7110-milkv-mars-cm.dtb"
-#define FDTFILE_MILK_V_MARS_CM_LITE \
-	"starfive/jh7110-milkv-mars-cm-lite.dtb"
 #define FDTFILE_VISIONFIVE2_1_2A \
 	"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
 #define FDTFILE_VISIONFIVE2_1_3B \
@@ -67,12 +63,7 @@ static void set_fdtfile(void)
 		log_err("Can't read EEPROM\n");
 		return;
 	}
-	if (!strncmp(product_id, "MARC", 4)) {
-		if (get_mmc_size_from_eeprom())
-			fdtfile = FDTFILE_MILK_V_MARS_CM;
-		else
-			fdtfile = FDTFILE_MILK_V_MARS_CM_LITE;
-	} else if (!strncmp(product_id, "MARS", 4)) {
+	if (!strncmp(product_id, "MARS", 4)) {
 		fdtfile = FDTFILE_MILK_V_MARS;
 	} else if (!strncmp(product_id, "VF7110", 6)) {
 		version = get_pcb_revision_from_eeprom();
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
index 838f41e41bd..010e386e64d 100644
--- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -573,9 +573,6 @@ u32 get_mmc_size_from_eeprom(void)
 {
 	u32 size;
 
-	if (IS_ENABLED(CONFIG_STARFIVE_NO_EMMC))
-		return 0;
-
 	if (read_eeprom())
 		return 0;
 
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index c7a2205ed61..ac9cefc6eac 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -563,7 +563,8 @@ void sunxi_board_init(void)
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
 	defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
 	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
-	defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER
+	defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER || \
+	defined CONFIG_AXP803_POWER
 	power_failed = axp_init();
 
 	if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
@@ -581,6 +582,8 @@ void sunxi_board_init(void)
 #endif
 #ifdef CONFIG_AXP_DCDC2_VOLT
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+#endif
+#ifdef CONFIG_AXP_DCDC3_VOLT
 	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
 #endif
 #ifdef CONFIG_AXP_DCDC4_VOLT
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 774ef7ac5e3..f738cba7bd1 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -955,7 +955,8 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 		return 0;
-	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+	else if (board_is_bone_lt() && !board_is_bbg1() &&
+		 !strcmp(name, "am335x-boneblack"))
 		return 0;
 	else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 		return 0;
diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml
index dc445a4b72f..73da85eeade 100644
--- a/board/ti/am62px/rm-cfg.yaml
+++ b/board/ti/am62px/rm-cfg.yaml
@@ -244,7 +244,7 @@ rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 1048
+            resasg_entries_size: 1112
             reserved: 0
     resasg_entries:
         -
@@ -303,31 +303,55 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 0
+            num_resource: 2
+            type: 1676
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1676
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1676
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 3
+            num_resource: 1
+            type: 1676
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4
             num_resource: 18
             type: 1677
             host_id: 12
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1677
             host_id: 35
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1677
             host_id: 36
             reserved: 0
         -
-            start_resource: 24
+            start_resource: 28
             num_resource: 2
             type: 1677
             host_id: 30
             reserved: 0
         -
-            start_resource: 26
-            num_resource: 6
+            start_resource: 30
+            num_resource: 2
             type: 1677
             host_id: 128
             reserved: 0
@@ -387,31 +411,55 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 0
+            num_resource: 2
+            type: 1695
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 3
+            num_resource: 1
+            type: 1695
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4
             num_resource: 18
             type: 1696
             host_id: 12
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1696
             host_id: 35
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1696
             host_id: 36
             reserved: 0
         -
-            start_resource: 24
+            start_resource: 28
             num_resource: 2
             type: 1696
             host_id: 30
             reserved: 0
         -
-            start_resource: 26
-            num_resource: 6
+            start_resource: 30
+            num_resource: 2
             type: 1696
             host_id: 128
             reserved: 0
diff --git a/board/ti/j7200/Kconfig b/board/ti/j7200/Kconfig
new file mode 100644
index 00000000000..093d23e7bf8
--- /dev/null
+++ b/board/ti/j7200/Kconfig
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+if TARGET_J7200_A72_EVM
+
+config SYS_BOARD
+       default "j7200"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config ENV_SOURCE_FILE
+       default "j7200"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J7200_R5_EVM
+
+config SYS_BOARD
+       default "j7200"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config ENV_SOURCE_FILE
+       default "j7200"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j7200/MAINTAINERS b/board/ti/j7200/MAINTAINERS
new file mode 100644
index 00000000000..626141367a5
--- /dev/null
+++ b/board/ti/j7200/MAINTAINERS
@@ -0,0 +1,7 @@
+J7200 BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/j7200
+F:	include/configs/j7200_evm.h
+F:	configs/j7200_evm_r5_defconfig
+F:	configs/j7200_evm_a72_defconfig
diff --git a/board/ti/j7200/Makefile b/board/ti/j7200/Makefile
new file mode 100644
index 00000000000..4ae69aaea7b
--- /dev/null
+++ b/board/ti/j7200/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += ../j721e/evm.o
diff --git a/board/ti/j721e/board-cfg_j7200.yaml b/board/ti/j7200/board-cfg.yaml
index a1e55a26be5..a1e55a26be5 100644
--- a/board/ti/j721e/board-cfg_j7200.yaml
+++ b/board/ti/j7200/board-cfg.yaml
diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env
new file mode 100644
index 00000000000..6cc92bf0d8d
--- /dev/null
+++ b/board/ti/j7200/j7200.env
@@ -0,0 +1,40 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
+
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000
+	${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+#if CONFIG_TARGET_J7200_R5_EVM
+addr_mcur5f0_0load=0x89000000
+name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
+#endif
+
+boot_targets=mmc1 mmc0 usb pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
+#if CONFIG_TARGET_J7200_A72_EVM
+do_main_cpsw0_qsgmii_phyinit=1
+init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
+	gpio clear gpio@22_16
+main_cpsw0_qsgmii_phyinit=
+	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then
+		run init_main_cpsw0_qsgmii_phy;
+	fi;
+#endif
+
+#if CONFIG_TARGET_J7200_A72_EVM
+rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
+#endif
diff --git a/board/ti/j721e/pm-cfg_j7200.yaml b/board/ti/j7200/pm-cfg.yaml
index 85cd2c9dbca..85cd2c9dbca 100644
--- a/board/ti/j721e/pm-cfg_j7200.yaml
+++ b/board/ti/j7200/pm-cfg.yaml
diff --git a/board/ti/j721e/rm-cfg_j7200.yaml b/board/ti/j7200/rm-cfg.yaml
index f83184bbfc0..f83184bbfc0 100644
--- a/board/ti/j721e/rm-cfg_j7200.yaml
+++ b/board/ti/j7200/rm-cfg.yaml
diff --git a/board/ti/j721e/sec-cfg_j7200.yaml b/board/ti/j7200/sec-cfg.yaml
index 4726ac24a38..4726ac24a38 100644
--- a/board/ti/j721e/sec-cfg_j7200.yaml
+++ b/board/ti/j7200/sec-cfg.yaml
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 6990f6ef4a4..7c7e23988d8 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -38,39 +38,3 @@ config ENV_SOURCE_FILE
 source "board/ti/common/Kconfig"
 
 endif
-
-if TARGET_J7200_A72_EVM
-
-config SYS_BOARD
-       default "j721e"
-
-config SYS_VENDOR
-       default "ti"
-
-config SYS_CONFIG_NAME
-       default "j721e_evm"
-
-config ENV_SOURCE_FILE
-       default "j721e"
-
-source "board/ti/common/Kconfig"
-
-endif
-
-if TARGET_J7200_R5_EVM
-
-config SYS_BOARD
-       default "j721e"
-
-config SYS_VENDOR
-       default "ti"
-
-config SYS_CONFIG_NAME
-       default "j721e_evm"
-
-config ENV_SOURCE_FILE
-       default "j721e"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS
index 06aba53d9b0..19199dbeadd 100644
--- a/board/ti/j721e/MAINTAINERS
+++ b/board/ti/j721e/MAINTAINERS
@@ -7,5 +7,3 @@ F:	configs/j721e_evm_r5_defconfig
 F:	configs/j721e_evm_a72_defconfig
 F:	configs/j721e_sk_r5_defconfig
 F:	configs/j721e_sk_a72_defconfig
-F:	configs/j7200_evm_r5_defconfig
-F:	configs/j7200_evm_a72_defconfig
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 38bfd7d4963..e5b4225b3ce 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -16,9 +16,6 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 #if CONFIG_TARGET_J721E_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
-#elif CONFIG_TARGET_J7200_R5_EVM
-addr_mcur5f0_0load=0x89000000
-name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
 #endif
 
 boot_targets=mmc1 mmc0 usb pxe dhcp
@@ -28,15 +25,7 @@ bootpart=1:2
 bootdir=/boot
 rd_spec=-
 
-#if CONFIG_TARGET_J7200_A72_EVM
-do_main_cpsw0_qsgmii_phyinit=1
-init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
-	gpio clear gpio@22_16
-main_cpsw0_qsgmii_phyinit=
-	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then
-		run init_main_cpsw0_qsgmii_phy;
-	fi;
-#elif CONFIG_TARGET_J721E_A72_EVM
+#if CONFIG_TARGET_J721E_A72_EVM
 init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
 	gpio clear gpio@22_16
 main_cpsw0_qsgmii_phyinit=
@@ -51,7 +40,3 @@ main_cpsw0_qsgmii_phyinit=
 #if CONFIG_TARGET_J721E_A72_EVM
 rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw
 #endif
-
-#if CONFIG_TARGET_J7200_A72_EVM
-rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
-#endif
diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig
index 490c7be66b3..de95ac575d7 100644
--- a/board/ti/j784s4/Kconfig
+++ b/board/ti/j784s4/Kconfig
@@ -35,3 +35,36 @@ config SPL_LDSCRIPT
 source "board/ti/common/Kconfig"
 
 endif
+
+if TARGET_J742S2_A72_EVM
+
+config SYS_BOARD
+       default "j784s4"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j784s4_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J742S2_R5_EVM
+
+config SYS_BOARD
+       default "j784s4"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j784s4_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
index e92e8d03cb3..b289c639f3f 100644
--- a/board/ti/j784s4/MAINTAINERS
+++ b/board/ti/j784s4/MAINTAINERS
@@ -20,3 +20,13 @@ F:	arch/arm/dts/k3-am69-sk-u-boot.dtsi
 F:	arch/arm/dts/k3-am69-r5-sk.dts
 F:	configs/am69_sk_r5_defconfig
 F:	configs/am69_sk_a72_defconfig
+
+J742S2 EVM BOARD
+M:	Manorit Chawdhry <m-chawdhry@ti.com>
+S:	Maintained
+F:	arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
+F:	arch/arm/dts/k3-j742s2-r5-evm.dts
+F:	arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
+F:	arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
+F:	configs/j742s2_evm_r5_defconfig
+F:	configs/j742s2_evm_a72_defconfig
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
index f5b72c7505e..9e1741be424 100644
--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -20,4 +20,8 @@ bootpart=1:2
 bootdir=/boot
 rd_spec=-
 
+#if CONFIG_TARGET_J784S4_A72_EVM
 rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw
+#elif CONFIG_TARGET_J742S2_A72_EVM
+rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw
+#endif
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index a1c471111a0..7b2eecbf659 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -112,13 +112,6 @@ int board_late_init(void)
 #define CORE_VOLTAGE			0x80000000
 #define MCU_CTRL_LFXOSC_32K_BYPASS_VAL	BIT(4)
 
-#if IS_ENABLED(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	fixup_memory_node(spl_image);
-}
-#endif
-
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void)
 {
diff --git a/boot/Kconfig b/boot/Kconfig
index c09a98c3233..f101200ba7a 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1436,14 +1436,6 @@ config NAND_BOOT
 	  booted via NAND flash. This is not a must, some SoCs need this,
 	  some not.
 
-config ONENAND_BOOT
-	bool "Support for booting from ONENAND"
-	imply MTD_RAW_NAND
-	help
-	  Enabling this will make a U-Boot binary that is capable of being
-	  booted via ONENAND. This is not a must, some SoCs need this,
-	  some not.
-
 config QSPI_BOOT
 	bool "Support for booting from QSPI flash"
 	help
diff --git a/boot/Makefile b/boot/Makefile
index f1e4444aa0a..34bac26c4e2 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
 
-obj-$(CONFIG_PXE_UTILS) += bootm.o pxe_utils.o
+obj-$(CONFIG_PXE_UTILS) += pxe_utils.o
 
 endif
 
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index c39147940b6..3791ebfcb42 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -168,8 +168,10 @@ int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
 		 */
 
 	/* if there are bootable partitions, scan only those */
-	} else if (iter->first_bootable >= 0 &&
+	} else if ((iter->flags & BOOTFLOWIF_ONLY_BOOTABLE) &&
+		   iter->first_bootable >= 0 &&
 		   (iter->first_bootable ? !info.bootable : iter->part != 1)) {
+		log_debug("Skipping non-bootable partition %d\n", iter->part);
 		return log_msg_ret("boot", -EINVAL);
 	} else {
 		ret = fs_set_blk_dev_with_part(desc, bflow->part);
@@ -577,6 +579,9 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,
 	struct udevice *dev;
 
 	log_debug("next\n");
+	if (iter->cur_label >= 0 && !iter->labels[iter->cur_label])
+		return log_msg_ret("fil", -ENODEV);
+
 	for (dev = NULL; !dev && iter->labels[++iter->cur_label];) {
 		const char *label = iter->labels[iter->cur_label];
 		int ret;
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 58a1afa7a75..4054a966af8 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -942,8 +942,9 @@ int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg)
 	*buf = '\0';
 	if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
 		snprintf(buf, sizeof(buf),
-			 "uart8250,mmio32,%#lx,%dn8", info.addr,
-			 info.baudrate);
+			 "uart8250,%s,%#lx,%dn8",
+			 info.addr_space == SERIAL_ADDRESS_SPACE_IO ? "io" :
+			 "mmio", info.addr, info.baudrate);
 	} else if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_PL01X) {
 		snprintf(buf, sizeof(buf),
 			 "pl011,mmio32,%#lx,%dn8", info.addr,
@@ -954,7 +955,7 @@ int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg)
 	}
 
 	if (!*buf) {
-		printf("Unknown param '%s\n", arg);
+		printf("Unknown param '%s'\n", arg);
 		return -ENOENT;
 	}
 
diff --git a/boot/bootm.c b/boot/bootm.c
index 8a1aac7515f..854ac7ec738 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -146,7 +146,7 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images,
 	/* check image type, for FIT images get FIT kernel node */
 	*os_data = *os_len = 0;
 	buf = map_sysmem(img_addr, 0);
-	switch (genimg_get_format_comp(buf)) {
+	switch (genimg_get_format(buf)) {
 #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)
 	case IMAGE_FORMAT_LEGACY:
 		printf("## Booting kernel from Legacy Image at %08lx ...\n",
@@ -227,9 +227,6 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images,
 		break;
 	}
 #endif
-	case IMAGE_FORMAT_BOOTI:
-		*os_data = img_addr;
-		break;
 	default:
 		bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
 		return -EPROTOTYPE;
@@ -289,35 +286,6 @@ static int bootm_pre_load(const char *addr_str)
 	return ret;
 }
 
-static int found_booti_os(enum image_comp_t comp)
-{
-	images.os.load = images.os.image_start;
-	images.os.type = IH_TYPE_KERNEL;
-	images.os.os = IH_OS_LINUX;
-	images.os.comp = comp;
-	if (IS_ENABLED(CONFIG_RISCV_SMODE))
-		images.os.arch = IH_ARCH_RISCV;
-	else if (IS_ENABLED(CONFIG_ARM64))
-		images.os.arch = IH_ARCH_ARM64;
-
-	log_debug("load %lx start %lx len %lx ep %lx os %x comp %x\n",
-		  images.os.load, images.os.image_start, images.os.image_len,
-		  images.ep, images.os.os, images.os.comp);
-	if (comp != IH_COMP_NONE) {
-		images.os.load = env_get_hex("kernel_comp_addr_r", 0);
-		images.os.image_len = env_get_ulong("kernel_comp_size", 16, 0);
-		if (!images.os.load || !images.os.image_len) {
-			puts("kernel_comp_addr_r or kernel_comp_size is not provided!\n");
-			return -ENOTSUPP;
-		}
-		if (lmb_reserve(images.os.load, images.os.image_len, LMB_NONE)
-		    < 0)
-			return -EXDEV;
-	}
-
-	return 0;
-}
-
 /**
  * bootm_find_os(): Find the OS to boot
  *
@@ -422,28 +390,7 @@ static int bootm_find_os(const char *cmd_name, const char *addr_fit)
 		}
 		break;
 #endif
-	case IMAGE_FORMAT_BOOTI:
-		if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
-			if (found_booti_os(IH_COMP_NONE))
-				return 1;
-			ep_found = true;
-			break;
-		}
-		fallthrough;
 	default:
-		/* any compressed image is probably a booti image */
-		if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
-			int comp;
-
-			comp = image_decomp_type(os_hdr, 2);
-			if (comp != IH_COMP_NONE) {
-				if (found_booti_os(comp))
-					return 1;
-				ep_found = true;
-			}
-			break;
-		}
-
 		puts("ERROR: unknown image format type!\n");
 		return 1;
 	}
@@ -594,7 +541,6 @@ int bootm_find_images(ulong img_addr, const char *conf_ramdisk,
 static int bootm_find_other(ulong img_addr, const char *conf_ramdisk,
 			    const char *conf_fdt)
 {
-	log_debug("find_other type %x os %x\n", images.os.type, images.os.os);
 	if ((images.os.type == IH_TYPE_KERNEL ||
 	     images.os.type == IH_TYPE_KERNEL_NOLOAD ||
 	     images.os.type == IH_TYPE_MULTI) &&
@@ -683,17 +629,15 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress)
 		debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n",
 		      req_size, load, image_len);
 	}
-	log_debug("load_os load %lx image_start %lx image_len %lx\n", load,
-		  image_start, image_len);
 
 	load_buf = map_sysmem(load, 0);
 	image_buf = map_sysmem(os.image_start, image_len);
 	err = image_decomp(os.comp, load, os.image_start, os.type,
-			   load_buf, image_buf, image_len, bootm_len(),
-			   &load_end);
+			   load_buf, image_buf, image_len,
+			   CONFIG_SYS_BOOTM_LEN, &load_end);
 	if (err) {
-		err = handle_decomp_error(os.comp, load_end - load, bootm_len(),
-					  err);
+		err = handle_decomp_error(os.comp, load_end - load,
+					  CONFIG_SYS_BOOTM_LEN, err);
 		bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
 		return err;
 	}
@@ -1166,10 +1110,6 @@ int boot_run(struct bootm_info *bmi, const char *cmd, int extra_states)
 		states |= BOOTM_STATE_RAMDISK;
 	states |= extra_states;
 
-	log_debug("cmd '%s' states %x addr_img '%s' conf_ramdisk '%s' conf_fdt '%s' images %p\n",
-		  cmd, states, bmi->addr_img, bmi->conf_ramdisk, bmi->conf_fdt,
-		  bmi->images);
-
 	return bootm_run_states(bmi, states);
 }
 
@@ -1187,9 +1127,7 @@ int bootz_run(struct bootm_info *bmi)
 
 int booti_run(struct bootm_info *bmi)
 {
-	return boot_run(bmi, "booti", BOOTM_STATE_START | BOOTM_STATE_FINDOS |
-			BOOTM_STATE_PRE_LOAD | BOOTM_STATE_FINDOTHER |
-			BOOTM_STATE_LOADOS);
+	return boot_run(bmi, "booti", 0);
 }
 
 int bootm_boot_start(ulong addr, const char *cmdline)
@@ -1228,8 +1166,7 @@ void bootm_init(struct bootm_info *bmi)
 {
 	memset(bmi, '\0', sizeof(struct bootm_info));
 	bmi->boot_progress = true;
-	if (IS_ENABLED(CONFIG_CMD_BOOTM) || IS_ENABLED(CONFIG_CMD_BOOTZ) ||
-	    IS_ENABLED(CONFIG_CMD_BOOTI) || IS_ENABLED(CONFIG_PXE_UTILS))
+	if (IS_ENABLED(CONFIG_CMD_BOOTM))
 		bmi->images = &images;
 }
 
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index ea4c9ed830f..c7b862e512a 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -446,9 +446,9 @@ static int cros_boot(struct udevice *dev, struct bootflow *bflow)
 	}
 
 	if (IS_ENABLED(CONFIG_X86)) {
-		ret = zboot_run_args(map_to_sysmem(bflow->buf), bflow->size, 0,
-				     0, map_to_sysmem(bflow->x86_setup),
-				     bflow->cmdline);
+		ret = zboot_run(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
+				map_to_sysmem(bflow->x86_setup),
+				bflow->cmdline);
 	} else {
 		ret = bootm_boot_start(map_to_sysmem(bflow->buf),
 				       bflow->cmdline);
diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c
index 17c6cebd2f4..921d721a27b 100644
--- a/boot/bootmeth_extlinux.c
+++ b/boot/bootmeth_extlinux.c
@@ -108,15 +108,15 @@ static int extlinux_check(struct udevice *dev, struct bootflow_iter *iter)
  */
 static int extlinux_fill_info(struct bootflow *bflow)
 {
-	struct membuff mb;
+	struct membuf mb;
 	char line[200];
 	char *data;
 	int len;
 
 	log_debug("parsing bflow file size %x\n", bflow->size);
-	membuff_init(&mb, bflow->buf, bflow->size);
-	membuff_putraw(&mb, bflow->size, true, &data);
-	while (len = membuff_readline(&mb, line, sizeof(line) - 1, ' ', true), len) {
+	membuf_init(&mb, bflow->buf, bflow->size);
+	membuf_putraw(&mb, bflow->size, true, &data);
+	while (len = membuf_readline(&mb, line, sizeof(line) - 1, ' ', true), len) {
 		char *tok, *p = line;
 
 		tok = strsep(&p, " ");
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index b91e61bcbc4..6e5e0f99ea4 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -73,6 +73,10 @@ static int extlinux_pxe_read_bootflow(struct udevice *dev,
 		return log_msg_ret("pxeb", -EPERM);
 	addr = simple_strtoul(addr_str, NULL, 16);
 
+	ret = dhcp_run(addr, NULL, false);
+	if (ret)
+		return log_msg_ret("dhc", ret);
+
 	log_debug("calling pxe_get()\n");
 	ret = pxe_get(addr, &bootdir, &size, false);
 	log_debug("pxe_get() returned %d\n", ret);
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 49efeec3681..92f2f534ee0 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -18,6 +18,7 @@
 #include <dm/ofnode.h>
 #include <linux/ctype.h>
 #include <linux/types.h>
+#include <linux/sizes.h>
 #include <asm/global_data.h>
 #include <asm/unaligned.h>
 #include <linux/libfdt.h>
@@ -464,7 +465,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
 	do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
 }
 
-#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
 /*
  * fdt_pack_reg - pack address and size array into the "reg"-suitable stream
  */
@@ -493,6 +493,7 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size,
 	return p - (char *)buf;
 }
 
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
 #if CONFIG_NR_DRAM_BANKS > 4
 #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
 #else
@@ -2222,3 +2223,39 @@ int fdt_valid(struct fdt_header **blobp)
 	}
 	return 1;
 }
+
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size)
+{
+	char node_name[32];
+	int nodeoffset, len;
+	int err;
+	u8 tmp[4 * 16]; /* Up to 64-bit address + 64-bit size */
+
+	if (!IS_ALIGNED(pmem_start, SZ_2M) ||
+	    !IS_ALIGNED(pmem_start + pmem_size, SZ_2M)) {
+		printf("Start and end address must be 2MiB aligned\n");
+		return -1;
+	}
+
+	snprintf(node_name, sizeof(node_name), "pmem@%llx", pmem_start);
+	nodeoffset = fdt_find_or_add_subnode(fdt, 0, node_name);
+	if (nodeoffset < 0)
+		return nodeoffset;
+
+	err = fdt_setprop_string(fdt, nodeoffset, "compatible", "pmem-region");
+	if (err)
+		return err;
+	err = fdt_setprop_empty(fdt, nodeoffset, "volatile");
+	if (err)
+		return err;
+
+	len = fdt_pack_reg(fdt, tmp, &pmem_start, &pmem_size, 1);
+	err = fdt_setprop(fdt, nodeoffset, "reg", tmp, len);
+	if (err < 0) {
+		printf("WARNING: could not set pmem %s %s.\n", "reg",
+		       fdt_strerror(err));
+		return err;
+	}
+
+	return 0;
+}
diff --git a/boot/image-board.c b/boot/image-board.c
index a2bafba7ae1..514f8e63f9c 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -234,7 +234,21 @@ ulong genimg_get_kernel_addr(char * const img_addr)
 					  &fit_uname_kernel);
 }
 
-enum image_fmt_t genimg_get_format(const void *img_addr)
+/**
+ * genimg_get_format - get image format type
+ * @img_addr: image start address
+ *
+ * genimg_get_format() checks whether provided address points to a valid
+ * legacy or FIT image.
+ *
+ * New uImage format and FDT blob are based on a libfdt. FDT blob
+ * may be passed directly or embedded in a FIT image. In both situations
+ * genimg_get_format() must be able to dectect libfdt header.
+ *
+ * returns:
+ *     image format type or IMAGE_FORMAT_INVALID if no image is present
+ */
+int genimg_get_format(const void *img_addr)
 {
 	if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
 		const struct legacy_img_hdr *hdr;
@@ -250,24 +264,10 @@ enum image_fmt_t genimg_get_format(const void *img_addr)
 	if (IS_ENABLED(CONFIG_ANDROID_BOOT_IMAGE) &&
 	    is_android_boot_image_header(img_addr))
 		return IMAGE_FORMAT_ANDROID;
-	if (IS_ENABLED(CONFIG_CMD_BOOTI) &&
-	    booti_is_valid(img_addr))
-		return IMAGE_FORMAT_BOOTI;
 
 	return IMAGE_FORMAT_INVALID;
 }
 
-enum image_fmt_t genimg_get_format_comp(const void *img_addr)
-{
-	enum image_fmt_t fmt = genimg_get_format(img_addr);
-
-	if (IS_ENABLED(CONFIG_CMD_BOOTI) && fmt == IMAGE_FORMAT_INVALID &&
-	    image_decomp_type(img_addr, 2) != IH_COMP_NONE)
-		fmt = IMAGE_FORMAT_BOOTI;
-
-	return fmt;
-}
-
 /**
  * fit_has_config - check if there is a valid FIT configuration
  * @images: pointer to the bootm command headers structure
@@ -364,7 +364,7 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a
 	 * check image type, for FIT images get FIT node.
 	 */
 	buf = map_sysmem(rd_addr, 0);
-	switch (genimg_get_format_comp(buf)) {
+	switch (genimg_get_format(buf)) {
 	case IMAGE_FORMAT_LEGACY:
 		if (CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) {
 			const struct legacy_img_hdr *rd_hdr;
@@ -434,10 +434,6 @@ static int select_ramdisk(struct bootm_headers *images, const char *select, u8 a
 			done = true;
 		}
 		break;
-	case IMAGE_FORMAT_BOOTI:
-		break;
-	case IMAGE_FORMAT_INVALID:
-		break;
 	}
 
 	if (!done) {
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 9d1598b1a93..8f718ad29f6 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -11,6 +11,7 @@
 #include <command.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <efi.h>
 #include <env.h>
 #include <errno.h>
 #include <image.h>
@@ -649,6 +650,12 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb)
 	if (!ft_verify_fdt(blob))
 		goto err;
 
+	if (CONFIG_IS_ENABLED(BLKMAP) && CONFIG_IS_ENABLED(EFI_LOADER)) {
+		fdt_ret = fdt_efi_pmem_setup(blob);
+		if (fdt_ret)
+			goto err;
+	}
+
 	/* after here we are using a livetree */
 	if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) {
 		struct event_ft_fixup fixup;
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index c606da9e96b..82f217aaf86 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -7,7 +7,6 @@
 #define LOG_CATEGORY	LOGC_BOOT
 
 #include <bootflow.h>
-#include <bootm.h>
 #include <command.h>
 #include <dm.h>
 #include <env.h>
@@ -433,42 +432,169 @@ skip_overlay:
 }
 #endif
 
-/*
- * label_process_fdt() - Process FDT for the label
- *
- * @ctx: PXE context
- * @label: Label to process
- * @kernel_addr: String containing kernel address
- * @fdt_argp: bootm argument to fill in, for FDT
- * Return: 0 if OK, -ENOMEM if out of memory, -ENOENT if FDT file could not be
- *	loaded
- *
- * fdt usage is optional:
- * It handles the following scenarios.
+/**
+ * label_boot() - Boot according to the contents of a pxe_label
  *
- * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
- * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
- * bootm, and adjust argc appropriately.
+ * If we can't boot for any reason, we return.  A successful boot never
+ * returns.
  *
- * If retrieve fails and no exact fdt blob is specified in pxe file with
- * "fdt" label, try Scenario 2.
+ * The kernel will be stored in the location given by the 'kernel_addr_r'
+ * environment variable.
  *
- * Scenario 2: If there is an fdt_addr specified, pass it along to
- * bootm, and adjust argc appropriately.
+ * If the label specifies an initrd file, it will be stored in the location
+ * given by the 'ramdisk_addr_r' environment variable.
  *
- * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
- * bootm, and adjust argc appropriately, unless the image type is fitImage.
+ * If the label specifies an 'append' line, its contents will overwrite that
+ * of the 'bootargs' environment variable.
  *
- * Scenario 4: fdt blob is not available.
+ * @ctx: PXE context
+ * @label: Label to process
+ * Returns does not return on success, otherwise returns 0 if a localboot
+ *	label was processed, or 1 on error
  */
-static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
-			     char *kernel_addr, const char **fdt_argp)
+static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
 {
+	char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL };
+	char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL };
+	char *kernel_addr = NULL;
+	char *initrd_addr_str = NULL;
+	char initrd_filesize[10];
+	char initrd_str[28];
+	char mac_str[29] = "";
+	char ip_str[68] = "";
+	char *fit_addr = NULL;
+	int bootm_argc = 2;
+	int zboot_argc = 3;
+	int len = 0;
+	ulong kernel_addr_r;
+	void *buf;
+
+	label_print(label);
+
+	label->attempted = 1;
+
+	if (label->localboot) {
+		if (label->localboot_val >= 0)
+			label_localboot(label);
+		return 0;
+	}
+
+	if (!label->kernel) {
+		printf("No kernel given, skipping %s\n",
+		       label->name);
+		return 1;
+	}
+
+	if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r",
+				(enum bootflow_img_t)IH_TYPE_KERNEL, NULL)
+				< 0) {
+		printf("Skipping %s for failure retrieving kernel\n",
+		       label->name);
+		return 1;
+	}
+
+	kernel_addr = env_get("kernel_addr_r");
+	/* for FIT, append the configuration identifier */
+	if (label->config) {
+		int len = strlen(kernel_addr) + strlen(label->config) + 1;
+
+		fit_addr = malloc(len);
+		if (!fit_addr) {
+			printf("malloc fail (FIT address)\n");
+			return 1;
+		}
+		snprintf(fit_addr, len, "%s%s", kernel_addr, label->config);
+		kernel_addr = fit_addr;
+	}
+
+	/* For FIT, the label can be identical to kernel one */
+	if (label->initrd && !strcmp(label->kernel_label, label->initrd)) {
+		initrd_addr_str =  kernel_addr;
+	} else if (label->initrd) {
+		ulong size;
+		if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
+					(enum bootflow_img_t)IH_TYPE_RAMDISK,
+					&size) < 0) {
+			printf("Skipping %s for failure retrieving initrd\n",
+			       label->name);
+			goto cleanup;
+		}
+		strcpy(initrd_filesize, simple_xtoa(size));
+		initrd_addr_str = env_get("ramdisk_addr_r");
+		size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
+				initrd_addr_str, size);
+		if (size >= sizeof(initrd_str))
+			goto cleanup;
+	}
+
+	if (label->ipappend & 0x1) {
+		sprintf(ip_str, " ip=%s:%s:%s:%s",
+			env_get("ipaddr"), env_get("serverip"),
+			env_get("gatewayip"), env_get("netmask"));
+	}
+
+	if (IS_ENABLED(CONFIG_CMD_NET))	{
+		if (label->ipappend & 0x2) {
+			int err;
+
+			strcpy(mac_str, " BOOTIF=");
+			err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
+			if (err < 0)
+				mac_str[0] = '\0';
+		}
+	}
+
+	if ((label->ipappend & 0x3) || label->append) {
+		char bootargs[CONFIG_SYS_CBSIZE] = "";
+		char finalbootargs[CONFIG_SYS_CBSIZE];
+
+		if (strlen(label->append ?: "") +
+		    strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) {
+			printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n",
+			       strlen(label->append ?: ""),
+			       strlen(ip_str), strlen(mac_str),
+			       sizeof(bootargs));
+			goto cleanup;
+		}
+
+		if (label->append)
+			strncpy(bootargs, label->append, sizeof(bootargs));
+
+		strcat(bootargs, ip_str);
+		strcat(bootargs, mac_str);
+
+		cli_simple_process_macros(bootargs, finalbootargs,
+					  sizeof(finalbootargs));
+		env_set("bootargs", finalbootargs);
+		printf("append: %s\n", finalbootargs);
+	}
+
+	/*
+	 * fdt usage is optional:
+	 * It handles the following scenarios.
+	 *
+	 * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
+	 * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
+	 * bootm, and adjust argc appropriately.
+	 *
+	 * If retrieve fails and no exact fdt blob is specified in pxe file with
+	 * "fdt" label, try Scenario 2.
+	 *
+	 * Scenario 2: If there is an fdt_addr specified, pass it along to
+	 * bootm, and adjust argc appropriately.
+	 *
+	 * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
+	 * bootm, and adjust argc appropriately, unless the image type is fitImage.
+	 *
+	 * Scenario 4: fdt blob is not available.
+	 */
+	bootm_argv[3] = env_get("fdt_addr_r");
+
 	/* For FIT, the label can be identical to kernel one */
 	if (label->fdt && !strcmp(label->kernel_label, label->fdt)) {
-		*fdt_argp = kernel_addr;
+		bootm_argv[3] = kernel_addr;
 	/* if fdt label is defined then get fdt from server */
-	} else if (*fdt_argp) {
+	} else if (bootm_argv[3]) {
 		char *fdtfile = NULL;
 		char *fdtfilefree = NULL;
 
@@ -481,7 +607,6 @@ static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
 			}
 		} else if (label->fdtdir) {
 			char *f1, *f2, *f3, *f4, *slash;
-			int len;
 
 			f1 = env_get("fdtfile");
 			if (f1) {
@@ -524,7 +649,7 @@ static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
 			fdtfilefree = malloc(len);
 			if (!fdtfilefree) {
 				printf("malloc fail (FDT filename)\n");
-				return -ENOMEM;
+				goto cleanup;
 			}
 
 			snprintf(fdtfilefree, len, "%s%s%s%s%s%s",
@@ -539,12 +664,12 @@ static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
 
 			free(fdtfilefree);
 			if (err < 0) {
-				*fdt_argp = NULL;
+				bootm_argv[3] = NULL;
 
 				if (label->fdt) {
 					printf("Skipping %s for failure retrieving FDT\n",
 					       label->name);
-					return -ENOENT;
+					goto cleanup;
 				}
 
 				if (label->fdtdir) {
@@ -561,236 +686,74 @@ static int label_process_fdt(struct pxe_context *ctx, struct pxe_label *label,
 				label_boot_fdtoverlay(ctx, label);
 #endif
 		} else {
-			*fdt_argp = NULL;
+			bootm_argv[3] = NULL;
 		}
 	}
 
-	return 0;
-}
-
-/**
- * label_run_boot() - Set up the FDT and call the appropriate bootm/z/i command
- *
- * @ctx: PXE context
- * @label: Label to process
- * @kernel_addr: String containing kernel address (cannot be NULL)
- * @initrd_addr_str: String containing initrd address (NULL if none)
- * @initrd_filesize: String containing initrd size (only used if
- *	@initrd_addr_str)
- * @initrd_str: initrd string to process (only used if @initrd_addr_str)
- * Return: does not return on success, or returns 0 if the boot command
- * returned, or -ve error value on error
- */
-static int label_run_boot(struct pxe_context *ctx, struct pxe_label *label,
-			  char *kernel_addr, char *initrd_addr_str,
-			  char *initrd_filesize, char *initrd_str)
-{
-	struct bootm_info bmi;
-	ulong kernel_addr_r;
-	void *buf;
-	int ret;
-
-	bootm_init(&bmi);
-
-	bmi.conf_fdt = env_get("fdt_addr_r");
-
-	ret = label_process_fdt(ctx, label, kernel_addr, &bmi.conf_fdt);
-	if (ret)
-		return ret;
-
-	bmi.addr_img = kernel_addr;
-	bootm_x86_set(&bmi, bzimage_addr, hextoul(kernel_addr, NULL));
+	bootm_argv[1] = kernel_addr;
+	zboot_argv[1] = kernel_addr;
 
 	if (initrd_addr_str) {
-		bmi.conf_ramdisk = initrd_str;
-		bootm_x86_set(&bmi, initrd_addr,
-			      hextoul(initrd_addr_str, NULL));
-		bootm_x86_set(&bmi, initrd_size,
-			      hextoul(initrd_filesize, NULL));
+		bootm_argv[2] = initrd_str;
+		bootm_argc = 3;
+
+		zboot_argv[3] = initrd_addr_str;
+		zboot_argv[4] = initrd_filesize;
+		zboot_argc = 5;
 	}
 
-	if (!bmi.conf_fdt) {
-		if (!IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS) ||
-		    strcmp("-", label->fdt))
-			bmi.conf_fdt = env_get("fdt_addr");
+	if (!bootm_argv[3]) {
+		if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
+			if (strcmp("-", label->fdt))
+				bootm_argv[3] = env_get("fdt_addr");
+		} else {
+			bootm_argv[3] = env_get("fdt_addr");
+		}
 	}
 
 	kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
 	buf = map_sysmem(kernel_addr_r, 0);
 
-	if (!bmi.conf_fdt && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
-		if (!IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS) ||
-		    strcmp("-", label->fdt))
-			bmi.conf_fdt = env_get("fdtcontroladdr");
+	if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
+		if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
+			if (strcmp("-", label->fdt))
+				bootm_argv[3] = env_get("fdtcontroladdr");
+		} else {
+			bootm_argv[3] = env_get("fdtcontroladdr");
+		}
+	}
+
+	if (bootm_argv[3]) {
+		if (!bootm_argv[2])
+			bootm_argv[2] = "-";
+		bootm_argc = 4;
 	}
 
 	/* Try bootm for legacy and FIT format image */
 	if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
 	    IS_ENABLED(CONFIG_CMD_BOOTM)) {
 		log_debug("using bootm\n");
-		ret = bootm_run(&bmi);
+		do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv);
 	/* Try booting an AArch64 Linux kernel image */
 	} else if (IS_ENABLED(CONFIG_CMD_BOOTI)) {
 		log_debug("using booti\n");
-		ret = booti_run(&bmi);
+		do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv);
 	/* Try booting a Image */
 	} else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) {
 		log_debug("using bootz\n");
-		ret = bootz_run(&bmi);
+		do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv);
 	/* Try booting an x86_64 Linux kernel image */
 	} else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) {
 		log_debug("using zboot\n");
-		ret = zboot_run(&bmi);
+		do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL);
 	}
 
 	unmap_sysmem(buf);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-/**
- * label_boot() - Boot according to the contents of a pxe_label
- *
- * If we can't boot for any reason, we return.  A successful boot never
- * returns.
- *
- * The kernel will be stored in the location given by the 'kernel_addr_r'
- * environment variable.
- *
- * If the label specifies an initrd file, it will be stored in the location
- * given by the 'ramdisk_addr_r' environment variable.
- *
- * If the label specifies an 'append' line, its contents will overwrite that
- * of the 'bootargs' environment variable.
- *
- * @ctx: PXE context
- * @label: Label to process
- * Returns does not return on success, otherwise returns 0 if a localboot
- *	label was processed, or 1 on error
- */
-static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
-{
-	char *kernel_addr = NULL;
-	char *initrd_addr_str = NULL;
-	char initrd_filesize[10];
-	char initrd_str[28];
-	char mac_str[29] = "";
-	char ip_str[68] = "";
-	char *fit_addr = NULL;
-
-	label_print(label);
-
-	label->attempted = 1;
-
-	if (label->localboot) {
-		if (label->localboot_val >= 0)
-			label_localboot(label);
-		return 0;
-	}
-
-	if (!label->kernel) {
-		printf("No kernel given, skipping %s\n",
-		       label->name);
-		return 1;
-	}
-
-	if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r",
-				(enum bootflow_img_t)IH_TYPE_KERNEL, NULL)
-				< 0) {
-		printf("Skipping %s for failure retrieving kernel\n",
-		       label->name);
-		return 1;
-	}
-
-	kernel_addr = env_get("kernel_addr_r");
-	/* for FIT, append the configuration identifier */
-	if (label->config) {
-		int len = strlen(kernel_addr) + strlen(label->config) + 1;
-
-		fit_addr = malloc(len);
-		if (!fit_addr) {
-			printf("malloc fail (FIT address)\n");
-			return 1;
-		}
-		snprintf(fit_addr, len, "%s%s", kernel_addr, label->config);
-		kernel_addr = fit_addr;
-	}
-
-	/* For FIT, the label can be identical to kernel one */
-	if (label->initrd && !strcmp(label->kernel_label, label->initrd)) {
-		initrd_addr_str =  kernel_addr;
-	} else if (label->initrd) {
-		ulong size;
-		int ret;
-
-		ret = get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
-					  (enum bootflow_img_t)IH_TYPE_RAMDISK,
-					  &size);
-		if (ret < 0) {
-			printf("Skipping %s for failure retrieving initrd\n",
-			       label->name);
-			goto cleanup;
-		}
-		strcpy(initrd_filesize, simple_xtoa(size));
-		initrd_addr_str = env_get("ramdisk_addr_r");
-		size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
-				initrd_addr_str, size);
-		if (size >= sizeof(initrd_str))
-			goto cleanup;
-	}
-
-	if (label->ipappend & 0x1) {
-		sprintf(ip_str, " ip=%s:%s:%s:%s",
-			env_get("ipaddr"), env_get("serverip"),
-			env_get("gatewayip"), env_get("netmask"));
-	}
-
-	if (IS_ENABLED(CONFIG_CMD_NET))	{
-		if (label->ipappend & 0x2) {
-			int err;
-
-			strcpy(mac_str, " BOOTIF=");
-			err = format_mac_pxe(mac_str + 8, sizeof(mac_str) - 8);
-			if (err < 0)
-				mac_str[0] = '\0';
-		}
-	}
-
-	if ((label->ipappend & 0x3) || label->append) {
-		char bootargs[CONFIG_SYS_CBSIZE] = "";
-		char finalbootargs[CONFIG_SYS_CBSIZE];
-
-		if (strlen(label->append ?: "") +
-		    strlen(ip_str) + strlen(mac_str) + 1 > sizeof(bootargs)) {
-			printf("bootarg overflow %zd+%zd+%zd+1 > %zd\n",
-			       strlen(label->append ?: ""),
-			       strlen(ip_str), strlen(mac_str),
-			       sizeof(bootargs));
-			goto cleanup;
-		}
-
-		if (label->append)
-			strlcpy(bootargs, label->append, sizeof(bootargs));
-
-		strcat(bootargs, ip_str);
-		strcat(bootargs, mac_str);
-
-		cli_simple_process_macros(bootargs, finalbootargs,
-					  sizeof(finalbootargs));
-		env_set("bootargs", finalbootargs);
-		printf("append: %s\n", finalbootargs);
-	}
-
-	label_run_boot(ctx, label, kernel_addr, initrd_addr_str,
-		       initrd_filesize, initrd_str);
-	/* ignore the error value since we are going to fail anyway */
 
 cleanup:
 	free(fit_addr);
 
-	return 1;	/* returning is always failure */
+	return 1;
 }
 
 /** enum token_type - Tokens for the pxe file parser */
diff --git a/cmd/Kconfig b/cmd/Kconfig
index cd391d422ae..ecef664fcea 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1236,6 +1236,14 @@ config CMD_FUSE
 	  which control the behaviour of the device. The command uses the
 	  fuse_...() API.
 
+config CMD_FUSE_WRITEBUFF
+	bool "Support for the fuse writebuff"
+	depends on CMD_FUSE
+	help
+	  This allows programming fuses, which control the behaviour of
+	  the device, using a structured buffer in memory. The command
+	  uses the fuse_writebuff() API.
+
 config CMD_GPIO
 	bool "gpio"
 	help
@@ -1834,12 +1842,10 @@ menuconfig CMD_NET
 	bool "Network commands"
 	default y
 
-endif
+if CMD_NET
 
 if NET
 
-if CMD_NET
-
 config CMD_BOOTP
 	bool "bootp"
 	default y
@@ -2062,7 +2068,7 @@ config CMD_SNTP
 
 config CMD_LINK_LOCAL
 	bool "linklocal"
-	select LIB_RAND
+	depends on (LIB_RAND || LIB_HW_RAND)
 	help
 	  Acquire a network IP address using the link-local protocol
 
@@ -2080,7 +2086,6 @@ config IPV6_ROUTER_DISCOVERY
 	help
 	  Will automatically perform router solicitation on first IPv6
 	  network operation
-endif  # if CMD_NET
 
 config CMD_ETHSW
 	bool "ethsw"
@@ -2097,10 +2102,6 @@ config CMD_WOL
 
 endif  # if NET
 
-if NET || NET_LWIP
-
-if CMD_NET
-
 config CMD_DHCP
 	bool "dhcp"
 	select PROT_DHCP_LWIP if NET_LWIP
@@ -2198,8 +2199,6 @@ config WGET_BUILTIN_CACERT_PATH
 	  Certification Authority certificates, a.k.a. root certificates, for
 	  the purpose of authenticating HTTPS connections.
 
-endif  # if CMD_NET
-
 config CMD_PXE
 	bool "pxe"
 	select PXE_UTILS
@@ -2207,7 +2206,9 @@ config CMD_PXE
 	help
 	  Boot image via network using PXE protocol
 
-endif  # if NET || NET_LWIP
+endif  # if CMD_NET
+
+endif # NET || NET_LWIP
 
 menu "Misc commands"
 
diff --git a/cmd/acpi.c b/cmd/acpi.c
index 094d9d4e858..bb243202009 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -7,6 +7,7 @@
 #include <display_options.h>
 #include <log.h>
 #include <mapmem.h>
+#include <tables_csum.h>
 #include <acpi/acpi_table.h>
 #include <asm/acpi_table.h>
 #include <asm/global_data.h>
@@ -15,6 +16,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *show_checksum(void *ptr, uint size, bool chksums)
+{
+	uint checksum;
+
+	if (!chksums)
+		return "";
+	checksum = table_compute_checksum(ptr, size);
+
+	return checksum ? "  bad" : "  OK";
+}
+
 /**
  * dump_hdr() - Dump an ACPI header
  *
@@ -23,16 +35,17 @@ DECLARE_GLOBAL_DATA_PTR;
  *
  * @hdr: ACPI header to dump
  */
-static void dump_hdr(struct acpi_table_header *hdr)
+static void dump_hdr(struct acpi_table_header *hdr, bool chksums)
 {
 	bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN);
 
 	printf("%.*s  %16lx  %5x", ACPI_NAME_LEN, hdr->signature,
 	       (ulong)map_to_sysmem(hdr), hdr->length);
 	if (has_hdr) {
-		printf("  v%02d %.6s %.8s %x %.4s %x\n", hdr->revision,
+		printf("  v%02d %.6s %.8s %x %.4s %x%s\n", hdr->revision,
 		       hdr->oem_id, hdr->oem_table_id, hdr->oem_revision,
-		       hdr->creator_id, hdr->creator_revision);
+		       hdr->creator_id, hdr->creator_revision,
+		       show_checksum(hdr, hdr->length, chksums));
 	} else {
 		printf("\n");
 	}
@@ -52,22 +65,22 @@ static int dump_table_name(const char *sig)
 	return 0;
 }
 
-static void list_fadt(struct acpi_fadt *fadt)
+static void list_fadt(struct acpi_fadt *fadt, bool chksums)
 {
 	if (fadt->header.revision >= 3 && fadt->x_dsdt)
-		dump_hdr(nomap_sysmem(fadt->x_dsdt, 0));
+		dump_hdr(nomap_sysmem(fadt->x_dsdt, 0), chksums);
 	else if (fadt->dsdt)
-		dump_hdr(nomap_sysmem(fadt->dsdt, 0));
-	if (!IS_ENABLED(CONFIG_X86) &&
+		dump_hdr(nomap_sysmem(fadt->dsdt, 0), chksums);
+	if (!IS_ENABLED(CONFIG_X86) && !IS_ENABLED(CONFIG_SANDBOX) &&
 	    !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI))
 		log_err("FADT not ACPI-hardware-reduced-compliant\n");
 	if (fadt->header.revision >= 3 && fadt->x_firmware_ctrl)
-		dump_hdr(nomap_sysmem(fadt->x_firmware_ctrl, 0));
+		dump_hdr(nomap_sysmem(fadt->x_firmware_ctrl, 0), chksums);
 	else if (fadt->firmware_ctrl)
-		dump_hdr(nomap_sysmem(fadt->firmware_ctrl, 0));
+		dump_hdr(nomap_sysmem(fadt->firmware_ctrl, 0), chksums);
 }
 
-static void list_rsdt(struct acpi_rsdp *rsdp)
+static void list_rsdt(struct acpi_rsdp *rsdp, bool chksums)
 {
 	int len, i, count;
 	struct acpi_rsdt *rsdt;
@@ -75,11 +88,11 @@ static void list_rsdt(struct acpi_rsdp *rsdp)
 
 	if (rsdp->rsdt_address) {
 		rsdt = nomap_sysmem(rsdp->rsdt_address, 0);
-		dump_hdr(&rsdt->header);
+		dump_hdr(&rsdt->header, chksums);
 	}
 	if (rsdp->xsdt_address) {
 		xsdt = nomap_sysmem(rsdp->xsdt_address, 0);
-		dump_hdr(&xsdt->header);
+		dump_hdr(&xsdt->header, chksums);
 		len = xsdt->header.length - sizeof(xsdt->header);
 		count = len / sizeof(u64);
 	} else if (rsdp->rsdt_address) {
@@ -100,24 +113,28 @@ static void list_rsdt(struct acpi_rsdp *rsdp)
 		if (!entry)
 			break;
 		hdr = nomap_sysmem(entry, 0);
-		dump_hdr(hdr);
+		dump_hdr(hdr, chksums);
 		if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN))
-			list_fadt((struct acpi_fadt *)hdr);
+			list_fadt((struct acpi_fadt *)hdr, chksums);
 	}
 }
 
-static void list_rsdp(struct acpi_rsdp *rsdp)
+static void list_rsdp(struct acpi_rsdp *rsdp, bool chksums)
 {
-	printf("RSDP  %16lx  %5x  v%02d %.6s\n", (ulong)map_to_sysmem(rsdp),
-	       rsdp->length, rsdp->revision, rsdp->oem_id);
-	list_rsdt(rsdp);
+	printf("RSDP  %16lx  %5x  v%02d %.6s%s%s\n",
+	       (ulong)map_to_sysmem(rsdp), rsdp->length, rsdp->revision,
+	       rsdp->oem_id, show_checksum(rsdp, 0x14, chksums),
+	       show_checksum(rsdp, rsdp->length, chksums));
+	list_rsdt(rsdp, chksums);
 }
 
 static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
 			char *const argv[])
 {
 	struct acpi_rsdp *rsdp;
+	bool chksums;
 
+	chksums = argc >= 2 && !strcmp("-c", argv[1]);
 	rsdp = map_sysmem(gd_acpi_start(), 0);
 	if (!rsdp) {
 		printf("No ACPI tables present\n");
@@ -125,7 +142,7 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 	printf("Name              Base   Size  Detail\n"
 	       "----  ----------------  -----  ----------------------------\n");
-	list_rsdp(rsdp);
+	list_rsdp(rsdp, chksums);
 
 	return 0;
 }
@@ -187,13 +204,13 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 
 U_BOOT_LONGHELP(acpi,
-	"list  - list ACPI tables\n"
+	"list [-c] - list ACPI tables [check checksums]\n"
 	"acpi items [-d]   - List/dump each piece of ACPI data from devices\n"
 	"acpi set [<addr>] - Set or show address of ACPI tables\n"
 	"acpi dump <name>  - Dump ACPI table");
 
 U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
-	U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
+	U_BOOT_SUBCMD_MKENT(list, 2, 1, do_acpi_list),
 	U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items),
 	U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set),
 	U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump));
diff --git a/cmd/blkmap.c b/cmd/blkmap.c
index 164f80f1387..86a123b1cd3 100644
--- a/cmd/blkmap.c
+++ b/cmd/blkmap.c
@@ -62,13 +62,18 @@ static int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[])
 {
 	phys_addr_t addr;
 	int err;
+	bool preserve = false;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
 	addr = hextoul(argv[1], NULL);
 
-	err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr);
+	if (argc == 3 && !strcmp(argv[2], "preserve"))
+		preserve = true;
+
+	err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr,
+			      preserve);
 	if (err) {
 		printf("Unable to map %#llx at block 0x" LBAF ": %d\n",
 		       (unsigned long long)addr, ctx->blknr, err);
@@ -221,7 +226,7 @@ U_BOOT_CMD_WITH_SUBCMDS(
 	"blkmap create <label> - create device\n"
 	"blkmap destroy <label> - destroy device\n"
 	"blkmap map <label> <blk#> <cnt> linear <interface> <dev> <blk#> - device mapping\n"
-	"blkmap map <label> <blk#> <cnt> mem <addr> - memory mapping\n",
+	"blkmap map <label> <blk#> <cnt> mem <addr> [preserve] - memory mapping\n",
 	U_BOOT_SUBCMD_MKENT(info, 2, 1, do_blkmap_common),
 	U_BOOT_SUBCMD_MKENT(part, 2, 1, do_blkmap_common),
 	U_BOOT_SUBCMD_MKENT(dev, 4, 1, do_blkmap_common),
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index 6d0be320bdb..a1fd59a69f4 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -173,7 +173,7 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	std->cur_bootflow = NULL;
 
-	flags = 0;
+	flags = BOOTFLOWIF_ONLY_BOOTABLE;
 	if (list)
 		flags |= BOOTFLOWIF_SHOW;
 	if (all)
@@ -380,13 +380,7 @@ static int do_bootflow_info(struct cmd_tbl *cmdtp, int flag, int argc,
 	bflow = std->cur_bootflow;
 
 	if (IS_ENABLED(CONFIG_X86) && x86_setup) {
-		struct bootm_info bmi;
-
-		bootm_init(&bmi);
-		/* we don't know this at present */
-		bootm_x86_set(&bmi, bzimage_addr, 0);
-		bootm_x86_set(&bmi, base_ptr, bflow->x86_setup);
-		zimage_dump(&bmi, false);
+		zimage_dump(bflow->x86_setup, false);
 
 		return 0;
 	}
diff --git a/cmd/fs.c b/cmd/fs.c
index 3faf7627447..7f1ab8f0fd2 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -85,6 +85,34 @@ U_BOOT_CMD(
 	"      device type 'interface' instance 'dev'."
 );
 
+static int do_mkdir_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	return do_mkdir(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+	mkdir,	4,	1,	do_mkdir_wrapper,
+	"create a directory",
+	"<interface> [<dev[:part]>] <directory>\n"
+	"    - Create a directory 'directory' of partition 'part' on\n"
+	"      device type 'interface' instance 'dev'."
+);
+
+static int do_rm_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return do_rm(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+	rm,	4,	1,	do_rm_wrapper,
+	"delete a file",
+	"<interface> [<dev[:part]>] <filename>\n"
+	"    - delete a file with the name 'filename' on\n"
+	"      device type 'interface' instance 'dev'."
+);
+
 static int do_fstype_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
 			     char *const argv[])
 {
diff --git a/cmd/fuse.c b/cmd/fuse.c
index 598ef496a43..6c42c096809 100644
--- a/cmd/fuse.c
+++ b/cmd/fuse.c
@@ -15,17 +15,6 @@
 #include <vsprintf.h>
 #include <linux/errno.h>
 
-static int strtou32(const char *str, unsigned int base, u32 *result)
-{
-	char *ep;
-
-	*result = simple_strtoul(str, &ep, base);
-	if (ep == str || *ep != '\0')
-		return -EINVAL;
-
-	return 0;
-}
-
 static int confirm_prog(void)
 {
 	puts("Warning: Programming fuses is an irreversible operation!\n"
@@ -54,14 +43,25 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	argc -= 2 + confirmed;
 	argv += 2 + confirmed;
 
-	if (argc < 2 || strtou32(argv[0], 0, &bank) ||
-			strtou32(argv[1], 0, &word))
-		return CMD_RET_USAGE;
+	if (IS_ENABLED(CONFIG_CMD_FUSE_WRITEBUFF) && !strcmp(op, "writebuff")) {
+		if (argc == 1)
+			addr = simple_strtoul(argv[0], NULL, 16);
+		else
+			return CMD_RET_USAGE;
+	} else {
+		if (argc < 2)
+			return CMD_RET_USAGE;
+
+		bank = simple_strtoul(argv[0], NULL, 0);
+		word = simple_strtoul(argv[1], NULL, 0);
+	}
 
 	if (!strcmp(op, "read")) {
 		if (argc == 2)
 			cnt = 1;
-		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+		else if (argc == 3)
+			cnt = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Reading bank %u:\n", bank);
@@ -79,7 +79,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	} else if (!strcmp(op, "readm")) {
 		if (argc == 3)
 			cnt = 1;
-		else if (argc != 4 || strtou32(argv[3], 0, &cnt))
+		else if (argc == 4)
+			cnt = simple_strtoul(argv[3], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		addr = simple_strtoul(argv[2], NULL, 16);
@@ -99,7 +101,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 
 		unmap_sysmem(start);
 	} else if (!strcmp(op, "cmp")) {
-		if (argc != 3 || strtou32(argv[2], 0, &cmp))
+		if (argc == 3)
+			cmp = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Comparing bank %u:\n", bank);
@@ -119,7 +123,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	} else if (!strcmp(op, "sense")) {
 		if (argc == 2)
 			cnt = 1;
-		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+		else if (argc == 3)
+			cnt = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Sensing bank %u:\n", bank);
@@ -139,8 +145,7 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			return CMD_RET_USAGE;
 
 		for (i = 2; i < argc; i++, word++) {
-			if (strtou32(argv[i], 16, &val))
-				return CMD_RET_USAGE;
+			val = simple_strtoul(argv[i], NULL, 16);
 
 			printf("Programming bank %u word 0x%.8x to 0x%.8x...\n",
 					bank, word, val);
@@ -155,8 +160,7 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			return CMD_RET_USAGE;
 
 		for (i = 2; i < argc; i++, word++) {
-			if (strtou32(argv[i], 16, &val))
-				return CMD_RET_USAGE;
+			val = simple_strtoul(argv[i], NULL, 16);
 
 			printf("Overriding bank %u word 0x%.8x with "
 					"0x%.8x...\n", bank, word, val);
@@ -164,6 +168,15 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			if (ret)
 				goto err;
 		}
+	} else if (IS_ENABLED(CONFIG_CMD_FUSE_WRITEBUFF) && !strcmp(op, "writebuff")) {
+		printf("Programming fuses using a structured buffer in memory "
+				"starting at addr 0x%lx\n", addr);
+		if (!confirmed && !confirm_prog())
+			return CMD_RET_FAILURE;
+
+		ret = fuse_writebuff(addr);
+		if (ret)
+			goto err;
 	} else {
 		return CMD_RET_USAGE;
 	}
@@ -189,5 +202,9 @@ U_BOOT_CMD(
 	"fuse prog [-y] <bank> <word> <hexval> [<hexval>...] - program 1 or\n"
 	"    several fuse words, starting at 'word' (PERMANENT)\n"
 	"fuse override <bank> <word> <hexval> [<hexval>...] - override 1 or\n"
-	"    several fuse words, starting at 'word'"
+	"    several fuse words, starting at 'word'\n"
+#ifdef CONFIG_CMD_FUSE_WRITEBUFF
+	"fuse writebuff [-y] <addr> - program fuse data\n"
+	"    using a structured buffer in memory starting at 'addr'\n"
+#endif /* CONFIG_CMD_FUSE_WRITEBUFF */
 );
diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c
index 58c10fbec7d..cecf8d02555 100644
--- a/cmd/net-lwip.c
+++ b/cmd/net-lwip.c
@@ -17,7 +17,7 @@ U_BOOT_CMD(ping, 2, 1, do_ping, "send ICMP ECHO_REQUEST to network host",
 
 #if defined(CONFIG_CMD_TFTPBOOT)
 U_BOOT_CMD(tftpboot, 3, 0, do_tftpb,
-	   "boot image via network using TFTP protocol\n",
+	   "boot image via network using TFTP protocol",
 	   "[loadAddress] [[hostIPaddr:]bootfilename]");
 #endif
 
diff --git a/cmd/net.c b/cmd/net.c
index 8f33c9f55d5..79525f73a51 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -297,15 +297,13 @@ static void netboot_update_env(void)
 /**
  * parse_addr_size() - parse address and size arguments for tftpput
  *
- * @argv:	command line arguments (argv[1] and argv[2] must be valid)
- * @addrp:	returns the address, on success
- * @sizep:	returns the size, on success
+ * @argv:	command line arguments
  * Return:	0 on success
  */
-static int parse_addr_size(char * const argv[], ulong *addrp, ulong *sizep)
+static int parse_addr_size(char * const argv[])
 {
-	if (strict_strtoul(argv[1], 16, addrp) < 0 ||
-	    strict_strtoul(argv[2], 16, sizep) < 0) {
+	if (strict_strtoul(argv[1], 16, &image_save_addr) < 0 ||
+	    strict_strtoul(argv[2], 16, &image_save_size) < 0) {
 		printf("Invalid address/size\n");
 		return CMD_RET_USAGE;
 	}
@@ -315,31 +313,24 @@ static int parse_addr_size(char * const argv[], ulong *addrp, ulong *sizep)
 /**
  * parse_args() - parse command line arguments
  *
- * Sets:
- * - image_save_addr and image_save_size, if proto == TFTPPUT
- *
  * @proto:	command prototype
- * @argc:	number of arguments, include the command, which has already been
- *		parsed
- * @argv:	command line arguments, with argv[0] being the command
- * @fnamep:	set to the filename, if provided, else NULL
- * @addrp:	returns the load/save address, if any is provided, else it is
- *		left unchanged
- * @sizep:	returns the save size, if any is provided, else it is left
- *		unchanged
+ * @argc:	number of arguments
+ * @argv:	command line arguments
  * Return:	0 on success
  */
-static int parse_args(enum proto_t proto, int argc, char *const argv[],
-		      const char **fnamep, ulong *addrp, ulong *sizep)
+static int parse_args(enum proto_t proto, int argc, char *const argv[])
 {
 	ulong addr;
 	char *end;
 
-	*fnamep = NULL;
 	switch (argc) {
 	case 1:
 		if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT)
 			return 1;
+
+		/* refresh bootfile name from env */
+		copy_filename(net_boot_file_name, env_get("bootfile"),
+			      sizeof(net_boot_file_name));
 		break;
 
 	case 2:
@@ -352,42 +343,48 @@ static int parse_args(enum proto_t proto, int argc, char *const argv[],
 		 * mis-interpreted as a valid number.
 		 */
 		addr = hextoul(argv[1], &end);
-		if (end == (argv[1] + strlen(argv[1])))
-			*addrp = addr;
-		else
-			*fnamep = argv[1];
+		if (end == (argv[1] + strlen(argv[1]))) {
+			image_load_addr = addr;
+			/* refresh bootfile name from env */
+			copy_filename(net_boot_file_name, env_get("bootfile"),
+				      sizeof(net_boot_file_name));
+		} else {
+			net_boot_file_name_explicit = true;
+			copy_filename(net_boot_file_name, argv[1],
+				      sizeof(net_boot_file_name));
+		}
 		break;
 
 	case 3:
 		if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT) {
-			if (parse_addr_size(argv, addrp, sizep))
+			if (parse_addr_size(argv))
 				return 1;
 		} else {
-			*addrp = hextoul(argv[1], NULL);
-			*fnamep = argv[2];
+			image_load_addr = hextoul(argv[1], NULL);
+			net_boot_file_name_explicit = true;
+			copy_filename(net_boot_file_name, argv[2],
+				      sizeof(net_boot_file_name));
 		}
 		break;
 
+#ifdef CONFIG_CMD_TFTPPUT
 	case 4:
-		if (IS_ENABLED(CONFIG_CMD_TFTPPUT)) {
-			if (parse_addr_size(argv, addrp, sizep))
-				return 1;
-			*fnamep = argv[3];
-			break;
-		}
+		if (parse_addr_size(argv))
+			return 1;
+		net_boot_file_name_explicit = true;
+		copy_filename(net_boot_file_name, argv[3],
+			      sizeof(net_boot_file_name));
+		break;
+#endif
 	default:
 		return 1;
 	}
-
 	return 0;
 }
 
 static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc,
 			  char *const argv[])
 {
-	ulong addr, save_size;
-	bool fname_explicit;
-	const char *fname;
 	char *s;
 	int   rcode = 0;
 	int   size;
@@ -395,10 +392,10 @@ static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc,
 	net_boot_file_name_explicit = false;
 	*net_boot_file_name = '\0';
 
-	/* pre-set addr */
+	/* pre-set image_load_addr */
 	s = env_get("loadaddr");
 	if (s != NULL)
-		addr = hextoul(s, NULL);
+		image_load_addr = hextoul(s, NULL);
 
 	if (IS_ENABLED(CONFIG_IPV6)) {
 		use_ip6 = false;
@@ -411,17 +408,12 @@ static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc,
 		}
 	}
 
-	if (parse_args(proto, argc, argv, &fname, &addr, &save_size)) {
+	if (parse_args(proto, argc, argv)) {
 		bootstage_error(BOOTSTAGE_ID_NET_START);
 		return CMD_RET_USAGE;
 	}
 
-	if (fname) {
-		fname_explicit = true;
-	} else {
-		fname_explicit = false;
-		fname = env_get("bootfile");
-	}
+	bootstage_mark(BOOTSTAGE_ID_NET_START);
 
 	if (IS_ENABLED(CONFIG_IPV6) && !use_ip6) {
 		char *s, *e;
@@ -436,10 +428,12 @@ static int netboot_common(enum proto_t proto, struct cmd_tbl *cmdtp, int argc,
 		}
 	}
 
-	size = netboot_run_(proto, addr, fname, save_size, fname_explicit,
-			    IS_ENABLED(CONFIG_IPV6) && use_ip6);
-	if (size < 0)
+	size = net_loop(proto);
+	if (size < 0) {
+		bootstage_error(BOOTSTAGE_ID_NET_NETLOOP_OK);
 		return CMD_RET_FAILURE;
+	}
+	bootstage_mark(BOOTSTAGE_ID_NET_NETLOOP_OK);
 
 	/* net_loop ok, update environment */
 	netboot_update_env();
diff --git a/cmd/version.c b/cmd/version.c
index 53db1a0b6bd..62406608eb0 100644
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -6,6 +6,7 @@
 
 #include <command.h>
 #include <display_options.h>
+#include <version.h>
 #include <version_string.h>
 #include <linux/compiler.h>
 #ifdef CONFIG_SYS_COREBOOT
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b2afb598c73..289865515ef 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -13,8 +13,8 @@
 static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
 {
 	const char *typename = argv[0];
-	uint32_t start, size;
-	uint64_t base, mask;
+	u64 start, size;
+	u64 base, mask;
 	int type = -1;
 	bool valid;
 	int ret;
@@ -26,13 +26,12 @@ static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
 		printf("Invalid type name %s\n", typename);
 		return CMD_RET_USAGE;
 	}
-	start = hextoul(argv[1], NULL);
-	size = hextoul(argv[2], NULL);
+	start = hextoull(argv[1], NULL);
+	size = hextoull(argv[2], NULL);
 
 	base = start | type;
 	valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
-	mask = ~((uint64_t)size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+	mask = mtrr_to_mask(size);
 	if (valid)
 		mask |= MTRR_PHYS_MASK_VALID;
 
diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c
index ee099ca041b..94e602b8a5b 100644
--- a/cmd/x86/zboot.c
+++ b/cmd/x86/zboot.c
@@ -7,15 +7,11 @@
 
 #define LOG_CATEGORY	LOGC_BOOT
 
-#include <bootm.h>
 #include <command.h>
 #include <mapmem.h>
 #include <vsprintf.h>
 #include <asm/zimage.h>
 
-/* Current state of the boot */
-static struct bootm_info bmi;
-
 static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
 {
@@ -24,8 +20,6 @@ static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
 	ulong base_addr;
 	int i;
 
-	bootm_init(&bmi);
-
 	log_debug("argc %d:", argc);
 	for (i = 0; i < argc; i++)
 		log_debug(" %s", argv[i]);
@@ -41,7 +35,7 @@ static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
 	base_addr = argc > 5 ? hextoul(argv[5], NULL) : 0;
 	cmdline = argc > 6 ? env_get(argv[6]) : NULL;
 
-	zboot_start(&bmi, bzimage_addr, bzimage_size, initrd_addr, initrd_size,
+	zboot_start(bzimage_addr, bzimage_size, initrd_addr, initrd_size,
 		    base_addr, cmdline);
 
 	return 0;
@@ -52,7 +46,7 @@ static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	int ret;
 
-	ret = zboot_load(&bmi);
+	ret = zboot_load();
 	if (ret)
 		return ret;
 
@@ -62,17 +56,16 @@ static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
 static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
 			  char *const argv[])
 {
-	if (!bmi.base_ptr) {
+	if (!state.base_ptr) {
 		printf("base is not set: use 'zboot load' first\n");
 		return CMD_RET_FAILURE;
 	}
-
-	if (zboot_setup(&bmi)) {
+	if (zboot_setup()) {
 		puts("Setting up boot parameters failed ...\n");
 		return CMD_RET_FAILURE;
 	}
 
-	if (zboot_setup(&bmi))
+	if (zboot_setup())
 		return CMD_RET_FAILURE;
 
 	return 0;
@@ -81,7 +74,7 @@ static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
 static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
 			 char *const argv[])
 {
-	zboot_info(&bmi);
+	zboot_info();
 
 	return 0;
 }
@@ -91,7 +84,7 @@ static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
 {
 	int ret;
 
-	ret = zboot_go(&bmi);
+	ret = zboot_go();
 	if (ret) {
 		printf("Kernel returned! (err=%d)\n", ret);
 		return CMD_RET_FAILURE;
@@ -103,13 +96,15 @@ static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
 static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 			 char *const argv[])
 {
+	struct boot_params *base_ptr = state.base_ptr;
+
 	if (argc > 1)
-		bmi.base_ptr = (void *)hextoul(argv[1], NULL);
-	if (!bmi.base_ptr) {
+		base_ptr = (void *)hextoul(argv[1], NULL);
+	if (!base_ptr) {
 		printf("No zboot setup_base\n");
 		return CMD_RET_FAILURE;
 	}
-	zimage_dump(&bmi, true);
+	zimage_dump(base_ptr, true);
 
 	return 0;
 }
@@ -124,8 +119,8 @@ U_BOOT_SUBCMDS(zboot,
 	U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""),
 )
 
-static int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
-			   char *const argv[], int state_mask)
+int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
+		    char *const argv[], int state_mask)
 {
 	int ret = 0;
 
diff --git a/common/console.c b/common/console.c
index 26812b2ccbe..b69bb189639 100644
--- a/common/console.c
+++ b/common/console.c
@@ -101,7 +101,7 @@ static void console_record_putc(const char c)
 	if (!(gd->flags & GD_FLG_RECORD))
 		return;
 	if  (gd->console_out.start &&
-	     !membuff_putbyte((struct membuff *)&gd->console_out, c))
+	     !membuf_putbyte((struct membuf *)&gd->console_out, c))
 		gd->flags |= GD_FLG_RECORD_OVF;
 }
 
@@ -112,7 +112,7 @@ static void console_record_puts(const char *s)
 	if  (gd->console_out.start) {
 		int len = strlen(s);
 
-		if (membuff_put((struct membuff *)&gd->console_out, s, len) !=
+		if (membuf_put((struct membuf *)&gd->console_out, s, len) !=
 		    len)
 			gd->flags |= GD_FLG_RECORD_OVF;
 	}
@@ -125,7 +125,7 @@ static int console_record_getc(void)
 	if (!gd->console_in.start)
 		return -1;
 
-	return membuff_getbyte((struct membuff *)&gd->console_in);
+	return membuf_getbyte((struct membuf *)&gd->console_in);
 }
 
 static int console_record_tstc(void)
@@ -133,7 +133,7 @@ static int console_record_tstc(void)
 	if (!(gd->flags & GD_FLG_RECORD))
 		return 0;
 	if (gd->console_in.start) {
-		if (membuff_peekbyte((struct membuff *)&gd->console_in) != -1)
+		if (membuf_peekbyte((struct membuf *)&gd->console_in) != -1)
 			return 1;
 	}
 	return 0;
@@ -810,14 +810,14 @@ int console_record_init(void)
 {
 	int ret;
 
-	ret = membuff_new((struct membuff *)&gd->console_out,
-			  gd->flags & GD_FLG_RELOC ?
-				  CONFIG_CONSOLE_RECORD_OUT_SIZE :
-				  CONFIG_CONSOLE_RECORD_OUT_SIZE_F);
+	ret = membuf_new((struct membuf *)&gd->console_out,
+			 gd->flags & GD_FLG_RELOC ?
+				CONFIG_CONSOLE_RECORD_OUT_SIZE :
+				CONFIG_CONSOLE_RECORD_OUT_SIZE_F);
 	if (ret)
 		return ret;
-	ret = membuff_new((struct membuff *)&gd->console_in,
-			  CONFIG_CONSOLE_RECORD_IN_SIZE);
+	ret = membuf_new((struct membuf *)&gd->console_in,
+			 CONFIG_CONSOLE_RECORD_IN_SIZE);
 
 	/* Start recording from the beginning */
 	gd->flags |= GD_FLG_RECORD;
@@ -827,8 +827,8 @@ int console_record_init(void)
 
 void console_record_reset(void)
 {
-	membuff_purge((struct membuff *)&gd->console_out);
-	membuff_purge((struct membuff *)&gd->console_in);
+	membuf_purge((struct membuf *)&gd->console_out);
+	membuf_purge((struct membuf *)&gd->console_in);
 	gd->flags &= ~GD_FLG_RECORD_OVF;
 }
 
@@ -847,23 +847,23 @@ int console_record_readline(char *str, int maxlen)
 	if (console_record_isempty())
 		return -ENOENT;
 
-	return membuff_readline((struct membuff *)&gd->console_out, str,
+	return membuf_readline((struct membuf *)&gd->console_out, str,
 				maxlen, '\0', false);
 }
 
 int console_record_avail(void)
 {
-	return membuff_avail((struct membuff *)&gd->console_out);
+	return membuf_avail((struct membuf *)&gd->console_out);
 }
 
 bool console_record_isempty(void)
 {
-	return membuff_isempty((struct membuff *)&gd->console_out);
+	return membuf_isempty((struct membuf *)&gd->console_out);
 }
 
 int console_in_puts(const char *str)
 {
-	return membuff_put((struct membuff *)&gd->console_in, str, strlen(str));
+	return membuf_put((struct membuf *)&gd->console_in, str, strlen(str));
 }
 
 #endif
diff --git a/common/edid.c b/common/edid.c
index e2ac7100a88..e5aa4ca494f 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -16,6 +16,7 @@
 #include <linux/ctype.h>
 #include <linux/string.h>
 
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
 #define TIMING(c, ha, hfp, hbp, hsl, va, vfp, vbp, vsl, f)	\
 	.pixelclock = { (c), (c), (c) },			\
 	.hactive = { (ha), (ha), (ha) },			\
@@ -206,6 +207,7 @@ static const struct display_timing dmt_timings[] = {
 	{ TIMING(556188000, 4096, 8, 32, 40, 2160, 48, 8, 6,
 		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
 };
+#endif
 
 int edid_check_info(struct edid1_info *edid_info)
 {
@@ -417,6 +419,7 @@ static bool edid_get_standard_timing(struct edid1_info *edid, int i, unsigned in
 	return false;
 }
 
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
 static bool edid_find_valid_standard_timing(struct edid1_info *buf,
 					    struct display_timing *timing,
 					    bool (*mode_valid)(void *priv,
@@ -446,6 +449,7 @@ static bool edid_find_valid_standard_timing(struct edid1_info *buf,
 
 	return found;
 }
+#endif
 
 int edid_get_timing_validate(u8 *buf, int buf_size,
 			     struct display_timing *timing,
@@ -493,10 +497,12 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
 		}
 	}
 
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
 	/* Look for timing in Standard Timings */
 	if (!found)
 		found = edid_find_valid_standard_timing(edid, timing, mode_valid,
 							mode_valid_priv);
+#endif
 
 	if (!found)
 		return -EINVAL;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 97f542fcc8a..c08045f9c8d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -80,11 +80,10 @@ config SPL_MAX_SIZE
 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
 	default 0xec00 if OMAP34XX
 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
 	default 0xbfa0 if MACH_SUN50I_H616
 	default 0x7000 if RCAR_GEN3
 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+	default 0x7fa0 if ARCH_SUNXI
 	default 0x10000 if ASPEED_AST2600
 	default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
 	default 0x30000 if ARCH_SC5XX && (SC59X_64 || SC59X)
@@ -1450,6 +1449,24 @@ config SYS_SPI_U_BOOT_OFFS
 	 Address within SPI-Flash from where the u-boot payload is fetched
 	 from.
 
+config SYS_SPI_KERNEL_OFFS
+	hex "Falcon mode: address of kernel payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+	help
+	 Address within SPI-Flash from where the kernel payload is fetched
+	 in falcon boot.
+
+config SYS_SPI_ARGS_OFFS
+	hex "Falcon mode: address of args payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+	help
+	 Address within SPI-Flash from where the args payload (usually the
+	 dtb) is fetched in falcon boot.
+
+config SYS_SPI_ARGS_SIZE
+	hex "Falcon mode: size of args payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+
 config SPL_THERMAL
 	bool "Driver support for thermal devices"
 	help
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index c5478820a9b..7e0274a3058 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -11,12 +11,20 @@
 static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 			  ulong size, void *buf)
 {
+	struct legacy_img_hdr *header;
 	int ret;
 	loff_t actlen;
 
 	ret = ext4fs_read(buf, file_offset, size, &actlen);
 	if (ret)
 		return ret;
+
+	if (CONFIG_IS_ENABLED(OS_BOOT)) {
+		header = (struct legacy_img_hdr *)buf;
+		if (image_get_magic(header) != FDT_MAGIC)
+			return size;
+	}
+
 	return actlen;
 }
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index fce451b7664..f426a068ff9 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -47,6 +47,7 @@ static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 			  ulong size, void *buf)
 {
+	struct legacy_img_hdr *header;
 	loff_t actread;
 	int ret;
 	char *filename = load->priv;
@@ -55,6 +56,12 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 	if (ret)
 		return ret;
 
+	if (CONFIG_IS_ENABLED(OS_BOOT)) {
+		header = (struct legacy_img_hdr *)buf;
+		if (image_get_magic(header) != FDT_MAGIC)
+			return size;
+	}
+
 	return actread;
 }
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 49b4df60560..86506d6905c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -397,7 +397,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 	 * Use the address following the image as target address for the
 	 * device tree.
 	 */
-	image_info.load_addr = spl_image->load_addr + spl_image->size;
+	image_info.load_addr = ALIGN(spl_image->load_addr + spl_image->size, 8);
 
 	/* Figure out which device tree the board wants to use */
 	node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 5a26d7c31a4..0ed6afeacc6 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -57,6 +57,11 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
 		hang();
 	}
 
+	if (!IS_ALIGNED((uintptr_t)spl_image->fdt_addr, 8)) {
+		pr_err("SPL image loaded an improperly-aligned device tree\n");
+		hang();
+	}
+
 	/*
 	 * Originally, u-boot-spl will place DTB directly after the kernel,
 	 * but the size of the kernel did not include the BSS section, which
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 691a431a926..00dbd3011f0 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -82,13 +82,14 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
 #if CONFIG_IS_ENABLED(OS_BOOT)
 	if (spl_start_uboot()) {
 		int err = spl_load(spl_image, bootdev, &load, 0,
-				   CFG_SYS_SPI_KERNEL_OFFS);
+				   CONFIG_SYS_SPI_KERNEL_OFFS);
 
 		if (!err)
 			/* Read device tree. */
-			return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
-					      CFG_SYS_SPI_ARGS_SIZE,
-					      (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
+			return spi_flash_read(
+				flash, CONFIG_SYS_SPI_ARGS_OFFS,
+				CONFIG_SYS_SPI_ARGS_SIZE,
+				(void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
 	}
 #endif
 
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 13260edf3f0..24212082c3b 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -40,6 +40,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index a406e899d42..2fc5e35873f 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -38,6 +38,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index d865b123b90..634294e4766 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -41,6 +41,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 3f002aecfa7..c2ad1242d20 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -71,6 +71,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 227de53795b..b0d333d95c2 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -1,7 +1,9 @@
+#include<configs/am65x_evm_r5_defconfig>
+
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SYS_MALLOC_F_LEN=0x57000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -13,103 +15,17 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_DM_RESET=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c7effc
-CONFIG_SPL_BSS_MAX_SIZE=0xc00
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SIZE_LIMIT=0x7ec00
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
 CONFIG_MISC=y
-CONFIG_K3_AVS0=y
-# CONFIG_MMC is not set
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_OMAP_USB2_PHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_TPS62360=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
@@ -126,4 +42,34 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_DFU=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_FS_FAT=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_CMD_MMC=n
+CONFIG_ENV_OVERWRITE=n
+CONFIG_ENV_IS_IN_FAT=n
+CONFIG_DMA_CHANNELS=n
+CONFIG_TI_K3_NAVSS_UDMA=n
+CONFIG_SUPPORT_EMMC_BOOT=n
+CONFIG_MMC_HS200_SUPPORT=n
+CONFIG_SPL_MMC_HS200_SUPPORT=n
+CONFIG_MMC_SDHCI=n
+CONFIG_SPL_MMC_SDHCI_ADMA=n
+CONFIG_MMC_SDHCI_AM654=n
+CONFIG_MTD=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SOC_DEVICE=n
+CONFIG_SOC_DEVICE_TI_K3=n
+CONFIG_SOC_TI=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index 097bed62061..d6ef89c7b84 100644
--- a/configs/am68_sk_r5_defconfig
+++ b/configs/am68_sk_r5_defconfig
@@ -6,7 +6,6 @@ CONFIG_SOC_K3_J721S2=y
 CONFIG_TARGET_J721S2_R5_EVM=y
 
 CONFIG_ESM_K3=n
-CONFIG_K3_AVS0=n
 CONFIG_ESM_PMIC=n
 CONFIG_DM_REGULATOR_TPS65941=n
 CONFIG_PMIC_TPS65941=n
diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
new file mode 100644
index 00000000000..f09b5b603a2
--- /dev/null
+++ b/configs/an7581_evb_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_TEXT_BASE=0x81E00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x7c000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="airoha/en7581-evb"
+CONFIG_DM_RESET=y
+CONFIG_SYS_LOAD_ADDR=0x81800000
+CONFIG_BUILD_TARGET="u-boot.bin"
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="en7581-evb"
+CONFIG_SYS_PBSIZE=1049
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_SYS_MAXARGS=8
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_BIND=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DMA=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SHA512=y
diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig
index 0f12db3db84..7483f128bae 100644
--- a/configs/bananapi-f3_defconfig
+++ b/configs/bananapi-f3_defconfig
@@ -18,3 +18,4 @@ CONFIG_HUSH_PARSER=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_RESET_SPACEMIT_K1=y
diff --git a/configs/coreboot64-no-spl_defconfig b/configs/coreboot64-no-spl_defconfig
new file mode 100644
index 00000000000..dd07524560b
--- /dev/null
+++ b/configs/coreboot64-no-spl_defconfig
@@ -0,0 +1,62 @@
+CONFIG_X86=y
+CONFIG_TEXT_BASE=0x1110000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_X86_RUN_64BIT_NO_SPL=y
+CONFIG_VENDOR_COREBOOT=y
+CONFIG_TARGET_COREBOOT=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_MONITOR_BASE=0x01110000
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then bootflow boot; fi"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_LINE=y
+CONFIG_LOGF_FUNC=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
+CONFIG_TFTP_TSIZE=y
+CONFIG_USE_ROOTPATH=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_NVME_PCI=y
+# CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_VIDEO_COPY=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_GZIP is not set
+CONFIG_SMBIOS_PARSER=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 55f9bbaa1cf..a00a042ada6 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -53,6 +53,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="display5 > "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 4007c8900ce..9965e00a1d0 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -48,6 +48,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="display5 factory > "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 2448befb295..f9cb732357c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -43,6 +43,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_CMD_SPL=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_NAND=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index f6f00454aaa..81da64be811 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -40,6 +40,9 @@ CONFIG_SPL_NAND_ECC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_NAND=y
 CONFIG_BOOTP_DNS2=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 850ccd934b7..1d099a56ee8 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -39,6 +39,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index 5e422f673f4..fb3d7fc6238 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -80,6 +80,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_LCD_ENDEAVORU=y
 CONFIG_VIDEO_DSI_TEGRA30=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index d1f6eef178e..bf80a19bd96 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -63,6 +63,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x100000
+CONFIG_SYS_SPI_ARGS_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_SIZE=0x8000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index a69e2ba4c7b..288626c1511 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -87,6 +87,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth1"
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x42800000
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 4760f7509f5..3126ba3d771 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -6,7 +6,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
+CONFIG_SOC_K3_J7200=y
 CONFIG_TARGET_J7200_A72_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
@@ -144,6 +144,7 @@ CONFIG_SPI_FLASH_S28HX_T=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MULTIPLEXER=y
 CONFIG_MUX_MMIO=y
+CONFIG_SPL_MUX_MMIO=y
 CONFIG_PHY_TI_DP83869=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index ae5849baf13..0ae07ddf7c8 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x70000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
+CONFIG_SOC_K3_J7200=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_J7200_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -99,7 +99,9 @@ CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
 CONFIG_SPL_FS_LOADER=y
+CONFIG_ESM_K3=y
 CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 71e6c2061b3..6bc716650cf 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -151,6 +151,7 @@ CONFIG_SPI_FLASH_MT35XU=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MULTIPLEXER=y
 CONFIG_MUX_MMIO=y
+CONFIG_SPL_MUX_MMIO=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
diff --git a/configs/j742s2_evm_a72_defconfig b/configs/j742s2_evm_a72_defconfig
new file mode 100644
index 00000000000..e534ce4c2e3
--- /dev/null
+++ b/configs/j742s2_evm_a72_defconfig
@@ -0,0 +1,9 @@
+#include <configs/j784s4_evm_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J742S2_A72_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j742s2-evm"
+CONFIG_SPL_OF_LIST="ti/k3-j742s2-evm"
diff --git a/configs/j742s2_evm_r5_defconfig b/configs/j742s2_evm_r5_defconfig
new file mode 100644
index 00000000000..2be6318df76
--- /dev/null
+++ b/configs/j742s2_evm_r5_defconfig
@@ -0,0 +1,9 @@
+#include <configs/j784s4_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J742S2_R5_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-j742s2-r5-evm"
+CONFIG_SPL_OF_LIST="k3-j742s2-r5-evm"
diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig
index 0cbedb21797..dfeb16ac08e 100644
--- a/configs/mocha_defconfig
+++ b/configs/mocha_defconfig
@@ -28,6 +28,7 @@ CONFIG_SYS_PBSIZE=2086
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 870b7a1be10..25b0b11342d 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
 # CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f841b21c016..737a079eaa7 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 11a18d16f52..964d00a4085 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 316f74c278b..369bc0f2e0a 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 8be5963a433..97d4f9fc65f 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -15,7 +15,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2c13dd4dbc3..1a49bc2cf01 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig
new file mode 100644
index 00000000000..d4ae9dbb57c
--- /dev/null
+++ b/configs/ouya_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="ouya"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA30=y
+CONFIG_TARGET_OUYA=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (Ouya) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_TPS65910=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_I2C_EDID_STANDARD=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 661a484f7bf..ba4d38d100e 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -97,6 +97,7 @@ CONFIG_PINCTRL_QCOM_APQ8016=y
 CONFIG_PINCTRL_QCOM_APQ8096=y
 CONFIG_PINCTRL_QCOM_QCM2290=y
 CONFIG_PINCTRL_QCOM_QCS404=y
+CONFIG_PINCTRL_QCOM_SC7280=y
 CONFIG_PINCTRL_QCOM_SDM845=y
 CONFIG_PINCTRL_QCOM_SM6115=y
 CONFIG_PINCTRL_QCOM_SM8150=y
@@ -120,6 +121,7 @@ CONFIG_QCOM_RPMH=y
 CONFIG_SPMI_MSM=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
+CONFIG_SYSRESET_QCOM_PSHOLD=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig
new file mode 100644
index 00000000000..9bc1e1c70b7
--- /dev/null
+++ b/configs/qcom_ipq9574_mmc_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_NR_DRAM_BANKS=24
+CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq9574-rdp433"
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_EFI_BINARY_EXEC is not set
+# CONFIG_EFI_VARIABLE_FILE_STORE is not set
+# CONFIG_PXE_UTILS is not set
+# CONFIG_BOOTSTD is not set
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_BOOTDELAY=2
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_LOG_MAX_LEVEL=9
+CONFIG_LOG_DEFAULT_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PART=y
+CONFIG_OF_LIVE=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env"
+CONFIG_CLK=y
+CONFIG_CLK_QCOM_IPQ9574=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SCSI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000
+CONFIG_MSM_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_IPQ9574=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_QCOM=y
+CONFIG_RGMII=y
+CONFIG_PHY=y
+CONFIG_PHY_QCOM_QMP_UFS=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_SCSI=y
+CONFIG_MSM_SERIAL=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SOC_QCOM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x78b1000
+CONFIG_DEBUG_UART_MSM=y
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_TEXT_BASE=0x4A240000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
+CONFIG_OF_LIVE=y
+CONFIG_MSM_SERIAL=y
+CONFIG_DM_EVENT=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0
+CONFIG_PARTITIONS=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_MTD=y
+CONFIG_MTD_PARTS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_PARTITIONS=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_SCSI is not set
+# CONFIG_SPMI is not set
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 792ba06c2b8..58b1fbf132d 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -1,13 +1,13 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0x1110000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_BLOBLIST_SIZE_RELOC=0x20000
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_BLOBLIST_SIZE_RELOC=0x40000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4800
 CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
@@ -41,9 +41,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_CPU=y
-CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NET=y
 CONFIG_SPL_PCI=y
 CONFIG_SPL_PCH=y
 CONFIG_SPL_RTC=y
@@ -54,6 +52,7 @@ CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -61,6 +60,9 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="virtio"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="bzImage"
@@ -83,11 +85,11 @@ CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_CONSOLE_TRUETYPE=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
-CONFIG_FRAMEBUFFER_VESA_MODE=0x144
+CONFIG_VIDEO_BOCHS=y
+# CONFIG_VIDEO_VESA is not set
 CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_SPL_VIDEO=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_CMD_DHRYSTONE=y
 # CONFIG_GZIP is not set
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 0b0e10c795f..099d3f32d1b 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,7 +1,7 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0xFFF00000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_BLOBLIST_SIZE_RELOC=0x20000
+CONFIG_BLOBLIST_SIZE_RELOC=0x40000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
@@ -34,6 +34,7 @@ CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -42,6 +43,9 @@ CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="virtio"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="bzImage"
@@ -62,9 +66,9 @@ CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_CONSOLE_TRUETYPE=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
-CONFIG_FRAMEBUFFER_VESA_MODE=0x144
+CONFIG_VIDEO_BOCHS=y
+# CONFIG_VIDEO_VESA is not set
 CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_CMD_DHRYSTONE=y
 # CONFIG_GZIP is not set
diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
index b49a81dcd49..8dcf8e35ee0 100644
--- a/configs/r8a779g0_whitehawk_defconfig
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -3,6 +3,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN4=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARMV8_PSCI=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779g0-white-hawk"
diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig
index 7a1224b3f07..b1d970b6b7e 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -54,5 +55,12 @@ CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_RAA215300=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index ad1621a94dd..0b7940f4fb4 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -84,6 +85,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index bb29121bb15..2e5a4acf27d 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -93,6 +94,7 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 308aafc7dfe..11a536d714c 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -15,6 +15,7 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -93,6 +94,7 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index ac14dd53838..86cb5c287be 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -15,6 +15,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -92,6 +93,7 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 6db27280f0f..014f0093eee 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -99,6 +100,7 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index 76556526516..efe23115f62 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
@@ -103,6 +104,7 @@ CONFIG_MACB=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_ATMEL_USART=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 7960b2ef42e..1236ce474a6 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -267,6 +267,7 @@ CONFIG_WDT_SANDBOX=y
 CONFIG_WDT_ALARM_SANDBOX=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXFAT=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 0b3c765389c..87f21fdbd12 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -352,6 +352,7 @@ CONFIG_WDT_ALARM_SANDBOX=y
 CONFIG_WDT_FTWDT010=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXFAT=y
 CONFIG_ADDR_MAP=y
 CONFIG_PANIC_HANG=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 88a75c03259..f70e3db4441 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -27,7 +27,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};nvme scan"
 CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 91074e998df..3e2db0cb7d0 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -90,6 +90,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index 12be929600e..e738bd232d0 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -83,6 +83,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1004
 CONFIG_USB_GADGET_PRODUCT_NUM=0x7100
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_BACKLIGHT_LM3533=y
 CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 1578edf6a41..6859e24b731 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -51,6 +51,9 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x280000
+CONFIG_SYS_SPI_ARGS_OFFS=0x200000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SYS_MAXARGS=32
 # CONFIG_BOOTM_NETBSD is not set
 CONFIG_CMD_IMLS=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 6f868739079..1f8e8c348eb 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -58,6 +58,9 @@ CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_SMBIOS=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 9641998a2ab..abd1e1bb574 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -56,6 +56,9 @@ CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_SMBIOS=y
diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII
deleted file mode 100644
index 05ab20376f3..00000000000
--- a/doc/README.bitbangMII
+++ /dev/null
@@ -1,39 +0,0 @@
-This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
-support an arbitrary number of mii buses. This feature is useful when your
-board uses different mii buses for different phys and all (or a part) of these
-buses are implemented via bit-banging mode.
-
-The driver requires that the following macros should be defined into the board
-configuration file:
-
-CONFIG_BITBANGMII	- Enable the miiphybb driver
-
-The board code needs to fill the bb_miiphy_buses[] array with a record for
-each required bus and declare the bb_miiphy_buses_num variable with the
-number of mii buses. The record (struct bb_miiphy_bus) has the following
-fields/callbacks (see miiphy.h for details):
-
-char name[]	       - The symbolic name that must be equal to the MII bus
-			 registered name
-int (*init)()	       - Initialization function called at startup time (just
-			 before the Ethernet initialization)
-int (*mdio_active)()   - Activate the MDIO pin as output
-int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
-int (*set_mdio)()      - Write the MDIO pin
-int (*get_mdio)()      - Read the MDIO pin
-int (*set_mdc)()       - Write the MDC pin
-int (*delay)()	       - Delay function
-void *priv	       - Private data used by board specific code
-
-The board code will look like:
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... },
- { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... },
- ...
-};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
-			  sizeof(bb_miiphy_buses[0]);
-
-2009 Industrie Dial Face S.p.A.
-     Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
diff --git a/doc/README.fuse b/doc/README.fuse
deleted file mode 100644
index 1bc91c44a6a..00000000000
--- a/doc/README.fuse
+++ /dev/null
@@ -1,67 +0,0 @@
-Fuse API functions and commands
-
-The fuse API allows to control a fusebox and how it is used by the upper
-hardware layers.
-
-A fuse corresponds to a single non-volatile memory bit that can be programmed
-(i.e. blown, set to 1) only once. The programming operation is irreversible. A
-fuse that has not been programmed reads 0.
-
-Fuses can be used by SoCs to store various permanent configuration and data,
-e.g. boot configuration, security configuration, MAC addresses, etc.
-
-A fuse word is the smallest group of fuses that can be read at once from the
-fusebox control IP registers. This is limited to 32 bits with the current API.
-
-A fuse bank is the smallest group of fuse words having a common ID, as defined
-by each SoC.
-
-Upon startup, the fusebox control IP reads the fuse values and stores them to a
-volatile shadow cache.
-
-See the README files of the drivers implementing this API in order to know the
-SoC- and implementation-specific details.
-
-Functions / commands:
-
-   int fuse_read(u32 bank, u32 word, u32 *val);
-   fuse read <bank> <word> [<cnt>]
-      Read fuse words from the shadow cache.
-
-   int fuse_sense(u32 bank, u32 word, u32 *val);
-   fuse sense <bank> <word> [<cnt>]
-      Sense - i.e. read directly from the fusebox, skipping the shadow cache -
-      fuse words. This operation does not update the shadow cache.
-
-      This is useful to know the true value of fuses if an override has been
-      performed (see below).
-
-   int fuse_prog(u32 bank, u32 word, u32 val);
-   fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
-      Program fuse words. This operation directly affects the fusebox and is
-      irreversible. The shadow cache is updated accordingly or not, depending on
-      each IP.
-
-      Only the bits to be programmed should be set in the input value (i.e. for
-      fuse bits that have already been programmed and hence should be left
-      unchanged by a further programming, it is preferable to clear the
-      corresponding bits in the input value in order not to perform a new
-      hardware programming operation on these fuse bits).
-
-   int fuse_override(u32 bank, u32 word, u32 val);
-   fuse override <bank> <word> <hexval> [<hexval>...]
-      Override fuse words in the shadow cache.
-
-      The fusebox is unaffected, so following this operation, the shadow cache
-      may differ from the fusebox values. Read or sense operations can then be
-      used to get the values from the shadow cache or from the fusebox.
-
-      This is useful to change the behaviors linked to some cached fuse values,
-      either because this is needed only temporarily, or because some of the
-      fuses have already been programmed or are locked (if the SoC allows to
-      override a locked fuse).
-
-Configuration:
-
-   CONFIG_CMD_FUSE
-      Define this to enable the fuse commands.
diff --git a/doc/README.pxe b/doc/README.pxe
index af2e64a5776..9fff2cd5ae9 100644
--- a/doc/README.pxe
+++ b/doc/README.pxe
@@ -160,7 +160,7 @@ kernel <path>	    - if this label is chosen, use tftp to retrieve the kernel
 		      It will passed to bootm with that address.
 		      (see: doc/uImage.FIT/command_syntax_extensions.txt)
 		      It useful for overlay selection in pxe file
-		      (see: doc/uImage.FIT/overlay-fdt-boot.txt)
+		      (see: doc/usage/fit/overlay-fdt-boot.rst).
 
 fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT
                       overlay(s) at <path>. it will be temporarily stored at the
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 84c135e02c1..7ad1137c94a 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -43,6 +43,7 @@ Board-specific doc
    microsoft/index
    nxp/index
    openpiton/index
+   ouya/index
    phytec/index
    purism/index
    qualcomm/index
diff --git a/doc/board/ouya/index.rst b/doc/board/ouya/index.rst
new file mode 100644
index 00000000000..7413240a1b8
--- /dev/null
+++ b/doc/board/ouya/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+OUYA
+====
+
+.. toctree::
+   :maxdepth: 2
+
+   ouya
diff --git a/doc/board/ouya/ouya.rst b/doc/board/ouya/ouya.rst
new file mode 100644
index 00000000000..641affc6294
--- /dev/null
+++ b/doc/board/ouya/ouya.rst
@@ -0,0 +1,124 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Ouya Game Console (ouya)
+=======================================
+
+``DISCLAMER!`` Moving your Ouya to use U-Boot assumes replacement of the
+vendor bootloader. Vendor android firmwares will no longer be able to run on the
+device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make ouya_defconfig
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+    $ git clone https://gitlab.com/grate-driver/re-crypt.git
+    $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+    $ ./re-crypt.py --dev ouya
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM. Regardless of the method bct and bootloader
+will end up in boot0 and boot1 partitions of eMMC.
+
+Flashing with the NV3P protocol
+*******************************
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+    $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct -b android_bootloader.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, interrupt bootflow by pressing ``CTRL + C`` (USB keyboard
+must be plugged in before U-Boot is preloaded, else it will not work), input
+``bootmenu`` from the keyboard and hit enter. The bootmenu will appear. There, select
+``fastboot`` using the up and down arrows and enter key. After, on host PC, do:
+
+.. code-block:: bash
+
+    $ fastboot flash 0.1 bct.img
+    $ fastboot flash 0.2 ebt.img
+    $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+bootmenu provides entries to mount eMMC as mass storage, fastboot, reboot,
+reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the USB. Enter
+bootmenu, choose update bootloader option with Enter and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 8c7969987a9..66bc922033a 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -10,3 +10,4 @@ Qualcomm
    rb3gen2
    board
    debugging
+   rdp
diff --git a/doc/board/qualcomm/rdp.rst b/doc/board/qualcomm/rdp.rst
new file mode 100644
index 00000000000..fd14f1d9829
--- /dev/null
+++ b/doc/board/qualcomm/rdp.rst
@@ -0,0 +1,55 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. sectionauthor:: Varadarajan Narayanan <quic_varada@quicinc.com>
+
+Qualcomm Reference Design Platform (RDP)
+========================================
+
+Qualcomm RDPs are development boards based on the Qualcomm IPQ series of
+SoCs. These SoCs are used as the application processors in WiFi router
+platforms. RDPs come in multiple variants with differences in storage
+medium (NOR, NAND, MMC), no. of USB and PCIe ports, n/w ports etc.
+
+.. _Qualcomm's product page: https://www.qualcomm.com/products/internet-of-things/networking/wi-fi-networks/networking-pro-series/qualcomm-networking-pro-820-platform
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``IPQ9574``::
+
+  $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+  $ make qcom_ipq9574_mmc_defconfig
+  $ make -j8
+
+This will build ``u-boot.elf`` in the configured output directory.
+
+Although the RDPs do not have secure boot set up by default, the firmware still
+expects firmware ELF images to be "signed". The signature does not provide any
+security in this case, but it provides the firmware with some required metadata.
+
+To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_::
+
+  $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf
+
+Then install the resulting ``u-boot.mbn`` to the ``0:APPSBL`` partition
+on your device with::
+
+  IPQ9574# tftpboot path/to/u-boot.mbn
+  IPQ9574# mmc part (note down the start & end block no.s of '0:APPSBL' partition)
+  IPQ9574# mmc erase <start blk no> <count>
+  IPQ9574# mmc write $fileaddr <blk no> <count>
+
+U-Boot should be running after a reboot (``reset``).
+
+.. WARNING
+	Boards with newer software versions would automatically go the emergency
+	download (EDL) mode if U-Boot is not functioning as expected. If its a
+	runtime failure at Uboot, the system will get reset (due to watchdog)
+	and XBL will try to boot from next bank and if Bank B also doesn't have
+	a functional image and is not booting fine, then the system will enter
+	EDL.  A tool like bkerler's `edl`_ can be used for flashing with the
+	firehose loader binary appropriate for the board.
+
+	Note that the support added is very basic. Restoring the original U-Boot
+	on boards with older version of the software requires a debugger.
+
+.. _qtestsign: https://github.com/msm8916-mainline/qtestsign
+.. _edl: https://github.com/bkerler/edl
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index 72ab6ddfbf6..2cba1b6dc56 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -7,6 +7,5 @@ StarFive
    :maxdepth: 1
 
    milk-v_mars
-   milk-v_mars_cm
    pine64_star64
    visionfive2
diff --git a/doc/board/starfive/milk-v_mars_cm.rst b/doc/board/starfive/milk-v_mars_cm.rst
deleted file mode 100644
index 52d4e5e9098..00000000000
--- a/doc/board/starfive/milk-v_mars_cm.rst
+++ /dev/null
@@ -1,193 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-Milk-V Mars CM
-==============
-
-U-Boot for the Milk-V Mars CM uses the same U-Boot binaries as the VisionFive 2
-board. In U-Boot SPL the actual board is detected and the device-tree patched
-accordingly.
-
-The Milk-V Mars CM Lite comes without eMMC and needs a different pin muxing
-than the Milk-V Mars CM. The availability and size of the eMMC shows up in the
-serial number displayed by the *mac* command, e.g.
-MARC-V10-2340-D002E016-00000304. The number after the E is the MMC size. U-Boot
-takes a value of E000 as an indicator for the Lite version. Unfortunately the
-vendor has not set this value correctly on some Lite boards.
-
-Please, use CONFIG_STARFIVE_NO_EMMC=y if EEPROM data indicates eMMC is present
-on the Milk-V Mars CM Lite. Otherwise you will not be able to read from the
-SD-card.
-
-The serial number can be corrected using the *mac* command:
-
-.. code-block::
-
-    mac read_eeprom
-    mac product_id MARC-V10-2340-D002E000-00000304
-    mac write_eeprom
-
-.. note::
-
-   The *mac initialize* command overwrites the vendor string and the MAC
-   addresses. This is why it is avoided here.
-
-By default the EEPROM is write protected. The write protection may be overcome
-by connecting the "GND" and "EN" test pads on top of the module.
-
-Building
-~~~~~~~~
-
-1. Add the RISC-V toolchain to your PATH.
-2. Setup ARCH & cross compilation environment variable:
-
-.. code-block:: none
-
-   export CROSS_COMPILE=<riscv64 toolchain prefix>
-
-The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
-is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
-Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
-a current release.
-
-.. code-block:: console
-
-	git clone https://github.com/riscv/opensbi.git
-	cd opensbi
-	make PLATFORM=generic FW_TEXT_START=0x40000000
-
-(*FW_TEXT_START* is not needed anymore after OpenSBI patch d4d2582eef7a
-"firmware: remove FW_TEXT_START" which should appear in OpenSBI 1.5.)
-
-Now build the U-Boot SPL and U-Boot proper.
-
-.. code-block:: console
-
-	cd <U-Boot-dir>
-	make starfive_visionfive2_defconfig
-	make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
-
-This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
-as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
-
-Device-tree selection
-~~~~~~~~~~~~~~~~~~~~~
-
-Depending on the board version U-Boot sets variable $fdtfile to either
-starfive/jh7110-milkv-mars-cm.dtb (with eMMC storage) or
-starfive/jh7110-milkv-mars-cm-lite.dtb (without eMMC storage).
-
-To overrule this selection the variable can be set manually and saved in the
-environment
-
-::
-
-    env set fdtfile my_device-tree.dtb
-    env save
-
-or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
-provide a default value.
-
-The variable *$fdtfile* is used in the boot process to automatically load
-a device-tree provided by the operating system. For details of the boot
-process refer to the :doc:`/develop/bootstd/index`
-description.
-
-Boot source selection
-~~~~~~~~~~~~~~~~~~~~~
-
-The low speed connector nRPIBOOT line is used to switch the boot source.
-
-* If nRPIBOOT is connected to ground, the board boots from UART.
-* If nRPIBOOT is not connected, the board boots from SPI flash.
-
-Compute module boards typically have a switch or jumper for this line.
-
-Flashing a new U-Boot version
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-U-Boot SPL is provided as file spl/u-boot-spl.bin.normal.out. Main U-Boot is
-in file u-boot.itb.
-
-Assuming your new U-Boot version is on partition 1 of an SD-card you could
-install it to the SPI flash with:
-
-::
-
-    sf probe
-    load mmc 0:1 $kernel_addr_r u-boot-spl.bin.normal.out
-    sf update $kernel_addr_r 0 $filesize
-    load mmc 0:1 $kernel_addr_r u-boot.itb
-    sf update $kernel_addr_r 0x100000 $filesize
-
-For loading the files from a TFTP server refer to the dhcp and tftpboot
-commands.
-
-After updating U-Boot you may want to reboot and reset the environment to the
-default.
-
-::
-
-    env default -f -a
-    env save
-
-Booting from UART
-~~~~~~~~~~~~~~~~~
-
-For booting via UART U-Boot must be built with CONFIG_SPL_YMODEM_SUPPORT=y.
-
-With nRPIBOOT connected to ground for UART boot, power the board and upload
-u-boot-spl.bin.normal.out via XMODEM. Then upload u-boot.itb via YMODEM.
-
-The XMODEM implementation in the boot ROM is not fully specification compliant.
-It sends too many NAKs in a row. Tio is a terminal emulation that tolerates
-these faults.
-
-::
-
-    $ tio -b 115200 --databits 8 --flow none --stopbits 1 /dev/ttyUSB0
-    [08:14:54.700] tio v2.7
-    [08:14:54.700] Press ctrl-t q to quit
-    [08:14:54.701] Connected
-
-    (C)StarFive
-    CCC
-    (C)StarFive
-    CCCCCCCC
-
-Press *ctrl-t x* to initiate XMODEM-1K transfer.
-
-::
-
-    [08:15:14.778] Send file with XMODEM
-    [08:15:22.459] Sending file 'u-boot-spl.bin.normal.out'
-    [08:15:22.459] Press any key to abort transfer
-    ........................................................................
-    .......................................................................|
-    [08:15:22.459] Done
-
-    U-Boot SPL 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200)
-    DDR version: dc2e84f0.
-    Trying to boot from UART
-    CC
-
-Press *ctrl-t y* to initiate YMODEM transfer.
-
-::
-
-    [08:15:50.331] Send file with YMODEM
-    [08:15:53.540] Sending file 'u-boot.itb'
-    [08:15:53.540] Press any key to abort transfer
-    ........................................................................
-    …
-    ...............|
-    [08:15:53.540] Done
-    Loaded 1040599 bytes
-
-
-    U-Boot 2024.07-rc1-00075-gd6a4ab20097 (Apr 25 2024 - 16:32:10 +0200)
-
-Booting from SPI flash
-~~~~~~~~~~~~~~~~~~~~~~
-
-With nRPIBOOT disconnected from ground for SPI boot, power up the board. You
-should see the U-Boot prompt on the serial console.
diff --git a/doc/build/docker.rst b/doc/build/docker.rst
index 01ed3505090..4974a98d4af 100644
--- a/doc/build/docker.rst
+++ b/doc/build/docker.rst
@@ -12,7 +12,9 @@ You will need a multi-platform container, otherwise this error is shown::
     ERROR: Multi-platform build is not supported for the docker driver.
     Switch to a different driver, or turn on the containerd image store, and try again.
 
-You can add a simple one with::
+You can add a simple one with:
+
+.. code-block:: bash
 
     sudo docker buildx create --name multiarch --driver docker-container --use
 
@@ -20,7 +22,9 @@ This will result in a builder that will use QEMU for the non-native
 architectures request in a build.  While both amd64 and arm64 happen in
 parallel, the non-native part will take considerably longer as it must use QEMU
 to emulate the foreign code.  An alternative, if you have accesss to reasonably
-fast amd64 (i.e. 64-bit x86) and arm64 machines is::
+fast amd64 (i.e. 64-bit x86) and arm64 machines is:
+
+.. code-block:: bash
 
     sudo docker buildx create --name multiarch-multinode --node localNode --bootstrap --use
     sudo docker buildx create --name multiarch-multinode --append --node remoteNode --bootstrap ssh://user@host
@@ -28,7 +32,7 @@ fast amd64 (i.e. 64-bit x86) and arm64 machines is::
 And this will result in a builder named multiarch-multinode that will build
 each platform natively on each node.
 
-To build the image yourself::
+To build the image yourself:
 
 .. code-block:: bash
 
diff --git a/doc/develop/bitbangmii.rst b/doc/develop/bitbangmii.rst
new file mode 100644
index 00000000000..35a4a0cb7f9
--- /dev/null
+++ b/doc/develop/bitbangmii.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>, Industrie Dial Face S.p.A., 2009
+
+Bit-banged MII bus support
+==========================
+
+The miiphybb ( Bit-banged MII bus driver ) supports an arbitrary number of
+MII buses. This feature is useful when a driver uses different MII buses for
+different PHYs and all (or a part) of these buses are implemented via
+bit-banging mode.
+
+The driver requires that the following macro is defined in the board
+configuration file:
+
+* CONFIG_BITBANGMII - Enable the miiphybb driver
+
+The driver code needs to allocate a regular MDIO device using mdio_alloc()
+and assign .read and .write accessors which wrap bb_miiphy_read() and
+bb_miiphy_write() functions respectively. The bb_miiphy_read() and
+bb_miiphy_write() functions take a pointer to a callback structure,
+struct bb_miiphy_bus_ops. The struct bb_miiphy_bus_ops has the following
+fields/callbacks (see miiphy.h for details):
+
+.. code-block:: c
+
+    int (*mdio_active)()   // Activate the MDIO pin as output
+    int (*mdio_tristate)() // Activate the MDIO pin as input/tristate pin
+    int (*set_mdio)()      // Write the MDIO pin
+    int (*get_mdio)()      // Read the MDIO pin
+    int (*set_mdc)()       // Write the MDC pin
+    int (*delay)()         // Delay function
+
+The driver code will look like:
+
+.. code-block:: c
+
+    static const struct bb_miiphy_bus_ops ravb_bb_miiphy_bus_ops = {
+        .mdio_active      = ravb_bb_mdio_active,
+        .mdio_tristate    = ravb_bb_mdio_tristate,
+        .set_mdio         = ravb_bb_set_mdio,
+        .get_mdio         = ravb_bb_get_mdio,
+        .set_mdc          = ravb_bb_set_mdc,
+        .delay            = ravb_bb_delay,
+    };
+
+    static int ravb_bb_miiphy_read(struct mii_dev *miidev, int addr,
+                                   int devad, int reg)
+    {
+        return bb_miiphy_read(miidev, &ravb_bb_miiphy_bus_ops,
+                              addr, devad, reg);
+    }
+
+    static int ravb_bb_miiphy_write(struct mii_dev *miidev, int addr,
+                                    int devad, int reg, u16 value)
+    {
+        return bb_miiphy_write(miidev, &ravb_bb_miiphy_bus_ops,
+                               addr, devad, reg, value);
+    }
+
+    static int ravb_probe(struct udevice *dev)
+    {
+        struct mii_dev *mdiodev;
+    ...
+        mdiodev = mdio_alloc();
+        if (!mdiodev)
+            return -ENOMEM;
+
+        mdiodev->read = ravb_bb_miiphy_read;
+        mdiodev->write = ravb_bb_miiphy_write;
+        mdiodev->priv = eth;
+        snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
+
+        ret = mdio_register(mdiodev);
+    ...
+    }
diff --git a/doc/develop/bootstd/overview.rst b/doc/develop/bootstd/overview.rst
index e3ce97cc4f5..9fe5630ab16 100644
--- a/doc/develop/bootstd/overview.rst
+++ b/doc/develop/bootstd/overview.rst
@@ -235,8 +235,9 @@ means that `default_get_bootflow()` is used. This simply obtains the
 block device and calls a bootdev helper function to do the rest. The
 implementation of `bootdev_find_in_blk()` checks the partition table, and
 attempts to read a file from a filesystem on the partition number given by the
-`@iter->part` parameter. If there are any bootable partitions in the table,
-then only bootable partitions are considered.
+`@iter->part` parameter. If there are any bootable partitions in the table and
+the BOOTFLOWIF_ONLY_BOOTABLE flag is set in `@iter->flags`, then only bootable
+partitions are considered.
 
 Each bootdev has a priority, which indicates the order in which it is used,
 if `boot_targets` is not used. Faster bootdevs are used first, since they are
diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst
index 92f638a0204..30093737200 100644
--- a/doc/develop/driver-model/design.rst
+++ b/doc/develop/driver-model/design.rst
@@ -843,8 +843,10 @@ steps (see device_probe()):
       activated and 'known' by the uclass.
 
 For some platforms, certain devices must be probed to get the platform into
-a working state. To help with this, drivers marked with DM_FLAG_PROBE_AFTER_BIND
-will be probed immediately after all devices are bound. For now, this happens in
+a working state. To help with this, devices marked with DM_FLAG_PROBE_AFTER_BIND
+will be probed immediately after all devices are bound. This flag must be set
+on the device in its ``bind()`` function with
+``dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND)``. For now, this happens in
 SPL, before relocation and after relocation. See the call to ``dm_autoprobe()``
 for where this is done.
 
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index d9f2a838207..c907f8c9c2c 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -9,6 +9,7 @@ General
 .. toctree::
    :maxdepth: 1
 
+   bitbangmii
    board_best_practices
    codingstyle
    designprinciples
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index dc5bb340ff2..cbbc2bad0eb 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -51,14 +51,15 @@ Examples::
 Current Status
 --------------
 
-* U-Boot v2025.01 was released on Mon 06 January 2025.
+* U-Boot v2025.04 was released on Monday, 07 April 2025.
 
-* The Merge Window for the next release (v2025.04) is **closed**.
+* The Merge Window for the next release (v2025.07) is **open** until the -rc1
+  release on Monday, 28 April 2025.
 
-* The next branch is now **open** with the -rc2 release on Mon 10 February
+* The next branch is now **closed** until the -rc2 release on Monday, 12 May
   2025.
 
-* Release "v2025.04" is scheduled for 07 April 2025.
+* Release "v2025.07" is scheduled for Monday, 07 July 2025.
 
 Future Releases
 ---------------
@@ -66,28 +67,28 @@ Future Releases
 .. The following commented out dates are for when release candidates are
    planned to be tagged.
 
-For the next scheduled release, release candidates were made on::
+.. For the next scheduled release, release candidates were made on::
 
-* U-Boot v2025.04-rc1 was released on Mon 27 January 2025.
+.. * U-Boot v2025.07-rc1 was released on Mon 21 April 2025.
 
-* U-Boot v2025.04-rc2 was released on Mon 10 February 2025.
+.. * U-Boot v2025.07-rc2 was released on Mon 12 May 2025.
 
-* U-Boot v2025.04-rc3 was released on Mon 24 February 2025.
+.. * U-Boot v2025.07-rc3 was released on Mon 26 May 2025.
 
-* U-Boot v2025.04-rc4 was released on Mon 10 March 2025.
+.. * U-Boot v2025.07-rc4 was released on Mon 09 June 2025.
 
-.. * U-Boot v2025.04-rc5 was released on Mon 24 March 2025.
+.. * U-Boot v2025.07-rc5 was released on Mon 23 June 2025.
 
 Please note that the following dates are planned only and may be deviated from
 as needed.
 
-* "v2025.04": end of MW = Mon, Jan 27, 2025; release = Mon, Apr 07, 2025
+* "v2025.07": end of MW = Mon, Apr 28, 2025; release = Mon, Jul 07, 2025
 
-* "v2025.07": end of MW = Mon, Apr 21, 2025; release = Mon, Jul 07, 2025
+* "v2025.10": end of MW = Mon, Jul 28, 2025; release = Mon, Oct 06, 2025
 
-* "v2025.10": end of MW = Mon, Jul 21, 2025; release = Mon, Oct 06, 2025
+* "v2026.01": end of MW = Mon, Oct 27, 2025; release = Mon, Jan 05, 2026
 
-* "v2026.01": end of MW = Mon, Oct 20, 2025; release = Mon, Jan 05, 2026
+* "v2025.04": end of MW = Mon, Jan 26, 2026; release = Mon, Apr 06, 2026
 
 Previous Releases
 -----------------
@@ -96,6 +97,8 @@ Note: these statistics are generated by our fork of `gitdm
 <https://source.denx.de/u-boot/gitdm>`_, which was originally created by
 Jonathan Corbet.
 
+* :doc:`statistics/u-boot-stats-v2025.04` which was released on 07 April 2025.
+
 * :doc:`statistics/u-boot-stats-v2025.01` which was released on 06 January 2025.
 
 * :doc:`statistics/u-boot-stats-v2024.10` which was released on 07 October 2024.
diff --git a/doc/develop/statistics/u-boot-stats-v2025.04.rst b/doc/develop/statistics/u-boot-stats-v2025.04.rst
new file mode 100644
index 00000000000..47944616e25
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2025.04.rst
@@ -0,0 +1,788 @@
+:orphan:
+
+Release Statistics for U-Boot v2025.04
+======================================
+
+* Processed 1264 changesets from 176 developers
+
+* 25 employers found
+
+* A total of 221825 lines added, 99018 removed (delta 122807)
+
+.. table:: Developers with the most changesets
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Simon Glass                           222 (17.6%)
+   Marek Vasut                           106 (8.4%)
+   Jonas Karlman                         69 (5.5%)
+   Heinrich Schuchardt                   58 (4.6%)
+   Tom Rini                              51 (4.0%)
+   Weijie Gao                            40 (3.2%)
+   Michal Simek                          31 (2.5%)
+   Peng Fan                              29 (2.3%)
+   Raymond Mao                           26 (2.1%)
+   Adriano Cordova                       25 (2.0%)
+   Patrice Chotard                       23 (1.8%)
+   Ilias Apalodimas                      22 (1.7%)
+   Neil Armstrong                        19 (1.5%)
+   Heiko Schocher                        17 (1.3%)
+   Christian Marangi                     15 (1.2%)
+   Hal Feng                              14 (1.1%)
+   Sam Protsenko                         14 (1.1%)
+   J. Neuschäfer                         13 (1.0%)
+   Svyatoslav Ryhel                      13 (1.0%)
+   Venkatesh Yadav Abbarapu              12 (0.9%)
+   Mikhail Kshevetskiy                   12 (0.9%)
+   Jerome Forissier                      9 (0.7%)
+   Stefan Eichenberger                   9 (0.7%)
+   Daniel Schultz                        9 (0.7%)
+   Caleb Connolly                        9 (0.7%)
+   Santhosh Kumar K                      9 (0.7%)
+   Philippe Reynes                       9 (0.7%)
+   Paul HENRYS                           9 (0.7%)
+   Tianling Shen                         8 (0.6%)
+   Wadim Egorov                          8 (0.6%)
+   Neha Malcom Francis                   8 (0.6%)
+   Vaishnav Achath                       8 (0.6%)
+   Andre Przywara                        7 (0.6%)
+   Yannic Moog                           7 (0.6%)
+   Udit Kumar                            6 (0.5%)
+   Judith Mendez                         6 (0.5%)
+   Andrew Goodbody                       6 (0.5%)
+   Ibai Erkiaga                          6 (0.5%)
+   Tim Harvey                            6 (0.5%)
+   Manorit Chawdhry                      6 (0.5%)
+   Evgeny Bachinin                       6 (0.5%)
+   Yuri Zaporozhets                      6 (0.5%)
+   Richard Weinberger                    6 (0.5%)
+   Guillaume La Roque                    6 (0.5%)
+   Enrico Leto                           6 (0.5%)
+   Varadarajan Narayanan                 5 (0.4%)
+   Jayesh Choudhary                      5 (0.4%)
+   Junhui Liu                            5 (0.4%)
+   Christoph Niedermaier                 5 (0.4%)
+   Fabio Estevam                         4 (0.3%)
+   Yao Zi                                4 (0.3%)
+   Sam Edwards                           4 (0.3%)
+   Ye Li                                 4 (0.3%)
+   Padmarao Begari                       4 (0.3%)
+   Liya Huang                            4 (0.3%)
+   Siddharth Vadapalli                   4 (0.3%)
+   Michael Chang                         4 (0.3%)
+   Love Kumar                            4 (0.3%)
+   Alexander Dahl                        4 (0.3%)
+   Boon Khai Ng                          4 (0.3%)
+   Bryan Brattlof                        4 (0.3%)
+   Alexander Sverdlin                    4 (0.3%)
+   Aparna Patra                          4 (0.3%)
+   Garrett Giordano                      4 (0.3%)
+   Yunus Bas                             4 (0.3%)
+   Reid Tonking                          4 (0.3%)
+   Zixun LI                              4 (0.3%)
+   Alexey Romanov                        4 (0.3%)
+   Leonard Anderweit                     3 (0.2%)
+   Mattijs Korpershoek                   3 (0.2%)
+   E Shattow                             3 (0.2%)
+   Sam Day                               3 (0.2%)
+   Johan Jonker                          3 (0.2%)
+   Paul Kocialkowski                     3 (0.2%)
+   Anurag Dutta                          3 (0.2%)
+   Yu-Chien Peter Lin                    3 (0.2%)
+   Duje Mihanović                        3 (0.2%)
+   david regan                           3 (0.2%)
+   Dmitry Rokosov                        3 (0.2%)
+   FUKAUMI Naoki                         3 (0.2%)
+   Maksim Kiselev                        3 (0.2%)
+   Thomas Bonnefille                     3 (0.2%)
+   Christoph Stoidner                    3 (0.2%)
+   Rasmus Villemoes                      3 (0.2%)
+   Heiko Stuebner                        2 (0.2%)
+   Vincent Stehlé                        2 (0.2%)
+   Fiona Klute                           2 (0.2%)
+   Benjamin Lemouzy                      2 (0.2%)
+   Maks Mishin                           2 (0.2%)
+   Patrick Delaunay                      2 (0.2%)
+   Aashvij Shenai                        2 (0.2%)
+   Prasad Kummari                        2 (0.2%)
+   Sam Shih                              2 (0.2%)
+   Mark Tomlinson                        2 (0.2%)
+   Rufus Segar                           2 (0.2%)
+   Jim Liu                               2 (0.2%)
+   Andrey Skvortsov                      2 (0.2%)
+   Christopher Obbard                    2 (0.2%)
+   Alice Guo                             2 (0.2%)
+   Mayuresh Chitale                      2 (0.2%)
+   Shree Ramamoorthy                     2 (0.2%)
+   Lothar Rubusch                        2 (0.2%)
+   Frank Sae                             2 (0.2%)
+   Kongyang Liu                          2 (0.2%)
+   Gokul Praveen                         2 (0.2%)
+   Benedikt Spranger                     2 (0.2%)
+   Andrew Davis                          1 (0.1%)
+   Quentin Schulz                        1 (0.1%)
+   Paul Barker                           1 (0.1%)
+   Michael Walle                         1 (0.1%)
+   Kory Maincent                         1 (0.1%)
+   Ben Schneider                         1 (0.1%)
+   Hendrik Donner                        1 (0.1%)
+   Peter Robinson                        1 (0.1%)
+   Martin Stolpe                         1 (0.1%)
+   Andrea della Porta                    1 (0.1%)
+   Diederik de Haas                      1 (0.1%)
+   Sumit Garg                            1 (0.1%)
+   Greg Malysa                           1 (0.1%)
+   Kever Yang                            1 (0.1%)
+   Justin Klaassen                       1 (0.1%)
+   Julius Lehmann                        1 (0.1%)
+   Joao Marcos Costa                     1 (0.1%)
+   Chen-Yu Tsai                          1 (0.1%)
+   Gao Xiang                             1 (0.1%)
+   ZHANG Yuntian                         1 (0.1%)
+   Nathan Morrisson                      1 (0.1%)
+   Michael Ferolito                      1 (0.1%)
+   Benjamin Szőke                        1 (0.1%)
+   John Crispin                          1 (0.1%)
+   Huan Zhou                             1 (0.1%)
+   Josua Mayer                           1 (0.1%)
+   Tony Dinh                             1 (0.1%)
+   Michael Trimarchi                     1 (0.1%)
+   Alif Zakuan Yuslaimi                  1 (0.1%)
+   Muhammad Hazim Izzat Zamri            1 (0.1%)
+   Julien Masson                         1 (0.1%)
+   Igor Opaniuk                          1 (0.1%)
+   Aaron Kling                           1 (0.1%)
+   Chanho Park                           1 (0.1%)
+   Ronald Wahl                           1 (0.1%)
+   Vignesh Raghavendra                   1 (0.1%)
+   Tengfei Fan                           1 (0.1%)
+   Patrick Rudolph                       1 (0.1%)
+   Jonathan Humphreys                    1 (0.1%)
+   Roger Quadros                         1 (0.1%)
+   Beleswar Padhi                        1 (0.1%)
+   Jesse Taube                           1 (0.1%)
+   Norbert van Bolhuis                   1 (0.1%)
+   Andy Yan                              1 (0.1%)
+   Sébastien Szymanski                   1 (0.1%)
+   Georgi Vlaev                          1 (0.1%)
+   Vincent Fazio                         1 (0.1%)
+   Jonathan Stroud                       1 (0.1%)
+   Neal Frager                           1 (0.1%)
+   Naman Trivedi                         1 (0.1%)
+   Daniel Semkowicz                      1 (0.1%)
+   Cristian Ciocaltea                    1 (0.1%)
+   Jacobe Zang                           1 (0.1%)
+   Yang Gang                             1 (0.1%)
+   Olivier L'Heureux                     1 (0.1%)
+   Aleksandar Gerasimovski               1 (0.1%)
+   Sean Edmond                           1 (0.1%)
+   Markus Gothe                          1 (0.1%)
+   Prasanth Babu Mantena                 1 (0.1%)
+   Meng Li                               1 (0.1%)
+   Hiago De Franco                       1 (0.1%)
+   Randolph                              1 (0.1%)
+   Marcus Folkesson                      1 (0.1%)
+   Christoph Fritz                       1 (0.1%)
+   Aswath Govindraju                     1 (0.1%)
+   Vitor Soares                          1 (0.1%)
+   Keerthy                               1 (0.1%)
+   Théo Lebrun                           1 (0.1%)
+   Aniket Limaye                         1 (0.1%)
+   Alessandro Zini                       1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Developers with the most changed lines
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Tom Rini                              140936 (51.6%)
+   Heinrich Schuchardt                   18527 (6.8%)
+   Peng Fan                              12959 (4.7%)
+   Andre Przywara                        11041 (4.0%)
+   Marek Vasut                           10096 (3.7%)
+   Weijie Gao                            7532 (2.8%)
+   Garrett Giordano                      6803 (2.5%)
+   Simon Glass                           6197 (2.3%)
+   Patrick Rudolph                       6036 (2.2%)
+   Jonas Karlman                         4841 (1.8%)
+   Johan Jonker                          3953 (1.4%)
+   Bryan Brattlof                        3220 (1.2%)
+   Raymond Mao                           3169 (1.2%)
+   Neil Armstrong                        3003 (1.1%)
+   Adriano Cordova                       2387 (0.9%)
+   Hal Feng                              2328 (0.9%)
+   Mikhail Kshevetskiy                   1740 (0.6%)
+   Patrick Delaunay                      1409 (0.5%)
+   Michal Simek                          1176 (0.4%)
+   Christoph Stoidner                    1112 (0.4%)
+   Alexey Romanov                        1109 (0.4%)
+   FUKAUMI Naoki                         1079 (0.4%)
+   Svyatoslav Ryhel                      1027 (0.4%)
+   Udit Kumar                            1020 (0.4%)
+   Boon Khai Ng                          930 (0.3%)
+   Enrico Leto                           886 (0.3%)
+   Kongyang Liu                          772 (0.3%)
+   Mayuresh Chitale                      771 (0.3%)
+   Varadarajan Narayanan                 716 (0.3%)
+   Sam Shih                              705 (0.3%)
+   Philippe Reynes                       702 (0.3%)
+   Tianling Shen                         656 (0.2%)
+   Christian Marangi                     635 (0.2%)
+   Patrice Chotard                       538 (0.2%)
+   david regan                           529 (0.2%)
+   Maksim Kiselev                        519 (0.2%)
+   Richard Weinberger                    472 (0.2%)
+   Junhui Liu                            443 (0.2%)
+   Ilias Apalodimas                      438 (0.2%)
+   Santhosh Kumar K                      420 (0.2%)
+   Love Kumar                            418 (0.2%)
+   Duje Mihanović                        384 (0.1%)
+   Heiko Schocher                        381 (0.1%)
+   Venkatesh Yadav Abbarapu              381 (0.1%)
+   Caleb Connolly                        379 (0.1%)
+   Paul HENRYS                           379 (0.1%)
+   Manorit Chawdhry                      359 (0.1%)
+   Christoph Niedermaier                 357 (0.1%)
+   Wadim Egorov                          342 (0.1%)
+   E Shattow                             332 (0.1%)
+   Markus Gothe                          320 (0.1%)
+   Alice Guo                             295 (0.1%)
+   Stefan Eichenberger                   281 (0.1%)
+   Thomas Bonnefille                     275 (0.1%)
+   Jacobe Zang                           272 (0.1%)
+   Sam Protsenko                         239 (0.1%)
+   Sam Edwards                           236 (0.1%)
+   Daniel Schultz                        232 (0.1%)
+   Jayesh Choudhary                      221 (0.1%)
+   Guillaume La Roque                    213 (0.1%)
+   Aparna Patra                          210 (0.1%)
+   Frank Sae                             183 (0.1%)
+   Jim Liu                               148 (0.1%)
+   J. Neuschäfer                         142 (0.1%)
+   Michael Chang                         135 (0.0%)
+   Yannic Moog                           131 (0.0%)
+   Michael Trimarchi                     130 (0.0%)
+   Lothar Rubusch                        122 (0.0%)
+   Vitor Soares                          117 (0.0%)
+   Jerome Forissier                      115 (0.0%)
+   Georgi Vlaev                          114 (0.0%)
+   Dmitry Rokosov                        109 (0.0%)
+   Alexander Dahl                        106 (0.0%)
+   Zixun LI                              99 (0.0%)
+   Yunus Bas                             93 (0.0%)
+   Julien Masson                         92 (0.0%)
+   Aniket Limaye                         91 (0.0%)
+   Neha Malcom Francis                   85 (0.0%)
+   Ibai Erkiaga                          82 (0.0%)
+   Gokul Praveen                         81 (0.0%)
+   Yao Zi                                68 (0.0%)
+   Alessandro Zini                       67 (0.0%)
+   Evgeny Bachinin                       58 (0.0%)
+   Tony Dinh                             57 (0.0%)
+   Judith Mendez                         54 (0.0%)
+   Vaishnav Achath                       52 (0.0%)
+   Reid Tonking                          52 (0.0%)
+   Rasmus Villemoes                      50 (0.0%)
+   Yuri Zaporozhets                      49 (0.0%)
+   John Crispin                          48 (0.0%)
+   Tim Harvey                            45 (0.0%)
+   Cristian Ciocaltea                    41 (0.0%)
+   Fabio Estevam                         38 (0.0%)
+   Huan Zhou                             38 (0.0%)
+   Andrew Goodbody                       37 (0.0%)
+   Aashvij Shenai                        35 (0.0%)
+   Yu-Chien Peter Lin                    32 (0.0%)
+   Mattijs Korpershoek                   31 (0.0%)
+   Alexander Sverdlin                    28 (0.0%)
+   Shree Ramamoorthy                     27 (0.0%)
+   Andrey Skvortsov                      26 (0.0%)
+   Keerthy                               23 (0.0%)
+   Liya Huang                            22 (0.0%)
+   Tengfei Fan                           22 (0.0%)
+   Padmarao Begari                       20 (0.0%)
+   Benjamin Lemouzy                      20 (0.0%)
+   Paul Kocialkowski                     19 (0.0%)
+   Vincent Stehlé                        19 (0.0%)
+   Vignesh Raghavendra                   19 (0.0%)
+   Ye Li                                 18 (0.0%)
+   Chanho Park                           18 (0.0%)
+   Quentin Schulz                        16 (0.0%)
+   Peter Robinson                        15 (0.0%)
+   Joao Marcos Costa                     15 (0.0%)
+   Sam Day                               14 (0.0%)
+   Diederik de Haas                      12 (0.0%)
+   Paul Barker                           11 (0.0%)
+   Alif Zakuan Yuslaimi                  10 (0.0%)
+   Naman Trivedi                         10 (0.0%)
+   Leonard Anderweit                     9 (0.0%)
+   Anurag Dutta                          9 (0.0%)
+   Maks Mishin                           9 (0.0%)
+   Siddharth Vadapalli                   8 (0.0%)
+   Marcus Folkesson                      8 (0.0%)
+   Prasad Kummari                        7 (0.0%)
+   Martin Stolpe                         7 (0.0%)
+   Gao Xiang                             7 (0.0%)
+   Fiona Klute                           6 (0.0%)
+   Mark Tomlinson                        6 (0.0%)
+   Hendrik Donner                        6 (0.0%)
+   Beleswar Padhi                        6 (0.0%)
+   Daniel Semkowicz                      6 (0.0%)
+   Aswath Govindraju                     6 (0.0%)
+   Heiko Stuebner                        5 (0.0%)
+   Rufus Segar                           5 (0.0%)
+   Sumit Garg                            5 (0.0%)
+   Kever Yang                            5 (0.0%)
+   Justin Klaassen                       5 (0.0%)
+   Jonathan Stroud                       5 (0.0%)
+   Christoph Fritz                       5 (0.0%)
+   Théo Lebrun                           5 (0.0%)
+   Chen-Yu Tsai                          4 (0.0%)
+   Aaron Kling                           4 (0.0%)
+   Norbert van Bolhuis                   4 (0.0%)
+   Prasanth Babu Mantena                 4 (0.0%)
+   Nathan Morrisson                      3 (0.0%)
+   Ronald Wahl                           3 (0.0%)
+   Olivier L'Heureux                     3 (0.0%)
+   Christopher Obbard                    2 (0.0%)
+   Benedikt Spranger                     2 (0.0%)
+   Kory Maincent                         2 (0.0%)
+   Andrea della Porta                    2 (0.0%)
+   Greg Malysa                           2 (0.0%)
+   Michael Ferolito                      2 (0.0%)
+   Igor Opaniuk                          2 (0.0%)
+   Jonathan Humphreys                    2 (0.0%)
+   Jesse Taube                           2 (0.0%)
+   Sean Edmond                           2 (0.0%)
+   Hiago De Franco                       2 (0.0%)
+   Andrew Davis                          1 (0.0%)
+   Michael Walle                         1 (0.0%)
+   Ben Schneider                         1 (0.0%)
+   Julius Lehmann                        1 (0.0%)
+   ZHANG Yuntian                         1 (0.0%)
+   Benjamin Szőke                        1 (0.0%)
+   Josua Mayer                           1 (0.0%)
+   Muhammad Hazim Izzat Zamri            1 (0.0%)
+   Roger Quadros                         1 (0.0%)
+   Andy Yan                              1 (0.0%)
+   Sébastien Szymanski                   1 (0.0%)
+   Vincent Fazio                         1 (0.0%)
+   Neal Frager                           1 (0.0%)
+   Yang Gang                             1 (0.0%)
+   Aleksandar Gerasimovski               1 (0.0%)
+   Meng Li                               1 (0.0%)
+   Randolph                              1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most lines removed
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Heinrich Schuchardt                   17182 (17.4%)
+   Andre Przywara                        10887 (11.0%)
+   Johan Jonker                          3926 (4.0%)
+   Jonas Karlman                         3734 (3.8%)
+   Bryan Brattlof                        3116 (3.1%)
+   Hal Feng                              1798 (1.8%)
+   Patrick Delaunay                      1396 (1.4%)
+   Alexey Romanov                        1109 (1.1%)
+   Udit Kumar                            984 (1.0%)
+   Sam Shih                              560 (0.6%)
+   david regan                           451 (0.5%)
+   Richard Weinberger                    260 (0.3%)
+   E Shattow                             211 (0.2%)
+   Patrice Chotard                       179 (0.2%)
+   Alexander Dahl                        95 (0.1%)
+   Yao Zi                                28 (0.0%)
+   Aashvij Shenai                        23 (0.0%)
+   Tony Dinh                             21 (0.0%)
+   Diederik de Haas                      11 (0.0%)
+   Paul Barker                           7 (0.0%)
+   Marcus Folkesson                      6 (0.0%)
+   Théo Lebrun                           5 (0.0%)
+   Neha Malcom Francis                   4 (0.0%)
+   Alif Zakuan Yuslaimi                  4 (0.0%)
+   Kever Yang                            4 (0.0%)
+   Christoph Fritz                       2 (0.0%)
+   ZHANG Yuntian                         1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Developers with the most signoffs (total 218)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Michal Simek                          30 (13.8%)
+   Caleb Connolly                        27 (12.4%)
+   Mattijs Korpershoek                   21 (9.6%)
+   Ilias Apalodimas                      13 (6.0%)
+   Heiko Stuebner                        10 (4.6%)
+   Sam Shih                              8 (3.7%)
+   Minkyu Kang                           7 (3.2%)
+   Heiko Schocher                        7 (3.2%)
+   Raymond Mao                           7 (3.2%)
+   Peng Fan                              7 (3.2%)
+   Simon Glass                           6 (2.8%)
+   Anurag Dutta                          5 (2.3%)
+   Neil Armstrong                        5 (2.3%)
+   Richard Weinberger                    4 (1.8%)
+   Prasanth Babu Mantena                 4 (1.8%)
+   Ye Li                                 4 (1.8%)
+   Jerome Forissier                      4 (1.8%)
+   Aniket Limaye                         4 (1.8%)
+   Peter Robinson                        3 (1.4%)
+   Santhosh Kumar K                      3 (1.4%)
+   Jim Liu                               3 (1.4%)
+   Adriano Cordova                       3 (1.4%)
+   Neha Malcom Francis                   2 (0.9%)
+   Kever Yang                            2 (0.9%)
+   SkyLake.Huang                         2 (0.9%)
+   Dan Carpenter                         2 (0.9%)
+   Judith Mendez                         2 (0.9%)
+   Huan Zhou                             2 (0.9%)
+   Weijie Gao                            2 (0.9%)
+   Marek Vasut                           2 (0.9%)
+   Heinrich Schuchardt                   1 (0.5%)
+   Andre Przywara                        1 (0.5%)
+   Udit Kumar                            1 (0.5%)
+   Patrice Chotard                       1 (0.5%)
+   Miquel Raynal                         1 (0.5%)
+   Ion Agorria                           1 (0.5%)
+   Kamlesh Gurudasani                    1 (0.5%)
+   Tejas Bhumkar                         1 (0.5%)
+   Bjorn Andersson                       1 (0.5%)
+   Naresh Solanki                        1 (0.5%)
+   Bo-Cun Chen                           1 (0.5%)
+   Andrej Valek                          1 (0.5%)
+   Vaishnav Achath                       1 (0.5%)
+   Daniel Schultz                        1 (0.5%)
+   Christian Marangi                     1 (0.5%)
+   Mikhail Kshevetskiy                   1 (0.5%)
+   Tom Rini                              1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Developers with the most reviews (total 588)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Kever Yang                            85 (14.5%)
+   Simon Glass                           63 (10.7%)
+   Ilias Apalodimas                      54 (9.2%)
+   Heinrich Schuchardt                   30 (5.1%)
+   Tom Rini                              24 (4.1%)
+   Mattijs Korpershoek                   23 (3.9%)
+   Quentin Schulz                        23 (3.9%)
+   Leo Yu-Chi Liang                      22 (3.7%)
+   Patrick Delaunay                      18 (3.1%)
+   Wadim Egorov                          17 (2.9%)
+   Jaehoon Chung                         14 (2.4%)
+   Caleb Connolly                        11 (1.9%)
+   Stefan Roese                          11 (1.9%)
+   Marek Vasut                           10 (1.7%)
+   Jerome Forissier                      9 (1.5%)
+   Neil Armstrong                        8 (1.4%)
+   Peter Robinson                        8 (1.4%)
+   Weijie Gao                            8 (1.4%)
+   Paul Barker                           8 (1.4%)
+   Alexander Sverdlin                    8 (1.4%)
+   Sam Protsenko                         8 (1.4%)
+   Manorit Chawdhry                      8 (1.4%)
+   Bryan Brattlof                        7 (1.2%)
+   Raymond Mao                           6 (1.0%)
+   Peng Fan                              6 (1.0%)
+   E Shattow                             5 (0.9%)
+   Tien Fong Chee                        5 (0.9%)
+   Udit Kumar                            4 (0.7%)
+   Sinan Akman                           4 (0.7%)
+   Devarsh Thakkar                       4 (0.7%)
+   Sumit Garg                            4 (0.7%)
+   Fabio Estevam                         4 (0.7%)
+   Heiko Schocher                        3 (0.5%)
+   Neha Malcom Francis                   3 (0.5%)
+   Andre Przywara                        3 (0.5%)
+   Patrice Chotard                       3 (0.5%)
+   Miquel Raynal                         3 (0.5%)
+   Roger Quadros                         3 (0.5%)
+   Matthias Brugger                      3 (0.5%)
+   Jernej Skrabec                        3 (0.5%)
+   William Zhang                         3 (0.5%)
+   Anand Gore                            3 (0.5%)
+   Julien Masson                         3 (0.5%)
+   Alexander Dahl                        2 (0.3%)
+   Dhruva Gole                           2 (0.3%)
+   Chris Packham                         2 (0.3%)
+   Jan Kiszka                            2 (0.3%)
+   Yixun Lan                             2 (0.3%)
+   John Ogness                           2 (0.3%)
+   Yannic Moog                           2 (0.3%)
+   Michael Trimarchi                     2 (0.3%)
+   Michal Simek                          1 (0.2%)
+   Anurag Dutta                          1 (0.2%)
+   Chen-Yu Tsai                          1 (0.2%)
+   Andrew Davis                          1 (0.2%)
+   Michael Brown                         1 (0.2%)
+   Tianrui Wei                           1 (0.2%)
+   Sughosh Ganu                          1 (0.2%)
+   Mark Kettenis                         1 (0.2%)
+   Anand Moon                            1 (0.2%)
+   Francesco Dolcini                     1 (0.2%)
+   Nicolas Belin                         1 (0.2%)
+   Konrad Dybcio                         1 (0.2%)
+   Viacheslav Mitrofanov                 1 (0.2%)
+   Dragan Simic                          1 (0.2%)
+   Siddharth Vadapalli                   1 (0.2%)
+   Tim Harvey                            1 (0.2%)
+   Paul Kocialkowski                     1 (0.2%)
+   Vignesh Raghavendra                   1 (0.2%)
+   Love Kumar                            1 (0.2%)
+   Patrick Rudolph                       1 (0.2%)
+   ====================================  =====
+
+
+.. table:: Developers with the most test credits (total 76)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   E Shattow                             12 (15.8%)
+   Anand Moon                            11 (14.5%)
+   Weijie Gao                            8 (10.5%)
+   Sam Protsenko                         8 (10.5%)
+   Mattijs Korpershoek                   3 (3.9%)
+   Caleb Connolly                        3 (3.9%)
+   Daniel Schultz                        3 (3.9%)
+   Marcel Ziswiler                       3 (3.9%)
+   FUKAUMI Naoki                         3 (3.9%)
+   Alexey Minnekhanov                    2 (2.6%)
+   Amit Pundir                           2 (2.6%)
+   Primoz Fiser                          2 (2.6%)
+   Heinrich Schuchardt                   1 (1.3%)
+   Quentin Schulz                        1 (1.3%)
+   Wadim Egorov                          1 (1.3%)
+   Jerome Forissier                      1 (1.3%)
+   Neil Armstrong                        1 (1.3%)
+   Neha Malcom Francis                   1 (1.3%)
+   Julien Masson                         1 (1.3%)
+   Yannic Moog                           1 (1.3%)
+   Michal Simek                          1 (1.3%)
+   Tony Dinh                             1 (1.3%)
+   Christian Kohlschütter                1 (1.3%)
+   Yuguo Pei                             1 (1.3%)
+   Ferass El Hafidi                      1 (1.3%)
+   Niklas Söderlund                      1 (1.3%)
+   Ben Schneider                         1 (1.3%)
+   Sam Day                               1 (1.3%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 76)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Hal Feng                              22 (28.9%)
+   Ilias Apalodimas                      9 (11.8%)
+   Christian Marangi                     7 (9.2%)
+   Caleb Connolly                        5 (6.6%)
+   Neil Armstrong                        4 (5.3%)
+   Wadim Egorov                          3 (3.9%)
+   Jonas Karlman                         3 (3.9%)
+   Heinrich Schuchardt                   2 (2.6%)
+   Jerome Forissier                      2 (2.6%)
+   Sam Day                               2 (2.6%)
+   Marek Vasut                           2 (2.6%)
+   Richard Weinberger                    2 (2.6%)
+   Kongyang Liu                          2 (2.6%)
+   Christoph Stoidner                    2 (2.6%)
+   Daniel Schultz                        1 (1.3%)
+   Fabio Estevam                         1 (1.3%)
+   Santhosh Kumar K                      1 (1.3%)
+   Huan Zhou                             1 (1.3%)
+   Yao Zi                                1 (1.3%)
+   Aaron Kling                           1 (1.3%)
+   John Crispin                          1 (1.3%)
+   Guillaume La Roque                    1 (1.3%)
+   Maksim Kiselev                        1 (1.3%)
+   ====================================  =====
+
+
+.. table:: Developers with the most report credits (total 13)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Ludwig Nussel                         2 (15.4%)
+   Ilias Apalodimas                      1 (7.7%)
+   E Shattow                             1 (7.7%)
+   Christian Kohlschütter                1 (7.7%)
+   Ben Schneider                         1 (7.7%)
+   Simon Glass                           1 (7.7%)
+   Tim Harvey                            1 (7.7%)
+   Love Kumar                            1 (7.7%)
+   Niklas Sombert                        1 (7.7%)
+   Björn Töpel                           1 (7.7%)
+   Ricardo Pardini                       1 (7.7%)
+   Liya Huang                            1 (7.7%)
+   ====================================  =====
+
+
+.. table:: Developers who gave the most report credits (total 13)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Ilias Apalodimas                      2 (15.4%)
+   Heinrich Schuchardt                   2 (15.4%)
+   Peng Fan                              2 (15.4%)
+   Hal Feng                              1 (7.7%)
+   Jonas Karlman                         1 (7.7%)
+   Jerome Forissier                      1 (7.7%)
+   Fabio Estevam                         1 (7.7%)
+   Michal Simek                          1 (7.7%)
+   Tom Rini                              1 (7.7%)
+   Raymond Mao                           1 (7.7%)
+   ====================================  =====
+
+
+.. table:: Top changeset contributors by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             458 (36.2%)
+   Google LLC                            222 (17.6%)
+   Linaro                                107 (8.5%)
+   Texas Instruments                     82 (6.5%)
+   Renesas Electronics                   74 (5.9%)
+   AMD                                   62 (4.9%)
+   DENX Software Engineering             54 (4.3%)
+   Konsulko Group                        51 (4.0%)
+   NXP                                   35 (2.8%)
+   Phytec                                34 (2.7%)
+   ST Microelectronics                   25 (2.0%)
+   Siemens                               11 (0.9%)
+   Toradex                               11 (0.9%)
+   ARM                                   9 (0.7%)
+   BayLibre SAS                          7 (0.6%)
+   Bootlin                               6 (0.5%)
+   Intel                                 5 (0.4%)
+   Broadcom                              3 (0.2%)
+   linutronix                            2 (0.2%)
+   Amarula Solutions                     1 (0.1%)
+   Collabora Ltd.                        1 (0.1%)
+   Wind River                            1 (0.1%)
+   Rockchip                              1 (0.1%)
+   SUSE                                  1 (0.1%)
+   Extreme Engineering Solutions         1 (0.1%)
+   ====================================  =====
+
+
+.. table:: Top lines changed by employer
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Konsulko Group                        140936 (51.6%)
+   (Unknown)                             67870 (24.9%)
+   NXP                                   13272 (4.9%)
+   ARM                                   11060 (4.1%)
+   Renesas Electronics                   8666 (3.2%)
+   Linaro                                7382 (2.7%)
+   Google LLC                            6197 (2.3%)
+   Texas Instruments                     6119 (2.2%)
+   AMD                                   2100 (0.8%)
+   ST Microelectronics                   1947 (0.7%)
+   Phytec                                1919 (0.7%)
+   DENX Software Engineering             1860 (0.7%)
+   Siemens                               981 (0.4%)
+   Intel                                 931 (0.3%)
+   Broadcom                              529 (0.2%)
+   Toradex                               400 (0.1%)
+   BayLibre SAS                          305 (0.1%)
+   Bootlin                               297 (0.1%)
+   Amarula Solutions                     130 (0.0%)
+   Collabora Ltd.                        41 (0.0%)
+   Rockchip                              5 (0.0%)
+   linutronix                            2 (0.0%)
+   SUSE                                  2 (0.0%)
+   Wind River                            1 (0.0%)
+   Extreme Engineering Solutions         1 (0.0%)
+   ====================================  =====
+
+
+.. table:: Employers with the most signoffs (total 218)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   Linaro                                58 (26.6%)
+   (Unknown)                             43 (19.7%)
+   AMD                                   31 (14.2%)
+   Texas Instruments                     23 (10.6%)
+   BayLibre SAS                          21 (9.6%)
+   NXP                                   11 (5.0%)
+   DENX Software Engineering             9 (4.1%)
+   Samsung                               7 (3.2%)
+   Google LLC                            6 (2.8%)
+   Rockchip                              2 (0.9%)
+   Konsulko Group                        1 (0.5%)
+   ARM                                   1 (0.5%)
+   ST Microelectronics                   1 (0.5%)
+   Phytec                                1 (0.5%)
+   Siemens                               1 (0.5%)
+   Bootlin                               1 (0.5%)
+   Canonical                             1 (0.5%)
+   ====================================  =====
+
+
+.. table:: Employers with the most hackers (total 177)
+   :widths: auto
+
+   ====================================  =====
+   Name                                  Count
+   ====================================  =====
+   (Unknown)                             94 (53.1%)
+   Texas Instruments                     24 (13.6%)
+   AMD                                   9 (5.1%)
+   Linaro                                8 (4.5%)
+   Phytec                                6 (3.4%)
+   Bootlin                               4 (2.3%)
+   NXP                                   3 (1.7%)
+   DENX Software Engineering             3 (1.7%)
+   Siemens                               3 (1.7%)
+   Toradex                               3 (1.7%)
+   BayLibre SAS                          2 (1.1%)
+   ARM                                   2 (1.1%)
+   ST Microelectronics                   2 (1.1%)
+   Renesas Electronics                   2 (1.1%)
+   Intel                                 2 (1.1%)
+   Google LLC                            1 (0.6%)
+   Rockchip                              1 (0.6%)
+   Konsulko Group                        1 (0.6%)
+   Broadcom                              1 (0.6%)
+   Amarula Solutions                     1 (0.6%)
+   Collabora Ltd.                        1 (0.6%)
+   linutronix                            1 (0.6%)
+   SUSE                                  1 (0.6%)
+   Wind River                            1 (0.6%)
+   Extreme Engineering Solutions         1 (0.6%)
+   ====================================  =====
diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst
index 9f30972fe53..e652968d584 100644
--- a/doc/usage/cmd/acpi.rst
+++ b/doc/usage/cmd/acpi.rst
@@ -11,7 +11,7 @@ Synopsis
 
 ::
 
-    acpi list
+    acpi list [-c]
     acpi items [-d]
     acpi dump <name>
     acpi set <address>
@@ -38,6 +38,9 @@ List the ACPI tables that have been generated. Each table has a 4-character
 table name (e.g. SSDT, FACS) and has a format defined by the
 `ACPI specification`_.
 
+The `-c` flag tells U-Boot to verify the checksums and print 'OK' or 'BAD' next
+to each table.
+
 U-Boot does not currently support decoding the tables. Unlike devicetree, ACPI
 tables have no regular schema and also some include bytecode, so decoding the
 tables requires a lot of code.
@@ -259,5 +262,20 @@ pointer::
     WAET  bff76a3b     28  v01 BOCHS  BXPC     1 BXPC 1
     SSDT  bff95040     c5  v02 COREv4 COREBOOT 2a CORE 20221020
 
+This shows checking that the checksums are correct for each table::
+
+    => acpi list -c
+    Name              Base   Size  Detail
+    ----  ----------------  -----  ----------------------------
+    RSDP          bec9a000     24  v00 BOCHS   OK OK
+    RSDT          bec9bd4a     38  v01 BOCHS  BXPC     1 BXPC 1  OK
+    FACP          bec9bb46     74  v01 BOCHS  BXPC     1 BXPC 1  OK
+    DSDT          bec9a080   1ac6  v01 BOCHS  BXPC     1 BXPC 1  OK
+    FACS          bec9a040     40
+    APIC          bec9bbba     78  v03 BOCHS  BXPC     1 BXPC 1  OK
+    HPET          bec9bc32     38  v01 BOCHS  BXPC     1 BXPC 1  OK
+    SRAT          bec9bc6a     b8  v01 BOCHS  BXPC     1 BXPC 1  OK
+    WAET          bec9bd22     28  v01 BOCHS  BXPC     1 BXPC 1  OK
+
 
 .. _`ACPI specification`: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index 5d41fe37a7a..01e7eff300b 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -18,7 +18,7 @@ Synopsis
     bootflow read
     bootflow boot
     bootflow cmdline [set|get|clear|delete|auto] <param> [<value>]
-    bootfloe menu [-t]
+    bootflow menu [-t]
 
 Description
 -----------
diff --git a/doc/usage/cmd/fuse.rst b/doc/usage/cmd/fuse.rst
new file mode 100644
index 00000000000..42c6e209f99
--- /dev/null
+++ b/doc/usage/cmd/fuse.rst
@@ -0,0 +1,176 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+   single: fuse (command)
+
+fuse command
+============
+
+Synopsis
+--------
+
+::
+
+    fuse read <bank> <word> [<cnt>]
+    fuse cmp <bank> <word> <hexval>
+    fuse readm <bank> <word> <addr> [<cnt>]
+    fuse sense <bank> <word> [<cnt>]
+    fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
+    fuse override <bank> <word> <hexval> [<hexval>...]
+    fuse writebuff [-y] <addr>
+
+Description
+-----------
+
+The fuse API allows to control a fusebox and how it is used by the upper
+hardware layers.
+
+A fuse corresponds to a single non-volatile memory bit that can be programmed
+(i.e., blown, set to 1) only once. The programming operation is irreversible.
+A fuse that has not been programmed reads as 0.
+
+Fuses can be used by SoCs to store various permanent configurations and data,
+such as boot configurations, security settings, MAC addresses, etc.
+
+A fuse 'word' is the smallest group of fuses that can be read at once from
+the fusebox control IP registers. In the current API, this is limited to 32 bits.
+
+A fuse 'bank' is the smallest group of fuse words having a common ID, as
+defined by each SoC.
+
+Upon startup, the fusebox control IP reads the fuse values and stores them in a
+volatile shadow cache.
+
+Commands
+--------
+
+- **fuse read <bank> <word> [<cnt>]**
+  Reads 1 or 'cnt' fuse words, starting at 'word' from the shadow cache.
+
+- **fuse cmp <bank> <word> <hexval>**
+  Compares 'hexval' to fuse at 'word'.
+
+- **fuse readm <bank> <word> <addr> [<cnt>]**
+  Reads 1 or 'cnt' fuse words, starting at 'word' into memory at 'addr'.
+
+- **fuse sense <bank> <word> [<cnt>]**
+  Sense 1 or 'cnt' fuse words, starting at 'word'.
+  Sense - i.e. read directly from the fusebox, skipping the shadow cache -
+  fuse words. This operation does not update the shadow cache. This is
+  useful to know the true value of fuses if an override has been
+  performed (see below).
+
+- **fuse prog [-y] <bank> <word> <hexval> [<hexval>...]**
+  Permanently programs 1 or several fuse words, starting at 'word'.
+  This operation directly affects the fusebox and is irreversible. The
+  shadow cache is updated accordingly or not, depending on each IP.
+  Only the bits to be programmed should be set in the input value (i.e.
+  for fuse bits that have already been programmed and hence should be
+  left unchanged by a further programming, it is preferable to clear
+  the corresponding bits in the input value in order not to perform a
+  new hardware programming operation on these fuse bits).
+
+- **fuse override <bank> <word> <hexval> [<hexval>...]**
+  Override 1 or several fuse words, starting at 'word' in the shadow cache.
+  The fusebox is unaffected, so following this operation, the shadow cache
+  may differ from the fusebox values. Read or sense operations can then be
+  used to get the values from the shadow cache or from the fusebox.
+  This is useful to change the behaviours linked to some cached fuse values,
+  either because this is needed only temporarily, or because some of the
+  fuses have already been programmed or are locked (if the SoC allows to
+  override a locked fuse).
+
+- **fuse writebuff [-y] <addr>**
+  Programs fuse data using a structured buffer in memory starting at 'addr'.
+  This operation directly affects the fusebox and is irreversible.
+
+  The structure of the buffer should contain all necessary details for
+  programming fuses, such as the values to be written to the fuse, optional
+  metadata for validation or programming constraints and any configuration
+  data required for the operation. Define CONFIG_CMD_FUSE_WRITEBUFF to
+  enable the fuse writebuff command.
+
+Examples
+--------
+
+fuse read
+~~~~~~~~~
+
+::
+
+    u-boot=> fuse read 0 1
+      Reading bank 0:
+
+      Word 0x00000001: 00000001
+
+fuse cmp
+~~~~~~~~
+
+::
+
+    u-boot=> fuse cmp 0 1 0x1
+      Comparing bank 0:
+
+      Word 0x00000001:
+      Value 0x00000001:0x00000001
+      passed
+
+fuse readm
+~~~~~~~~~~
+
+::
+
+    u-boot=> fuse readm 0 1 0x83000000
+      Reading bank 0 len 1 to 0x83000000
+
+fuse sense
+~~~~~~~~~~
+
+::
+
+    u-boot=> fuse sense 0 1
+      Sensing bank 0:
+
+      Word 0x00000001: 00000001
+
+fuse prog
+~~~~~~~~~
+
+::
+
+    u-boot=> fuse prog 0 1 0x00000002
+      Programming bank 0 word 0x00000001 to 0x00000002...
+      Warning: Programming fuses is an irreversible operation!
+               This may brick your system.
+               Use this command only if you are sure of what you are doing!
+
+      Really perform this fuse programming? <y/N>
+      y
+
+fuse override
+~~~~~~~~~~~~~
+
+::
+
+    u-boot=> fuse override 0 1 0x00000003
+      Overriding bank 0 word 0x00000001 with 0x00000003...
+
+fuse writebuff
+~~~~~~~~~~~~~~
+
+::
+
+    u-boot=> fuse writebuff -y 0x84000000
+      Programming fuses with buffer at addr 0x84000000
+
+Configuration
+-------------
+
+The fuse commands are available if CONFIG_CMD_FUSE=y.
+The fuse writebuff command is available if CONFIG_CMD_FUSE_WRITEBUFF=y.
+
+Return code
+-----------
+
+The return value $? is set to 0 (true) if the command is successful,
+1 (false) otherwise.
diff --git a/doc/usage/fdt_overlays.rst b/doc/usage/fdt_overlays.rst
index 81d0d37f3f1..15ebd17ccb1 100644
--- a/doc/usage/fdt_overlays.rst
+++ b/doc/usage/fdt_overlays.rst
@@ -76,8 +76,8 @@ There are two ways to apply overlays in U-Boot.
 * Manually load and apply overlays
 
 The remainder of this document will discuss using overlays via the manual
-approach. For information on using overlays as part of a FIT image please see:
-doc/uImage.FIT/overlay-fdt-boot.txt
+approach. For information on using overlays as part of a FIT image please see
+:ref:`fit_configuration_using_overlays`.
 
 Manually Loading and Applying Overlays
 --------------------------------------
diff --git a/doc/usage/fit/overlay-fdt-boot.rst b/doc/usage/fit/overlay-fdt-boot.rst
index a7db1a37f7a..3d7296ad913 100644
--- a/doc/usage/fit/overlay-fdt-boot.rst
+++ b/doc/usage/fit/overlay-fdt-boot.rst
@@ -111,6 +111,8 @@ Where config is one of::
 
 This selects the DTB to use when booting.
 
+.. _fit_configuration_using_overlays:
+
 Configuration using overlays
 ----------------------------
 
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index fc058476f39..372ef56c967 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -72,6 +72,7 @@ Shell commands
    cmd/fdt
    cmd/font
    cmd/for
+   cmd/fuse
    cmd/fwu_mdata
    cmd/gpio
    cmd/gpt
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 34eed1380dc..473c65b5911 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -17,6 +17,30 @@
 struct blkmap;
 
 /**
+ * define BLKMAP_SLICE_LINEAR - Linear mapping to another block device
+ *
+ * This blkmap slice type is used for mapping to other existing block
+ * devices.
+ */
+#define BLKMAP_SLICE_LINEAR	BIT(0)
+
+/**
+ * define BLKMAP_SLICE_MEM - Linear mapping to memory based block device
+ *
+ * This blkmap slice type is used for mapping to memory based block
+ * devices, like ramdisks.
+ */
+#define BLKMAP_SLICE_MEM	BIT(1)
+
+/**
+ * define BLKMAP_SLICE_PRESERVE - Preserved blkmap slice
+ *
+ * This blkmap slice is intended to be preserved, and it's
+ * information passed on to a later stage, like OS.
+ */
+#define BLKMAP_SLICE_PRESERVE	BIT(2)
+
+/**
  * struct blkmap_slice - Region mapped to a blkmap
  *
  * Common data for a region mapped to a blkmap, specialized by each
@@ -25,12 +49,14 @@ struct blkmap;
  * @node: List node used to associate this slice with a blkmap
  * @blknr: Start block number of the mapping
  * @blkcnt: Number of blocks covered by this mapping
+ * @attr: Attributes of blkmap slice
  */
 struct blkmap_slice {
 	struct list_head node;
 
 	lbaint_t blknr;
 	lbaint_t blkcnt;
+	uint     attr;
 
 	/**
 	 * @read: - Read from slice
@@ -169,6 +195,7 @@ int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.slice = {
 			.blknr = blknr,
 			.blkcnt = blkcnt,
+			.attr = BLKMAP_SLICE_LINEAR,
 
 			.read = blkmap_linear_read,
 			.write = blkmap_linear_write,
@@ -234,7 +261,7 @@ static void blkmap_mem_destroy(struct blkmap *bm, struct blkmap_slice *bms)
 }
 
 int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		     void *addr, bool remapped)
+		     void *addr, bool remapped, bool preserve)
 {
 	struct blkmap *bm = dev_get_plat(dev);
 	struct blkmap_mem *bmm;
@@ -248,6 +275,7 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.slice = {
 			.blknr = blknr,
 			.blkcnt = blkcnt,
+			.attr = BLKMAP_SLICE_MEM,
 
 			.read = blkmap_mem_read,
 			.write = blkmap_mem_write,
@@ -258,6 +286,9 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.remapped = remapped,
 	};
 
+	if (preserve)
+		bmm->slice.attr |= BLKMAP_SLICE_PRESERVE;
+
 	err = blkmap_slice_add(bm, &bmm->slice);
 	if (err)
 		free(bmm);
@@ -268,11 +299,11 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		   void *addr)
 {
-	return __blkmap_map_mem(dev, blknr, blkcnt, addr, false);
+	return __blkmap_map_mem(dev, blknr, blkcnt, addr, false, false);
 }
 
 int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		    phys_addr_t paddr)
+		    phys_addr_t paddr, bool preserve)
 {
 	struct blkmap *bm = dev_get_plat(dev);
 	struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
@@ -283,7 +314,7 @@ int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 	if (!addr)
 		return -ENOMEM;
 
-	err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true);
+	err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true, preserve);
 	if (err)
 		unmap_sysmem(addr);
 
@@ -486,6 +517,49 @@ err:
 	return err;
 }
 
+static bool blkmap_mem_preserve_slice(struct blkmap_slice *bms)
+{
+	return (bms->attr & (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE)) ==
+		(BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE);
+}
+
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+					       u64 size), void *ctx)
+{
+	int ret;
+	u64 addr, size;
+	struct udevice *dev;
+	struct uclass *uc;
+	struct blkmap *bm;
+	struct blkmap_mem *bmm;
+	struct blkmap_slice *bms;
+	struct blk_desc *bd;
+
+	if (!cb) {
+		log_debug("%s: No callback passed to the function\n", __func__);
+		return 0;
+	}
+
+	uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) {
+		bm = dev_get_plat(dev);
+		bd = dev_get_uclass_plat(bm->blk);
+
+		list_for_each_entry(bms, &bm->slices, node) {
+			if (!blkmap_mem_preserve_slice(bms))
+				continue;
+
+			bmm = container_of(bms, struct blkmap_mem, slice);
+			addr = (u64)(uintptr_t)bmm->addr;
+			size = (u64)bms->blkcnt << bd->log2blksz;
+			ret = cb(ctx, addr, size);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
 int blkmap_destroy(struct udevice *dev)
 {
 	int err;
diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c
index bfba14110d2..2f1bc28ee5d 100644
--- a/drivers/block/blkmap_helper.c
+++ b/drivers/block/blkmap_helper.c
@@ -28,7 +28,7 @@ int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
 	bm = dev_get_plat(bm_dev);
 	desc = dev_get_uclass_plat(bm->blk);
 	blknum = image_size >> desc->log2blksz;
-	ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+	ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr, true);
 	if (ret) {
 		log_err("Unable to map %#llx at block %d : %d\n",
 			(unsigned long long)image_addr, 0, ret);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fe0e49f6112..8411205ee04 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o
 obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o
 
 obj-y += adi/
+obj-y += airoha/
 obj-y += analogbits/
 obj-y += imx/
 obj-$(CONFIG_CLK_JH7110) += starfive/
diff --git a/drivers/clk/airoha/Makefile b/drivers/clk/airoha/Makefile
new file mode 100644
index 00000000000..1744c5f7236
--- /dev/null
+++ b/drivers/clk/airoha/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_AIROHA) += clk-airoha.o
diff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c
new file mode 100644
index 00000000000..1b2c4c98de5
--- /dev/null
+++ b/drivers/clk/airoha/clk-airoha.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Based on the Linux clk-en7523.c but majorly reworked
+ * for U-Boot that doesn't require CCF subsystem.
+ *
+ * Major modification, support for set_rate, realtime
+ * get_rate and split for reset part to a different driver.
+ *
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org> (original driver)
+ *	   Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include <dt-bindings/clock/en7523-clk.h>
+
+#define REG_GSW_CLK_DIV_SEL		0x1b4
+#define REG_EMI_CLK_DIV_SEL		0x1b8
+#define REG_BUS_CLK_DIV_SEL		0x1bc
+#define REG_SPI_CLK_DIV_SEL		0x1c4
+#define REG_SPI_CLK_FREQ_SEL		0x1c8
+#define REG_NPU_CLK_DIV_SEL		0x1fc
+
+#define REG_NP_SCU_PCIC			0x88
+#define REG_NP_SCU_SSTR			0x9c
+#define REG_PCIE_XSI0_SEL_MASK		GENMASK(14, 13)
+#define REG_PCIE_XSI1_SEL_MASK		GENMASK(12, 11)
+#define REG_CRYPTO_CLKSRC2		0x20c
+
+#define EN7581_MAX_CLKS			9
+
+struct airoha_clk_desc {
+	int id;
+	const char *name;
+	u32 base_reg;
+	u8 base_bits;
+	u8 base_shift;
+	union {
+		const unsigned int *base_values;
+		unsigned int base_value;
+	};
+	size_t n_base_values;
+
+	u16 div_reg;
+	u8 div_bits;
+	u8 div_shift;
+	u16 div_val0;
+	u8 div_step;
+	u8 div_offset;
+};
+
+struct airoha_clk_priv {
+	struct regmap *chip_scu_map;
+	struct airoha_clk_soc_data *data;
+};
+
+struct airoha_clk_soc_data {
+	u32 num_clocks;
+	const struct airoha_clk_desc *descs;
+};
+
+static const u32 gsw_base[] = { 400000000, 500000000 };
+static const u32 slic_base[] = { 100000000, 3125000 };
+
+static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
+static const u32 bus7581_base[] = { 600000000, 540000000 };
+static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
+static const u32 crypto_base[] = { 540000000, 480000000 };
+static const u32 emmc7581_base[] = { 200000000, 150000000 };
+
+static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = {
+	[EN7523_CLK_GSW] = {
+		.id = EN7523_CLK_GSW,
+		.name = "gsw",
+
+		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = gsw_base,
+		.n_base_values = ARRAY_SIZE(gsw_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_EMI] = {
+		.id = EN7523_CLK_EMI,
+		.name = "emi",
+
+		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = emi7581_base,
+		.n_base_values = ARRAY_SIZE(emi7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_BUS] = {
+		.id = EN7523_CLK_BUS,
+		.name = "bus",
+
+		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = bus7581_base,
+		.n_base_values = ARRAY_SIZE(bus7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_SLIC] = {
+		.id = EN7523_CLK_SLIC,
+		.name = "slic",
+
+		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = slic_base,
+		.n_base_values = ARRAY_SIZE(slic_base),
+
+		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_bits = 5,
+		.div_shift = 24,
+		.div_val0 = 20,
+		.div_step = 2,
+	},
+	[EN7523_CLK_SPI] = {
+		.id = EN7523_CLK_SPI,
+		.name = "spi",
+
+		.base_reg = REG_SPI_CLK_DIV_SEL,
+
+		.base_value = 400000000,
+
+		.div_bits = 5,
+		.div_shift = 8,
+		.div_val0 = 40,
+		.div_step = 2,
+	},
+	[EN7523_CLK_NPU] = {
+		.id = EN7523_CLK_NPU,
+		.name = "npu",
+
+		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = npu7581_base,
+		.n_base_values = ARRAY_SIZE(npu7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_CRYPTO] = {
+		.id = EN7523_CLK_CRYPTO,
+		.name = "crypto",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = crypto_base,
+		.n_base_values = ARRAY_SIZE(crypto_base),
+	},
+	[EN7581_CLK_EMMC] = {
+		.id = EN7581_CLK_EMMC,
+		.name = "emmc",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 12,
+		.base_values = emmc7581_base,
+		.n_base_values = ARRAY_SIZE(emmc7581_base),
+	}
+};
+
+static u32 airoha_clk_get_base_rate(const struct airoha_clk_desc *desc, u32 val)
+{
+	if (!desc->base_bits)
+		return desc->base_value;
+
+	val >>= desc->base_shift;
+	val &= (1 << desc->base_bits) - 1;
+
+	if (val >= desc->n_base_values)
+		return 0;
+
+	return desc->base_values[val];
+}
+
+static u32 airoha_clk_get_div(const struct airoha_clk_desc *desc, u32 val)
+{
+	if (!desc->div_bits)
+		return 1;
+
+	val >>= desc->div_shift;
+	val &= (1 << desc->div_bits) - 1;
+
+	if (!val && desc->div_val0)
+		return desc->div_val0;
+
+	return (val + desc->div_offset) * desc->div_step;
+}
+
+static int airoha_clk_enable(struct clk *clk)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	int id = clk->id;
+
+	if (id > data->num_clocks)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int airoha_clk_disable(struct clk *clk)
+{
+	return 0;
+}
+
+static ulong airoha_clk_get_rate(struct clk *clk)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	const struct airoha_clk_desc *desc;
+	struct regmap *map = priv->chip_scu_map;
+	int id = clk->id;
+	u32 reg, val;
+	ulong rate;
+	int ret;
+
+	if (id > data->num_clocks) {
+		dev_err(clk->dev, "Invalid clk ID %d\n", id);
+		return 0;
+	}
+
+	desc = &data->descs[id];
+
+	ret = regmap_read(map, desc->base_reg, &val);
+	if (ret) {
+		dev_err(clk->dev, "Failed to read reg for clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	rate = airoha_clk_get_base_rate(desc, val);
+
+	reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+	ret = regmap_read(map, reg, &val);
+	if (ret) {
+		dev_err(clk->dev, "Failed to read reg for clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	rate /= airoha_clk_get_div(desc, val);
+
+	return rate;
+}
+
+static int airoha_clk_search_rate(const struct airoha_clk_desc *desc, int div,
+				  ulong rate)
+{
+	int i;
+
+	/* Single base rate */
+	if (!desc->base_bits) {
+		if (rate != desc->base_value / div)
+			goto err;
+
+		return 0;
+	}
+
+	/* Check every base rate with provided divisor */
+	for (i = 0; i < desc->n_base_values; i++)
+		if (rate == desc->base_values[i] / div)
+			return i;
+
+err:
+	return -EINVAL;
+}
+
+static ulong airoha_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	const struct airoha_clk_desc *desc;
+	struct regmap *map = priv->chip_scu_map;
+	int div_val, base_val;
+	u32 reg, val, mask;
+	int id = clk->id;
+	int div;
+	int ret;
+
+	if (id > data->num_clocks) {
+		dev_err(clk->dev, "Invalid clk ID %d\n", id);
+		return 0;
+	}
+
+	desc = &data->descs[id];
+
+	if (!desc->base_bits && !desc->div_bits) {
+		dev_err(clk->dev, "Can't set rate for fixed clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	if (!desc->div_bits) {
+		/* Divisor not supported, just search in base rate */
+		div_val = 0;
+		base_val = airoha_clk_search_rate(desc, 1, rate);
+		if (base_val < 0) {
+			dev_err(clk->dev, "Invalid rate for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	} else {
+		div_val = 0;
+
+		/* Check if div0 satisfy the request */
+		if (desc->div_val0) {
+			base_val = airoha_clk_search_rate(desc, desc->div_val0,
+							  rate);
+			if (base_val >= 0) {
+				div_val = 0;
+				goto apply;
+			}
+
+			/* Skip checking first divisor val */
+			div_val = 1;
+		}
+
+		/* Simulate rate with every divisor supported */
+		for (div_val = div_val + desc->div_offset;
+		     div_val < BIT(desc->div_bits) - 1; div_val++) {
+			div = div_val * desc->div_step;
+
+			base_val = airoha_clk_search_rate(desc, div, rate);
+			if (base_val >= 0)
+				break;
+		}
+
+		if (div_val == BIT(desc->div_bits) - 1) {
+			dev_err(clk->dev, "Invalid rate for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+apply:
+	if (desc->div_bits) {
+		reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+
+		mask = (BIT(desc->div_bits) - 1) << desc->div_shift;
+		val = div_val << desc->div_shift;
+
+		ret = regmap_update_bits(map, reg, mask, val);
+		if (ret) {
+			dev_err(clk->dev, "Failed to update div reg for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+	if (desc->base_bits) {
+		mask = (BIT(desc->base_bits) - 1) << desc->base_shift;
+		val = base_val << desc->base_shift;
+
+		ret = regmap_update_bits(map, desc->base_reg, mask, val);
+		if (ret) {
+			dev_err(clk->dev, "Failed to update reg for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+	return rate;
+}
+
+const struct clk_ops airoha_clk_ops = {
+	.enable = airoha_clk_enable,
+	.disable = airoha_clk_disable,
+	.get_rate = airoha_clk_get_rate,
+	.set_rate = airoha_clk_set_rate,
+};
+
+static int airoha_clk_probe(struct udevice *dev)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(dev);
+	ofnode chip_scu_node;
+
+	chip_scu_node = ofnode_by_compatible(ofnode_null(),
+					     "airoha,en7581-chip-scu");
+	if (!ofnode_valid(chip_scu_node))
+		return -EINVAL;
+
+	priv->chip_scu_map = syscon_node_to_regmap(chip_scu_node);
+	if (IS_ERR(priv->chip_scu_map))
+		return PTR_ERR(priv->chip_scu_map);
+
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static int airoha_clk_bind(struct udevice *dev)
+{
+	struct udevice *rst_dev;
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(RESET_AIROHA)) {
+		ret = device_bind_driver_to_node(dev, "airoha-reset", "reset",
+						 dev_ofnode(dev), &rst_dev);
+		if (ret)
+			debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
+static const struct airoha_clk_soc_data en7581_data = {
+	.num_clocks = ARRAY_SIZE(en7581_base_clks),
+	.descs = en7581_base_clks,
+};
+
+static const struct udevice_id airoha_clk_ids[] = {
+	{ .compatible = "airoha,en7581-scu",
+	  .data = (ulong)&en7581_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(airoha_clk) = {
+	.name = "clk-airoha",
+	.id = UCLASS_CLK,
+	.of_match = airoha_clk_ids,
+	.probe = airoha_clk_probe,
+	.bind = airoha_clk_bind,
+	.priv_auto = sizeof(struct airoha_clk_priv),
+	.ops = &airoha_clk_ops,
+};
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 199ca6eaa37..9e3b5191767 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -97,7 +97,7 @@ static int clk_composite_disable(struct clk *clk)
 		return 0;
 }
 
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
 				   const char * const *parent_names,
 				   int num_parents, struct clk *mux,
 				   const struct clk_ops *mux_ops,
@@ -149,7 +149,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 	clk = &composite->clk;
 	clk->flags = flags;
 	ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
-			   parent_names[clk_composite_get_parent(clk)]);
+		clk_resolve_parent_clk(dev, parent_names[clk_composite_get_parent(clk)]));
 	if (ret) {
 		clk = ERR_PTR(ret);
 		goto err;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index aa210e3d15f..e692b9c2167 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -183,7 +183,7 @@ const struct clk_ops clk_divider_ops = {
 	.set_rate = clk_divider_set_rate,
 };
 
-static struct clk *_register_divider(struct device *dev, const char *name,
+static struct clk *_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags, const struct clk_div_table *table)
@@ -218,7 +218,8 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	clk = &div->clk;
 	clk->flags = flags;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name,
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(div);
 		return ERR_PTR(ret);
@@ -227,7 +228,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	return clk;
 }
 
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 068798cf9b0..4eb8be728e6 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -37,7 +37,7 @@ const struct clk_ops ccf_clk_fixed_factor_ops = {
 	.get_rate = clk_factor_recalc_rate,
 };
 
-struct clk *clk_hw_register_fixed_factor(struct device *dev,
+struct clk *clk_hw_register_fixed_factor(struct udevice *dev,
 		const char *name, const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div)
 {
@@ -56,7 +56,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev,
 	clk->flags = flags;
 
 	ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name,
-			   parent_name);
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(fix);
 		return ERR_PTR(ret);
@@ -65,7 +65,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev,
 	return clk;
 }
 
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div)
 {
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index bf1c6a93b46..256ff108991 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -117,7 +117,7 @@ const struct clk_ops clk_gate_ops = {
 	.get_rate = clk_generic_get_rate,
 };
 
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
 			      const char *parent_name, unsigned long flags,
 			      void __iomem *reg, u8 bit_idx,
 			      u8 clk_gate_flags, spinlock_t *lock)
@@ -149,7 +149,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	clk = &gate->clk;
 	clk->flags = flags;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_GATE, name,
+		clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(gate);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 62477e15d27..d7411f8f282 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -113,6 +113,11 @@ int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent)
 	for (i = 0; i < mux->num_parents; i++) {
 		if (!strcmp(parent->dev->name, mux->parent_names[i]))
 			return i;
+		if (!strcmp(parent->dev->name,
+			    clk_resolve_parent_clk(clk->dev,
+						   mux->parent_names[i])))
+			return i;
+
 	}
 
 	return -EINVAL;
@@ -159,15 +164,15 @@ const struct clk_ops clk_mux_ops = {
 	.set_parent = clk_mux_set_parent,
 };
 
-struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags,
-		void __iomem *reg, u8 shift, u32 mask,
-		u8 clk_mux_flags, u32 *table)
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags)
 {
+	u32 mask = BIT(width) - 1;
 	struct clk_mux *mux;
 	struct clk *clk;
-	u8 width = 0;
 	int ret;
 
 	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
@@ -192,7 +197,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	mux->shift = shift;
 	mux->mask = mask;
 	mux->flags = clk_mux_flags;
-	mux->table = table;
+	mux->table = NULL;
 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
 	mux->io_mux_val = *(u32 *)reg;
 #endif
@@ -207,7 +212,8 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	 * for the corresponding clock (to do that define .set_parent() method).
 	 */
 	ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
-			   parent_names[clk_mux_get_parent(clk)]);
+			   clk_resolve_parent_clk(dev,
+				parent_names[clk_mux_get_parent(clk)]));
 	if (ret) {
 		kfree(mux);
 		return ERR_PTR(ret);
@@ -216,35 +222,6 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	return clk;
 }
 
-struct clk *clk_register_mux_table(struct device *dev, const char *name,
-		const char * const *parent_names, u8 num_parents,
-		unsigned long flags,
-		void __iomem *reg, u8 shift, u32 mask,
-		u8 clk_mux_flags, u32 *table)
-{
-	struct clk *clk;
-
-	clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
-				       flags, reg, shift, mask, clk_mux_flags,
-				       table);
-	if (IS_ERR(clk))
-		return ERR_CAST(clk);
-	return clk;
-}
-
-struct clk *clk_register_mux(struct device *dev, const char *name,
-		const char * const *parent_names, u8 num_parents,
-		unsigned long flags,
-		void __iomem *reg, u8 shift, u8 width,
-		u8 clk_mux_flags)
-{
-	u32 mask = BIT(width) - 1;
-
-	return clk_register_mux_table(dev, name, parent_names, num_parents,
-				      flags, reg, shift, mask, clk_mux_flags,
-				      NULL);
-}
-
 U_BOOT_DRIVER(ccf_clk_mux) = {
 	.name	= UBOOT_DM_CLK_CCF_MUX,
 	.id	= UCLASS_CLK,
diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 5fbbb07b7f7..343fa5cd3fe 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = {
 
 static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,rpmcc" },
+	{ .compatible = "qcom,sc7280-rpmh-clk" },
 	{ .compatible = "qcom,sm8150-rpmh-clk" },
 	{ .compatible = "qcom,sm8250-rpmh-clk" },
 	{ .compatible = "qcom,sm8550-rpmh-clk" },
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 353ae476068..90b70529a47 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -420,6 +420,24 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
 	return clk_get_by_index_nodev(node, index, clk);
 }
 
+const char *
+clk_resolve_parent_clk(struct udevice *dev, const char *name)
+{
+	struct udevice *parent;
+	struct clk clk;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_CLK, name, &parent);
+	if (!ret)
+		return name;
+
+	ret = clk_get_by_name(dev, name, &clk);
+	if (!clk.dev)
+		return name;
+
+	return clk.dev->name;
+}
+
 int clk_release_all(struct clk *clk, unsigned int count)
 {
 	unsigned int i;
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 56d893e0579..d17a54fb9b3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -60,6 +60,7 @@ config SPL_CLK_IMX8MP
 	depends on ARCH_IMX8M && SPL
 	select SPL_CLK
 	select SPL_CLK_CCF
+	select SPL_CLK_COMPOSITE_CCF
 	help
 	  This enables SPL DM/DTS support for clock driver in i.MX8MP
 
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 64bffa3b181..14c5b92939c 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -151,7 +151,7 @@ const struct clk_ops imx8m_clk_mux_ops = {
 	.set_parent = imx8m_clk_mux_set_parent,
 };
 
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
 				      const char * const *parent_names,
 				      int num_parents, void __iomem *reg,
 				      unsigned long flags)
@@ -187,7 +187,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
 	gate->reg = reg;
 	gate->bit_idx = PCG_CGC_SHIFT;
 
-	clk = clk_register_composite(NULL, name,
+	clk = clk_register_composite(dev, name,
 				     parent_names, num_parents,
 				     &mux->clk, &imx8m_clk_mux_ops, &div->clk,
 				     &imx8m_clk_composite_divider_ops,
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 65fa6b5b139..fa07b13249b 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -90,7 +90,7 @@ static const struct clk_ops clk_gate2_ops = {
 	.get_rate = clk_generic_get_rate,
 };
 
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate2_flags, unsigned int *share_count)
@@ -111,7 +111,8 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
 
 	clk = &gate->clk;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name,
+		clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(gate);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f0285e1e..13239f2f64d 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,8 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *const periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
 					       "pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
 {
@@ -44,21 +46,21 @@ static int imx6q_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX6QDL_CLK_PLL2,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
 			     base + 0x30, 0x1));
 	clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
 			     base + 0x10, 0x3));
 	clk_dm(IMX6QDL_CLK_PLL3_60M,
-	       imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
+	       imx_clk_fixed_factor(dev, "pll3_60m",  "pll3_usb_otg",   1, 8));
 	clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
 	clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
 	       imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
 	clk_dm(IMX6QDL_CLK_PLL6,
-	       imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+	       imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
 	clk_dm(IMX6QDL_CLK_PLL6_ENET,
-	       imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
+	       imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
@@ -66,76 +68,98 @@ static int imx6q_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMX6QDL_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC3_SEL,
-	       imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
+	       imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC4_SEL,
-	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
+	       imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
+	if (of_machine_is_compatible("fsl,imx6qp")) {
+		clk_dm(IMX6QDL_CLK_UART_SEL,
+		       imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels,
+				   ARRAY_SIZE(uart_sels)));
+		clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+		       imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
+				   ARRAY_SIZE(ecspi_sels)));
+	}
+
 	clk_dm(IMX6QDL_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMX6QDL_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMX6QDL_CLK_USDHC3_PODF,
-	       imx_clk_divider("usdhc3_podf", "usdhc3_sel",
+	       imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel",
 			       base + 0x24, 19, 3));
 	clk_dm(IMX6QDL_CLK_USDHC4_PODF,
-	       imx_clk_divider("usdhc4_podf", "usdhc4_sel",
+	       imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel",
 			       base + 0x24, 22, 3));
 
-	clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
-	       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	if (of_machine_is_compatible("fsl,imx6qp")) {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+	} else {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	}
 
 	clk_dm(IMX6QDL_CLK_ECSPI1,
-	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+	       imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0));
 	clk_dm(IMX6QDL_CLK_ECSPI2,
-	       imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
+	       imx_clk_gate2(dev, "ecspi2", "ecspi_root", base + 0x6c, 2));
 	clk_dm(IMX6QDL_CLK_ECSPI3,
-	       imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
+	       imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4));
 	clk_dm(IMX6QDL_CLK_ECSPI4,
-	       imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+	       imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6));
+	clk_dm(IMX6QDL_CLK_UART_IPG,
+	       imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24));
+	clk_dm(IMX6QDL_CLK_UART_SERIAL,
+	       imx_clk_gate2(dev, "uart_serial", "uart_serial_podf",  base + 0x7c, 26));
 	clk_dm(IMX6QDL_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMX6QDL_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMX6QDL_CLK_USDHC3,
-	       imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
+	       imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6));
 	clk_dm(IMX6QDL_CLK_USDHC4,
-	       imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
+	       imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8));
 
 	clk_dm(IMX6QDL_CLK_PERIPH_PRE,
-	       imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
+	       imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels,
 			   ARRAY_SIZE(periph_pre_sels)));
 	clk_dm(IMX6QDL_CLK_PERIPH,
-	       imx_clk_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48,
+	       imx_clk_busy_mux(dev, "periph",  base + 0x14, 25, 1, base + 0x48,
 				5, periph_sels,  ARRAY_SIZE(periph_sels)));
 	clk_dm(IMX6QDL_CLK_AHB,
-	       imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
+	       imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3,
 				    base + 0x48, 1));
 	clk_dm(IMX6QDL_CLK_IPG,
-	       imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
+	       imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2));
 	clk_dm(IMX6QDL_CLK_IPG_PER,
-	       imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
+	       imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6));
 	clk_dm(IMX6QDL_CLK_I2C1,
-	       imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
+	       imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6));
 	clk_dm(IMX6QDL_CLK_I2C2,
-	       imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
+	       imx_clk_gate2(dev, "i2c2", "ipg_per", base + 0x70, 8));
 	clk_dm(IMX6QDL_CLK_I2C3,
-	       imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10));
+	       imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10));
 	clk_dm(IMX6QDL_CLK_PWM1,
-	       imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16));
+	       imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16));
 
-	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
+	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
 	clk_dm(IMX6QDL_CLK_ENET_REF,
-	       imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
+	       imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1));
 
 	return 0;
 }
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bb6958f0ec2..b81db516a69 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -14,7 +14,7 @@
 
 #include "clk.h"
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,128 +23,144 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll1_out", };
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 						    "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
 						    "audio_pll2_out", };
 #endif
 
-static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
-static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m",
+static const char * const imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
 						      "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
 						      "sys_pll2_333m", "sys_pll3_out", };
 
-static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m",
+static const char * const imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
 						     "clk_ext1", "clk_ext2", "clk_ext3",
 						     "clk_ext4", "sys_pll1_400m", };
 
-static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
 						     "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
 						     "sys_pll1_160m", "sys_pll1_200m", };
 #endif
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 #endif
 
-static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m", };
 
-static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_clk", "sys_pll1_100m", };
 
 #if CONFIG_IS_ENABLED(NXP_FSPI)
-static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 #endif
 
-static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext3", "audio_pll2_out", };
 
 #if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 #endif
@@ -156,19 +172,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
-	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+	       imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
-	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+	       imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
-	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+	       imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MM_DRAM_PLL,
@@ -189,238 +205,254 @@ static int imx8mm_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MM_DRAM_PLL_BYPASS,
-	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+	       imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
 				 dram_pll_bypass_sels,
 				 ARRAY_SIZE(dram_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL1_BYPASS,
-	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
 				 sys_pll1_bypass_sels,
 				 ARRAY_SIZE(sys_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL2_BYPASS,
-	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
 				 sys_pll2_bypass_sels,
 				 ARRAY_SIZE(sys_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL3_BYPASS,
-	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
 				 sys_pll3_bypass_sels,
 				 ARRAY_SIZE(sys_pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MM_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
 			    base + 0x50, 13));
 	clk_dm(IMX8MM_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x84, 11));
 	clk_dm(IMX8MM_SYS_PLL1_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
 			    base + 0x94, 11));
 	clk_dm(IMX8MM_SYS_PLL2_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
 			    base + 0x104, 11));
 	clk_dm(IMX8MM_SYS_PLL3_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
 			    base + 0x114, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MM_SYS_PLL1_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MM_SYS_PLL1_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MM_SYS_PLL1_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MM_SYS_PLL1_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MM_SYS_PLL1_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MM_SYS_PLL1_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MM_SYS_PLL1_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MM_SYS_PLL1_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MM_SYS_PLL1_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MM_SYS_PLL2_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MM_SYS_PLL2_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MM_SYS_PLL2_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MM_SYS_PLL2_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MM_SYS_PLL2_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MM_SYS_PLL2_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MM_SYS_PLL2_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MM_SYS_PLL2_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MM_SYS_PLL2_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	base = dev_read_addr_ptr(dev);
 	if (!base)
 		return -EINVAL;
 
 	clk_dm(IMX8MM_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
 	clk_dm(IMX8MM_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MM_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 
 	clk_dm(IMX8MM_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MM_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mm_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MM_CLK_USB_BUS,
-		imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
+		imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
 
 	/* IP */
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
 	clk_dm(IMX8MM_CLK_PCIE1_CTRL,
-	       imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+	       imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
 				   base + 0xa300));
 	clk_dm(IMX8MM_CLK_PCIE1_PHY,
-	       imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+	       imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels,
 				   base + 0xa380));
 	clk_dm(IMX8MM_CLK_PCIE1_AUX,
-	       imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+	       imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels,
 				   base + 0xa400));
 #endif
 	clk_dm(IMX8MM_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MM_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MM_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MM_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MM_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MM_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MM_CLK_UART1,
+	       imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MM_CLK_UART2,
+	       imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MM_CLK_UART3,
+	       imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MM_CLK_UART4,
+	       imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MM_CLK_UART1_ROOT,
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MM_CLK_UART2_ROOT,
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MM_CLK_UART3_ROOT,
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MM_CLK_UART4_ROOT,
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MM_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MM_CLK_USDHC3,
-	       imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+	       imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels,
 				   base + 0xbc80));
 	clk_dm(IMX8MM_CLK_USB_CORE_REF,
-		imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
+		imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MM_CLK_USB_PHY_REF,
-		imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
+		imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
 	clk_dm(IMX8MM_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MM_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MM_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MM_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MM_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MM_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MM_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MM_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MM_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MM_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MM_CLK_USDHC3_ROOT,
-	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	       imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 	clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
-		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+		imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 
 	/* clks not needed in SPL stage */
 #ifndef CONFIG_XPL_BUILD
 	clk_dm(IMX8MM_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MM_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels,
 	       base + 0xa980));
 	clk_dm(IMX8MM_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels,
 	       base + 0xaa00));
 	clk_dm(IMX8MM_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels,
 	       base + 0xaa80));
 	clk_dm(IMX8MM_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 	       base + 0x40a0, 0));
 	clk_dm(IMX8MM_CLK_PWM1,
-	       imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+	       imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380));
 	clk_dm(IMX8MM_CLK_PWM2,
-	       imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+	       imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400));
 	clk_dm(IMX8MM_CLK_PWM3,
-	       imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+	       imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480));
 	clk_dm(IMX8MM_CLK_PWM4,
-	       imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+	       imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500));
 	clk_dm(IMX8MM_CLK_PWM1_ROOT,
-	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	       imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
 	clk_dm(IMX8MM_CLK_PWM2_ROOT,
-	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	       imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
 	clk_dm(IMX8MM_CLK_PWM3_ROOT,
-	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	       imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
 	clk_dm(IMX8MM_CLK_PWM4_ROOT,
-	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	       imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
 	clk_dm(IMX8MM_CLK_PCIE1_ROOT,
-	       imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+	       imx_clk_gate4(dev, "pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(DM_SPI)
 	clk_dm(IMX8MM_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MM_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MM_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
 
 	clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(NXP_FSPI)
 	clk_dm(IMX8MM_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MM_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 #endif
 
 	clk_dm(IMX8MM_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mm_arm_core_sels,
 				  ARRAY_SIZE(imx8mm_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be15ebd0e25..be5b7933a8d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -16,7 +16,7 @@
 
 static u32 share_count_nand;
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -25,117 +25,133 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll_out", };
 
-static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll_out", "sys_pll3_out", };
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll_out", "clk_ext4", };
 
-static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll_out", };
 
-static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 						    "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
 						    "video_pll_out", "audio_pll2_out", };
 #endif
 
-static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
 #if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 #endif
 
-static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll_out", };
 #endif
 
-static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"m7_alt_pll", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m", };
 
-static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_clk", "sys_pll1_100m", };
 
-static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 
-static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out",
+static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
 						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
 						"sys_pll2_250m", "video_pll_out", };
 
-static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext3", "audio_pll2_out", };
 
@@ -148,19 +164,19 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
-	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+	       imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
-	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+	       imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
-	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+	       imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MN_DRAM_PLL,
@@ -181,86 +197,86 @@ static int imx8mn_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MN_DRAM_PLL_BYPASS,
-	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+	       imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
 				 dram_pll_bypass_sels,
 				 ARRAY_SIZE(dram_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL1_BYPASS,
-	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
 				 sys_pll1_bypass_sels,
 				 ARRAY_SIZE(sys_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL2_BYPASS,
-	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
 				 sys_pll2_bypass_sels,
 				 ARRAY_SIZE(sys_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL3_BYPASS,
-	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
 				 sys_pll3_bypass_sels,
 				 ARRAY_SIZE(sys_pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MN_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
 			    base + 0x50, 13));
 	clk_dm(IMX8MN_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x84, 11));
 	clk_dm(IMX8MN_SYS_PLL1_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
 			    base + 0x94, 11));
 	clk_dm(IMX8MN_SYS_PLL2_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
 			    base + 0x104, 11));
 	clk_dm(IMX8MN_SYS_PLL3_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
 			    base + 0x114, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MN_SYS_PLL1_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MN_SYS_PLL1_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MN_SYS_PLL1_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MN_SYS_PLL1_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MN_SYS_PLL1_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MN_SYS_PLL1_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MN_SYS_PLL1_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MN_SYS_PLL1_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MN_SYS_PLL1_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MN_SYS_PLL2_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MN_SYS_PLL2_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MN_SYS_PLL2_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MN_SYS_PLL2_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MN_SYS_PLL2_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MN_SYS_PLL2_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MN_SYS_PLL2_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MN_SYS_PLL2_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MN_SYS_PLL2_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
 	if (ret)
@@ -272,141 +288,157 @@ static int imx8mn_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMX8MN_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
 	clk_dm(IMX8MN_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MN_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 
 	clk_dm(IMX8MN_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MN_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MN_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mn_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MN_CLK_USB_BUS,
-		imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
+		imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
 
 	/* IP */
 	clk_dm(IMX8MN_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MN_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MN_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MN_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MN_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MN_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MN_CLK_UART1,
+	       imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MN_CLK_UART2,
+	       imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MN_CLK_UART3,
+	       imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MN_CLK_UART4,
+	       imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080));
 	clk_dm(IMX8MN_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MN_CLK_USDHC3,
-	       imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+	       imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels,
 				   base + 0xbc80));
 	clk_dm(IMX8MN_CLK_NAND,
-	       imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
+	       imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00));
 	clk_dm(IMX8MN_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MN_CLK_USB_CORE_REF,
-		imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+		imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MN_CLK_USB_PHY_REF,
-		imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
+		imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
 
 	clk_dm(IMX8MN_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MN_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MN_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MN_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MN_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MN_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MN_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MN_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MN_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MN_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MN_CLK_USDHC3_ROOT,
-	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	       imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 	clk_dm(IMX8MN_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 	clk_dm(IMX8MN_CLK_NAND_ROOT,
-	       imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
+	       imx_clk_gate2_shared2(dev, "nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
 	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
-	       imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
+	       imx_clk_gate2_shared2(dev, "nand_usdhc_rawnand_clk",
 				     "nand_usdhc_bus", base + 0x4300, 0,
 				     &share_count_nand));
+	clk_dm(IMX8MN_CLK_UART1_ROOT,
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MN_CLK_UART2_ROOT,
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MN_CLK_UART3_ROOT,
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MN_CLK_UART4_ROOT,
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
-		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+		imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 
 	/* clks not needed in SPL stage */
 #ifndef CONFIG_XPL_BUILD
 	clk_dm(IMX8MN_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels,
 	       base + 0xa980));
 	clk_dm(IMX8MN_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels,
 	       base + 0xaa00));
 	clk_dm(IMX8MN_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels,
 	       base + 0xaa80));
 	clk_dm(IMX8MN_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 	       base + 0x40a0, 0));
 	clk_dm(IMX8MN_CLK_PWM1,
-	       imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+	       imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380));
 	clk_dm(IMX8MN_CLK_PWM2,
-	       imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+	       imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400));
 	clk_dm(IMX8MN_CLK_PWM3,
-	       imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+	       imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480));
 	clk_dm(IMX8MN_CLK_PWM4,
-	       imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+	       imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500));
 	clk_dm(IMX8MN_CLK_PWM1_ROOT,
-	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	       imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
 	clk_dm(IMX8MN_CLK_PWM2_ROOT,
-	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	       imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
 	clk_dm(IMX8MN_CLK_PWM3_ROOT,
-	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	       imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
 	clk_dm(IMX8MN_CLK_PWM4_ROOT,
-	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	       imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(DM_SPI)
 	clk_dm(IMX8MN_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MN_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MN_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
 	clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
 
 	clk_dm(IMX8MN_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mn_arm_core_sels,
 				  ARRAY_SIZE(imx8mn_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 1d04090ca00..bad579f8d5e 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -14,7 +14,7 @@
 
 #include "clk.h"
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,167 +23,167 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
+static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll1_100m",};
 
-static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
 					       "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
 					       "video_pll1_out", "audio_pll2_out", };
 
-static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
 						  "video_pll1_out", "audio_pll2_out", };
 
-static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll1_out", };
 
-static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
+static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
 						    "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
 						    "audio_pll1_out", "sys_pll1_266m", };
 
-static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						    "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						    "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
 						    "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
 						    "sys_pll1_160m", "sys_pll1_200m", };
 
-static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 							  "clk_ext1", "clk_ext2", "clk_ext3",
 							  "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 							"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 							"clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						       "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						       "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 					       "sys_pll2_100m", "sys_pll1_800m",
 					       "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
 
-static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m" };
 
-static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 							"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
 							"video_pll1_out", "audio_pll2_out", };
 
@@ -199,11 +199,11 @@ static int imx8mp_clk_probe(struct udevice *dev)
 
 	clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
 
-	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
 						&imx_1443x_dram_pll));
@@ -216,37 +216,37 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
 						&imx_1416x_pll));
 
-	clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
-
-	clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
-	clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
-	clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
-	clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
-	clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
-
-	clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
-	clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
-	clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
-	clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
-	clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
-	clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
-	clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
-	clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
-	clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
-
-	clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
-	clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
-	clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
-	clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
-	clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
-	clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
-	clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
-	clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
-	clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
+
+	clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
+	clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
+	clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
+	clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
+	clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
+
+	clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
+	clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
+	clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
+	clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
+	clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
+	clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
+	clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
+	clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
+	clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+	clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
+	clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
+	clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
+	clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
+	clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
+	clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
+	clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
+	clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
+	clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
 	if (ret)
@@ -262,104 +262,104 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	if (!base)
 		return -EINVAL;
 
-	clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
-	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
-	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
-
-	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
-	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
-	clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
-	clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
-	clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
-	clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
-
-	clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
-
-	clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
-
-	clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
-	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
-	clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
-	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
-	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
-	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
-	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
-	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
-	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
-	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
-	clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
-	clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
-	clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
-	clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
-	clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
-	clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
-	clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
-
-	clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
-	clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
-	clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
-	clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
-	clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
-	clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
-	clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
-	clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
-	clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
-	clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380));
-	clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400));
-	clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480));
-	clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500));
-	clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
-
-	clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
-	clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
-
-	clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
-	clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
-
-	clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
-	clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
-	clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
-	clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
-	clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
-	clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
-	clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
-	clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
-	clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
-	clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
-	clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
-	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
-	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
-	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
-	clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0));
-	clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
-	clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
-	clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
-	clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
-	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
-	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
-	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
-	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
-	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
-	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
-	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
-	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
-	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
-	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
-	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
-	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));
-	clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0));
-	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
-	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
-	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
-	clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
-	clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
-	clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
-	clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0));
-
-	clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
+	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
+
+	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800));
+	clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
+	clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
+	clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00));
+	clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80));
+
+	clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000));
+
+	clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1));
+
+	clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
+	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+	clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
+	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480));
+	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500));
+	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
+	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
+	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
+	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
+	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
+	clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80));
+	clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
+	clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
+	clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00));
+	clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80));
+	clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00));
+	clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80));
+
+	clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+	clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
+	clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200));
+	clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
+	clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
+	clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380));
+	clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400));
+	clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480));
+	clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500));
+	clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
+
+	clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900));
+	clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
+
+	clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
+	clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
+
+	clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
+	clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0));
+	clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4(dev, "gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
+	clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4(dev, "gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
+	clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4(dev, "gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
+	clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4(dev, "gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
+	clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4(dev, "gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
+	clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4(dev, "pcie_root_clk", "pcie_aux", base + 0x4250, 0));
+	clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4(dev, "qos_root_clk", "ipg_root", base + 0x42c0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4(dev, "qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
+	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
+	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2(dev, "i2c5_root_clk", "i2c5", base + 0x4330, 0));
+	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2(dev, "i2c6_root_clk", "i2c6", base + 0x4340, 0));
+	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4(dev, "sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
+	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4(dev, "enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
+	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
+	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "osc_24m", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
+	clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
+	clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
+	clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0));
+
+	clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 
 	clk_dm(IMX8MP_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mp_arm_core_sels,
 				  ARRAY_SIZE(imx8mp_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index ed4acd79ef7..fe6cba19758 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -152,31 +152,31 @@ static int imx8mq_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000));
 
 	clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_GPU_PLL_REF_SEL,
-	       imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
+	       imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VPU_PLL_REF_SEL,
-	       imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
+	       imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL,
-	       imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
+	       imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL,
-	       imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+	       imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL,
-	       imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
+	       imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL,
-	       imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2,
+	       imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL,
-	       imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2,
+	       imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MQ_ARM_PLL,
@@ -207,140 +207,140 @@ static int imx8mq_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MQ_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x28, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_GPU_PLL_BYPASS,
-	       imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1,
+	       imx_clk_mux_flags(dev, "gpu_pll_bypass", base + 0x18, 4, 1,
 				 gpu_pll_bypass_sels,
 				 ARRAY_SIZE(gpu_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_VPU_PLL_BYPASS,
-	       imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1,
+	       imx_clk_mux_flags(dev, "vpu_pll_bypass", base + 0x20, 4, 1,
 				 vpu_pll_bypass_sels,
 				 ARRAY_SIZE(vpu_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS,
-	       imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1,
+	       imx_clk_mux_flags(dev, "audio_pll1_bypass", base + 0x0, 4, 1,
 				 audio_pll1_bypass_sels,
 				 ARRAY_SIZE(audio_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS,
-	       imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1,
+	       imx_clk_mux_flags(dev, "audio_pll2_bypass", base + 0x8, 4, 1,
 				 audio_pll2_bypass_sels,
 				 ARRAY_SIZE(audio_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS,
-	       imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1,
+	       imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x10, 4, 1,
 				 video_pll1_bypass_sels,
 				 ARRAY_SIZE(video_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MQ_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_ref_sel",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_ref_sel",
 			    base + 0x60, 13));
 	clk_dm(IMX8MQ_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x28, 11));
 	clk_dm(IMX8MQ_GPU_PLL_OUT,
-	       imx_clk_gate("gpu_pll_out", "gpu_pll_bypass",
+	       imx_clk_gate(dev, "gpu_pll_out", "gpu_pll_bypass",
 			    base + 0x18, 11));
 	clk_dm(IMX8MQ_VPU_PLL_OUT,
-	       imx_clk_gate("vpu_pll_out", "vpu_pll_bypass",
+	       imx_clk_gate(dev, "vpu_pll_out", "vpu_pll_bypass",
 			    base + 0x20, 11));
 	clk_dm(IMX8MQ_AUDIO_PLL1_OUT,
-	       imx_clk_gate("audio_pll1_out", "audio_pll1_bypass",
+	       imx_clk_gate(dev, "audio_pll1_out", "audio_pll1_bypass",
 			    base + 0x0, 11));
 	clk_dm(IMX8MQ_AUDIO_PLL2_OUT,
-	       imx_clk_gate("audio_pll2_out", "audio_pll2_bypass",
+	       imx_clk_gate(dev, "audio_pll2_out", "audio_pll2_bypass",
 			    base + 0x8, 11));
 	clk_dm(IMX8MQ_VIDEO_PLL1_OUT,
-	       imx_clk_gate("video_pll1_out", "video_pll1_bypass",
+	       imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass",
 			    base + 0x10, 11));
 
 	clk_dm(IMX8MQ_SYS1_PLL_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys1_pll",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys1_pll",
 			    base + 0x30, 11));
 	clk_dm(IMX8MQ_SYS2_PLL_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys2_pll",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys2_pll",
 			    base + 0x3c, 11));
 	clk_dm(IMX8MQ_SYS3_PLL_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys3_pll",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys3_pll",
 			    base + 0x48, 11));
 	clk_dm(IMX8MQ_VIDEO2_PLL_OUT,
-	       imx_clk_gate("video_pll2_out", "video_pll2_ref_sel",
+	       imx_clk_gate(dev, "video_pll2_out", "video_pll2_ref_sel",
 			    base + 0x54, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MQ_SYS1_PLL_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MQ_SYS1_PLL_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MQ_SYS1_PLL_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MQ_SYS1_PLL_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MQ_SYS1_PLL_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MQ_SYS1_PLL_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MQ_SYS1_PLL_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MQ_SYS1_PLL_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MQ_SYS1_PLL_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MQ_SYS2_PLL_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MQ_SYS2_PLL_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MQ_SYS2_PLL_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MQ_SYS2_PLL_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MQ_SYS2_PLL_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MQ_SYS2_PLL_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MQ_SYS2_PLL_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MQ_SYS2_PLL_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MQ_SYS2_PLL_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV,
-	       imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
+	       imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
 	clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV,
-	       imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
+	       imx_clk_divider(dev, "audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
 	clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV,
-	       imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
+	       imx_clk_divider(dev, "video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
 	clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV,
-	       imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
+	       imx_clk_divider(dev, "gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
 	clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV,
-	       imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
+	       imx_clk_divider(dev, "vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
 	clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV,
-	       imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
+	       imx_clk_divider(dev, "arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV,
-	       imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
+	       imx_clk_divider(dev, "sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV,
-	       imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
+	       imx_clk_divider(dev, "sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV,
-	       imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
+	       imx_clk_divider(dev, "sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
 	clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV,
-	       imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
+	       imx_clk_divider(dev, "dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
 	clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV,
-	       imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
+	       imx_clk_divider(dev, "video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
 	clk_dm(IMX8MQ_CLK_MON_SEL,
-	       imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4,
+	       imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4,
 				 pllout_monitor_sels,
 				 ARRAY_SIZE(pllout_monitor_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_CLK_MON_CLK2_OUT,
-	       imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
+	       imx_clk_gate4(dev, "pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
 
 	base = dev_read_addr_ptr(dev);
 	if (!base) {
@@ -349,140 +349,140 @@ static int imx8mq_clk_probe(struct udevice *dev)
 	}
 
 	clk_dm(IMX8MQ_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)));
 	clk_dm(IMX8MQ_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MQ_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 	clk_dm(IMX8MQ_CLK_A53_CORE,
-	       imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1,
 			    imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
 
 	clk_dm(IMX8MQ_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MQ_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MQ_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mq_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MQ_CLK_USB_BUS,
-	       imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
+	       imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
 
 	/* DRAM */
 	clk_dm(IMX8MQ_CLK_DRAM_CORE,
-	       imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1,
+	       imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1,
 			    imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
 	clk_dm(IMX8MQ_CLK_DRAM_ALT,
-	       imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
+	       imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
 	clk_dm(IMX8MQ_CLK_DRAM_APB,
-	       imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
+	       imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
 
 	/* IP */
 	clk_dm(IMX8MQ_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MQ_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MQ_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MQ_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MQ_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MQ_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80));
 	clk_dm(IMX8MQ_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MQ_CLK_UART1,
-	       imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
+	       imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00));
 	clk_dm(IMX8MQ_CLK_UART2,
-	       imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
+	       imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80));
 	clk_dm(IMX8MQ_CLK_UART3,
-	       imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
+	       imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000));
 	clk_dm(IMX8MQ_CLK_UART4,
-	       imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
+	       imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080));
 	clk_dm(IMX8MQ_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MQ_CLK_USB_CORE_REF,
-	       imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
+	       imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MQ_CLK_USB_PHY_REF,
-	       imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
+	       imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
 	clk_dm(IMX8MQ_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MQ_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MQ_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
 
 	clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MQ_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MQ_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 	clk_dm(IMX8MQ_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MQ_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MQ_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MQ_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MQ_CLK_UART1_ROOT,
-	       imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
 	clk_dm(IMX8MQ_CLK_UART2_ROOT,
-	       imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
 	clk_dm(IMX8MQ_CLK_UART3_ROOT,
-	       imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
 	clk_dm(IMX8MQ_CLK_UART4_ROOT,
-	       imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MQ_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MQ_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MQ_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MQ_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MQ_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MQ_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MQ_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 	clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT,
-	       imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+	       imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 	clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT,
-	       imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
+	       imx_clk_gate4(dev, "usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
 	clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT,
-	       imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+	       imx_clk_gate4(dev, "usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
 	clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT,
-	       imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
+	       imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
 
 	clk_dm(IMX8MQ_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels,
 				   base + 0xa980));
 	clk_dm(IMX8MQ_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels,
 				   base + 0xaa00));
 	clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels,
 				   base + 0xaa80));
 	clk_dm(IMX8MQ_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 			     base + 0x40a0, 0));
 
 	clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT,
-	       imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
+	       imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
 
 	return 0;
 }
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index b31e57a4a01..c3112968c17 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -291,15 +291,15 @@ static int imx93_clk_probe(struct udevice *dev)
 	clk_dm(IMX93_CLK_SYS_PLL_PFD0,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD1,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD2,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
 
 	anatop_base = (void *)ANATOP_BASE_ADDR;
 
@@ -338,7 +338,7 @@ static int imx93_clk_probe(struct udevice *dev)
 	}
 
 	clk_dm(IMX93_CLK_A55_SEL,
-	       imx_clk_mux2("a55_sel", base + 0x4820, 0, 1,
+	       imx_clk_mux2(dev, "a55_sel", base + 0x4820, 0, 1,
 			    a55_core_sels, ARRAY_SIZE(a55_core_sels)));
 
 	return 0;
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 752434cb0ad..c14afdaf236 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -38,26 +38,26 @@ static int imxrt1020_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1020_CLK_PLL2_SYS,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc",
 			     base + 0x30, 0x1));
 	clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
 			     base + 0x10, 0x1));
 
 	/* PLL bypass out */
 	clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
-	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+	       imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
 				 pll2_bypass_sels,
 				 ARRAY_SIZE(pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
-	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+	       imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
 				 pll3_bypass_sels,
 				 ARRAY_SIZE(pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	clk_dm(IMXRT1020_CLK_PLL3_80M,
-	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+	       imx_clk_fixed_factor(dev, "pll3_80m",  "pll3_usb_otg",   1, 6));
 
 	clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -78,51 +78,51 @@ static int imxrt1020_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
-	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+	       imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
 			   pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
 	clk_dm(IMXRT1020_CLK_PERIPH_SEL,
-	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+	       imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
 			   periph_sels, ARRAY_SIZE(periph_sels)));
 	clk_dm(IMXRT1020_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1020_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1020_CLK_LPUART_SEL,
-	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+	       imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
 			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
 	clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
-	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+	       imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
 			   semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
 	clk_dm(IMXRT1020_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+	       imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 
 	clk_dm(IMXRT1020_CLK_AHB_PODF,
-	       imx_clk_divider("ahb_podf", "periph_sel",
+	       imx_clk_divider(dev, "ahb_podf", "periph_sel",
 			       base + 0x14, 10, 3));
 	clk_dm(IMXRT1020_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMXRT1020_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMXRT1020_CLK_LPUART_PODF,
-	       imx_clk_divider("lpuart_podf", "lpuart_sel",
+	       imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
 			       base + 0x24, 0, 6));
 	clk_dm(IMXRT1020_CLK_SEMC_PODF,
-	       imx_clk_divider("semc_podf", "semc_sel",
+	       imx_clk_divider(dev, "semc_podf", "semc_sel",
 			       base + 0x14, 16, 3));
 
 	clk_dm(IMXRT1020_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMXRT1020_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMXRT1020_CLK_LPUART1,
-	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+	       imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
 	clk_dm(IMXRT1020_CLK_SEMC,
-	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+	       imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
 
 #ifdef CONFIG_XPL_BUILD
 	struct clk *clk, *clk1;
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 2c029ec5a6e..ba5b48748ef 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -36,63 +36,63 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
-	       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+	       imx_clk_mux(dev, "pll1_arm_ref_sel", base + 0x0, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
-	       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
+	       imx_clk_mux(dev, "pll2_sys_ref_sel", base + 0x30, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
-	       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
+	       imx_clk_mux(dev, "pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
-	       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
+	       imx_clk_mux(dev, "pll5_video_ref_sel", base + 0xa0, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMXRT1050_CLK_PLL1_ARM,
-	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
 			     base + 0x0, 0x7f));
 	clk_dm(IMXRT1050_CLK_PLL2_SYS,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
 			     base + 0x30, 0x1));
 	clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg",
 			     "pll3_usb_otg_ref_sel",
 			     base + 0x10, 0x1));
 	clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
-	       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
 			     base + 0xa0, 0x7f));
 
 	/* PLL bypass out */
 	clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
-	       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
+	       imx_clk_mux_flags(dev, "pll1_bypass", base + 0x0, 16, 1,
 				 pll1_bypass_sels,
 				 ARRAY_SIZE(pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
-	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+	       imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
 				 pll2_bypass_sels,
 				 ARRAY_SIZE(pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
-	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+	       imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
 				 pll3_bypass_sels,
 				 ARRAY_SIZE(pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
-	       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
+	       imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1,
 				 pll5_bypass_sels,
 				 ARRAY_SIZE(pll5_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
-	       imx_clk_divider("video_post_div_sel", "pll5_video",
+	       imx_clk_divider(dev, "video_post_div_sel", "pll5_video",
 			       base + 0xa0, 19, 2));
 	clk_dm(IMXRT1050_CLK_VIDEO_DIV,
-	       imx_clk_divider("video_div", "video_post_div_sel",
+	       imx_clk_divider(dev, "video_div", "video_post_div_sel",
 			       base + 0x170, 30, 2));
 
 	clk_dm(IMXRT1050_CLK_PLL3_80M,
-	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+	       imx_clk_fixed_factor(dev, "pll3_80m",  "pll3_usb_otg",   1, 6));
 
 	clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -113,73 +113,73 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1050_CLK_ARM_PODF,
-	       imx_clk_divider("arm_podf", "pll1_arm",
+	       imx_clk_divider(dev, "arm_podf", "pll1_arm",
 			       base + 0x10, 0, 3));
 
 	clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
-	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+	       imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
 			   pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
 	clk_dm(IMXRT1050_CLK_PERIPH_SEL,
-	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+	       imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
 			   periph_sels, ARRAY_SIZE(periph_sels)));
 	clk_dm(IMXRT1050_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1050_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1050_CLK_LPUART_SEL,
-	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+	       imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
 			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
 	clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
-	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+	       imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
 			   semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
 	clk_dm(IMXRT1050_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+	       imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 	clk_dm(IMXRT1050_CLK_LCDIF_SEL,
-	       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
+	       imx_clk_mux(dev, "lcdif_sel", base + 0x38, 15, 3,
 			   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
 
 	clk_dm(IMXRT1050_CLK_AHB_PODF,
-	       imx_clk_divider("ahb_podf", "periph_sel",
+	       imx_clk_divider(dev, "ahb_podf", "periph_sel",
 			       base + 0x14, 10, 3));
 	clk_dm(IMXRT1050_CLK_IPG_PDOF,
-	       imx_clk_divider("ipg_podf", "ahb_podf",
+	       imx_clk_divider(dev, "ipg_podf", "ahb_podf",
 			       base + 0x14, 8, 2));
 	clk_dm(IMXRT1050_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMXRT1050_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMXRT1050_CLK_LPUART_PODF,
-	       imx_clk_divider("lpuart_podf", "lpuart_sel",
+	       imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
 			       base + 0x24, 0, 6));
 	clk_dm(IMXRT1050_CLK_SEMC_PODF,
-	       imx_clk_divider("semc_podf", "semc_sel",
+	       imx_clk_divider(dev, "semc_podf", "semc_sel",
 			       base + 0x14, 16, 3));
 	clk_dm(IMXRT1050_CLK_LCDIF_PRED,
-	       imx_clk_divider("lcdif_pred", "lcdif_sel",
+	       imx_clk_divider(dev, "lcdif_pred", "lcdif_sel",
 			       base + 0x38, 12, 3));
 	clk_dm(IMXRT1050_CLK_LCDIF_PODF,
-	       imx_clk_divider("lcdif_podf", "lcdif_pred",
+	       imx_clk_divider(dev, "lcdif_podf", "lcdif_pred",
 			       base + 0x18, 23, 3));
 
 	clk_dm(IMXRT1050_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMXRT1050_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMXRT1050_CLK_LPUART1,
-	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+	       imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
 	clk_dm(IMXRT1050_CLK_SEMC,
-	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+	       imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
 	clk_dm(IMXRT1050_CLK_LCDIF_APB,
-	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+	       imx_clk_gate2(dev, "lcdif", "lcdif_podf", base + 0x70, 28));
 	clk_dm(IMXRT1050_CLK_LCDIF_PIX,
-	       imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
+	       imx_clk_gate2(dev, "lcdif_pix", "lcdif", base + 0x74, 10));
 	clk_dm(IMXRT1050_CLK_USBOH3,
-	       imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0));
+	       imx_clk_gate2(dev, "usboh3", "pll3_usb_otg", base + 0x80, 0));
 
 	struct clk *clk, *clk1;
 
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
index 88a294f4165..3f55d0d0127 100644
--- a/drivers/clk/imx/clk-imxrt1170.c
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -114,20 +114,20 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1170_CLK_RCOSC_48M,
-	       imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
+	       imx_clk_fixed_factor(dev, "rcosc48M", "rcosc16M", 3, 1));
 	clk_dm(IMXRT1170_CLK_RCOSC_400M,
-	       imx_clk_fixed_factor("rcosc400M",  "rcosc16M", 25, 1));
+	       imx_clk_fixed_factor(dev, "rcosc400M",  "rcosc16M", 25, 1));
 	clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
-	       imx_clk_fixed_factor("rcosc48M_div2",  "rcosc48M", 1, 2));
+	       imx_clk_fixed_factor(dev, "rcosc48M_div2",  "rcosc48M", 1, 2));
 
 	clk_dm(IMXRT1170_CLK_PLL_ARM,
-	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc",
 			     base + 0x200, 0xff));
 	clk_dm(IMXRT1170_CLK_PLL3,
-	       imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
 			     base + 0x210, 1));
 	clk_dm(IMXRT1170_CLK_PLL2,
-	       imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
 			     base + 0x240, 1));
 
 	clk_dm(IMXRT1170_CLK_PLL3_PFD0,
@@ -149,7 +149,7 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	       imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3));
 
 	clk_dm(IMXRT1170_CLK_PLL3_DIV2,
-	       imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2));
+	       imx_clk_fixed_factor(dev, "pll3_div2", "pll3_sys", 1, 2));
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
@@ -157,31 +157,31 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1170_CLK_LPUART1_SEL,
-	       imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3,
 			   lpuart1_sels, ARRAY_SIZE(lpuart1_sels)));
 	clk_dm(IMXRT1170_CLK_LPUART1,
-	       imx_clk_divider("lpuart1", "lpuart1_sel",
+	       imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
 			       base + (25 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
 			   usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
 	clk_dm(IMXRT1170_CLK_USDHC1,
-	       imx_clk_divider("usdhc1", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1", "usdhc1_sel",
 			       base + (58 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_GPT1_SEL,
-	       imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3,
 			   gpt1_sels, ARRAY_SIZE(gpt1_sels)));
 	clk_dm(IMXRT1170_CLK_GPT1,
-	       imx_clk_divider("gpt1", "gpt1_sel",
+	       imx_clk_divider(dev, "gpt1", "gpt1_sel",
 			       base + (14 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 	clk_dm(IMXRT1170_CLK_SEMC,
-	       imx_clk_divider("semc", "semc_sel",
+	       imx_clk_divider(dev, "semc", "semc_sel",
 			       base + (4 * 0x80), 0, 8));
 	struct clk *clk, *clk1;
 
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index c6692f2f9f5..85b6a9809e8 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -281,9 +281,9 @@ static const struct clk_ops clk_pllv3_enet_ops = {
 	.get_rate	= clk_pllv3_enet_get_rate,
 };
 
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-			  const char *parent_name, void __iomem *base,
-			  u32 div_mask)
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+			  const char *name, const char *parent_name,
+			  void __iomem *base, u32 div_mask)
 {
 	struct clk_pllv3 *pll;
 	struct clk *clk;
@@ -339,7 +339,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 	pll->div_mask = div_mask;
 	clk = &pll->clk;
 
-	ret = clk_register(clk, drv_name, name, parent_name);
+	ret = clk_register(clk, drv_name, name,
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(pll);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 27a53ae5583..7d14dbc395f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -78,84 +78,89 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 			    void __iomem *base,
 			    const struct imx_pll14xx_clk *pll_clk);
 
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate_flags, unsigned int *share_count);
 
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-			  const char *parent_name, void __iomem *base,
-			  u32 div_mask);
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+			  const char *name, const char *parent_name,
+			  void __iomem *base, u32 div_mask);
 
-static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
-					void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name,
+					const char *parent, void __iomem *reg,
+					u8 shift)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 			shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate2_shared(const char *name,
+static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name,
 					       const char *parent,
 					       void __iomem *reg, u8 shift,
 					       unsigned int *share_count)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 				  shift, 0x3, 0, share_count);
 }
 
-static inline struct clk *imx_clk_gate2_shared2(const char *name,
+static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char *name,
 						const char *parent,
 						void __iomem *reg, u8 shift,
 						unsigned int *share_count)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT |
 				  CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
 				  share_count);
 }
 
-static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_register_gate2(NULL, name, parent,
+	return clk_register_gate2(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate4_flags(const char *name,
+static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *name,
 		const char *parent, void __iomem *reg, u8 shift,
 		unsigned long flags)
 {
-	return clk_register_gate2(NULL, name, parent,
+	return clk_register_gate2(dev, name, parent,
 			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_fixed_factor(const char *name,
-		const char *parent, unsigned int mult, unsigned int div)
+static inline struct clk *
+imx_clk_fixed_factor(struct udevice *dev, const char *name, const char *parent,
+		     unsigned int mult, unsigned int div)
 {
-	return clk_register_fixed_factor(NULL, name, parent,
+	return clk_register_fixed_factor(dev, name, parent,
 			CLK_SET_RATE_PARENT, mult, div);
 }
 
-static inline struct clk *imx_clk_divider(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider(struct udevice *dev, const char *name,
+					  const char *parent, void __iomem *reg,
+					  u8 shift, u8 width)
 {
-	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+	return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
 			reg, shift, width, 0);
 }
 
 static inline struct clk *
-imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
-		     u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
+imx_clk_busy_divider(struct udevice *dev, const char *name,
+		     const char *parent, void __iomem *reg, u8 shift, u8 width,
+		     void __iomem *busy_reg, u8 busy_shift)
 {
-	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+	return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider2(struct udevice *dev, const char *name,
+					   const char *parent, void __iomem *reg,
+					   u8 shift, u8 width)
 {
-	return clk_register_divider(NULL, name, parent,
+	return clk_register_divider(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
@@ -167,90 +172,93 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
 			      u8 shift, u8 width, const char * const *parents,
 			      int num_parents, void (*fixup)(u32 *val));
 
-static inline struct clk *imx_clk_mux_flags(const char *name,
+static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *name,
 			void __iomem *reg, u8 shift, u8 width,
 			const char * const *parents, int num_parents,
 			unsigned long flags)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 				flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
 				width, 0);
 }
 
-static inline struct clk *imx_clk_mux2_flags(const char *name,
+static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		const char * const *parents,
 		int num_parents, unsigned long flags)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
-			u8 shift, u8 width, const char * const *parents,
+static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name,
+			void __iomem *reg, u8 shift, u8 width, const char * const *parents,
 			int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0);
 }
 
 static inline struct clk *
-imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
+imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width,
 		 void __iomem *busy_reg, u8 busy_shift,
 		 const char * const *parents, int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0);
 }
 
-static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, void __iomem *reg,
 			u8 shift, u8 width, const char * const *parents,
 			int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_gate(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name,
+				       const char *parent, void __iomem *reg,
+				       u8 shift)
 {
-	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 			shift, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, unsigned long flags)
+static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *name,
+					     const char *parent, void __iomem *reg,
+					     u8 shift, unsigned long flags)
 {
-	return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 			shift, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name,
+					const char *parent, void __iomem *reg,
+					u8 shift)
 {
-	return clk_register_gate(NULL, name, parent,
+	return clk_register_gate(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0, NULL);
 }
 
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
 		const char * const *parent_names,
 		int num_parents, void __iomem *reg, unsigned long flags);
 
-#define __imx8m_clk_composite(name, parent_names, reg, flags) \
-	imx8m_clk_composite_flags(name, parent_names, \
+#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \
+	imx8m_clk_composite_flags(dev, name, parent_names, \
 		ARRAY_SIZE(parent_names), reg, \
 		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 
-#define imx8m_clk_composite(name, parent_names, reg) \
-	__imx8m_clk_composite(name, parent_names, reg, 0)
+#define imx8m_clk_composite(dev, name, parent_names, reg) \
+	__imx8m_clk_composite(dev, name, parent_names, reg, 0)
 
-#define imx8m_clk_composite_critical(name, parent_names, reg) \
-	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \
+	__imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL)
 
 struct clk *imx93_clk_composite_flags(const char *name,
 				      const char * const *parent_names,
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cb867acc48c..3ea01f3c969 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
 	  on the Snapdragon IPQ4019 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon IPQ9574 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 config CLK_QCOM_QCM2290
 	bool "Qualcomm QCM2290 GCC"
 	select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1bc0f15005b..e13fc8c1071 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
 obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
 obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
 obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
 obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index b5def55dbc2..6a53f900a9e 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -54,8 +54,9 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 };
 
 static const struct gate_clk apq8016_clks[] = {
-	GATE_CLK(GCC_USB_HS_AHB_CLK,    0x41008, 0x00000001),
-	GATE_CLK(GCC_USB_HS_SYSTEM_CLK,	0x41004, 0x00000001),
+	GATE_CLK(GCC_PRNG_AHB_CLK,	0x45004, BIT(8)),
+	GATE_CLK(GCC_USB_HS_AHB_CLK,    0x41008, BIT(0)),
+	GATE_CLK(GCC_USB_HS_SYSTEM_CLK,	0x41004, BIT(0)),
 };
 
 /* SDHCI */
@@ -139,15 +140,14 @@ static int apq8016_clk_enable(struct clk *clk)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (priv->data->num_clks < clk->id) {
+	if (priv->data->num_clks < clk->id || !apq8016_clks[clk->id].reg) {
 		log_warning("%s: unknown clk id %lu\n", __func__, clk->id);
 		return 0;
 	}
 
-	debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
-	qcom_gate_clk_en(priv, clk->id);
+	debug("%s: enabling clock %s\n", __func__, apq8016_clks[clk->id].name);
 
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static struct msm_clk_data apq8016_clk_data = {
diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
new file mode 100644
index 00000000000..b0af4036059
--- /dev/null
+++ b/drivers/clk/qcom/clock-ipq9574.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+#include "clock-qcom.h"
+
+#define GCC_BLSP1_AHB_CBCR			0x1004
+#define GCC_BLSP1_UART3_APPS_CMD_RCGR		0x402C
+#define GCC_BLSP1_UART3_APPS_CBCR		0x4054
+
+#define GCC_SDCC1_APPS_CBCR			0x3302C
+#define GCC_SDCC1_AHB_CBCR			0x33034
+#define GCC_SDCC1_APPS_CMD_RCGR			0x33004
+#define GCC_SDCC1_ICE_CORE_CBCR			0x33030
+
+static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_BLSP1_UART3_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
+				     0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
+		return rate;
+	case GCC_SDCC1_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
+				     11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
+		return rate;
+	default:
+		return -EINVAL;
+	}
+}
+
+static const struct gate_clk ipq9574_clks[] = {
+	GATE_CLK(GCC_BLSP1_UART3_APPS_CLK,	 0x4054, 0x00000001),
+	GATE_CLK(GCC_BLSP1_AHB_CLK,		 0x1004, 0x00000001),
+	GATE_CLK(GCC_SDCC1_AHB_CLK,		0x33034, 0x00000001),
+	GATE_CLK(GCC_SDCC1_APPS_CLK,		0x3302C, 0x00000001),
+	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK,	0x33030, 0x00000001),
+};
+
+static int ipq9574_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name);
+
+	if (!ipq9574_clks[clk->id].reg)
+		return -EINVAL;
+
+	qcom_gate_clk_en(priv, clk->id);
+
+	return 0;
+}
+
+static const struct qcom_reset_map ipq9574_gcc_resets[] = {
+	[GCC_SDCC_BCR] = { 0x33000 },
+};
+
+static struct msm_clk_data ipq9574_gcc_data = {
+	.resets = ipq9574_gcc_resets,
+	.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
+	.enable = ipq9574_enable,
+	.set_rate = ipq9574_set_rate,
+};
+
+static const struct udevice_id gcc_ipq9574_of_match[] = {
+	{
+		.compatible = "qcom,ipq9574-gcc",
+		.data = (ulong)&ipq9574_gcc_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(gcc_ipq9574) = {
+	.name		= "gcc_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= gcc_ipq9574_of_match,
+	.bind		= qcom_cc_bind,
+	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index c78705cb8cf..1326b770c3e 100644
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -134,9 +134,7 @@ static int qcm2290_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map qcm2290_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index ff336dea39c..f43edea2525 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -7,10 +7,12 @@
 
 #include <asm/io.h>
 #include <linux/bitfield.h>
+#include <errno.h>
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
+#define CFG_CLK_SRC_GPLL2 (2 << 8)
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
@@ -105,14 +107,19 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
 		      int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
-static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
 {
 	u32 val;
-	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
-		return;
+	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+		log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+			priv->base, id);
+		return -ENOENT;
+	}
 
 	val = readl(priv->base + priv->data->clks[id].reg);
 	writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+
+	return 0;
 }
 
 #endif
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index e31f24ed4f0..527cecf5c82 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -73,9 +73,7 @@ static int sa8775p_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sa8775p_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 5d343f12051..8691f08109b 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -16,29 +16,64 @@
 
 #include "clock-qcom.h"
 
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
+#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
+#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
+#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
+#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
+	F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
+	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+	{ }
+};
 
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
 
 	switch (clk->id) {
-	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
-		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
-		clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
-		return rate;
 	case GCC_USB30_PRIM_MASTER_CLK:
-		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
-				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
-		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
-		return rate;
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB30_SEC_MASTER_CLK:
+		freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_SEC_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_PCIE1_PHY_RCHNG_CLK:
+		clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
+		return 100000000;
 	default:
-		return 0;
+		return rate;
 	}
 }
 
@@ -50,13 +85,35 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
+	GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
+	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
+	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
+	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
+	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
+	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
+	GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
+	GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
+	GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
+	GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
+	GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
+	GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
+	GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
 };
 
 static int sc7280_enable(struct clk *clk)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (priv->data->num_clks < clk->id) {
+	if (priv->data->num_clks <= clk->id) {
 		debug("%s: unknown clk id %lu\n", __func__, clk->id);
 		return 0;
 	}
@@ -71,11 +128,32 @@ static int sc7280_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
+	case GCC_AGGRE_USB3_SEC_AXI_CLK:
+		qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
+		fallthrough;
+	case GCC_USB30_SEC_MASTER_CLK:
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+		break;
+	case GCC_PCIE_1_PIPE_CLK:
+		clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
+		break;
+	case GCC_PCIE_1_AUX_CLK:
+		clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
+				     CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S0_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S1_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S3_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sc7280_gcc_resets[] = {
@@ -100,6 +178,20 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = {
 static const struct qcom_power_map sc7280_gdscs[] = {
 	[GCC_UFS_PHY_GDSC] = { 0x77004 },
 	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
+	[GCC_USB30_SEC_GDSC] = { 0x9e004 },
+	[GCC_PCIE_1_GDSC] = { 0x8d004 },
+};
+
+static const phys_addr_t sc7280_rcg_addrs[] = {
+	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
+	0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
+	0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
+};
+
+static const char *const sc7280_rcg_names[] = {
+	"USB30_PRIM_MASTER_CLK_SRC",
+	"USB30_PRIM_MOCK_UTMI_CLK_SRC",
+	"GCC_PCIE_1_AUX_CLK_SRC",
 };
 
 static struct msm_clk_data qcs404_gcc_data = {
@@ -113,6 +205,10 @@ static struct msm_clk_data qcs404_gcc_data = {
 
 	.enable = sc7280_enable,
 	.set_rate = sc7280_set_rate,
+
+	.dbg_rcg_addrs = sc7280_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
+	.dbg_rcg_names = sc7280_rcg_names,
 };
 
 static const struct udevice_id gcc_sc7280_of_match[] = {
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index adffb0cb240..6a0bf16ba2d 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -162,9 +162,7 @@ static int sdm845_clk_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sdm845_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
index 9057dfe0bb1..17c2e561758 100644
--- a/drivers/clk/qcom/clock-sm6115.c
+++ b/drivers/clk/qcom/clock-sm6115.c
@@ -146,9 +146,7 @@ static int sm6115_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm6115_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
index 88f2e678f43..7dd0d56eb43 100644
--- a/drivers/clk/qcom/clock-sm8150.c
+++ b/drivers/clk/qcom/clock-sm8150.c
@@ -243,9 +243,7 @@ static int sm8150_clk_enable(struct clk *clk)
 		break;
 	};
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8150_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
index e322a923a5c..26396847d85 100644
--- a/drivers/clk/qcom/clock-sm8250.c
+++ b/drivers/clk/qcom/clock-sm8250.c
@@ -195,9 +195,7 @@ static int sm8250_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8250_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
index 62b5a409e8e..7c06489b9c4 100644
--- a/drivers/clk/qcom/clock-sm8550.c
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -220,9 +220,7 @@ static int sm8550_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8550_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
index 9baaecb571f..364454644a6 100644
--- a/drivers/clk/qcom/clock-sm8650.c
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -217,9 +217,7 @@ static int sm8650_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8650_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
index bd9c6ed1c8a..542d6248d65 100644
--- a/drivers/clk/qcom/clock-x1e80100.c
+++ b/drivers/clk/qcom/clock-x1e80100.c
@@ -174,9 +174,7 @@ static int x1e80100_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map x1e80100_gcc_resets[] = {
diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h
index 95b82e968d0..a9e83d0d689 100644
--- a/drivers/clk/sophgo/clk-common.h
+++ b/drivers/clk/sophgo/clk-common.h
@@ -45,12 +45,14 @@ static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit)
 
 static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit)
 {
-	return setbits_le32(base + bit->offset, BIT(bit->shift));
+	setbits_le32(base + bit->offset, BIT(bit->shift));
+	return 0;
 }
 
 static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit)
 {
-	return clrbits_le32(base + bit->offset, BIT(bit->shift));
+	clrbits_le32(base + bit->offset, BIT(bit->shift));
+	return 0;
 }
 
 static inline u32 cv1800b_clk_getfield(void *base,
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 8bdc0944896..f44db76c182 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -122,4 +122,11 @@ config CLK_SUN50I_A64
 	  This enables common clock driver support for platforms based
 	  on Allwinner A64 SoC.
 
+config CLK_SUN50I_A100
+	bool "Clock driver for Allwinner A100/A133"
+	default MACH_SUN50I_A133
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A100/A133 SoCs.
+
 endif # CLK_SUNXI
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 90a277489dc..7ff71c756e0 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
+obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
diff --git a/drivers/clk/sunxi/clk_a100.c b/drivers/clk/sunxi/clk_a100.c
new file mode 100644
index 00000000000..b641feb8612
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a100.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2024 Arm Ltd.
+ */
+
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-a100-ccu.h>
+#include <dt-bindings/reset/sun50i-a100-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a100_gates[] = {
+	[CLK_PLL_PERIPH0]	= GATE(0x020, BIT(31) | BIT(27)),
+
+	[CLK_APB1]		= GATE_DUMMY,
+
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
+
+	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
+
+	[CLK_SPI0]		= GATE(0x940, BIT(31)),
+	[CLK_SPI1]		= GATE(0x944, BIT(31)),
+	[CLK_SPI2]		= GATE(0x948, BIT(31)),
+
+	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
+	[CLK_BUS_SPI2]		= GATE(0x96c, BIT(2)),
+
+	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
+
+	[CLK_USB_PHY0]		= GATE(0xa70, BIT(29)),
+	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
+
+	[CLK_USB_PHY1]		= GATE(0xa74, BIT(29)),
+	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
+
+	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
+	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
+	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
+	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
+	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_TCON_LCD]		= GATE(0xb60, BIT(31)),
+	[CLK_BUS_TCON_LCD]	= GATE(0xb7c, BIT(0)),
+};
+
+static struct ccu_reset a100_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
+
+	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
+	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
+	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
+
+	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
+	[RST_BUS_SPI2]		= RESET(0x96c, BIT(18)),
+
+	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
+
+	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
+
+	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
+
+	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
+	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
+	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
+	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_TCON_LCD]	= RESET(0xb7c, BIT(16)),
+};
+
+const struct ccu_desc a100_ccu_desc = {
+	.gates = a100_gates,
+	.resets = a100_resets,
+	.num_gates = ARRAY_SIZE(a100_gates),
+	.num_resets = ARRAY_SIZE(a100_resets),
+};
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 2ef4f45dacf..e0765cbc6dc 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -122,6 +122,7 @@ extern const struct ccu_desc f1c100s_ccu_desc;
 extern const struct ccu_desc h3_ccu_desc;
 extern const struct ccu_desc h6_ccu_desc;
 extern const struct ccu_desc h616_ccu_desc;
+extern const struct ccu_desc a100_ccu_desc;
 extern const struct ccu_desc h6_r_ccu_desc;
 extern const struct ccu_desc r40_ccu_desc;
 extern const struct ccu_desc v3s_ccu_desc;
@@ -215,6 +216,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
 	{ .compatible = "allwinner,sun50i-h616-r-ccu",
 	  .data = (ulong)&h6_r_ccu_desc },
 #endif
+#ifdef CONFIG_CLK_SUN50I_A100
+	{ .compatible = "allwinner,sun50i-a100-ccu",
+	  .data = (ulong)&a100_ccu_desc },
+#endif
 #ifdef CONFIG_CLK_SUNIV_F1C100S
 	{ .compatible = "allwinner,suniv-f1c100s-ccu",
 	  .data = (ulong)&f1c100s_ccu_desc },
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index bf65f573cb8..b38e559e45a 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -82,6 +82,8 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
 		.family = "J721E",
 		.data = &j721e_clk_platdata,
 	},
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J7200)
 	{
 		.family = "J7200",
 		.data = &j7200_clk_platdata,
@@ -104,6 +106,10 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
 		.family = "J784S4",
 		.data = &j784s4_clk_platdata,
 	},
+	{
+		.family = "J742S2",
+		.data = &j784s4_clk_platdata,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 53d31b3c0bf..4e1eccaa5b0 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -35,11 +35,49 @@ static const char *get_imx_type_str(u32 imxtype)
 {
 	switch (imxtype) {
 	case MXC_CPU_IMX8MM:
-		return "8MM";
+		return "8MMQ";	/* Quad-core version of the imx8mm */
+	case MXC_CPU_IMX8MML:
+		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMD:
+		return "8MMD";	/* Dual-core version of the imx8mm */
+	case MXC_CPU_IMX8MMDL:
+		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMS:
+		return "8MMS";	/* Single-core version of the imx8mm */
+	case MXC_CPU_IMX8MMSL:
+		return "8MMSL";	/* Single-core Lite version of the imx8mm */
 	case MXC_CPU_IMX8MN:
-		return "8MN";
+		return "8MNano Quad"; /* Quad-core version */
+	case MXC_CPU_IMX8MND:
+		return "8MNano Dual"; /* Dual-core version */
+	case MXC_CPU_IMX8MNS:
+		return "8MNano Solo"; /* Single-core version */
+	case MXC_CPU_IMX8MNL:
+		return "8MNano QuadLite"; /* Quad-core Lite version */
+	case MXC_CPU_IMX8MNDL:
+		return "8MNano DualLite"; /* Dual-core Lite version */
+	case MXC_CPU_IMX8MNSL:
+		return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
+	case MXC_CPU_IMX8MNUQ:
+		return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
+	case MXC_CPU_IMX8MNUD:
+		return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
+	case MXC_CPU_IMX8MNUS:
+		return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
 	case MXC_CPU_IMX8MP:
-		return "8MP";
+		return "8MP[8]";	/* Quad-core version of the imx8mp */
+	case MXC_CPU_IMX8MPD:
+		return "8MP Dual[3]";	/* Dual-core version of the imx8mp */
+	case MXC_CPU_IMX8MPL:
+		return "8MP Lite[4]";	/* Quad-core Lite version of the imx8mp */
+	case MXC_CPU_IMX8MP6:
+		return "8MP[6]";	/* Quad-core version of the imx8mp, NPU fused */
+	case MXC_CPU_IMX8MQ:
+		return "8MQ";	/* Quad-core version of the imx8mq */
+	case MXC_CPU_IMX8MQL:
+		return "8MQLite";	/* Quad-core Lite version of the imx8mq */
+	case MXC_CPU_IMX8MD:
+		return "8MD";	/* Dual-core version of the imx8mq */
 	case MXC_CPU_IMX8QXP:
 	case MXC_CPU_IMX8QXP_A0:
 		return "8QXP";
@@ -177,19 +215,19 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 	ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
 		       plat->type, plat->rev, plat->name, plat->freq_mhz);
 
-	if (IS_ENABLED(CONFIG_IMX9)) {
+	if (IS_ENABLED(CONFIG_IMX_TMU)) {
 		switch (get_cpu_temp_grade(&minc, &maxc)) {
 		case TEMP_AUTOMOTIVE:
-			grade = "Automotive temperature grade ";
+			grade = "Automotive temperature grade";
 			break;
 		case TEMP_INDUSTRIAL:
-			grade = "Industrial temperature grade ";
+			grade = "Industrial temperature grade";
 			break;
 		case TEMP_EXTCOMMERCIAL:
-			grade = "Extended Consumer temperature grade ";
+			grade = "Extended Consumer temperature grade";
 			break;
 		default:
-			grade = "Consumer temperature grade ";
+			grade = "Consumer temperature grade";
 			break;
 		}
 
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 94ec13ba7ca..90c20a6a3fa 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
 k3-psil-data-y += k3-psil.o
 k3-psil-data-$(CONFIG_SOC_K3_AM654) += k3-psil-am654.o
 k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_J7200) += k3-psil-j721e.o
 k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
 k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
 k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index 369e679886f..39798844a8a 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
 			soc_ep_map = &am654_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
 			soc_ep_map = &j721e_ep_map;
+		else if (IS_ENABLED(CONFIG_SOC_K3_J7200))
+			soc_ep_map = &j721e_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721S2))
 			soc_ep_map = &j721s2_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 3370f80231d..2e61e0c7de1 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
 
 #if IS_ENABLED(CONFIG_K3_DM_FW)
 
-#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+#if IS_ENABLED(CONFIG_SOC_K3_J721E) || IS_ENABLED(CONFIG_SOC_K3_J7200)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 713d93a200c..851aa737c03 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -270,5 +270,4 @@ U_BOOT_DRIVER(zynqmp_ipi) = {
 	.id = UCLASS_NOP,
 	.of_match = zynqmp_ipi_ids,
 	.probe = zynqmp_ipi_probe,
-	.flags = DM_FLAG_PROBE_AFTER_BIND,
 };
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index da84b35e804..834e0285097 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -468,6 +468,13 @@ config STM32MP_FUSE
 	  for STM32MP architecture.
 	  This API is needed for CMD_FUSE.
 
+config K3_FUSE
+	bool "Enable TI K3 fuse wrapper providing the fuse API"
+	depends on MISC && CMD_FUSE && CMD_FUSE_WRITEBUFF
+	help
+	  If you say Y here, you will get support for the fuse API (OTP)
+	  for TI K3 architecture.
+
 config STM32_RCC
 	bool "Enable RCC driver for the STM32 SoC's family"
 	depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dac805e4cdd..0b81ba2604f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_$(XPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
 obj-$(CONFIG_IMX_ELE) += imx_ele/
+obj-$(CONFIG_K3_FUSE) += k3_fuse.o
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/k3_fuse.c b/drivers/misc/k3_fuse.c
new file mode 100644
index 00000000000..4a8ff1f2523
--- /dev/null
+++ b/drivers/misc/k3_fuse.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <fuse.h>
+#include <linux/arm-smccc.h>
+#include <string.h>
+
+#define K3_SIP_OTP_WRITEBUFF 0xC2000000
+#define K3_SIP_OTP_WRITE 0xC2000001
+#define K3_SIP_OTP_READ 0xC2000002
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct arm_smccc_res res;
+
+	if (bank != 0U) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	/* Make SiP SMC call and send the word in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_READ, word,
+		      0, 0, 0, 0, 0, 0, &res);
+
+	*val = res.a1;
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	return -EPERM;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct arm_smccc_res res;
+	u32 mask = val;
+
+	if (bank != 0U) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	/* Make SiP SMC call and send the word, val and mask in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_WRITE, word,
+		      val, mask, 0, 0, 0, 0, &res);
+
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	return -EPERM;
+}
+
+int fuse_writebuff(ulong addr)
+{
+	struct arm_smccc_res res;
+
+	/* Make SiP SMC call and send the addr in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_WRITEBUFF, (unsigned long)addr,
+		      0, 0, 0, 0, 0, 0, &res);
+
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
diff --git a/drivers/misc/qfw_acpi.c b/drivers/misc/qfw_acpi.c
index 0d0cf764689..c6c052ac6c3 100644
--- a/drivers/misc/qfw_acpi.c
+++ b/drivers/misc/qfw_acpi.c
@@ -25,17 +25,18 @@ DECLARE_GLOBAL_DATA_PTR;
  *
  * @entry : BIOS linker command entry which tells where to allocate memory
  *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
+ * @addr  : The address that should be used for low memory allocation. If the
  *          memory allocation request is 'ZONE_HIGH' then this parameter will
  *          be ignored.
  * @return: 0 on success, or negative value on failure
  */
-static int bios_linker_allocate(struct udevice *dev,
+static int bios_linker_allocate(struct acpi_ctx *ctx, struct udevice *dev,
 				struct bios_linker_entry *entry, ulong *addr)
 {
 	uint32_t size, align;
 	struct fw_file *file;
 	unsigned long aligned_addr;
+	struct acpi_rsdp *rsdp;
 
 	align = le32_to_cpu(entry->alloc.align);
 	/* align must be power of 2 */
@@ -58,7 +59,9 @@ static int bios_linker_allocate(struct udevice *dev,
 	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
 	 * in which is low memory
 	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+		aligned_addr = ALIGN(*addr, align);
+	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
 		aligned_addr = (unsigned long)memalign(align, size);
 		if (!aligned_addr) {
 			printf("error: allocating resource\n");
@@ -83,8 +86,13 @@ static int bios_linker_allocate(struct udevice *dev,
 		       (void *)aligned_addr);
 	file->addr = aligned_addr;
 
+	rsdp = (void *)aligned_addr;
+	if (!strncmp(rsdp->signature, RSDP_SIG, sizeof(rsdp->signature)))
+		ctx->rsdp = rsdp;
+
 	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) ||
+	    entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
 		*addr = (aligned_addr + size);
 
 	return 0;
@@ -209,19 +217,23 @@ ulong write_acpi_tables(ulong addr)
 	qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
 
 	for (i = 0; i < (size / sizeof(*entry)); i++) {
+		log_content("entry %d: addr %lx\n", i, addr);
 		entry = table_loader + i;
 		switch (le32_to_cpu(entry->command)) {
 		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(dev, entry, &addr);
+			log_content("   - %s\n", entry->alloc.file);
+			ret = bios_linker_allocate(ctx, dev, entry, &addr);
 			if (ret)
 				goto out;
 			break;
 		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+			log_content("   - %s\n", entry->pointer.src_file);
 			ret = bios_linker_add_pointer(dev, entry);
 			if (ret)
 				goto out;
 			break;
 		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+			log_content("   - %s\n", entry->cksum.file);
 			ret = bios_linker_add_checksum(dev, entry);
 			if (ret)
 				goto out;
@@ -246,6 +258,16 @@ out:
 
 	free(table_loader);
 
+	if (!ctx->rsdp) {
+		printf("error: no RSDP found\n");
+		return addr;
+	}
+	struct acpi_rsdp *rsdp = ctx->rsdp;
+
+	rsdp->length = sizeof(*rsdp);
+	rsdp->xsdt_address = 0;
+	rsdp->ext_checksum = table_compute_checksum((u8 *)rsdp, sizeof(*rsdp));
+
 	gd_set_acpi_start(acpi_get_rsdp_addr());
 
 	return addr;
@@ -305,7 +327,7 @@ static int evt_write_acpi_tables(void)
 	/* Generate ACPI tables */
 	end = write_acpi_tables(addr);
 	gd->arch.table_start = addr;
-	gd->arch.table_end = addr;
+	gd->arch.table_end = end;
 
 	return 0;
 }
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 27bb7052fca..ac77fb06bf7 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -10,6 +10,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <malloc.h>
+#include <reset.h>
 #include <sdhci.h>
 #include <wait_bit.h>
 #include <asm/global_data.h>
@@ -153,9 +154,18 @@ static int msm_sdc_probe(struct udevice *dev)
 	const struct msm_sdhc_variant_info *var_info;
 	struct sdhci_host *host = &prv->host;
 	u32 core_version, core_minor, core_major;
+	struct reset_ctl bcr_rst;
 	u32 caps;
 	int ret;
 
+	ret = reset_get_by_index(dev, 0, &bcr_rst);
+	if (!ret) {
+		reset_assert(&bcr_rst);
+		udelay(200);
+		reset_deassert(&bcr_rst);
+		udelay(200);
+	}
+
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
 
 	host->max_clk = 0;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0b56d1405be..951e6acd34d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -92,6 +92,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 		pll = CCM_MMC_CTRL_PLL6;
 		pll_hz = clock_get_pll6();
 #endif
+		/*
+		 * On the D1/R528/T113 mux source 1 refers to PLL_PERIPH0(1x),
+		 * like for the older SoCs. However we still have the hidden
+		 * divider of 2x, so compensate for that here.
+		 */
+		if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+			pll_hz /= 2;
 	}
 
 	div = pll_hz / hz;
@@ -442,6 +449,26 @@ out:
 	return error;
 }
 
+static void sunxi_mmc_reset(void *regs)
+{
+	/* Reset controller */
+	writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
+	udelay(1000);
+
+	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+		/* Reset card */
+		writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
+		udelay(10);
+		writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
+		udelay(300);
+
+		/* Setup FIFO R/W threshold. Needed on H616. */
+		writel(SUNXI_MMC_THLDC_READ_THLD(512) |
+		       SUNXI_MMC_THLDC_WRITE_EN |
+		       SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
+	}
+}
+
 /* non-DM code here is used by the (ARM) SPL only */
 
 #if !CONFIG_IS_ENABLED(DM_MMC)
@@ -489,9 +516,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
 {
 	struct sunxi_mmc_priv *priv = mmc->priv;
 
-	/* Reset controller */
-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
-	udelay(1000);
+	sunxi_mmc_reset(priv->reg);
 
 	return 0;
 }
@@ -684,9 +709,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 
 	upriv->mmc = &plat->mmc;
 
-	/* Reset controller */
-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
-	udelay(1000);
+	sunxi_mmc_reset(priv->reg);
 
 	return 0;
 }
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index f4ae5a790c8..71865160319 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -37,7 +37,9 @@ struct sunxi_mmc {
 	u32 res0;		/* 0x54 reserved */
 	u32 a12a;		/* 0x58 Auto command 12 argument */
 	u32 ntsr;		/* 0x5c	New timing set register */
-	u32 res1[8];
+	u32 res1[6];
+	u32 hwrst;		/* 0x78 Hardware Reset */
+	u32 res5;
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
@@ -46,7 +48,8 @@ struct sunxi_mmc {
 	u32 cbda;		/* 0x94 */
 	u32 res2[26];
 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
-	u32 res3[17];
+	u32 thldc;		/* 0x100 Threshold control */
+	u32 res3[16];
 	u32 samp_dl;
 	u32 res4[46];
 #endif
@@ -57,6 +60,7 @@ struct sunxi_mmc {
 #define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
 #define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
 
+#define SUNXI_MMC_GCTRL		0x000
 #define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
 #define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
 #define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
@@ -123,6 +127,10 @@ struct sunxi_mmc {
 
 #define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
 
+#define SUNXI_MMC_HWRST		0x078
+#define SUNXI_MMC_HWRST_ASSERT		(0x0 << 0)
+#define SUNXI_MMC_HWRST_DEASSERT	(0x1 << 0)
+
 #define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
 #define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
 #define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
@@ -133,6 +141,12 @@ struct sunxi_mmc {
 #define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
 
+#define SUNXI_MMC_THLDC		0x100
+#define SUNXI_MMC_THLDC_READ_EN		(0x1 << 0)
+#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN	(0x1 << 1)
+#define SUNXI_MMC_THLDC_WRITE_EN	(0x1 << 2)
+#define SUNXI_MMC_THLDC_READ_THLD(x)	(((x) & 0xfff) << 16)
+
 #define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
 
 #endif /* _SUNXI_MMC_H */
diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig
index f15ee4f833f..2b95eb02177 100644
--- a/drivers/mux/Kconfig
+++ b/drivers/mux/Kconfig
@@ -10,6 +10,16 @@ config MULTIPLEXER
 
 if MULTIPLEXER
 
+config SPL_MUX_MMIO
+	bool "MMIO register bitfield-controlled Multiplexer"
+        depends on MULTIPLEXER && SYSCON
+        help
+          MMIO register bitfield-controlled Multiplexer controller.
+
+          The driver builds multiplexer controllers for bitfields in a syscon
+          register. For N bit wide bitfields, there will be 2^N possible
+          multiplexer states.
+
 config MUX_MMIO
 	bool "MMIO register bitfield-controlled Multiplexer"
 	depends on MULTIPLEXER && SYSCON
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index c48ae6e88f3..ee8eae1efd9 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -389,10 +389,126 @@ U_BOOT_PHY_DRIVER(ksz9031) = {
 #define KSZ9131RN_DLL_ENABLE_DELAY	0
 #define KSZ9131RN_DLL_DISABLE_DELAY	BIT(12)
 
+#define KSZ9131RN_COMMON_CTRL				0
+#define KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE	BIT(4)
+
+#define KSZ9131RN_LED_ERRATA_REG	0x1e
+#define KSZ9131RN_LED_ERRATA_BIT	BIT(9)
+
+#define KSZ9131RN_CONTROL_PAD_SKEW	4
+#define KSZ9131RN_RX_DATA_PAD_SKEW	5
+#define KSZ9131RN_TX_DATA_PAD_SKEW	6
+#define KSZ9131RN_CLK_PAD_SKEW		8
+
+#define KSZ9131RN_SKEW_5BIT_MAX		2400
+#define KSZ9131RN_SKEW_4BIT_MAX		800
+#define KSZ9131RN_OFFSET		700
+#define KSZ9131RN_STEP			100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+				       ofnode of_node,
+				       u16 reg, size_t field_sz,
+				       const char *field[], u8 numfields)
+{
+	int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET),
+		      -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)};
+	int skewval, skewmax = 0;
+	int matches = 0;
+	u16 maxval;
+	u16 newval;
+	u16 mask;
+	int i;
+
+	/* psec properties in dts should mean x pico seconds */
+	if (field_sz == 5)
+		skewmax = KSZ9131RN_SKEW_5BIT_MAX;
+	else
+		skewmax = KSZ9131RN_SKEW_4BIT_MAX;
+
+	for (i = 0; i < numfields; i++)
+		if (!ofnode_read_s32(of_node, field[i], &skewval)) {
+			if (skewval < -KSZ9131RN_OFFSET)
+				skewval = -KSZ9131RN_OFFSET;
+			else if (skewval > skewmax)
+				skewval = skewmax;
+
+			val[i] = skewval + KSZ9131RN_OFFSET;
+			matches++;
+		}
+
+	if (!matches)
+		return 0;
+
+	if (matches < numfields)
+		newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg);
+	else
+		newval = 0;
+
+	maxval = (field_sz == 4) ? 0xf : 0x1f;
+	for (i = 0; i < numfields; i++)
+		if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) {
+			mask = 0xffff;
+			mask ^= maxval << (field_sz * i);
+			newval = (newval & mask) |
+				(((val[i] / KSZ9131RN_STEP) & maxval)
+					<< (field_sz * i));
+		}
+
+	return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, newval);
+}
+
+static int ksz9131_of_load_all_skew_values(struct phy_device *phydev)
+{
+	const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" };
+	const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" };
+	const char *rx_data_skews[4] = {
+		"rxd0-skew-psec", "rxd1-skew-psec",
+		"rxd2-skew-psec", "rxd3-skew-psec"
+	};
+	const char *tx_data_skews[4] = {
+		"txd0-skew-psec", "txd1-skew-psec",
+		"txd2-skew-psec", "txd3-skew-psec"
+	};
+	struct ofnode_phandle_args phandle_args;
+	int ret;
+
+	/*
+	 * Silently ignore failure here as the device tree is not required to
+	 * contain a phy node.
+	 */
+	if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args))
+		return 0;
+
+	if (!ofnode_valid(phandle_args.node))
+		return 0;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_CLK_PAD_SKEW, 5,
+					  clk_skews, 2);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_CONTROL_PAD_SKEW, 4,
+					  control_skews, 2);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_RX_DATA_PAD_SKEW, 4,
+					  rx_data_skews, 4);
+	if (ret < 0)
+		return ret;
+
+	return ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					   KSZ9131RN_TX_DATA_PAD_SKEW, 4,
+					   tx_data_skews, 4);
+}
+
 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 {
-	struct phy_driver *drv = phydev->drv;
-	u16 rxcdll_val, txcdll_val, val;
+	u16 rxcdll_val, txcdll_val;
 	int ret;
 
 	switch (phydev->interface) {
@@ -416,24 +532,37 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 		return 0;
 	}
 
-	val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			   KSZ9131RN_RXC_DLL_CTRL);
-	val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-	val |= rxcdll_val;
-	ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			    KSZ9131RN_RXC_DLL_CTRL, val);
-	if (ret)
+	ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			     KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+			     rxcdll_val);
+	if (ret < 0)
 		return ret;
 
-	val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			   KSZ9131RN_TXC_DLL_CTRL);
+	return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			      KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+			      txcdll_val);
+}
+
+/* Silicon Errata DS80000693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+	int reg;
 
-	val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-	val |= txcdll_val;
-	ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			    KSZ9131RN_TXC_DLL_CTRL, val);
+	reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			   KSZ9131RN_COMMON_CTRL);
+	if (reg < 0)
+		return reg;
 
-	return ret;
+	if (!(reg & KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE))
+		return 0;
+
+	return phy_set_bits(phydev, MDIO_DEVAD_NONE, KSZ9131RN_LED_ERRATA_REG,
+			    KSZ9131RN_LED_ERRATA_BIT);
 }
 
 static int ksz9131_config(struct phy_device *phydev)
@@ -446,6 +575,14 @@ static int ksz9131_config(struct phy_device *phydev)
 			return ret;
 	}
 
+	ret = ksz9131_of_load_all_skew_values(phydev);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_led_errata(phydev);
+	if (ret < 0)
+		return ret;
+
 	/* add an option to disable the gigabit feature of this PHY */
 	if (env_get("disable_giga")) {
 		unsigned features;
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c39bef17b79..539fd37ee59 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -592,7 +592,7 @@ static int ravb_probe(struct udevice *dev)
 
 	ret = clk_get_bulk(dev, &eth->clks);
 	if (ret < 0)
-		goto err_mdio_alloc;
+		goto err_clk_get;
 
 	mdiodev = mdio_alloc();
 	if (!mdiodev) {
@@ -614,23 +614,25 @@ static int ravb_probe(struct udevice *dev)
 	/* Bring up PHY */
 	ret = clk_enable_bulk(&eth->clks);
 	if (ret)
-		goto err_mdio_register;
+		goto err_clk_enable;
 
 	ret = ravb_reset(dev);
 	if (ret)
-		goto err_mdio_reset;
+		goto err_clk_enable;
 
 	ret = ravb_phy_config(dev);
 	if (ret)
-		goto err_mdio_reset;
+		goto err_clk_enable;
 
 	return 0;
 
-err_mdio_reset:
-	clk_release_bulk(&eth->clks);
+err_clk_enable:
+	mdio_unregister(mdiodev);
 err_mdio_register:
 	mdio_free(mdiodev);
 err_mdio_alloc:
+	clk_release_bulk(&eth->clks);
+err_clk_get:
 	unmap_physmem(eth->iobase, MAP_NOCACHE);
 	return ret;
 }
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index c70b42f6bcc..3c62fc0b428 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -661,7 +661,7 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
 
 	dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
 	if (pdata->max_speed)
-		dev_err(dev, "Port %u speed froced to %uMbit\n",
+		dev_err(dev, "Port %u speed forced to %uMbit\n",
 			priv->port_id, pdata->max_speed);
 
 	return 0;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index f940648fe58..d3fe90d939e 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -163,8 +163,8 @@ config PHY_RCAR_GEN2
 
 config PHY_RCAR_GEN3
 	tristate "Renesas R-Car Gen3 USB PHY"
-	depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR
-	default y if RCAR_GEN3
+	depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L)
+	default y if (RCAR_GEN3 || RZG2L)
 	help
 	  Support for the Renesas R-Car Gen3 USB PHY. This driver operates the
 	  PHY connected to EHCI USB module and controls USB OTG operation.
diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c
index 8c004eaf4c6..d06861c4f79 100644
--- a/drivers/phy/phy-rcar-gen3.c
+++ b/drivers/phy/phy-rcar-gen3.c
@@ -55,6 +55,7 @@
 
 /* VBCTRL */
 #define USB2_VBCTRL_DRVVBUSSEL		BIT(8)
+#define USB2_VBCTRL_VBOUT		BIT(0)
 
 /* LINECTRL1 */
 #define USB2_LINECTRL1_DPRPD_EN		BIT(19)
@@ -68,6 +69,13 @@
 #define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
 #define USB2_ADPCTRL_DRVVBUS		BIT(4)
 
+/*  RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN		BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON	BIT(0)
+
+/* Device flags */
+#define RCAR_GEN3_PHY_NO_ADPCTRL	BIT(0)
+
 struct rcar_gen3_phy {
 	fdt_addr_t	regs;
 	struct clk	clk;
@@ -122,15 +130,50 @@ static int rcar_gen3_phy_phy_power_off(struct phy *phy)
 	return regulator_set_enable(priv->vbus_supply, false);
 }
 
+static bool rcar_gen3_phy_check_id(struct phy *phy)
+{
+	const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
+	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+	ulong flags = dev_get_driver_data(phy->dev);
+	u32 val;
+
+	if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+		val = readl(priv->regs + USB2_LINECTRL1);
+		return !!(val & USB2_LINECTRL1_USB2_IDMON);
+	}
+
+	val = readl(priv->regs + USB2_ADPCTRL);
+	return (val & adpdevmask) == adpdevmask;
+}
+
+static void rcar_gen3_phy_set_vbus(struct phy *phy, bool enable)
+{
+	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+	ulong flags = dev_get_driver_data(phy->dev);
+	u32 bits = USB2_ADPCTRL_DRVVBUS;
+	u64 reg = USB2_ADPCTRL;
+
+	if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+		bits = USB2_VBCTRL_VBOUT;
+		reg = USB2_VBCTRL;
+	}
+
+	if (enable)
+		setbits_le32(priv->regs + reg, bits);
+	else
+		clrbits_le32(priv->regs + reg, bits);
+}
+
 static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 				      int submode)
 {
-	const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
 	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
-	u32 adpctrl;
+	ulong flags = dev_get_driver_data(phy->dev);
 
 	if (mode == PHY_MODE_USB_OTG) {
 		if (submode) {
+			u32 obint_enable_bits;
+
 			/* OTG submode is used as initialization indicator */
 			writel(USB2_INT_ENABLE_UCOM_INTEN |
 			       USB2_INT_ENABLE_USBH_INTB_EN |
@@ -138,13 +181,16 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 			       priv->regs + USB2_INT_ENABLE);
 			setbits_le32(priv->regs + USB2_VBCTRL,
 				     USB2_VBCTRL_DRVVBUSSEL);
-			writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG,
-			       priv->regs + USB2_OBINTSTA);
-			setbits_le32(priv->regs + USB2_OBINTEN,
-				     USB2_OBINT_SESSVLDCHG |
-				     USB2_OBINT_IDDIGCHG);
-			setbits_le32(priv->regs + USB2_ADPCTRL,
-				     USB2_ADPCTRL_IDPULLUP);
+			if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+				obint_enable_bits = USB2_OBINT_IDCHG_EN;
+			} else {
+				obint_enable_bits = USB2_OBINT_SESSVLDCHG |
+						    USB2_OBINT_IDDIGCHG;
+				setbits_le32(priv->regs + USB2_ADPCTRL,
+					     USB2_ADPCTRL_IDPULLUP);
+			}
+			writel(obint_enable_bits, priv->regs + USB2_OBINTSTA);
+			setbits_le32(priv->regs + USB2_OBINTEN, obint_enable_bits);
 			clrsetbits_le32(priv->regs + USB2_LINECTRL1,
 					USB2_LINECTRL1_DP_RPD |
 					USB2_LINECTRL1_DM_RPD |
@@ -154,8 +200,7 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 					USB2_LINECTRL1_DMRPD_EN);
 		}
 
-		adpctrl = readl(priv->regs + USB2_ADPCTRL);
-		if ((adpctrl & adpdevmask) == adpdevmask)
+		if (rcar_gen3_phy_check_id(phy))
 			mode = PHY_MODE_USB_DEVICE;
 		else
 			mode = PHY_MODE_USB_HOST;
@@ -165,13 +210,13 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 		clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
 		setbits_le32(priv->regs + USB2_LINECTRL1,
 			     USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
-		setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+		rcar_gen3_phy_set_vbus(phy, true);
 	} else if (mode == PHY_MODE_USB_DEVICE) {
 		setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
 		clrsetbits_le32(priv->regs + USB2_LINECTRL1,
 				USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD,
 				USB2_LINECTRL1_DM_RPD);
-		clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+		rcar_gen3_phy_set_vbus(phy, false);
 	} else {
 		dev_err(phy->dev, "Unknown mode %d\n", mode);
 		return -EINVAL;
@@ -226,7 +271,13 @@ static int rcar_gen3_phy_remove(struct udevice *dev)
 }
 
 static const struct udevice_id rcar_gen3_phy_of_match[] = {
-	{ .compatible = "renesas,rcar-gen3-usb2-phy", },
+	{
+		.compatible = "renesas,rcar-gen3-usb2-phy",
+	},
+	{
+		.compatible = "renesas,rzg2l-usb2-phy",
+		.data = RCAR_GEN3_PHY_NO_ADPCTRL,
+	},
 	{ },
 };
 
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 316a8fe27fd..0d8bfc53c11 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -8,9 +8,6 @@ config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
 	bool
 	default y
 
-config INTEL_PINCTRL_PADCFG_PADTOL
-	bool n
-
 config INTEL_PINCTRL_IOSTANDBY
 	bool
 	default y
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb6998551..f4a3942ee2f 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -7,84 +7,98 @@ config PINCTRL_QCOM
 menu "Qualcomm pinctrl drivers"
 
 config PINCTRL_QCOM_APQ8016
-	bool "Qualcomm APQ8016 GCC"
+	bool "Qualcomm APQ8016 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
 	  Snapdragon 410 SoC, as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_APQ8096
-	bool "Qualcomm APQ8096 GCC"
+	bool "Qualcomm APQ8096 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
 	  Snapdragon 820 SoC, as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_IPQ4019
-	bool "Qualcomm IPQ4019 GCC"
+	bool "Qualcomm IPQ4019 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the IPQ4019 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 Pinctrl"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the IPQ9574 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_QCM2290
-	bool "Qualcomm QCM2290 GCC"
+	bool "Qualcomm QCM2290 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_QCS404
-	bool "Qualcomm QCS404 GCC"
+	bool "Qualcomm QCS404 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SC7280
+	bool "Qualcomm SC7280/QCM6490 Pinctrl"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_SDM845
-	bool "Qualcomm SDM845 GCC"
+	bool "Qualcomm SDM845 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM6115
-	bool "Qualcomm SM6115 GCC"
+	bool "Qualcomm SM6115 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8150
-	bool "Qualcomm SM8150 GCC"
+	bool "Qualcomm SM8150 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8250
-	bool "Qualcomm SM8250 GCC"
+	bool "Qualcomm SM8250 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8550
-	bool "Qualcomm SM8550 GCC"
+	bool "Qualcomm SM8550 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8650
-	bool "Qualcomm SM8650 GCC"
+	bool "Qualcomm SM8650 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_X1E80100
-	bool "Qualcomm X1E80100 GCC"
+	bool "Qualcomm X1E80100 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC,
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95f93a..94cdc6e4a62 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,9 +5,11 @@
 obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
 obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
 obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 0c7437822ff..9ae07d43d93 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -50,8 +50,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
-					     unsigned int selector)
+static int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+				    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 132ece868bf..eaa927c6e22 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -43,8 +43,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
-					     unsigned int selector)
+static int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+				    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 3215c677b26..dafcd494df4 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -311,8 +311,7 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int ipq4019_get_function_mux(unsigned int pin,
-					     unsigned int selector)
+static int ipq4019_get_function_mux(unsigned int pin, unsigned int selector)
 {
 	unsigned int i;
 	const msm_pin_function *func = ipq4019_pin_functions + pin;
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 00000000000..ce09072ae3c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pinctrl driver for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq9574_functions {
+	msm_mux_blsp0_spi,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp4_i2c,
+	msm_mux_blsp4_spi,
+	msm_mux_blsp4_uart,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_uart,
+	msm_mux_gpio,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_pcie0_clk,
+	msm_mux_pcie0_wake,
+	msm_mux_pcie1_clk,
+	msm_mux_pcie1_wake,
+	msm_mux_pcie2_clk,
+	msm_mux_pcie2_wake,
+	msm_mux_pcie3_clk,
+	msm_mux_pcie3_wake,
+	msm_mux_qspi_data,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_sdc_data,
+	msm_mux_sdc_clk,
+	msm_mux_sdc_cmd,
+	msm_mux_sdc_rclk,
+	msm_mux_NA,
+};
+
+#define MSM_PIN_FUNCTION(fname)				\
+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	MSM_PIN_FUNCTION(blsp0_spi),
+	MSM_PIN_FUNCTION(blsp0_uart),
+	MSM_PIN_FUNCTION(blsp1_i2c),
+	MSM_PIN_FUNCTION(blsp1_spi),
+	MSM_PIN_FUNCTION(blsp1_uart),
+	MSM_PIN_FUNCTION(blsp2_i2c),
+	MSM_PIN_FUNCTION(blsp2_spi),
+	MSM_PIN_FUNCTION(blsp2_uart),
+	MSM_PIN_FUNCTION(blsp3_i2c),
+	MSM_PIN_FUNCTION(blsp3_spi),
+	MSM_PIN_FUNCTION(blsp3_uart),
+	MSM_PIN_FUNCTION(blsp4_i2c),
+	MSM_PIN_FUNCTION(blsp4_spi),
+	MSM_PIN_FUNCTION(blsp4_uart),
+	MSM_PIN_FUNCTION(blsp5_i2c),
+	MSM_PIN_FUNCTION(blsp5_uart),
+	MSM_PIN_FUNCTION(gpio),
+	MSM_PIN_FUNCTION(mdc),
+	MSM_PIN_FUNCTION(mdio),
+	MSM_PIN_FUNCTION(pcie0_clk),
+	MSM_PIN_FUNCTION(pcie0_wake),
+	MSM_PIN_FUNCTION(pcie1_clk),
+	MSM_PIN_FUNCTION(pcie1_wake),
+	MSM_PIN_FUNCTION(pcie2_clk),
+	MSM_PIN_FUNCTION(pcie2_wake),
+	MSM_PIN_FUNCTION(pcie3_clk),
+	MSM_PIN_FUNCTION(pcie3_wake),
+	MSM_PIN_FUNCTION(qspi_data),
+	MSM_PIN_FUNCTION(qspi_clk),
+	MSM_PIN_FUNCTION(qspi_cs),
+	MSM_PIN_FUNCTION(sdc_data),
+	MSM_PIN_FUNCTION(sdc_clk),
+	MSM_PIN_FUNCTION(sdc_cmd),
+	MSM_PIN_FUNCTION(sdc_rclk),
+};
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+	[id] = {        msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9,			\
+	}
+
+static const msm_pin_function ipq9574_pin_functions[] = {
+	PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const char *ipq9574_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *ipq9574_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+	return pin_name;
+}
+
+static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector)
+{
+	unsigned int i;
+	const msm_pin_function *func = ipq9574_pin_functions + pin;
+
+	for (i = 0; i < 10; i++)
+		if ((*func)[i] == selector)
+			return i;
+
+	debug("Can't find requested function for pin:selector %u:%u\n",
+	      pin, selector);
+
+	return -EINVAL;
+}
+
+static const struct msm_pinctrl_data ipq9574_data = {
+	.pin_data = {
+		.pin_count = 65,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = ipq9574_get_function_name,
+	.get_function_mux = ipq9574_get_function_mux,
+	.get_pin_name = ipq9574_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ipq9574) = {
+	.name		= "pinctrl_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
index af969e177d7..0c2222ce663 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
@@ -38,7 +38,7 @@ static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int select
 	return pin_name;
 }
 
-static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 26a3fba194a..24d031947a3 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -92,7 +92,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 			  unsigned int func_selector)
 {
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-	u32 func = priv->data->get_function_mux(pin_selector, func_selector);
+	int func = priv->data->get_function_mux(pin_selector, func_selector);
+
+	if (func < 0)
+		return func;
 
 	/* Always NOP for special pins, assume they're in the correct state */
 	if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 49b7bfbc001..cd167e63868 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,8 +18,7 @@ struct msm_pinctrl_data {
 	int functions_count;
 	const char *(*get_function_name)(struct udevice *dev,
 					 unsigned int selector);
-	unsigned int (*get_function_mux)(unsigned int pin,
-					 unsigned int selector);
+	int (*get_function_mux)(unsigned int pin, unsigned int selector);
 	const char *(*get_pin_name)(struct udevice *dev,
 				    unsigned int selector);
 };
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index fb6defaeddf..c272595aa2a 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -93,8 +93,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 00000000000..fe87947fbbf
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sc7280 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x00000000
+#define SOUTH 0x00400000
+#define NORTH 0x00800000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{ "qup05", 1 },
+	{ "gpio", 0 },
+	{ "pcie1_clkreqn", 3},
+};
+#define SDC_PINGROUP(pg_name, ctl, pull, drv)		\
+	{						\
+		.name = pg_name,			\
+		.ctl_reg = ctl,				\
+		.io_reg = 0,				\
+		.pull_bit = pull,			\
+		.drv_bit = drv,				\
+		.oe_bit = -1,				\
+		.in_bit = -1,				\
+		.out_bit = -1,				\
+	}
+
+#define UFS_RESET(pg_name, offset)			\
+	{						\
+		.name = pg_name,			\
+		.ctl_reg = offset,			\
+		.io_reg = offset + 0x4,			\
+		.pull_bit = 3,				\
+		.drv_bit = 0,				\
+		.oe_bit = -1,				\
+		.in_bit = -1,				\
+		.out_bit = 0,				\
+	}
+
+static const struct msm_special_pin_data sc7280_special_pins_data[] = {
+	[0] = UFS_RESET("ufs_reset", SOUTH + 0xbe000),
+	[1] = SDC_PINGROUP("sdc1_rclk", 0xb3004, 0, 6),
+	[2] = SDC_PINGROUP("sdc1_clk", 0xb3000, 13, 6),
+	[3] = SDC_PINGROUP("sdc1_cmd", 0xb3000, 11, 3),
+	[4] = SDC_PINGROUP("sdc1_data", 0xb3000, 9, 0),
+	[5] = SDC_PINGROUP("sdc2_clk", 0xb4000, 14, 6),
+	[6] = SDC_PINGROUP("sdc2_cmd", 0xb4000, 11, 3),
+	[7] = SDC_PINGROUP("sdc2_data", 0xb4000, 9, 0),
+};
+
+static const char *sc7280_get_function_name(struct udevice *dev, unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sc7280_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+	if (selector >= 175 && selector <= 182)
+		snprintf(pin_name, MAX_PIN_NAME_LEN,
+			 sc7280_special_pins_data[selector - 175].name);
+	else
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+	return pin_name;
+}
+
+static int sc7280_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sc7280_data = {
+	.pin_data = {
+		.pin_count = 183,
+		.special_pins_start = 175,
+		.special_pins_data = sc7280_special_pins_data,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sc7280_get_function_name,
+	.get_function_mux = sc7280_get_function_mux,
+	.get_pin_name = sc7280_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{
+		.compatible = "qcom,sc7280-pinctrl",
+		.data = (ulong)&sc7280_data
+	},
+	{ /* Sentinel */ } };
+
+U_BOOT_DRIVER(pinctrl_sc7280) = {
+	.name = "pinctrl_sc7280",
+	.id = UCLASS_NOP,
+	.of_match = msm_pinctrl_ids,
+	.ops = &msm_pinctrl_ops,
+	.bind = msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index f1a23f51099..3f55fc81c8e 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -80,8 +80,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sdm845_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c
index f07f39f4ac3..7e80ea39a12 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c
@@ -167,7 +167,7 @@ static const char *sm6115_get_pin_name(struct udevice *dev, unsigned int selecto
 	return pin_name;
 }
 
-static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
index 1fb2ffb9597..fe789e8639b 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -123,8 +123,8 @@ static const char *sm8150_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8150_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c
index b21cdc4d24b..d5447651695 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -99,7 +99,7 @@ static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selecto
 	return pin_name;
 }
 
-static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c
index 25b972a6d82..f7fcad0e4aa 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -68,8 +68,8 @@ static const char *sm8550_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c
index 9146d6abd9a..6b9d56b1058 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -69,8 +69,8 @@ static const char *sm8650_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
index f39dc426d68..319667bfc16 100644
--- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c
+++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
@@ -72,8 +72,8 @@ static const char *x1e80100_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
-					      unsigned int selector)
+static int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
+				     unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index cbd61795986..65e8192a99a 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,6 +124,16 @@ config PINCTRL_SUN50I_H616_R
 	default MACH_SUN50I_H616
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A100
+	bool "Support for the Allwinner A100/A133 PIO"
+	default MACH_SUN50I_A133
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+	bool "Support for the Allwinner A100/A133 R-PIO"
+	default MACH_SUN50I_A133
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN20I_D1
 	bool "Support for the Allwinner D1/R528 PIO"
 	default MACH_SUN8I_R528
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 37ea93715d1..c38edf7d4f5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -774,6 +774,41 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun50i_a100_pinctrl_functions[] = {
+	{ "emac0",	5 },	/* PH0-PH16 */
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC0-PC16 */
+	{ "spi0",	4 },	/* PC2-PC4, PC7, PC12, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB9-PB10 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_pinctrl_desc = {
+	.functions	= sun50i_a100_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a100_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a100_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "s_i2c0",	2 },
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc = {
+	.functions	= sun50i_a100_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a100_r_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
 static const struct udevice_id sunxi_pinctrl_ids[] = {
 #ifdef CONFIG_PINCTRL_SUNIV_F1C100S
 	{
@@ -937,6 +972,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
 		.data = (ulong)&sun50i_h616_r_pinctrl_desc,
 	},
 #endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100
+	{
+		.compatible = "allwinner,sun50i-a100-pinctrl",
+		.data = (ulong)&sun50i_a100_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100_R
+	{
+		.compatible = "allwinner,sun50i-a100-r-pinctrl",
+		.data = (ulong)&sun50i_a100_r_pinctrl_desc,
+	},
+#endif
 	{}
 };
 
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index e6b957f5537..b04be168bc8 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -23,18 +23,18 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
 		return;
 	}
 
-	drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
-	drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
-	drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
-	drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
+	drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE);
+	drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE);
+	drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE);
+	drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", PMUX_DRVDN_NONE);
 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
-	drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
+	drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE);
 #endif
 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
-	drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+	drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
 #endif
 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
-	drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+	drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
 #endif
 
 	for (i = 1; i < drvcnt; i++)
@@ -142,31 +142,31 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 
 	pinmux_group[0].func = i;
 
-	pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
-	pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
+	pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
+	pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", PMUX_TRI_TRISTATE);
 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
-	pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
+	pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
-	pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
+	pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_OD
-	pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
+	pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
-	pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
+	pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", PMUX_PIN_IO_RESET_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
-	pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
+	pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", PMUX_PIN_RCV_SEL_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
-	pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
+	pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", PMUX_PIN_E_IO_HV_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
-	pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+	pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_HSM
-	pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+	pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
 #endif
 
 	for (i = 1; i < pincnt; i++)
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 4b81aeb7497..eed65058e66 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -116,6 +116,12 @@ config AXP717_POWER
 	---help---
 	Select this to enable support for the AXP717 PMIC found on some boards.
 
+config AXP803_POWER
+	bool "AXP803 PMIC support"
+	select AXP_PMIC_BUS
+	---help---
+	Select this to enable support for the AXP803 PMIC found on some boards.
+
 config AXP809_POWER
 	bool "axp809 pmic support"
 	depends on MACH_SUN9I
@@ -142,10 +148,20 @@ config SY8106A_POWER
 
 endchoice
 
+config AXP_I2C_ADDRESS
+	hex "AXP PMIC I2C address"
+	depends on ARCH_SUNXI && !SUNXI_NO_PMIC
+	default 0x36 if AXP305_POWER
+	default 0x36 if AXP313_POWER
+	default 0x30 if AXP152_POWER
+	default 0x34
+	---help---
+	I2C address of the AXP PMIC, used for the SPL only.
+
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 3300 if AXP818_POWER || MACH_SUN8I_R40
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
+	default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER
 	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@@ -158,11 +174,12 @@ config AXP_DCDC1_VOLT
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER || AXP803_POWER
 	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1000 if AXP313_POWER
 	default 1000 if AXP717_POWER
+	default 1000 if AXP803_POWER
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
 	default 0 if MACH_SUN9I
@@ -219,7 +236,7 @@ config AXP_DCDC4_VOLT
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
 	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 3f4d56f5139..3363191fdc8 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AXP313_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP717_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
+obj-$(CONFIG_AXP803_POWER)	+= axp_spl.o
 endif
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_SY8106A_POWER)	+= sy8106a.o
diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
index 3c86eb20ab4..7c51a9b3dfb 100644
--- a/drivers/power/axp_spl.c
+++ b/drivers/power/axp_spl.c
@@ -36,6 +36,23 @@ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
 #define AXP_SHUTDOWN_REG	0x27
 #define AXP_SHUTDOWN_MASK	BIT(0)
 
+#elif defined(CONFIG_AXP803_POWER)				/* AXP803 */
+
+static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
+	{ 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
+	{ 0x10, BIT(1), 0x21, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(2), 0x22, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(3), 0x23, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(4), 0x24, 0x7f,  800, 1840,  10, 32 },
+	{ 0x10, BIT(5), 0x25, 0x7f,  600, 1520,  10, 50 },
+};
+
+#define AXP_CHIP_VERSION	0x3
+#define AXP_CHIP_VERSION_MASK	0xcf
+#define AXP_CHIP_ID		0x41
+#define AXP_SHUTDOWN_REG	0x32
+#define AXP_SHUTDOWN_MASK	BIT(7)
+
 #elif defined(CONFIG_AXP313_POWER)				/* AXP313 */
 
 static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 5e7a4c5648d..c3519307340 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -94,6 +94,8 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
 		.family = "J721E",
 		.data = &j721e_pd_platdata,
 	},
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J7200)
 	{
 		.family = "J7200",
 		.data = &j7200_pd_platdata,
@@ -116,6 +118,10 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
 		.family = "J784S4",
 		.data = &j784s4_pd_platdata,
 	},
+	{
+		.family = "J742S2",
+		.data = &j784s4_pd_platdata,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 958f337c7e7..8f102a92c23 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -478,3 +478,11 @@ config DM_REGULATOR_TPS65219
 	features for REGULATOR TPS65219 and the family of TPS65219 PMICs.
 	TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs.
 	The driver implements get/set api for value and enable.
+
+config REGULATOR_RZG2L_USBPHY
+	bool "Enable driver for RZ/G2L USB PHY VBUS supply"
+	depends on DM_REGULATOR
+	help
+	  Enable this option to support controlling the VBUS supply in
+	  the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
+	  is required in order to use the USB OTG port.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index ca6c89d13b5..4382d4b3ab9 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
 obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
 obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
+obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c
new file mode 100644
index 00000000000..451f04c140e
--- /dev/null
+++ b/drivers/power/regulator/rzg2l-usbphy-regulator.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <power/regulator.h>
+#include <renesas/rzg2l-usbphy.h>
+
+#define VBENCTL			0x03c
+#define VBENCTL_VBUS_SEL	BIT(0)
+
+static int rzg2l_usbphy_regulator_set_enable(struct udevice *dev, bool enable)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+	if (enable)
+		clrbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+	else
+		setbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+
+	return 0;
+}
+
+static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+	return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL;
+}
+
+static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = {
+	.get_enable = rzg2l_usbphy_regulator_get_enable,
+	.set_enable = rzg2l_usbphy_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(rzg2l_usbphy_regulator) = {
+	.name = "rzg2l_usbphy_regulator",
+	.id = UCLASS_REGULATOR,
+	.ops = &rzg2l_usbphy_regulator_ops,
+};
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 5cf2eba2ba0..898e353b370 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -30,6 +30,7 @@
 enum mtk_pwm_reg_ver {
 	PWM_REG_V1,
 	PWM_REG_V2,
+	PWM_REG_V3,
 };
 
 static const unsigned int mtk_pwm_reg_offset_v1[] = {
@@ -40,6 +41,10 @@ static const unsigned int mtk_pwm_reg_offset_v2[] = {
 	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
 };
 
+static const unsigned int mtk_pwm_reg_offset_v3[] = {
+	0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800
+};
+
 struct mtk_pwm_soc {
 	unsigned int num_pwms;
 	bool pwm45_fixup;
@@ -60,6 +65,10 @@ static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
 	u32 offset;
 
 	switch (priv->soc->reg_ver) {
+	case PWM_REG_V3:
+		offset = mtk_pwm_reg_offset_v3[channel];
+		break;
+
 	case PWM_REG_V2:
 		offset = mtk_pwm_reg_offset_v2[channel];
 		break;
@@ -203,6 +212,12 @@ static const struct mtk_pwm_soc mt7986_data = {
 	.reg_ver = PWM_REG_V1,
 };
 
+static const struct mtk_pwm_soc mt7987_data = {
+	.num_pwms = 3,
+	.pwm45_fixup = false,
+	.reg_ver = PWM_REG_V3,
+};
+
 static const struct mtk_pwm_soc mt7988_data = {
 	.num_pwms = 8,
 	.pwm45_fixup = false,
@@ -215,6 +230,7 @@ static const struct udevice_id mtk_pwm_ids[] = {
 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+	{ .compatible = "mediatek,mt7987-pwm", .data = (ulong)&mt7987_data },
 	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
 	{ }
 };
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 899d7585489..2a40b0c9f81 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -71,7 +71,7 @@ choice
 	depends on K3_DDRSS
 	prompt "K3 DDRSS Arch Support"
 
-	default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default K3_AM64_DDRSS if SOC_K3_AM642
 	default K3_AM64_DDRSS if SOC_K3_AM625
 	default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c
index d24b7c5c30a..4cbc6aeda43 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.c
+++ b/drivers/ram/renesas/dbsc5/dbsc5.c
@@ -59,7 +59,8 @@ int renesas_dbsc5_bind(struct udevice *dev)
 
 struct renesas_dbsc5_data r8a779g0_dbsc5_data = {
 	.clock_node = "renesas,r8a779g0-cpg-mssr",
-	.reset_node = "renesas,r8a779g0-rst"
+	.reset_node = "renesas,r8a779g0-rst",
+	.otp_node = "renesas,r8a779g0-otp",
 };
 
 static const struct udevice_id renesas_dbsc5_ids[] = {
diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h
index c410eb0c5ed..bf22fcb8c11 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.h
+++ b/drivers/ram/renesas/dbsc5/dbsc5.h
@@ -23,6 +23,7 @@
 struct renesas_dbsc5_data {
 	const char		*clock_node;
 	const char		*reset_node;
+	const char		*otp_node;
 };
 
 #endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 210a68f6496..ca8a7fb4783 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -4,6 +4,7 @@
  */
 
 #include <asm/io.h>
+#include <dbsc5.h>
 #include <dm.h>
 #include <errno.h>
 #include <hang.h>
@@ -12,13 +13,6 @@
 #include <linux/sizes.h>
 #include "dbsc5.h"
 
-/* The number of channels V4H has */
-#define DRAM_CH_CNT			4
-/* The number of slices V4H has */
-#define SLICE_CNT			2
-/* The number of chip select V4H has */
-#define CS_CNT				2
-
 /* Number of array elements in Data Slice */
 #define DDR_PHY_SLICE_REGSET_SIZE_V4H	0x100
 /* Number of array elements in Data Slice */
@@ -220,6 +214,7 @@ static const u16 jedec_spec2_tRFC_ab[] = {
 #define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS		DDR_REGDEF(0x00, 0x09, 0x103F)
 #define PHY_WDQLVL_STATUS_OBS			DDR_REGDEF(0x00, 0x20, 0x1043)
 #define PHY_DATA_DC_CAL_START			DDR_REGDEF(0x18, 0x01, 0x104D)
+#define PHY_SLV_DLY_CTRL_GATE_DISABLE		DDR_REGDEF(0x10, 0x01, 0x104E)
 #define PHY_REGULATOR_EN_CNT			DDR_REGDEF(0x18, 0x06, 0x1050)
 #define PHY_VREF_INITIAL_START_POINT		DDR_REGDEF(0x00, 0x09, 0x1055)
 #define PHY_VREF_INITIAL_STOP_POINT		DDR_REGDEF(0x10, 0x09, 0x1055)
@@ -469,7 +464,7 @@ static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = {
 	0x00000000, 0x00500050, 0x00500050, 0x00500050,
 	0x00500050, 0x0D000050, 0x10100004, 0x06102010,
 	0x61619041, 0x07097000, 0x00644180, 0x00803280,
-	0x00808001, 0x13010100, 0x02000016, 0x10001003,
+	0x00808001, 0x13010101, 0x02000016, 0x10001003,
 	0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140,
 	0x00000100, 0x000001D1, 0x05000068, 0x00030402,
 	0x01400000, 0x80800300, 0x00160010, 0x76543210,
@@ -512,8 +507,8 @@ static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = {
 	0x00040101, 0x00000000, 0x00000000, 0x00000064,
 	0x00000000, 0x00000000, 0x39421B42, 0x00010124,
 	0x00520052, 0x00000052, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x07030102,
+	0x00010001, 0x00000000, 0x00000000, 0x00010001,
+	0x00000000, 0x00000000, 0x00010001, 0x07030102,
 	0x01030307, 0x00000054, 0x00004096, 0x08200820,
 	0x08200820, 0x08200820, 0x08200820, 0x00000820,
 	0x004103B8, 0x0000003F, 0x000C0006, 0x00000000,
@@ -1294,7 +1289,7 @@ static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = {
 };
 
 static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = {
-	PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03
+	PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02
 };
 
 static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = {
@@ -1330,6 +1325,11 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = {
 #define DBSC_DBACEN			0x200
 #define DBSC_DBRFEN			0x204
 #define DBSC_DBCMD			0x208
+#define DBSC_DBCMD_CMD_OPCODE_PD	0x8
+#define DBSC_DBCMD_CMD_OPCODE_MRW	0xe
+#define DBSC_DBCMD_CMD_OPCODE_MRR	0xf
+#define DBSC_DBCMD_CMD_CHANNEL_ALL	0x8
+#define DBSC_DBCMD_CMD_RANK_ALL		0x4
 #define DBSC_DBWAIT			0x210
 #define DBSC_DBBL			0x400
 #define DBSC_DBBLA			0x400
@@ -1374,46 +1374,6 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = {
 
 #define CLK_DIV(a, diva, b, divb)	(((a) * (divb)) / ((b) * (diva)))
 
-struct renesas_dbsc5_board_config {
-	/* Channels in use */
-	u8 bdcfg_phyvalid;
-	/* Read vref (SoC) training range */
-	u32 bdcfg_vref_r;
-	/* Write vref (MR14, MR15) training range */
-	u16 bdcfg_vref_w;
-	/* CA vref (MR12) training range */
-	u16 bdcfg_vref_ca;
-	/* RFM required check */
-	bool bdcfg_rfm_chk;
-
-	/* Board parameter about channels */
-	struct {
-		/*
-		 * 0x00:  4Gb dual channel die /  2Gb single channel die
-		 * 0x01:  6Gb dual channel die /  3Gb single channel die
-		 * 0x02:  8Gb dual channel die /  4Gb single channel die
-		 * 0x03: 12Gb dual channel die /  6Gb single channel die
-		 * 0x04: 16Gb dual channel die /  8Gb single channel die
-		 * 0x05: 24Gb dual channel die / 12Gb single channel die
-		 * 0x06: 32Gb dual channel die / 16Gb single channel die
-		 * 0x07: 24Gb single channel die
-		 * 0x08: 32Gb single channel die
-		 * 0xFF: NO_MEMORY
-		 */
-		u8 bdcfg_ddr_density[CS_CNT];
-		/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
-		u32 bdcfg_ca_swap;
-		/* SoC dqsX([1][0]) -> MEM dqsY: */
-		u8 bdcfg_dqs_swap;
-		/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
-		u32 bdcfg_dq_swap[SLICE_CNT];
-		/* SoC dm -> MEM dqY/dm:  (8 means DM) */
-		u8 bdcfg_dm_swap[SLICE_CNT];
-		/* SoC ckeX([1][0]) -> MEM csY */
-		u8 bdcfg_cs_swap;
-	} ch[4];
-};
-
 struct renesas_dbsc5_dram_priv {
 	void __iomem	*regs;
 	void __iomem	*cpg_regs;
@@ -1713,14 +1673,17 @@ static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
-	u32 i, ch, reg;
+	u32 i, ch, chk, reg;
 
 	for (i = 0; i < 2; i++) {
 		do {
 			reg = status;
-			r_foreach_vch(dev, ch)
+			chk = 0;
+			r_foreach_vch(dev, ch) {
 				reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch));
-		} while (reg != status);
+				chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch));
+			}
+		} while (reg != status && !(chk & BIT(0)));
 	}
 }
 
@@ -1778,24 +1741,20 @@ static void dbsc5_reg_write(void __iomem *addr, u32 data)
 }
 
 /**
- * dbsc5_reg_write() - DRAM Command Write Access
+ * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion
  * @dev: DBSC5 device
- * @cmd DRAM command.
  *
- * First, execute the dummy read to DBSC_DBCMD.
- * Confirm that no DBSC command operation is in progress 0.
- * Write the contents of the command to be sent to DRAM.
+ * Wait for DRAM access completion. This is used before sending a command
+ * to the DRAM to assure no other command is in flight already, or while
+ * waiting for MRR command to complete.
  */
-static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd)
+static void dbsc5_wait_dbwait(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
 	u32 val;
 	int ret;
 
-	/* dummy read */
-	readl(regs_dbsc_d + DBSC_DBCMD);
-
 	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000);
 	if (ret < 0) {
 		printf("%s DBWAIT bit 0 timeout\n", __func__);
@@ -1807,6 +1766,32 @@ static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd)
 		printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__);
 		hang();
 	}
+}
+
+/**
+ * dbsc5_send_dbcmd2() - DRAM Command Write Access
+ * @dev: DBSC5 device
+ * @opcode DRAM controller opcode
+ * @channel DRAM controller channel (0..3)
+ * @rank DRAM controller rank (0..1)
+ * @arg Command and argument bits (command specific encoding)
+ *
+ * First, execute the dummy read to DBSC_DBCMD.
+ * Confirm that no DBSC command operation is in progress 0.
+ * Write the contents of the command to be sent to DRAM.
+ */
+static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode,
+			      const u8 channel, const u8 rank,
+			      const u16 arg)
+{
+	const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg;
+	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
+	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
+
+	/* dummy read */
+	readl(regs_dbsc_d + DBSC_DBCMD);
+
+	dbsc5_wait_dbwait(dev);
 
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd);
 }
@@ -2192,7 +2177,7 @@ static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv)
 		if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3)
 			break;
 
-	priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI);
+	priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI);
 
 	priv->RL = js1[priv->js1_ind].RLset1;
 	priv->WL = js1[priv->js1_ind].WLsetA;
@@ -2635,7 +2620,7 @@ static void dbsc5_dbsc_regset(struct udevice *dev)
 	 */
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11),
 			priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] -
-			js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]);
+			js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2);
 
 	/* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12),
@@ -2992,10 +2977,14 @@ static u32 dbsc5_pi_training(struct udevice *dev)
 		writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch));
 
 	/* Dummy PDE */
-	dbsc5_send_dbcmd2(dev, 0x8840000);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, 0);
 
 	/* PDX */
-	dbsc5_send_dbcmd2(dev, 0x8840001);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, 1);
 
 	/* Wait init_complete */
 	for (retry = 0; retry < retry_max; retry++) {
@@ -3491,13 +3480,10 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1;
-	u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-	u32 slv_dly_center_cyc;
-	u32 slv_dly_center_dly;
+	u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+	u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT];
 	u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT];
 	u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT];
-	u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-	u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
 	u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT];
 	u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT];
 	u32 phy_dcc_code_mid;
@@ -3521,18 +3507,9 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 		dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs);
 		r_foreach_vch(dev, ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
-				slv_dly_center[ch][cs][slice] =
-					dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY);
-				slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180;
-				slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F;
-				slv_dly_min_tmp[ch][cs][slice] =
-					slv_dly_center_cyc |
-					(slv_dly_center_dly * ratio_min / ratio_min_div);
-				slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc;
-				if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div))
-					slv_dly_max_tmp[ch][cs][slice] |= 0x7F;
-				else
-					slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div;
+				phy_slv_dly[ch][cs][slice] =
+					dbsc5_ddr_getval_slice(dev, ch, slice,
+							       PHY_CLK_WRDQS_SLAVE_DELAY);
 			}
 		}
 	}
@@ -3540,22 +3517,22 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 	r_foreach_vch(dev, ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			if (rank == 0x2) {
-				if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice])
-					slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice];
-				else
-					slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
-
-				if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice])
-					slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
-				else
-					slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice];
+				/* Calculate average between ranks */
+				phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] +
+							      phy_slv_dly[ch][1][slice]) / 2;
 			} else {
-				slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
-				slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
+				phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice];
 			}
+			/* Determine the search range */
+			slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div;
+			slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div;
+			if (slv_dly_max[ch][slice] > 0x7F)
+				slv_dly_max[ch][slice] = 0x7F;
 		}
 	}
 
+	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1);
+
 	for (i = 0; i <= 0x7F; i++) {
 		r_foreach_vch(dev, ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3621,13 +3598,16 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 			for (slice = 0; slice < SLICE_CNT; slice++) {
 				dbsc5_ddr_setval_slice(dev, ch, slice,
 						       PHY_CLK_WRDQS_SLAVE_DELAY,
-						       slv_dly_center[ch][cs][slice]);
+						       phy_slv_dly[ch][cs][slice]);
 				dbsc5_ddr_setval_slice(dev, ch, slice,
 						       SC_PHY_WCK_CALC, 0x1);
 				dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1);
 			}
 		}
 	}
+
+	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0);
+
 	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1);
 
 	r_foreach_vch(dev, ch) {
@@ -4136,25 +4116,27 @@ static u32 dbsc5_read_training(struct udevice *dev)
 }
 
 /**
- * dbsc5_ddr_register_set() - DDR mode register setting
+ * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set
  * @dev: DBSC5 device
  *
  * Set the mode register 28 of the SDRAM.
  * ZQ Mode: Command-Based ZQ Calibration
  * ZQ interval: Background Cal Interval < 64ms
  */
-static void dbsc5_ddr_register_set(struct udevice *dev)
+static void dbsc5_ddr_register_mr28_set(struct udevice *dev)
 {
-	dbsc5_send_dbcmd2(dev, 0xE841C24);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRW,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, (28 << 8) | 0x24);
 }
 
 /**
- * dbsc5_ddr_register_read() - DDR mode register read
+ * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read
  * @dev: DBSC5 device
  *
  * Set the mode register 27 and 57 of the SDRAM.
  */
-static void dbsc5_ddr_register_read(struct udevice *dev)
+static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 
@@ -4162,17 +4144,21 @@ static void dbsc5_ddr_register_read(struct udevice *dev)
 		return;
 
 	/* MR27 rank0 */
-	dbsc5_send_dbcmd2(dev, 0xF801B00);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 27 << 8);
 	/* MR57 rank0 */
-	dbsc5_send_dbcmd2(dev, 0xF803900);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 57 << 8);
 
 	if (!priv->ch_have_this_cs[1])
 		return;
 
 	/* MR27 rank1 */
-	dbsc5_send_dbcmd2(dev, 0xF811B00);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 27 << 8);
 	/* MR57 rank1 */
-	dbsc5_send_dbcmd2(dev, 0xF813900);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 57 << 8);
 }
 
 /**
@@ -4251,8 +4237,8 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 	dbsc5_dbsc_regset(dev);
 
 	/* Frequency selection change (F1->F2) */
-	 dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
-	 dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
+	dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
+	dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
 
 	/* dfi_init_start (start ddrphy) & execute pi_training */
 	phytrainingok = dbsc5_pi_training(dev);
@@ -4329,10 +4315,10 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 
 	/* setup DDR mode registers */
 	/* MRS */
-	dbsc5_ddr_register_set(dev);
+	dbsc5_ddr_register_mr28_set(dev);
 
 	/* MRR */
-	dbsc5_ddr_register_read(dev);
+	dbsc5_ddr_register_mr27_mr57_read(dev);
 
 	/* training complete, setup DBSC */
 	dbsc5_dbsc_regset_post(dev);
@@ -4347,10 +4333,13 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 
 /**
  * dbsc5_get_board_data() - Obtain board specific DRAM configuration
+ * @dev: DBSC5 device
+ * @modemr0: MODEMR0 register content
  *
  * Return board specific DRAM configuration structure pointer.
  */
-__weak const struct renesas_dbsc5_board_config *dbsc5_get_board_data(void)
+__weak const struct renesas_dbsc5_board_config *
+dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
 {
 	return &renesas_v4h_dbsc5_board_config;
 }
@@ -4369,20 +4358,24 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 {
 #define RST_MODEMR0			0x0
 #define RST_MODEMR1			0x4
+#define OTP_MONITOR17			0x1144
 	struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev);
 	ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node);
 	ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node);
+	ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node);
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET;
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
 	phys_addr_t rregs = ofnode_get_addr(rnode);
 	const u32 modemr0 = readl(rregs + RST_MODEMR0);
 	const u32 modemr1 = readl(rregs + RST_MODEMR1);
-	u32 breg, reg, md, sscg;
+	phys_addr_t oregs = ofnode_get_addr(onode);
+	const u32 otpmon17 = readl(oregs + OTP_MONITOR17);
+	u32 breg, reg, md, sscg, product;
 	u32 ch, cs;
 
 	/* Get board data */
-	priv->dbsc5_board_config = dbsc5_get_board_data();
+	priv->dbsc5_board_config = dbsc5_get_board_data(dev, modemr0);
 	priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid);
 	priv->max_density = 0;
 	priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode);
@@ -4433,29 +4426,41 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 
 	/* Decode DDR operating frequency from MD[37:36,19,17] pins */
 	md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17);
+	product = otpmon17 & 0xff;
 	sscg = (modemr1 >> 4) & 0x03;
 	if (sscg == 2) {
 		printf("MD[37:36] setting 0x%x not supported!", sscg);
 		hang();
 	}
 
-	if (md == 0) {
-		if (sscg == 0) {
-			priv->ddr_mbps = 6400;
-			priv->ddr_mbpsdiv = 1;
-		} else {
-			priv->ddr_mbps = 19000;
-			priv->ddr_mbpsdiv = 3;
-		}
-	} else if (md == 1) {
-		priv->ddr_mbps = 6000;
-		priv->ddr_mbpsdiv = 1;
-	} else if (md == 1) {
-		priv->ddr_mbps = 5500;
-		priv->ddr_mbpsdiv = 1;
-	} else if (md == 1) {
+	if (product == 0x2) {			/* V4H-3 */
 		priv->ddr_mbps = 4800;
 		priv->ddr_mbpsdiv = 1;
+	} else if (product == 0x1) {		/* V4H-5 */
+		if (md == 3)
+			priv->ddr_mbps = 4800;
+		else
+			priv->ddr_mbps = 5000;
+		priv->ddr_mbpsdiv = 1;
+	} else {				/* V4H-7 */
+		if (md == 0) {
+			if (sscg == 0) {
+				priv->ddr_mbps = 6400;
+				priv->ddr_mbpsdiv = 1;
+			} else {
+				priv->ddr_mbps = 19000;
+				priv->ddr_mbpsdiv = 3;
+			}
+		} else if (md == 1) {
+			priv->ddr_mbps = 6000;
+			priv->ddr_mbpsdiv = 1;
+		} else if (md == 2) {
+			priv->ddr_mbps = 5500;
+			priv->ddr_mbpsdiv = 1;
+		} else if (md == 3) {
+			priv->ddr_mbps = 4800;
+			priv->ddr_mbpsdiv = 1;
+		}
 	}
 
 	priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2,
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index fe5c1214f57..a0d079c4555 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -49,6 +49,13 @@ config TEGRA186_RESET
 	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
 	  requests to the BPMP (Boot and Power Management Processor).
 
+config RESET_AIROHA
+	bool "Reset controller driver for Airoha SoCs"
+	depends on DM_RESET && ARCH_AIROHA
+	default y
+	help
+	  Support for reset controller on Airoha SoCs.
+
 config RESET_TI_SCI
 	bool "TI System Control Interface (TI SCI) reset driver"
 	depends on DM_RESET && TI_SCI_PROTOCOL
@@ -235,4 +242,20 @@ config RESET_AT91
 	  This enables the Reset Controller driver support for Microchip/Atmel
 	  SoCs. Mainly used to expose assert/deassert methods to other drivers
 	  that require it.
+
+config RESET_RZG2L_USBPHY_CTRL
+	bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control"
+	depends on DM_RESET
+	select REGULATOR_RZG2L_USBPHY
+	help
+	  Enable support for controlling USB 2.0 PHY resets on the Renesas
+	  RZ/G2L SoC. This is required for USB 2.0 functionality to work on this
+	  SoC.
+
+config RESET_SPACEMIT_K1
+	bool "Support for SPACEMIT's K1 Reset driver"
+	depends on DM_RESET
+	help
+	  Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert
+	  is supported.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d99a78c9828..b9494396013 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_STI_RESET) += sti-reset.o
 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
@@ -33,3 +34,5 @@ obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
 obj-$(CONFIG_RESET_AT91) += reset-at91.o
 obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o
+obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
diff --git a/drivers/reset/reset-airoha.c b/drivers/reset/reset-airoha.c
new file mode 100644
index 00000000000..e878af6167c
--- /dev/null
+++ b/drivers/reset/reset-airoha.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Based on Linux drivers/clk/clk-en7523.c reworked
+ * and detached to a dedicated driver
+ *
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org> (original driver)
+ *	   Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <dm.h>
+#include <linux/io.h>
+#include <reset-uclass.h>
+
+#include <dt-bindings/reset/airoha,en7581-reset.h>
+
+#define RST_NR_PER_BANK			32
+
+#define REG_RESET_CONTROL2		0x830
+#define REG_RESET_CONTROL1		0x834
+
+struct airoha_reset_priv {
+	const u16 *bank_ofs;
+	const u16 *idx_map;
+	void __iomem *base;
+};
+
+static const u16 en7581_rst_ofs[] = {
+	REG_RESET_CONTROL2,
+	REG_RESET_CONTROL1,
+};
+
+static const u16 en7581_rst_map[] = {
+	/* RST_CTRL2 */
+	[EN7581_XPON_PHY_RST]		= 0,
+	[EN7581_CPU_TIMER2_RST]		= 2,
+	[EN7581_HSUART_RST]		= 3,
+	[EN7581_UART4_RST]		= 4,
+	[EN7581_UART5_RST]		= 5,
+	[EN7581_I2C2_RST]		= 6,
+	[EN7581_XSI_MAC_RST]		= 7,
+	[EN7581_XSI_PHY_RST]		= 8,
+	[EN7581_NPU_RST]		= 9,
+	[EN7581_I2S_RST]		= 10,
+	[EN7581_TRNG_RST]		= 11,
+	[EN7581_TRNG_MSTART_RST]	= 12,
+	[EN7581_DUAL_HSI0_RST]		= 13,
+	[EN7581_DUAL_HSI1_RST]		= 14,
+	[EN7581_HSI_RST]		= 15,
+	[EN7581_DUAL_HSI0_MAC_RST]	= 16,
+	[EN7581_DUAL_HSI1_MAC_RST]	= 17,
+	[EN7581_HSI_MAC_RST]		= 18,
+	[EN7581_WDMA_RST]		= 19,
+	[EN7581_WOE0_RST]		= 20,
+	[EN7581_WOE1_RST]		= 21,
+	[EN7581_HSDMA_RST]		= 22,
+	[EN7581_TDMA_RST]		= 24,
+	[EN7581_EMMC_RST]		= 25,
+	[EN7581_SOE_RST]		= 26,
+	[EN7581_PCIE2_RST]		= 27,
+	[EN7581_XFP_MAC_RST]		= 28,
+	[EN7581_USB_HOST_P1_RST]	= 29,
+	[EN7581_USB_HOST_P1_U3_PHY_RST]	= 30,
+	/* RST_CTRL1 */
+	[EN7581_PCM1_ZSI_ISI_RST]	= RST_NR_PER_BANK + 0,
+	[EN7581_FE_PDMA_RST]		= RST_NR_PER_BANK + 1,
+	[EN7581_FE_QDMA_RST]		= RST_NR_PER_BANK + 2,
+	[EN7581_PCM_SPIWP_RST]		= RST_NR_PER_BANK + 4,
+	[EN7581_CRYPTO_RST]		= RST_NR_PER_BANK + 6,
+	[EN7581_TIMER_RST]		= RST_NR_PER_BANK + 8,
+	[EN7581_PCM1_RST]		= RST_NR_PER_BANK + 11,
+	[EN7581_UART_RST]		= RST_NR_PER_BANK + 12,
+	[EN7581_GPIO_RST]		= RST_NR_PER_BANK + 13,
+	[EN7581_GDMA_RST]		= RST_NR_PER_BANK + 14,
+	[EN7581_I2C_MASTER_RST]		= RST_NR_PER_BANK + 16,
+	[EN7581_PCM2_ZSI_ISI_RST]	= RST_NR_PER_BANK + 17,
+	[EN7581_SFC_RST]		= RST_NR_PER_BANK + 18,
+	[EN7581_UART2_RST]		= RST_NR_PER_BANK + 19,
+	[EN7581_GDMP_RST]		= RST_NR_PER_BANK + 20,
+	[EN7581_FE_RST]			= RST_NR_PER_BANK + 21,
+	[EN7581_USB_HOST_P0_RST]	= RST_NR_PER_BANK + 22,
+	[EN7581_GSW_RST]		= RST_NR_PER_BANK + 23,
+	[EN7581_SFC2_PCM_RST]		= RST_NR_PER_BANK + 25,
+	[EN7581_PCIE0_RST]		= RST_NR_PER_BANK + 26,
+	[EN7581_PCIE1_RST]		= RST_NR_PER_BANK + 27,
+	[EN7581_CPU_TIMER_RST]		= RST_NR_PER_BANK + 28,
+	[EN7581_PCIE_HB_RST]		= RST_NR_PER_BANK + 29,
+	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
+};
+
+static int airoha_reset_update(struct airoha_reset_priv *priv,
+			       unsigned long id, bool assert)
+{
+	void __iomem *addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
+	u32 val;
+
+	val = readl(addr);
+	if (assert)
+		val |= BIT(id % RST_NR_PER_BANK);
+	else
+		val &= ~BIT(id % RST_NR_PER_BANK);
+	writel(val, addr);
+
+	return 0;
+}
+
+static int airoha_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	return airoha_reset_update(priv, id, true);
+}
+
+static int airoha_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	return airoha_reset_update(priv, id, false);
+}
+
+static int airoha_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+	void __iomem *addr;
+
+	addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
+
+	return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
+}
+
+static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
+			      struct ofnode_phandle_args *args)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	if (args->args[0] >= ARRAY_SIZE(en7581_rst_map))
+		return -EINVAL;
+
+	reset_ctl->id = priv->idx_map[args->args[0]];
+
+	return 0;
+}
+
+static struct reset_ops airoha_reset_ops = {
+	.of_xlate = airoha_reset_xlate,
+	.rst_assert = airoha_reset_assert,
+	.rst_deassert = airoha_reset_deassert,
+	.rst_status = airoha_reset_status,
+};
+
+static int airoha_reset_probe(struct udevice *dev)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->bank_ofs = en7581_rst_ofs;
+	priv->idx_map = en7581_rst_map;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(airoha_reset) = {
+	.name = "airoha-reset",
+	.id = UCLASS_RESET,
+	.probe = airoha_reset_probe,
+	.ops = &airoha_reset_ops,
+	.priv_auto = sizeof(struct airoha_reset_priv),
+};
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
new file mode 100644
index 00000000000..622d7b9cf4f
--- /dev/null
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <renesas/rzg2l-usbphy.h>
+#include <reset-uclass.h>
+#include <reset.h>
+
+#define RESET			0x000
+
+#define RESET_SEL_PLLRESET	BIT(12)
+#define RESET_PLLRESET		BIT(8)
+
+#define RESET_SEL_P2RESET	BIT(5)
+#define RESET_SEL_P1RESET	BIT(4)
+#define RESET_PHYRST_2		BIT(1)
+#define RESET_PHYRST_1		BIT(0)
+
+#define PHY_RESET_MASK          (RESET_PHYRST_1 | RESET_PHYRST_2)
+
+#define NUM_PORTS		2
+
+static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+	u32 val;
+
+	val = readl(priv->regs + RESET);
+	val |= reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+	/* If both ports are in reset, we can also place the PLL into reset. */
+	if ((val & PHY_RESET_MASK) == PHY_RESET_MASK)
+		val |= RESET_PLLRESET;
+
+	writel(val, priv->regs + RESET);
+	return 0;
+}
+
+static int rzg2l_usbphy_ctrl_deassert(struct reset_ctl *reset_ctl)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+	u32 val = reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+	/* If either port is out of reset, the PLL must also be out of reset. */
+	val |= RESET_PLLRESET;
+
+	clrbits_le32(priv->regs + RESET, val);
+	return 0;
+}
+
+static int rzg2l_usbphy_ctrl_of_xlate(struct reset_ctl *reset_ctl,
+				      struct ofnode_phandle_args *args)
+{
+	if (args->args[0] >= NUM_PORTS)
+		return -EINVAL;
+
+	reset_ctl->id = args->args[0];
+	return 0;
+}
+
+struct reset_ops rzg2l_usbphy_ctrl_ops = {
+	.rst_assert = rzg2l_usbphy_ctrl_assert,
+	.rst_deassert = rzg2l_usbphy_ctrl_deassert,
+	.of_xlate = rzg2l_usbphy_ctrl_of_xlate,
+};
+
+static int rzg2l_usbphy_ctrl_probe(struct udevice *dev)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev);
+	struct reset_ctl rst;
+	int ret;
+
+	priv->regs = dev_read_addr(dev);
+
+	ret = reset_get_by_index(dev, 0, &rst);
+	if (ret < 0) {
+		dev_err(dev, "failed to get reset line: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_deassert(&rst);
+	if (ret < 0) {
+		dev_err(dev, "failed to de-assert reset line: %d\n", ret);
+		return ret;
+	}
+
+	/* put pll and phy into reset state */
+	setbits_le32(priv->regs + RESET,
+		     RESET_SEL_PLLRESET | RESET_PLLRESET |
+		     RESET_SEL_P1RESET | RESET_PHYRST_1 |
+		     RESET_SEL_P2RESET | RESET_PHYRST_2);
+
+	return 0;
+}
+
+static const struct udevice_id rzg2l_usbphy_ctrl_ids[] = {
+	{ .compatible = "renesas,rzg2l-usbphy-ctrl", },
+	{ /* sentinel */ }
+};
+
+static int rzg2l_usbphy_ctrl_bind(struct udevice *dev)
+{
+	struct driver *drv;
+	ofnode node;
+	int ret;
+
+	node = ofnode_find_subnode(dev_ofnode(dev), "regulator-vbus");
+	if (!ofnode_valid(node)) {
+		dev_err(dev, "Failed to find vbus regulator devicetree node\n");
+		return -ENOENT;
+	}
+
+	drv = lists_driver_lookup_name("rzg2l_usbphy_regulator");
+	if (!drv) {
+		dev_err(dev, "Failed to find vbus regulator driver\n");
+		return -ENOENT;
+	}
+
+	ret = device_bind(dev, drv, dev->name, NULL, node, NULL);
+	if (ret) {
+		dev_err(dev, "Failed to bind vbus regulator: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rzg2l_usbphy_ctrl) = {
+	.name           = "rzg2l_usbphy_ctrl",
+	.id             = UCLASS_RESET,
+	.of_match       = rzg2l_usbphy_ctrl_ids,
+	.bind           = rzg2l_usbphy_ctrl_bind,
+	.probe          = rzg2l_usbphy_ctrl_probe,
+	.ops            = &rzg2l_usbphy_ctrl_ops,
+	.priv_auto      = sizeof(struct rzg2l_usbphy_ctrl_priv),
+};
diff --git a/drivers/reset/reset-spacemit-k1.c b/drivers/reset/reset-spacemit-k1.c
new file mode 100644
index 00000000000..613e002fc4f
--- /dev/null
+++ b/drivers/reset/reset-spacemit-k1.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/reset/spacemit-k1-reset.h>
+#include <linux/bitops.h>
+#include <reset-uclass.h>
+
+/* APBC register offset */
+#define APBC_UART1_CLK_RST      0x0
+#define APBC_UART2_CLK_RST      0x4
+#define APBC_GPIO_CLK_RST       0x8
+#define APBC_PWM0_CLK_RST       0xc
+#define APBC_PWM1_CLK_RST       0x10
+#define APBC_PWM2_CLK_RST       0x14
+#define APBC_PWM3_CLK_RST       0x18
+#define APBC_TWSI8_CLK_RST      0x20
+#define APBC_UART3_CLK_RST      0x24
+#define APBC_RTC_CLK_RST        0x28
+#define APBC_TWSI0_CLK_RST      0x2c
+#define APBC_TWSI1_CLK_RST      0x30
+#define APBC_TIMERS1_CLK_RST    0x34
+#define APBC_TWSI2_CLK_RST      0x38
+#define APBC_AIB_CLK_RST        0x3c
+#define APBC_TWSI4_CLK_RST      0x40
+#define APBC_TIMERS2_CLK_RST    0x44
+#define APBC_ONEWIRE_CLK_RST    0x48
+#define APBC_TWSI5_CLK_RST      0x4c
+#define APBC_DRO_CLK_RST        0x58
+#define APBC_IR_CLK_RST         0x5c
+#define APBC_TWSI6_CLK_RST      0x60
+#define APBC_TWSI7_CLK_RST      0x68
+#define APBC_TSEN_CLK_RST       0x6c
+
+#define APBC_UART4_CLK_RST      0x70
+#define APBC_UART5_CLK_RST      0x74
+#define APBC_UART6_CLK_RST      0x78
+#define APBC_SSP3_CLK_RST       0x7c
+
+#define APBC_SSPA0_CLK_RST      0x80
+#define APBC_SSPA1_CLK_RST      0x84
+
+#define APBC_IPC_AP2AUD_CLK_RST 0x90
+#define APBC_UART7_CLK_RST      0x94
+#define APBC_UART8_CLK_RST      0x98
+#define APBC_UART9_CLK_RST      0x9c
+
+#define APBC_CAN0_CLK_RST       0xa0
+#define APBC_PWM4_CLK_RST       0xa8
+#define APBC_PWM5_CLK_RST       0xac
+#define APBC_PWM6_CLK_RST       0xb0
+#define APBC_PWM7_CLK_RST       0xb4
+#define APBC_PWM8_CLK_RST       0xb8
+#define APBC_PWM9_CLK_RST       0xbc
+#define APBC_PWM10_CLK_RST      0xc0
+#define APBC_PWM11_CLK_RST      0xc4
+#define APBC_PWM12_CLK_RST      0xc8
+#define APBC_PWM13_CLK_RST      0xcc
+#define APBC_PWM14_CLK_RST      0xd0
+#define APBC_PWM15_CLK_RST      0xd4
+#define APBC_PWM16_CLK_RST      0xd8
+#define APBC_PWM17_CLK_RST      0xdc
+#define APBC_PWM18_CLK_RST      0xe0
+#define APBC_PWM19_CLK_RST      0xe4
+/* end of APBC register offset */
+
+/* MPMU register offset */
+#define MPMU_WDTPCR     0x200
+/* end of MPMU register offset */
+
+/* APMU register offset */
+#define APMU_JPG_CLK_RES_CTRL       0x20
+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24
+#define APMU_ISP_CLK_RES_CTRL       0x38
+#define APMU_LCD_CLK_RES_CTRL1      0x44
+#define APMU_LCD_SPI_CLK_RES_CTRL   0x48
+#define APMU_LCD_CLK_RES_CTRL2      0x4c
+#define APMU_CCIC_CLK_RES_CTRL      0x50
+#define APMU_SDH0_CLK_RES_CTRL      0x54
+#define APMU_SDH1_CLK_RES_CTRL      0x58
+#define APMU_USB_CLK_RES_CTRL       0x5c
+#define APMU_QSPI_CLK_RES_CTRL      0x60
+#define APMU_USB_CLK_RES_CTRL       0x5c
+#define APMU_DMA_CLK_RES_CTRL       0x64
+#define APMU_AES_CLK_RES_CTRL       0x68
+#define APMU_VPU_CLK_RES_CTRL       0xa4
+#define APMU_GPU_CLK_RES_CTRL       0xcc
+#define APMU_SDH2_CLK_RES_CTRL      0xe0
+#define APMU_PMUA_MC_CTRL           0xe8
+#define APMU_PMU_CC2_AP             0x100
+#define APMU_PMUA_EM_CLK_RES_CTRL   0x104
+
+#define APMU_AUDIO_CLK_RES_CTRL     0x14c
+#define APMU_HDMI_CLK_RES_CTRL      0x1B8
+
+#define APMU_PCIE_CLK_RES_CTRL_0    0x3cc
+#define APMU_PCIE_CLK_RES_CTRL_1    0x3d4
+#define APMU_PCIE_CLK_RES_CTRL_2    0x3dc
+
+#define APMU_EMAC0_CLK_RES_CTRL     0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL     0x3ec
+/* end of APMU register offset */
+
+/* APBC2 register offset */
+#define APBC2_UART1_CLK_RST		0x00
+#define APBC2_SSP2_CLK_RST		0x04
+#define APBC2_TWSI3_CLK_RST		0x08
+#define APBC2_RTC_CLK_RST		0x0c
+#define APBC2_TIMERS0_CLK_RST	0x10
+#define APBC2_KPC_CLK_RST		0x14
+#define APBC2_GPIO_CLK_RST		0x1c
+/* end of APBC2 register offset */
+
+enum spacemit_reset_base_type {
+	RST_BASE_TYPE_MPMU       = 0,
+	RST_BASE_TYPE_APMU       = 1,
+	RST_BASE_TYPE_APBC       = 2,
+	RST_BASE_TYPE_APBS       = 3,
+	RST_BASE_TYPE_CIU        = 4,
+	RST_BASE_TYPE_DCIU       = 5,
+	RST_BASE_TYPE_DDRC       = 6,
+	RST_BASE_TYPE_AUDC       = 7,
+	RST_BASE_TYPE_APBC2      = 8,
+};
+
+struct spacemit_reset_signal {
+	u32 offset;
+	u32 mask;
+	u32 deassert_val;
+	u32 assert_val;
+	enum spacemit_reset_base_type type;
+};
+
+struct spacemit_reset_base {
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+	void __iomem *apbs_base;
+	void __iomem *ciu_base;
+	void __iomem *dciu_base;
+	void __iomem *ddrc_base;
+	void __iomem *audio_ctrl_base;
+	void __iomem *apbc2_base;
+};
+
+struct spacemit_reset {
+	struct spacemit_reset_base io_base;
+	const struct spacemit_reset_signal *signals;
+};
+
+enum {
+	RESET_TWSI6_SPL = 0,
+	RESET_TWSI8_SPL,
+	RESET_SDH_AXI_SPL,
+	RESET_SDH0_SPL,
+	RESET_USB_AXI_SPL,
+	RESET_USBP1_AXI_SPL,
+	RESET_USB3_0_SPL,
+	RESET_QSPI_SPL,
+	RESET_QSPI_BUS_SPL,
+	RESET_AES_SPL,
+	RESET_SDH2_SPL,
+	RESET_NUMBER_SPL
+};
+
+static const struct spacemit_reset_signal
+	k1_reset_signals[RESET_NUMBER] = {
+	[RESET_UART1]   = { APBC_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART2]   = { APBC_UART2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_GPIO]    = { APBC_GPIO_CLK_RST, BIT(2), 0,
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM0]    = { APBC_PWM0_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM1]    = { APBC_PWM1_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM2]    = { APBC_PWM2_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM3]    = { APBC_PWM3_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM4]    = { APBC_PWM4_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM5]    = { APBC_PWM5_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM6]    = { APBC_PWM6_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM7]    = { APBC_PWM7_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM8]    = { APBC_PWM8_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM9]    = { APBC_PWM9_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM10]   = { APBC_PWM10_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM11]   = { APBC_PWM11_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM12]   = { APBC_PWM12_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM13]   = { APBC_PWM13_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM14]   = { APBC_PWM14_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM15]   = { APBC_PWM15_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM16]   = { APBC_PWM16_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM17]   = { APBC_PWM17_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM18]   = { APBC_PWM18_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM19]   = { APBC_PWM19_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_SSP3]    = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART3]   = { APBC_UART3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_RTC]     = { APBC_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI0]   = { APBC_TWSI0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_AIB]     = { APBC_AIB_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SSPA0]   = { APBC_SSPA0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SSPA1]   = { APBC_SSPA1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_DRO]     = { APBC_DRO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IR]      = { APBC_IR_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI1]   = { APBC_TWSI1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TSEN]    = { APBC_TSEN_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI2]   = { APBC_TWSI2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI4]   = { APBC_TWSI4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI5]   = { APBC_TWSI5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI6]   = { APBC_TWSI6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI7]   = { APBC_TWSI7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI8]   = { APBC_TWSI8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IPC_AP2AUD]   = { APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART4]   = { APBC_UART4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART5]   = { APBC_UART5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART6]   = { APBC_UART6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART7]   = { APBC_UART7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART8]   = { APBC_UART8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART9]   = { APBC_UART9_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN0]    = { APBC_CAN0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	/* MPMU */
+	[RESET_WDT]     = { MPMU_WDTPCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU },
+	/* APMU */
+	[RESET_JPG]     = { APMU_JPG_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_CSI]     = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC2_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+				BIT(2),
+				BIT(2),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_CCIC3_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+				BIT(29),
+				BIT(29),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_ISP]     = { APMU_ISP_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_AHB] = { APMU_ISP_CLK_RES_CTRL, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_CI]  = { APMU_ISP_CLK_RES_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_CPP] = { APMU_ISP_CLK_RES_CTRL, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD]     = { APMU_LCD_CLK_RES_CTRL1, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI_ESC] = { APMU_LCD_CLK_RES_CTRL1, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_V2D]     = { APMU_LCD_CLK_RES_CTRL1, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+	[RESET_MIPI]    = { APMU_LCD_CLK_RES_CTRL1, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI] = { APMU_LCD_SPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI_BUS]     = { APMU_LCD_SPI_CLK_RES_CTRL,
+				BIT(4),
+				BIT(4),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI_HBUS]    = { APMU_LCD_SPI_CLK_RES_CTRL,
+				BIT(2),
+				BIT(2),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_LCD_MCLK]    = { APMU_LCD_CLK_RES_CTRL2, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC_4X]     = { APMU_CCIC_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC1_PHY]   = { APMU_CCIC_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH_AXI]     = { APMU_SDH0_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH0]      = { APMU_SDH0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH1]	  = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB_AXI]	  = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_0]	  = { APMU_USB_CLK_RES_CTRL,
+				BIT(9) | BIT(10) | BIT(11),
+				BIT(9) | BIT(10) | BIT(11),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_QSPI]  = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_QSPI_BUS]  = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_DMA]	 = { APMU_DMA_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_AES]	 = { APMU_AES_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_VPU]	 = { APMU_VPU_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_GPU]	 = { APMU_GPU_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH2] = { APMU_SDH2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_MC]	 = { APMU_PMUA_MC_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EM_AXI]	= { APMU_PMUA_EM_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EM]	= { APMU_PMUA_EM_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_AUDIO_SYS] = { APMU_AUDIO_CLK_RES_CTRL,
+				BIT(0) | BIT(2) | BIT(3),
+				BIT(0) | BIT(2) | BIT(3),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_HDMI]	 = { APMU_HDMI_CLK_RES_CTRL, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE0]	 = { APMU_PCIE_CLK_RES_CTRL_0,
+				BIT(3) | BIT(4) | BIT(5) | BIT(8),
+				BIT(3) | BIT(4) | BIT(5),
+				BIT(8),
+				RST_BASE_TYPE_APMU },
+	[RESET_PCIE1]	 = { APMU_PCIE_CLK_RES_CTRL_1,
+				BIT(3) | BIT(4) | BIT(5) | BIT(8),
+				BIT(3) | BIT(4) | BIT(5),
+				BIT(8),
+				RST_BASE_TYPE_APMU },
+	[RESET_PCIE2]	 = { APMU_PCIE_CLK_RES_CTRL_2, 0x138, 0x38, 0x100, RST_BASE_TYPE_APMU },
+	[RESET_EMAC0]	 = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_EMAC1]	 = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SEC_UART1]	= { APBC2_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_SSP2]	= { APBC2_SSP2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TWSI3]	= { APBC2_TWSI3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_RTC]		= { APBC2_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TIMERS0]	= { APBC2_TIMERS0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_KPC]		= { APBC2_KPC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_GPIO]	= { APBC2_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	};
+
+static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->io_base.apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->io_base.apbc_base;
+		break;
+	default:
+		base = reset->io_base.apbc_base;
+		break;
+	}
+
+	return readl(base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->io_base.apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->io_base.apbc_base;
+		break;
+	default:
+		base = reset->io_base.apbc_base;
+		break;
+	}
+
+	writel(value, base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_set(struct reset_ctl *rst, u32 id, bool assert)
+{
+	u32 value;
+	struct spacemit_reset *reset = dev_get_priv(rst->dev);
+
+	value = spacemit_reset_read(reset, id);
+
+	if (assert) {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].assert_val;
+	} else {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].deassert_val;
+	}
+
+	spacemit_reset_write(reset, value, id);
+}
+
+static int spacemit_reset_update(struct reset_ctl *rst, bool assert)
+{
+	if (rst->id < RESET_UART1 || rst->id >= RESET_NUMBER)
+		return 0;
+
+	/* can not write to twsi8 */
+	if (rst->id == RESET_TWSI8)
+		return 0;
+
+	spacemit_reset_set(rst, rst->id, assert);
+	return 0;
+}
+
+static int spacemit_reset_assert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, true);
+}
+
+static int spacemit_reset_deassert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, false);
+}
+
+static int spacemit_k1_reset_probe(struct udevice *dev)
+{
+	struct spacemit_reset *reset = dev_get_priv(dev);
+
+	reset->io_base.mpmu_base = (void *)dev_remap_addr_index(dev, 0);
+	if (!reset->io_base.mpmu_base) {
+		pr_err("failed to map mpmu registers\n");
+		goto out;
+	}
+
+	reset->io_base.apmu_base = (void *)dev_remap_addr_index(dev, 1);
+	if (!reset->io_base.apmu_base) {
+		pr_err("failed to map apmu registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbc_base = (void *)dev_remap_addr_index(dev, 2);
+	if (!reset->io_base.apbc_base) {
+		pr_err("failed to map apbc registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbs_base = (void *)dev_remap_addr_index(dev, 3);
+	if (!reset->io_base.apbs_base) {
+		pr_err("failed to map apbs registers\n");
+		goto out;
+	}
+
+	reset->io_base.ciu_base = (void *)dev_remap_addr_index(dev, 4);
+	if (!reset->io_base.ciu_base) {
+		pr_err("failed to map ciu registers\n");
+		goto out;
+	}
+
+	reset->io_base.dciu_base = (void *)dev_remap_addr_index(dev, 5);
+	if (!reset->io_base.dciu_base) {
+		pr_err("failed to map dragon ciu registers\n");
+		goto out;
+	}
+
+	reset->io_base.ddrc_base = (void *)dev_remap_addr_index(dev, 6);
+	if (!reset->io_base.ddrc_base) {
+		pr_err("failed to map ddrc registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbc2_base = (void *)dev_remap_addr_index(dev, 7);
+	if (!reset->io_base.apbc2_base) {
+		pr_err("failed to map apbc2 registers\n");
+		goto out;
+	}
+
+	reset->signals = k1_reset_signals;
+
+out:
+	return 0;
+}
+
+const struct reset_ops k1_reset_ops = {
+	.rst_assert = spacemit_reset_assert,
+	.rst_deassert = spacemit_reset_deassert,
+};
+
+static const struct udevice_id k1_reset_ids[] = {
+	{ .compatible = "spacemit,k1-reset", },
+	{},
+};
+
+U_BOOT_DRIVER(k1_reset) = {
+	.name		= "spacemit,k1-reset",
+	.id		= UCLASS_RESET,
+	.ops		= &k1_reset_ops,
+	.of_match	= k1_reset_ids,
+	.probe		= spacemit_k1_reset_probe,
+	.priv_auto	= sizeof(struct spacemit_reset),
+};
diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c
index f790d3b60f9..aab602c5ed0 100644
--- a/drivers/rng/msm_rng.c
+++ b/drivers/rng/msm_rng.c
@@ -44,6 +44,11 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len)
 	u32 *retdata = data;
 	size_t maxsize;
 	u32 val;
+	int ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
 
 	/* calculate max size bytes to transfer back to caller */
 	maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
@@ -66,6 +71,8 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len)
 			break;
 	} while (currsize < maxsize);
 
+	clk_disable(&priv->clk);
+
 	return 0;
 }
 
@@ -76,7 +83,7 @@ static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
 	if (enable) {
 		/* Enable PRNG only if it is not already enabled */
 		val = readl_relaxed(priv->base + PRNG_CONFIG);
-		if (val & PRNG_CONFIG_HW_ENABLE) {
+		if (!(val & PRNG_CONFIG_HW_ENABLE)) {
 			val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
 			val &= ~PRNG_LFSR_CFG_MASK;
 			val |= PRNG_LFSR_CFG_CLOCKS;
@@ -118,7 +125,9 @@ static int msm_rng_probe(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
-	return msm_rng_enable(priv, 1);
+	ret = msm_rng_enable(priv, 1);
+	clk_disable(&priv->clk);
+	return ret;
 }
 
 static int msm_rng_remove(struct udevice *dev)
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index 77a1558db68..cc0491bc3c8 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -63,7 +63,7 @@ static int sandbox_serial_probe(struct udevice *dev)
 
 	if (state->term_raw != STATE_TERM_RAW)
 		disable_ctrlc(1);
-	membuff_init(&priv->buf, priv->serial_buf, sizeof(priv->serial_buf));
+	membuf_init(&priv->buf, priv->serial_buf, sizeof(priv->serial_buf));
 
 	return 0;
 }
@@ -138,15 +138,15 @@ static int sandbox_serial_pending(struct udevice *dev, bool input)
 		return 0;
 
 	os_usleep(100);
-	avail = membuff_putraw(&priv->buf, 100, false, &data);
+	avail = membuf_putraw(&priv->buf, 100, false, &data);
 	if (!avail)
 		return 1;	/* buffer full */
 
 	count = os_read(0, data, avail);
 	if (count > 0)
-		membuff_putraw(&priv->buf, count, true, &data);
+		membuf_putraw(&priv->buf, count, true, &data);
 
-	return membuff_avail(&priv->buf);
+	return membuf_avail(&priv->buf);
 }
 
 static int sandbox_serial_getc(struct udevice *dev)
@@ -156,7 +156,7 @@ static int sandbox_serial_getc(struct udevice *dev)
 	if (!sandbox_serial_pending(dev, true))
 		return -EAGAIN;	/* buffer empty */
 
-	return membuff_getbyte(&priv->buf);
+	return membuf_getbyte(&priv->buf);
 }
 
 #ifdef CONFIG_DEBUG_UART_SANDBOX
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index c5fd740be4d..28f4435d01d 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
  * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
  */
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <watchdog.h>
@@ -312,7 +313,17 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 static int mxc_serial_probe(struct udevice *dev)
 {
 	struct mxc_serial_plat *plat = dev_get_plat(dev);
+#if CONFIG_IS_ENABLED(CLK_CCF)
+	int ret;
 
+	ret = clk_get_bulk(dev, &plat->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&plat->clks);
+	if (ret)
+		return ret;
+#endif
 	_mxc_serial_init(plat->reg, plat->use_dte);
 
 	return 0;
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index a3acca4d394..b34cbd08e07 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -18,8 +18,12 @@ struct soc_ti_k3_plat {
 static const char *get_family_string(u32 idreg)
 {
 	const char *family;
+	u32 jtag_dev_id;
+	u32 pkg;
 	u32 soc;
 
+	jtag_dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+
 	soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
 	switch (soc) {
@@ -51,8 +55,16 @@ static const char *get_family_string(u32 idreg)
 		family = "J722S";
 		break;
 	case JTAG_ID_PARTNO_J784S4:
-		family = "J784S4";
-		break;
+		{
+			/* Keep default family as J784S4 */
+			family = "J784S4";
+
+			pkg = (jtag_dev_id & JTAG_DEV_J742S2_PKG_MASK) >> JTAG_DEV_J742S2_PKG_SHIFT;
+			if (pkg == JTAG_ID_PKG_J742S2)
+				family = "J742S2";
+
+			break;
+		}
 	default:
 		family = "Unknown Silicon";
 	};
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 121194e4418..475540ffac7 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -242,7 +242,6 @@ config SYSRESET_RAA215300
 
 config SYSRESET_QCOM_PSHOLD
 	bool "Support sysreset for Qualcomm SoCs via PSHOLD"
-	depends on ARCH_IPQ40XX
 	help
 	  Add support for the system reboot on Qualcomm SoCs via PSHOLD.
 
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e5a383407a2..477ecd02098 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1631,8 +1631,25 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
 		return dwc3_find_ep(gadget, "ep1in");
 	if (usb_endpoint_is_bulk_out(desc))
 		return dwc3_find_ep(gadget, "ep2out");
-	if (usb_endpoint_is_int_in(desc))
+	if (usb_endpoint_is_int_in(desc)) {
+		/*
+		 * Special workaround for NXP UUU tool in SPL.
+		 *
+		 * The tool excepts the interrupt-in endpoint to be ep1in,
+		 * otherwise it crashes. This is a result of the previous
+		 * hard-coded EP setup in drivers/usb/gadget/epautoconf.c
+		 * which did special-case EP allocation for SPL builds,
+		 * and which was since converted to this callback, but
+		 * without the special-case EP allocation in SPL part.
+		 *
+		 * This reinstates the SPL part in an isolated manner,
+		 * only for NXP iMX SoCs, only for SPL builds, and only
+		 * for the ep1in interrupt-in endpoint.
+		 */
+		if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD))
+			return dwc3_find_ep(gadget, "ep1in");
 		return dwc3_find_ep(gadget, "ep3in");
+	}
 
 	return NULL;
 }
diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c
index db769883ba3..5ed8c2c799a 100644
--- a/drivers/usb/emul/sandbox_keyb.c
+++ b/drivers/usb/emul/sandbox_keyb.c
@@ -38,7 +38,7 @@ enum {
  *
  */
 struct sandbox_keyb_priv {
-	struct membuff in;
+	struct membuf in;
 };
 
 struct sandbox_keyb_plat {
@@ -167,7 +167,7 @@ int sandbox_usb_keyb_add_string(struct udevice *dev,
 	struct sandbox_keyb_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = membuff_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE);
+	ret = membuf_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE);
 	if (ret != USB_KBD_BOOT_REPORT_SIZE)
 		return -ENOSPC;
 
@@ -194,7 +194,7 @@ static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev,
 	if (length < USB_KBD_BOOT_REPORT_SIZE)
 		return 0;
 
-	membuff_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE);
+	membuf_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE);
 
 	return 0;
 }
@@ -220,7 +220,7 @@ static int sandbox_keyb_probe(struct udevice *dev)
 	struct sandbox_keyb_priv *priv = dev_get_priv(dev);
 
 	/* Provide an 80 character keyboard buffer */
-	return membuff_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE);
+	return membuf_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE);
 }
 
 static const struct dm_usb_ops sandbox_usb_keyb_ops = {
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index a5263dfbff9..df607303616 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -700,6 +700,12 @@ config I2C_EDID
 	help
 	   This enables library for accessing EDID data from an LCD panel.
 
+config I2C_EDID_STANDARD
+	bool "Enable standard timings EDID library expansion"
+	depends on I2C_EDID
+	help
+	   This enables standard timings expansion for EDID data from an LCD panel.
+
 config DISPLAY
 	bool "Enable Display support"
 	depends on DM
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
index 21c5a043e02..be53034bd3d 100644
--- a/drivers/video/bridge/Kconfig
+++ b/drivers/video/bridge/Kconfig
@@ -9,7 +9,7 @@ config VIDEO_BRIDGE
 
 config VIDEO_BRIDGE_PARADE_DP501
 	bool "Support Parade DP501 DP & DVI/HDMI dual mode transmitter"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select DM_I2C
 	help
 	  The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It
@@ -46,14 +46,14 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345
 
 config VIDEO_BRIDGE_SOLOMON_SSD2825
 	bool "Solomon SSD2825 bridge driver"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_MIPI_DSI
 	help
-	  Solomon SSD2824 SPI RGB-DSI bridge driver wrapped into panel uClass.
+	  Solomon SSD2824 SPI RGB-DSI bridge driver.
 
 config VIDEO_BRIDGE_TOSHIBA_TC358768
 	bool "Support Toshiba TC358768 MIPI DSI bridge"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_MIPI_DSI
 	select DM_I2C
 	help
diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c
index 095e3e71fed..9937cfe095b 100644
--- a/drivers/video/bridge/dp501.c
+++ b/drivers/video/bridge/dp501.c
@@ -9,6 +9,7 @@
 #include <log.h>
 #include <backlight.h>
 #include <panel.h>
+#include <video_bridge.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <power/regulator.h>
@@ -206,7 +207,6 @@ struct dp501_priv {
 	struct udevice *chip2;
 
 	struct udevice *vdd;
-	struct gpio_desc reset_gpio;
 	struct gpio_desc enable_gpio;
 };
 
@@ -484,16 +484,19 @@ static int dp501_panel_timings(struct udevice *dev,
 	return 0;
 }
 
-static void dp501_hw_init(struct dp501_priv *priv)
+static void dp501_hw_init(struct udevice *dev)
 {
-	dm_gpio_set_value(&priv->reset_gpio, 1);
+	struct dp501_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	dm_gpio_set_value(&uc_priv->reset, 1);
 
 	regulator_set_enable_if_allowed(priv->vdd, 1);
 	dm_gpio_set_value(&priv->enable_gpio, 1);
 
 	udelay(100);
 
-	dm_gpio_set_value(&priv->reset_gpio, 0);
+	dm_gpio_set_value(&uc_priv->reset, 0);
 	mdelay(80);
 }
 
@@ -521,14 +524,6 @@ static int dp501_setup(struct udevice *dev)
 	}
 
 	/* get gpios */
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_debug("%s: Could not decode reset-gpios (%d)\n",
-			  __func__, ret);
-		return ret;
-	}
-
 	ret = gpio_request_by_name(dev, "enable-gpios", 0,
 				   &priv->enable_gpio, GPIOD_IS_OUT);
 	if (ret) {
@@ -544,7 +539,7 @@ static int dp501_setup(struct udevice *dev)
 		return ret;
 	}
 
-	dp501_hw_init(priv);
+	dp501_hw_init(dev);
 
 	/* get EDID */
 	return panel_get_display_timing(priv->panel, &priv->timing);
@@ -558,8 +553,8 @@ static int dp501_probe(struct udevice *dev)
 	return dp501_setup(dev);
 }
 
-struct panel_ops dp501_ops = {
-	.enable_backlight	= dp501_attach,
+static const struct video_bridge_ops dp501_ops = {
+	.attach			= dp501_attach,
 	.set_backlight		= dp501_set_backlight,
 	.get_display_timing	= dp501_panel_timings,
 };
@@ -571,7 +566,7 @@ static const struct udevice_id dp501_ids[] = {
 
 U_BOOT_DRIVER(dp501) = {
 	.name		= "dp501",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= dp501_ids,
 	.ops		= &dp501_ops,
 	.probe		= dp501_probe,
diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c
index f978021c860..a307993377c 100644
--- a/drivers/video/bridge/ssd2825.c
+++ b/drivers/video/bridge/ssd2825.c
@@ -5,12 +5,15 @@
 
 #include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <log.h>
 #include <misc.h>
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
+#include <video_bridge.h>
 #include <panel.h>
+#include <power/regulator.h>
 #include <spi.h>
 #include <linux/delay.h>
 #include <linux/err.h>
@@ -106,6 +109,10 @@
 #define SSD2825_LP_MIN_CLK		5000 /* KHz */
 #define SSD2825_REF_MIN_CLK		2000 /* KHz */
 
+static const char * const ssd2825_supplies[] = {
+	"dvdd-supply", "avdd-supply", "vddio-supply"
+};
+
 struct ssd2825_bridge_priv {
 	struct mipi_dsi_host host;
 	struct mipi_dsi_device device;
@@ -113,12 +120,16 @@ struct ssd2825_bridge_priv {
 	struct udevice *panel;
 	struct display_timing timing;
 
+	struct udevice *supplies[ARRAY_SIZE(ssd2825_supplies)];
+
 	struct gpio_desc power_gpio;
-	struct gpio_desc reset_gpio;
 
 	struct clk *tx_clk;
 
 	u32 pll_freq_kbps;	/* PLL in kbps */
+
+	u32 hzd;		/* HS Zero Delay in ns */
+	u32 hpd;		/* HS Prepare Delay is ns */
 };
 
 static int ssd2825_spi_write(struct udevice *dev, int reg,
@@ -231,7 +242,6 @@ static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host,
 				       const struct mipi_dsi_msg *msg)
 {
 	struct udevice *dev = (struct udevice *)host->dev;
-	u8 buf = *(u8 *)msg->tx_buf;
 	u16 config;
 	int ret;
 
@@ -260,15 +270,6 @@ static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host,
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 	ssd2825_write_dsi(dev, msg->tx_buf, msg->tx_len);
 
-	if (buf == MIPI_DCS_SET_DISPLAY_ON) {
-		ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
-				SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
-				SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
-				SSD2825_CONF_REG_EOT);
-		ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
-		ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
-	}
-
 	return 0;
 }
 
@@ -312,9 +313,14 @@ static void ssd2825_setup_pll(struct udevice *dev)
 	struct mipi_dsi_device *device = &priv->device;
 	struct display_timing *dt = &priv->timing;
 	u16 pll_config, lp_div;
+	u32 nibble_delay, nibble_freq_khz;
 	u32 pclk_mult, tx_freq_khz, pd_lines;
+	u8 hzd, hpd;
 
 	tx_freq_khz = clk_get_rate(priv->tx_clk) / 1000;
+	if (!tx_freq_khz || tx_freq_khz < 0)
+		tx_freq_khz = SSD2825_REF_MIN_CLK;
+
 	pd_lines = mipi_dsi_pixel_format_to_bpp(device->format);
 	pclk_mult = pd_lines / device->lanes + 1;
 
@@ -324,12 +330,19 @@ static void ssd2825_setup_pll(struct udevice *dev)
 
 	lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8);
 
+	/* nibble_delay in nanoseconds */
+	nibble_freq_khz = priv->pll_freq_kbps / 4;
+	nibble_delay = 1000 * 1000 / nibble_freq_khz;
+
+	hzd = priv->hzd / nibble_delay;
+	hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay;
+
 	/* Disable PLL */
 	ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0000);
 	ssd2825_write_register(dev, SSD2825_LINE_CTRL_REG, 0x0001);
 
 	/* Set delays */
-	ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, 0x2103);
+	ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd);
 
 	/* Set PLL coeficients */
 	ssd2825_write_register(dev, SSD2825_PLL_CONFIGURATION_REG, pll_config);
@@ -343,11 +356,30 @@ static void ssd2825_setup_pll(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 }
 
-static int ssd2825_bridge_enable_panel(struct udevice *dev)
+static int ssd2825_bridge_attach(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct display_timing *dt = &priv->timing;
+	u8 pixel_format;
+	int ret;
+
+	/* Set pixel format */
+	switch (device->format) {
+	case MIPI_DSI_FMT_RGB565:
+		pixel_format = 0x00;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		pixel_format = 0x01;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		pixel_format = 0x02;
+		break;
+	case MIPI_DSI_FMT_RGB888:
+	default:
+		pixel_format = 0x03;
+		break;
+	}
 
 	/* Perform SW reset */
 	ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100);
@@ -367,7 +399,7 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_6,
 			       SSD2825_HSYNC_HIGH | SSD2825_VSYNC_HIGH |
 			       SSD2825_PCKL_HIGH | SSD2825_NON_BURST |
-			       (3 - device->format));
+			       pixel_format);
 	ssd2825_write_register(dev, SSD2825_LANE_CONFIGURATION_REG,
 			       device->lanes - 1);
 	ssd2825_write_register(dev, SSD2825_TEST_REG, 0x0004);
@@ -384,7 +416,18 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 
 	/* Perform panel setup */
-	return panel_enable_backlight(priv->panel);
+	ret = panel_enable_backlight(priv->panel);
+	if (ret)
+		return ret;
+
+	ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
+			       SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
+			       SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
+			       SSD2825_CONF_REG_EOT);
+	ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
+	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
+
+	return 0;
 }
 
 static int ssd2825_bridge_set_panel(struct udevice *dev, int percent)
@@ -407,7 +450,8 @@ static int ssd2825_bridge_panel_timings(struct udevice *dev,
 static int ssd2825_bridge_hw_init(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
-	int ret;
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+	int i, ret;
 
 	ret = clk_prepare_enable(priv->tx_clk);
 	if (ret) {
@@ -416,25 +460,28 @@ static int ssd2825_bridge_hw_init(struct udevice *dev)
 		return ret;
 	}
 
-	ret = dm_gpio_set_value(&priv->power_gpio, 1);
-	if (ret) {
-		log_debug("%s: error changing power-gpios (%d)\n",
-			  __func__, ret);
-		return ret;
+	/* enable supplies */
+	for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+		ret = regulator_set_enable_if_allowed(priv->supplies[i], 1);
+		if (ret) {
+			log_debug("%s: cannot enable %s %d\n", __func__,
+				  ssd2825_supplies[i], ret);
+			return ret;
+		}
 	}
 	mdelay(10);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&uc_priv->reset, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error entering reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(10);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	ret = dm_gpio_set_value(&uc_priv->reset, 0);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error exiting reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -443,13 +490,33 @@ static int ssd2825_bridge_hw_init(struct udevice *dev)
 	return 0;
 }
 
+static int ssd2825_bridge_get_panel(struct udevice *dev)
+{
+	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+						  &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
 static int ssd2825_bridge_probe(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
 	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct mipi_dsi_panel_plat *mipi_plat;
-	int ret;
+	int i, ret;
 
 	ret = spi_claim_bus(slave);
 	if (ret) {
@@ -457,10 +524,9 @@ static int ssd2825_bridge_probe(struct udevice *dev)
 		return ret;
 	}
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
-					   "panel", &priv->panel);
+	ret = ssd2825_bridge_get_panel(dev);
 	if (ret) {
-		log_err("cannot get panel: ret=%d\n", ret);
+		log_debug("%s: panel not found, ret %d\n", __func__, ret);
 		return ret;
 	}
 
@@ -477,33 +543,33 @@ static int ssd2825_bridge_probe(struct udevice *dev)
 	device->format = mipi_plat->format;
 	device->mode_flags = mipi_plat->mode_flags;
 
-	/* get panel gpios */
-	ret = gpio_request_by_name(dev, "power-gpios", 0,
-				   &priv->power_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_err("could not decode power-gpios (%d)\n", ret);
-		return ret;
-	}
-
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_err("could not decode reset-gpios (%d)\n", ret);
-		return ret;
+	/* get supplies */
+	for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+		ret = device_get_supply_regulator(dev, ssd2825_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  ssd2825_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
 	}
 
 	/* get clk */
-	priv->tx_clk = devm_clk_get(dev, "tx_clk");
+	priv->tx_clk = devm_clk_get_optional(dev, NULL);
 	if (IS_ERR(priv->tx_clk)) {
 		log_err("cannot get tx_clk: %ld\n", PTR_ERR(priv->tx_clk));
 		return PTR_ERR(priv->tx_clk);
 	}
 
+	priv->hzd = dev_read_u32_default(dev, "solomon,hs-zero-delay-ns", 133);
+	priv->hpd = dev_read_u32_default(dev, "solomon,hs-prep-delay-ns", 40);
+
 	return ssd2825_bridge_hw_init(dev);
 }
 
-static const struct panel_ops ssd2825_bridge_ops = {
-	.enable_backlight	= ssd2825_bridge_enable_panel,
+static const struct video_bridge_ops ssd2825_bridge_ops = {
+	.attach			= ssd2825_bridge_attach,
 	.set_backlight		= ssd2825_bridge_set_panel,
 	.get_display_timing	= ssd2825_bridge_panel_timings,
 };
@@ -515,9 +581,10 @@ static const struct udevice_id ssd2825_bridge_ids[] = {
 
 U_BOOT_DRIVER(ssd2825) = {
 	.name		= "ssd2825",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= ssd2825_bridge_ids,
 	.ops		= &ssd2825_bridge_ops,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= ssd2825_bridge_probe,
 	.priv_auto	= sizeof(struct ssd2825_bridge_priv),
 };
diff --git a/drivers/video/bridge/tc358768.c b/drivers/video/bridge/tc358768.c
index 19b6ca29d3e..358004f30f2 100644
--- a/drivers/video/bridge/tc358768.c
+++ b/drivers/video/bridge/tc358768.c
@@ -6,12 +6,14 @@
 
 #include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <i2c.h>
 #include <log.h>
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
 #include <panel.h>
+#include <video_bridge.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
@@ -122,6 +124,10 @@
 #define NANO	1000000000UL
 #define PICO	1000000000000ULL
 
+static const char * const tc358768_supplies[] = {
+	"vddc-supply", "vddmipi-supply", "vddio-supply"
+};
+
 struct tc358768_priv {
 	struct mipi_dsi_host host;
 	struct mipi_dsi_device device;
@@ -129,9 +135,7 @@ struct tc358768_priv {
 	struct udevice *panel;
 	struct display_timing timing;
 
-	struct udevice *vddc;
-	struct udevice *vddmipi;
-	struct udevice *vddio;
+	struct udevice *supplies[ARRAY_SIZE(tc358768_supplies)];
 
 	struct clk *refclk;
 
@@ -265,25 +269,27 @@ static void tc358768_sw_reset(struct udevice *dev)
 	tc358768_write(dev, TC358768_SYSCTL, 0);
 }
 
-static void tc358768_hw_enable(struct tc358768_priv *priv)
+static void tc358768_hw_enable(struct udevice *dev)
 {
+	struct tc358768_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
 	int ret;
 
 	ret = clk_prepare_enable(priv->refclk);
 	if (ret)
 		log_debug("%s: error enabling refclk (%d)\n", __func__, ret);
 
-	ret = regulator_set_enable_if_allowed(priv->vddc, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[0], true);
 	if (ret)
 		log_debug("%s: error enabling vddc (%d)\n", __func__, ret);
 
-	ret = regulator_set_enable_if_allowed(priv->vddmipi, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[1], true);
 	if (ret)
 		log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret);
 
 	mdelay(10);
 
-	ret = regulator_set_enable_if_allowed(priv->vddio, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[2], true);
 	if (ret)
 		log_debug("%s: error enabling vddio (%d)\n", __func__, ret);
 
@@ -293,7 +299,7 @@ static void tc358768_hw_enable(struct tc358768_priv *priv)
 	 * The RESX is active low (GPIO_ACTIVE_LOW).
 	 * DEASSERT (value = 0) the reset_gpio to enable the chip
 	 */
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&uc_priv->reset, 0);
 	if (ret)
 		log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret);
 
@@ -477,7 +483,7 @@ static int tc358768_attach(struct udevice *dev)
 		device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
 	}
 
-	tc358768_hw_enable(priv);
+	tc358768_hw_enable(dev);
 	tc358768_sw_reset(dev);
 
 	tc358768_setup_pll(dev);
@@ -874,12 +880,33 @@ static int tc358768_panel_timings(struct udevice *dev,
 	return 0;
 }
 
+static int tc358768_get_panel(struct udevice *dev)
+{
+	struct tc358768_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+						  &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
 static int tc358768_setup(struct udevice *dev)
 {
 	struct tc358768_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct mipi_dsi_panel_plat *mipi_plat;
-	int ret;
+	int i, ret;
 
 	/* The bridge uses 16 bit registers */
 	ret = i2c_set_chip_offset_len(dev, 2);
@@ -889,11 +916,10 @@ static int tc358768_setup(struct udevice *dev)
 		return ret;
 	}
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
-					   "panel", &priv->panel);
+	ret = tc358768_get_panel(dev);
 	if (ret) {
-		log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret);
-		return log_ret(ret);
+		log_debug("%s: panel not found, ret %d\n", __func__, ret);
+		return ret;
 	}
 
 	panel_get_display_timing(priv->panel, &priv->timing);
@@ -913,44 +939,26 @@ static int tc358768_setup(struct udevice *dev)
 	priv->dsi_lanes = device->lanes;
 
 	/* get regulators */
-	ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc);
-	if (ret) {
-		log_debug("%s: vddc regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
-	}
-
-	ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi);
-	if (ret) {
-		log_debug("%s: vddmipi regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
-	}
-
-	ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
-	if (ret) {
-		log_debug("%s: vddio regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
+	for (i = 0; i < ARRAY_SIZE(tc358768_supplies); i++) {
+		ret = device_get_supply_regulator(dev, tc358768_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  tc358768_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
 	}
 
 	/* get clk */
-	priv->refclk = devm_clk_get(dev, "refclk");
+	priv->refclk = devm_clk_get(dev, NULL);
 	if (IS_ERR(priv->refclk)) {
 		log_debug("%s: Could not get refclk: %ld\n",
 			  __func__, PTR_ERR(priv->refclk));
 		return PTR_ERR(priv->refclk);
 	}
 
-	/* get gpios */
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
-		return ret;
-	}
-
-	dm_gpio_set_value(&priv->reset_gpio, 1);
+	dm_gpio_set_value(&uc_priv->reset, 1);
 
 	return 0;
 }
@@ -963,8 +971,8 @@ static int tc358768_probe(struct udevice *dev)
 	return tc358768_setup(dev);
 }
 
-struct panel_ops tc358768_ops = {
-	.enable_backlight	= tc358768_attach,
+static const struct video_bridge_ops tc358768_ops = {
+	.attach			= tc358768_attach,
 	.set_backlight		= tc358768_set_backlight,
 	.get_display_timing	= tc358768_panel_timings,
 };
@@ -977,9 +985,10 @@ static const struct udevice_id tc358768_ids[] = {
 
 U_BOOT_DRIVER(tc358768) = {
 	.name		= "tc358768",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= tc358768_ids,
 	.ops		= &tc358768_ops,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= tc358768_probe,
 	.priv_auto	= sizeof(struct tc358768_priv),
 };
diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c
index d4ba4d8b6da..9950ff8bb05 100644
--- a/drivers/video/endeavoru-panel.c
+++ b/drivers/video/endeavoru-panel.c
@@ -117,6 +117,18 @@ static int endeavoru_panel_set_backlight(struct udevice *dev, int percent)
 	struct endeavoru_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
+	/*
+	 * Due to the use of the Tegra DC backlight feature, backlight
+	 * requests MUST NOT be made during probe or earlier. This is
+	 * because it creates a loop, as the backlight is a DC child.
+	 */
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_err("cannot get backlight: ret = %d\n", ret);
+		return ret;
+	}
+
 	ret = backlight_enable(priv->backlight);
 	if (ret)
 		return ret;
@@ -136,13 +148,6 @@ static int endeavoru_panel_of_to_plat(struct udevice *dev)
 	struct endeavoru_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
-					   "backlight", &priv->backlight);
-	if (ret) {
-		log_err("cannot get backlight: ret = %d\n", ret);
-		return ret;
-	}
-
 	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
 					   "vdd-supply", &priv->vdd);
 	if (ret) {
@@ -231,7 +236,7 @@ static int endeavoru_panel_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 2;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return endeavoru_panel_hw_init(dev);
 }
diff --git a/drivers/video/lg-ld070wx3.c b/drivers/video/lg-ld070wx3.c
index 610a06ffe7b..3676e45bc65 100644
--- a/drivers/video/lg-ld070wx3.c
+++ b/drivers/video/lg-ld070wx3.c
@@ -158,7 +158,7 @@ static int lg_ld070wx3_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return lg_ld070wx3_hw_init(dev);
 }
diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c
index 6b51fa0628e..7b87b6bd40b 100644
--- a/drivers/video/lm3533_backlight.c
+++ b/drivers/video/lm3533_backlight.c
@@ -7,6 +7,7 @@
 
 #include <backlight.h>
 #include <dm.h>
+#include <dm/ofnode.h>
 #include <i2c.h>
 #include <log.h>
 #include <linux/delay.h>
@@ -17,56 +18,79 @@
 #define LM3533_BL_MAX_BRIGHTNESS			0xFF
 
 #define LM3533_SINK_OUTPUT_CONFIG_1			0x10
-#define LM3533_CONTROL_BANK_A_PWM			0x14
+#define LM3533_CONTROL_PWM_BASE				0x14
+#define   PWM_MAX					GENMASK(5, 0)
 #define LM3533_CONTROL_BANK_AB_BRIGHTNESS		0x1A
-#define LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT		0x1F
+#define LM3533_CONTROL_FULLSCALE_CURRENT_BASE		0x1F
+#define   MAX_CURRENT_MIN				5000
+#define   MAX_CURRENT_MAX				29800
+#define   MAX_CURRENT_STEP				800
 #define LM3533_CONTROL_BANK_ENABLE			0x27
 #define LM3533_OVP_FREQUENCY_PWM_POLARITY		0x2C
+#define   BOOST_OVP_MASK				GENMASK(2, 1)
+#define   BOOST_OVP_SHIFT				1
+#define   BOOST_FREQ_MASK				BIT(0)
+#define   BOOST_FREQ_SHIFT				0
 #define LM3533_BRIGHTNESS_REGISTER_A			0x40
 
+#define LM3533_BOOST_OVP_16V				16000000UL
+#define LM3533_BOOST_FREQ_500KHZ			500000UL
+
 struct lm3533_backlight_priv {
 	struct gpio_desc enable_gpio;
 	u32 def_bl_lvl;
+
+	/* Core */
+	u32 boost_ovp;
+	u32 boost_freq;
+
+	/* Backlight */
+	u32 reg;
+	u16 max_current;		/* 5000 - 29800 uA (800 uA step) */
+	u8 pwm;				/* 0 - 0x3f */
+	bool linear;
+	bool hvled;
 };
 
 static int lm3533_backlight_enable(struct udevice *dev)
 {
 	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+	u8 val, id = priv->reg;
 	int ret;
 
-	dm_gpio_set_value(&priv->enable_gpio, 1);
-	mdelay(5);
+	if (priv->linear) {
+		ret = dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS,
+					BIT(2 * id + 1), BIT(2 * id + 1));
+		if (ret)
+			return ret;
+	}
 
-	/* HVLED 1 & 2 are controlled by Bank A */
-	ret = dm_i2c_reg_write(dev, LM3533_SINK_OUTPUT_CONFIG_1, 0x00);
-	if (ret)
-		return ret;
+	if (priv->hvled) {
+		ret = dm_i2c_reg_clrset(dev, LM3533_SINK_OUTPUT_CONFIG_1,
+					BIT(0) | BIT(1), id | id << 1);
+		if (ret)
+			return ret;
+	}
 
-	/* PWM input is disabled for CABC */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_PWM, 0x00);
-	if (ret)
-		return ret;
+	/* Set current */
+	if (priv->max_current < MAX_CURRENT_MIN || priv->max_current > MAX_CURRENT_MAX)
+		return -EINVAL;
 
-	/* Linear & Control Bank A is configured for register Current control */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS, 0x02);
+	val = (priv->max_current - MAX_CURRENT_MIN) / MAX_CURRENT_STEP;
+	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_FULLSCALE_CURRENT_BASE + id, val);
 	if (ret)
 		return ret;
 
-	/* Full-Scale Current (20.2mA) */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT, 0x13);
-	if (ret)
-		return ret;
+	/* Set PWM mask */
+	if (priv->pwm > PWM_MAX)
+		return -EINVAL;
 
-	/* Control Bank A is enable */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_ENABLE, 0x01);
+	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_PWM_BASE + id, priv->pwm);
 	if (ret)
 		return ret;
 
-	ret = dm_i2c_reg_write(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY, 0x0A);
-	if (ret)
-		return ret;
-
-	return 0;
+	/* Enable Control Bank */
+	return dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_ENABLE, BIT(id), BIT(id));
 }
 
 static int lm3533_backlight_set_brightness(struct udevice *dev, int percent)
@@ -92,6 +116,56 @@ static int lm3533_backlight_set_brightness(struct udevice *dev, int percent)
 	return 0;
 }
 
+static int lm3533_backlight_of_to_plat(struct udevice *dev)
+{
+	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+	ofnode child;
+	int ret;
+
+	ret = gpio_request_by_name(dev, "enable-gpios", 0,
+				   &priv->enable_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("Could not decode enable-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	priv->boost_ovp = dev_read_u32_default(dev, "ti,boost-ovp-microvolt",
+					       LM3533_BOOST_OVP_16V);
+
+	/* boost_ovp is defined in microvolts, convert to enum value */
+	priv->boost_ovp = priv->boost_ovp / (8 * 1000 * 1000) - 2;
+
+	priv->boost_freq = dev_read_u32_default(dev, "ti,boost-freq-hz",
+						LM3533_BOOST_FREQ_500KHZ);
+
+	/* boost_freq is defined in Hz, convert to enum value */
+	priv->boost_freq = priv->boost_freq / (500 * 1000) - 1;
+
+	/* Backlight is one of children but has no dedicated driver */
+	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+		if (ofnode_device_is_compatible(child, "ti,lm3533-backlight")) {
+			const char *node_name = ofnode_get_name(child);
+
+			if (!strcmp(&node_name[10], "1"))
+				priv->reg = 1;
+			else
+				priv->reg = 0;
+
+			priv->max_current = ofnode_read_u32_default(child, "ti,max-current-microamp",
+								    5000);
+			priv->pwm = ofnode_read_u32_default(child, "ti,pwm-config-mask", 0);
+
+			priv->def_bl_lvl = ofnode_read_u32_default(child, "default-brightness",
+								   LM3533_BL_MAX_BRIGHTNESS);
+
+			priv->linear = ofnode_read_bool(child, "ti,linear-mapping-mode");
+			priv->hvled = ofnode_read_bool(child, "ti,hardware-controlled");
+		}
+	}
+
+	return 0;
+}
+
 static int lm3533_backlight_probe(struct udevice *dev)
 {
 	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
@@ -100,15 +174,22 @@ static int lm3533_backlight_probe(struct udevice *dev)
 	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
 		return -EPROTONOSUPPORT;
 
-	ret = gpio_request_by_name(dev, "enable-gpios", 0,
-				   &priv->enable_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->enable_gpio, 1);
+	mdelay(5);
+
+	ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+				BOOST_FREQ_MASK, priv->boost_freq << BOOST_FREQ_SHIFT);
 	if (ret) {
-		log_err("Could not decode enable-gpios (%d)\n", ret);
+		log_debug("%s: freq config failed %d\n", __func__, ret);
 		return ret;
 	}
 
-	priv->def_bl_lvl = dev_read_u32_default(dev, "default-brightness-level",
-						LM3533_BL_MAX_BRIGHTNESS);
+	ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+				BOOST_OVP_MASK, priv->boost_ovp << BOOST_OVP_SHIFT);
+	if (ret) {
+		log_debug("%s: ovp config failed %d\n", __func__, ret);
+		return ret;
+	}
 
 	return 0;
 }
@@ -127,6 +208,7 @@ U_BOOT_DRIVER(lm3533_backlight) = {
 	.name		= "lm3533_backlight",
 	.id		= UCLASS_PANEL_BACKLIGHT,
 	.of_match	= lm3533_backlight_ids,
+	.of_to_plat	= lm3533_backlight_of_to_plat,
 	.probe		= lm3533_backlight_probe,
 	.ops		= &lm3533_backlight_ops,
 	.priv_auto	= sizeof(struct lm3533_backlight_priv),
diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c
index a3697bce5ee..ef6fab1e953 100644
--- a/drivers/video/renesas-r61307.c
+++ b/drivers/video/renesas-r61307.c
@@ -254,17 +254,17 @@ static int renesas_r61307_hw_init(struct udevice *dev)
 		return ret;
 	}
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 	if (ret) {
-		log_debug("%s: changing reset-gpio failed (%d)\n",
+		log_debug("%s: entering reset failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(5);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
 	if (ret) {
-		log_debug("%s: changing reset-gpio failed (%d)\n",
+		log_debug("%s: exiting reset failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -281,7 +281,8 @@ static int renesas_r61307_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			   MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
 
 	return renesas_r61307_hw_init(dev);
 }
@@ -294,7 +295,7 @@ static const struct panel_ops renesas_r61307_ops = {
 
 static const struct udevice_id renesas_r61307_ids[] = {
 	{ .compatible = "koe,tx13d100vm0eaa" },
-	{ .compatible = "hitachi,tx13d100vm0eaa" },
+	{ .compatible = "hit,tx13d100vm0eaa" },
 	{ }
 };
 
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index 9861c3fef11..0954b04b62e 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -32,9 +32,11 @@
 #define R69328_POWER_SET	0xD1
 
 struct renesas_r69328_priv {
+	struct udevice *vdd;
+	struct udevice *vddio;
+
 	struct udevice *backlight;
 
-	struct gpio_desc enable_gpio;
 	struct gpio_desc reset_gpio;
 };
 
@@ -159,10 +161,15 @@ static int renesas_r69328_of_to_plat(struct udevice *dev)
 		return ret;
 	}
 
-	ret = gpio_request_by_name(dev, "enable-gpios", 0,
-				   &priv->enable_gpio, GPIOD_IS_OUT);
+	ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
 	if (ret) {
-		log_err("could not decode enable-gpios (%d)\n", ret);
+		log_err("Cannot get vdd-supply: ret = %d\n", ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
+	if (ret) {
+		log_err("Cannot get vddio-supply: ret = %d\n", ret);
 		return ret;
 	}
 
@@ -181,25 +188,32 @@ static int renesas_r69328_hw_init(struct udevice *dev)
 	struct renesas_r69328_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = dm_gpio_set_value(&priv->enable_gpio, 1);
+	ret = regulator_set_enable_if_allowed(priv->vddio, 1);
 	if (ret) {
-		log_debug("%s: error changing enable-gpios (%d)\n",
+		log_debug("%s: enabling vddio-supply failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(5);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = regulator_set_enable_if_allowed(priv->vdd, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: enabling vdd-supply failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
-	mdelay(5);
 
 	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error entering reset (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	mdelay(5);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error exiting reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -216,7 +230,8 @@ static int renesas_r69328_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			   MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
 
 	return renesas_r69328_hw_init(dev);
 }
diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c
index 5e6c11c4be3..1efc9fca610 100644
--- a/drivers/video/samsung-ltl106hl02.c
+++ b/drivers/video/samsung-ltl106hl02.c
@@ -129,7 +129,7 @@ static int samsung_ltl106hl02_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return samsung_ltl106hl02_hw_init(dev);
 }
diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c
index 5d8453fd796..4fdf0da8a94 100644
--- a/drivers/video/sharp-lq101r1sx01.c
+++ b/drivers/video/sharp-lq101r1sx01.c
@@ -255,6 +255,7 @@ static int sharp_lq101r1sx01_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_LPM;
 
 	return sharp_lq101r1sx01_hw_init(dev);
 }
diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
index f5c4843e119..598f9ea1f21 100644
--- a/drivers/video/tegra20/Kconfig
+++ b/drivers/video/tegra20/Kconfig
@@ -1,6 +1,11 @@
+config HOST1X_TEGRA
+	bool "NVIDIA Tegra host1x BUS support"
+	depends on SIMPLE_BUS
+
 config VIDEO_TEGRA20
 	bool "Enable Display Controller support on Tegra20 and Tegra 30"
 	depends on OF_CONTROL
+	select HOST1X_TEGRA
 	help
 	   T20/T30 support video output to an attached LCD panel as well as
 	   other options such as HDMI. Only the LCD is supported in U-Boot.
@@ -9,13 +14,22 @@ config VIDEO_TEGRA20
 
 config VIDEO_DSI_TEGRA30
 	bool "Enable Tegra 30 DSI support"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_TEGRA20
 	select VIDEO_MIPI_DSI
 	help
 	   T30 has native support for DSI panels. This option enables support
 	   for such panels which can be used on endeavoru and tf600t.
 
+config VIDEO_HDMI_TEGRA
+	bool "Enable Tegra HDMI support"
+	depends on VIDEO_BRIDGE && DM_I2C
+	select I2C_EDID
+	select VIDEO_TEGRA20
+	help
+	   Tegra has native support for HDMI. This option enables support
+	   for such connection and can be used for any supported device.
+
 config TEGRA_BACKLIGHT_PWM
 	bool "Enable Tegra DC PWM backlight support"
 	depends on BACKLIGHT
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
index a75aea2a875..78521405749 100644
--- a/drivers/video/tegra20/Makefile
+++ b/drivers/video/tegra20/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
 obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o
 obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 16a2b5281bf..1f43153ff27 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -1,16 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
  */
 
 #include <backlight.h>
 #include <cpu_func.h>
 #include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <fdtdec.h>
 #include <log.h>
 #include <panel.h>
 #include <video.h>
+#include <video_bridge.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -31,7 +34,8 @@ struct tegra_lcd_priv {
 	int height;			/* height in pixels */
 	enum video_log2_bpp log2_bpp;	/* colour depth */
 	struct display_timing timing;
-	struct udevice *panel;
+	struct udevice *panel;		/* Panels attached to RGB */
+	struct udevice *bridge;		/* Bridge linked with DC */
 	struct dc_ctlr *dc;		/* Display controller regmap */
 	const struct tegra_dc_soc_info *soc;
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
@@ -319,11 +323,6 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
 						/ priv->pixel_clock) - 2;
 	log_debug("Display clock %lu, divider %lu\n", rate, priv->scdiv);
 
-	/*
-	 * HOST1X is init by default at 150MHz with PLLC as parent
-	 */
-	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL,
-			       150 * 1000000);
 	clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
 			       rate);
 
@@ -378,11 +377,12 @@ static int tegra_lcd_probe(struct udevice *dev)
 	}
 
 	/* Get shift clock divider from Tegra DSI if used */
-	if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
-	    !strcmp(priv->panel->name, TEGRA_DSI_B)) {
-		struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
+	if (priv->bridge) {
+		if (!strcmp(priv->bridge->driver->name, "tegra_dsi")) {
+			struct tegra_dc_plat *dc_plat = dev_get_plat(priv->bridge);
 
-		priv->scdiv = dc_plat->scdiv;
+			priv->scdiv = dc_plat->scdiv;
+		}
 	}
 
 	/* Clean the framebuffer area */
@@ -395,10 +395,20 @@ static int tegra_lcd_probe(struct udevice *dev)
 		return ret;
 	}
 
-	ret = panel_enable_backlight(priv->panel);
-	if (ret) {
-		log_debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
-		return ret;
+	if (priv->panel) {
+		ret = panel_enable_backlight(priv->panel);
+		if (ret) {
+			log_debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+			return ret;
+		}
+	}
+
+	if (priv->bridge) {
+		ret = video_bridge_attach(priv->bridge);
+		if (ret) {
+			log_debug("%s: Cannot attach bridge, ret=%d\n", __func__, ret);
+			return ret;
+		}
 	}
 
 	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
@@ -413,17 +423,129 @@ static int tegra_lcd_probe(struct udevice *dev)
 	log_debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
 		  plat->size);
 
-	return panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+	if (priv->panel) {
+		ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+		if (ret)
+			return ret;
+	}
+
+	if (priv->bridge) {
+		ret = video_bridge_set_backlight(priv->bridge, BACKLIGHT_DEFAULT);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int tegra_lcd_configure_rgb(struct udevice *dev, ofnode rgb)
+{
+	struct tegra_lcd_priv *priv = dev_get_priv(dev);
+	ofnode remote;
+	int ret;
+
+	/* DC can have only 1 port */
+	remote = ofnode_graph_get_remote_node(rgb, -1, -1);
+
+	ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+	if (!ret)
+		return 0;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &priv->bridge);
+	if (!ret)
+		return 0;
+
+	/* Try legacy method if graph did not work */
+	remote = ofnode_parse_phandle(rgb, "nvidia,panel", 0);
+	if (!ofnode_valid(remote))
+		return -EINVAL;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+	if (ret) {
+		log_debug("%s: Cannot find panel for '%s' (ret=%d)\n",
+			  __func__, dev->name, ret);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote,
+						  &priv->bridge);
+		if (ret) {
+			log_err("%s: Cannot find panel or bridge for '%s' (ret=%d)\n",
+				__func__, dev->name, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int tegra_lcd_configure_internal(struct udevice *dev)
+{
+	struct tegra_lcd_priv *priv = dev_get_priv(dev);
+	struct tegra_dc_plat *dc_plat;
+	ofnode host1x = ofnode_get_parent(dev_ofnode(dev));
+	ofnode node;
+	int ret;
+
+	switch (priv->pipe) {
+	case 0: /* DC0 is usually used for DSI */
+		/* Check for ganged DSI configuration */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node) &&
+			    ofnode_read_bool(node, "nvidia,ganged-mode"))
+				goto exit;
+
+		/* If no master DSI found loop for any active DSI */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node))
+				goto exit;
+
+		log_err("%s: failed to find DSI device for '%s'\n",
+			__func__, dev->name);
+
+		return -ENODEV;
+	case 1: /* DC1 is usually used for HDMI */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "hdmi"))
+				goto exit;
+
+		log_err("%s: failed to find HDMI device for '%s'\n",
+			__func__, dev->name);
+
+		return -ENODEV;
+	default:
+		log_debug("Unsupported DC selection\n");
+		return -EINVAL;
+	}
+
+exit:
+	ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, node, &priv->bridge);
+	if (ret) {
+		log_err("%s: failed to get DSI/HDMI device for '%s' (ret %d)\n",
+			__func__, dev->name, ret);
+		return ret;
+	}
+
+	priv->clk_parent = devm_clk_get(priv->bridge, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get DC clock parent from DSI/HDMI: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
+	}
+
+	dc_plat = dev_get_plat(priv->bridge);
+
+	/* Fill the platform data for internal devices */
+	dc_plat->dev = dev;
+	dc_plat->dc = priv->dc;
+	dc_plat->pipe = priv->pipe;
+
+	return 0;
 }
 
 static int tegra_lcd_of_to_plat(struct udevice *dev)
 {
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
 	struct display_timing *timing;
-	int node = dev_of_offset(dev);
-	int panel_node;
-	int rgb;
+	ofnode rgb;
 	int ret;
 
 	priv->dc = (struct dc_ctlr *)dev_read_addr_ptr(dev);
@@ -451,44 +573,42 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
 	priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
 	priv->pipe = dev_read_u32_default(dev, "nvidia,head", 0);
 
-	rgb = fdt_subnode_offset(blob, node, "rgb");
-	if (rgb < 0) {
-		log_debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
-			  __func__, dev->name, rgb);
-		return -EINVAL;
-	}
-
 	/*
-	 * Sadly the panel phandle is in an rgb subnode so we cannot use
-	 * uclass_get_device_by_phandle().
+	 * Usual logic of Tegra video routing should be next:
+	 * 1. Check rgb subnode for RGB/LVDS panels or bridges
+	 * 2. If none found, then iterate through bridges bound,
+	 *    looking for DSIA or DSIB for DC0 and HDMI for DC1.
+	 * If none of above is valid, then configuration is not
+	 * valid.
 	 */
-	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (panel_node < 0) {
-		log_debug("%s: Cannot find panel information\n", __func__);
-		return -EINVAL;
-	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
-					     &priv->panel);
-	if (ret) {
-		log_debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
-			  dev->name, ret);
-		return ret;
+	rgb = dev_read_subnode(dev, "rgb");
+	if (ofnode_valid(rgb) && ofnode_is_enabled(rgb)) {
+		/* RGB is available, use it */
+		ret = tegra_lcd_configure_rgb(dev, rgb);
+		if (ret)
+			return ret;
+	} else {
+		/* RGB is not available, check for internal devices */
+		ret = tegra_lcd_configure_internal(dev);
+		if (ret)
+			return ret;
 	}
 
-	/* Fill the platform data for internal devices */
-	if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
-	    !strcmp(priv->panel->name, TEGRA_DSI_B)) {
-		struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
-
-		dc_plat->dev = dev;
-		dc_plat->dc = priv->dc;
-		dc_plat->pipe = priv->pipe;
+	if (priv->panel) {
+		ret = panel_get_display_timing(priv->panel, &priv->timing);
+		if (ret) {
+			ret = ofnode_decode_display_timing(rgb, 0, &priv->timing);
+			if (ret) {
+				log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+					  __func__, dev->name, ret);
+				return -EINVAL;
+			}
+		}
 	}
 
-	ret = panel_get_display_timing(priv->panel, &priv->timing);
-	if (ret) {
-		ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+	if (priv->bridge) {
+		ret = video_bridge_get_display_timing(priv->bridge, &priv->timing);
 		if (ret) {
 			log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
 				  __func__, dev->name, ret);
@@ -508,23 +628,13 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
 static int tegra_lcd_bind(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
-	int rgb;
-
-	rgb = fdt_subnode_offset(blob, node, "rgb");
-	if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
-		return -ENODEV;
 
 	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 		(1 << LCD_MAX_LOG2_BPP) / 8;
 
-	return 0;
+	return dm_scan_fdt_dev(dev);
 }
 
-static const struct video_ops tegra_lcd_ops = {
-};
-
 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
 	.has_timer = true,
 	.has_rgb = true,
@@ -565,7 +675,6 @@ U_BOOT_DRIVER(tegra_lcd) = {
 	.name		= "tegra_lcd",
 	.id		= UCLASS_VIDEO,
 	.of_match	= tegra_lcd_ids,
-	.ops		= &tegra_lcd_ops,
 	.bind		= tegra_lcd_bind,
 	.probe		= tegra_lcd_probe,
 	.of_to_plat	= tegra_lcd_of_to_plat,
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 7d0c189ec80..2a4013b3355 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -14,9 +14,6 @@
 /* arch-tegra/dc exists only because T124 uses it */
 #include <asm/arch-tegra/dc.h>
 
-#define TEGRA_DSI_A		"dsi@54300000"
-#define TEGRA_DSI_B		"dsi@54400000"
-
 struct tegra_dc_plat {
 	struct udevice *dev;		/* Display controller device */
 	struct dc_ctlr *dc;		/* Display controller regmap */
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 9f39ac7589b..a2a22fa0fe2 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -11,6 +11,7 @@
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
+#include <video_bridge.h>
 #include <panel.h>
 #include <reset.h>
 #include <linux/delay.h>
@@ -250,6 +251,9 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
 		DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
 
+	if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
+		value |= DSI_HOST_CONTROL_HS;
+
 	/*
 	 * The host FIFO has a maximum of 64 words, so larger transmissions
 	 * need to use the video FIFO.
@@ -991,7 +995,7 @@ static int tegra_dsi_ganged_probe(struct udevice *dev)
 	struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
 	struct udevice *gangster;
 
-	uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+	uclass_get_device_by_phandle(UCLASS_VIDEO_BRIDGE, dev,
 				     "nvidia,ganged-mode", &gangster);
 	if (gangster) {
 		/* Ganged mode is set */
@@ -1118,8 +1122,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
 	return 0;
 }
 
-static const struct panel_ops tegra_dsi_bridge_ops = {
-	.enable_backlight	= tegra_dsi_encoder_enable,
+static const struct video_bridge_ops tegra_dsi_bridge_ops = {
+	.attach			= tegra_dsi_encoder_enable,
 	.set_backlight		= tegra_dsi_bridge_set_panel,
 	.get_display_timing	= tegra_dsi_panel_timings,
 };
@@ -1133,7 +1137,7 @@ static const struct udevice_id tegra_dsi_bridge_ids[] = {
 
 U_BOOT_DRIVER(tegra_dsi) = {
 	.name		= "tegra_dsi",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= tegra_dsi_bridge_ids,
 	.ops		= &tegra_dsi_bridge_ops,
 	.bind		= dm_scan_fdt_dev,
diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra20/tegra-hdmi.c
new file mode 100644
index 00000000000..bda69919d92
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <edid.h>
+#include <i2c.h>
+#include <log.h>
+#include <misc.h>
+#include <panel.h>
+#include <reset.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/time.h>
+#include <power/regulator.h>
+#include <video_bridge.h>
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#include "tegra-dc.h"
+#include "tegra-hdmi.h"
+
+#define DDCCI_ENTRY_ADDR	0x37
+#define DDCCI_SOURSE_ADDR	0x51
+#define DDCCI_COMMAND_WRITE	0x03
+#define DDCCI_CTRL_BRIGHTNESS	0x10
+
+#define HDMI_EDID_I2C_ADDR	0x50
+#define HDMI_REKEY_DEFAULT	56
+
+static const char * const hdmi_supplies[] = {
+	"hdmi-supply", "pll-supply", "vdd-supply"
+};
+
+struct tmds_config {
+	unsigned int pclk;
+	u32 pll0;
+	u32 pll1;
+	u32 pe_current;
+	u32 drive_current;
+	u32 peak_current;
+};
+
+struct tegra_hdmi_config {
+	const struct tmds_config *tmds;
+	unsigned int num_tmds;
+	unsigned int max_pclk;
+
+	/* to be filled */
+};
+
+struct tegra_hdmi_priv {
+	struct hdmi_ctlr *hdmi_regmap;
+
+	struct udevice *supplies[ARRAY_SIZE(hdmi_supplies)];
+	struct udevice *hdmi_ddc;
+
+	struct gpio_desc hpd; /* hotplug detection gpio */
+	struct display_timing timing;
+
+	struct clk *clk;
+	struct clk *clk_parent;
+
+	int panel_bits_per_colourp;
+	const struct tegra_hdmi_config *config;
+};
+
+/* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
+static struct display_timing default_720p_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 1280,
+	.hfront_porch.typ	= 110,
+	.hback_porch.typ	= 220,
+	.hsync_len.typ		= 40,
+	.vactive.typ		= 720,
+	.vfront_porch.typ	= 5,
+	.vback_porch.typ	= 20,
+	.vsync_len.typ		= 5,
+	.flags			= DISPLAY_FLAGS_HSYNC_HIGH |
+				  DISPLAY_FLAGS_VSYNC_HIGH,
+};
+
+static const struct tmds_config tegra20_tmds_config[] = {
+	{ /* slow pixel clock modes */
+		.pclk = 27000000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+			SOR_PLL_TX_REG_LOAD(3),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+		.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+			PE_CURRENT1(PE_CURRENT_0_0_mA) |
+			PE_CURRENT2(PE_CURRENT_0_0_mA) |
+			PE_CURRENT3(PE_CURRENT_0_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+	},
+	{ /* high pixel clock modes */
+		.pclk = UINT_MAX,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+			SOR_PLL_TX_REG_LOAD(3),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+			PE_CURRENT1(PE_CURRENT_6_0_mA) |
+			PE_CURRENT2(PE_CURRENT_6_0_mA) |
+			PE_CURRENT3(PE_CURRENT_6_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+	},
+};
+
+static const struct tmds_config tegra30_tmds_config[] = {
+	{ /* 480p modes */
+		.pclk = 27000000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+		.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+			PE_CURRENT1(PE_CURRENT_0_0_mA) |
+			PE_CURRENT2(PE_CURRENT_0_0_mA) |
+			PE_CURRENT3(PE_CURRENT_0_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	}, { /* 720p modes */
+		.pclk = 74250000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+			PE_CURRENT1(PE_CURRENT_5_0_mA) |
+			PE_CURRENT2(PE_CURRENT_5_0_mA) |
+			PE_CURRENT3(PE_CURRENT_5_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	}, { /* 1080p modes */
+		.pclk = UINT_MAX,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+			PE_CURRENT1(PE_CURRENT_5_0_mA) |
+			PE_CURRENT2(PE_CURRENT_5_0_mA) |
+			PE_CURRENT3(PE_CURRENT_5_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	},
+};
+
+static void tegra_dc_enable_controller(struct udevice *dev)
+{
+	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+	struct dc_ctlr *dc = dc_plat->dc;
+	u32 value;
+
+	value = readl(&dc->disp.disp_win_opt);
+	value |= HDMI_ENABLE;
+	writel(value, &dc->disp.disp_win_opt);
+
+	writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
+	writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
+}
+
+static void tegra_hdmi_setup_tmds(struct tegra_hdmi_priv *priv,
+				  const struct tmds_config *tmds)
+{
+	struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+	u32 value;
+
+	writel(tmds->pll0, &hdmi->nv_pdisp_sor_pll0);
+	writel(tmds->pll1, &hdmi->nv_pdisp_sor_pll1);
+	writel(tmds->pe_current, &hdmi->nv_pdisp_pe_current);
+
+	writel(tmds->drive_current, &hdmi->nv_pdisp_sor_lane_drive_current);
+
+	value = readl(&hdmi->nv_pdisp_sor_lane_drive_current);
+	value |= BIT(31);
+	writel(value, &hdmi->nv_pdisp_sor_lane_drive_current);
+}
+
+static int tegra_hdmi_encoder_enable(struct udevice *dev)
+{
+	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct dc_ctlr *dc = dc_plat->dc;
+	struct display_timing *dt = &priv->timing;
+	struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+	unsigned long rate, div82;
+	unsigned int pulse_start, rekey;
+	int retries = 1000;
+	u32 value;
+	int i;
+
+	/* power up sequence */
+	value = readl(&hdmi->nv_pdisp_sor_pll0);
+	value &= ~SOR_PLL_PDBG;
+	writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+	udelay(20);
+
+	value = readl(&hdmi->nv_pdisp_sor_pll0);
+	value &= ~SOR_PLL_PWR;
+	writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+	writel(VSYNC_H_POSITION(1), &dc->disp.disp_timing_opt);
+	writel(DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
+	       &dc->disp.disp_color_ctrl);
+
+	/* video_preamble uses h_pulse2 */
+	pulse_start = 1 + dt->hsync_len.typ + dt->hback_porch.typ - 10;
+
+	writel(H_PULSE2_ENABLE, &dc->disp.disp_signal_opt0);
+
+	value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH |
+		PULSE_QUAL_VACTIVE | PULSE_LAST_END_A;
+	writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_ctrl);
+
+	value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
+	writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_pos[H_PULSE0_POSITION_A]);
+
+	value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
+		VSYNC_WINDOW_ENABLE;
+	writel(value, &hdmi->nv_pdisp_hdmi_vsync_window);
+
+	if (dc_plat->pipe)
+		value = HDMI_SRC_DISPLAYB;
+	else
+		value = HDMI_SRC_DISPLAYA;
+
+	if (dt->hactive.typ == 720 && (dt->vactive.typ == 480 ||
+				       dt->vactive.typ == 576))
+		writel(value | ARM_VIDEO_RANGE_FULL,
+		       &hdmi->nv_pdisp_input_control);
+	else
+		writel(value | ARM_VIDEO_RANGE_LIMITED,
+		       &hdmi->nv_pdisp_input_control);
+
+	rate = clock_get_periph_rate(priv->clk->id, priv->clk_parent->id);
+	div82 = rate / USEC_PER_SEC * 4;
+	value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
+	writel(value, &hdmi->nv_pdisp_sor_refclk);
+
+	rekey = HDMI_REKEY_DEFAULT;
+	value = HDMI_CTRL_REKEY(rekey);
+	value |= HDMI_CTRL_MAX_AC_PACKET((dt->hsync_len.typ + dt->hback_porch.typ +
+					  dt->hfront_porch.typ - rekey - 18) / 32);
+	writel(value, &hdmi->nv_pdisp_hdmi_ctrl);
+
+	/* TMDS CONFIG */
+	for (i = 0; i < priv->config->num_tmds; i++) {
+		if (dt->pixelclock.typ <= priv->config->tmds[i].pclk) {
+			tegra_hdmi_setup_tmds(priv, &priv->config->tmds[i]);
+			break;
+		}
+	}
+
+	writel(SOR_SEQ_PU_PC(0) | SOR_SEQ_PU_PC_ALT(0) | SOR_SEQ_PD_PC(8) |
+	       SOR_SEQ_PD_PC_ALT(8), &hdmi->nv_pdisp_sor_seq_ctl);
+
+	value = SOR_SEQ_INST_WAIT_TIME(1) | SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+		SOR_SEQ_INST_HALT | SOR_SEQ_INST_PIN_A_LOW |
+		SOR_SEQ_INST_PIN_B_LOW | SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
+
+	writel(value, &hdmi->nv_pdisp_sor_seq_inst0);
+	writel(value, &hdmi->nv_pdisp_sor_seq_inst8);
+
+	value = readl(&hdmi->nv_pdisp_sor_cstm);
+
+	value &= ~SOR_CSTM_ROTCLK(~0);
+	value |= SOR_CSTM_ROTCLK(2);
+	value |= SOR_CSTM_PLLDIV;
+	value &= ~SOR_CSTM_LVDS_ENABLE;
+	value &= ~SOR_CSTM_MODE_MASK;
+	value |= SOR_CSTM_MODE_TMDS;
+
+	writel(value, &hdmi->nv_pdisp_sor_cstm);
+
+	/* start SOR */
+	writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+	       SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_TRIGGER,
+	       &hdmi->nv_pdisp_sor_pwr);
+	writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+	       SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_DONE,
+	       &hdmi->nv_pdisp_sor_pwr);
+
+	do {
+		if (--retries < 0)
+			return -ETIME;
+		value = readl(&hdmi->nv_pdisp_sor_pwr);
+	} while (value & SOR_PWR_SETTING_NEW_PENDING);
+
+	value = SOR_STATE_ASY_CRCMODE_COMPLETE |
+		SOR_STATE_ASY_OWNER_HEAD0 |
+		SOR_STATE_ASY_SUBOWNER_BOTH |
+		SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
+		SOR_STATE_ASY_DEPOL_POS;
+
+	/* setup sync polarities */
+	if (dt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		value |= SOR_STATE_ASY_HSYNCPOL_POS;
+
+	if (dt->flags & DISPLAY_FLAGS_HSYNC_LOW)
+		value |= SOR_STATE_ASY_HSYNCPOL_NEG;
+
+	if (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		value |= SOR_STATE_ASY_VSYNCPOL_POS;
+
+	if (dt->flags & DISPLAY_FLAGS_VSYNC_LOW)
+		value |= SOR_STATE_ASY_VSYNCPOL_NEG;
+
+	writel(value, &hdmi->nv_pdisp_sor_state2);
+
+	value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
+	writel(value, &hdmi->nv_pdisp_sor_state1);
+
+	writel(0, &hdmi->nv_pdisp_sor_state0);
+	writel(SOR_STATE_UPDATE, &hdmi->nv_pdisp_sor_state0);
+	writel(value | SOR_STATE_ATTACHED,
+	       &hdmi->nv_pdisp_sor_state1);
+	writel(0, &hdmi->nv_pdisp_sor_state0);
+
+	tegra_dc_enable_controller(dev);
+
+	return 0;
+}
+
+/* DDC/CI backlight control */
+static int tegra_hdmi_set_connector(struct udevice *dev, int percent)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct udevice *ddc_entry;
+	struct i2c_msg msg[1];
+	u8 checksum = DDCCI_ENTRY_ADDR << 1;
+	int i, ret;
+
+	ret = dm_i2c_probe(priv->hdmi_ddc, DDCCI_ENTRY_ADDR, 0, &ddc_entry);
+	if (ret) {
+		log_debug("%s: cannot probe DDC/CI entry: error %d\n",
+			  __func__, ret);
+		return 0;
+	}
+
+	/*
+	 * payload[1] is length: hithest bit OR last 4 bits indicate
+	 * the number of following bytes (excluding checksum)
+	 */
+	u8 payload[7] = { DDCCI_SOURSE_ADDR, BIT(7) | (sizeof(payload) - 3),
+			  DDCCI_COMMAND_WRITE, DDCCI_CTRL_BRIGHTNESS,
+			  (u8)(percent & 0xff), (u8)(percent & 0xff), 0 };
+
+	/* DDC/CI checksum is a simple XOR of all preceding bytes */
+	for (i = 0; i < (sizeof(payload) - 1); i++)
+		checksum ^= payload[i];
+
+	payload[6] = checksum;
+
+	msg->addr = DDCCI_ENTRY_ADDR;
+	msg->flags = 0;
+	msg->len = sizeof(payload);
+	msg->buf = payload;
+
+	dm_i2c_xfer(ddc_entry, msg, 1);
+
+	return 0;
+}
+
+static int tegra_hdmi_timings(struct udevice *dev,
+			      struct display_timing *timing)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+
+	memcpy(timing, &priv->timing, sizeof(*timing));
+
+	return 0;
+}
+
+static void tegra_hdmi_init_clocks(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	u32 n = priv->timing.pixelclock.typ * 2 / USEC_PER_SEC;
+
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+	case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 12, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+	case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 13, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_19_2:
+	case CLOCK_OSC_FREQ_38_4:
+	default:
+		/*
+		 * These are not supported.
+		 */
+		break;
+	}
+
+	clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
+			       priv->timing.pixelclock.typ);
+}
+
+static bool tegra_hdmi_mode_valid(void *hdmi_priv, const struct display_timing *timing)
+{
+	struct tegra_hdmi_priv *priv = hdmi_priv;
+
+	if (timing->pixelclock.typ > priv->config->max_pclk)
+		return false;
+
+	return true;
+}
+
+static int tegra_hdmi_decode_edid(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct udevice *hdmi_edid;
+	uchar edid_buf[EDID_SIZE] = { 0 };
+	int i, ret;
+
+	/* Poll for 1 sec in case EDID is not ready right after hpd */
+	for (i = 0; i < 10; i++) {
+		ret = dm_i2c_probe(priv->hdmi_ddc, HDMI_EDID_I2C_ADDR, 0,
+				   &hdmi_edid);
+		if (!ret)
+			break;
+
+		mdelay(100);
+	}
+	if (ret) {
+		log_debug("%s: cannot probe EDID: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_read(hdmi_edid, 0, edid_buf, sizeof(edid_buf));
+	if (ret) {
+		log_debug("%s: cannot dump EDID buffer: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = edid_get_timing_validate(edid_buf, sizeof(edid_buf), &priv->timing,
+				       &priv->panel_bits_per_colourp,
+				       tegra_hdmi_mode_valid, priv);
+	if (ret) {
+		log_debug("%s: cannot decode EDID info: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int tegra_hdmi_wait_hpd(struct tegra_hdmi_priv *priv)
+{
+	int i;
+
+	/* Poll 1 second for HPD signal */
+	for (i = 0; i < 10; i++) {
+		if (dm_gpio_get_value(&priv->hpd))
+			return 0;
+
+		mdelay(100);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int tegra_hdmi_probe(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct reset_ctl reset_ctl;
+	int i, ret;
+
+	priv->hdmi_regmap = (struct hdmi_ctlr *)dev_read_addr_ptr(dev);
+	if (!priv->hdmi_regmap) {
+		log_debug("%s: no display controller address\n", __func__);
+		return -EINVAL;
+	}
+
+	priv->config = (struct tegra_hdmi_config *)dev_get_driver_data(dev);
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		log_debug("%s: Could not get HDMI clock: %ld\n",
+			  __func__, PTR_ERR(priv->clk));
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->clk_parent = devm_clk_get(dev, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get HDMI clock parent: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(hdmi_supplies); i++) {
+		ret = device_get_supply_regulator(dev, hdmi_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  hdmi_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
+
+		ret = regulator_set_enable_if_allowed(priv->supplies[i], true);
+		if (ret && ret != -ENOSYS) {
+			log_debug("%s: cannot enable %s: error %d\n",
+				  __func__, hdmi_supplies[i], ret);
+			return ret;
+		}
+	}
+
+	ret = reset_get_by_name(dev, "hdmi", &reset_ctl);
+	if (ret) {
+		log_debug("%s: reset_get_by_name() failed: %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_I2C, dev,
+					   "nvidia,ddc-i2c-bus",
+					   &priv->hdmi_ddc);
+	if (ret) {
+		log_debug("%s: cannot get hdmi ddc i2c bus: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "nvidia,hpd-gpio", 0,
+				   &priv->hpd, GPIOD_IS_IN);
+	if (ret) {
+		log_debug("%s: Could not decode hpd-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	/* wait for connector */
+	ret = tegra_hdmi_wait_hpd(priv);
+	if (ret) {
+		/* HPD failed, use default timings */
+		memcpy(&priv->timing, &default_720p_timing,
+		       sizeof(default_720p_timing));
+	} else {
+		ret = tegra_hdmi_decode_edid(dev);
+		if (ret)
+			memcpy(&priv->timing, &default_720p_timing,
+			       sizeof(default_720p_timing));
+	}
+
+	reset_assert(&reset_ctl);
+	tegra_hdmi_init_clocks(dev);
+
+	mdelay(2);
+	reset_deassert(&reset_ctl);
+
+	return 0;
+}
+
+static const struct tegra_hdmi_config tegra20_hdmi_config = {
+	.tmds = tegra20_tmds_config,
+	.num_tmds = ARRAY_SIZE(tegra20_tmds_config),
+	.max_pclk = 148500000, /* 1080p */
+};
+
+static const struct tegra_hdmi_config tegra30_hdmi_config = {
+	.tmds = tegra30_tmds_config,
+	.num_tmds = ARRAY_SIZE(tegra30_tmds_config),
+	.max_pclk = 148500000, /* 1080p */
+};
+
+static const struct video_bridge_ops tegra_hdmi_ops = {
+	.attach			= tegra_hdmi_encoder_enable,
+	.set_backlight		= tegra_hdmi_set_connector,
+	.get_display_timing	= tegra_hdmi_timings,
+};
+
+static const struct udevice_id tegra_hdmi_ids[] = {
+	{
+		.compatible = "nvidia,tegra20-hdmi",
+		.data = (ulong)&tegra20_hdmi_config
+	}, {
+		.compatible = "nvidia,tegra30-hdmi",
+		.data = (ulong)&tegra30_hdmi_config
+	}, {
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(tegra_hdmi) = {
+	.name		= "tegra_hdmi",
+	.id		= UCLASS_VIDEO_BRIDGE,
+	.of_match	= tegra_hdmi_ids,
+	.ops		= &tegra_hdmi_ops,
+	.probe		= tegra_hdmi_probe,
+	.plat_auto	= sizeof(struct tegra_dc_plat),
+	.priv_auto	= sizeof(struct tegra_hdmi_priv),
+};
diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra20/tegra-hdmi.h
new file mode 100644
index 00000000000..d17655973e3
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.h
@@ -0,0 +1,648 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_HDMI_H
+#define _TEGRA_HDMI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/* Register definitions for the Tegra high-definition multimedia interface */
+
+/* High-Definition Multimedia Interface (HDMI_) regs */
+struct hdmi_ctlr {
+	/* Address 0x000 ~ 0x0d2 */
+	uint ctxsw;						/* _CTXSW */  /* 0x00 */
+
+	uint nv_pdisp_sor_state0;				/* _NV_PDISP_SOR_STATE0 */
+	uint nv_pdisp_sor_state1;				/* _NV_PDISP_SOR_STATE1 */
+	uint nv_pdisp_sor_state2;				/* _NV_PDISP_SOR_STATE2 */
+
+	uint nv_pdisp_rg_hdcp_an_msb;				/* _NV_PDISP_RG_HDCP_AN_MSB */
+	uint nv_pdisp_rg_hdcp_an_lsb;				/* _NV_PDISP_RG_HDCP_AN_LSB */
+	uint nv_pdisp_rg_hdcp_cn_msb;				/* _NV_PDISP_RG_HDCP_CN_MSB */
+	uint nv_pdisp_rg_hdcp_cn_lsb;				/* _NV_PDISP_RG_HDCP_CN_LSB */
+	uint nv_pdisp_rg_hdcp_aksv_msb;				/* _NV_PDISP_RG_HDCP_AKSV_MSB */
+	uint nv_pdisp_rg_hdcp_aksv_lsb;				/* _NV_PDISP_RG_HDCP_AKSV_LSB */
+	uint nv_pdisp_rg_hdcp_bksv_msb;				/* _NV_PDISP_RG_HDCP_BKSV_MSB */
+	uint nv_pdisp_rg_hdcp_bksv_lsb;				/* _NV_PDISP_RG_HDCP_BKSV_LSB */
+	uint nv_pdisp_rg_hdcp_cksv_msb;				/* _NV_PDISP_RG_HDCP_CKSV_MSB */
+	uint nv_pdisp_rg_hdcp_cksv_lsb;				/* _NV_PDISP_RG_HDCP_CKSV_LSB */
+	uint nv_pdisp_rg_hdcp_dksv_msb;				/* _NV_PDISP_RG_HDCP_DKSV_MSB */
+	uint nv_pdisp_rg_hdcp_dksv_lsb;				/* _NV_PDISP_RG_HDCP_DKSV_LSB */
+	uint nv_pdisp_rg_hdcp_ctrl;				/* _NV_PDISP_RG_HDCP_CTRL */  /* 0x10 */
+	uint nv_pdisp_rg_hdcp_cmode;				/* _NV_PDISP_RG_HDCP_CMODE */
+	uint nv_pdisp_rg_hdcp_mprime_msb;			/* _NV_PDISP_RG_HDCP_MPRIME_MSB */
+	uint nv_pdisp_rg_hdcp_mprime_lsb;			/* _NV_PDISP_RG_HDCP_MPRIME_LSB */
+	uint nv_pdisp_rg_hdcp_sprime_msb;			/* _NV_PDISP_RG_HDCP_SPRIME_MSB */
+	uint nv_pdisp_rg_hdcp_sprime_lsb2;			/* _NV_PDISP_RG_HDCP_SPRIME_LSB2 */
+	uint nv_pdisp_rg_hdcp_sprime_lsb1;			/* _NV_PDISP_RG_HDCP_SPRIME_LSB1 */
+	uint nv_pdisp_rg_hdcp_ri;				/* _NV_PDISP_RG_HDCP_RI */
+	uint nv_pdisp_rg_hdcp_cs_msb;				/* _NV_PDISP_RG_HDCP_CS_MSB */
+	uint nv_pdisp_rg_hdcp_cs_lsb;				/* _NV_PDISP_RG_HDCP_CS_LSB */
+
+	uint nv_pdisp_hdmi_audio_emu0;				/* _NV_PDISP_HDMI_AUDIO_EMU0 */
+	uint nv_pdisp_hdmi_audio_emu_rdata0;			/* _NV_PDISP_HDMI_AUDIO_EMU_RDATA0 */
+	uint nv_pdisp_hdmi_audio_emu1;				/* _NV_PDISP_HDMI_AUDIO_EMU1 */
+	uint nv_pdisp_hdmi_audio_emu2;				/* _NV_PDISP_HDMI_AUDIO_EMU2 */
+	uint nv_pdisp_hdmi_audio_infoframe_ctrl;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL */
+	uint nv_pdisp_hdmi_audio_infoframe_status;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS */
+	uint nv_pdisp_hdmi_audio_infoframe_header;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER */  /* 0x20 */
+	uint nv_pdisp_hdmi_audio_infoframe_subpack0_low;	/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_audio_infoframe_subpack0_high;	/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH */
+
+	uint nv_pdisp_hdmi_avi_infoframe_ctrl;			/* _NV_PDISP_HDMI_AVI_INFOFRAME_CTRL */
+	uint nv_pdisp_hdmi_avi_infoframe_status;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_STATUS */
+	uint nv_pdisp_hdmi_avi_infoframe_header;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_HEADER */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack0_low;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack0_high;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack1_low;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack1_high;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH */
+
+	uint nv_pdisp_hdmi_generic_ctrl;			/* _NV_PDISP_HDMI_GENERIC_CTRL */
+	uint nv_pdisp_hdmi_generic_status;			/* _NV_PDISP_HDMI_GENERIC_STATUS */
+	uint nv_pdisp_hdmi_generic_header;			/* _NV_PDISP_HDMI_GENERIC_HEADER */
+	uint nv_pdisp_hdmi_generic_subpack0_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_generic_subpack0_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack1_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW */
+	uint nv_pdisp_hdmi_generic_subpack1_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack2_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW */
+	uint nv_pdisp_hdmi_generic_subpack2_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack3_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW */
+	uint nv_pdisp_hdmi_generic_subpack3_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH */
+
+	uint nv_pdisp_hdmi_acr_ctrl;				/* _NV_PDISP_HDMI_ACR_CTRL */
+	uint nv_pdisp_hdmi_acr_0320_subpack_low;		/* _NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0320_subpack_high;		/* _NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0441_subpack_low;		/* _NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0441_subpack_high;		/* _NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0882_subpack_low;		/* _NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0882_subpack_high;		/* _NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_1764_subpack_low;		/* _NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_1764_subpack_high;		/* _NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0480_subpack_low;		/* _NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0480_subpack_high;		/* _NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0960_subpack_low;		/* _NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0960_subpack_high;		/* _NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_1920_subpack_low;		/* _NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_1920_subpack_high;		/* _NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH */
+
+	uint nv_pdisp_hdmi_ctrl;				/* _NV_PDISP_HDMI_CTRL */
+	uint nv_pdisp_hdmi_vsync_keepout;			/* _NV_PDISP_HDMI_VSYNC_KEEPOUT */
+	uint nv_pdisp_hdmi_vsync_window;			/* _NV_PDISP_HDMI_VSYNC_WINDOW */
+	uint nv_pdisp_hdmi_gcp_ctrl;				/* _NV_PDISP_HDMI_GCP_CTRL */
+	uint nv_pdisp_hdmi_gcp_status;				/* _NV_PDISP_HDMI_GCP_STATUS */
+	uint nv_pdisp_hdmi_gcp_subpack;				/* _NV_PDISP_HDMI_GCP_SUBPACK */
+	uint nv_pdisp_hdmi_channel_status1;			/* _NV_PDISP_HDMI_CHANNEL_STATUS1 */
+	uint nv_pdisp_hdmi_channel_status2;			/* _NV_PDISP_HDMI_CHANNEL_STATUS2 */
+	uint nv_pdisp_hdmi_emu0;				/* _NV_PDISP_HDMI_EMU0 */
+	uint nv_pdisp_hdmi_emu1;				/* _NV_PDISP_HDMI_EMU1 */
+	uint nv_pdisp_hdmi_emu1_rdata;				/* _NV_PDISP_HDMI_EMU1_RDATA */
+	uint nv_pdisp_hdmi_spare;				/* _NV_PDISP_HDMI_SPARE */
+	uint nv_pdisp_hdmi_spdif_chn_status1;			/* _NV_PDISP_HDMI_SPDIF_CHN_STATUS1 */
+	uint nv_pdisp_hdmi_spdif_chn_status2;			/* _NV_PDISP_HDMI_SPDIF_CHN_STATUS2 */
+
+	uint nv_pdisp_hdcprif_rom_ctrl;				/* _NV_PDISP_HDCPRIF_ROM_CTRL */
+
+	uint unused;
+
+	uint nv_pdisp_sor_cap;					/* _NV_PDISP_SOR_CAP */
+	uint nv_pdisp_sor_pwr;					/* _NV_PDISP_SOR_PWR */
+	uint nv_pdisp_sor_test;					/* _NV_PDISP_SOR_TEST */
+	uint nv_pdisp_sor_pll0;					/* _NV_PDISP_SOR_PLL0 */
+	uint nv_pdisp_sor_pll1;					/* _NV_PDISP_SOR_PLL1 */
+	uint nv_pdisp_sor_pll2;					/* _NV_PDISP_SOR_PLL2 */
+	uint nv_pdisp_sor_cstm;					/* _NV_PDISP_SOR_CSTM */
+	uint nv_pdisp_sor_lvds;					/* _NV_PDISP_SOR_LVDS */
+	uint nv_pdisp_sor_crca;					/* _NV_PDISP_SOR_CRCA */
+	uint nv_pdisp_sor_crcb;					/* _NV_PDISP_SOR_CRCB */
+	uint nv_pdisp_sor_blank;				/* _NV_PDISP_SOR_BLANK */
+
+	uint nv_pdisp_sor_seq_ctl;				/* _NV_PDISP_SOR_SEQ_CTL */
+	uint nv_pdisp_sor_seq_inst0;				/* _NV_PDISP_SOR_SEQ_INST0 */
+	uint nv_pdisp_sor_seq_inst1;				/* _NV_PDISP_SOR_SEQ_INST1 */
+	uint nv_pdisp_sor_seq_inst2;				/* _NV_PDISP_SOR_SEQ_INST2 */
+	uint nv_pdisp_sor_seq_inst3;				/* _NV_PDISP_SOR_SEQ_INST3 */
+	uint nv_pdisp_sor_seq_inst4;				/* _NV_PDISP_SOR_SEQ_INST4 */
+	uint nv_pdisp_sor_seq_inst5;				/* _NV_PDISP_SOR_SEQ_INST5 */
+	uint nv_pdisp_sor_seq_inst6;				/* _NV_PDISP_SOR_SEQ_INST6 */
+	uint nv_pdisp_sor_seq_inst7;				/* _NV_PDISP_SOR_SEQ_INST7 */
+	uint nv_pdisp_sor_seq_inst8;				/* _NV_PDISP_SOR_SEQ_INST8 */
+	uint nv_pdisp_sor_seq_inst9;				/* _NV_PDISP_SOR_SEQ_INST9 */
+	uint nv_pdisp_sor_seq_insta;				/* _NV_PDISP_SOR_SEQ_INSTA */
+	uint nv_pdisp_sor_seq_instb;				/* _NV_PDISP_SOR_SEQ_INSTB */
+	uint nv_pdisp_sor_seq_instc;				/* _NV_PDISP_SOR_SEQ_INSTC */
+	uint nv_pdisp_sor_seq_instd;				/* _NV_PDISP_SOR_SEQ_INSTD */
+	uint nv_pdisp_sor_seq_inste;				/* _NV_PDISP_SOR_SEQ_INSTE */
+	uint nv_pdisp_sor_seq_instf;				/* _NV_PDISP_SOR_SEQ_INSTF */
+
+	uint unused1[2];
+
+	uint nv_pdisp_sor_vcrca0;				/* _NV_PDISP_SOR_VCRCA0 */
+	uint nv_pdisp_sor_vcrca1;				/* _NV_PDISP_SOR_VCRCA1 */
+	uint nv_pdisp_sor_ccrca0;				/* _NV_PDISP_SOR_CCRCA0 */
+	uint nv_pdisp_sor_ccrca1;				/* _NV_PDISP_SOR_CCRCA1 */
+
+	uint nv_pdisp_sor_edataa0;				/* _NV_PDISP_SOR_EDATAA0 */
+	uint nv_pdisp_sor_edataa1;				/* _NV_PDISP_SOR_EDATAA1 */
+
+	uint nv_pdisp_sor_counta0;				/* _NV_PDISP_SOR_COUNTA0 */
+	uint nv_pdisp_sor_counta1;				/* _NV_PDISP_SOR_COUNTA1 */
+
+	uint nv_pdisp_sor_debuga0;				/* _NV_PDISP_SOR_DEBUGA0 */
+	uint nv_pdisp_sor_debuga1;				/* _NV_PDISP_SOR_DEBUGA1 */
+
+	uint nv_pdisp_sor_trig;					/* _NV_PDISP_SOR_TRIG */
+	uint nv_pdisp_sor_mscheck;				/* _NV_PDISP_SOR_MSCHECK */
+	uint nv_pdisp_sor_lane_drive_current;			/* _NV_PDISP_SOR_LANE_DRIVE_CURRENT */
+
+	uint nv_pdisp_audio_debug0;				/* _NV_PDISP_AUDIO_DEBUG0 0x7f */
+	uint nv_pdisp_audio_debug1;				/* _NV_PDISP_AUDIO_DEBUG1 0x80 */
+	uint nv_pdisp_audio_debug2;				/* _NV_PDISP_AUDIO_DEBUG2 0x81 */
+
+	uint nv_pdisp_audio_fs1;				/* _NV_PDISP_AUDIO_FS1 0x82 */
+	uint nv_pdisp_audio_fs2;				/* _NV_PDISP_AUDIO_FS2 */
+	uint nv_pdisp_audio_fs3;				/* _NV_PDISP_AUDIO_FS3 */
+	uint nv_pdisp_audio_fs4;				/* _NV_PDISP_AUDIO_FS4 */
+	uint nv_pdisp_audio_fs5;				/* _NV_PDISP_AUDIO_FS5 */
+	uint nv_pdisp_audio_fs6;				/* _NV_PDISP_AUDIO_FS6 */
+	uint nv_pdisp_audio_fs7;				/* _NV_PDISP_AUDIO_FS7 0x88 */
+
+	uint nv_pdisp_audio_pulse_width;			/* _NV_PDISP_AUDIO_PULSE_WIDTH */
+	uint nv_pdisp_audio_threshold;				/* _NV_PDISP_AUDIO_THRESHOLD */
+	uint nv_pdisp_audio_cntrl0;				/* _NV_PDISP_AUDIO_CNTRL0 */
+	uint nv_pdisp_audio_n;					/* _NV_PDISP_AUDIO_N */
+	uint nv_pdisp_audio_nval[7];				/* _NV_PDISP_AUDIO_NVAL */
+
+	uint nv_pdisp_hdcprif_rom_timing;			/* _NV_PDISP_HDCPRIF_ROM_TIMING */
+	uint nv_pdisp_sor_refclk;				/* _NV_PDISP_SOR_REFCLK */
+	uint nv_pdisp_crc_control;				/* _NV_PDISP_CRC_CONTROL */
+	uint nv_pdisp_input_control;				/* _NV_PDISP_INPUT_CONTROL */
+	uint nv_pdisp_scratch;					/* _NV_PDISP_SCRATCH */
+	uint nv_pdisp_pe_current;				/* _NV_PDISP_PE_CURRENT */
+
+	uint nv_pdisp_key_ctrl;					/* _NV_PDISP_KEY_CTRL */
+	uint nv_pdisp_key_debug0;				/* _NV_PDISP_KEY_DEBUG0 */
+	uint nv_pdisp_key_debug1;				/* _NV_PDISP_KEY_DEBUG1 */
+	uint nv_pdisp_key_debug2;				/* _NV_PDISP_KEY_DEBUG2 */
+	uint nv_pdisp_key_hdcp_key_0;				/* _NV_PDISP_KEY_HDCP_KEY_0 */
+	uint nv_pdisp_key_hdcp_key_1;				/* _NV_PDISP_KEY_HDCP_KEY_1 */
+	uint nv_pdisp_key_hdcp_key_2;				/* _NV_PDISP_KEY_HDCP_KEY_2 */
+	uint nv_pdisp_key_hdcp_key_3;				/* _NV_PDISP_KEY_HDCP_KEY_3 */
+	uint nv_pdisp_key_hdcp_key_trig;			/* _NV_PDISP_KEY_HDCP_KEY_3 */
+	uint nv_pdisp_key_skey_index;				/* _NV_PDISP_KEY_HDCP_KEY_3 */ /* 0xa3 */
+
+	uint unused2[8];
+
+	uint nv_pdisp_sor_audio_cntrl0;				/* _NV_PDISP_SOR_AUDIO_CNTRL0 */ /* 0xac */
+	uint nv_pdisp_sor_audio_debug;				/* _NV_PDISP_SOR_AUDIO_DEBUG */
+	uint nv_pdisp_sor_audio_spare0;				/* _NV_PDISP_SOR_AUDIO_SPARE0 */
+	uint nv_pdisp_sor_audio_nval[7];			/* _NV_PDISP_SOR_AUDIO_NVAL 0xaf ~ 0xb5 */
+	uint nv_pdisp_sor_audio_hda_scratch[4];			/* _NV_PDISP_SOR_AUDIO_HDA_SCRATCH 0xb6 ~ 0xb9 */
+	uint nv_pdisp_sor_audio_hda_codec_scratch[2];		/* _NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH 0xba ~ 0xbb */
+
+	uint nv_pdisp_sor_audio_hda_eld_bufwr;			/* _NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR */
+	uint nv_pdisp_sor_audio_hda_presense;			/* _NV_PDISP_SOR_AUDIO_HDA_PRESENSE */
+	uint nv_pdisp_sor_audio_hda_cp;				/* _NV_PDISP_SOR_AUDIO_HDA_CP */
+	uint nv_pdisp_sor_audio_aval[8];			/* _NV_PDISP_SOR_AUDIO_AVAL */
+	uint nv_pdisp_sor_audio_gen_ctrl;			/* _NV_PDISP_SOR_AUDIO_GEN_CTRL */
+
+	uint unused3[4];
+
+	uint nv_pdisp_int_status;				/* _NV_PDISP_INT_STATUS */
+	uint nv_pdisp_int_mask;					/* _NV_PDISP_INT_MASK */
+	uint nv_pdisp_int_enable;				/* _NV_PDISP_INT_ENABLE */
+
+	uint unused4[2];
+
+	uint nv_pdisp_sor_io_peak_current;			/* _NV_PDISP_SOR_IO_PEAK_CURRENT */
+	uint nv_pdisp_sor_pad_ctls0;				/* _NV_PDISP_SOR_PAD_CTLS0 */
+};
+
+/* HDMI_NV_PDISP_SOR_STATE0	0x01 */
+#define SOR_STATE_UPDATE			BIT(0)
+
+/* HDMI_NV_PDISP_SOR_STATE1	0x02 */
+#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE		BIT(1)
+#define SOR_STATE_ASY_ORMODE_NORMAL		BIT(2)
+#define SOR_STATE_ATTACHED			BIT(3)
+
+/* HDMI_NV_PDISP_SOR_STATE2	0x03 */
+#define SOR_STATE_ASY_OWNER_NONE		(0 << 0)
+#define SOR_STATE_ASY_OWNER_HEAD0		(1 << 0)
+#define SOR_STATE_ASY_SUBOWNER_NONE		(0 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0		(1 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1		(2 << 4)
+#define SOR_STATE_ASY_SUBOWNER_BOTH		(3 << 4)
+#define SOR_STATE_ASY_CRCMODE_ACTIVE		(0 << 6)
+#define SOR_STATE_ASY_CRCMODE_COMPLETE		(1 << 6)
+#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE	(2 << 6)
+#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A	(1 << 8)
+#define SOR_STATE_ASY_PROTOCOL_CUSTOM		(15 << 8)
+#define SOR_STATE_ASY_HSYNCPOL_POS		(0 << 12)
+#define SOR_STATE_ASY_HSYNCPOL_NEG		(1 << 12)
+#define SOR_STATE_ASY_VSYNCPOL_POS		(0 << 13)
+#define SOR_STATE_ASY_VSYNCPOL_NEG		(1 << 13)
+#define SOR_STATE_ASY_DEPOL_POS			(0 << 14)
+#define SOR_STATE_ASY_DEPOL_NEG			(1 << 14)
+
+#define INFOFRAME_CTRL_ENABLE			BIT(0)
+#define INFOFRAME_HEADER_TYPE(x)		(((x) & 0xff) <<  0)
+#define INFOFRAME_HEADER_VERSION(x)		(((x) & 0xff) <<  8)
+#define INFOFRAME_HEADER_LEN(x)			(((x) & 0x0f) << 16)
+
+/* HDMI_NV_PDISP_HDMI_GENERIC_CTRL	0x2a */
+#define GENERIC_CTRL_ENABLE			BIT(0)
+#define GENERIC_CTRL_OTHER			BIT(4)
+#define GENERIC_CTRL_SINGLE			BIT(8)
+#define GENERIC_CTRL_HBLANK			BIT(12)
+#define GENERIC_CTRL_AUDIO			BIT(16)
+
+/* HDMI_NV_PDISP_HDMI_ACR_* */
+#define ACR_SUBPACK_CTS(x)			(((x) & 0xffffff) << 8)
+#define ACR_SUBPACK_N(x)			(((x) & 0xffffff) << 0)
+#define ACR_ENABLE				BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_CTRL	0x44 */
+#define HDMI_CTRL_REKEY(x)			(((x) & 0x7f) <<  0)
+#define HDMI_CTRL_MAX_AC_PACKET(x)		(((x) & 0x1f) << 16)
+#define HDMI_CTRL_ENABLE			BIT(30)
+
+/* HDMI_NV_PDISP_HDMI_VSYNC_* */
+#define VSYNC_WINDOW_END(x)			(((x) & 0x3ff) <<  0)
+#define VSYNC_WINDOW_START(x)			(((x) & 0x3ff) << 16)
+#define VSYNC_WINDOW_ENABLE			BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_SPARE	0x4f */
+#define SPARE_HW_CTS				BIT(0)
+#define SPARE_FORCE_SW_CTS			BIT(1)
+#define SPARE_CTS_RESET_VAL(x)			(((x) & 0x7) << 16)
+
+/* HDMI_NV_PDISP_SOR_PWR	0x55 */
+#define SOR_PWR_NORMAL_STATE_PD			(0 <<  0)
+#define SOR_PWR_NORMAL_STATE_PU			(1 <<  0)
+#define SOR_PWR_NORMAL_START_NORMAL		(0 <<  1)
+#define SOR_PWR_NORMAL_START_ALT		(1 <<  1)
+#define SOR_PWR_SAFE_STATE_PD			(0 << 16)
+#define SOR_PWR_SAFE_STATE_PU			(1 << 16)
+#define SOR_PWR_SETTING_NEW_DONE		(0 << 31)
+#define SOR_PWR_SETTING_NEW_PENDING		(1 << 31)
+#define SOR_PWR_SETTING_NEW_TRIGGER		(1 << 31)
+
+/* HDMI_NV_PDISP_SOR_PLL0	0x57 */
+#define SOR_PLL_PWR				BIT(0)
+#define SOR_PLL_PDBG				BIT(1)
+#define SOR_PLL_VCAPD				BIT(2)
+#define SOR_PLL_PDPORT				BIT(3)
+#define SOR_PLL_RESISTORSEL			BIT(4)
+#define SOR_PLL_PULLDOWN			BIT(5)
+#define SOR_PLL_VCOCAP(x)			(((x) & 0xf) <<  8)
+#define SOR_PLL_BG_V17_S(x)			(((x) & 0xf) << 12)
+#define SOR_PLL_FILTER(x)			(((x) & 0xf) << 16)
+#define SOR_PLL_ICHPMP(x)			(((x) & 0xf) << 24)
+#define SOR_PLL_TX_REG_LOAD(x)			(((x) & 0xf) << 28)
+
+/* HDMI_NV_PDISP_SOR_PLL1	0x58 */
+#define SOR_PLL_TMDS_TERM_ENABLE		BIT(8)
+#define SOR_PLL_TMDS_TERMADJ(x)			(((x) & 0xf) <<  9)
+#define SOR_PLL_LOADADJ(x)			(((x) & 0xf) << 20)
+#define SOR_PLL_PE_EN				BIT(28)
+#define SOR_PLL_HALF_FULL_PE			BIT(29)
+#define SOR_PLL_S_D_PIN_PE			BIT(30)
+
+/* HDMI_NV_PDISP_SOR_CSTM	0x5a */
+#define SOR_CSTM_ROTCLK(x)			(((x) & 0xf) << 24)
+#define SOR_CSTM_PLLDIV				BIT(21)
+#define SOR_CSTM_LVDS_ENABLE			BIT(16)
+#define SOR_CSTM_MODE_LVDS			(0 << 12)
+#define SOR_CSTM_MODE_TMDS			(1 << 12)
+#define SOR_CSTM_MODE_MASK			(3 << 12)
+
+/* HDMI_NV_PDISP_SOR_SEQ_CTL	0x5f */
+#define SOR_SEQ_PU_PC(x)			(((x) & 0xf) <<  0)
+#define SOR_SEQ_PU_PC_ALT(x)			(((x) & 0xf) <<  4)
+#define SOR_SEQ_PD_PC(x)			(((x) & 0xf) <<  8)
+#define SOR_SEQ_PD_PC_ALT(x)			(((x) & 0xf) << 12)
+#define SOR_SEQ_PC(x)				(((x) & 0xf) << 16)
+#define SOR_SEQ_STATUS				BIT(28)
+#define SOR_SEQ_SWITCH				BIT(30)
+
+/* HDMI_NV_PDISP_SOR_SEQ_INST(x)	(0x60 + (x)) */
+#define SOR_SEQ_INST_WAIT_TIME(x)		(((x) & 0x3ff) << 0)
+#define SOR_SEQ_INST_WAIT_UNITS_VSYNC		(2 << 12)
+#define SOR_SEQ_INST_HALT			(1 << 15)
+#define SOR_SEQ_INST_PIN_A_LOW			(0 << 21)
+#define SOR_SEQ_INST_PIN_A_HIGH			(1 << 21)
+#define SOR_SEQ_INST_PIN_B_LOW			(0 << 22)
+#define SOR_SEQ_INST_PIN_B_HIGH			(1 << 22)
+#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO		(1 << 23)
+
+/* HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT	0x7e */
+#define DRIVE_CURRENT_LANE0(x)			(((x) & 0x3f) <<  0)
+#define DRIVE_CURRENT_LANE1(x)			(((x) & 0x3f) <<  8)
+#define DRIVE_CURRENT_LANE2(x)			(((x) & 0x3f) << 16)
+#define DRIVE_CURRENT_LANE3(x)			(((x) & 0x3f) << 24)
+#define DRIVE_CURRENT_LANE0_T114(x)		(((x) & 0x7f) <<  0)
+#define DRIVE_CURRENT_LANE1_T114(x)		(((x) & 0x7f) <<  8)
+#define DRIVE_CURRENT_LANE2_T114(x)		(((x) & 0x7f) << 16)
+#define DRIVE_CURRENT_LANE3_T114(x)		(((x) & 0x7f) << 24)
+
+/* Drive current list */
+enum {
+	DRIVE_CURRENT_1_500_mA,
+	DRIVE_CURRENT_1_875_mA,
+	DRIVE_CURRENT_2_250_mA,
+	DRIVE_CURRENT_2_625_mA,
+	DRIVE_CURRENT_3_000_mA,
+	DRIVE_CURRENT_3_375_mA,
+	DRIVE_CURRENT_3_750_mA,
+	DRIVE_CURRENT_4_125_mA,
+	DRIVE_CURRENT_4_500_mA,
+	DRIVE_CURRENT_4_875_mA,
+	DRIVE_CURRENT_5_250_mA,
+	DRIVE_CURRENT_5_625_mA,
+	DRIVE_CURRENT_6_000_mA,
+	DRIVE_CURRENT_6_375_mA,
+	DRIVE_CURRENT_6_750_mA,
+	DRIVE_CURRENT_7_125_mA,
+	DRIVE_CURRENT_7_500_mA,
+	DRIVE_CURRENT_7_875_mA,
+	DRIVE_CURRENT_8_250_mA,
+	DRIVE_CURRENT_8_625_mA,
+	DRIVE_CURRENT_9_000_mA,
+	DRIVE_CURRENT_9_375_mA,
+	DRIVE_CURRENT_9_750_mA,
+	DRIVE_CURRENT_10_125_mA,
+	DRIVE_CURRENT_10_500_mA,
+	DRIVE_CURRENT_10_875_mA,
+	DRIVE_CURRENT_11_250_mA,
+	DRIVE_CURRENT_11_625_mA,
+	DRIVE_CURRENT_12_000_mA,
+	DRIVE_CURRENT_12_375_mA,
+	DRIVE_CURRENT_12_750_mA,
+	DRIVE_CURRENT_13_125_mA,
+	DRIVE_CURRENT_13_500_mA,
+	DRIVE_CURRENT_13_875_mA,
+	DRIVE_CURRENT_14_250_mA,
+	DRIVE_CURRENT_14_625_mA,
+	DRIVE_CURRENT_15_000_mA,
+	DRIVE_CURRENT_15_375_mA,
+	DRIVE_CURRENT_15_750_mA,
+	DRIVE_CURRENT_16_125_mA,
+	DRIVE_CURRENT_16_500_mA,
+	DRIVE_CURRENT_16_875_mA,
+	DRIVE_CURRENT_17_250_mA,
+	DRIVE_CURRENT_17_625_mA,
+	DRIVE_CURRENT_18_000_mA,
+	DRIVE_CURRENT_18_375_mA,
+	DRIVE_CURRENT_18_750_mA,
+	DRIVE_CURRENT_19_125_mA,
+	DRIVE_CURRENT_19_500_mA,
+	DRIVE_CURRENT_19_875_mA,
+	DRIVE_CURRENT_20_250_mA,
+	DRIVE_CURRENT_20_625_mA,
+	DRIVE_CURRENT_21_000_mA,
+	DRIVE_CURRENT_21_375_mA,
+	DRIVE_CURRENT_21_750_mA,
+	DRIVE_CURRENT_22_125_mA,
+	DRIVE_CURRENT_22_500_mA,
+	DRIVE_CURRENT_22_875_mA,
+	DRIVE_CURRENT_23_250_mA,
+	DRIVE_CURRENT_23_625_mA,
+	DRIVE_CURRENT_24_000_mA,
+	DRIVE_CURRENT_24_375_mA,
+	DRIVE_CURRENT_24_750_mA,
+};
+
+/* Drive current list for T114 */
+enum {
+	DRIVE_CURRENT_0_000_mA_T114,
+	DRIVE_CURRENT_0_400_mA_T114,
+	DRIVE_CURRENT_0_800_mA_T114,
+	DRIVE_CURRENT_1_200_mA_T114,
+	DRIVE_CURRENT_1_600_mA_T114,
+	DRIVE_CURRENT_2_000_mA_T114,
+	DRIVE_CURRENT_2_400_mA_T114,
+	DRIVE_CURRENT_2_800_mA_T114,
+	DRIVE_CURRENT_3_200_mA_T114,
+	DRIVE_CURRENT_3_600_mA_T114,
+	DRIVE_CURRENT_4_000_mA_T114,
+	DRIVE_CURRENT_4_400_mA_T114,
+	DRIVE_CURRENT_4_800_mA_T114,
+	DRIVE_CURRENT_5_200_mA_T114,
+	DRIVE_CURRENT_5_600_mA_T114,
+	DRIVE_CURRENT_6_000_mA_T114,
+	DRIVE_CURRENT_6_400_mA_T114,
+	DRIVE_CURRENT_6_800_mA_T114,
+	DRIVE_CURRENT_7_200_mA_T114,
+	DRIVE_CURRENT_7_600_mA_T114,
+	DRIVE_CURRENT_8_000_mA_T114,
+	DRIVE_CURRENT_8_400_mA_T114,
+	DRIVE_CURRENT_8_800_mA_T114,
+	DRIVE_CURRENT_9_200_mA_T114,
+	DRIVE_CURRENT_9_600_mA_T114,
+	DRIVE_CURRENT_10_000_mA_T114,
+	DRIVE_CURRENT_10_400_mA_T114,
+	DRIVE_CURRENT_10_800_mA_T114,
+	DRIVE_CURRENT_11_200_mA_T114,
+	DRIVE_CURRENT_11_600_mA_T114,
+	DRIVE_CURRENT_12_000_mA_T114,
+	DRIVE_CURRENT_12_400_mA_T114,
+	DRIVE_CURRENT_12_800_mA_T114,
+	DRIVE_CURRENT_13_200_mA_T114,
+	DRIVE_CURRENT_13_600_mA_T114,
+	DRIVE_CURRENT_14_000_mA_T114,
+	DRIVE_CURRENT_14_400_mA_T114,
+	DRIVE_CURRENT_14_800_mA_T114,
+	DRIVE_CURRENT_15_200_mA_T114,
+	DRIVE_CURRENT_15_600_mA_T114,
+	DRIVE_CURRENT_16_000_mA_T114,
+	DRIVE_CURRENT_16_400_mA_T114,
+	DRIVE_CURRENT_16_800_mA_T114,
+	DRIVE_CURRENT_17_200_mA_T114,
+	DRIVE_CURRENT_17_600_mA_T114,
+	DRIVE_CURRENT_18_000_mA_T114,
+	DRIVE_CURRENT_18_400_mA_T114,
+	DRIVE_CURRENT_18_800_mA_T114,
+	DRIVE_CURRENT_19_200_mA_T114,
+	DRIVE_CURRENT_19_600_mA_T114,
+	DRIVE_CURRENT_20_000_mA_T114,
+	DRIVE_CURRENT_20_400_mA_T114,
+	DRIVE_CURRENT_20_800_mA_T114,
+	DRIVE_CURRENT_21_200_mA_T114,
+	DRIVE_CURRENT_21_600_mA_T114,
+	DRIVE_CURRENT_22_000_mA_T114,
+	DRIVE_CURRENT_22_400_mA_T114,
+	DRIVE_CURRENT_22_800_mA_T114,
+	DRIVE_CURRENT_23_200_mA_T114,
+	DRIVE_CURRENT_23_600_mA_T114,
+	DRIVE_CURRENT_24_000_mA_T114,
+	DRIVE_CURRENT_24_400_mA_T114,
+	DRIVE_CURRENT_24_800_mA_T114,
+	DRIVE_CURRENT_25_200_mA_T114,
+	DRIVE_CURRENT_25_400_mA_T114,
+	DRIVE_CURRENT_25_800_mA_T114,
+	DRIVE_CURRENT_26_200_mA_T114,
+	DRIVE_CURRENT_26_600_mA_T114,
+	DRIVE_CURRENT_27_000_mA_T114,
+	DRIVE_CURRENT_27_400_mA_T114,
+	DRIVE_CURRENT_27_800_mA_T114,
+	DRIVE_CURRENT_28_200_mA_T114,
+};
+
+/* HDMI_NV_PDISP_AUDIO_FS */
+#define AUDIO_FS_LOW(x)				(((x) & 0xfff) <<  0)
+#define AUDIO_FS_HIGH(x)			(((x) & 0xfff) << 16)
+
+/* HDMI_NV_PDISP_AUDIO_CNTRL0	0x8b */
+#define AUDIO_CNTRL0_ERROR_TOLERANCE(x)		(((x) & 0xff) << 0)
+#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO		(0 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	(1 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL		(2 << 20)
+#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x)	(((x) & 0xff) << 24)
+
+/* HDMI_NV_PDISP_AUDIO_N	0x8c */
+#define AUDIO_N_VALUE(x)			(((x) & 0xfffff) << 0)
+#define AUDIO_N_RESETF				(1 << 20)
+#define AUDIO_N_GENERATE_NORMAL			(0 << 24)
+#define AUDIO_N_GENERATE_ALTERNATE		(1 << 24)
+
+/* HDMI_NV_PDISP_SOR_REFCLK	0x95 */
+#define SOR_REFCLK_DIV_INT(x)			(((x) & 0xff) << 8)
+#define SOR_REFCLK_DIV_FRAC(x)			(((x) & 0x03) << 6)
+
+/* HDMI_NV_PDISP_INPUT_CONTROL	0x97 */
+#define HDMI_SRC_DISPLAYA			(0 << 0)
+#define HDMI_SRC_DISPLAYB			(1 << 0)
+#define ARM_VIDEO_RANGE_FULL			(0 << 1)
+#define ARM_VIDEO_RANGE_LIMITED			(1 << 1)
+
+/* HDMI_NV_PDISP_PE_CURRENT	0x99 */
+#define PE_CURRENT0(x)				(((x) & 0xf) << 0)
+#define PE_CURRENT1(x)				(((x) & 0xf) << 8)
+#define PE_CURRENT2(x)				(((x) & 0xf) << 16)
+#define PE_CURRENT3(x)				(((x) & 0xf) << 24)
+
+enum {
+	PE_CURRENT_0_0_mA,
+	PE_CURRENT_0_5_mA,
+	PE_CURRENT_1_0_mA,
+	PE_CURRENT_1_5_mA,
+	PE_CURRENT_2_0_mA,
+	PE_CURRENT_2_5_mA,
+	PE_CURRENT_3_0_mA,
+	PE_CURRENT_3_5_mA,
+	PE_CURRENT_4_0_mA,
+	PE_CURRENT_4_5_mA,
+	PE_CURRENT_5_0_mA,
+	PE_CURRENT_5_5_mA,
+	PE_CURRENT_6_0_mA,
+	PE_CURRENT_6_5_mA,
+	PE_CURRENT_7_0_mA,
+	PE_CURRENT_7_5_mA,
+};
+
+enum {
+	PE_CURRENT_0_mA_T114,
+	PE_CURRENT_1_mA_T114,
+	PE_CURRENT_2_mA_T114,
+	PE_CURRENT_3_mA_T114,
+	PE_CURRENT_4_mA_T114,
+	PE_CURRENT_5_mA_T114,
+	PE_CURRENT_6_mA_T114,
+	PE_CURRENT_7_mA_T114,
+	PE_CURRENT_8_mA_T114,
+	PE_CURRENT_9_mA_T114,
+	PE_CURRENT_10_mA_T114,
+	PE_CURRENT_11_mA_T114,
+	PE_CURRENT_12_mA_T114,
+	PE_CURRENT_13_mA_T114,
+	PE_CURRENT_14_mA_T114,
+	PE_CURRENT_15_mA_T114,
+};
+
+/* HDMI_NV_PDISP_SOR_AUDIO_CNTRL0	0xac */
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO	(0 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	(1 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL	(2 << 20)
+#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL	(1 << 29)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_SPARE0	0xae */
+#define SOR_AUDIO_SPARE0_HBR_ENABLE		BIT(27)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0	0xba */
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID	BIT(30)
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK	0xffff
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE	0xbd */
+#define SOR_AUDIO_HDA_PRESENSE_VALID		BIT(1)
+#define SOR_AUDIO_HDA_PRESENSE_PRESENT		BIT(0)
+
+/* HDMI_NV_PDISP_INT_STATUS		0xcc */
+#define INT_SCRATCH				BIT(3)
+#define INT_CP_REQUEST				BIT(2)
+#define INT_CODEC_SCRATCH1			BIT(1)
+#define INT_CODEC_SCRATCH0			BIT(0)
+
+/* HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT	0xd1 */
+#define PEAK_CURRENT_LANE0(x)			(((x) & 0x7f) <<  0)
+#define PEAK_CURRENT_LANE1(x)			(((x) & 0x7f) <<  8)
+#define PEAK_CURRENT_LANE2(x)			(((x) & 0x7f) << 16)
+#define PEAK_CURRENT_LANE3(x)			(((x) & 0x7f) << 24)
+
+enum {
+	PEAK_CURRENT_0_000_mA,
+	PEAK_CURRENT_0_200_mA,
+	PEAK_CURRENT_0_400_mA,
+	PEAK_CURRENT_0_600_mA,
+	PEAK_CURRENT_0_800_mA,
+	PEAK_CURRENT_1_000_mA,
+	PEAK_CURRENT_1_200_mA,
+	PEAK_CURRENT_1_400_mA,
+	PEAK_CURRENT_1_600_mA,
+	PEAK_CURRENT_1_800_mA,
+	PEAK_CURRENT_2_000_mA,
+	PEAK_CURRENT_2_200_mA,
+	PEAK_CURRENT_2_400_mA,
+	PEAK_CURRENT_2_600_mA,
+	PEAK_CURRENT_2_800_mA,
+	PEAK_CURRENT_3_000_mA,
+	PEAK_CURRENT_3_200_mA,
+	PEAK_CURRENT_3_400_mA,
+	PEAK_CURRENT_3_600_mA,
+	PEAK_CURRENT_3_800_mA,
+	PEAK_CURRENT_4_000_mA,
+	PEAK_CURRENT_4_200_mA,
+	PEAK_CURRENT_4_400_mA,
+	PEAK_CURRENT_4_600_mA,
+	PEAK_CURRENT_4_800_mA,
+	PEAK_CURRENT_5_000_mA,
+	PEAK_CURRENT_5_200_mA,
+	PEAK_CURRENT_5_400_mA,
+	PEAK_CURRENT_5_600_mA,
+	PEAK_CURRENT_5_800_mA,
+	PEAK_CURRENT_6_000_mA,
+	PEAK_CURRENT_6_200_mA,
+	PEAK_CURRENT_6_400_mA,
+	PEAK_CURRENT_6_600_mA,
+	PEAK_CURRENT_6_800_mA,
+	PEAK_CURRENT_7_000_mA,
+	PEAK_CURRENT_7_200_mA,
+	PEAK_CURRENT_7_400_mA,
+	PEAK_CURRENT_7_600_mA,
+	PEAK_CURRENT_7_800_mA,
+	PEAK_CURRENT_8_000_mA,
+	PEAK_CURRENT_8_200_mA,
+	PEAK_CURRENT_8_400_mA,
+	PEAK_CURRENT_8_600_mA,
+	PEAK_CURRENT_8_800_mA,
+	PEAK_CURRENT_9_000_mA,
+	PEAK_CURRENT_9_200_mA,
+	PEAK_CURRENT_9_400_mA,
+};
+
+#endif /* _TEGRA_HDMI_H */
diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra20/tegra-host1x.c
new file mode 100644
index 00000000000..58ab871a3b4
--- /dev/null
+++ b/drivers/video/tegra20/tegra-host1x.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <log.h>
+#include <reset.h>
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+struct tegra_host1x_info {
+	u32 clk_parent;
+	u32 rate;
+};
+
+static int tegra_host1x_probe(struct udevice *dev)
+{
+	struct clk *clk;
+	struct reset_ctl reset_ctl;
+	const struct tegra_host1x_info *info;
+	int ret;
+
+	clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(clk)) {
+		log_debug("%s: cannot get HOST1X clock: %ld\n",
+			  __func__, PTR_ERR(clk));
+		return PTR_ERR(clk);
+	}
+
+	ret = reset_get_by_name(dev, "host1x", &reset_ctl);
+	if (ret) {
+		log_debug("%s: cannot get HOST1X reset: %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	info = (struct tegra_host1x_info *)dev_get_driver_data(dev);
+
+	reset_assert(&reset_ctl);
+	clock_start_periph_pll(clk->id, info->clk_parent, info->rate);
+
+	mdelay(2);
+	reset_deassert(&reset_ctl);
+
+	return 0;
+}
+
+static const struct tegra_host1x_info tegra20_host1x_info = {
+	.clk_parent = CLOCK_ID_CGENERAL,
+	.rate = 150000000, /* 150 MHz */
+};
+
+static const struct tegra_host1x_info tegra114_host1x_info = {
+	.clk_parent = CLOCK_ID_PERIPH,
+	.rate = 136000000, /* 136 MHz */
+};
+
+static const struct udevice_id tegra_host1x_ids[] = {
+	{
+		.compatible = "nvidia,tegra20-host1x",
+		.data = (ulong)&tegra20_host1x_info
+	}, {
+		.compatible = "nvidia,tegra30-host1x",
+		.data = (ulong)&tegra20_host1x_info
+	}, {
+		.compatible = "nvidia,tegra114-host1x",
+		.data = (ulong)&tegra114_host1x_info
+	}, {
+		.compatible = "nvidia,tegra124-host1x",
+		.data = (ulong)&tegra114_host1x_info
+	}, {
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(tegra_host1x) = {
+	.name		= "tegra_host1x",
+	.id		= UCLASS_SIMPLE_BUS,
+	.of_match	= tegra_host1x_ids,
+	.probe		= tegra_host1x_probe,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c
index 79d8a021a3a..998f0df1991 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra20/tegra-pwm-backlight.c
@@ -17,9 +17,6 @@
 
 #include "tegra-dc.h"
 
-#define TEGRA_DISPLAY_A_BASE		0x54200000
-#define TEGRA_DISPLAY_B_BASE		0x54240000
-
 #define TEGRA_PWM_BL_MIN_BRIGHTNESS	0x10
 #define TEGRA_PWM_BL_MAX_BRIGHTNESS	0xFF
 
@@ -106,14 +103,11 @@ static int tegra_pwm_backlight_enable(struct udevice *dev)
 static int tegra_pwm_backlight_probe(struct udevice *dev)
 {
 	struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev);
+	ofnode dc = ofnode_get_parent(dev_ofnode(dev));
 
-	if (dev_read_bool(dev, "nvidia,display-b-base"))
-		priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_B_BASE;
-	else
-		priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_A_BASE;
-
+	priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc);
 	if (!priv->dc) {
-		log_err("no display controller address\n");
+		log_err("%s: failed to get DC controller\n", __func__);
 		return -EINVAL;
 	}
 
diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c
index 493e2f18cd2..340c79299ba 100644
--- a/drivers/video/ti/tilcdc.c
+++ b/drivers/video/ti/tilcdc.c
@@ -234,7 +234,7 @@ static int tilcdc_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
+	err = uclass_get_device_by_name(UCLASS_CLK, "clock-lcd-gclk@534", &clk_dev);
 	if (err) {
 		dev_err(dev, "failed to get lcd_gclk device\n");
 		return err;
@@ -252,7 +252,7 @@ static int tilcdc_probe(struct udevice *dev)
 		return rate;
 	}
 
-	err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
+	err = uclass_get_device_by_name(UCLASS_CLK, "clock-dpll-disp-m2@4a4",
 					&clk_dev);
 	if (err) {
 		dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
diff --git a/drivers/watchdog/da9063-wdt.c b/drivers/watchdog/da9063-wdt.c
index b7216b57863..ec9bc033011 100644
--- a/drivers/watchdog/da9063-wdt.c
+++ b/drivers/watchdog/da9063-wdt.c
@@ -145,5 +145,4 @@ U_BOOT_DRIVER(da9063_wdt) = {
 	.id = UCLASS_WDT,
 	.of_match = da9063_wdt_ids,
 	.ops = &da9063_wdt_ops,
-	.flags = DM_FLAG_PROBE_AFTER_BIND,
 };
diff --git a/dts/upstream/Bindings/arm/altera/socfpga-system.txt b/dts/upstream/Bindings/arm/altera/socfpga-system.txt
deleted file mode 100644
index 82edbaaa3f8..00000000000
--- a/dts/upstream/Bindings/arm/altera/socfpga-system.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Altera SOCFPGA System Manager
-
-Required properties:
-- compatible : "altr,sys-mgr"
-- reg : Should contain 1 register ranges(address and length)
-- cpu1-start-addr : CPU1 start address in hex.
-
-Example:
-	 sysmgr@ffd08000 {
-		compatible = "altr,sys-mgr";
-		reg = <0xffd08000 0x1000>;
-		cpu1-start-addr = <0xffd080c4>;
-	};
-
-ARM64 - Stratix10
-Required properties:
-- compatible : "altr,sys-mgr-s10"
-- reg : Should contain 1 register range(address and length)
-        for system manager register.
-
-Example:
-	 sysmgr@ffd12000 {
-		compatible = "altr,sys-mgr-s10";
-		reg = <0xffd12000 0x228>;
-	};
diff --git a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
index 04a8c37b4af..742dc4e25d3 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
@@ -38,6 +38,12 @@ properties:
     enum:
       - arm,coresight-dummy-source
 
+  arm,static-trace-id:
+    description: If dummy source needs static id support, use this to set trace id.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 111
+
   out-ports:
     $ref: /schemas/graph.yaml#/properties/ports
 
diff --git a/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml b/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
index 1892a091ac3..a6f793ea03b 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
@@ -45,7 +45,22 @@ properties:
     patternProperties:
       '^port@[01]$':
         description: Output connections to CoreSight Trace bus
-        $ref: /schemas/graph.yaml#/properties/port
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+
+        properties:
+          endpoint:
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
+
+            properties:
+              filter-source:
+                $ref: /schemas/types.yaml#/definitions/phandle
+                description:
+                  phandle to the coresight trace source device matching the
+                  hard coded filtering for this port
+
+              remote-endpoint: true
 
 required:
   - compatible
@@ -72,6 +87,7 @@ examples:
                 reg = <0>;
                 replicator_out_port0: endpoint {
                     remote-endpoint = <&etb_in_port>;
+                    filter-source = <&tpdm_video>;
                 };
             };
 
@@ -79,6 +95,7 @@ examples:
                 reg = <1>;
                 replicator_out_port1: endpoint {
                     remote-endpoint = <&tpiu_in_port>;
+                    filter-source = <&tpdm_mdss>;
                 };
             };
         };
diff --git a/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml b/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
index f725e694099..9c2c9ac9705 100644
--- a/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
+++ b/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
@@ -23,7 +23,7 @@ description: |
 
 properties:
   $nodename:
-    pattern: "^ete([0-9a-f]+)$"
+    pattern: "^ete(-[0-9]+)?$"
   compatible:
     items:
       - const: arm,embedded-trace-extension
@@ -55,13 +55,13 @@ examples:
 
 # An ETE node without legacy CoreSight connections
   - |
-    ete0 {
+    ete-0 {
       compatible = "arm,embedded-trace-extension";
       cpu = <&cpu_0>;
     };
 # An ETE node with legacy CoreSight connections
   - |
-   ete1 {
+   ete-1 {
       compatible = "arm,embedded-trace-extension";
       cpu = <&cpu_1>;
 
diff --git a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
index 2f92b8ab08f..01333ac111f 100644
--- a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
+++ b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
@@ -74,6 +74,7 @@ properties:
       - description: AST2600 based boards
         items:
           - enum:
+              - ampere,mtjefferson-bmc
               - ampere,mtmitchell-bmc
               - aspeed,ast2600-evb
               - aspeed,ast2600-evb-a1
@@ -91,6 +92,7 @@ properties:
               - ibm,everest-bmc
               - ibm,fuji-bmc
               - ibm,rainier-bmc
+              - ibm,sbp1-bmc
               - ibm,system1-bmc
               - ibm,tacoma-bmc
               - inventec,starscream-bmc
diff --git a/dts/upstream/Bindings/arm/atmel-at91.yaml b/dts/upstream/Bindings/arm/atmel-at91.yaml
index 7160ec80ac1..0ec29366e6c 100644
--- a/dts/upstream/Bindings/arm/atmel-at91.yaml
+++ b/dts/upstream/Bindings/arm/atmel-at91.yaml
@@ -180,6 +180,13 @@ properties:
           - const: atmel,sama5d4
           - const: atmel,sama5
 
+      - description: Microchip SAMA7D65 Curiosity Board
+        items:
+          - const: microchip,sama7d65-curiosity
+          - const: microchip,sama7d65
+          - const: microchip,sama7d6
+          - const: microchip,sama7
+
       - items:
           - const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
           - const: microchip,sama7g5
diff --git a/dts/upstream/Bindings/arm/atmel-sysregs.txt b/dts/upstream/Bindings/arm/atmel-sysregs.txt
index 76e2b797825..1a173e92bb1 100644
--- a/dts/upstream/Bindings/arm/atmel-sysregs.txt
+++ b/dts/upstream/Bindings/arm/atmel-sysregs.txt
@@ -13,6 +13,7 @@ PIT Timer required properties:
 PIT64B Timer required properties:
 - compatible: Should be "microchip,sam9x60-pit64b" or
 			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
+			"microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt for PIT64B timer
 - clocks: Should contain the available clock sources for PIT64B timer.
@@ -27,12 +28,13 @@ Its subnodes can be:
 - watchdog: compatible should be "atmel,at91rm9200-wdt"
 
 RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
-			"atmel,at91sam9260-sdramc",
-			"atmel,at91sam9g45-ddramc",
-			"atmel,sama5d3-ddramc",
-			"microchip,sam9x60-ddramc",
-			"microchip,sama7g5-uddrc",
+- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or
+			"atmel,at91sam9260-sdramc" or
+			"atmel,at91sam9g45-ddramc" or
+			"atmel,sama5d3-ddramc" or
+			"microchip,sam9x60-ddramc" or
+			"microchip,sama7g5-uddrc" or
+			"microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or
 			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
 - reg: Should contain registers location and length
 
diff --git a/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml b/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
index 07892cbdd23..354bb1420cd 100644
--- a/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
+++ b/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
@@ -34,6 +34,7 @@ properties:
           - enum:
               - netgear,r8000p
               - tplink,archer-c2300-v1
+              - zyxel,ex3510b
           - const: brcm,bcm4906
           - const: brcm,bcm4908
           - const: brcm,bcmbca
@@ -115,6 +116,7 @@ properties:
         items:
           - enum:
               - brcm,bcm96846
+              - genexis,xg6846b
           - const: brcm,bcm6846
           - const: brcm,bcmbca
 
diff --git a/dts/upstream/Bindings/arm/blaize.yaml b/dts/upstream/Bindings/arm/blaize.yaml
new file mode 100644
index 00000000000..af39e275640
--- /dev/null
+++ b/dts/upstream/Bindings/arm/blaize.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/blaize.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Blaize Platforms
+
+maintainers:
+  - James Cowgill <james.cowgill@blaize.com>
+  - Matt Redfearn <matt.redfearn@blaize.com>
+  - Neil Jones <neil.jones@blaize.com>
+  - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+
+description: |
+  Blaize Platforms using SoCs designed by Blaize Inc.
+
+  The products based on the BLZP1600 SoC:
+
+  - BLZP1600-SoM: SoM (System on Module)
+  - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
+
+  BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
+  and a Blaize Graph Streaming Processor for AI and ML workloads,
+  plus a suite of connectivity and other peripherals.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Blaize BLZP1600 based boards
+        items:
+          - enum:
+              - blaize,blzp1600-cb2
+          - const: blaize,blzp1600
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/arm/fsl.yaml b/dts/upstream/Bindings/arm/fsl.yaml
index 6e0dcf4307f..0db2cbd7891 100644
--- a/dts/upstream/Bindings/arm/fsl.yaml
+++ b/dts/upstream/Bindings/arm/fsl.yaml
@@ -1091,6 +1091,7 @@ properties:
               - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
               - emcraft,imx8mp-navqp      # i.MX8MP Emcraft Systems NavQ+ Kit
               - fsl,imx8mp-evk            # i.MX8MP EVK Board
+              - fsl,imx8mp-evk-revb4      # i.MX8MP EVK Rev B4 Board
               - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
@@ -1106,6 +1107,15 @@ properties:
               - ysoft,imx8mp-iota2-lumpy  # Y Soft i.MX8MP IOTA2 Lumpy Board
           - const: fsl,imx8mp
 
+      - description: ABB Boards with i.MX8M Plus Modules from ADLink
+        items:
+          - enum:
+              - abb,imx8mp-aristanetos3-adpismarc # i.MX8MP ABB SoM on PI SMARC Board
+              - abb,imx8mp-aristanetos3-helios    # i.MX8MP ABB SoM on helios Board
+              - abb,imx8mp-aristanetos3-proton2s  # i.MX8MP ABB SoM on proton2s Board
+          - const: abb,imx8mp-aristanetos3-som    # i.MX8MP ABB SoM
+          - const: fsl,imx8mp
+
       - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
         items:
           - const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E on SM2-MB-EP1 Carrier Board
@@ -1262,6 +1272,7 @@ properties:
         items:
           - enum:
               - fsl,imx8qm-mek           # i.MX8QM MEK Board
+              - fsl,imx8qm-mek-revd      # i.MX8QM MEK Rev D Board
               - toradex,apalis-imx8      # Apalis iMX8 Modules
               - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
           - const: fsl,imx8qm
@@ -1290,6 +1301,7 @@ properties:
           - enum:
               - einfochips,imx8qxp-ai_ml  # i.MX8QXP AI_ML Board
               - fsl,imx8qxp-mek           # i.MX8QXP MEK Board
+              - fsl,imx8qxp-mek-wcpu      # i.MX8QXP MEK WCPU Board
           - const: fsl,imx8qxp
 
       - description: i.MX8DXL based Boards
diff --git a/dts/upstream/Bindings/arm/mediatek.yaml b/dts/upstream/Bindings/arm/mediatek.yaml
index 1d4bb50fcd8..3ce34d68c21 100644
--- a/dts/upstream/Bindings/arm/mediatek.yaml
+++ b/dts/upstream/Bindings/arm/mediatek.yaml
@@ -239,6 +239,34 @@ properties:
           - enum:
               - mediatek,mt8183-pumpkin
           - const: mediatek,mt8183
+      - description: Google Chinchou (Asus Chromebook CZ1104CM2A/CZ1204CM2A)
+        items:
+          - const: google,chinchou-sku0
+          - const: google,chinchou-sku2
+          - const: google,chinchou-sku4
+          - const: google,chinchou-sku5
+          - const: google,chinchou
+          - const: mediatek,mt8186
+      - description: Google Chinchou (Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A)
+        items:
+          - const: google,chinchou-sku1
+          - const: google,chinchou-sku3
+          - const: google,chinchou-sku6
+          - const: google,chinchou-sku7
+          - const: google,chinchou-sku17
+          - const: google,chinchou-sku20
+          - const: google,chinchou-sku22
+          - const: google,chinchou-sku23
+          - const: google,chinchou
+          - const: mediatek,mt8186
+      - description: Google Chinchou360 (Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip)
+        items:
+          - const: google,chinchou-sku16
+          - const: google,chinchou-sku18
+          - const: google,chinchou-sku19
+          - const: google,chinchou-sku21
+          - const: google,chinchou
+          - const: mediatek,mt8186
       - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
         items:
           - const: google,steelix-sku393219
@@ -263,6 +291,19 @@ properties:
           - const: google,steelix-sku196608
           - const: google,steelix
           - const: mediatek,mt8186
+      - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
+        items:
+          - const: google,starmie-sku0
+          - const: google,starmie-sku2
+          - const: google,starmie-sku3
+          - const: google,starmie
+          - const: mediatek,mt8186
+      - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
+        items:
+          - const: google,starmie-sku1
+          - const: google,starmie-sku4
+          - const: google,starmie
+          - const: mediatek,mt8186
       - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
         items:
           - enum:
@@ -307,6 +348,19 @@ properties:
           - enum:
               - mediatek,mt8186-evb
           - const: mediatek,mt8186
+      - description: Google Ciri (Lenovo Chromebook Duet (11", 9))
+        items:
+          - enum:
+              - google,ciri-sku0
+              - google,ciri-sku1
+              - google,ciri-sku2
+              - google,ciri-sku3
+              - google,ciri-sku4
+              - google,ciri-sku5
+              - google,ciri-sku6
+              - google,ciri-sku7
+          - const: google,ciri
+          - const: mediatek,mt8188
       - items:
           - enum:
               - mediatek,mt8188-evb
@@ -316,12 +370,6 @@ properties:
           - const: google,hayato-rev1
           - const: google,hayato
           - const: mediatek,mt8192
-      - description: Google Hayato rev5
-        items:
-          - const: google,hayato-rev5-sku2
-          - const: google,hayato-sku2
-          - const: google,hayato
-          - const: mediatek,mt8192
       - description: Google Spherion (Acer Chromebook 514)
         items:
           - const: google,spherion-rev3
@@ -330,11 +378,6 @@ properties:
           - const: google,spherion-rev0
           - const: google,spherion
           - const: mediatek,mt8192
-      - description: Google Spherion rev4 (Acer Chromebook 514)
-        items:
-          - const: google,spherion-rev4
-          - const: google,spherion
-          - const: mediatek,mt8192
       - items:
           - enum:
               - mediatek,mt8192-evb
diff --git a/dts/upstream/Bindings/arm/qcom-soc.yaml b/dts/upstream/Bindings/arm/qcom-soc.yaml
index d0751a572af..a77d68dcad4 100644
--- a/dts/upstream/Bindings/arm/qcom-soc.yaml
+++ b/dts/upstream/Bindings/arm/qcom-soc.yaml
@@ -23,7 +23,7 @@ description: |
 select:
   properties:
     compatible:
-      pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
   required:
     - compatible
 
@@ -31,7 +31,8 @@ properties:
   compatible:
     oneOf:
       # Preferred naming style for compatibles of SoC components:
-      - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
+      - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
+      - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
       - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
 
       # Legacy namings - variations of existing patterns/compatibles are OK,
@@ -39,9 +40,9 @@ properties:
       - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
       - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
       - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
-      - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
       - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
-      - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
       - enum:
           - qcom,dsi-ctrl-6g-qcm2290
           - qcom,gpucc-sdm630
diff --git a/dts/upstream/Bindings/arm/qcom.yaml b/dts/upstream/Bindings/arm/qcom.yaml
index 9679fed7259..618a87693ac 100644
--- a/dts/upstream/Bindings/arm/qcom.yaml
+++ b/dts/upstream/Bindings/arm/qcom.yaml
@@ -19,29 +19,42 @@ description: |
 
         apq8016
         apq8026
+        apq8064
         apq8074
         apq8084
+        apq8094
         apq8096
         ipq4018
+        ipq4019
         ipq5018
         ipq5332
+        ipq5424
         ipq6018
+        ipq8064
         ipq8074
         ipq9574
         mdm9615
         msm8226
+        msm8660
         msm8916
+        msm8917
+        msm8926
+        msm8929
         msm8939
         msm8953
         msm8956
         msm8960
         msm8974
+        msm8974pro
         msm8976
         msm8992
         msm8994
         msm8996
+        msm8996pro
         msm8998
         qcs404
+        qcs615
+        qcs8300
         qcs8550
         qcm2290
         qcm6490
@@ -53,6 +66,7 @@ description: |
         sa8155p
         sa8540p
         sa8775p
+        sar2130p
         sc7180
         sc7280
         sc8180x
@@ -84,7 +98,10 @@ description: |
         sm8450
         sm8550
         sm8650
+        sm8750
+        x1e78100
         x1e80100
+        x1p42100
 
   There are many devices in the list below that run the standard ChromeOS
   bootloader setup and use the open source depthcharge bootloader to boot the
@@ -252,6 +269,11 @@ properties:
 
       - items:
           - enum:
+              - xiaomi,riva
+          - const: qcom,msm8917
+
+      - items:
+          - enum:
               - motorola,potter
               - xiaomi,daisy
               - xiaomi,mido
@@ -354,6 +376,11 @@ properties:
 
       - items:
           - enum:
+              - qcom,ipq5424-rdp466
+          - const: qcom,ipq5424
+
+      - items:
+          - enum:
               - mikrotik,rb3011
               - qcom,ipq8064-ap148
           - const: qcom,ipq8064
@@ -408,6 +435,12 @@ properties:
               - qcom,qru1000-idp
           - const: qcom,qru1000
 
+      - description: Qualcomm AR2 Gen1 platform
+        items:
+          - enum:
+              - qcom,qar2130p
+          - const: qcom,sar2130p
+
       - items:
           - enum:
               - acer,aspire1
@@ -822,8 +855,10 @@ properties:
 
       - items:
           - enum:
+              - huawei,gaokun3
               - lenovo,thinkpad-x13s
               - microsoft,arcata
+              - microsoft,blackrock
               - qcom,sc8280xp-crd
               - qcom,sc8280xp-qrd
           - const: qcom,sc8280xp
@@ -900,6 +935,16 @@ properties:
 
       - items:
           - enum:
+              - qcom,qcs8300-ride
+          - const: qcom,qcs8300
+
+      - items:
+          - enum:
+              - qcom,qcs615-ride
+          - const: qcom,qcs615
+
+      - items:
+          - enum:
               - qcom,sa8155p-adp
           - const: qcom,sa8155p
 
@@ -1066,6 +1111,18 @@ properties:
 
       - items:
           - enum:
+              - qcom,sm8750-mtp
+              - qcom,sm8750-qrd
+          - const: qcom,sm8750
+
+      - items:
+          - enum:
+              - qcom,x1e001de-devkit
+          - const: qcom,x1e001de
+          - const: qcom,x1e80100
+
+      - items:
+          - enum:
               - lenovo,thinkpad-t14s
           - const: qcom,x1e78100
           - const: qcom,x1e80100
@@ -1074,6 +1131,7 @@ properties:
           - enum:
               - asus,vivobook-s15
               - dell,xps13-9345
+              - hp,omnibook-x14
               - lenovo,yoga-slim7x
               - microsoft,romulus13
               - microsoft,romulus15
@@ -1081,6 +1139,11 @@ properties:
               - qcom,x1e80100-qcp
           - const: qcom,x1e80100
 
+      - items:
+          - enum:
+              - qcom,x1p42100-crd
+          - const: qcom,x1p42100
+
   # Board compatibles go above
 
   qcom,msm-id:
@@ -1158,6 +1221,7 @@ allOf:
               - qcom,apq8026
               - qcom,apq8094
               - qcom,apq8096
+              - qcom,msm8917
               - qcom,msm8939
               - qcom,msm8953
               - qcom,msm8956
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 753199a1292..522a6f0450e 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -81,6 +81,17 @@ properties:
           - const: azw,beelink-a1
           - const: rockchip,rk3328
 
+      - description: BigTreeTech CB2 Manta M4/8P
+        items:
+          - const: bigtreetech,cb2-manta
+          - const: bigtreetech,cb2
+          - const: rockchip,rk3566
+
+      - description: BigTreeTech Pi 2
+        items:
+          - const: bigtreetech,pi2
+          - const: rockchip,rk3566
+
       - description: bq Curie 2 tablet
         items:
           - const: mundoreader,bq-curie2
@@ -167,6 +178,13 @@ properties:
           - const: engicam,px30-core
           - const: rockchip,px30
 
+      - description: Firefly Core-3588J-based boards
+        items:
+          - enum:
+              - firefly,itx-3588j
+          - const: firefly,core-3588j
+          - const: rockchip,rk3588
+
       - description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
         items:
           - const: firefly,px30-jd4-core-mb
@@ -597,6 +615,11 @@ properties:
           - const: google,veyron
           - const: rockchip,rk3288
 
+      - description: H96 Max V58 TV Box
+        items:
+          - const: haochuangyi,h96-max-v58
+          - const: rockchip,rk3588
+
       - description: Haoyu MarsBoard RK3066
         items:
           - const: haoyu,marsboard-rk3066
@@ -812,6 +835,12 @@ properties:
           - const: radxa,e20c
           - const: rockchip,rk3528
 
+      - description: Radxa E52C
+        items:
+          - const: radxa,e52c
+          - const: rockchip,rk3582
+          - const: rockchip,rk3588s
+
       - description: Radxa Rock
         items:
           - const: radxa,rock
@@ -1006,6 +1035,21 @@ properties:
           - const: rockchip,rk3399-sapphire-excavator
           - const: rockchip,rk3399
 
+      - description: Rockchip RK3566 BOX Evaluation Demo board
+        items:
+          - const: rockchip,rk3566-box-demo
+          - const: rockchip,rk3566
+
+      - description: Rockchip RK3568 Evaluation board
+        items:
+          - const: rockchip,rk3568-evb1-v10
+          - const: rockchip,rk3568
+
+      - description: Rockchip RK3576 Evaluation board
+        items:
+          - const: rockchip,rk3576-evb1-v10
+          - const: rockchip,rk3576
+
       - description: Rockchip RK3588 Evaluation board
         items:
           - const: rockchip,rk3588-evb1-v10
@@ -1026,6 +1070,23 @@ properties:
           - const: rockchip,rk3588-toybrick-x0
           - const: rockchip,rk3588
 
+      - description: Sinovoip RK3308 Banana Pi P2 Pro
+        items:
+          - const: sinovoip,rk3308-bpi-p2pro
+          - const: rockchip,rk3308
+
+      - description: Sinovoip RK3568 Banana Pi R2 Pro
+        items:
+          - const: sinovoip,rk3568-bpi-r2pro
+          - const: rockchip,rk3568
+
+      - description: Sonoff iHost Smart Home Hub
+        items:
+          - const: itead,sonoff-ihost
+          - enum:
+              - rockchip,rv1126
+              - rockchip,rv1109
+
       - description: Theobroma Systems PX30-uQ7 with Haikou baseboard
         items:
           - const: tsd,px30-ringneck-haikou
@@ -1075,9 +1136,11 @@ properties:
           - const: xunlong,orangepi-3b
           - const: rockchip,rk3566
 
-      - description: Xunlong Orange Pi 5 Plus
+      - description: Xunlong Orange Pi 5 Max/Plus
         items:
-          - const: xunlong,orangepi-5-plus
+          - enum:
+              - xunlong,orangepi-5-max
+              - xunlong,orangepi-5-plus
           - const: rockchip,rk3588
 
       - description: Xunlong Orange Pi R1 Plus / LTS
@@ -1099,33 +1162,6 @@ properties:
           - const: zkmagic,a95x-z2
           - const: rockchip,rk3318
 
-      - description: Rockchip RK3566 BOX Evaluation Demo board
-        items:
-          - const: rockchip,rk3566-box-demo
-          - const: rockchip,rk3566
-
-      - description: Rockchip RK3568 Evaluation board
-        items:
-          - const: rockchip,rk3568-evb1-v10
-          - const: rockchip,rk3568
-
-      - description: Sinovoip RK3308 Banana Pi P2 Pro
-        items:
-          - const: sinovoip,rk3308-bpi-p2pro
-          - const: rockchip,rk3308
-
-      - description: Sinovoip RK3568 Banana Pi R2 Pro
-        items:
-          - const: sinovoip,rk3568-bpi-r2pro
-          - const: rockchip,rk3568
-
-      - description: Sonoff iHost Smart Home Hub
-        items:
-          - const: itead,sonoff-ihost
-          - enum:
-              - rockchip,rv1126
-              - rockchip,rv1109
-
 additionalProperties: true
 
 ...
diff --git a/dts/upstream/Bindings/arm/rockchip/pmu.yaml b/dts/upstream/Bindings/arm/rockchip/pmu.yaml
index 932f981265c..52016a14122 100644
--- a/dts/upstream/Bindings/arm/rockchip/pmu.yaml
+++ b/dts/upstream/Bindings/arm/rockchip/pmu.yaml
@@ -53,11 +53,17 @@ properties:
   reg:
     maxItems: 1
 
+  power-controller:
+    type: object
+
+  reboot-mode:
+    type: object
+
 required:
   - compatible
   - reg
 
-additionalProperties: true
+additionalProperties: false
 
 examples:
   - |
diff --git a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
index b5ba5ffc36d..fab29f95d8e 100644
--- a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
+++ b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
@@ -240,6 +240,9 @@ properties:
         items:
           - enum:
               - samsung,c1s                     # Samsung Galaxy Note20 5G (SM-N981B)
+              - samsung,r8s                     # Samsung Galaxy S20 FE (SM-G780F)
+              - samsung,x1s                     # Samsung Galaxy S20 5G (SM-G981B)
+              - samsung,x1slte                  # Samsung Galaxy S20 (SM-G980F)
           - const: samsung,exynos990
 
       - description: Exynos Auto v9 based boards
diff --git a/dts/upstream/Bindings/arm/stm32/stm32.yaml b/dts/upstream/Bindings/arm/stm32/stm32.yaml
index 703d4b57439..b6c56d4ce6b 100644
--- a/dts/upstream/Bindings/arm/stm32/stm32.yaml
+++ b/dts/upstream/Bindings/arm/stm32/stm32.yaml
@@ -91,6 +91,13 @@ properties:
           - const: dh,stm32mp153c-dhcor-som
           - const: st,stm32mp153
 
+      - description: Octavo OSD32MP153 System-in-Package based boards
+        items:
+          - enum:
+              - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3)
+          - const: oct,stm32mp153x-osd32
+          - const: st,stm32mp153
+
       - items:
           - enum:
               - shiratech,stm32mp157a-iot-box # IoT Box
diff --git a/dts/upstream/Bindings/cache/qcom,llcc.yaml b/dts/upstream/Bindings/cache/qcom,llcc.yaml
index 03b1941eaa3..e5effbb4a60 100644
--- a/dts/upstream/Bindings/cache/qcom,llcc.yaml
+++ b/dts/upstream/Bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,ipq5424-llcc
       - qcom,qcs615-llcc
       - qcom,qcs8300-llcc
       - qcom,qdu1000-llcc
@@ -42,11 +43,11 @@ properties:
       - qcom,x1e80100-llcc
 
   reg:
-    minItems: 2
+    minItems: 1
     maxItems: 10
 
   reg-names:
-    minItems: 2
+    minItems: 1
     maxItems: 10
 
   interrupts:
@@ -71,6 +72,21 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq5424-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+        reg-names:
+          items:
+            - const: llcc0_base
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
               - qcom,sar1130p-llcc
               - qcom,sar2130p-llcc
     then:
diff --git a/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml b/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml
deleted file mode 100644
index c94ab8f9e0b..00000000000
--- a/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ChromeOS keyboard backlight LED driver.
-
-maintainers:
-  - Tzung-Bi Shih <tzungbi@kernel.org>
-
-properties:
-  compatible:
-    const: google,cros-kbd-led-backlight
-
-required:
-  - compatible
-
-additionalProperties: false
-
-examples:
-  - |
-    spi {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      cros_ec: ec@0 {
-        compatible = "google,cros-ec-spi";
-        reg = <0>;
-        interrupts = <15 0>;
-
-        kbd-led-backlight {
-          compatible = "google,cros-kbd-led-backlight";
-        };
-      };
-    };
diff --git a/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml b/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
index c9eb60776b4..885d47dd572 100644
--- a/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -43,6 +43,7 @@ properties:
               - atmel,sama5d4-pmc
               - microchip,sam9x60-pmc
               - microchip,sam9x7-pmc
+              - microchip,sama7d65-pmc
               - microchip,sama7g5-pmc
           - const: syscon
 
@@ -90,6 +91,7 @@ allOf:
             enum:
               - microchip,sam9x60-pmc
               - microchip,sam9x7-pmc
+              - microchip,sama7d65-pmc
               - microchip,sama7g5-pmc
     then:
       properties:
diff --git a/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml b/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
index c2283cd07f0..d4cf8ae2961 100644
--- a/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -20,6 +20,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-sckc
+              - microchip,sama7d65-sckc
               - microchip,sama7g5-sckc
           - const: microchip,sam9x60-sckc
 
diff --git a/dts/upstream/Bindings/clock/qcom,gpucc.yaml b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
index 0858fd63528..4cdff6161bf 100644
--- a/dts/upstream/Bindings/clock/qcom,gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller
 
 maintainers:
   - Taniya Das <quic_tdas@quicinc.com>
+  - Imran Shaik <quic_imrashai@quicinc.com>
 
 description: |
   Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,10 +24,12 @@ description: |
     include/dt-bindings/clock/qcom,gpucc-sm8150.h
     include/dt-bindings/clock/qcom,gpucc-sm8250.h
     include/dt-bindings/clock/qcom,gpucc-sm8350.h
+    include/dt-bindings/clock/qcom,qcs8300-gpucc.h
 
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-gpucc
       - qcom,sdm845-gpucc
       - qcom,sa8775p-gpucc
       - qcom,sc7180-gpucc
diff --git a/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml b/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
new file mode 100644
index 00000000000..f869b3739be
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Luo Jie <quic_luoj@quicinc.com>
+
+description:
+  The CMN (or common) PLL clock controller expects a reference
+  input clock. This reference clock is from the on-board Wi-Fi.
+  The CMN PLL supplies a number of fixed rate output clocks to
+  the devices providing networking functions and to GCC. These
+  networking hardware include PPE (packet process engine), PCS
+  and the externally connected switch or PHY devices. The CMN
+  PLL block also outputs fixed rate clocks to GCC. The PLL's
+  primary function is to enable fixed rate output clocks for
+  networking hardware functions used with the IPQ SoC.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq9574-cmn-pll
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: The reference clock. The supported clock rates include
+          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
+      - description: The AHB clock
+      - description: The SYS clock
+    description:
+      The reference clock is the source clock of CMN PLL, which is from the
+      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
+      clock registers.
+
+  clock-names:
+    items:
+      - const: ref
+      - const: ahb
+      - const: sys
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
+    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+    cmn_pll: clock-controller@9b000 {
+        compatible = "qcom,ipq9574-cmn-pll";
+        reg = <0x0009b000 0x800>;
+        clocks = <&cmn_pll_ref_clk>,
+                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+        clock-names = "ref", "ahb", "sys";
+        #clock-cells = <1>;
+        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,mmcc.yaml b/dts/upstream/Bindings/clock/qcom,mmcc.yaml
index aa35a40648b..59ac288ca5f 100644
--- a/dts/upstream/Bindings/clock/qcom,mmcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,mmcc.yaml
@@ -78,6 +78,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 8
           items:
             - description: Board PXO source
             - description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf:
             - description: DSI phy instance 2 dsi clock
             - description: DSI phy instance 2 byte clock
             - description: HDMI phy PLL clock
+            - description: LVDS PLL clock
 
         clock-names:
+          minItems: 8
           items:
             - const: pxo
             - const: pll3
@@ -98,6 +101,7 @@ allOf:
             - const: dsi2pll
             - const: dsi2pllbyte
             - const: hdmipll
+            - const: lvdspll
 
   - if:
       properties:
diff --git a/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml b/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
new file mode 100644
index 00000000000..4a828e102d2
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on QCS615
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on QCS615.
+
+  See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
+
+properties:
+  compatible:
+    const: qcom,qcs615-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: bi_tcxo_ao
+      - const: sleep_clk
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,qcs615-gcc";
+      reg = <0x00100000 0x1f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
index 02fcffe93f1..be3835e2e04 100644
--- a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
@@ -33,6 +33,8 @@ properties:
           - qcom,rpmcc-msm8916
           - qcom,rpmcc-msm8917
           - qcom,rpmcc-msm8936
+          - qcom,rpmcc-msm8937
+          - qcom,rpmcc-msm8940
           - qcom,rpmcc-msm8953
           - qcom,rpmcc-msm8974
           - qcom,rpmcc-msm8976
@@ -110,6 +112,8 @@ allOf:
               - qcom,rpmcc-msm8916
               - qcom,rpmcc-msm8917
               - qcom,rpmcc-msm8936
+              - qcom,rpmcc-msm8937
+              - qcom,rpmcc-msm8940
               - qcom,rpmcc-msm8953
               - qcom,rpmcc-msm8974
               - qcom,rpmcc-msm8976
diff --git a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
index a561a306b94..dcb872b9cf3 100644
--- a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
@@ -17,6 +17,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs615-rpmh-clk
       - qcom,qdu1000-rpmh-clk
       - qcom,sa8775p-rpmh-clk
       - qcom,sar2130p-rpmh-clk
@@ -37,6 +38,7 @@ properties:
       - qcom,sm8450-rpmh-clk
       - qcom,sm8550-rpmh-clk
       - qcom,sm8650-rpmh-clk
+      - qcom,sm8750-rpmh-clk
       - qcom,x1e80100-rpmh-clk
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
index 36a60d8f5ae..81623f59d11 100644
--- a/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
@@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P
 
 maintainers:
   - Taniya Das <quic_tdas@quicinc.com>
+  - Imran Shaik <quic_imrashai@quicinc.com>
 
 description: |
   Qualcomm camera clock control module provides the clocks, resets and power
   domains on SA8775p.
 
-  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
+  See also:
+    include/dt-bindings/clock/qcom,qcs8300-camcc.h
+    include/dt-bindings/clock/qcom,sa8775p-camcc.h
 
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-camcc
       - qcom,sa8775p-camcc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
index 928131bff4c..07e5d811d81 100644
--- a/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
@@ -18,6 +18,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-videocc
       - qcom,sa8775p-videocc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
index deee5423d66..488d6395942 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -18,12 +18,6 @@ description: |
     include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
 
 properties:
-  clocks: true
-
-  clock-names: true
-
-  reg: true
-
   compatible:
     enum:
       - qcom,sc7280-lpassaoncc
@@ -31,12 +25,24 @@ properties:
       - qcom,sc7280-lpasscorecc
       - qcom,sc7280-lpasshm
 
-  power-domains:
-    maxItems: 1
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    maxItems: 3
 
   '#clock-cells':
     const: 1
 
+  power-domains:
+    maxItems: 1
+
   '#power-domain-cells':
     const: 1
 
@@ -57,8 +63,6 @@ required:
   - '#clock-cells'
   - '#power-domain-cells'
 
-additionalProperties: false
-
 allOf:
   - if:
       properties:
@@ -125,6 +129,9 @@ allOf:
 
         reg:
           maxItems: 1
+
+additionalProperties: false
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
index 810b852ae37..fa95c3a1ba3 100644
--- a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
@@ -20,7 +20,11 @@ allOf:
 
 properties:
   compatible:
-    const: qcom,sdm845-camcc
+    oneOf:
+      - items:
+          - const: qcom,sdm670-camcc
+          - const: qcom,sdm845-camcc
+      - const: qcom,sdm845-camcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml b/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 00000000000..8cbab3fbb66
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+  - Konrad Dybcio <konradybcio@kernel.org>
+  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+  Qualcomm LPASS core and audio clock controllers provide audio-related resets
+  on SM6115 and its derivatives.
+
+  See also::
+    include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm6115-lpassaudiocc
+      - qcom,sm6115-lpasscc
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    lpass_audiocc: clock-controller@a6a9000 {
+        compatible = "qcom,sm6115-lpassaudiocc";
+        reg = <0x0a6a9000 0x1000>;
+        #reset-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
index 0766f66c7dc..b88b6c9b399 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -19,7 +19,6 @@ description: |
     include/dt-bindings/clock/qcom,sm8450-camcc.h
     include/dt-bindings/clock/qcom,sm8550-camcc.h
     include/dt-bindings/clock/qcom,sm8650-camcc.h
-    include/dt-bindings/clock/qcom,x1e80100-camcc.h
 
 properties:
   compatible:
@@ -29,7 +28,6 @@ properties:
       - qcom,sm8475-camcc
       - qcom,sm8550-camcc
       - qcom,sm8650-camcc
-      - qcom,x1e80100-camcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
index 5c65f5ecf0f..02968632fb3 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -32,6 +32,7 @@ properties:
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
       - qcom,x1e80100-gpucc
+      - qcom,x1p42100-gpucc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
index c57d55a9293..30e4b463157 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
@@ -12,11 +12,12 @@ maintainers:
 
 description: |
   Qualcomm display clock control module provides the clocks, resets and power
-  domains on SM8550.
+  domains on SM8550, SM8650, SM8750 and few other platforms.
 
   See also:
   - include/dt-bindings/clock/qcom,sm8550-dispcc.h
   - include/dt-bindings/clock/qcom,sm8650-dispcc.h
+  - include/dt-bindings/clock/qcom,sm8750-dispcc.h
   - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
 
 properties:
@@ -25,6 +26,7 @@ properties:
       - qcom,sar2130p-dispcc
       - qcom,sm8550-dispcc
       - qcom,sm8650-dispcc
+      - qcom,sm8750-dispcc
       - qcom,x1e80100-dispcc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
index 3b546deb514..f3afbb25e86 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
@@ -16,6 +16,7 @@ description: |
   See also:
   - include/dt-bindings/clock/qcom,sm8550-tcsr.h
   - include/dt-bindings/clock/qcom,sm8650-tcsr.h
+  - include/dt-bindings/clock/qcom,sm8750-tcsr.h
 
 properties:
   compatible:
@@ -24,6 +25,7 @@ properties:
           - qcom,sar2130p-tcsr
           - qcom,sm8550-tcsr
           - qcom,sm8650-tcsr
+          - qcom,sm8750-tcsr
           - qcom,x1e80100-tcsr
       - const: syscon
 
diff --git a/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
new file mode 100644
index 00000000000..aab7039fd28
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM8750
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on SM8750
+
+  See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
+
+properties:
+  compatible:
+    const: qcom,sm8750-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board Always On XO source
+      - description: Sleep clock source
+      - description: PCIE 0 Pipe clock source
+      - description: UFS Phy Rx symbol 0 clock source
+      - description: UFS Phy Rx symbol 1 clock source
+      - description: UFS Phy Tx symbol 0 clock source
+      - description: USB3 Phy wrapper pipe clock source
+
+required:
+  - compatible
+  - clocks
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,sm8750-gcc";
+      reg = <0x00100000 0x001f4200>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>,
+               <&pcie0_phy>,
+               <&ufs_mem_phy 0>,
+               <&ufs_mem_phy 1>,
+               <&ufs_mem_phy 2>,
+               <&usb_1_qmpphy>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
new file mode 100644
index 00000000000..5bbbaa15a26
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on x1e80100
+
+maintainers:
+  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+  Qualcomm camera clock control module provides the clocks, resets and power
+  domains on x1e80100.
+
+  See also:
+    include/dt-bindings/clock/qcom,x1e80100-camcc.h
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+properties:
+  compatible:
+    enum:
+      - qcom,x1e80100-camcc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Camera AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  power-domains:
+    items:
+      - description: A phandle to the MXC power-domain
+      - description: A phandle to the MMCX power-domain
+
+  required-opps:
+    maxItems: 1
+    description:
+      A phandle to an OPP node describing MMCX performance points.
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - required-opps
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    clock-controller@ade0000 {
+      compatible = "qcom,x1e80100-camcc";
+      reg = <0xade0000 0x20000>;
+      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd RPMHPD_MXC>,
+                      <&rpmhpd RPMHPD_MMCX>;
+      required-opps = <&rpmhpd_opp_low_svs>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
index 5951a60ab08..28797d0c5d8 100644
--- a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
@@ -17,7 +17,11 @@ description: |
 
 properties:
   compatible:
-    const: qcom,x1e80100-gcc
+    oneOf:
+      - items:
+          - const: qcom,x1p42100-gcc
+          - const: qcom,x1e80100-gcc
+      - const: qcom,x1e80100-gcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/renesas,5p35023.yaml b/dts/upstream/Bindings/clock/renesas,5p35023.yaml
index 42b6f80613f..162d3803518 100644
--- a/dts/upstream/Bindings/clock/renesas,5p35023.yaml
+++ b/dts/upstream/Bindings/clock/renesas,5p35023.yaml
@@ -31,6 +31,7 @@ description: |
 properties:
   compatible:
     enum:
+      - renesas,5l35023
       - renesas,5p35023
 
   reg:
diff --git a/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml b/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
index 926c503bed1..c3fe76abd54 100644
--- a/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
@@ -4,19 +4,22 @@
 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
-  and control of clock signals for the IP modules, generation and control of resets,
-  and control over booting, low power consumption and power supply domains.
+  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+  generation and control of clock signals for the IP modules, generation and
+  control of resets, and control over booting, low power consumption and power
+  supply domains.
 
 properties:
   compatible:
-    const: renesas,r9a09g057-cpg
+    enum:
+      - renesas,r9a09g047-cpg # RZ/G3E
+      - renesas,r9a09g057-cpg # RZ/V2H
 
   reg:
     maxItems: 1
@@ -37,7 +40,7 @@ properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
         a module number.  The module number is calculated as the CLKON register
         offset index multiplied by 16, plus the actual bit in the register
diff --git a/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml b/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
new file mode 100644
index 00000000000..9e7944b5f13
--- /dev/null
+++ b/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos990 SoC clock controller
+
+maintainers:
+  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  Exynos990 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (26 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/samsung,exynos990.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos990-cmu-hsi0
+      - samsung,exynos990-cmu-top
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - "#clock-cells"
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos990-cmu-hsi0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_HSI0 BUS clock (from CMU_TOP)
+            - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
+            - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
+            - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: usb31drd
+            - const: usbdp_debug
+            - const: dpgtc
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos990-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/samsung,exynos990.h>
+
+    cmu_hsi0: clock-controller@10a00000 {
+        compatible = "samsung,exynos990-cmu-hsi0";
+        reg = <0x10a00000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
+        clock-names = "oscclk",
+                      "bus",
+                      "usb31drd",
+                      "usbdp_debug",
+                      "dpgtc";
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/st,stm32-rcc.txt b/dts/upstream/Bindings/clock/st,stm32-rcc.txt
deleted file mode 100644
index cfa04b614d8..00000000000
--- a/dts/upstream/Bindings/clock/st,stm32-rcc.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-STMicroelectronics STM32 Reset and Clock Controller
-===================================================
-
-The RCC IP is both a reset and a clock controller.
-
-Please refer to clock-bindings.txt for common clock controller binding usage.
-Please also refer to reset.txt for common reset controller binding usage.
-
-Required properties:
-- compatible: Should be:
-  "st,stm32f42xx-rcc"
-  "st,stm32f469-rcc"
-  "st,stm32f746-rcc"
-  "st,stm32f769-rcc"
-
-- reg: should be register base and length as documented in the
-  datasheet
-- #reset-cells: 1, see below
-- #clock-cells: 2, device nodes should specify the clock in their "clocks"
-  property, containing a phandle to the clock device node, an index selecting
-  between gated clocks and other clocks and an index specifying the clock to
-  use.
-- clocks: External oscillator clock phandle
-  - high speed external clock signal (HSE)
-  - external I2S clock (I2S_CKIN)
-
-Example:
-
-	rcc: rcc@40023800 {
-		#reset-cells = <1>;
-		#clock-cells = <2>
-		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-		reg = <0x40023800 0x400>;
-		clocks = <&clk_hse>, <&clk_i2s_ckin>;
-	};
-
-Specifying gated clocks
-=======================
-
-The primary index must be set to 0.
-
-The secondary index is the bit number within the RCC register bank, starting
-from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
-
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
-
-To simplify the usage and to share bit definition with the reset and clock
-drivers of the RCC IP, macros are available to generate the index in
-human-readble format.
-
-For STM32F4 series, the macro are available here:
- - include/dt-bindings/mfd/stm32f4-rcc.h
-
-Example:
-
-	/* Gated clock, AHB1 bit 0 (GPIOA) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
-	};
-
-	/* Gated clock, AHB2 bit 4 (CRYP) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
-	};
-
-Specifying other clocks
-=======================
-
-The primary index must be set to 1.
-
-The secondary index is bound with the following magic numbers:
-
-	0	SYSTICK
-	1	FCLK
-	2	CLK_LSI		(low-power clock source)
-	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
-				 crystal or ceramic resonator)
-	4	CLK_HSE_RTC	(HSE division factor for RTC clock)
-	5	CLK_RTC		(real-time clock)
-	6	PLL_VCO_I2S	(vco frequency of I2S pll)
-	7	PLL_VCO_SAI	(vco frequency of SAI pll)
-	8	CLK_LCD		(LCD-TFT)
-	9	CLK_I2S		(I2S clocks)
-	10	CLK_SAI1	(audio clocks)
-	11	CLK_SAI2
-	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
-	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)
-
-	14	CLK_HSI		(Internal ocscillator clock)
-	15	CLK_SYSCLK	(System Clock)
-	16	CLK_HDMI_CEC	(HDMI-CEC clock)
-	17	CLK_SPDIF	(SPDIF-Rx clock)
-	18	CLK_USART1	(U(s)arts clocks)
-	19	CLK_USART2
-	20	CLK_USART3
-	21	CLK_UART4
-	22	CLK_UART5
-	23	CLK_USART6
-	24	CLK_UART7
-	25	CLK_UART8
-	26	CLK_I2C1	(I2S clocks)
-	27	CLK_I2C2
-	28	CLK_I2C3
-	29	CLK_I2C4
-	30	CLK_LPTIMER	(LPTimer1 clock)
-	31	CLK_PLL_SRC
-	32	CLK_DFSDM1
-	33	CLK_ADFSDM1
-	34	CLK_F769_DSI
-)
-
-Example:
-
-	/* Misc clock, FCLK */
-	... {
-		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
-	};
-
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-For example, for CRC reset:
-  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
-
-example:
-
-	timer2 {
-		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
-	};
diff --git a/dts/upstream/Bindings/clock/st,stm32-rcc.yaml b/dts/upstream/Bindings/clock/st,stm32-rcc.yaml
new file mode 100644
index 00000000000..f83a6120d65
--- /dev/null
+++ b/dts/upstream/Bindings/clock/st,stm32-rcc.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Reset Clock Controller
+
+maintainers:
+  - Dario Binacchi <dario.binacchi@amarulasolutions.com>
+
+description: |
+  The RCC IP is both a reset and a clock controller.
+  The reset phandle argument is the bit number within the RCC registers bank,
+  starting from RCC base address.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - st,stm32f42xx-rcc
+              - st,stm32f746-rcc
+              - st,stm32h743-rcc
+          - const: st,stm32-rcc
+      - items:
+          - enum:
+              - st,stm32f469-rcc
+          - const: st,stm32f42xx-rcc
+          - const: st,stm32-rcc
+      - items:
+          - enum:
+              - st,stm32f769-rcc
+          - const: st,stm32f746-rcc
+          - const: st,stm32-rcc
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#clock-cells':
+    enum: [1, 2]
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  st,syscfg:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to system configuration controller. It can be used to control the
+      power domain circuitry.
+
+  st,ssc-modfreq-hz:
+    description:
+      The modulation frequency for main PLL (in Hz)
+
+  st,ssc-moddepth-permyriad:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The modulation rate for main PLL (in permyriad, i.e. 0.01%)
+    minimum: 25
+    maximum: 200
+
+  st,ssc-modmethod:
+    $ref: /schemas/types.yaml#/definitions/string
+    description:
+      The modulation techniques for main PLL.
+    items:
+      enum:
+        - center-spread
+        - down-spread
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+  - '#clock-cells'
+  - clocks
+  - st,syscfg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32h743-rcc
+    then:
+      properties:
+        '#clock-cells':
+          const: 1
+          description: |
+            The clock index for the specified type.
+        clocks:
+          items:
+            - description: high speed external (HSE) clock input
+            - description: low speed external (LSE) clock input
+            - description: Inter-IC sound (I2S) clock input
+        st,ssc-modfreq-hz: false
+        st,ssc-moddepth-permyriad: false
+        st,ssc-modmethod: false
+
+    else:
+      properties:
+        '#clock-cells':
+          const: 2
+          description: |
+            - The first cell is the clock type, possible values are 0 for
+              gated clocks and 1 otherwise.
+            - The second cell is the clock index for the specified type.
+        clocks:
+          items:
+            - description: high speed external (HSE) clock input
+            - description: Inter-IC sound (I2S) clock input
+
+additionalProperties: false
+
+examples:
+  # Reset and Clock Control Module node:
+  - |
+    clock-controller@40023800 {
+        compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+        reg = <0x40023800 0x400>;
+        #clock-cells = <2>;
+        #reset-cells = <1>;
+        clocks = <&clk_hse>, <&clk_i2s_ckin>;
+        st,syscfg = <&pwrcfg>;
+        st,ssc-modfreq-hz = <10000>;
+        st,ssc-moddepth-permyriad = <200>;
+        st,ssc-modmethod = "center-spread";
+    };
+  - |
+    clock-controller@58024400 {
+        compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+        reg = <0x58024400 0x400>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+        st,syscfg = <&pwrcfg>;
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml b/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
index 9b3aaae546c..e72f46e79b9 100644
--- a/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
+++ b/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
@@ -21,7 +21,7 @@ description: |
   =================
 
   All available clocks are defined as preprocessor macros in
-  dt-bindings/clock/stm32mp1-clks.h header and can be used in device
+  include/dt-bindings/clock/stm32mp1-clks.h header and can be used in device
   tree sources.
 
   Specifying softreset control of devices
@@ -40,8 +40,8 @@ description: |
           = 0x180 / 4 * 32 + 0 = 3072
 
   The list of valid indices for STM32MP1 is available in:
-  include/dt-bindings/reset-controller/stm32mp1-resets.h
-  include/dt-bindings/reset-controller/stm32mp13-resets.h
+  include/dt-bindings/reset/stm32mp1-resets.h
+  include/dt-bindings/reset/stm32mp13-resets.h
 
   This file implements defines like:
   #define LTDC_R	3072
diff --git a/dts/upstream/Bindings/clock/ti/composite.txt b/dts/upstream/Bindings/clock/ti/composite.txt
deleted file mode 100644
index 238e6f7d74f..00000000000
--- a/dts/upstream/Bindings/clock/ti/composite.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Binding for TI composite clock.
-
-This binding uses the common clock binding[1]. It assumes a
-register-mapped composite clock with multiple different sub-types;
-
-a multiplexer clock with multiple input clock signals or parents, one
-of which can be selected as output, this behaves exactly as [2]
-
-an adjustable clock rate divider, this behaves exactly as [3]
-
-a gating function which can be used to enable and disable the output
-clock, this behaves exactly as [4]
-
-The binding must provide a list of the component clocks that shall be
-merged to this clock. The component clocks shall be of one of the
-"ti,*composite*-clock" types.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
-[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
-[4] Documentation/devicetree/bindings/clock/ti/gate.txt
-
-Required properties:
-- compatible : shall be: "ti,composite-clock"
-- clocks : link phandles of component clocks
-- #clock-cells : from common clock binding; shall be set to 0.
-
-Optional properties:
-- clock-output-names : from common clock binding.
-
-Examples:
-
-usb_l4_gate_ick: usb_l4_gate_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-interface-clock";
-	clocks = <&l4_ick>;
-	ti,bit-shift = <5>;
-	reg = <0x0a10>;
-};
-
-usb_l4_div_ick: usb_l4_div_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-divider-clock";
-	clocks = <&l4_ick>;
-	ti,bit-shift = <4>;
-	ti,max-div = <1>;
-	reg = <0x0a40>;
-	ti,index-starts-at-one;
-};
-
-usb_l4_ick: usb_l4_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-clock";
-	clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
-};
diff --git a/dts/upstream/Bindings/clock/ti/gate.txt b/dts/upstream/Bindings/clock/ti/gate.txt
deleted file mode 100644
index a8e0335b006..00000000000
--- a/dts/upstream/Bindings/clock/ti/gate.txt
+++ /dev/null
@@ -1,105 +0,0 @@
-Binding for Texas Instruments gate clock.
-
-This binding uses the common clock binding[1]. This clock is
-quite much similar to the basic gate-clock [2], however,
-it supports a number of additional features. If no register
-is provided for this clock, the code assumes that a clockdomain
-will be controlled instead and the corresponding hw-ops for
-that is used.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
-[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
-
-Required properties:
-- compatible : shall be one of:
-  "ti,gate-clock" - basic gate clock
-  "ti,wait-gate-clock" - gate clock which waits until clock is active before
-			 returning from clk_enable()
-  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
-  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
-  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
-			  clock directly from a clockdomain, see [3] how
-			  to map clockdomains properly
-  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
-			  required for a hardware errata
-  "ti,composite-gate-clock" - composite gate clock, to be part of composite
-			      clock
-  "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
-				      for clock to be active before returning
-				      from clk_enable()
-- #clock-cells : from common clock binding; shall be set to 0
-- clocks : link to phandle of parent clock
-- reg : offset for register controlling adjustable gate, not needed for
-	ti,clkdm-gate-clock type
-
-Optional properties:
-- clock-output-names : from common clock binding.
-- ti,bit-shift : bit shift for programming the clock gate, invalid for
-		 ti,clkdm-gate-clock type
-- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
-  gates the clock and clearing the bit ungates the clock.
-
-Examples:
-	mmchs2_fck: mmchs2_fck@48004a00 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&core_96m_fck>;
-		reg = <0x0a00>;
-		ti,bit-shift = <25>;
-	};
-
-	uart4_fck_am35xx: uart4_fck_am35xx {
-		#clock-cells = <0>;
-		compatible = "ti,wait-gate-clock";
-		clocks = <&core_48m_fck>;
-		reg = <0x0a00>;
-		ti,bit-shift = <23>;
-	};
-
-	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
-		#clock-cells = <0>;
-		compatible = "ti,dss-gate-clock";
-		clocks = <&dpll4_m4x2_ck>;
-		reg = <0x0e00>;
-		ti,bit-shift = <0>;
-	};
-
-	emac_ick: emac_ick@4800259c {
-		#clock-cells = <0>;
-		compatible = "ti,am35xx-gate-clock";
-		clocks = <&ipss_ick>;
-		reg = <0x059c>;
-		ti,bit-shift = <1>;
-	};
-
-	emu_src_ck: emu_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,clkdm-gate-clock";
-		clocks = <&emu_src_mux_ck>;
-	};
-
-	dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
-		#clock-cells = <0>;
-		compatible = "ti,hsdiv-gate-clock";
-		clocks = <&dpll4_m2x2_mul_ck>;
-		ti,bit-shift = <0x1b>;
-		reg = <0x0d00>;
-		ti,set-bit-to-disable;
-	};
-
-	vlynq_gate_fck: vlynq_gate_fck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-gate-clock";
-		clocks = <&core_ck>;
-		ti,bit-shift = <3>;
-		reg = <0x0200>;
-	};
-
-	sys_clkout2_src_gate: sys_clkout2_src_gate {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&core_ck>;
-		ti,bit-shift = <15>;
-		reg = <0x0070>;
-	};
diff --git a/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml b/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
new file mode 100644
index 00000000000..31a6794852c
--- /dev/null
+++ b/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments composite clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  *Deprecated design pattern: one node per clock*
+
+  This binding assumes a register-mapped composite clock with multiple
+  different sub-types:
+
+    a multiplexer clock with multiple input clock signals or parents, one
+    of which can be selected as output, this behaves exactly as [1].
+
+    an adjustable clock rate divider, this behaves exactly as [2].
+
+    a gating function which can be used to enable and disable the output
+    clock, this behaves exactly as [3].
+
+  The binding must provide a list of the component clocks that shall be
+  merged to this clock. The component clocks shall be of one of the
+  "ti,*composite*-clock" types.
+
+  [1] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
+  [2] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
+  [3] Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml
+
+properties:
+  compatible:
+    const: ti,composite-clock
+
+  "#clock-cells":
+    const: 0
+
+  clocks: true
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      usb_l4_gate_ick: clock-controller@a10 {
+        #clock-cells = <0>;
+        compatible = "ti,composite-gate-clock";
+        clocks = <&l4_ick>;
+        ti,bit-shift = <5>;
+        reg = <0x0a10>;
+      };
+
+      usb_l4_div_ick: clock-controller@a40 {
+        #clock-cells = <0>;
+        compatible = "ti,composite-divider-clock";
+        clocks = <&l4_ick>;
+        ti,bit-shift = <4>;
+        ti,max-div = <1>;
+        reg = <0x0a40>;
+        ti,index-starts-at-one;
+      };
+    };
+
+    clock-controller {
+      #clock-cells = <0>;
+      compatible = "ti,composite-clock";
+      clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+    };
diff --git a/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml b/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
new file mode 100644
index 00000000000..eaa727ab0d7
--- /dev/null
+++ b/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments gate clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  *Deprecated design pattern: one node per clock*
+
+  This clock is quite much similar to the basic gate-clock [1], however,
+  it supports a number of additional features. If no register
+  is provided for this clock, the code assumes that a clockdomain
+  will be controlled instead and the corresponding hw-ops for
+  that is used.
+
+  [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
+  [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+properties:
+  compatible:
+    enum:
+      - ti,gate-clock           # basic gate clock
+      - ti,wait-gate-clock      # gate clock which waits until clock is
+                                # active before returning from clk_enable()
+      - ti,dss-gate-clock       # gate clock with DSS specific hardware
+                                # handling
+      - ti,am35xx-gate-clock    # gate clock with AM35xx specific hardware
+                                # handling
+      - ti,clkdm-gate-clock     # clockdomain gate clock, which derives its
+                                # functional clock directly from a
+                                # clockdomain, see [2] how to map
+                                # clockdomains properly
+      - ti,hsdiv-gate-clock     # gate clock with OMAP36xx specific hardware
+                                # handling, required for a hardware errata
+      - ti,composite-gate-clock # composite gate clock, to be part of
+                                # composite clock
+      - ti,composite-no-wait-gate-clock # composite gate clock that does not
+                                        # wait for clock to be active before
+                                        # returning from clk_enable()
+  "#clock-cells":
+    const: 0
+
+  clocks: true
+
+  clock-output-names:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ti,bit-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of bits to shift the bit-mask
+    maximum: 31
+    default: 0
+
+  ti,set-bit-to-disable:
+    type: boolean
+    description:
+      Inverts default gate programming. Setting the bit
+      gates the clock and clearing the bit ungates the clock.
+
+  ti,set-rate-parent:
+    type: boolean
+    description:
+      clk_set_rate is propagated to parent clock,
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: ti,clkdm-gate-clock
+then:
+  properties:
+    reg: false
+  required:
+    - compatible
+    - "#clock-cells"
+    - clocks
+else:
+  required:
+    - compatible
+    - "#clock-cells"
+    - clocks
+    - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      clock-controller@a00 {
+        #clock-cells = <0>;
+        compatible = "ti,gate-clock";
+        clocks = <&core_96m_fck>;
+        reg = <0x0a00>;
+        ti,bit-shift = <25>;
+      };
+
+      clock-controller@d00 {
+        compatible = "ti,hsdiv-gate-clock";
+        reg = <0x0d00>;
+        #clock-cells = <0>;
+        clocks = <&dpll4_m2x2_mul_ck>;
+        ti,bit-shift = <0x1b>;
+        ti,set-bit-to-disable;
+      };
+    };
+
+  - |
+    clock-controller {
+      #clock-cells = <0>;
+      compatible = "ti,clkdm-gate-clock";
+      clocks = <&emu_src_mux_ck>;
+    };
+
diff --git a/dts/upstream/Bindings/clock/xlnx,vcu.yaml b/dts/upstream/Bindings/clock/xlnx,vcu.yaml
new file mode 100644
index 00000000000..19dc923e2ee
--- /dev/null
+++ b/dts/upstream/Bindings/clock/xlnx,vcu.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: LogicoreIP designed compatible with Xilinx ZYNQ family.
+
+maintainers:
+  - Rohit Visavalia <rohit.visavalia@amd.com>
+
+description:
+  LogicoreIP design to provide the isolation between processing system
+  and programmable logic. Also provides the list of register set to configure
+  the frequency.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,vcu
+          - xlnx,vcu-logicoreip-1.0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: pll ref clocksource
+      - description: aclk
+
+  clock-names:
+    items:
+      - const: pll_ref
+      - const: aclk
+
+  reset-gpios:
+    maxItems: 1
+
+required:
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    fpga {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        xlnx_vcu: vcu@a0040000 {
+            compatible = "xlnx,vcu-logicoreip-1.0";
+            reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
+            clocks = <&si570_1>, <&clkc 71>;
+            clock-names = "pll_ref", "aclk";
+        };
+    };
diff --git a/dts/upstream/Bindings/connector/usb-connector.yaml b/dts/upstream/Bindings/connector/usb-connector.yaml
index 67700440e23..11e40d225b9 100644
--- a/dts/upstream/Bindings/connector/usb-connector.yaml
+++ b/dts/upstream/Bindings/connector/usb-connector.yaml
@@ -293,6 +293,13 @@ properties:
       PD negotiation till BC1.2 detection completes.
     default: 0
 
+  pd-revision:
+    description: Specifies the maximum USB PD revision and version supported by
+      the connector. This property is specified in the following order;
+      <revision_major, revision_minor, version_major, version_minor>.
+    $ref: /schemas/types.yaml#/definitions/uint8-array
+    maxItems: 4
+
 dependencies:
   sink-vdos-v1: [ sink-vdos ]
   sink-vdos: [ sink-vdos-v1 ]
diff --git a/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml b/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
new file mode 100644
index 00000000000..7d4510b3219
--- /dev/null
+++ b/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 CPUFreq
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description: |
+  On newer Airoha SoC, CPU Frequency is scaled indirectly with SMC commands
+  to ATF.
+
+  A virtual clock is exposed. This virtual clock is a get-only clock and
+  is used to expose the current global CPU clock. The frequency info comes
+  by the output of the SMC command that reports the clock in MHz.
+
+  The SMC sets the CPU clock by providing an index, this is modelled as
+  performance states in a power domain.
+
+  CPUs can't be individually scaled as the CPU frequency is shared across
+  all CPUs and is global.
+
+properties:
+  compatible:
+    const: airoha,en7581-cpufreq
+
+  '#clock-cells':
+    const: 0
+
+  '#power-domain-cells':
+    const: 0
+
+  operating-points-v2: true
+
+required:
+  - compatible
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - operating-points-v2
+
+additionalProperties: false
+
+examples:
+  - |
+    performance-domain {
+        compatible = "airoha,en7581-cpufreq";
+
+        operating-points-v2 = <&cpu_smcc_opp_table>;
+
+        #power-domain-cells = <0>;
+        #clock-cells = <0>;
+    };
diff --git a/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml b/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
index 76cb9726660..896276b8c6b 100644
--- a/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
+++ b/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
@@ -24,9 +24,17 @@ properties:
               - apple,t8112-cluster-cpufreq
           - const: apple,cluster-cpufreq
       - items:
-          - const: apple,t6000-cluster-cpufreq
+          - enum:
+              - apple,s8000-cluster-cpufreq
+              - apple,t8010-cluster-cpufreq
+              - apple,t8015-cluster-cpufreq
+              - apple,t6000-cluster-cpufreq
           - const: apple,t8103-cluster-cpufreq
           - const: apple,cluster-cpufreq
+      - items:
+          - const: apple,t7000-cluster-cpufreq
+          - const: apple,s5l8960x-cluster-cpufreq
+      - const: apple,s5l8960x-cluster-cpufreq
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
index 0304f074cf0..08fe6a707a3 100644
--- a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -13,12 +13,14 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs8300-inline-crypto-engine
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine
           - qcom,sc7280-inline-crypto-engine
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
+          - qcom,sm8750-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:
diff --git a/dts/upstream/Bindings/crypto/qcom,prng.yaml b/dts/upstream/Bindings/crypto/qcom,prng.yaml
index 048b769a73c..5e6f8b64254 100644
--- a/dts/upstream/Bindings/crypto/qcom,prng.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,prng.yaml
@@ -17,12 +17,17 @@ properties:
           - qcom,prng-ee  # 8996 and later using EE
       - items:
           - enum:
+              - qcom,ipq5332-trng
+              - qcom,ipq5424-trng
+              - qcom,ipq9574-trng
+              - qcom,qcs8300-trng
               - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
               - qcom,sm8450-trng
               - qcom,sm8550-trng
               - qcom,sm8650-trng
+              - qcom,sm8750-trng
           - const: qcom,trng
 
   reg:
diff --git a/dts/upstream/Bindings/crypto/qcom-qce.yaml b/dts/upstream/Bindings/crypto/qcom-qce.yaml
index c09be97434a..3ed56d9d378 100644
--- a/dts/upstream/Bindings/crypto/qcom-qce.yaml
+++ b/dts/upstream/Bindings/crypto/qcom-qce.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm crypto engine driver
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   This document defines the binding for the QCE crypto
@@ -44,6 +45,7 @@ properties:
 
       - items:
           - enum:
+              - qcom,qcs8300-qce
               - qcom,sa8775p-qce
               - qcom,sc7280-qce
               - qcom,sm6350-qce
@@ -52,6 +54,7 @@ properties:
               - qcom,sm8450-qce
               - qcom,sm8550-qce
               - qcom,sm8650-qce
+              - qcom,sm8750-qce
           - const: qcom,sm8150-qce
           - const: qcom,qce
 
diff --git a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
index 84d68b8cfcc..416fe263ac9 100644
--- a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -148,10 +148,10 @@ examples:
 
         /* TMDS Output */
         hdmi_tx_tmds_port: port@1 {
-             reg = <1>;
+            reg = <1>;
 
-             hdmi_tx_tmds_out: endpoint {
-                 remote-endpoint = <&hdmi_connector_in>;
-             };
+            hdmi_tx_tmds_out: endpoint {
+                remote-endpoint = <&hdmi_connector_in>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
index 5b35adf34c7..6d11f5955b5 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
@@ -14,6 +14,8 @@ properties:
     enum:
       - brcm,bcm2711-hdmi0
       - brcm,bcm2711-hdmi1
+      - brcm,bcm2712-hdmi0
+      - brcm,bcm2712-hdmi1
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
index 2e8566f47e6..f91c9dce2a4 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     enum:
       - brcm,bcm2711-hvs
+      - brcm,bcm2712-hvs
       - brcm,bcm2835-hvs
 
   reg:
@@ -36,7 +37,9 @@ if:
   properties:
     compatible:
       contains:
-        const: brcm,bcm2711-hvs
+        enum:
+          - brcm,bcm2711-hvs
+          - brcm,bcm2712-hvs
 
 then:
   required:
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
index 4e1ba03f647..6b5b1d3fbc0 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
@@ -20,6 +20,9 @@ properties:
       - brcm,bcm2711-pixelvalve2
       - brcm,bcm2711-pixelvalve3
       - brcm,bcm2711-pixelvalve4
+      - brcm,bcm2712-pixelvalve0
+      - brcm,bcm2712-pixelvalve1
+      - brcm,bcm2712-pixelvalve2
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
index bb186197e47..16f45afd2ba 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
@@ -11,7 +11,10 @@ maintainers:
 
 properties:
   compatible:
-    const: brcm,bcm2835-txp
+    enum:
+      - brcm,bcm2712-mop
+      - brcm,bcm2712-moplet
+      - brcm,bcm2835-txp
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
index 49a5e041aa4..2aa9d5d2aff 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - brcm,bcm2711-vc5
+      - brcm,bcm2712-vc6
       - brcm,bcm2835-vc4
       - brcm,cygnus-vc4
 
diff --git a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
index 3791c9f4eba..05442d43775 100644
--- a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
+++ b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
@@ -82,21 +82,21 @@ examples:
         power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
         reg-io-width = <1>;
         ports {
-           #address-cells = <1>;
-           #size-cells = <0>;
-           port@0 {
-             reg = <0>;
-
-             hdmi_tx_from_pvi: endpoint {
-               remote-endpoint = <&pvi_to_hdmi_tx>;
-             };
-          };
-
-          port@1 {
-            reg = <1>;
-              hdmi_tx_out: endpoint {
-                remote-endpoint = <&hdmi0_con>;
-              };
-          };
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+
+                endpoint {
+                    remote-endpoint = <&pvi_to_hdmi_tx>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&hdmi0_con>;
+                };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
index d33026f85e1..c167795c63f 100644
--- a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
+++ b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
@@ -19,6 +19,7 @@ properties:
     enum:
       - renesas,r8a779a0-dsi-csi2-tx    # for V3U
       - renesas,r8a779g0-dsi-csi2-tx    # for V4H
+      - renesas,r8a779h0-dsi-csi2-tx    # for V4M
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml b/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
index 4ed7a799ba2..1acad99f396 100644
--- a/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -27,7 +27,9 @@ properties:
           - fsl,imx8mm-mipi-dsim
           - fsl,imx8mp-mipi-dsim
       - items:
-          - const: fsl,imx8mn-mipi-dsim
+          - enum:
+              - fsl,imx7d-mipi-dsim
+              - fsl,imx8mn-mipi-dsim
           - const: fsl,imx8mm-mipi-dsim
 
   reg:
@@ -241,40 +243,40 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     dsi@13900000 {
-       compatible = "samsung,exynos5433-mipi-dsi";
-       reg = <0x13900000 0xC0>;
-       interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-       phys = <&mipi_phy 1>;
-       phy-names = "dsim";
-       clocks = <&cmu_disp CLK_PCLK_DSIM0>,
-                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
-                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
-                <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
-                <&cmu_disp CLK_SCLK_DSIM0>;
-       clock-names = "bus_clk",
-                     "phyclk_mipidphy0_bitclkdiv8",
-                     "phyclk_mipidphy0_rxclkesc0",
-                     "sclk_rgb_vclk_to_dsim0",
-                     "sclk_mipi";
-       power-domains = <&pd_disp>;
-       vddcore-supply = <&ldo6_reg>;
-       vddio-supply = <&ldo7_reg>;
-       samsung,burst-clock-frequency = <512000000>;
-       samsung,esc-clock-frequency = <16000000>;
-       samsung,pll-clock-frequency = <24000000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&te_irq>;
-
-       ports {
-          #address-cells = <1>;
-          #size-cells = <0>;
-
-          port@0 {
-             reg = <0>;
-
-             dsi_to_mic: endpoint {
-                remote-endpoint = <&mic_to_dsi>;
-             };
-          };
-       };
+        compatible = "samsung,exynos5433-mipi-dsi";
+        reg = <0x13900000 0xC0>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+        phys = <&mipi_phy 1>;
+        phy-names = "dsim";
+        clocks = <&cmu_disp CLK_PCLK_DSIM0>,
+                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
+                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
+                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
+                 <&cmu_disp CLK_SCLK_DSIM0>;
+        clock-names = "bus_clk",
+                      "phyclk_mipidphy0_bitclkdiv8",
+                      "phyclk_mipidphy0_rxclkesc0",
+                      "sclk_rgb_vclk_to_dsim0",
+                      "sclk_mipi";
+        power-domains = <&pd_disp>;
+        vddcore-supply = <&ldo6_reg>;
+        vddio-supply = <&ldo7_reg>;
+        samsung,burst-clock-frequency = <512000000>;
+        samsung,esc-clock-frequency = <16000000>;
+        samsung,pll-clock-frequency = <24000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&te_irq>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                dsi_to_mic: endpoint {
+                    remote-endpoint = <&mic_to_dsi>;
+                };
+            };
+        };
     };
diff --git a/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml b/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
index 48a97bb3e2e..bad6f5c81b0 100644
--- a/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
+++ b/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
@@ -80,12 +80,12 @@ properties:
                   - const: 4
 
       port@2:
-        $ref: /schemas/graph.yaml#/properties/port
         description: Video port for LVDS Channel-A output (panel or bridge).
+        $ref: '#/$defs/lvds-port'
 
       port@3:
-        $ref: /schemas/graph.yaml#/properties/port
         description: Video port for LVDS Channel-B output (panel or bridge).
+        $ref: '#/$defs/lvds-port'
 
     required:
       - port@0
@@ -96,6 +96,36 @@ required:
   - reg
   - ports
 
+$defs:
+  lvds-port:
+    $ref: /schemas/graph.yaml#/$defs/port-base
+    unevaluatedProperties: false
+
+    properties:
+      endpoint:
+        $ref: /schemas/media/video-interfaces.yaml#
+        unevaluatedProperties: false
+
+        properties:
+          ti,lvds-termination-ohms:
+            description: The value of near end differential termination in ohms.
+            enum: [100, 200]
+            default: 200
+
+          ti,lvds-vod-swing-clock-microvolt:
+            description: LVDS diferential output voltage <min max> for clock
+              lanes in microvolts.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 2
+            maxItems: 2
+
+          ti,lvds-vod-swing-data-microvolt:
+            description: LVDS diferential output voltage <min max> for data
+              lanes in microvolts.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 2
+            maxItems: 2
+
 allOf:
   - if:
       properties:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
index 47ddba5c41a..5d2089dc596 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
@@ -104,30 +104,30 @@ examples:
         #size-cells = <2>;
 
         aal@14015000 {
-           compatible = "mediatek,mt8173-disp-aal";
-           reg = <0 0x14015000 0 0x1000>;
-           interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
-           power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-           clocks = <&mmsys CLK_MM_DISP_AAL>;
-           mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
-
-           ports {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               port@0 {
-                   reg = <0>;
-                   aal0_in: endpoint {
-                       remote-endpoint = <&ccorr0_out>;
-                   };
-               };
-
-               port@1 {
-                   reg = <1>;
-                   aal0_out: endpoint {
-                       remote-endpoint = <&gamma0_in>;
-                   };
-               };
-           };
-       };
+            compatible = "mediatek,mt8173-disp-aal";
+            reg = <0 0x14015000 0 0x1000>;
+            interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+            clocks = <&mmsys CLK_MM_DISP_AAL>;
+            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    endpoint {
+                        remote-endpoint = <&ccorr0_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    endpoint {
+                        remote-endpoint = <&gamma0_in>;
+                    };
+                };
+            };
+        };
     };
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
index 9ea796a033b..4f110635afb 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -26,6 +26,7 @@ properties:
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl
           - mediatek,mt8192-disp-ovl
+          - mediatek,mt8195-disp-ovl
           - mediatek,mt8195-mdp3-ovl
       - items:
           - enum:
@@ -38,14 +39,15 @@ properties:
           - const: mediatek,mt8173-disp-ovl
       - items:
           - enum:
-              - mediatek,mt8188-disp-ovl
-              - mediatek,mt8195-disp-ovl
-          - const: mediatek,mt8183-disp-ovl
-      - items:
-          - enum:
               - mediatek,mt8186-disp-ovl
               - mediatek,mt8365-disp-ovl
           - const: mediatek,mt8192-disp-ovl
+      - items:
+          - const: mediatek,mt8188-disp-ovl
+          - const: mediatek,mt8195-disp-ovl
+      - items:
+          - const: mediatek,mt8188-mdp3-ovl
+          - const: mediatek,mt8195-mdp3-ovl
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/msm/dp-controller.yaml b/dts/upstream/Bindings/display/msm/dp-controller.yaml
index a212f335d5f..e00b88332f2 100644
--- a/dts/upstream/Bindings/display/msm/dp-controller.yaml
+++ b/dts/upstream/Bindings/display/msm/dp-controller.yaml
@@ -8,6 +8,7 @@ title: MSM Display Port Controller
 
 maintainers:
   - Kuogee Hsieh <quic_khsieh@quicinc.com>
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
 
 description: |
   Device tree bindings for DisplayPort host controller for MSM targets
diff --git a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
index b0fd96b76ed..ffbd1dc9470 100644
--- a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
@@ -30,6 +30,7 @@ properties:
               - qcom,sdm845-dsi-ctrl
               - qcom,sm6115-dsi-ctrl
               - qcom,sm6125-dsi-ctrl
+              - qcom,sm6150-dsi-ctrl
               - qcom,sm6350-dsi-ctrl
               - qcom,sm6375-dsi-ctrl
               - qcom,sm7150-dsi-ctrl
@@ -349,6 +350,7 @@ allOf:
             enum:
               - qcom,sc7180-dsi-ctrl
               - qcom,sc7280-dsi-ctrl
+              - qcom,sm6150-dsi-ctrl
               - qcom,sm7150-dsi-ctrl
               - qcom,sm8150-dsi-ctrl
               - qcom,sm8250-dsi-ctrl
@@ -416,63 +418,63 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/interrupt-controller/arm-gic.h>
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
-     #include <dt-bindings/power/qcom-rpmpd.h>
-
-     dsi@ae94000 {
-           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
-           reg = <0x0ae94000 0x400>;
-           reg-names = "dsi_ctrl";
-
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           interrupt-parent = <&mdss>;
-           interrupts = <4>;
-
-           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
-                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
-                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
-                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
-                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
-           clock-names = "byte",
-                         "byte_intf",
-                         "pixel",
-                         "core",
-                         "iface",
-                         "bus";
-
-           phys = <&dsi0_phy>;
-           phy-names = "dsi";
-
-           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
-           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
-
-           power-domains = <&rpmhpd SC7180_CX>;
-           operating-points-v2 = <&dsi_opp_table>;
-
-           ports {
-                  #address-cells = <1>;
-                  #size-cells = <0>;
-
-                  port@0 {
-                          reg = <0>;
-                          dsi0_in: endpoint {
-                                   remote-endpoint = <&dpu_intf1_out>;
-                          };
-                  };
-
-                  port@1 {
-                          reg = <1>;
-                          dsi0_out: endpoint {
-                                   remote-endpoint = <&sn65dsi86_in>;
-                                   data-lanes = <0 1 2 3>;
-                                   qcom,te-source = "mdp_vsync_e";
-                          };
-                  };
-           };
-     };
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    dsi@ae94000 {
+        compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+        reg = <0x0ae94000 0x400>;
+        reg-names = "dsi_ctrl";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <4>;
+
+        clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+        clock-names = "byte",
+                      "byte_intf",
+                      "pixel",
+                      "core",
+                      "iface",
+                      "bus";
+
+        phys = <&dsi0_phy>;
+        phy-names = "dsi";
+
+        assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+        assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+
+        power-domains = <&rpmhpd SC7180_CX>;
+        operating-points-v2 = <&dsi_opp_table>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&dpu_intf1_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&sn65dsi86_in>;
+                    data-lanes = <0 1 2 3>;
+                    qcom,te-source = "mdp_vsync_e";
+                };
+            };
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
index 69d13867b7c..fc9abf090f0 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
@@ -74,28 +74,28 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
-
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-10nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94a00 0x1e0>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
-
-         #clock-cells = <1>;
-         #phy-cells = <0>;
-
-         vdds-supply = <&vdda_mipi_dsi0_pll>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-
-         qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
-         qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
-         qcom,phy-drive-ldo-level = <400>;
-     };
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-10nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94a00 0x1e0>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
+
+        #clock-cells = <1>;
+        #phy-cells = <0>;
+
+        vdds-supply = <&vdda_mipi_dsi0_pll>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+
+        qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
+        qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
+        qcom,phy-drive-ldo-level = <400>;
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
index 52bbe132e6d..206a9a4b384 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
@@ -20,6 +20,7 @@ properties:
       - qcom,dsi-phy-14nm-660
       - qcom,dsi-phy-14nm-8953
       - qcom,sm6125-dsi-phy-14nm
+      - qcom,sm6150-dsi-phy-14nm
 
   reg:
     items:
@@ -55,24 +56,24 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-14nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94a00 0x1e0>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-14nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94a00 0x1e0>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vcca-supply = <&vcca_reg>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        vcca-supply = <&vcca_reg>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
index 7e6687cb002..93570052992 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
@@ -45,26 +45,26 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@fd922a00 {
-         compatible = "qcom,dsi-phy-20nm";
-         reg = <0xfd922a00 0xd4>,
-               <0xfd922b00 0x2b0>,
-               <0xfd922d80 0x7b>;
-         reg-names = "dsi_pll",
-                     "dsi_phy",
-                     "dsi_phy_regulator";
+    dsi-phy@fd922a00 {
+        compatible = "qcom,dsi-phy-20nm";
+        reg = <0xfd922a00 0xd4>,
+              <0xfd922b00 0x2b0>,
+              <0xfd922d80 0x7b>;
+        reg-names = "dsi_pll",
+                    "dsi_phy",
+                    "dsi_phy_regulator";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vcca-supply = <&vcca_reg>;
-         vddio-supply = <&vddio_reg>;
+        vcca-supply = <&vcca_reg>;
+        vddio-supply = <&vddio_reg>;
 
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
index a55c2445d18..371befa9f9d 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
@@ -51,25 +51,25 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@fd922a00 {
-         compatible = "qcom,dsi-phy-28nm-lp";
-         reg = <0xfd922a00 0xd4>,
-               <0xfd922b00 0x2b0>,
-               <0xfd922d80 0x7b>;
-         reg-names = "dsi_pll",
-                     "dsi_phy",
-                     "dsi_phy_regulator";
+    dsi-phy@fd922a00 {
+        compatible = "qcom,dsi-phy-28nm-lp";
+        reg = <0xfd922a00 0xd4>,
+              <0xfd922b00 0x2b0>,
+              <0xfd922d80 0x7b>;
+        reg-names = "dsi_pll",
+                    "dsi_phy",
+                    "dsi_phy_regulator";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vddio-supply = <&vddio_reg>;
+        vddio-supply = <&vddio_reg>;
 
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
index 7e764eac3ef..321470435e6 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
@@ -54,23 +54,23 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-7nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94900 0x260>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-7nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94900 0x260>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vdds-supply = <&vreg_l5a_0p88>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        vdds-supply = <&vreg_l5a_0p88>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
diff --git a/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
index 58f8a01f29c..a90a8b3f1a9 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -78,7 +78,6 @@ examples:
                              "mdp1-mem",
                              "cpu-cfg";
 
-
         resets = <&dispcc_core_bcr>;
         power-domains = <&dispcc_gdsc>;
 
@@ -129,7 +128,7 @@ examples:
                 port@0 {
                     reg = <0>;
                     dpu_intf0_out: endpoint {
-                         remote-endpoint = <&mdss0_dp0_in>;
+                        remote-endpoint = <&mdss0_dp0_in>;
                     };
                 };
             };
@@ -168,7 +167,8 @@ examples:
             reg = <0xaf54000 0x104>,
                   <0xaf54200 0x0c0>,
                   <0xaf55000 0x770>,
-                  <0xaf56000 0x09c>;
+                  <0xaf56000 0x09c>,
+                  <0xaf57000 0x09c>;
 
             interrupt-parent = <&mdss0>;
             interrupts = <12>;
@@ -208,8 +208,8 @@ examples:
                 };
 
                 port@1 {
-                   reg = <1>;
-                   mdss0_dp_out: endpoint { };
+                    reg = <1>;
+                    mdss0_dp_out: endpoint { };
                 };
             };
 
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
new file mode 100644
index 00000000000..b4f43717221
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display DPU
+
+maintainers:
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sm6150-dpu
+
+  reg:
+    items:
+      - description: Address offset and size for mdp register set
+      - description: Address offset and size for vbif register set
+
+  reg-names:
+    items:
+      - const: mdp
+      - const: vbif
+
+  clocks:
+    items:
+      - description: Display ahb clock
+      - description: Display hf axi clock
+      - description: Display core clock
+      - description: Display vsync clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+      - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-controller@ae01000 {
+        compatible = "qcom,sm6150-dpu";
+        reg = <0x0ae01000 0x8f000>,
+              <0x0aeb0000 0x2008>;
+        reg-names = "mdp", "vbif";
+
+        clocks = <&dispcc_mdss_ahb_clk>,
+                 <&gcc_disp_hf_axi_clk>,
+                 <&dispcc_mdss_mdp_clk>,
+                 <&dispcc_mdss_vsync_clk>;
+        clock-names = "iface", "bus", "core", "vsync";
+
+        assigned-clocks = <&dispcc_mdss_vsync_clk>;
+        assigned-clock-rates = <19200000>;
+
+        operating-points-v2 = <&mdp_opp_table>;
+        power-domains = <&rpmhpd RPMHPD_CX>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dpu_intf0_out: endpoint {
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dpu_intf1_out: endpoint {
+                  remote-endpoint = <&mdss_dsi0_in>;
+                };
+            };
+        };
+
+        mdp_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-19200000 {
+              opp-hz = /bits/ 64 <19200000>;
+              required-opps = <&rpmhpd_opp_low_svs>;
+            };
+
+            opp-25600000 {
+              opp-hz = /bits/ 64 <25600000>;
+              required-opps = <&rpmhpd_opp_svs>;
+            };
+
+            opp-307200000 {
+              opp-hz = /bits/ 64 <307200000>;
+              required-opps = <&rpmhpd_opp_nom>;
+            };
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
new file mode 100644
index 00000000000..9ac24f99d3a
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
@@ -0,0 +1,245 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display MDSS
+
+maintainers:
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS are mentioned for SM6150 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: qcom,sm6150-mdss
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display hf axi clock
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm6150-dpu
+
+  "^dsi@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        items:
+          - const: qcom,sm6150-dsi-ctrl
+          - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm6150-dsi-phy-14nm
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-subsystem@ae00000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "qcom,sm6150-mdss";
+        reg = <0x0ae00000 0x1000>;
+        reg-names = "mdss";
+
+        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+        interconnect-names = "mdp0-mem", "cpu-cfg";
+
+        power-domains = <&dispcc_mdss_gdsc>;
+
+        clocks = <&dispcc_mdss_ahb_clk>,
+                 <&gcc_disp_hf_axi_clk>,
+                 <&dispcc_mdss_mdp_clk>;
+
+        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        iommus = <&apps_smmu 0x800 0x0>;
+
+        ranges;
+
+        display-controller@ae01000 {
+            compatible = "qcom,sm6150-dpu";
+            reg = <0x0ae01000 0x8f000>,
+                  <0x0aeb0000 0x2008>;
+            reg-names = "mdp", "vbif";
+
+            clocks = <&dispcc_mdss_ahb_clk>,
+                     <&gcc_disp_hf_axi_clk>,
+                     <&dispcc_mdss_mdp_clk>,
+                     <&dispcc_mdss_vsync_clk>;
+            clock-names = "iface", "bus", "core", "vsync";
+
+            assigned-clocks = <&dispcc_mdss_vsync_clk>;
+            assigned-clock-rates = <19200000>;
+
+            operating-points-v2 = <&mdp_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_CX>;
+
+            interrupt-parent = <&mdss>;
+            interrupts = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                  reg = <0>;
+                  dpu_intf0_out: endpoint {
+                  };
+                };
+
+                port@1 {
+                  reg = <1>;
+                  dpu_intf1_out: endpoint {
+                      remote-endpoint = <&mdss_dsi0_in>;
+                  };
+                };
+            };
+
+            mdp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-19200000 {
+                  opp-hz = /bits/ 64 <19200000>;
+                  required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-25600000 {
+                  opp-hz = /bits/ 64 <25600000>;
+                  required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-307200000 {
+                  opp-hz = /bits/ 64 <307200000>;
+                  required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+
+        dsi@ae94000 {
+            compatible = "qcom,sm6150-dsi-ctrl",
+                         "qcom,mdss-dsi-ctrl";
+            reg = <0x0ae94000 0x400>;
+            reg-names = "dsi_ctrl";
+
+            interrupt-parent = <&mdss>;
+            interrupts = <4>;
+
+            clocks = <&dispcc_mdss_byte0_clk>,
+                     <&dispcc_mdss_byte0_intf_clk>,
+                     <&dispcc_mdss_pclk0_clk>,
+                     <&dispcc_mdss_esc0_clk>,
+                     <&dispcc_mdss_ahb_clk>,
+                     <&gcc_disp_hf_axi_clk>;
+            clock-names = "byte",
+                          "byte_intf",
+                          "pixel",
+                          "core",
+                          "iface",
+                          "bus";
+
+            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
+                              <&dispcc_mdss_pclk0_clk_src>;
+            assigned-clock-parents = <&mdss_dsi0_phy 0>,
+                                     <&mdss_dsi0_phy 1>;
+
+            operating-points-v2 = <&dsi0_opp_table>;
+
+            phys = <&mdss_dsi0_phy>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    mdss_dsi0_in: endpoint {
+                        remote-endpoint = <&dpu_intf1_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    mdss_dsi0_out: endpoint {
+                    };
+                };
+            };
+
+            dsi0_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-164000000 {
+                    opp-hz = /bits/ 64 <164000000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+            };
+        };
+
+        mdss_dsi0_phy: phy@ae94400 {
+            compatible = "qcom,sm6150-dsi-phy-14nm";
+            reg = <0x0ae94400 0x100>,
+                  <0x0ae94500 0x300>,
+                  <0x0ae94800 0x188>;
+            reg-names = "dsi_phy",
+                        "dsi_phy_lane",
+                        "dsi_pll";
+
+            #clock-cells = <1>;
+            #phy-cells = <0>;
+
+            clocks = <&dispcc_mdss_ahb_clk>,
+                     <&rpmhcc RPMH_CXO_CLK>;
+            clock-names = "iface", "ref";
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/display/panel/panel-lvds.yaml b/dts/upstream/Bindings/display/panel/panel-lvds.yaml
index 5af2d693007..fcb5834f799 100644
--- a/dts/upstream/Bindings/display/panel/panel-lvds.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-lvds.yaml
@@ -42,6 +42,8 @@ properties:
           # Admatec 9904379 10.1" 1024x600 LVDS panel
           - admatec,9904379
           - auo,b101ew05
+          # AUO G084SN05 V9 8.4" 800x600 LVDS panel
+          - auo,g084sn05
           # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
           - chunghwa,claa070wp03xg
           # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
diff --git a/dts/upstream/Bindings/display/panel/panel-simple.yaml b/dts/upstream/Bindings/display/panel/panel-simple.yaml
index 18b63f356bb..e3ee3a332bb 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple.yaml
@@ -206,12 +206,16 @@ properties:
       - mitsubishi,aa070mc01-ca1
         # Mitsubishi AA084XE01 8.4" XGA TFT LCD panel
       - mitsubishi,aa084xe01
+        # Multi-Inno Technology Co.,Ltd MI0700A2T-30 7" 800x480 TFT Resistive Touch Module
+      - multi-inno,mi0700a2t-30
         # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
       - multi-inno,mi0700s4t-6
         # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module
       - multi-inno,mi0800ft-9
         # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
       - multi-inno,mi1010ait-1cp
+        # Multi-Inno Technology Co.,Ltd MI1010Z1T-1CP11 10.1" 1024x600 TFT Resistive Touch Module
+      - multi-inno,mi1010z1t-1cp11
         # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
       - nec,nl12880bc20-05
         # NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
@@ -280,10 +284,14 @@ properties:
       - team-source-display,tst043015cmhx
         # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
       - tianma,tm070jdhg30
+        # Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel
+      - tianma,tm070jdhg34-00
         # Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
       - tianma,tm070jvhg33
         # Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
       - tianma,tm070rvhg71
+        # Topland TIAN-G07017-01 7.0" WSVGA TFT-LCD panel with capacitive touch
+      - topland,tian-g07017-01
         # Toshiba 8.9" WXGA (1280x768) TFT LCD panel
       - toshiba,lt089ac29000
         # TPK U.S.A. LLC Fusion 7" 800 x 480 (WVGA) LCD panel with capacitive touch
diff --git a/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml b/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
new file mode 100644
index 00000000000..b7d74faeb5d
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/powertip,hx8238a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Powertip Electronic Technology Co. 320 x 240 LCD panel
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+allOf:
+  - $ref: panel-dpi.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: powertip,hx8238a
+      - {} # panel-dpi, but not listed here to avoid false select
+
+  height-mm: true
+  panel-timing: true
+  port: true
+  power-supply: true
+  width-mm: true
+
+additionalProperties: false
+
+...
diff --git a/dts/upstream/Bindings/display/panel/powertip,st7272.yaml b/dts/upstream/Bindings/display/panel/powertip,st7272.yaml
new file mode 100644
index 00000000000..f3622800f13
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/powertip,st7272.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/powertip,st7272.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Powertip Electronic Technology Co. 320 x 240 LCD panel
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+allOf:
+  - $ref: panel-dpi.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: powertip,st7272
+      - {} # panel-dpi, but not listed here to avoid false select
+
+  height-mm: true
+  panel-timing: true
+  port: true
+  power-supply: true
+  width-mm: true
+
+additionalProperties: false
+
+...
diff --git a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
index 032f783eefc..684c2896d23 100644
--- a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
+++ b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
@@ -23,6 +23,8 @@ properties:
               - samsung,atna45af01
               # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
               - samsung,atna45dc02
+              # Samsung 15.6" 3K (2880x1620 pixels) eDP AMOLED panel
+              - samsung,atna56ac03
           - const: samsung,atna33xc20
 
   enable-gpios: true
diff --git a/dts/upstream/Bindings/display/renesas,cmm.yaml b/dts/upstream/Bindings/display/renesas,cmm.yaml
index 561efaaa5a9..fc4933c343c 100644
--- a/dts/upstream/Bindings/display/renesas,cmm.yaml
+++ b/dts/upstream/Bindings/display/renesas,cmm.yaml
@@ -58,10 +58,10 @@ examples:
     #include <dt-bindings/power/r8a7796-sysc.h>
 
     cmm0: cmm@fea40000 {
-         compatible = "renesas,r8a7796-cmm",
-                      "renesas,rcar-gen3-cmm";
-         reg = <0xfea40000 0x1000>;
-         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-         clocks = <&cpg CPG_MOD 711>;
-         resets = <&cpg 711>;
+        compatible = "renesas,r8a7796-cmm",
+                     "renesas,rcar-gen3-cmm";
+        reg = <0xfea40000 0x1000>;
+        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+        clocks = <&cpg CPG_MOD 711>;
+        resets = <&cpg 711>;
     };
diff --git a/dts/upstream/Bindings/display/renesas,du.yaml b/dts/upstream/Bindings/display/renesas,du.yaml
index c5b9e6812bc..3880b4c2ea9 100644
--- a/dts/upstream/Bindings/display/renesas,du.yaml
+++ b/dts/upstream/Bindings/display/renesas,du.yaml
@@ -41,6 +41,7 @@ properties:
       - renesas,du-r8a77995 # for R-Car D3 compatible DU
       - renesas,du-r8a779a0 # for R-Car V3U compatible DU
       - renesas,du-r8a779g0 # for R-Car V4H compatible DU
+      - renesas,du-r8a779h0 # for R-Car V4M compatible DU
 
   reg:
     maxItems: 1
@@ -69,14 +70,12 @@ properties:
         $ref: /schemas/graph.yaml#/properties/port
         unevaluatedProperties: false
 
-    required:
-      - port@0
-      - port@1
-
     unevaluatedProperties: false
 
   renesas,cmms:
     $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 4
     items:
       maxItems: 1
     description:
@@ -85,6 +84,8 @@ properties:
 
   renesas,vsps:
     $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 4
     items:
       items:
         - description: phandle to VSP instance that serves the DU channel
@@ -489,9 +490,11 @@ allOf:
 
         renesas,cmms:
           minItems: 4
+          maxItems: 4
 
         renesas,vsps:
           minItems: 4
+          maxItems: 4
 
       required:
         - clock-names
@@ -558,9 +561,11 @@ allOf:
 
         renesas,cmms:
           minItems: 3
+          maxItems: 3
 
         renesas,vsps:
           minItems: 3
+          maxItems: 3
 
       required:
         - clock-names
@@ -627,9 +632,11 @@ allOf:
 
         renesas,cmms:
           minItems: 3
+          maxItems: 3
 
         renesas,vsps:
           minItems: 3
+          maxItems: 3
 
       required:
         - clock-names
@@ -683,7 +690,7 @@ allOf:
             - port@1
 
         renesas,vsps:
-          minItems: 1
+          maxItems: 1
 
       required:
         - clock-names
@@ -746,9 +753,11 @@ allOf:
 
         renesas,cmms:
           minItems: 2
+          maxItems: 2
 
         renesas,vsps:
           minItems: 2
+          maxItems: 2
 
       required:
         - clock-names
@@ -799,6 +808,54 @@ allOf:
 
         renesas,vsps:
           minItems: 2
+          maxItems: 2
+
+      required:
+        - clock-names
+        - interrupts
+        - resets
+        - reset-names
+        - renesas,vsps
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r8a779h0
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Functional clock
+
+        clock-names:
+          items:
+            - const: du.0
+
+        interrupts:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            - const: du.0
+
+        ports:
+          properties:
+            port@0:
+              description: DSI 0
+            port@1: false
+            port@2: false
+            port@3: false
+
+          required:
+            - port@0
+
+        renesas,vsps:
+          maxItems: 1
 
       required:
         - clock-names
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
new file mode 100644
index 00000000000..53384e47b50
--- /dev/null
+++ b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3588-mipi-dsi2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: sys
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      This SoC uses GRF regs to switch between vopl/vopb.
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: dcphy
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: apb
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input node to receive pixel data.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DSI output node to panel.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - rockchip,grf
+  - phys
+  - phy-names
+  - ports
+  - reg
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/power/rk3588-power.h>
+    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      dsi@fde20000 {
+        compatible = "rockchip,rk3588-mipi-dsi2";
+        reg = <0x0 0xfde20000 0x0 0x10000>;
+        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+        clock-names = "pclk", "sys";
+        resets = <&cru SRST_P_DSIHOST0>;
+        reset-names = "apb";
+        power-domains = <&power RK3588_PD_VOP>;
+        phys = <&mipidcphy0 PHY_TYPE_DPHY>;
+        phy-names = "dcphy";
+        rockchip,grf = <&vop_grf>;
+
+        ports {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          dsi0_in: port@0 {
+            reg = <0>;
+          };
+
+          dsi0_out: port@1 {
+            reg = <1>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
index 55e3e490d0e..31c4ffcb599 100644
--- a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
@@ -23,7 +23,7 @@ properties:
   compatible:
     enum:
       - ti,am625-dss
-      - ti,am62a7,dss
+      - ti,am62a7-dss
       - ti,am65x-dss
 
   reg:
diff --git a/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
index 554f9d5809d..6b754d4f260 100644
--- a/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
+++ b/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -100,12 +100,16 @@ properties:
       - description: Video layer, plane 1 (U/V or U)
       - description: Video layer, plane 2 (V)
       - description: Graphics layer
+      - description: Audio channel 0
+      - description: Audio channel 1
   dma-names:
     items:
       - const: vid0
       - const: vid1
       - const: vid2
       - const: gfx0
+      - const: aud0
+      - const: aud1
 
   phys:
     description: PHYs for the DP data lanes
@@ -194,11 +198,13 @@ examples:
         power-domains = <&pd_dp>;
         resets = <&reset ZYNQMP_RESET_DP>;
 
-        dma-names = "vid0", "vid1", "vid2", "gfx0";
+        dma-names = "vid0", "vid1", "vid2", "gfx0", "aud0", "aud1";
         dmas = <&xlnx_dpdma 0>,
                <&xlnx_dpdma 1>,
                <&xlnx_dpdma 2>,
-               <&xlnx_dpdma 3>;
+               <&xlnx_dpdma 3>,
+               <&xlnx_dpdma 4>,
+               <&xlnx_dpdma 5>;
 
         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
                <&psgtr 0 PHY_TYPE_DP 1 3>;
diff --git a/dts/upstream/Bindings/dma/adi,axi-dmac.txt b/dts/upstream/Bindings/dma/adi,axi-dmac.txt
deleted file mode 100644
index cd17684aaab..00000000000
--- a/dts/upstream/Bindings/dma/adi,axi-dmac.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Analog Devices AXI-DMAC DMA controller
-
-Required properties:
- - compatible: Must be "adi,axi-dmac-1.00.a".
- - reg: Specification for the controllers memory mapped register map.
- - interrupts: Specification for the controllers interrupt.
- - clocks: Phandle and specifier to the controllers AXI interface clock
- - #dma-cells: Must be 1.
-
-Required sub-nodes:
- - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
-   the channel sub-nodes the following bindings apply. They must match the
-   configuration options of the peripheral as it was instantiated.
-
-Required properties for adi,channels sub-node:
- - #size-cells: Must be 0
- - #address-cells: Must be 1
-
-Required channel sub-node properties:
- - reg: Which channel this node refers to.
- - adi,source-bus-width,
-   adi,destination-bus-width: Width of the source or destination bus in bits.
- - adi,source-bus-type,
-   adi,destination-bus-type: Type of the source or destination bus. Must be one
-   of the following:
-	0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
-	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
-	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
-
-Deprecated optional channel properties:
- - adi,length-width: Width of the DMA transfer length register.
- - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
-   transfers.
- - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
-
-DMA clients connected to the AXI-DMAC DMA controller must use the format
-described in the dma.txt file using a one-cell specifier. The value of the
-specifier refers to the DMA channel index.
-
-Example:
-
-dma: dma@7c420000 {
-	compatible = "adi,axi-dmac-1.00.a";
-	reg = <0x7c420000 0x10000>;
-	interrupts = <0 57 0>;
-	clocks = <&clkc 16>;
-	#dma-cells = <1>;
-
-	adi,channels {
-		#size-cells = <0>;
-		#address-cells = <1>;
-
-		dma-channel@0 {
-			reg = <0>;
-			adi,source-bus-width = <32>;
-			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
-			adi,destination-bus-width = <64>;
-			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
-		};
-	};
-};
diff --git a/dts/upstream/Bindings/dma/adi,axi-dmac.yaml b/dts/upstream/Bindings/dma/adi,axi-dmac.yaml
new file mode 100644
index 00000000000..63b6fb0423c
--- /dev/null
+++ b/dts/upstream/Bindings/dma/adi,axi-dmac.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI-DMAC DMA controller
+
+description: |
+  FPGA-based DMA controller designed for use with high-speed converter hardware.
+
+  http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html
+
+maintainers:
+  - Nuno Sa <nuno.sa@analog.com>
+
+additionalProperties: false
+
+properties:
+  compatible:
+    const: adi,axi-dmac-1.00.a
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#dma-cells":
+    const: 1
+
+  adi,channels:
+    deprecated: true
+    type: object
+    description:
+      This sub-node must contain a sub-node for each DMA channel. This node is
+      only required for IP versions older than 4.3.a and should otherwise be
+      omitted.
+    additionalProperties: false
+
+    properties:
+      "#size-cells":
+        const: 0
+      "#address-cells":
+        const: 1
+
+    patternProperties:
+      "^dma-channel@[0-9a-f]+$":
+        type: object
+        description:
+          DMA channel properties based on HDL compile-time configuration.
+        additionalProperties: false
+
+        properties:
+          reg:
+            maxItems: 1
+
+          adi,source-bus-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the source bus in bits.
+            enum: [8, 16, 32, 64, 128]
+
+          adi,destination-bus-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the destination bus in bits.
+            enum: [8, 16, 32, 64, 128]
+
+          adi,source-bus-type:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: |
+              Type of the source bus.
+
+              0: Memory mapped AXI interface
+              1: Streaming AXI interface
+              2: FIFO interface
+            enum: [0, 1, 2]
+
+          adi,destination-bus-type:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Type of the destination bus (see adi,source-bus-type).
+            enum: [0, 1, 2]
+
+          adi,length-width:
+            deprecated: true
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the DMA transfer length register.
+
+          adi,cyclic:
+            deprecated: true
+            type: boolean
+            description:
+              Must be set if the channel supports hardware cyclic DMA transfers.
+
+          adi,2d:
+            deprecated: true
+            type: boolean
+            description:
+              Must be set if the channel supports hardware 2D DMA transfers.
+
+        required:
+          - reg
+          - adi,source-bus-width
+          - adi,destination-bus-width
+          - adi,source-bus-type
+          - adi,destination-bus-type
+
+    required:
+      - "#size-cells"
+      - "#address-cells"
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - "#dma-cells"
+
+examples:
+  - |
+    dma-controller@7c420000 {
+        compatible = "adi,axi-dmac-1.00.a";
+        reg = <0x7c420000 0x10000>;
+        interrupts = <0 57 0>;
+        clocks = <&clkc 16>;
+        #dma-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml b/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
index 02d5bd03540..9b5180c0a7c 100644
--- a/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
+++ b/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
@@ -22,7 +22,9 @@ properties:
       number.
 
   compatible:
-    const: allwinner,sun4i-a10-dma
+    enum:
+      - allwinner,sun4i-a10-dma
+      - allwinner,suniv-f1c100s-dma
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml b/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
new file mode 100644
index 00000000000..9ca1c5d1f00
--- /dev/null
+++ b/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Extensible Direct Memory Access Controller
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+  - Charan Pedumuru <charan.pedumuru@microchip.com>
+
+description:
+  The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
+  controller. It performs peripheral data transfer and memory move operations
+  over one or two bus ports through the unidirectional communication
+  channel. Each channel is fully programmable and provides both peripheral
+  or memory-to-memory transfers. The channel features are configurable at
+  implementation.
+
+allOf:
+  - $ref: dma-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,sama5d4-dma
+          - microchip,sama7g5-dma
+      - items:
+          - enum:
+              - microchip,sam9x60-dma
+              - microchip,sam9x7-dma
+          - const: atmel,sama5d4-dma
+
+  "#dma-cells":
+    description: |
+      Represents the number of integer cells in the `dmas` property of client
+      devices. The single cell specifies the channel configuration register:
+        - bit 13: SIF (Source Interface Identifier) for memory interface.
+        - bit 14: DIF (Destination Interface Identifier) for peripheral interface.
+        - bit 30-24: PERID (Peripheral Identifier).
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: dma_clk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/dma/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    dma-controller@f0008000 {
+        compatible = "atmel,sama5d4-dma";
+        reg = <0xf0008000 0x1000>;
+        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+        #dma-cells = <1>;
+        clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+        clock-names = "dma_clk";
+    };
diff --git a/dts/upstream/Bindings/dma/atmel-xdma.txt b/dts/upstream/Bindings/dma/atmel-xdma.txt
deleted file mode 100644
index 76d649b3a25..00000000000
--- a/dts/upstream/Bindings/dma/atmel-xdma.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* Atmel Extensible Direct Memory Access Controller (XDMAC)
-
-* XDMA Controller
-Required properties:
-- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
-  "microchip,sama7g5-dma" or
-  "microchip,sam9x7-dma", "atmel,sama5d4-dma".
-- reg: Should contain DMA registers location and length.
-- interrupts: Should contain DMA interrupt.
-- #dma-cells: Must be <1>, used to represent the number of integer cells in
-the dmas property of client devices.
-  - The 1st cell specifies the channel configuration register:
-    - bit 13: SIF, source interface identifier, used to get the memory
-    interface identifier,
-    - bit 14: DIF, destination interface identifier, used to get the peripheral
-    interface identifier,
-    - bit 30-24: PERID, peripheral identifier.
-
-Example:
-
-dma1: dma-controller@f0004000 {
-	compatible = "atmel,sama5d4-dma";
-	reg = <0xf0004000 0x200>;
-	interrupts = <50 4 0>;
-	#dma-cells = <1>;
-};
-
-
-* DMA clients
-DMA clients connected to the Atmel XDMA controller must use the format
-described in the dma.txt file, using a one-cell specifier for each channel.
-The two cells in order are:
-1. A phandle pointing to the DMA controller.
-2. Channel configuration register. Configurable fields are:
-    - bit 13: SIF, source interface identifier, used to get the memory
-    interface identifier,
-    - bit 14: DIF, destination interface identifier, used to get the peripheral
-    interface identifier,
-  - bit 30-24: PERID, peripheral identifier.
-
-Example:
-
-i2c2: i2c@f8024000 {
-	compatible = "atmel,at91sam9x5-i2c";
-	reg = <0xf8024000 0x4000>;
-	interrupts = <34 4 6>;
-	dmas = <&dma1
-		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
-		 | AT91_XDMAC_DT_PERID(6))>,
-	       <&dma1
-		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
-		| AT91_XDMAC_DT_PERID(7))>;
-	dma-names = "tx", "rx";
-};
diff --git a/dts/upstream/Bindings/dma/fsl,edma.yaml b/dts/upstream/Bindings/dma/fsl,edma.yaml
index d54140f18d3..4f925469533 100644
--- a/dts/upstream/Bindings/dma/fsl,edma.yaml
+++ b/dts/upstream/Bindings/dma/fsl,edma.yaml
@@ -26,9 +26,13 @@ properties:
           - fsl,imx93-edma3
           - fsl,imx93-edma4
           - fsl,imx95-edma5
+          - nxp,s32g2-edma
       - items:
           - const: fsl,ls1028a-edma
           - const: fsl,vf610-edma
+      - items:
+          - const: nxp,s32g3-edma
+          - const: nxp,s32g2-edma
 
   reg:
     minItems: 1
@@ -221,6 +225,36 @@ allOf:
       properties:
         power-domains: false
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nxp,s32g2-edma
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: dmamux0
+            - const: dmamux1
+        interrupts:
+          minItems: 3
+          maxItems: 3
+        interrupt-names:
+          items:
+            - const: tx-0-15
+            - const: tx-16-31
+            - const: err
+        reg:
+          minItems: 3
+          maxItems: 3
+        "#dma-cells":
+          const: 2
+        dma-channels:
+          const: 32
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
index 877147e95ec..d3f8c269916 100644
--- a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
+++ b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
@@ -13,9 +13,6 @@ description: |
 maintainers:
   - Jon Hunter <jonathanh@nvidia.com>
 
-allOf:
-  - $ref: dma-controller.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -29,7 +26,19 @@ properties:
           - const: nvidia,tegra186-adma
 
   reg:
-    maxItems: 1
+    description:
+      The 'page' region describes the address space of the page
+      used for accessing the DMA channel registers. The 'global'
+      region describes the address space of the global DMA registers.
+      In the absence of the 'reg-names' property, there must be a
+      single entry that covers the address space of the global DMA
+      registers and the DMA channel registers.
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
 
   interrupts:
     description: |
@@ -63,6 +72,49 @@ required:
   - clocks
   - clock-names
 
+allOf:
+  - $ref: dma-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra210-adma
+    then:
+      properties:
+        reg:
+          items:
+            - description: Full address space range of DMA registers.
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-adma
+    then:
+      anyOf:
+        - properties:
+            reg:
+              items:
+                - description: Full address space range of DMA registers.
+        - properties:
+            reg:
+              items:
+                - description: Channel Page address space range of DMA registers.
+            reg-names:
+              items:
+                - const: page
+        - properties:
+            reg:
+              items:
+                - description: Channel Page address space range of DMA registers.
+                - description: Global Page address space range of DMA registers.
+            reg-names:
+              items:
+                - const: page
+                - const: global
+
 additionalProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/dma/qcom,gpi.yaml b/dts/upstream/Bindings/dma/qcom,gpi.yaml
index 4ad56a409b9..7052468b15c 100644
--- a/dts/upstream/Bindings/dma/qcom,gpi.yaml
+++ b/dts/upstream/Bindings/dma/qcom,gpi.yaml
@@ -25,7 +25,9 @@ properties:
       - items:
           - enum:
               - qcom,qcm2290-gpi-dma
+              - qcom,qcs8300-gpi-dma
               - qcom,qdu1000-gpi-dma
+              - qcom,sa8775p-gpi-dma
               - qcom,sar2130p-gpi-dma
               - qcom,sc7280-gpi-dma
               - qcom,sdx75-gpi-dma
@@ -35,10 +37,12 @@ properties:
               - qcom,sm8450-gpi-dma
               - qcom,sm8550-gpi-dma
               - qcom,sm8650-gpi-dma
+              - qcom,sm8750-gpi-dma
               - qcom,x1e80100-gpi-dma
           - const: qcom,sm6350-gpi-dma
       - items:
           - enum:
+              - qcom,qcs615-gpi-dma
               - qcom,sdm670-gpi-dma
               - qcom,sm6125-gpi-dma
               - qcom,sm8150-gpi-dma
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
index f26c914a3a9..b7bca1a8376 100644
--- a/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
@@ -15,6 +15,16 @@ allOf:
 properties:
   "#dma-cells":
     const: 3
+    description: |
+      Each cell represents the following:
+      1. The mux input number/line for the request
+      2. Bitfield representing DMA channel configuration that is passed
+         to the real DMA controller
+      3. Bitfield representing device dependent DMA features passed to
+         the real DMA controller
+
+      For bitfield definitions of cells 2 and 3, see the associated
+      bindings doc for the actual DMA controller in st,stm32-dma.yaml.
 
   compatible:
     const: st,stm32h7-dmamux
diff --git a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
index 27b8e163656..b5bc842c5a0 100644
--- a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
+++ b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
@@ -34,6 +34,7 @@ properties:
       - ti,am62a-dmss-bcdma-csirx
       - ti,am64-dmss-bcdma
       - ti,j721s2-dmss-bcdma-csi
+      - ti,j722s-dmss-bcdma-csi
 
   reg:
     minItems: 3
@@ -196,7 +197,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: ti,j721s2-dmss-bcdma-csi
+            enum:
+              - ti,j721s2-dmss-bcdma-csi
+              - ti,j722s-dmss-bcdma-csi
     then:
       properties:
         ti,sci-rm-range-bchan: false
diff --git a/dts/upstream/Bindings/dts-coding-style.rst b/dts/upstream/Bindings/dts-coding-style.rst
index 8a68331075a..4772ded8a98 100644
--- a/dts/upstream/Bindings/dts-coding-style.rst
+++ b/dts/upstream/Bindings/dts-coding-style.rst
@@ -162,14 +162,17 @@ Example::
 		status = "okay";
 	}
 
-Indentation
------------
+Indentation and wrapping
+------------------------
 
-1. Use indentation according to Documentation/process/coding-style.rst.
+1. Use indentation and wrap lines according to
+   Documentation/process/coding-style.rst.
 2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
    shall be enclosed in <>.
-3. For arrays spanning across lines, it is preferred to align the continued
-   entries with opening < from the first line.
+3. For arrays spanning across lines, it is preferred to split on item boundary
+   and align the continued entries with opening < from the first line.
+   Usually avoid splitting individual items unless they significantly exceed
+   line wrap limit.
 
 Example::
 
@@ -177,6 +180,9 @@ Example::
 		compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
 		reg = <0x0 0x0c271000 0x0 0x1000>,
 		      <0x0 0x0c222000 0x0 0x1000>;
+		/* Lines exceeding coding style line wrap limit: */
+		interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
 	};
 
 Organizing DTSI and DTS
diff --git a/dts/upstream/Bindings/eeprom/at24.yaml b/dts/upstream/Bindings/eeprom/at24.yaml
index 590ba0ef5fa..c9e4afbdc44 100644
--- a/dts/upstream/Bindings/eeprom/at24.yaml
+++ b/dts/upstream/Bindings/eeprom/at24.yaml
@@ -134,10 +134,15 @@ properties:
           - const: atmel,24c64
       - items:
           - enum:
+              - giantec,gt24p128f
               - renesas,r1ex24128
               - samsung,s524ad0xd1
           - const: atmel,24c128
       - items:
+          - enum:
+              - puya,p24c256c
+          - const: atmel,24c256
+      - items:
           - const: microchip,24aa025e48
       - items:
           - const: microchip,24aa025e64
diff --git a/dts/upstream/Bindings/firmware/qcom,scm.yaml b/dts/upstream/Bindings/firmware/qcom,scm.yaml
index 2ee03000000..8cdaac8011b 100644
--- a/dts/upstream/Bindings/firmware/qcom,scm.yaml
+++ b/dts/upstream/Bindings/firmware/qcom,scm.yaml
@@ -26,6 +26,7 @@ properties:
           - qcom,scm-ipq4019
           - qcom,scm-ipq5018
           - qcom,scm-ipq5332
+          - qcom,scm-ipq5424
           - qcom,scm-ipq6018
           - qcom,scm-ipq806x
           - qcom,scm-ipq8074
@@ -42,6 +43,7 @@ properties:
           - qcom,scm-msm8996
           - qcom,scm-msm8998
           - qcom,scm-qcm2290
+          - qcom,scm-qcs615
           - qcom,scm-qcs8300
           - qcom,scm-qdu1000
           - qcom,scm-sa8255p
diff --git a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
index f096f286da1..fbd69b4cecc 100644
--- a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
@@ -64,6 +64,10 @@ properties:
 
   gpio-ranges: true
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 128
+
   wakeup-source:
     type: boolean
     description: >
diff --git a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
index e8bc9f018ed..0e5c22929bd 100644
--- a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
+++ b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
@@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Generic 8-bit shift register
 
+description: |
+  NOTE: These chips nominally don't have a chip select pin. They do however
+  have a rising-edge triggered latch clock (or storage register clock) pin,
+  which behaves like an active-low chip select.
+
+  After the bits are shifted into the shift register, CS# is driven high, which
+  the 74HC595 sees as a rising edge on the latch clock that results in a
+  transfer of the bits from the shift register to the storage register and thus
+  to the output pins.
+                      _   _       _   _
+  shift clock    ____| |_| |_..._| |_| |_________
+
+  latch clock                           * trigger
+                 ___                     ________
+  chip select#      |___________________|
+
+
 maintainers:
   - Maxime Ripard <mripard@kernel.org>
 
diff --git a/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
index 84fd82291ee..f1b60ab3f35 100644
--- a/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
@@ -15,6 +15,7 @@ properties:
       - enum:
           - fsl,mpc5121-gpio
           - fsl,mpc5125-gpio
+          - fsl,mpc8314-gpio
           - fsl,mpc8349-gpio
           - fsl,mpc8572-gpio
           - fsl,mpc8610-gpio
diff --git a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
index abd4aa335fb..9318817ea13 100644
--- a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
+++ b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
@@ -33,6 +33,7 @@ properties:
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
+              - st,stih410-mali
               - stericsson,db8500-mali
               - xlnx,zynqmp-mali
           - const: arm,mali-400
diff --git a/dts/upstream/Bindings/hwmon/adi,adm1275.yaml b/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
index 5b076d67739..fd79bf2e0d1 100644
--- a/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
+++ b/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
@@ -24,6 +24,7 @@ properties:
     enum:
       - adi,adm1075
       - adi,adm1272
+      - adi,adm1273
       - adi,adm1275
       - adi,adm1276
       - adi,adm1278
@@ -79,6 +80,7 @@ allOf:
           contains:
             enum:
               - adi,adm1272
+              - adi,adm1273
     then:
       properties:
         adi,volt-curr-sample-average:
diff --git a/dts/upstream/Bindings/hwmon/lm75.yaml b/dts/upstream/Bindings/hwmon/lm75.yaml
index 29bd7460cc2..c38255243f5 100644
--- a/dts/upstream/Bindings/hwmon/lm75.yaml
+++ b/dts/upstream/Bindings/hwmon/lm75.yaml
@@ -28,6 +28,7 @@ properties:
       - maxim,max31725
       - maxim,max31726
       - maxim,mcp980x
+      - nxp,p3t1755
       - nxp,pct2075
       - st,stds75
       - st,stlm75
diff --git a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
index cc8bba5537b..70cc2ee9ee2 100644
--- a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
@@ -25,6 +25,7 @@ properties:
           - samsung,exynos5250-hsi2c    # Exynos5250 and Exynos5420
           - samsung,exynos5260-hsi2c    # Exynos5260
           - samsung,exynos7-hsi2c       # Exynos7
+          - samsung,exynos8895-hsi2c
           - samsung,exynosautov9-hsi2c
       - items:
           - enum:
diff --git a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
index ef26ba6eda2..73144473b9b 100644
--- a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
+++ b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
@@ -34,6 +34,7 @@ properties:
               - qcom,sm8450-cci
               - qcom,sm8550-cci
               - qcom,sm8650-cci
+              - qcom,x1e80100-cci
           - const: qcom,msm8996-cci # CCI v2
 
   "#address-cells":
@@ -224,6 +225,7 @@ allOf:
             enum:
               - qcom,sm8550-cci
               - qcom,sm8650-cci
+              - qcom,x1e80100-cci
     then:
       properties:
         clocks:
diff --git a/dts/upstream/Bindings/i2c/renesas,riic.yaml b/dts/upstream/Bindings/i2c/renesas,riic.yaml
index 505a8ec9226..1b7fed23264 100644
--- a/dts/upstream/Bindings/i2c/renesas,riic.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,riic.yaml
@@ -26,7 +26,9 @@ properties:
           - const: renesas,riic-rz      # RZ/A or RZ/G2L
 
       - items:
-          - const: renesas,riic-r9a08g045   # RZ/G3S
+          - enum:
+              - renesas,riic-r9a08g045   # RZ/G3S
+              - renesas,riic-r9a09g047   # RZ/G3E
           - const: renesas,riic-r9a09g057   # RZ/V2H(P)
 
       - const: renesas,riic-r9a09g057   # RZ/V2H(P)
@@ -89,6 +91,7 @@ if:
           - renesas,riic-r9a07g043
           - renesas,riic-r9a07g044
           - renesas,riic-r9a07g054
+          - renesas,riic-r9a09g057
 then:
   required:
     - resets
diff --git a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
index 280ed479ef5..84d94939201 100644
--- a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
+++ b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
@@ -37,10 +37,17 @@ properties:
   interrupts:
     maxItems: 1
 
+  interrupt-names:
+    items:
+      - enum: [INT1, INT2]
+
+dependencies:
+  interrupts: [ interrupt-names ]
+  interrupt-names: [ interrupts ]
+
 required:
   - compatible
   - reg
-  - interrupts
 
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
@@ -61,6 +68,7 @@ examples:
             reg = <0x2a>;
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "INT1";
         };
     };
   - |
@@ -79,5 +87,6 @@ examples:
             spi-cpha;
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "INT2";
         };
     };
diff --git a/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml b/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
index 66ea894dbe5..f07c70e51c4 100644
--- a/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
+++ b/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
@@ -4,23 +4,26 @@
 $id: http://devicetree.org/schemas/iio/accel/kionix,kx022a.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: ROHM/Kionix KX022A, KX132-1211 and KX132ACR-LBZ Accelerometers
+title: ROHM/Kionix KX022A, KX132/134-1211 and KX132/134ACR-LBZ Accelerometers
 
 maintainers:
   - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   KX022A, KX132ACR-LBZ and KX132-1211 are 3-axis accelerometers supporting
-  +/- 2G, 4G, 8G and 16G ranges, variable output data-rates and a
-  hardware-fifo buffering. These accelerometers can be accessed either
-  via I2C or SPI.
+  +/- 2G, 4G, 8G and 16G ranges. The KX134ACR-LBZ and KX134-1211 support
+  +/- 8G, 16G, 32G and 64G. All the sensors also have variable output
+  data-rates and a hardware-fifo buffering. These accelerometers can be
+  accessed either via I2C or SPI.
 
 properties:
   compatible:
     enum:
       - kionix,kx022a
       - kionix,kx132-1211
+      - kionix,kx134-1211
       - rohm,kx132acr-lbz
+      - rohm,kx134acr-lbz
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml b/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
index 783c7ddfcd9..c175f4c4cbd 100644
--- a/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
+++ b/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
@@ -14,12 +14,20 @@ description: |
   SPI and I2C interface.
     https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf
     https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf
+    https://www.nxp.com/docs/en/data-sheet/FXLS8967AF.pdf
+    https://www.nxp.com/docs/en/data-sheet/FXLS8974CF.pdf
 
 properties:
   compatible:
-    enum:
-      - nxp,fxls8962af
-      - nxp,fxls8964af
+    oneOf:
+      - enum:
+          - nxp,fxls8962af
+          - nxp,fxls8964af
+      - items:
+          - enum:
+              - nxp,fxls8967af
+              - nxp,fxls8974cf
+          - const: nxp,fxls8962af
 
   reg:
     maxItems: 1
@@ -38,6 +46,11 @@ properties:
   drive-open-drain:
     type: boolean
 
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable wake on accelerometer event
+
 required:
   - compatible
   - reg
@@ -61,6 +74,7 @@ examples:
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "INT1";
+            wakeup-source;
         };
     };
   - |
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml b/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
index e413a9d8d2a..96e01a97dd9 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
@@ -19,49 +19,82 @@ description: |
     https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
     https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
     https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4003.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7685.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7686.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7687.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7688.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7690.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7691.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7693.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7942.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7946.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7982.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7983.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7984.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7988-1_7988-5.pdf
 
 $ref: /schemas/spi/spi-peripheral-props.yaml#
 
 properties:
   compatible:
     oneOf:
-      - const: adi,ad4000
+      - enum:
+          - adi,ad4000
+          - adi,ad4001
+          - adi,ad4002
+          - adi,ad4003
+          - adi,ad4020
+          - adi,adaq4001
+          - adi,adaq4003
+          - adi,ad7687
+          - adi,ad7691
+          - adi,ad7942
+          - adi,ad7946
+          - adi,ad7983
       - items:
           - enum:
               - adi,ad4004
               - adi,ad4008
           - const: adi,ad4000
-
-      - const: adi,ad4001
       - items:
           - enum:
               - adi,ad4005
           - const: adi,ad4001
-
-      - const: adi,ad4002
       - items:
           - enum:
               - adi,ad4006
               - adi,ad4010
           - const: adi,ad4002
-
-      - const: adi,ad4003
       - items:
           - enum:
               - adi,ad4007
               - adi,ad4011
           - const: adi,ad4003
-
-      - const: adi,ad4020
       - items:
           - enum:
               - adi,ad4021
               - adi,ad4022
           - const: adi,ad4020
-
-      - const: adi,adaq4001
-
-      - const: adi,adaq4003
+      - items:
+          - enum:
+              - adi,ad7685
+              - adi,ad7686
+              - adi,ad7980
+              - adi,ad7988-1
+              - adi,ad7988-5
+          - const: adi,ad7983
+      - items:
+          - enum:
+              - adi,ad7688
+              - adi,ad7693
+          - const: adi,ad7687
+      - items:
+          - enum:
+              - adi,ad7690
+              - adi,ad7982
+              - adi,ad7984
+          - const: adi,ad7691
 
   reg:
     maxItems: 1
@@ -133,6 +166,22 @@ required:
   - ref-supply
 
 allOf:
+  # Single-channel PulSAR devices have SDI either tied to VIO, GND, or host CS.
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,ad7687
+              - adi,ad7691
+              - adi,ad7942
+              - adi,ad7946
+              - adi,ad7983
+    then:
+      properties:
+        adi,sdi-pin:
+          enum: [ high, low, cs ]
+          default: cs
   # The configuration register can only be accessed if SDI is connected to MOSI
   - if:
       required:
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml b/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
index 310f046e139..7d2229dee44 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
@@ -134,8 +134,9 @@ patternProperties:
         description:
           Describes the common mode channel for single channels. 0xFF is REFGND
           and OxFE is COM. Macros are available for these values in
-          dt-bindings/iio/adi,ad4695.h. Values 1 to 15 correspond to INx inputs.
-          Only odd numbered INx inputs can be used as common mode channels.
+          dt-bindings/iio/adc/adi,ad4695.h. Values 1 to 15 correspond to INx
+          inputs. Only odd numbered INx inputs can be used as common mode
+          channels.
         enum: [1, 3, 5, 7, 9, 11, 13, 15, 0xFE, 0xFF]
         default: 0xFF
 
@@ -209,7 +210,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/gpio/gpio.h>
-    #include <dt-bindings/iio/adi,ad4695.h>
+    #include <dt-bindings/iio/adc/adi,ad4695.h>
 
     spi {
         #address-cells = <1>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
index 35ed04350e2..7146a654ae3 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
@@ -37,6 +37,17 @@ properties:
     description: IRQ line for the ADC
     maxItems: 1
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
   '#address-cells':
     const: 1
 
@@ -111,6 +122,7 @@ unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
       #address-cells = <1>;
       #size-cells = <0>;
@@ -121,6 +133,7 @@ examples:
         spi-max-frequency = <5000000>;
         interrupts = <25 2>;
         interrupt-parent = <&gpio>;
+        rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
         refin1-supply = <&adc_vref>;
         clocks = <&ad7124_mclk>;
         clock-names = "mclk";
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
index ad15cf9bc2f..21ee319d467 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
@@ -135,6 +135,17 @@ properties:
   '#clock-cells':
     const: 0
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 patternProperties:
   "^channel@[0-9a-f]$":
     type: object
@@ -443,6 +454,7 @@ examples:
         interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
         interrupt-names = "rdy";
         interrupt-parent = <&gpio>;
+        rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
         spi-max-frequency = <5000000>;
         gpio-controller;
         #gpio-cells = <2>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
index 66dd1c549bd..0bd2c6906c8 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
@@ -106,6 +106,17 @@ properties:
     description: see Documentation/devicetree/bindings/iio/adc/adc.yaml
     type: boolean
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 patternProperties:
   "^channel@[0-9a-f]+$":
     type: object
@@ -181,6 +192,7 @@ unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
         #address-cells = <1>;
         #size-cells = <0>;
@@ -195,6 +207,7 @@ examples:
             clock-names = "mclk";
             interrupts = <25 0x2>;
             interrupt-parent = <&gpio>;
+            rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
             aincom-supply = <&aincom>;
             dvdd-supply = <&dvdd>;
             avdd-supply = <&avdd>;
@@ -207,6 +220,7 @@ examples:
         };
     };
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
         #address-cells = <1>;
         #size-cells = <0>;
@@ -224,6 +238,7 @@ examples:
             #clock-cells = <0>;
             interrupts = <25 0x2>;
             interrupt-parent = <&gpio>;
+            rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
             aincom-supply = <&aincom>;
             dvdd-supply = <&dvdd>;
             avdd-supply = <&avdd>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
index ab5881d0d01..52d3f1ce336 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
@@ -146,6 +146,7 @@ properties:
     maxItems: 2
 
   pwm-names:
+    minItems: 1
     items:
       - const: convst1
       - const: convst2
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
index be2616ff9af..5c8df45bfab 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
@@ -63,6 +63,17 @@ properties:
       marked GPIO_ACTIVE_LOW.
     maxItems: 1
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 required:
   - compatible
   - reg
diff --git a/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml b/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
index ba86c7b7d62..40341d54172 100644
--- a/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -17,12 +17,15 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
-          - renesas,r9a07g044-adc   # RZ/G2L
-          - renesas,r9a07g054-adc   # RZ/V2L
-      - const: renesas,rzg2l-adc
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
+              - renesas,r9a07g044-adc   # RZ/G2L
+              - renesas,r9a07g054-adc   # RZ/V2L
+          - const: renesas,rzg2l-adc
+      - items:
+          - const: renesas,r9a08g045-adc  # RZ/G3S
 
   reg:
     maxItems: 1
@@ -57,6 +60,9 @@ properties:
   '#size-cells':
     const: 0
 
+  "#io-channel-cells":
+    const: 1
+
 required:
   - compatible
   - reg
@@ -68,7 +74,7 @@ required:
   - reset-names
 
 patternProperties:
-  "^channel@[0-7]$":
+  "^channel@[0-8]$":
     $ref: adc.yaml
     type: object
     description: |
@@ -78,6 +84,8 @@ patternProperties:
       reg:
         description: |
           The channel number.
+        minimum: 0
+        maximum: 8
 
     required:
       - reg
@@ -92,18 +100,25 @@ allOf:
             const: renesas,r9a07g043-adc
     then:
       patternProperties:
-        "^channel@[2-7]$": false
+        "^channel@[2-8]$": false
         "^channel@[0-1]$":
           properties:
             reg:
-              minimum: 0
               maximum: 1
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g044-adc
+              - renesas,r9a07g054-adc
+    then:
       patternProperties:
+        "^channel@[8]$": false
         "^channel@[0-7]$":
           properties:
             reg:
-              minimum: 0
               maximum: 7
 
 additionalProperties: false
diff --git a/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml b/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml
new file mode 100644
index 00000000000..fe98ec44f08
--- /dev/null
+++ b/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/chemical/bosch,bme680.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BME680 Gas sensor
+
+maintainers:
+  - Vasileios Amoiridis <vassilisamir@gmail.com>
+
+description: >
+  BME680 is a gas sensor which combines relative humidity, barometric pressure,
+  ambient temperature and gas (VOC - Volatile Organic Compounds) measurements.
+
+  https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf
+
+properties:
+  compatible:
+    const: bosch,bme680
+
+  reg:
+    maxItems: 1
+
+  vdd-supply: true
+  vddio-supply: true
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        co2-sensor@77 {
+            compatible = "bosch,bme680";
+            reg = <0x77>;
+            vddio-supply = <&vddio>;
+            vdd-supply = <&vdd>;
+        };
+    };
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        co2-sensor@0 {
+            compatible = "bosch,bme680";
+            reg = <0>;
+            spi-max-frequency = <500000>;
+            vddio-supply = <&vddio>;
+            vdd-supply = <&vdd>;
+        };
+    };
diff --git a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
index 79cb4b78a88..2bd89e0aa46 100644
--- a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
+++ b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
@@ -91,7 +91,7 @@ examples:
             vrefn-supply = <&dac_vrefn>;
             reset-gpios = <&gpio_bd 16 GPIO_ACTIVE_LOW>;
             clear-gpios = <&gpio_bd 17 GPIO_ACTIVE_LOW>;
-            ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_HIGH>;
+            ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_LOW>;
         };
     };
 ...
diff --git a/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml b/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml
new file mode 100644
index 00000000000..941a49c9394
--- /dev/null
+++ b/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2024 ROHM Semiconductor.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/rohm,bd79703.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD79703 DAC device driver
+
+maintainers:
+  - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description: |
+  The ROHM BD79703 is a 6 channel, 8-bit DAC.
+  Datasheet can be found here:
+  https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79702fv-lb_bd79703fv-lb-e.pdf
+
+properties:
+  compatible:
+    const: rohm,bd79703
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 30000000
+
+  vfs-supply:
+    description:
+      The regulator to use as a full scale voltage. The voltage should be between 2.7V .. VCC
+
+  vcc-supply:
+    description:
+      The regulator supplying the operating voltage. Should be between 2.7V ... 5.5V
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+  - vfs-supply
+  - vcc-supply
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        dac@0 {
+            compatible = "rohm,bd79703";
+            reg = <0>;
+            spi-max-frequency = <30000000>;
+            vcc-supply = <&vcc>;
+            vfs-supply = <&vref>;
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
index e3eec38897b..7a1a74fec28 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
@@ -11,24 +11,30 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - adi,adis16375
-      - adi,adis16480
-      - adi,adis16485
-      - adi,adis16488
-      - adi,adis16490
-      - adi,adis16495-1
-      - adi,adis16495-2
-      - adi,adis16495-3
-      - adi,adis16497-1
-      - adi,adis16497-2
-      - adi,adis16497-3
-      - adi,adis16545-1
-      - adi,adis16545-2
-      - adi,adis16545-3
-      - adi,adis16547-1
-      - adi,adis16547-2
-      - adi,adis16547-3
+    oneOf:
+      - enum:
+          - adi,adis16375
+          - adi,adis16480
+          - adi,adis16485
+          - adi,adis16486
+          - adi,adis16488
+          - adi,adis16489
+          - adi,adis16490
+          - adi,adis16495-1
+          - adi,adis16495-2
+          - adi,adis16495-3
+          - adi,adis16497-1
+          - adi,adis16497-2
+          - adi,adis16497-3
+          - adi,adis16545-1
+          - adi,adis16545-2
+          - adi,adis16545-3
+          - adi,adis16547-1
+          - adi,adis16547-2
+          - adi,adis16547-3
+      - items:
+          - const: adi,adis16487
+          - const: adi,adis16485
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
index 3b0a2d8b2e9..2cf8a0c7eb4 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
@@ -37,6 +37,7 @@ properties:
       to "INT2" if INT2 pin should be used instead
 
   drive-open-drain:
+    type: boolean
     description: |
       set if the specified interrupt pin should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
index 7b0cde1c9b0..860a6c1fea3 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
@@ -41,6 +41,7 @@ properties:
         - INT2
 
   drive-open-drain:
+    type: boolean
     description:
       set if the specified interrupt pins should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
index 64ef26e1966..7bf8294a8f2 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
@@ -38,6 +38,7 @@ properties:
         - INT2
 
   drive-open-drain:
+    type: boolean
     description:
       set if the specified interrupt pin should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
index f91954870a4..0bce71529e3 100644
--- a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
+++ b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - invensense,iam20380
           - invensense,iam20680
           - invensense,icm20608
           - invensense,icm20609
diff --git a/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml b/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml
deleted file mode 100644
index 4f66fd47b01..00000000000
--- a/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/iio/light/rohm,bu27008.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ROHM BU27008 color sensor
-
-maintainers:
-  - Matti Vaittinen <mazziesaccount@gmail.com>
-
-description:
-  The ROHM BU27008 is a sensor with 5 photodiodes (red, green, blue, clear
-  and IR) with four configurable channels. Red and green being always
-  available and two out of the rest three (blue, clear, IR) can be
-  selected to be simultaneously measured. Typical application is adjusting
-  LCD backlight of TVs, mobile phones and tablet PCs.
-
-properties:
-  compatible:
-    const: rohm,bu27008
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  vdd-supply: true
-
-required:
-  - compatible
-  - reg
-
-additionalProperties: false
-
-examples:
-  - |
-    i2c {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      light-sensor@38 {
-        compatible = "rohm,bu27008";
-        reg = <0x38>;
-      };
-    };
-
-...
diff --git a/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml b/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml
deleted file mode 100644
index bed42d5d0d9..00000000000
--- a/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/iio/light/rohm,bu27010.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ROHM BU27010 color sensor
-
-maintainers:
-  - Matti Vaittinen <mazziesaccount@gmail.com>
-
-description: |
-  The ROHM BU27010 is a sensor with 6 photodiodes (red, green, blue, clear,
-  IR and flickering detection) with five configurable channels. Red, green
-  and flickering detection being always available and two out of the rest
-  three (blue, clear, IR) can be selected to be simultaneously measured.
-  Typical application is adjusting LCD/OLED backlight of TVs, mobile phones
-  and tablet PCs.
-
-properties:
-  compatible:
-    const: rohm,bu27010
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  vdd-supply: true
-
-required:
-  - compatible
-  - reg
-  - vdd-supply
-
-additionalProperties: false
-
-examples:
-  - |
-    i2c {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      light-sensor@38 {
-        compatible = "rohm,bu27010";
-        reg = <0x38>;
-        vdd-supply = <&vdd>;
-      };
-    };
diff --git a/dts/upstream/Bindings/iio/light/ti,opt4060.yaml b/dts/upstream/Bindings/iio/light/ti,opt4060.yaml
new file mode 100644
index 00000000000..568fb2a9b7a
--- /dev/null
+++ b/dts/upstream/Bindings/iio/light/ti,opt4060.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/ti,opt4060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OPT4060 RGBW Color Sensor
+
+maintainers:
+  - Per-Daniel Olsson <perdaniel.olsson@axis.com>
+
+description:
+  Texas Instrument RGBW high resolution color sensor over I2C.
+  https://www.ti.com/lit/gpn/opt4060
+
+properties:
+  compatible:
+    enum:
+      - ti,opt4060
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  vdd-supply: true
+
+required:
+  - compatible
+  - reg
+  - vdd-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        light-sensor@44 {
+            compatible = "ti,opt4060";
+            reg = <0x44>;
+            vdd-supply = <&vdd_reg>;
+            interrupt-parent = <&gpio5>;
+            interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/iio/pressure/bmp085.yaml b/dts/upstream/Bindings/iio/pressure/bmp085.yaml
index cb201cecfa1..706b7e24f18 100644
--- a/dts/upstream/Bindings/iio/pressure/bmp085.yaml
+++ b/dts/upstream/Bindings/iio/pressure/bmp085.yaml
@@ -55,12 +55,16 @@ properties:
       If not set, defaults to push-pull configuration.
     type: boolean
 
+  spi-max-frequency:
+    maximum: 10000000
+
 required:
   - compatible
   - vddd-supply
   - vdda-supply
 
 allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
   - if:
       properties:
         compatible:
@@ -73,6 +77,16 @@ allOf:
     then:
       properties:
         interrupts: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - bosch,bmp085
+              - bosch,bmp180
+    then:
+      properties:
+        spi-max-frequency: false
 
 additionalProperties: false
 
@@ -93,3 +107,18 @@ examples:
             vdda-supply = <&bar>;
         };
     };
+  - |
+    # include <dt-bindings/gpio/gpio.h>
+    # include <dt-bindings/interrupt-controller/irq.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pressure@0 {
+            compatible = "bosch,bmp280";
+            reg = <0>;
+            spi-max-frequency = <10000000>;
+            reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+            vddd-supply = <&foo>;
+            vdda-supply = <&bar>;
+        };
+    };
diff --git a/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml b/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
index 47aac8794b6..517a4ac1bea 100644
--- a/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
+++ b/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
@@ -26,6 +26,9 @@ properties:
       - items:
           - enum:
               - mediatek,mt6873-keypad
+              - mediatek,mt8183-keypad
+              - mediatek,mt8365-keypad
+              - mediatek,mt8516-keypad
           - const: mediatek,mt6779-keypad
 
   reg:
diff --git a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
index 60f09caa0e4..b95435bd6a9 100644
--- a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
+++ b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     enum:
       - mediatek,mt6323-keys
+      - mediatek,mt6328-keys
       - mediatek,mt6331-keys
       - mediatek,mt6357-keys
       - mediatek,mt6358-keys
diff --git a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
index e24cbd96099..bd8ede3a4ad 100644
--- a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
@@ -19,6 +19,7 @@ properties:
       - imagis,ist3038
       - imagis,ist3038b
       - imagis,ist3038c
+      - imagis,ist3038h
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
index 251410aabf3..83bcf0575cd 100644
--- a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -26,6 +26,7 @@ properties:
       - items:
           - enum:
               - qcom,qcm2290-cpu-bwmon
+              - qcom,qcs615-cpu-bwmon
               - qcom,qcs8300-cpu-bwmon
               - qcom,sa8775p-cpu-bwmon
               - qcom,sc7180-cpu-bwmon
@@ -37,10 +38,12 @@ properties:
               - qcom,sm8250-cpu-bwmon
               - qcom,sm8550-cpu-bwmon
               - qcom,sm8650-cpu-bwmon
+              - qcom,sm8750-cpu-bwmon
               - qcom,x1e80100-cpu-bwmon
           - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
       - items:
           - enum:
+              - qcom,qcs615-llcc-bwmon
               - qcom,qcs8300-llcc-bwmon
               - qcom,sa8775p-llcc-bwmon
               - qcom,sc7180-llcc-bwmon
diff --git a/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml b/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
index 21dae0b9281..4ac0863205b 100644
--- a/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
@@ -33,6 +33,7 @@ properties:
               - qcom,sm6375-cpucp-l3
               - qcom,sm8250-epss-l3
               - qcom,sm8350-epss-l3
+              - qcom,sm8650-epss-l3
           - const: qcom,epss-l3
 
   reg:
diff --git a/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml
new file mode 100644
index 00000000000..a816acc301e
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm8750-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on SM8750
+
+maintainers:
+  - Abel Vesa <abel.vesa@linaro.org>
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+description: |
+  RPMh interconnect providers support system bandwidth requirements through
+  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+  able to communicate with the BCM through the Resource State Coordinator (RSC)
+  associated with each execution environment. Provider nodes must point to at
+  least one RPMh device child node pertaining to their RSC and each provider
+  can map to multiple RPMh resources.
+
+  See also:: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm8750-aggre1-noc
+      - qcom,sm8750-aggre2-noc
+      - qcom,sm8750-clk-virt
+      - qcom,sm8750-cnoc-main
+      - qcom,sm8750-config-noc
+      - qcom,sm8750-gem-noc
+      - qcom,sm8750-lpass-ag-noc
+      - qcom,sm8750-lpass-lpiaon-noc
+      - qcom,sm8750-lpass-lpicx-noc
+      - qcom,sm8750-mc-virt
+      - qcom,sm8750-mmss-noc
+      - qcom,sm8750-nsp-noc
+      - qcom,sm8750-pcie-anoc
+      - qcom,sm8750-system-noc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+required:
+  - compatible
+
+allOf:
+  - $ref: qcom,rpmh-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-clk-virt
+              - qcom,sm8750-mc-virt
+    then:
+      properties:
+        reg: false
+    else:
+      required:
+        - reg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-pcie-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre-NOC PCIe AXI clock
+            - description: cfg-NOC PCIe a-NOC AHB clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+            - description: aggre USB3 PRIM AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre2-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: RPMH CC IPA clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre1-noc
+              - qcom,sm8750-aggre2-noc
+              - qcom,sm8750-pcie-anoc
+    then:
+      required:
+        - clocks
+    else:
+      properties:
+        clocks: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    clk_virt: interconnect-0 {
+      compatible = "qcom,sm8750-clk-virt";
+      #interconnect-cells = <2>;
+      qcom,bcm-voters = <&apps_bcm_voter>;
+    };
+
+    aggre1_noc: interconnect@16e0000 {
+      compatible = "qcom,sm8750-aggre1-noc";
+      reg = <0x016e0000 0x16400>;
+      #interconnect-cells = <2>;
+      clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
+      qcom,bcm-voters = <&apps_bcm_voter>;
+    };
diff --git a/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml b/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
index a2846e49349..7173c4b5a22 100644
--- a/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
@@ -110,8 +110,8 @@ properties:
 
   interrupts:
     description: Interrupt source of the parent interrupt controller on
-      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
-      below).
+      secondary GICs, or VGIC maintenance interrupt on primary GIC (see "GICv2
+      with virtualization extensions" paragraph in the "reg" property).
     maxItems: 1
 
   cpu-offset:
diff --git a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
index 73e8b9a39bd..86516cd44b9 100644
--- a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
@@ -52,11 +52,11 @@ additionalProperties: false
 examples:
   - |
     interrupt-controller@1e6c0080 {
-         compatible = "aspeed,ast2400-vic";
-         reg = <0x1e6c0080 0x80>;
-         interrupt-controller;
-         #interrupt-cells = <1>;
-         valid-sources = <0xffffffff 0x0007ffff>;
+        compatible = "aspeed,ast2400-vic";
+        reg = <0x1e6c0080 0x80>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        valid-sources = <0xffffffff 0x0007ffff>;
     };
 
 ...
diff --git a/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
index 786f2426399..0fcbe304cd0 100644
--- a/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -130,23 +130,23 @@ required:
 examples:
   - |
     irq0_intc: interrupt-controller@f0406800 {
-      compatible = "brcm,bcm7120-l2-intc";
-      interrupt-parent = <&intc>;
-      #interrupt-cells = <1>;
-      reg = <0xf0406800 0x8>;
-      interrupt-controller;
-      interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
-      brcm,int-map-mask = <0xeb8>, <0x140>;
-      brcm,int-fwd-mask = <0x7>;
+        compatible = "brcm,bcm7120-l2-intc";
+        interrupt-parent = <&intc>;
+        #interrupt-cells = <1>;
+        reg = <0xf0406800 0x8>;
+        interrupt-controller;
+        interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+        brcm,int-map-mask = <0xeb8>, <0x140>;
+        brcm,int-fwd-mask = <0x7>;
     };
 
   - |
     irq1_intc: interrupt-controller@10000020 {
-       compatible = "brcm,bcm3380-l2-intc";
-       reg = <0x10000024 0x4>, <0x1000002c 0x4>,
-             <0x10000020 0x4>, <0x10000028 0x4>;
-       interrupt-controller;
-       #interrupt-cells = <1>;
-       interrupt-parent = <&cpu_intc>;
-       interrupts = <2>;
+        compatible = "brcm,bcm3380-l2-intc";
+        reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+              <0x10000020 0x4>, <0x10000028 0x4>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&cpu_intc>;
+        interrupts = <2>;
     };
diff --git a/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
index b2adc717417..dca16e202da 100644
--- a/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
@@ -14,9 +14,8 @@ allOf:
 
 description: |
   The Microchip LAN966x outband interrupt controller (OIC) maps the internal
-  interrupt sources of the LAN966x device to an external interrupt.
-  When the LAN966x device is used as a PCI device, the external interrupt is
-  routed to the PCI interrupt.
+  interrupt sources of the LAN966x device to a PCI interrupt when the LAN966x
+  device is used as a PCI device.
 
 properties:
   compatible:
diff --git a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
index a54da66a89e..f06b40f8877 100644
--- a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,8 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-pdc
+          - qcom,qcs8300-pdc
           - qcom,qdu1000-pdc
           - qcom,sa8255p-pdc
           - qcom,sa8775p-pdc
@@ -47,6 +49,7 @@ properties:
           - qcom,sm8450-pdc
           - qcom,sm8550-pdc
           - qcom,sm8650-pdc
+          - qcom,sm8750-pdc
           - qcom,x1e80100-pdc
       - const: qcom,pdc
 
diff --git a/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml b/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
index 84976f17a4a..c23b5c09fdb 100644
--- a/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
@@ -142,7 +142,7 @@ examples:
                             <&cpu2_intc 11>,
                             <&cpu3_intc 11>,
                             <&cpu4_intc 11>;
-      reg = <0x28000000 0x4000>;
+      reg = <0x24000000 0x4000>;
       interrupt-controller;
       #interrupt-cells = <0>;
       msi-controller;
diff --git a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 7e1451f9786..3dfe425909d 100644
--- a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -59,6 +59,7 @@ properties:
           - enum:
               - canaan,k210-plic
               - sifive,fu540-c000-plic
+              - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
           - const: sifive,plic-1.0.0
diff --git a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.txt
index 422d6908f8b..422d6908f8b 100644
--- a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu
+++ b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.txt
diff --git a/dts/upstream/Bindings/iommu/arm,smmu.yaml b/dts/upstream/Bindings/iommu/arm,smmu.yaml
index c1e11bc6b7a..032fdc27127 100644
--- a/dts/upstream/Bindings/iommu/arm,smmu.yaml
+++ b/dts/upstream/Bindings/iommu/arm,smmu.yaml
@@ -61,6 +61,7 @@ properties:
               - qcom,sm8450-smmu-500
               - qcom,sm8550-smmu-500
               - qcom,sm8650-smmu-500
+              - qcom,sm8750-smmu-500
               - qcom,x1e80100-smmu-500
           - const: qcom,smmu-500
           - const: arm,mmu-500
@@ -88,6 +89,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-smmu-500
+              - qcom,qcs615-smmu-500
               - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sar2130p-smmu-500
@@ -102,6 +104,7 @@ properties:
               - qcom,sm8450-smmu-500
               - qcom,sm8550-smmu-500
               - qcom,sm8650-smmu-500
+              - qcom,sm8750-smmu-500
               - qcom,x1e80100-smmu-500
           - const: qcom,adreno-smmu
           - const: qcom,smmu-500
@@ -122,6 +125,7 @@ properties:
               - qcom,msm8996-smmu-v2
               - qcom,sc7180-smmu-v2
               - qcom,sdm630-smmu-v2
+              - qcom,sdm670-smmu-v2
               - qcom,sdm845-smmu-v2
               - qcom,sm6350-smmu-v2
               - qcom,sm7150-smmu-v2
@@ -474,6 +478,7 @@ allOf:
           items:
             - enum:
                 - qcom,qcm2290-smmu-500
+                - qcom,qcs615-smmu-500
                 - qcom,sm6115-smmu-500
                 - qcom,sm6125-smmu-500
             - const: qcom,adreno-smmu
@@ -550,6 +555,23 @@ allOf:
             - description: GPU SNoC bus clock
             - description: GPU AHB clock
 
+  - if:
+      properties:
+        compatible:
+          items:
+            - const: qcom,sm8750-smmu-500
+            - const: qcom,adreno-smmu
+            - const: qcom,smmu-500
+            - const: arm,mmu-500
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: hlos
+        clocks:
+          items:
+            - description: HLOS vote clock
+
   # Disallow clocks for all other platforms with specific compatibles
   - if:
       properties:
@@ -559,7 +581,6 @@ allOf:
               - cavium,smmu-v2
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
-              - qcom,qcs615-smmu-500
               - qcom,qcs8300-smmu-500
               - qcom,qdu1000-smmu-500
               - qcom,sa8255p-smmu-500
diff --git a/dts/upstream/Bindings/iommu/qcom,iommu.yaml b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
index f8cebc9e8cd..5ae9a628261 100644
--- a/dts/upstream/Bindings/iommu/qcom,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
@@ -21,6 +21,7 @@ properties:
       - items:
           - enum:
               - qcom,msm8916-iommu
+              - qcom,msm8917-iommu
               - qcom,msm8953-iommu
           - const: qcom,msm-iommu-v1
       - items:
diff --git a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
index 621dde0e45d..6ce41d11ff5 100644
--- a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
@@ -25,6 +25,7 @@ properties:
           - rockchip,rk3568-iommu
       - items:
           - enum:
+              - rockchip,rk3576-iommu
               - rockchip,rk3588-iommu
           - const: rockchip,rk3568-iommu
 
diff --git a/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml b/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
index 34ef5215c15..f52f6304c79 100644
--- a/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
+++ b/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
@@ -23,6 +23,12 @@ properties:
     description: I2C slave address of the microcontroller.
     maxItems: 1
 
+  interrupts:
+    description:
+      Specifier for the global LED brightness changed by front button press
+      interrupt.
+    maxItems: 1
+
   "#address-cells":
     const: 1
 
@@ -56,6 +62,7 @@ additionalProperties: false
 examples:
   - |
 
+    #include <dt-bindings/interrupt-controller/irq.h>
     #include <dt-bindings/leds/common.h>
 
     i2c {
@@ -65,6 +72,7 @@ examples:
         led-controller@2b {
             compatible = "cznic,turris-omnia-leds";
             reg = <0x2b>;
+            interrupts-extended = <&mcu 11 IRQ_TYPE_NONE>;
             #address-cells = <1>;
             #size-cells = <0>;
 
diff --git a/dts/upstream/Bindings/leds/leds-class-multicolor.yaml b/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
index e850a889475..bb40bb9e036 100644
--- a/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
+++ b/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
@@ -27,7 +27,7 @@ properties:
     description: |
       For multicolor LED support this property should be defined as either
       LED_COLOR_ID_RGB or LED_COLOR_ID_MULTI which can be found in
-      include/linux/leds/common.h.
+      include/dt-bindings/leds/common.h.
     enum: [ 8, 9 ]
 
 required:
diff --git a/dts/upstream/Bindings/leds/leds-lp8860.txt b/dts/upstream/Bindings/leds/leds-lp8860.txt
deleted file mode 100644
index 8bb25749a3d..00000000000
--- a/dts/upstream/Bindings/leds/leds-lp8860.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Texas Instruments - lp8860 4-Channel LED Driver
-
-The LP8860-Q1 is an high-efficiency LED
-driver with boost controller. It has 4 high-precision
-current sinks that can be controlled by a PWM input
-signal, a SPI/I2C master, or both.
-
-Required properties:
-	- compatible :
-		"ti,lp8860"
-	- reg : I2C slave address
-	- #address-cells : 1
-	- #size-cells : 0
-
-Optional properties:
-	- enable-gpios : gpio pin to enable (active high)/disable the device.
-	- vled-supply : LED supply
-
-Required child properties:
-	- reg : 0
-
-Optional child properties:
-	- function : see Documentation/devicetree/bindings/leds/common.txt
-	- color : see Documentation/devicetree/bindings/leds/common.txt
-	- label : see Documentation/devicetree/bindings/leds/common.txt (deprecated)
-	- linux,default-trigger :
-	   see Documentation/devicetree/bindings/leds/common.txt
-
-Example:
-
-#include <dt-bindings/leds/common.h>
-
-led-controller@2d {
-	compatible = "ti,lp8860";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0x2d>;
-	enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-	vled-supply = <&vbatt>;
-
-	led@0 {
-		reg = <0>;
-		function = LED_FUNCTION_BACKLIGHT;
-		color = <LED_COLOR_ID_WHITE>;
-		linux,default-trigger = "backlight";
-	};
-}
-
-For more product information please see the link below:
-https://www.ti.com/product/lp8860-q1
diff --git a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
index 1ba607685f5..bcf0ad4ea57 100644
--- a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
+++ b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
@@ -23,6 +23,7 @@ properties:
     items:
       - enum:
           - qcom,pm6150l-flash-led
+          - qcom,pm660l-flash-led
           - qcom,pm8150c-flash-led
           - qcom,pm8150l-flash-led
           - qcom,pm8350c-flash-led
diff --git a/dts/upstream/Bindings/leds/st,led1202.yaml b/dts/upstream/Bindings/leds/st,led1202.yaml
new file mode 100644
index 00000000000..f1e5e4efaa3
--- /dev/null
+++ b/dts/upstream/Bindings/leds/st,led1202.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/st,led1202.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST LED1202 LED controllers
+
+maintainers:
+  - Vicentiu Galanopulo <vicentiu.galanopulo@remote-tech.co.uk>
+
+description: |
+  The LED1202 is a 12-channel low quiescent current LED controller
+  programmable via I2C; The output current can be adjusted separately
+  for each channel by 8-bit analog and 12-bit digital dimming control.
+  Datasheet available at
+  https://www.st.com/en/power-management/led1202.html
+
+properties:
+  compatible:
+    const: st,led1202
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^led@[0-9a-f]$":
+    type: object
+    $ref: common.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      reg:
+        minimum: 0
+        maximum: 11
+
+    required:
+      - reg
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/leds/common.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        led-controller@58 {
+            compatible = "st,led1202";
+            reg = <0x58>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            led@0 {
+                reg = <0x0>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <1>;
+            };
+
+            led@1 {
+                reg = <0x1>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <2>;
+            };
+
+            led@2 {
+                reg = <0x2>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <3>;
+            };
+
+            led@3 {
+                reg = <0x3>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <4>;
+            };
+
+            led@4 {
+                reg = <0x4>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <5>;
+            };
+
+            led@5 {
+                reg = <0x5>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <6>;
+            };
+
+            led@6 {
+                reg = <0x6>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <7>;
+            };
+
+            led@7 {
+                reg = <0x7>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <8>;
+            };
+
+            led@8 {
+                reg = <0x8>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <9>;
+            };
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/leds/ti,lp8860.yaml b/dts/upstream/Bindings/leds/ti,lp8860.yaml
new file mode 100644
index 00000000000..0ee357b0266
--- /dev/null
+++ b/dts/upstream/Bindings/leds/ti,lp8860.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/ti,lp8860.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments - lp8860 4-Channel LED Driver
+
+maintainers:
+  - Andrew Davis <afd@ti.com>
+
+description: |
+  The LP8860-Q1 is an high-efficiency LED driver with boost controller.
+  It has 4 high-precision current sinks that can be controlled by a PWM input
+  signal, a SPI/I2C master, or both.
+
+  For more product information please see the link below:
+    https://www.ti.com/product/lp8860-q1
+
+properties:
+  compatible:
+    const: ti,lp8860
+
+  reg:
+    maxItems: 1
+    description: I2C slave address
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  enable-gpios:
+    maxItems: 1
+    description: GPIO pin to enable (active high) / disable the device
+
+  vled-supply:
+    description: LED supply
+
+patternProperties:
+  "^led(@[0-3])?$":
+    type: object
+    $ref: common.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      reg:
+        description:
+          Index of the LED.
+        maxItems: 1
+
+      function: true
+      color: true
+      label: true
+      linux,default-trigger: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/leds/common.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        led-controller@2d {
+            compatible = "ti,lp8860";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0x2d>;
+            enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+            vled-supply = <&vbatt>;
+
+            led@0 {
+                reg = <0>;
+                function = LED_FUNCTION_BACKLIGHT;
+                color = <LED_COLOR_ID_WHITE>;
+                linux,default-trigger = "backlight";
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml b/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml
new file mode 100644
index 00000000000..e249db4c1fb
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2024 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Mailbox Controller
+
+maintainers:
+  - Tudor Ambarus <tudor.ambarus@linaro.org>
+
+description:
+  The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
+  bits for hardware interrupt generation and a shared register for passing
+  mailbox messages. When the controller is used by the ACPM interface
+  the shared register is ignored and the mailbox controller acts as a doorbell.
+  The controller just raises the interrupt to the firmware after the
+  ACPM interface has written the message to SRAM.
+
+properties:
+  compatible:
+    const: google,gs101-mbox
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pclk
+
+  interrupts:
+    description: IRQ line for the RX mailbox.
+    maxItems: 1
+
+  '#mbox-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - '#mbox-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/google,gs101.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ap2apm_mailbox: mailbox@17610000 {
+            compatible = "google,gs101-mbox";
+            reg = <0x17610000 0x1000>;
+            clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
+            clock-names = "pclk";
+            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
+            #mbox-cells = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml b/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml
new file mode 100644
index 00000000000..8ed67ea7c88
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Inter-processor communication (IPC) mailbox controller
+
+maintainers:
+  - Valentina Fernandez <valentina.fernandezalanis@microchip.com>
+
+description:
+  The Microchip Inter-processor Communication (IPC) facilitates
+  message passing between processors using an interrupt signaling
+  mechanism.
+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          Intended for use by software running in supervisor privileged
+          mode (s-mode). This SBI interface is compatible with the Mi-V
+          Inter-hart Communication (IHC) IP.
+        const: microchip,sbi-ipc
+
+      - description:
+          Intended for use by the SBI implementation in machine mode
+          (m-mode), this compatible string is for the MIV_IHC Soft-IP.
+        const: microchip,miv-ihc-rtl-v2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 5
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 5
+    items:
+      enum:
+        - hart-0
+        - hart-1
+        - hart-2
+        - hart-3
+        - hart-4
+        - hart-5
+
+  "#mbox-cells":
+    description: >
+      For "microchip,sbi-ipc", the cell represents the global "logical"
+      channel IDs. The meaning of channel IDs are platform firmware dependent.
+
+      For "microchip,miv-ihc-rtl-v2", the cell represents the physical
+      channel and does not vary based on the platform firmware.
+    const: 1
+
+  microchip,ihc-chan-disabled-mask:
+    description: >
+      Represents the enable/disable state of the bi-directional IHC
+      channels within the MIV-IHC IP configuration.
+
+      A bit set to '1' indicates that the corresponding channel is disabled,
+      and any read or write operations to that channel will return zero.
+
+      A bit set to '0' indicates that the corresponding channel is enabled
+      and will be accessible through its dedicated address range registers.
+
+      The actual enable/disable state of each channel is determined by the
+      IP block’s configuration.
+    $ref: /schemas/types.yaml#/definitions/uint16
+    maximum: 0x7fff
+    default: 0
+
+required:
+  - compatible
+  - interrupts
+  - interrupt-names
+  - "#mbox-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sbi-ipc
+    then:
+      properties:
+        reg:
+          not: {}
+          description:
+            The 'microchip,sbi-ipc' operates in a programming model
+            that does not require memory-mapped I/O (MMIO) registers
+            since it uses SBI ecalls provided by the m-mode/firmware
+            SBI implementation to access hardware registers.
+        microchip,ihc-chan-disabled-mask: false
+    else:
+      required:
+        - reg
+        - microchip,ihc-chan-disabled-mask
+
+additionalProperties: false
+
+examples:
+  - |
+    mailbox {
+      compatible = "microchip,sbi-ipc";
+      interrupt-parent = <&plic>;
+      interrupts = <180>, <179>, <178>;
+      interrupt-names = "hart-1", "hart-2", "hart-3";
+      #mbox-cells = <1>;
+    };
+  - |
+    mailbox@50000000 {
+      compatible = "microchip,miv-ihc-rtl-v2";
+      microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+      reg = <0x50000000 0x1c000>;
+      interrupt-parent = <&plic>;
+      interrupts = <180>, <179>, <178>;
+      interrupt-names = "hart-1", "hart-2", "hart-3";
+      #mbox-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
index 9d2dfd85b20..78f68dacd02 100644
--- a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -20,6 +20,7 @@ properties:
           - enum:
               - qcom,ipq5018-apcs-apps-global
               - qcom,ipq5332-apcs-apps-global
+              - qcom,ipq5424-apcs-apps-global
               - qcom,ipq8074-apcs-apps-global
               - qcom,ipq9574-apcs-apps-global
           - const: qcom,ipq6018-apcs-apps-global
@@ -44,6 +45,7 @@ properties:
           - const: qcom,msm8994-apcs-kpss-global
       - items:
           - enum:
+              - qcom,qcs615-apss-shared
               - qcom,sc7180-apss-shared
               - qcom,sc8180x-apss-shared
               - qcom,sm8150-apss-shared
diff --git a/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
index a4f06bbdfe4..8ba5177ac63 100644
--- a/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
+++ b/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
diff --git a/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml b/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
index 377acce9342..6da8a6aded2 100644
--- a/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
+++ b/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#
diff --git a/dts/upstream/Bindings/media/amphion,vpu.yaml b/dts/upstream/Bindings/media/amphion,vpu.yaml
index 9801de3ed84..5a920d9e78c 100644
--- a/dts/upstream/Bindings/media/amphion,vpu.yaml
+++ b/dts/upstream/Bindings/media/amphion,vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
diff --git a/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml b/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
index 84a5e894ace..3f47744459a 100644
--- a/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
+++ b/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#
diff --git a/dts/upstream/Bindings/media/i2c/sony,imx290.yaml b/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
index bf05ca48601..fa69bd21c8d 100644
--- a/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
+++ b/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
@@ -33,6 +33,8 @@ properties:
           - sony,imx290lqr # Colour
           - sony,imx290llr # Monochrome
           - sony,imx327lqr # Colour
+          - sony,imx462lqr # Colour
+          - sony,imx462llr # Monochrome
       - const: sony,imx290
         deprecated: true
 
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
index b401c67e3ba..d726d141a43 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
index b45743d0a9e..110e8f5f1f9 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
index a500a585c69..5865e6f0be8 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
diff --git a/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml b/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
index 59b805ca47c..ede086d55ad 100644
--- a/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
+++ b/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#
@@ -36,12 +35,12 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/at91.h>
-        #include <dt-bindings/interrupt-controller/irq.h>
-
-        vdec0: vdec@300000 {
-                compatible = "microchip,sama5d4-vdec";
-                reg = <0x00300000 0x100000>;
-                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
-                clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
-        };
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    vdec@300000 {
+        compatible = "microchip,sama5d4-vdec";
+        reg = <0x00300000 0x100000>;
+        interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+        clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+    };
diff --git a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
index 4d5348d456a..f43b91984f0 100644
--- a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
+++ b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
@@ -21,6 +21,7 @@ properties:
     enum:
       - fsl,imx8mn-isi
       - fsl,imx8mp-isi
+      - fsl,imx8ulp-isi
       - fsl,imx93-isi
 
   reg:
@@ -75,6 +76,7 @@ allOf:
           contains:
             enum:
               - fsl,imx8mn-isi
+              - fsl,imx8ulp-isi
               - fsl,imx93-isi
     then:
       properties:
diff --git a/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml b/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
index 3d58f02b0c5..19528262810 100644
--- a/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
+++ b/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
@@ -44,26 +43,26 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/imx8mq-clock.h>
-        #include <dt-bindings/power/imx8mq-power.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/power/imx8mq-power.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-        vpu_g1: video-codec@38300000 {
-                compatible = "nxp,imx8mq-vpu-g1";
-                reg = <0x38300000 0x10000>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
-                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
-        };
+    video-codec@38300000 {
+        compatible = "nxp,imx8mq-vpu-g1";
+        reg = <0x38300000 0x10000>;
+        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
+        power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+    };
   - |
-        #include <dt-bindings/clock/imx8mq-clock.h>
-        #include <dt-bindings/power/imx8mq-power.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/power/imx8mq-power.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-        vpu_g2: video-codec@38300000 {
-                compatible = "nxp,imx8mq-vpu-g2";
-                reg = <0x38310000 0x10000>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
-                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
-        };
+    video-codec@38300000 {
+        compatible = "nxp,imx8mq-vpu-g2";
+        reg = <0x38310000 0x10000>;
+        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+        power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
+    };
diff --git a/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml b/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
index 9cc0a968a40..3469a43f00d 100644
--- a/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml b/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
index 9410f13ca97..da140c2e3d3 100644
--- a/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
@@ -45,6 +45,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -57,13 +58,12 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -83,12 +83,4 @@ examples:
         power-domains = <&gcc VENUS_GDSC>;
         iommus = <&apps_iommu 5>;
         memory-region = <&venus_mem>;
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml b/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
index 5cb0e337ea6..644646de338 100644
--- a/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml b/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
index 5cec1d077cd..83c4a5d95f0 100644
--- a/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
@@ -70,6 +70,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -82,14 +83,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -114,12 +114,4 @@ examples:
                       "vcodec0_core", "vcodec0_bus";
         iommus = <&apps_smmu 0x0c00 0x60>;
         memory-region = <&venus_mem>;
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml b/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml
new file mode 100644
index 00000000000..e11141b812a
--- /dev/null
+++ b/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml
@@ -0,0 +1,425 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 CAMSS ISP
+
+maintainers:
+  - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
+  - Hariram Purushothaman <hariramp@quicinc.com>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,sc7280-camss
+
+  reg:
+    maxItems: 15
+
+  reg-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid2
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: csiphy3
+      - const: csiphy4
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  clocks:
+    maxItems: 33
+
+  clock-names:
+    items:
+      - const: camnoc_axi
+      - const: cpas_ahb
+      - const: csiphy0
+      - const: csiphy0_timer
+      - const: csiphy1
+      - const: csiphy1_timer
+      - const: csiphy2
+      - const: csiphy2_timer
+      - const: csiphy3
+      - const: csiphy3_timer
+      - const: csiphy4
+      - const: csiphy4_timer
+      - const: gcc_camera_ahb
+      - const: gcc_cam_hf_axi
+      - const: icp_ahb
+      - const: vfe0
+      - const: vfe0_axi
+      - const: vfe0_cphy_rx
+      - const: vfe0_csid
+      - const: vfe1
+      - const: vfe1_axi
+      - const: vfe1_cphy_rx
+      - const: vfe1_csid
+      - const: vfe2
+      - const: vfe2_axi
+      - const: vfe2_cphy_rx
+      - const: vfe2_csid
+      - const: vfe_lite0
+      - const: vfe_lite0_cphy_rx
+      - const: vfe_lite0_csid
+      - const: vfe_lite1
+      - const: vfe_lite1_cphy_rx
+      - const: vfe_lite1_csid
+
+  interrupts:
+    maxItems: 15
+
+  interrupt-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid2
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: csiphy3
+      - const: csiphy4
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ahb
+      - const: hf_0
+
+  iommus:
+    maxItems: 1
+
+  power-domains:
+    items:
+      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+  power-domain-names:
+    items:
+      - const: ife0
+      - const: ife1
+      - const: ife2
+      - const: top
+
+  vdda-phy-supply:
+    description:
+      Phandle to a regulator supply to PHY core block.
+
+  vdda-pll-supply:
+    description:
+      Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    description:
+      CSI input ports.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 0.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 1.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@2:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 2.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@3:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 3.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@4:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 4.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interrupts
+  - interrupt-names
+  - interconnects
+  - interconnect-names
+  - iommus
+  - power-domains
+  - power-domain-names
+  - vdda-phy-supply
+  - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,camcc-sc7280.h>
+    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+    #include <dt-bindings/interconnect/qcom,sc7280.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        isp@acb3000 {
+            compatible = "qcom,sc7280-camss";
+
+            reg = <0x0 0x0acb3000 0x0 0x1000>,
+                  <0x0 0x0acba000 0x0 0x1000>,
+                  <0x0 0x0acc1000 0x0 0x1000>,
+                  <0x0 0x0acc8000 0x0 0x1000>,
+                  <0x0 0x0accf000 0x0 0x1000>,
+                  <0x0 0x0ace0000 0x0 0x2000>,
+                  <0x0 0x0ace2000 0x0 0x2000>,
+                  <0x0 0x0ace4000 0x0 0x2000>,
+                  <0x0 0x0ace6000 0x0 0x2000>,
+                  <0x0 0x0ace8000 0x0 0x2000>,
+                  <0x0 0x0acaf000 0x0 0x4000>,
+                  <0x0 0x0acb6000 0x0 0x4000>,
+                  <0x0 0x0acbd000 0x0 0x4000>,
+                  <0x0 0x0acc4000 0x0 0x4000>,
+                  <0x0 0x0accb000 0x0 0x4000>;
+            reg-names = "csid0",
+                        "csid1",
+                        "csid2",
+                        "csid_lite0",
+                        "csid_lite1",
+                        "csiphy0",
+                        "csiphy1",
+                        "csiphy2",
+                        "csiphy3",
+                        "csiphy4",
+                        "vfe0",
+                        "vfe1",
+                        "vfe2",
+                        "vfe_lite0",
+                        "vfe_lite1";
+
+            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                     <&camcc CAM_CC_CPAS_AHB_CLK>,
+                     <&camcc CAM_CC_CSIPHY0_CLK>,
+                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY1_CLK>,
+                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY2_CLK>,
+                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY3_CLK>,
+                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY4_CLK>,
+                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+                     <&gcc GCC_CAMERA_AHB_CLK>,
+                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                     <&camcc CAM_CC_ICP_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_0_CLK>,
+                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_1_CLK>,
+                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_2_CLK>,
+                     <&camcc CAM_CC_IFE_2_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_2_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
+            clock-names = "camnoc_axi",
+                          "cpas_ahb",
+                          "csiphy0",
+                          "csiphy0_timer",
+                          "csiphy1",
+                          "csiphy1_timer",
+                          "csiphy2",
+                          "csiphy2_timer",
+                          "csiphy3",
+                          "csiphy3_timer",
+                          "csiphy4",
+                          "csiphy4_timer",
+                          "gcc_camera_ahb",
+                          "gcc_cam_hf_axi",
+                          "icp_ahb",
+                          "vfe0",
+                          "vfe0_axi",
+                          "vfe0_cphy_rx",
+                          "vfe0_csid",
+                          "vfe1",
+                          "vfe1_axi",
+                          "vfe1_cphy_rx",
+                          "vfe1_csid",
+                          "vfe2",
+                          "vfe2_axi",
+                          "vfe2_cphy_rx",
+                          "vfe2_csid",
+                          "vfe_lite0",
+                          "vfe_lite0_cphy_rx",
+                          "vfe_lite0_csid",
+                          "vfe_lite1",
+                          "vfe_lite1_cphy_rx",
+                          "vfe_lite1_csid";
+
+            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "csid0",
+                              "csid1",
+                              "csid2",
+                              "csid_lite0",
+                              "csid_lite1",
+                              "csiphy0",
+                              "csiphy1",
+                              "csiphy2",
+                              "csiphy3",
+                              "csiphy4",
+                              "vfe0",
+                              "vfe1",
+                              "vfe2",
+                              "vfe_lite0",
+                              "vfe_lite1";
+
+            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+            interconnect-names = "ahb",
+                                 "hf_0";
+
+            iommus = <&apps_smmu 0x800 0x4e0>;
+
+            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+                            <&camcc CAM_CC_IFE_1_GDSC>,
+                            <&camcc CAM_CC_IFE_2_GDSC>,
+                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
+            power-domain-names = "ife0",
+                                 "ife1",
+                                 "ife2",
+                                 "top";
+
+            vdda-phy-supply = <&vreg_l10c_0p88>;
+            vdda-pll-supply = <&vreg_l6b_1p2>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml b/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
index 10c334e6b3d..413c5b4ee65 100644
--- a/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
@@ -68,6 +68,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -80,14 +81,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -125,14 +125,6 @@ examples:
 
         memory-region = <&video_mem>;
 
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
-
         video-firmware {
             iommus = <&apps_smmu 0x21a2 0x0>;
         };
diff --git a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
index c0bc3170987..9936f013241 100644
--- a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
@@ -328,26 +328,26 @@ examples:
             vdda-phy-supply = <&vreg_l6d>;
             vdda-pll-supply = <&vreg_l4d>;
 
-            interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+            interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
 
             interrupt-names = "csid1_lite",
                               "vfe_lite1",
diff --git a/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml b/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
index 584106e275f..68d8670557f 100644
--- a/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml b/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
index ec4380a0a03..289494f561e 100644
--- a/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
@@ -296,16 +295,16 @@ examples:
           "vfe_lite_cphy_rx",
           "vfe_lite_src";
 
-        interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
 
         interrupt-names = "csid0",
           "csid1",
diff --git a/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml b/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
index 6228fd2b324..c839cb1ebc0 100644
--- a/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
@@ -70,6 +70,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-core1:
@@ -82,14 +83,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-core0
-  - video-core1
 
 unevaluatedProperties: false
 
@@ -119,12 +119,4 @@ examples:
         iommus = <&apps_smmu 0x10a0 0x8>,
                  <&apps_smmu 0x10b0 0x0>;
         memory-region = <&venus_mem>;
-
-        video-core0 {
-            compatible = "venus-decoder";
-        };
-
-        video-core1 {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml b/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
index fa5073c0fd1..a372d991e65 100644
--- a/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
@@ -329,20 +328,20 @@ examples:
             vdda-phy-supply = <&vreg_l5a_0p88>;
             vdda-pll-supply = <&vreg_l9a_1p2>;
 
-            interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+            interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
             interrupt-names = "csiphy0",
                               "csiphy1",
                               "csiphy2",
diff --git a/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml b/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
index f66033ae8b5..da54493220c 100644
--- a/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
@@ -73,6 +73,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -85,6 +86,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
@@ -95,8 +97,6 @@ required:
   - iommus
   - resets
   - reset-names
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -132,12 +132,4 @@ examples:
         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
         reset-names = "bus", "core";
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml b/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
index 947ad699cc5..d246f5d3842 100644
--- a/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
+++ b/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#
diff --git a/dts/upstream/Bindings/media/rockchip-vpu.yaml b/dts/upstream/Bindings/media/rockchip-vpu.yaml
index 719aeb2dc59..8c250163408 100644
--- a/dts/upstream/Bindings/media/rockchip-vpu.yaml
+++ b/dts/upstream/Bindings/media/rockchip-vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
@@ -92,18 +91,18 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/rk3288-cru.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
-        #include <dt-bindings/power/rk3288-power.h>
-
-        vpu: video-codec@ff9a0000 {
-                compatible = "rockchip,rk3288-vpu";
-                reg = <0xff9a0000 0x800>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "vepu", "vdpu";
-                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
-                clock-names = "aclk", "hclk";
-                power-domains = <&power RK3288_PD_VIDEO>;
-                iommus = <&vpu_mmu>;
-        };
+    #include <dt-bindings/clock/rk3288-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/rk3288-power.h>
+
+    video-codec@ff9a0000 {
+        compatible = "rockchip,rk3288-vpu";
+        reg = <0xff9a0000 0x800>;
+        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "vepu", "vdpu";
+        clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+        clock-names = "aclk", "hclk";
+        power-domains = <&power RK3288_PD_VIDEO>;
+        iommus = <&vpu_mmu>;
+    };
diff --git a/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
index 87731f3ce7b..7b03a77adbc 100644
--- a/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
+++ b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
@@ -12,7 +12,9 @@ maintainers:
 
 properties:
   compatible:
-    const: st,stm32mp13-dcmipp
+    enum:
+      - st,stm32mp13-dcmipp
+      - st,stm32mp25-dcmipp
 
   reg:
     maxItems: 1
@@ -21,11 +23,24 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    items:
+      - description: bus clock
+      - description: csi clock
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: kclk
+      - const: mclk
+    minItems: 1
 
   resets:
     maxItems: 1
 
+  access-controllers:
+    minItems: 1
+    maxItems: 2
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
@@ -39,7 +54,7 @@ properties:
 
         properties:
           bus-type:
-            enum: [5, 6]
+            enum: [4, 5, 6]
             default: 5
 
           bus-width:
@@ -50,9 +65,6 @@ properties:
           hsync-active: true
           vsync-active: true
 
-        required:
-          - pclk-sample
-
 required:
   - compatible
   - reg
@@ -61,6 +73,35 @@ required:
   - resets
   - port
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - st,stm32mp13-dcmipp
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          maxItems: 1
+
+        port:
+          properties:
+            endpoint:
+              properties:
+                bus-type:
+                  enum: [5, 6]
+    else:
+      properties:
+        clocks:
+          minItems: 2
+
+        clock-names:
+          minItems: 2
+
 additionalProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml b/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml
new file mode 100644
index 00000000000..33bedfe4192
--- /dev/null
+++ b/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32mp25-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 CSI controller
+
+description:
+  The STM32 CSI controller allows connecting a CSI based
+  camera to the DCMIPP camera pipeline.
+
+maintainers:
+  - Alain Volmat <alain.volmat@foss.st.com>
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp25-csi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: txesc
+      - const: csi2phy
+
+  resets:
+    maxItems: 1
+
+  vdd-supply:
+    description: Digital core power supply (0.91V)
+
+  vdda18-supply:
+    description: System analog power supply (1.8V)
+
+  access-controllers:
+    minItems: 1
+    maxItems: 2
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port node
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                items:
+                  - const: 1
+                  - const: 2
+
+            required:
+              - data-lanes
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port node
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/media/video-interfaces.h>
+    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+    csi@48020000 {
+        compatible = "st,stm32mp25-csi";
+        reg = <0x48020000 0x2000>;
+        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+        resets = <&rcc CSI_R>;
+        clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>;
+        clock-names = "pclk", "txesc", "csi2phy";
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&imx335_ep>;
+                    data-lanes = <1 2>;
+                    bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&dcmipp_0>;
+                };
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/media/video-interfaces.yaml b/dts/upstream/Bindings/media/video-interfaces.yaml
index 26e3e7d7c67..038e85b45be 100644
--- a/dts/upstream/Bindings/media/video-interfaces.yaml
+++ b/dts/upstream/Bindings/media/video-interfaces.yaml
@@ -210,6 +210,27 @@ properties:
       lane-polarities property is omitted, the value must be interpreted as 0
       (normal). This property is valid for serial busses only.
 
+  line-orders:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 8
+    items:
+      enum:
+        - 0 # ABC
+        - 1 # ACB
+        - 2 # BAC
+        - 3 # BCA
+        - 4 # CAB
+        - 5 # CBA
+    description:
+      An array of line orders of the CSI-2 C-PHY data lanes. The order of the
+      lanes are the same as in data-lanes property. Valid values are 0-5 as
+      defined in the MIPI Discovery and Configuration (DisCo) Specification for
+      Imaging. The length of the array must be the same length as the
+      data-lanes property. If the line-orders property is omitted, the value
+      shall be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY
+      busses only.
+
   strobe:
     $ref: /schemas/types.yaml#/definitions/uint32
     enum: [ 0, 1 ]
diff --git a/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml b/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
index 0c511ab906b..8b937f90a1f 100644
--- a/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
+++ b/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
@@ -52,10 +52,3 @@ examples:
 
         #qca,ddr-wb-channel-cells = <1>;
     };
-
-    interrupt-controller {
-        // ...
-        qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
-        qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
-                              <&ddr_ctrl 0>, <&ddr_ctrl 1>;
-    };
diff --git a/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml b/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml
new file mode 100644
index 00000000000..f805545aa62
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,at91sam9260-gpbr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 General Purpose Backup Registers
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+description:
+  The system controller embeds 256 bits of General Purpose Backup
+  registers organized as 8 32-bit registers.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - atmel,at91sam9260-gpbr
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sam9x60-gpbr
+              - microchip,sam9x7-gpbr
+          - const: atmel,at91sam9260-gpbr
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@fffffd50 {
+        compatible = "atmel,at91sam9260-gpbr", "syscon";
+        reg = <0xfffffd50 0x10>;
+    };
diff --git a/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml b/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml
new file mode 100644
index 00000000000..447b3a3edbf
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,at91sam9260-matrix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Bus Matrix
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+description:
+  The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the
+  AHB-Lite protocol, that enables parallel access paths between multiple
+  masters and slaves in a system, thus increasing the overall bandwidth.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - atmel,at91sam9260-matrix
+              - atmel,at91sam9261-matrix
+              - atmel,at91sam9263-matrix
+              - atmel,at91sam9rl-matrix
+              - atmel,at91sam9g45-matrix
+              - atmel,at91sam9n12-matrix
+              - atmel,at91sam9x5-matrix
+              - atmel,sama5d3-matrix
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sam9x60-matrix
+              - microchip,sam9x7-matrix
+          - const: atmel,at91sam9x5-matrix
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@ffffec00 {
+        compatible = "atmel,sama5d3-matrix", "syscon";
+        reg = <0xffffec00 0x200>;
+    };
diff --git a/dts/upstream/Bindings/mfd/atmel-gpbr.txt b/dts/upstream/Bindings/mfd/atmel-gpbr.txt
deleted file mode 100644
index 3c989d1760a..00000000000
--- a/dts/upstream/Bindings/mfd/atmel-gpbr.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)
-
-The GPBR are a set of battery-backed registers.
-
-Required properties:
-- compatible:		Should be one of the following:
-			"atmel,at91sam9260-gpbr", "syscon"
-			"microchip,sam9x60-gpbr", "syscon"
-			"microchip,sam9x7-gpbr", "microchip,sam9x60-gpbr", "syscon"
-- reg:			contains offset/length value of the GPBR memory
-			region.
-
-Example:
-
-gpbr: gpbr@fffffd50 {
-	compatible = "atmel,at91sam9260-gpbr", "syscon";
-	reg = <0xfffffd50 0x10>;
-};
diff --git a/dts/upstream/Bindings/mfd/atmel-matrix.txt b/dts/upstream/Bindings/mfd/atmel-matrix.txt
deleted file mode 100644
index 6e5f83614e8..00000000000
--- a/dts/upstream/Bindings/mfd/atmel-matrix.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Device tree bindings for Atmel Bus Matrix
-
-The Bus Matrix registers are used to configure Atmel SoCs internal bus
-behavior (master/slave priorities, undefined burst length type, ...)
-
-Required properties:
-- compatible:		Should be one of the following
-			"atmel,at91sam9260-matrix", "syscon"
-			"atmel,at91sam9261-matrix", "syscon"
-			"atmel,at91sam9263-matrix", "syscon"
-			"atmel,at91sam9rl-matrix", "syscon"
-			"atmel,at91sam9g45-matrix", "syscon"
-			"atmel,at91sam9n12-matrix", "syscon"
-			"atmel,at91sam9x5-matrix", "syscon"
-			"atmel,sama5d3-matrix", "syscon"
-			"microchip,sam9x60-matrix", "syscon"
-			"microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"
-- reg:			Contains offset/length value of the Bus Matrix
-			memory region.
-
-Example:
-
-matrix: matrix@ffffec00 {
-	compatible = "atmel,sama5d3-matrix", "syscon";
-	reg = <0xffffec00 0x200>;
-};
diff --git a/dts/upstream/Bindings/mfd/google,cros-ec.yaml b/dts/upstream/Bindings/mfd/google,cros-ec.yaml
index aac8819bd00..50f45709006 100644
--- a/dts/upstream/Bindings/mfd/google,cros-ec.yaml
+++ b/dts/upstream/Bindings/mfd/google,cros-ec.yaml
@@ -108,9 +108,6 @@ properties:
   pwm:
     $ref: /schemas/pwm/google,cros-ec-pwm.yaml#
 
-  kbd-led-backlight:
-    $ref: /schemas/chrome/google,cros-kbd-led-backlight.yaml#
-
   keyboard-controller:
     $ref: /schemas/input/google,cros-ec-keyb.yaml#
 
diff --git a/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml b/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
index 86451f151a6..6a89b479d10 100644
--- a/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
+++ b/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
@@ -36,6 +36,7 @@ properties:
       - enum:
           - mediatek,mt6323
           - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332.
+          - mediatek,mt6328
           - mediatek,mt6358
           - mediatek,mt6359
           - mediatek,mt6397
@@ -88,6 +89,7 @@ properties:
         oneOf:
           - enum:
               - mediatek,mt6323-regulator
+              - mediatek,mt6328-regulator
               - mediatek,mt6358-regulator
               - mediatek,mt6359-regulator
               - mediatek,mt6397-regulator
diff --git a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
index 79add913e35..a503b67f2db 100644
--- a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
@@ -42,6 +42,7 @@ properties:
           - qcom,tcsr-apq8064
           - qcom,tcsr-apq8084
           - qcom,tcsr-ipq5332
+          - qcom,tcsr-ipq5424
           - qcom,tcsr-ipq6018
           - qcom,tcsr-ipq8064
           - qcom,tcsr-ipq8074
diff --git a/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml b/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml
new file mode 100644
index 00000000000..877078ac172
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qnap,ts433-mcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QNAP NAS on-board Microcontroller
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  QNAP embeds a microcontroller on their NAS devices adding system feature
+  as PWM Fan control, additional LEDs, power button status and more.
+
+properties:
+  compatible:
+    enum:
+      - qnap,ts433-mcu
+
+patternProperties:
+  "^fan-[0-9]+$":
+    $ref: /schemas/hwmon/fan-common.yaml#
+    unevaluatedProperties: false
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    uart {
+      mcu {
+        compatible = "qnap,ts433-mcu";
+
+        fan-0 {
+          #cooling-cells = <2>;
+          cooling-levels = <0 64 89 128 166 204 221 238>;
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml b/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
index bb81307dc11..4fc78efaa55 100644
--- a/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
+++ b/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
@@ -50,15 +50,15 @@ properties:
     minimum: 0
     maximum: 1
 
-  rohm,charger-sense-resistor-ohms:
-    minimum: 10000000
-    maximum: 50000000
+  rohm,charger-sense-resistor-micro-ohms:
+    minimum: 10000
+    maximum: 50000
     description: |
-      BD71827 and BD71828 have SAR ADC for measuring charging currents.
-      External sense resistor (RSENSE in data sheet) should be used. If
-      something other but 30MOhm resistor is used the resistance value
-      should be given here in Ohms.
-    default: 30000000
+      BD71815 has SAR ADC for measuring charging currents. External sense
+      resistor (RSENSE in data sheet) should be used. If something other
+      but a 30 mOhm resistor is used the resistance value should be given
+      here in micro Ohms.
+    default: 30000
 
   regulators:
     $ref: /schemas/regulator/rohm,bd71815-regulator.yaml
@@ -67,7 +67,7 @@ properties:
 
   gpio-reserved-ranges:
     description: |
-      Usage of BD71828 GPIO pins can be changed via OTP. This property can be
+      Usage of BD71815 GPIO pins can be changed via OTP. This property can be
       used to mark the pins which should not be configured for GPIO. Please see
       the ../gpio/gpio.txt for more information.
 
@@ -113,7 +113,7 @@ examples:
             gpio-controller;
             #gpio-cells = <2>;
 
-            rohm,charger-sense-resistor-ohms = <10000000>;
+            rohm,charger-sense-resistor-micro-ohms = <10000>;
 
             regulators {
                 buck1: buck1 {
diff --git a/dts/upstream/Bindings/mfd/sprd,sc2731.yaml b/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
index 8beec7e8e4c..b023e1ef8d3 100644
--- a/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
+++ b/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
@@ -67,15 +67,7 @@ patternProperties:
 
   "^efuse@[0-9a-f]+$":
     type: object
-    additionalProperties: true
-    properties:
-      compatible:
-        enum:
-          - sprd,sc2720-efuse
-          - sprd,sc2721-efuse
-          - sprd,sc2723-efuse
-          - sprd,sc2730-efuse
-          - sprd,sc2731-efuse
+    $ref: /schemas/nvmem/sprd,sc2731-efuse.yaml#
 
   "^fuel-gauge@[0-9a-f]+$":
     type: object
@@ -199,7 +191,7 @@ examples:
           };
         };
 
-        adc@480 {
+        pmic_adc: adc@480 {
           compatible = "sprd,sc2731-adc";
           reg = <0x480>;
           interrupt-parent = <&sc2731_pmic>;
diff --git a/dts/upstream/Bindings/mfd/syscon.yaml b/dts/upstream/Bindings/mfd/syscon.yaml
index b414de4fa77..4d67ff26d44 100644
--- a/dts/upstream/Bindings/mfd/syscon.yaml
+++ b/dts/upstream/Bindings/mfd/syscon.yaml
@@ -27,7 +27,7 @@ select:
     compatible:
       contains:
         enum:
-          - al,alpine-sysfabric-servic
+          - al,alpine-sysfabric-service
           - allwinner,sun8i-a83t-system-controller
           - allwinner,sun8i-h3-system-controller
           - allwinner,sun8i-v3s-system-controller
@@ -103,6 +103,7 @@ select:
           - rockchip,rk3288-qos
           - rockchip,rk3368-qos
           - rockchip,rk3399-qos
+          - rockchip,rk3562-qos
           - rockchip,rk3568-qos
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
@@ -201,6 +202,7 @@ properties:
           - rockchip,rk3288-qos
           - rockchip,rk3368-qos
           - rockchip,rk3399-qos
+          - rockchip,rk3562-qos
           - rockchip,rk3568-qos
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
@@ -213,6 +215,7 @@ properties:
           - ti,am625-dss-oldi-io-ctrl
           - ti,am62p-cpsw-mac-efuse
           - ti,am654-dss-oldi-io-ctrl
+          - ti,j784s4-acspcie-proxy-ctrl
           - ti,j784s4-pcie-ctrl
           - ti,keystone-pllctrl
       - const: syscon
diff --git a/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml b/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml
new file mode 100644
index 00000000000..73fbf672e22
--- /dev/null
+++ b/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/lwn,bk4-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Liebherr's BK4 external SPI controller
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+description: |
+  Liebherr's BK4 external SPI controller is a device which handles data
+  acquisition from compatible industrial peripherals.
+  The SPI is used for data and management purposes in both master and
+  slave modes.
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: lwn,bk4-spi
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 30000000
+
+  fsl,spi-cs-sck-delay: true
+
+  fsl,spi-sck-cs-delay: true
+
+required:
+  - compatible
+  - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        spidev@0 {
+            compatible = "lwn,bk4-spi";
+            reg = <0>;
+            spi-max-frequency = <30000000>;
+            fsl,spi-cs-sck-delay = <200>;
+            fsl,spi-sck-cs-delay = <400>;
+        };
+    };
diff --git a/dts/upstream/Bindings/misc/lwn-bk4.txt b/dts/upstream/Bindings/misc/lwn-bk4.txt
deleted file mode 100644
index d6a8c188c08..00000000000
--- a/dts/upstream/Bindings/misc/lwn-bk4.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Liebherr's BK4 controller external SPI
-
-A device which handles data acquisition from compatible industrial
-peripherals.
-The SPI is used for data and management purposes in both master and
-slave modes.
-
-Required properties:
-
-- compatible : Should be "lwn,bk4"
-
-Required SPI properties:
-
-- reg : Should be address of the device chip select within
-  the controller.
-
-- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
-  30MHz at most for the Liebherr's BK4 external bus.
-
-Example:
-
-spidev0: spi@0 {
-	compatible = "lwn,bk4";
-	spi-max-frequency = <30000000>;
-	reg = <0>;
-};
diff --git a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt
deleted file mode 100644
index 8765c605e6b..00000000000
--- a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
-
-The highspeed MMC host controller on Amlogic SoCs provides an interface
-for MMC, SD, SDIO and SDHC types of memory cards.
-
-Supported maximum speeds are the ones of the eMMC standard 4.41 as well
-as the speed of SD standard 2.0.
-
-The hardware provides an internal "mux" which allows up to three slots
-to be controlled. Only one slot can be accessed at a time.
-
-Required properties:
- - compatible : must be one of
-	- "amlogic,meson8-sdio"
-	- "amlogic,meson8b-sdio"
-	along with the generic "amlogic,meson-mx-sdio"
- - reg : mmc controller base registers
- - interrupts : mmc controller interrupt
- - #address-cells : must be 1
- - size-cells : must be 0
- - clocks : phandle to clock providers
- - clock-names : must contain "core" and "clkin"
-
-Required child nodes:
-A node for each slot provided by the MMC controller is required.
-NOTE: due to a driver limitation currently only one slot (= child node)
-      is supported!
-
-Required properties on each child node (= slot):
- - compatible : must be "mmc-slot" (see mmc.txt within this directory)
- - reg : the slot (or "port") ID
-
-Optional properties on each child node (= slot):
- - bus-width : must be 1 or 4 (8-bit bus is not supported)
- - for cd and all other additional generic mmc parameters
-   please refer to mmc.txt within this directory
-
-Examples:
-	mmc@c1108c20 {
-		compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
-		reg = <0xc1108c20 0x20>;
-		interrupts = <0 28 1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
-		clock-names = "core", "clkin";
-
-		slot@1 {
-			compatible = "mmc-slot";
-			reg = <1>;
-
-			bus-width = <4>;
-		};
-	};
diff --git a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml
new file mode 100644
index 00000000000..022682a977c
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
+
+description: |
+  The highspeed MMC host controller on Amlogic SoCs provides an interface
+  for MMC, SD, SDIO and SDHC types of memory cards.
+
+  Supported maximum speeds are the ones of the eMMC standard 4.41 as well
+  as the speed of SD standard 2.0.
+
+  The hardware provides an internal "mux" which allows up to three slots
+  to be controlled. Only one slot can be accessed at a time.
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - amlogic,meson8-sdio
+          - amlogic,meson8b-sdio
+      - const: amlogic,meson-mx-sdio
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: core
+      - const: clkin
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "slot@[0-2]$":
+    $ref: mmc-slot.yaml#
+    description:
+      A node for each slot provided by the MMC controller
+
+    properties:
+      reg:
+        enum: [0, 1, 2]
+
+      bus-width:
+        enum: [1, 4]
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mmc@c1108c20 {
+        compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+        reg = <0xc1108c20 0x20>;
+        interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
+        clocks = <&clk_core>, <&clk_in>;
+        clock-names = "core", "clkin";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        slot@1 {
+            compatible = "mmc-slot";
+            reg = <1>;
+            bus-width = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml b/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
index 8c8ade88e8f..ba75623b777 100644
--- a/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
@@ -22,6 +22,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-sdhci
+              - microchip,sama7d65-sdhci
               - microchip,sama7g5-sdhci
           - const: microchip,sam9x60-sdhci
 
diff --git a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
index cfe6237716f..3f48d8292d5 100644
--- a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
@@ -38,15 +38,9 @@ properties:
 
   reg:
     minItems: 1
-    maxItems: 2
-    description: |
-      For "marvell,armada-3700-sdhci", two register areas.  The first one
-      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
-      Voltage Control register.  Please follow the examples with compatible
-      "marvell,armada-3700-sdhci" in below.
-      Please also check property marvell,pad-type in below.
-
-      For other compatible strings, one register area for Xenon IP.
+    items:
+      - description: Xenon IP registers
+      - description: Armada 3700 SoC PHY PAD Voltage Control register
 
   clocks:
     minItems: 1
@@ -61,6 +55,17 @@ properties:
   interrupts:
     maxItems: 1
 
+  marvell,pad-type:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - sd
+      - fixed-1-8v
+    description:
+      Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
+      selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
+      1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
+      PAD is fixed 1.8V, such as for eMMC.
+
   marvell,xenon-sdhc-id:
     $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
@@ -147,27 +152,18 @@ allOf:
     then:
       properties:
         reg:
-          items:
-            - description: Xenon IP registers
-            - description: Armada 3700 SoC PHY PAD Voltage Control register
-
-        marvell,pad-type:
-          $ref: /schemas/types.yaml#/definitions/string
-          enum:
-            - sd
-            - fixed-1-8v
-          description: |
-            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
-            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
-            and is switched to 1.8V when later in higher speed mode.
-            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
-            eMMC.
-            Please follow the examples with compatible
-            "marvell,armada-3700-sdhci" in below.
+          minItems: 2
 
       required:
         - marvell,pad-type
 
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
+        marvell,pad-type: false
+
   - if:
       properties:
         compatible:
diff --git a/dts/upstream/Bindings/mmc/mmc-controller-common.yaml b/dts/upstream/Bindings/mmc/mmc-controller-common.yaml
new file mode 100644
index 00000000000..9a723543975
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/mmc-controller-common.yaml
@@ -0,0 +1,357 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMC Controller & Slots Common Properties
+
+maintainers:
+  - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+  These properties are common to multiple MMC host controllers and the
+  possible slots or ports for multi-slot controllers.
+
+properties:
+  "#address-cells":
+    const: 1
+    description:
+      The cell is the SDIO function number if a function subnode is used.
+
+  "#size-cells":
+    const: 0
+
+  # Card Detection.
+  # If none of these properties are supplied, the host native card
+  # detect will be used. Only one of them should be provided.
+
+  broken-cd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      There is no card detection available; polling must be used.
+
+  cd-gpios:
+    maxItems: 1
+    description:
+      The card detection will be done using the GPIO provided.
+
+  non-removable:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Non-removable slot (like eMMC); assume always present.
+
+  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
+  # controllers line polarity properties, we have to fix the meaning
+  # of the "normal" and "inverted" line levels. We choose to follow
+  # the SDHCI standard, which specifies both those lines as "active
+  # low." Therefore, using the "cd-inverted" property means, that the
+  # CD line is active high, i.e. it is high, when a card is
+  # inserted. Similar logic applies to the "wp-inverted" property.
+  #
+  # CD and WP lines can be implemented on the hardware in one of two
+  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
+  # as dedicated pins. Polarity of dedicated pins can be specified,
+  # using *-inverted properties. GPIO polarity can also be specified
+  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
+  # latter case. We choose to use the XOR logic for GPIO CD and WP
+  # lines.  This means, the two properties are "superimposed," for
+  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
+  # respective *-inverted property property results in a
+  # double-inversion and actually means the "normal" line polarity is
+  # in effect.
+  wp-inverted:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The Write Protect line polarity is inverted.
+
+  cd-inverted:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The CD line polarity is inverted.
+
+  # Other properties
+
+  bus-width:
+    description:
+      Number of data lines.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 4, 8]
+    default: 1
+
+  max-frequency:
+    description: |
+      Maximum operating frequency of the bus:
+        - for eMMC, the maximum supported frequency is 200MHz,
+        - for SD/SDIO cards the SDR104 mode has a max supported
+          frequency of 208MHz,
+        - some mmc host controllers do support a max frequency upto
+          384MHz.
+      So, lets keep the maximum supported value here.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 400000
+    maximum: 384000000
+
+  disable-wp:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      When set, no physical write-protect line is present. This
+      property should only be specified when the controller has a
+      dedicated write-protect detection logic. If a GPIO is always used
+      for the write-protect detection logic, it is sufficient to not
+      specify the wp-gpios property in the absence of a write-protect
+      line. Not used in combination with eMMC or SDIO.
+
+  wp-gpios:
+    maxItems: 1
+    description:
+      GPIO to use for the write-protect detection.
+
+  cd-debounce-delay-ms:
+    description:
+      Set delay time before detecting card after card insert
+      interrupt.
+
+  no-1-8-v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      When specified, denotes that 1.8V card voltage is not supported
+      on this system, even if the controller claims it.
+
+  cap-sd-highspeed:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD high-speed timing is supported.
+
+  cap-mmc-highspeed:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      MMC high-speed timing is supported.
+
+  sd-uhs-sdr12:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR12 speed is supported.
+
+  sd-uhs-sdr25:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR25 speed is supported.
+
+  sd-uhs-sdr50:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR50 speed is supported.
+
+  sd-uhs-sdr104:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR104 speed is supported.
+
+  sd-uhs-ddr50:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS DDR50 speed is supported.
+
+  cap-power-off-card:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Powering off the card is safe.
+
+  cap-mmc-hw-reset:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC hardware reset is supported
+
+  cap-sdio-irq:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      enable SDIO IRQ signalling on this interface
+
+  full-pwr-cycle:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Full power cycle of the card is supported.
+
+  full-pwr-cycle-in-suspend:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Full power cycle of the card in suspend is supported.
+
+  mmc-ddr-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (1.2V I/O) is supported.
+
+  mmc-ddr-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (1.8V I/O) is supported.
+
+  mmc-ddr-3_3v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (3.3V I/O) is supported.
+
+  mmc-hs200-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS200 mode (1.2V I/O) is supported.
+
+  mmc-hs200-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS200 mode (1.8V I/O) is supported.
+
+  mmc-hs400-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 mode (1.2V I/O) is supported.
+
+  mmc-hs400-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 mode (1.8V I/O) is supported.
+
+  mmc-hs400-enhanced-strobe:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 enhanced strobe mode is supported
+
+  no-mmc-hs400:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      All eMMC HS400 modes are not supported.
+
+  dsr:
+    description:
+      Value the card Driver Stage Register (DSR) should be programmed
+      with.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 0xffff
+
+  no-sdio:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send SDIO commands during
+      initialization.
+
+  no-sd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send SD commands during initialization.
+
+  no-mmc:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send MMC commands during
+      initialization.
+
+  fixed-emmc-driver-type:
+    description:
+      For non-removable eMMC, enforce this driver type. The value is
+      the driver type as specified in the eMMC specification (table
+      206 in spec version 5.1)
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 4
+
+  post-power-on-delay-ms:
+    description:
+      It was invented for MMC pwrseq-simple which could be referred to
+      mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
+      waiting for I/O signalling and card power supply to be stable,
+      regardless of whether pwrseq-simple is used. Default to 10ms if
+      no available.
+    default: 10
+
+  supports-cqe:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The presence of this property indicates that the corresponding
+      MMC host controller supports HW command queue feature.
+
+  disable-cqe-dcmd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The presence of this property indicates that the MMC
+      controller\'s command queue engine (CQE) does not support direct
+      commands (DCMDs).
+
+  keep-power-in-suspend:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SDIO only. Preserves card power during a suspend/resume cycle.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SDIO only. Enables wake up of host system on SDIO IRQ assertion.
+
+  vmmc-supply:
+    description:
+      Supply for the card power
+
+  vqmmc-supply:
+    description:
+      Supply for the bus IO line power, such as a level shifter.
+      If the level shifter is controlled by a GPIO line, this shall
+      be modeled as a "regulator-fixed" with a GPIO line for
+      switching the level shifter on/off.
+
+  mmc-pwrseq:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      System-on-Chip designs may specify a specific MMC power
+      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
+      power sequence must be maintained while initializing the card.
+
+patternProperties:
+  "^.*@[0-9]+$":
+    type: object
+    description: |
+      On embedded systems the cards connected to a host may need
+      additional properties. These can be specified in subnodes to the
+      host controller node. The subnodes are identified by the
+      standard \'reg\' property. Which information exactly can be
+      specified depends on the bindings for the SDIO function driver
+      for the subnode, as specified by the compatible string.
+
+    properties:
+      compatible:
+        description:
+          Name of SDIO function following generic names recommended
+          practice
+
+      reg:
+        items:
+          - minimum: 0
+            maximum: 7
+            description:
+              Must contain the SDIO function number of the function this
+              subnode describes. A value of 0 denotes the memory SD
+              function, values from 1 to 7 denote the SDIO functions.
+
+    required:
+      - reg
+
+  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+    minItems: 2
+    maxItems: 2
+    items:
+      minimum: 0
+      maximum: 359
+      description:
+        Set the clock (phase) delays which are to be configured in the
+        controller while switching to particular speed mode. These values
+        are in pair of degrees.
+
+dependencies:
+  cd-debounce-delay-ms: [ cd-gpios ]
+  fixed-emmc-driver-type: [ non-removable ]
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/mmc/mmc-controller.yaml b/dts/upstream/Bindings/mmc/mmc-controller.yaml
index 58ae298cd2f..9d7a1298c45 100644
--- a/dts/upstream/Bindings/mmc/mmc-controller.yaml
+++ b/dts/upstream/Bindings/mmc/mmc-controller.yaml
@@ -9,7 +9,7 @@ title: MMC Controller Common Properties
 maintainers:
   - Ulf Hansson <ulf.hansson@linaro.org>
 
-description: |
+description:
   These properties are common to multiple MMC host controllers. Any host
   that requires the respective functionality should implement them using
   these definitions.
@@ -18,351 +18,13 @@ description: |
   (and the corresponding mmcblkN devices) by defining an alias in the
   /aliases device tree node.
 
+$ref: mmc-controller-common.yaml#
+
 properties:
   $nodename:
     pattern: "^mmc(@.*)?$"
 
-  "#address-cells":
-    const: 1
-    description: |
-      The cell is the slot ID if a function subnode is used.
-
-  "#size-cells":
-    const: 0
-
-  # Card Detection.
-  # If none of these properties are supplied, the host native card
-  # detect will be used. Only one of them should be provided.
-
-  broken-cd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      There is no card detection available; polling must be used.
-
-  cd-gpios:
-    maxItems: 1
-    description:
-      The card detection will be done using the GPIO provided.
-
-  non-removable:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Non-removable slot (like eMMC); assume always present.
-
-  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
-  # controllers line polarity properties, we have to fix the meaning
-  # of the "normal" and "inverted" line levels. We choose to follow
-  # the SDHCI standard, which specifies both those lines as "active
-  # low." Therefore, using the "cd-inverted" property means, that the
-  # CD line is active high, i.e. it is high, when a card is
-  # inserted. Similar logic applies to the "wp-inverted" property.
-  #
-  # CD and WP lines can be implemented on the hardware in one of two
-  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
-  # as dedicated pins. Polarity of dedicated pins can be specified,
-  # using *-inverted properties. GPIO polarity can also be specified
-  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
-  # latter case. We choose to use the XOR logic for GPIO CD and WP
-  # lines.  This means, the two properties are "superimposed," for
-  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
-  # respective *-inverted property property results in a
-  # double-inversion and actually means the "normal" line polarity is
-  # in effect.
-  wp-inverted:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The Write Protect line polarity is inverted.
-
-  cd-inverted:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The CD line polarity is inverted.
-
-  # Other properties
-
-  bus-width:
-    description:
-      Number of data lines.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [1, 4, 8]
-    default: 1
-
-  max-frequency:
-    description: |
-      Maximum operating frequency of the bus:
-        - for eMMC, the maximum supported frequency is 200MHz,
-        - for SD/SDIO cards the SDR104 mode has a max supported
-          frequency of 208MHz,
-        - some mmc host controllers do support a max frequency upto
-          384MHz.
-      So, lets keep the maximum supported value here.
-
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 400000
-    maximum: 384000000
-
-  disable-wp:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      When set, no physical write-protect line is present. This
-      property should only be specified when the controller has a
-      dedicated write-protect detection logic. If a GPIO is always used
-      for the write-protect detection logic, it is sufficient to not
-      specify the wp-gpios property in the absence of a write-protect
-      line. Not used in combination with eMMC or SDIO.
-
-  wp-gpios:
-    maxItems: 1
-    description:
-      GPIO to use for the write-protect detection.
-
-  cd-debounce-delay-ms:
-    description:
-      Set delay time before detecting card after card insert
-      interrupt.
-
-  no-1-8-v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      When specified, denotes that 1.8V card voltage is not supported
-      on this system, even if the controller claims it.
-
-  cap-sd-highspeed:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD high-speed timing is supported.
-
-  cap-mmc-highspeed:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      MMC high-speed timing is supported.
-
-  sd-uhs-sdr12:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR12 speed is supported.
-
-  sd-uhs-sdr25:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR25 speed is supported.
-
-  sd-uhs-sdr50:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR50 speed is supported.
-
-  sd-uhs-sdr104:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR104 speed is supported.
-
-  sd-uhs-ddr50:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS DDR50 speed is supported.
-
-  cap-power-off-card:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Powering off the card is safe.
-
-  cap-mmc-hw-reset:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC hardware reset is supported
-
-  cap-sdio-irq:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      enable SDIO IRQ signalling on this interface
-
-  full-pwr-cycle:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Full power cycle of the card is supported.
-
-  full-pwr-cycle-in-suspend:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Full power cycle of the card in suspend is supported.
-
-  mmc-ddr-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (1.2V I/O) is supported.
-
-  mmc-ddr-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (1.8V I/O) is supported.
-
-  mmc-ddr-3_3v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (3.3V I/O) is supported.
-
-  mmc-hs200-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS200 mode (1.2V I/O) is supported.
-
-  mmc-hs200-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS200 mode (1.8V I/O) is supported.
-
-  mmc-hs400-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 mode (1.2V I/O) is supported.
-
-  mmc-hs400-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 mode (1.8V I/O) is supported.
-
-  mmc-hs400-enhanced-strobe:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 enhanced strobe mode is supported
-
-  no-mmc-hs400:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      All eMMC HS400 modes are not supported.
-
-  dsr:
-    description:
-      Value the card Driver Stage Register (DSR) should be programmed
-      with.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 0xffff
-
-  no-sdio:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send SDIO commands during
-      initialization.
-
-  no-sd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send SD commands during initialization.
-
-  no-mmc:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send MMC commands during
-      initialization.
-
-  fixed-emmc-driver-type:
-    description:
-      For non-removable eMMC, enforce this driver type. The value is
-      the driver type as specified in the eMMC specification (table
-      206 in spec version 5.1)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 4
-
-  post-power-on-delay-ms:
-    description:
-      It was invented for MMC pwrseq-simple which could be referred to
-      mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
-      waiting for I/O signalling and card power supply to be stable,
-      regardless of whether pwrseq-simple is used. Default to 10ms if
-      no available.
-    default: 10
-
-  supports-cqe:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The presence of this property indicates that the corresponding
-      MMC host controller supports HW command queue feature.
-
-  disable-cqe-dcmd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The presence of this property indicates that the MMC
-      controller\'s command queue engine (CQE) does not support direct
-      commands (DCMDs).
-
-  keep-power-in-suspend:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SDIO only. Preserves card power during a suspend/resume cycle.
-
-  wakeup-source:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SDIO only. Enables wake up of host system on SDIO IRQ assertion.
-
-  vmmc-supply:
-    description:
-      Supply for the card power
-
-  vqmmc-supply:
-    description:
-      Supply for the bus IO line power, such as a level shifter.
-      If the level shifter is controlled by a GPIO line, this shall
-      be modeled as a "regulator-fixed" with a GPIO line for
-      switching the level shifter on/off.
-
-  mmc-pwrseq:
-    $ref: /schemas/types.yaml#/definitions/phandle
-    description:
-      System-on-Chip designs may specify a specific MMC power
-      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
-      power sequence must be maintained while initializing the card.
-
-patternProperties:
-  "^.*@[0-9]+$":
-    type: object
-    description: |
-      On embedded systems the cards connected to a host may need
-      additional properties. These can be specified in subnodes to the
-      host controller node. The subnodes are identified by the
-      standard \'reg\' property. Which information exactly can be
-      specified depends on the bindings for the SDIO function driver
-      for the subnode, as specified by the compatible string.
-
-    properties:
-      compatible:
-        description: |
-          Name of SDIO function following generic names recommended
-          practice
-
-      reg:
-        items:
-          - minimum: 0
-            maximum: 7
-            description:
-              Must contain the SDIO function number of the function this
-              subnode describes. A value of 0 denotes the memory SD
-              function, values from 1 to 7 denote the SDIO functions.
-
-    required:
-      - reg
-
-  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-
-    minItems: 2
-    maxItems: 2
-    items:
-      minimum: 0
-      maximum: 359
-      description:
-        Set the clock (phase) delays which are to be configured in the
-        controller while switching to particular speed mode. These values
-        are in pair of degrees.
-
-dependencies:
-  cd-debounce-delay-ms: [ cd-gpios ]
-  fixed-emmc-driver-type: [ non-removable ]
-
-additionalProperties: true
+unevaluatedProperties: true
 
 examples:
   - |
diff --git a/dts/upstream/Bindings/mmc/mmc-slot.yaml b/dts/upstream/Bindings/mmc/mmc-slot.yaml
new file mode 100644
index 00000000000..1f066782806
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/mmc-slot.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMC slot properties
+
+maintainers:
+  - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+  These properties defines slot properties for MMC controlers that
+  have multiple slots or ports provided by the same controller and
+  sharing the same resources.
+
+$ref: mmc-controller-common.yaml#
+
+properties:
+  $nodename:
+    pattern: "^slot(@.*)?$"
+
+  compatible:
+    const: mmc-slot
+
+  reg:
+    description:
+      the slot (or "port") ID
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    mmc {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      slot@0 {
+        compatible = "mmc-slot";
+        reg = <0>;
+        bus-width = <4>;
+      };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mmc/mtk-sd.yaml b/dts/upstream/Bindings/mmc/mtk-sd.yaml
index f86ebd81f5a..0debccbd651 100644
--- a/dts/upstream/Bindings/mmc/mtk-sd.yaml
+++ b/dts/upstream/Bindings/mmc/mtk-sd.yaml
@@ -235,11 +235,19 @@ allOf:
       properties:
         compatible:
           contains:
-            const: mediatek,mt8183-mmc
+            enum:
+              - mediatek,mt7986-mmc
+              - mediatek,mt7988-mmc
+              - mediatek,mt8183-mmc
+              - mediatek,mt8196-mmc
     then:
       properties:
         reg:
           minItems: 2
+    else:
+      properties:
+        reg:
+          maxItems: 1
 
   - if:
       properties:
diff --git a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
index 5fe65795f79..ef2d1d7c92f 100644
--- a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
+++ b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
@@ -29,6 +29,7 @@ properties:
               - samsung,exynos5433-dw-mshc-smu
               - samsung,exynos7885-dw-mshc-smu
               - samsung,exynos850-dw-mshc-smu
+              - samsung,exynos8895-dw-mshc-smu
           - const: samsung,exynos7-dw-mshc-smu
 
   reg:
diff --git a/dts/upstream/Bindings/mmc/sdhci-msm.yaml b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
index 8b393e26e02..eed9063e9bb 100644
--- a/dts/upstream/Bindings/mmc/sdhci-msm.yaml
+++ b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm SDHCI controller (sdhci-msm)
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   Secure Digital Host Controller Interface (SDHCI) present on
diff --git a/dts/upstream/Bindings/mtd/cadence-nand-controller.txt b/dts/upstream/Bindings/mtd/cadence-nand-controller.txt
deleted file mode 100644
index d2eada5044b..00000000000
--- a/dts/upstream/Bindings/mtd/cadence-nand-controller.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Cadence NAND controller
-
-Required properties:
-  - compatible : "cdns,hp-nfc"
-  - reg : Contains two entries, each of which is a tuple consisting of a
-	  physical address and length. The first entry is the address and
-	  length of the controller register set. The second entry is the
-	  address and length of the Slave DMA data port.
-  - reg-names: should contain "reg" and "sdma"
-  - #address-cells: should be 1. The cell encodes the chip select connection.
-  - #size-cells : should be 0.
-  - interrupts : The interrupt number.
-  - clocks: phandle of the controller core clock (nf_clk).
-
-Optional properties:
-  - dmas: shall reference DMA channel associated to the NAND controller
-  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
-    round trip delay for the signals and is used for deciding on values
-    associated with data read capture. The example formula for SDR mode is
-    the following:
-    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
-    + DQ PAD delay
-
-Child nodes represent the available NAND chips.
-
-Required properties of NAND chips:
-  - reg: shall contain the native Chip Select ids from 0 to max supported by
-    the cadence nand flash controller
-
-See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
-generic bindings.
-
-Example:
-
-nand_controller: nand-controller@60000000 {
-	  compatible = "cdns,hp-nfc";
-	  #address-cells = <1>;
-	  #size-cells = <0>;
-	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
-	  reg-names = "reg", "sdma";
-	  clocks = <&nf_clk>;
-	  cdns,board-delay-ps = <4830>;
-	  interrupts = <2 0>;
-	  nand@0 {
-	      reg = <0>;
-	      label = "nand-1";
-	  };
-	  nand@1 {
-	      reg = <1>;
-	      label = "nand-2";
-	  };
-
-};
diff --git a/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml
new file mode 100644
index 00000000000..e1f4d7c35a8
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
+
+allOf:
+  - $ref: nand-controller.yaml
+
+properties:
+  compatible:
+    items:
+      - const: cdns,hp-nfc
+
+  reg:
+    items:
+      - description: Controller register set
+      - description: Slave DMA data port register set
+
+  reg-names:
+    items:
+      - const: reg
+      - const: sdma
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: nf_clk
+
+  dmas:
+    maxItems: 1
+
+  cdns,board-delay-ps:
+    description: |
+      Estimated Board delay. The value includes the total round trip
+      delay for the signals and is used for deciding on values associated
+      with data read capture. The example formula for SDR mode is the
+      following.
+      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+      + DQ PAD delay
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    nand-controller@10b80000 {
+        compatible = "cdns,hp-nfc";
+        reg = <0x10b80000 0x10000>,
+              <0x10840000 0x10000>;
+        reg-names = "reg", "sdma";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk>;
+        clock-names = "nf_clk";
+        cdns,board-delay-ps = <4830>;
+
+        nand@0 {
+            reg = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mtd/davinci-nand.txt b/dts/upstream/Bindings/mtd/davinci-nand.txt
deleted file mode 100644
index eb8e2ff4dbd..00000000000
--- a/dts/upstream/Bindings/mtd/davinci-nand.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Device tree bindings for Texas instruments Davinci/Keystone NAND controller
-
-This file provides information, what the device node for the davinci/keystone
-NAND interface contains.
-
-Documentation:
-Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
-Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
-
-Required properties:
-
-- compatible:			"ti,davinci-nand"
-				"ti,keystone-nand"
-
-- reg:				Contains 2 offset/length values:
-				- offset and length for the access window.
-				- offset and length for accessing the AEMIF
-				control registers.
-
-- ti,davinci-chipselect:	number of chipselect. Indicates on the
-				davinci_nand driver which chipselect is used
-				for accessing the nand.
-				Can be in the range [0-3].
-
-Recommended properties :
-
-- ti,davinci-mask-ale:		mask for ALE. Needed for executing address
-				phase. These offset will be added to the base
-				address for the chip select space the NAND Flash
-				device is connected to.
-				If not set equal to 0x08.
-
-- ti,davinci-mask-cle:		mask for CLE. Needed for executing command
-				phase. These offset will be added to the base
-				address for the chip select space the NAND Flash
-				device is connected to.
-				If not set equal to 0x10.
-
-- ti,davinci-mask-chipsel:	mask for chipselect address. Needed to mask
-				addresses for given chipselect.
-
-- nand-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
-				valid values for davinci driver:
-				- "none"
-				- "soft"
-				- "hw"
-
-- ti,davinci-ecc-bits:		used ECC bits, currently supported 1 or 4.
-
-- nand-bus-width:		buswidth 8 or 16. If not present 8.
-
-- nand-on-flash-bbt:		use flash based bad block table support. OOB
-				identifier is saved in OOB area. If not present
-				false.
-
-Deprecated properties:
-
-- ti,davinci-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
-				valid values for davinci driver:
-				- "none"
-				- "soft"
-				- "hw"
-
-- ti,davinci-nand-buswidth:	buswidth 8 or 16. If not present 8.
-
-- ti,davinci-nand-use-bbt:	use flash based bad block table support. OOB
-				identifier is saved in OOB area. If not present
-				false.
-
-Nand device bindings may contain additional sub-nodes describing partitions of
-the address space. See mtd.yaml for more detail. The NAND Flash timing
-values must be programmed in the chip select’s node of AEMIF
-memory-controller (see Documentation/devicetree/bindings/memory-controllers/
-davinci-aemif.txt).
-
-Example(da850 EVM ):
-
-nand_cs3@62000000 {
-	compatible = "ti,davinci-nand";
-	reg = <0x62000000 0x807ff
-	       0x68000000 0x8000>;
-	ti,davinci-chipselect = <1>;
-	ti,davinci-mask-ale = <0>;
-	ti,davinci-mask-cle = <0>;
-	ti,davinci-mask-chipsel = <0>;
-	nand-ecc-mode = "hw";
-	ti,davinci-ecc-bits = <4>;
-	nand-on-flash-bbt;
-
-	partition@180000 {
-		label = "ubifs";
-		reg = <0x180000 0x7e80000>;
-	};
-};
diff --git a/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml b/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
index 6e3afb42926..335f8204aa1 100644
--- a/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
+++ b/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
@@ -96,6 +96,10 @@ properties:
       If "broken-flash-reset" is present then having this property does not
       make any difference.
 
+  vcc-supply:
+    description:
+      Supply for the SPI NOR power.
+
   spi-cpol: true
   spi-cpha: true
 
diff --git a/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml b/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
index 0ff32bd00bf..5c6b628c608 100644
--- a/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
+++ b/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
@@ -16,8 +16,9 @@ description: |
 
 properties:
   compatible:
-    items:
-      - const: microchip,48l640
+    enum:
+      - fujitsu,mb85rs128ty
+      - microchip,48l640
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml b/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index 00000000000..0b651450a8f
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+maintainers:
+  - Hui-Ping Chen <hpchen0nvt@gmail.com>
+
+allOf:
+  - $ref: nand-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,ma35d1-nand-controller
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    $ref: raw-nand-chip.yaml
+    properties:
+      reg:
+        minimum: 0
+        maximum: 1
+
+      nand-ecc-step-size:
+        enum: [512, 1024]
+
+      nand-ecc-strength:
+        enum: [8, 12, 24]
+
+    required:
+      - reg
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        nand-controller@401A0000 {
+            compatible = "nuvoton,ma35d1-nand-controller";
+            reg = <0x0 0x401A0000 0x0 0x1000>;
+            interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clk NAND_GATE>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            nand@0 {
+                reg = <0>;
+                nand-on-flash-bbt;
+                nand-ecc-step-size = <512>;
+                nand-ecc-strength = <8>;
+
+                partitions {
+                    compatible = "fixed-partitions";
+                    #address-cells = <1>;
+                    #size-cells = <1>;
+
+                    uboot@0 {
+                        label = "nand-uboot";
+                        read-only;
+                        reg = <0x0 0x300000>;
+                    };
+                };
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml b/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml
new file mode 100644
index 00000000000..ed24b0ea86e
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci NAND controller
+
+maintainers:
+  - Marcus Folkesson <marcus.folkesson@gmail.com>
+
+allOf:
+  - $ref: nand-controller.yaml
+
+properties:
+  compatible:
+    enum:
+      - ti,davinci-nand
+      - ti,keystone-nand
+
+  reg:
+    items:
+      - description: Access window.
+      - description: AEMIF control registers.
+
+  partitions:
+    $ref: /schemas/mtd/partitions/partitions.yaml
+
+  ti,davinci-chipselect:
+    description:
+      Number of chipselect. Indicate on the davinci_nand driver which
+      chipselect is used for accessing the nand.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
+
+  ti,davinci-mask-ale:
+    description:
+      Mask for ALE. Needed for executing address phase. These offset will be
+      added to the base address for the chip select space the NAND Flash
+      device is connected to.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0x08
+
+  ti,davinci-mask-cle:
+    description:
+      Mask for CLE. Needed for executing command phase. These offset will be
+      added to the base address for the chip select space the NAND Flash device
+      is connected to.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0x10
+
+  ti,davinci-mask-chipsel:
+    description:
+      Mask for chipselect address. Needed to mask addresses for given
+      chipselect.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  ti,davinci-ecc-bits:
+    description: Used ECC bits.
+    enum: [1, 4]
+
+  ti,davinci-ecc-mode:
+    description: Operation mode of the NAND ECC mode.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [none, soft, hw, on-die]
+    deprecated: true
+
+  ti,davinci-nand-buswidth:
+    description: Bus width to the NAND chip.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8, 16]
+    default: 8
+    deprecated: true
+
+  ti,davinci-nand-use-bbt:
+    type: boolean
+    description:
+      Use flash based bad block table support. OOB identifier is saved in OOB
+      area.
+    deprecated: true
+
+required:
+  - compatible
+  - reg
+  - ti,davinci-chipselect
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <2>;
+      #size-cells = <1>;
+
+      nand-controller@2000000,0 {
+        compatible = "ti,davinci-nand";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0 0x02000000 0x02000000>,
+              <1 0x00000000 0x00008000>;
+
+        ti,davinci-chipselect = <1>;
+        ti,davinci-mask-ale = <0>;
+        ti,davinci-mask-cle = <0>;
+        ti,davinci-mask-chipsel = <0>;
+
+        ti,davinci-nand-buswidth = <16>;
+        ti,davinci-ecc-mode = "hw";
+        ti,davinci-ecc-bits = <4>;
+        ti,davinci-nand-use-bbt;
+
+        partitions {
+          compatible = "fixed-partitions";
+          #address-cells = <1>;
+          #size-cells = <1>;
+
+          partition@0 {
+            label = "u-boot env";
+            reg = <0 0x020000>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml b/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
index d1e2bca3c50..798a4c19f18 100644
--- a/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
+++ b/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
@@ -166,11 +166,11 @@ unevaluatedProperties: false
 examples:
   - |
     ethmac: ethernet@c9410000 {
-         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
-         reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
-         interrupts = <8>;
-         interrupt-names = "macirq";
-         clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
-         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
-         phy-mode = "rgmii";
+        compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+        reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
+        interrupts = <8>;
+        interrupt-names = "macirq";
+        clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
+        clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
+        phy-mode = "rgmii";
     };
diff --git a/dts/upstream/Bindings/net/asix,ax88178.yaml b/dts/upstream/Bindings/net/asix,ax88178.yaml
index 768504ccbf7..03341b7438d 100644
--- a/dts/upstream/Bindings/net/asix,ax88178.yaml
+++ b/dts/upstream/Bindings/net/asix,ax88178.yaml
@@ -63,8 +63,8 @@ examples:
             #size-cells = <0>;
 
             ethernet@1 {
-               compatible = "usbb95,772b";
-               reg = <1>;
+                compatible = "usbb95,772b";
+                reg = <1>;
             };
         };
     };
diff --git a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
index 7bb68311c60..a72152f7e29 100644
--- a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
+++ b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
@@ -101,7 +101,10 @@ properties:
   max-speed: true
 
   firmware-name:
-    description: specify the name of nvm firmware to load
+    minItems: 1
+    items:
+      - description: specify the name of nvm firmware to load
+      - description: specify the name of rampatch firmware to load
 
   local-bd-address: true
 
@@ -154,16 +157,11 @@ allOf:
               - qcom,wcn6750-bt
     then:
       required:
-        - enable-gpios
-        - swctrl-gpios
-        - vddio-supply
         - vddaon-supply
-        - vddbtcxmx-supply
         - vddrfacmn-supply
         - vddrfa0p8-supply
         - vddrfa1p7-supply
         - vddrfa1p2-supply
-        - vddasd-supply
   - if:
       properties:
         compatible:
diff --git a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
index 7c90a439053..0e3fb4e42e3 100644
--- a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
+++ b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
@@ -85,16 +85,16 @@ examples:
         #size-cells = <1>;
 
         mdio0: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
 
-           phy1: ethernet-phy@1 {
+            phy1: ethernet-phy@1 {
                 max-speed = <1000>;
                 reg = <1>;
                 compatible = "ethernet-phy-ieee802.3-c22";
-           };
+            };
         };
     };
 
@@ -110,10 +110,10 @@ examples:
         interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;
 
         mdio1: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
         };
     };
 
@@ -129,15 +129,15 @@ examples:
         interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;
 
         mdio2: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
 
-           phy0: ethernet-phy@0 {
+            phy0: ethernet-phy@0 {
                 max-speed = <1000>;
                 reg = <0>;
                 compatible = "ethernet-phy-ieee802.3-c22";
-           };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
index af96b4fd89d..3f27746d9a5 100644
--- a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
+++ b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
@@ -38,43 +38,43 @@ unevaluatedProperties: false
 
 examples:
   - |
-    mdio_mux_iproc: mdio-mux@66020000 {
+    mdio-mux@66020000 {
         compatible = "brcm,mdio-mux-iproc";
         reg = <0x66020000 0x250>;
         #address-cells = <1>;
         #size-cells = <0>;
 
         mdio@0 {
-           reg = <0x0>;
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           pci_phy0: pci-phy@0 {
-              compatible = "brcm,ns2-pcie-phy";
-              reg = <0x0>;
-              #phy-cells = <0>;
-           };
+            reg = <0x0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            pci-phy@0 {
+                compatible = "brcm,ns2-pcie-phy";
+                reg = <0x0>;
+                #phy-cells = <0>;
+            };
         };
 
         mdio@7 {
-           reg = <0x7>;
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           pci_phy1: pci-phy@0 {
-              compatible = "brcm,ns2-pcie-phy";
-              reg = <0x0>;
-              #phy-cells = <0>;
-           };
+            reg = <0x7>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            pci-phy@0 {
+                compatible = "brcm,ns2-pcie-phy";
+                reg = <0x0>;
+                #phy-cells = <0>;
+            };
         };
 
         mdio@10 {
-           reg = <0x10>;
-           #address-cells = <1>;
-           #size-cells = <0>;
+            reg = <0x10>;
+            #address-cells = <1>;
+            #size-cells = <0>;
 
-           gphy0: eth-phy@10 {
-              reg = <0x10>;
-           };
+            eth-phy@10 {
+                reg = <0x10>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml b/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml
new file mode 100644
index 00000000000..c818c01a718
--- /dev/null
+++ b/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/atmel,at91sam9263-can.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 CAN Controller
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+allOf:
+  - $ref: can-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,at91sam9263-can
+          - atmel,at91sam9x5-can
+      - items:
+          - enum:
+              - microchip,sam9x60-can
+          - const: atmel,at91sam9x5-can
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: can_clk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/at91.h>
+    can@f000c000 {
+          compatible = "atmel,at91sam9263-can";
+          reg = <0xf000c000 0x300>;
+          interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+          clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
+          clock-names = "can_clk";
+    };
diff --git a/dts/upstream/Bindings/net/can/atmel-can.txt b/dts/upstream/Bindings/net/can/atmel-can.txt
deleted file mode 100644
index 218a3b3eb27..00000000000
--- a/dts/upstream/Bindings/net/can/atmel-can.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* AT91 CAN *
-
-Required properties:
-  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
-    "microchip,sam9x60-can"
-  - reg: Should contain CAN controller registers location and length
-  - interrupts: Should contain IRQ line for the CAN controller
-
-Example:
-
-	can0: can@f000c000 {
-		compatible = "atmel,at91sam9x5-can";
-		reg = <0xf000c000 0x300>;
-		interrupts = <40 4 5>
-	};
diff --git a/dts/upstream/Bindings/net/can/bosch,c_can.yaml b/dts/upstream/Bindings/net/can/bosch,c_can.yaml
index 4d7d67ee175..ff1b59a0294 100644
--- a/dts/upstream/Bindings/net/can/bosch,c_can.yaml
+++ b/dts/upstream/Bindings/net/can/bosch,c_can.yaml
@@ -99,11 +99,11 @@ examples:
     #include <dt-bindings/reset/altr,rst-mgr.h>
 
     can@ffc00000 {
-       compatible = "bosch,d_can";
-       reg = <0xffc00000 0x1000>;
-       interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
-       clocks = <&can0_clk>;
-       resets = <&rst CAN0_RESET>;
+        compatible = "bosch,d_can";
+        reg = <0xffc00000 0x1000>;
+        interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+        clocks = <&can0_clk>;
+        resets = <&rst CAN0_RESET>;
     };
   - |
     can@0 {
diff --git a/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml b/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
index db446dde684..e0ec53bc10c 100644
--- a/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
+++ b/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
@@ -56,15 +56,15 @@ examples:
         #size-cells = <0>;
 
         can@1 {
-             compatible = "microchip,mcp2515";
-             reg = <1>;
-             clocks = <&clk24m>;
-             interrupt-parent = <&gpio4>;
-             interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
-             vdd-supply = <&reg5v0>;
-             xceiver-supply = <&reg5v0>;
-             gpio-controller;
-             #gpio-cells = <2>;
+            compatible = "microchip,mcp2515";
+            reg = <1>;
+            clocks = <&clk24m>;
+            interrupt-parent = <&gpio4>;
+            interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+            vdd-supply = <&reg5v0>;
+            xceiver-supply = <&reg5v0>;
+            gpio-controller;
+            #gpio-cells = <2>;
         };
     };
 
diff --git a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
index 01e4d4a54df..1219c5cb601 100644
--- a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
+++ b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
@@ -15,7 +15,11 @@ allOf:
 
 properties:
   compatible:
-    const: microchip,mpfs-can
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-can
+          - const: microchip,mpfs-can
+      - const: microchip,mpfs-can
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml b/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
index 7c5ac5d2e88..f6884f6e59e 100644
--- a/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
+++ b/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
@@ -170,7 +170,7 @@ allOf:
             const: renesas,r8a779h0-canfd
     then:
       patternProperties:
-        "^channel[5-7]$": false
+        "^channel[4-7]$": false
     else:
       if:
         not:
diff --git a/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml b/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
index de1d4298893..c7510b00954 100644
--- a/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
+++ b/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
@@ -63,7 +63,7 @@ properties:
     maxItems: 1
 
   st,gcan:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
+    $ref: /schemas/types.yaml#/definitions/phandle
     description:
       The phandle to the gcan node which allows to access the 512-bytes
       SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
diff --git a/dts/upstream/Bindings/net/can/tcan4x5x.txt b/dts/upstream/Bindings/net/can/tcan4x5x.txt
deleted file mode 100644
index 20c0572c985..00000000000
--- a/dts/upstream/Bindings/net/can/tcan4x5x.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Texas Instruments TCAN4x5x CAN Controller
-================================================
-
-This file provides device node information for the TCAN4x5x interface contains.
-
-Required properties:
-	- compatible:
-		"ti,tcan4552", "ti,tcan4x5x"
-		"ti,tcan4553", "ti,tcan4x5x" or
-		"ti,tcan4x5x"
-	- reg: 0
-	- #address-cells: 1
-	- #size-cells: 0
-	- spi-max-frequency: Maximum frequency of the SPI bus the chip can
-			     operate at should be less than or equal to 18 MHz.
-	- interrupt-parent: the phandle to the interrupt controller which provides
-                    the interrupt.
-	- interrupts: interrupt specification for data-ready.
-
-See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional
-required property details.
-
-Optional properties:
-	- reset-gpios: Hardwired output GPIO. If not defined then software
-		       reset.
-	- device-state-gpios: Input GPIO that indicates if the device is in
-			      a sleep state or if the device is active. Not
-			      available with tcan4552/4553.
-	- device-wake-gpios: Wake up GPIO to wake up the TCAN device. Not
-			     available with tcan4552/4553.
-	- wakeup-source: Leave the chip running when suspended, and configure
-			 the RX interrupt to wake up the device.
-
-Example:
-tcan4x5x: tcan4x5x@0 {
-		compatible = "ti,tcan4x5x";
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <10000000>;
-		bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
-		device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
-		device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		wakeup-source;
-};
diff --git a/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml b/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml
new file mode 100644
index 00000000000..384e15da271
--- /dev/null
+++ b/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/ti,tcan4x5x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TCAN4x5x CAN Controller
+
+maintainers:
+  - Marc Kleine-Budde <mkl@pengutronix.de>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - ti,tcan4552
+              - ti,tcan4553
+          - const: ti,tcan4x5x
+      - const: ti,tcan4x5x
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description: The GPIO parent interrupt.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: cclk
+
+  reset-gpios:
+    description: Hardwired output GPIO. If not defined then software reset.
+    maxItems: 1
+
+  device-state-gpios:
+    description:
+      Input GPIO that indicates if the device is in a sleep state or if the
+      device is active. Not available with tcan4552/4553.
+    maxItems: 1
+
+  device-wake-gpios:
+    description:
+      Wake up GPIO to wake up the TCAN device.
+      Not available with tcan4552/4553.
+    maxItems: 1
+
+  bosch,mram-cfg:
+    description: |
+      Message RAM configuration data.
+      Multiple M_CAN instances can share the same Message RAM
+      and each element(e.g Rx FIFO or Tx Buffer and etc) number
+      in Message RAM is also configurable, so this property is
+      telling driver how the shared or private Message RAM are
+      used by this M_CAN controller.
+
+      The format should be as follows:
+      <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems>
+      The 'offset' is an address offset of the Message RAM where
+      the following elements start from. This is usually set to
+      0x0 if you're using a private Message RAM. The remain cells
+      are used to specify how many elements are used for each FIFO/Buffer.
+
+      M_CAN includes the following elements according to user manual:
+      11-bit Filter	0-128 elements / 0-128 words
+      29-bit Filter	0-64 elements / 0-128 words
+      Rx FIFO 0		0-64 elements / 0-1152 words
+      Rx FIFO 1		0-64 elements / 0-1152 words
+      Rx Buffers	0-64 elements / 0-1152 words
+      Tx Event FIFO	0-32 elements / 0-64 words
+      Tx Buffers	0-32 elements / 0-576 words
+
+      Please refer to 2.4.1 Message RAM Configuration in Bosch
+      M_CAN user manual for details.
+    $ref: /schemas/types.yaml#/definitions/int32-array
+    items:
+      - description: The 'offset' is an address offset of the Message RAM where
+          the following elements start from. This is usually set to 0x0 if
+          you're using a private Message RAM.
+        default: 0
+      - description: 11-bit Filter 0-128 elements / 0-128 words
+        minimum: 0
+        maximum: 128
+      - description: 29-bit Filter 0-64 elements / 0-128 words
+        minimum: 0
+        maximum: 64
+      - description: Rx FIFO 0 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Rx FIFO 1 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Rx Buffers 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Tx Event FIFO 0-32 elements / 0-64 words
+        minimum: 0
+        maximum: 32
+      - description: Tx Buffers 0-32 elements / 0-576 words
+        minimum: 0
+        maximum: 32
+    minItems: 1
+
+  spi-max-frequency:
+    description:
+      Must be half or less of "clocks" frequency.
+    maximum: 18000000
+
+  ti,nwkrq-voltage-vio:
+    type: boolean
+    description:
+      nWKRQ Pin GPO buffer voltage configuration.
+      Set nWKRQ to use VIO voltage rail.
+      When not set nWKRQ will use internal voltage rail.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable CAN remote wakeup.
+
+allOf:
+  - $ref: can-controller.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,tcan4552
+              - ti,tcan4553
+    then:
+      properties:
+        device-state-gpios: false
+        device-wake-gpios: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - bosch,mram-cfg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        can@0 {
+            compatible = "ti,tcan4x5x";
+            reg = <0>;
+            clocks = <&can0_osc>;
+            clock-names = "cclk";
+            pinctrl-names = "default";
+            pinctrl-0 = <&can0_pins>;
+            spi-max-frequency = <10000000>;
+            bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+            device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+            device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+            ti,nwkrq-voltage-vio;
+            wakeup-source;
+        };
+    };
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        can@0 {
+            compatible = "ti,tcan4552", "ti,tcan4x5x";
+            reg = <0>;
+            clocks = <&can0_osc>;
+            clock-names = "cclk";
+            pinctrl-names = "default";
+            pinctrl-0 = <&can0_pins>;
+            spi-max-frequency = <10000000>;
+            bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+            reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+            wakeup-source;
+        };
+    };
diff --git a/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml b/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
index dedfad52666..a73fc503690 100644
--- a/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
+++ b/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
@@ -129,6 +129,24 @@ properties:
             minimum: 0
             maximum: 383
 
+          rx-internal-delay-ps:
+            description:
+              RGMII Receive Clock Delay defined in pico seconds, used to select
+              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
+              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
+              any delay. The Default is no delay.
+            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
+            default: 0
+
+          tx-internal-delay-ps:
+            description:
+              RGMII Transmit Clock Delay defined in pico seconds, used to select
+              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
+              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
+              any delay. The Default is no delay.
+            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
+            default: 0
+
         required:
           - reg
           - phys
diff --git a/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml b/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml
new file mode 100644
index 00000000000..2b8b74c5fee
--- /dev/null
+++ b/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021-2024 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
+
+maintainers:
+  - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
+
+description:
+  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
+  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
+  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
+  interface over Pinctrl device or the output can be routed
+  to the embedded SerDes for SGMII connectivity.
+
+properties:
+  compatible:
+    oneOf:
+      - const: nxp,s32g2-dwmac
+      - items:
+          - enum:
+              - nxp,s32g3-dwmac
+              - nxp,s32r45-dwmac
+          - const: nxp,s32g2-dwmac
+
+  reg:
+    items:
+      - description: Main GMAC registers
+      - description: GMAC PHY mode control register
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    const: macirq
+
+  clocks:
+    items:
+      - description: Main GMAC clock
+      - description: Transmit clock
+      - description: Receive clock
+      - description: PTP reference clock
+
+  clock-names:
+    items:
+      - const: stmmaceth
+      - const: tx
+      - const: rx
+      - const: ptp_ref
+
+required:
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/phy/phy.h>
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      ethernet@4033c000 {
+        compatible = "nxp,s32g2-dwmac";
+        reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
+              <0x0 0x4007c004 0x0 0x4>;    /* GMAC_0_CTRL_STS */
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq";
+        snps,mtl-rx-config = <&mtl_rx_setup>;
+        snps,mtl-tx-config = <&mtl_tx_setup>;
+        clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
+        clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
+        phy-mode = "rgmii-id";
+        phy-handle = <&phy0>;
+
+        mtl_rx_setup: rx-queues-config {
+          snps,rx-queues-to-use = <5>;
+        };
+
+        mtl_tx_setup: tx-queues-config {
+          snps,tx-queues-to-use = <5>;
+        };
+
+        mdio {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "snps,dwmac-mdio";
+
+          phy0: ethernet-phy@0 {
+            reg = <0>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/net/qcom,ethqos.yaml b/dts/upstream/Bindings/net/qcom,ethqos.yaml
index 0bcd593a7bd..e7ee0d9efed 100644
--- a/dts/upstream/Bindings/net/qcom,ethqos.yaml
+++ b/dts/upstream/Bindings/net/qcom,ethqos.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Ethernet ETHQOS device
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   dwmmac based Qualcomm ethernet devices which support Gigabit
@@ -21,12 +22,12 @@ properties:
     oneOf:
       - items:
           - enum:
-              - qcom,qcs8300-ethqos
-          - const: qcom,sa8775p-ethqos
+              - qcom,qcs615-ethqos
+          - const: qcom,qcs404-ethqos
       - items:
           - enum:
-              - qcom,qcs615-ethqos
-          - const: qcom,sm8150-ethqos
+              - qcom,qcs8300-ethqos
+          - const: qcom,sa8775p-ethqos
       - enum:
           - qcom,qcs404-ethqos
           - qcom,sa8775p-ethqos
diff --git a/dts/upstream/Bindings/net/qcom,ipa.yaml b/dts/upstream/Bindings/net/qcom,ipa.yaml
index 53cae71d995..1a46d80a66e 100644
--- a/dts/upstream/Bindings/net/qcom,ipa.yaml
+++ b/dts/upstream/Bindings/net/qcom,ipa.yaml
@@ -239,7 +239,7 @@ examples:
 
                 qcom,gsi-loader = "self";
                 memory-region = <&ipa_fw_mem>;
-                firmware-name = "qcom/sc7180-trogdor/modem/modem.mdt";
+                firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn";
 
                 iommus = <&apps_smmu 0x440 0x0>,
                          <&apps_smmu 0x442 0x0>;
diff --git a/dts/upstream/Bindings/net/snps,dwmac.yaml b/dts/upstream/Bindings/net/snps,dwmac.yaml
index eb1f3ae41ab..91e75eb3f32 100644
--- a/dts/upstream/Bindings/net/snps,dwmac.yaml
+++ b/dts/upstream/Bindings/net/snps,dwmac.yaml
@@ -67,6 +67,7 @@ properties:
         - ingenic,x2000-mac
         - loongson,ls2k-dwmac
         - loongson,ls7a-dwmac
+        - nxp,s32g2-dwmac
         - qcom,qcs404-ethqos
         - qcom,sa8775p-ethqos
         - qcom,sc8280xp-ethqos
diff --git a/dts/upstream/Bindings/net/stm32-dwmac.yaml b/dts/upstream/Bindings/net/stm32-dwmac.yaml
index bf23838fe6e..85cea9966a2 100644
--- a/dts/upstream/Bindings/net/stm32-dwmac.yaml
+++ b/dts/upstream/Bindings/net/stm32-dwmac.yaml
@@ -154,56 +154,56 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/stm32mp1-clks.h>
     //Example 1
-     ethernet0: ethernet@5800a000 {
-           compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-           reg = <0x5800a000 0x2000>;
-           reg-names = "stmmaceth";
-           interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-           interrupt-names = "macirq";
-           clock-names = "stmmaceth",
-                     "mac-clk-tx",
-                     "mac-clk-rx",
-                     "ethstp",
-                     "eth-ck";
-           clocks = <&rcc ETHMAC>,
-                <&rcc ETHTX>,
-                <&rcc ETHRX>,
-                <&rcc ETHSTP>,
-                <&rcc ETHCK_K>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <2>;
-           snps,axi-config = <&stmmac_axi_config_0>;
-           snps,tso;
-           phy-mode = "rgmii";
-       };
+    ethernet0: ethernet@5800a000 {
+        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+        reg = <0x5800a000 0x2000>;
+        reg-names = "stmmaceth";
+        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq";
+        clock-names = "stmmaceth",
+                      "mac-clk-tx",
+                      "mac-clk-rx",
+                      "ethstp",
+                      "eth-ck";
+        clocks = <&rcc ETHMAC>,
+                 <&rcc ETHTX>,
+                 <&rcc ETHRX>,
+                 <&rcc ETHSTP>,
+                 <&rcc ETHCK_K>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <2>;
+        snps,axi-config = <&stmmac_axi_config_0>;
+        snps,tso;
+        phy-mode = "rgmii";
+    };
 
   - |
     //Example 2 (MCU example)
-     ethernet1: ethernet@40028000 {
-           compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
-           reg = <0x40028000 0x8000>;
-           reg-names = "stmmaceth";
-           interrupts = <0 61 0>, <0 62 0>;
-           interrupt-names = "macirq", "eth_wake_irq";
-           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-           clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <8>;
-           snps,mixed-burst;
-           phy-mode = "mii";
-       };
+    ethernet1: ethernet@40028000 {
+        compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+        reg = <0x40028000 0x8000>;
+        reg-names = "stmmaceth";
+        interrupts = <0 61 0>, <0 62 0>;
+        interrupt-names = "macirq", "eth_wake_irq";
+        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+        clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <8>;
+        snps,mixed-burst;
+        phy-mode = "mii";
+    };
 
   - |
     //Example 3
-     ethernet2: ethernet@40027000 {
-           compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
-           reg = <0x40028000 0x8000>;
-           reg-names = "stmmaceth";
-           interrupts = <61>;
-           interrupt-names = "macirq";
-           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-           clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <8>;
-           phy-mode = "mii";
-       };
+    ethernet2: ethernet@40027000 {
+        compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+        reg = <0x40028000 0x8000>;
+        reg-names = "stmmaceth";
+        interrupts = <61>;
+        interrupt-names = "macirq";
+        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+        clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <8>;
+        phy-mode = "mii";
+    };
diff --git a/dts/upstream/Bindings/net/ti,davinci-mdio.yaml b/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
index 53604fab0b7..08119b6880e 100644
--- a/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
+++ b/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
@@ -72,9 +72,9 @@ unevaluatedProperties: false
 examples:
   - |
     davinci_mdio: mdio@4a101000 {
-         compatible = "ti,davinci_mdio";
-         #address-cells = <1>;
-         #size-cells = <0>;
-         reg = <0x4a101000 0x1000>;
-         bus_freq = <1000000>;
+        compatible = "ti,davinci_mdio";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x4a101000 0x1000>;
+        bus_freq = <1000000>;
     };
diff --git a/dts/upstream/Bindings/net/ti,dp83822.yaml b/dts/upstream/Bindings/net/ti,dp83822.yaml
index 784866ea392..50c24248df2 100644
--- a/dts/upstream/Bindings/net/ti,dp83822.yaml
+++ b/dts/upstream/Bindings/net/ti,dp83822.yaml
@@ -96,6 +96,32 @@ properties:
       - master
       - slave
 
+  ti,gpio2-clk-out:
+    description: |
+       DP83822 PHY only.
+       The GPIO2 pin on the DP83822 can be configured as clock output. When
+       omitted, the PHY's default will be left as is.
+
+       - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
+         clock frequency is 50-MHz and in RGMII Mode the clock frequency is
+         25-MHz.
+       - 'xi': XI clock(pass-through clock from XI pin).
+       - 'int-ref': Internal reference clock 25-MHz.
+       - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
+         master mode reference clock is identical to MAC IF clock in RMII master
+         mode.
+       - 'free-running': Free running clock 125-MHz.
+       - 'recovered': Recovered clock is a 125-MHz recovered clock from a
+         connected link partner.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - mac-if
+      - xi
+      - int-ref
+      - rmii-master-mode-ref
+      - free-running
+      - recovered
+
 required:
   - reg
 
@@ -110,6 +136,7 @@ examples:
         reg = <0>;
         rx-internal-delay-ps = <1>;
         tx-internal-delay-ps = <1>;
+        ti,gpio2-clk-out = "xi";
       };
     };
 
diff --git a/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
index 02b6d32003c..b11894fbaec 100644
--- a/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
+++ b/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -302,16 +302,16 @@ examples:
                     ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                 };
             };
-        };
 
-        cpts@3d000 {
-             compatible = "ti,am65-cpts";
-             reg = <0x0 0x3d000 0x0 0x400>;
-             clocks = <&k3_clks 18 2>;
-             clock-names = "cpts";
-             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
-             interrupt-names = "cpts";
-             ti,cpts-ext-ts-inputs = <4>;
-             ti,cpts-periodic-outputs = <2>;
+            cpts@3d000 {
+                compatible = "ti,am65-cpts";
+                reg = <0x0 0x3d000 0x0 0x400>;
+                clocks = <&k3_clks 18 2>;
+                clock-names = "cpts";
+                interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "cpts";
+                ti,cpts-ext-ts-inputs = <4>;
+                ti,cpts-periodic-outputs = <2>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml b/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
index 3888692275a..3572749147f 100644
--- a/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
+++ b/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
@@ -131,23 +131,23 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     cpts@310d0000 {
-         compatible = "ti,am65-cpts";
-         reg = <0x310d0000 0x400>;
-         reg-names = "cpts";
-         clocks = <&main_cpts_mux>;
-         clock-names = "cpts";
-         interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
-         interrupt-names = "cpts";
-         ti,cpts-periodic-outputs = <6>;
-         ti,cpts-ext-ts-inputs = <8>;
-
-         main_cpts_mux: refclk-mux {
-               #clock-cells = <0>;
-               clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
-                        <&k3_clks 157 91>, <&k3_clks 157 77>,
-                        <&k3_clks 157 102>, <&k3_clks 157 80>,
-                        <&k3_clks 120 3>, <&k3_clks 121 3>;
-               assigned-clocks = <&main_cpts_mux>;
-               assigned-clock-parents = <&k3_clks 118 11>;
-         };
+        compatible = "ti,am65-cpts";
+        reg = <0x310d0000 0x400>;
+        reg-names = "cpts";
+        clocks = <&main_cpts_mux>;
+        clock-names = "cpts";
+        interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "cpts";
+        ti,cpts-periodic-outputs = <6>;
+        ti,cpts-ext-ts-inputs = <8>;
+
+        main_cpts_mux: refclk-mux {
+            #clock-cells = <0>;
+            clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+                     <&k3_clks 157 91>, <&k3_clks 157 77>,
+                     <&k3_clks 157 102>, <&k3_clks 157 80>,
+                     <&k3_clks 120 3>, <&k3_clks 121 3>;
+            assigned-clocks = <&main_cpts_mux>;
+            assigned-clock-parents = <&k3_clks 118 11>;
+        };
     };
diff --git a/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml b/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
index 1715b22e0dc..930b700b73d 100644
--- a/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
+++ b/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
@@ -79,15 +79,14 @@ examples:
     #include <dt-bindings/interrupt-controller/irq.h>
 
     mmc {
-         #address-cells = <1>;
-         #size-cells = <0>;
-
-         wifi@1 {
-             compatible = "marvell,sd8897";
-             reg = <1>;
-             interrupt-parent = <&pio>;
-             interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
-             marvell,wakeup-pin = <3>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        wifi@1 {
+            compatible = "marvell,sd8897";
+            reg = <1>;
+            interrupt-parent = <&pio>;
+            interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+            marvell,wakeup-pin = <3>;
         };
     };
-
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
index 070c4c9b864..aace072e2d5 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
@@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath10k wireless devices
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description:
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
index a71fdf05bc1..a4425cf196a 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath11k wireless devices (PCIe)
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description: |
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
index ff5763dc66a..a69ffb7b3cb 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath11k wireless devices
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description: |
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml
new file mode 100644
index 00000000000..318f305405e
--- /dev/null
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k-wsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies ath12k wireless devices (PCIe) with WSI interface
+
+maintainers:
+  - Jeff Johnson <jjohnson@kernel.org>
+
+description: |
+  Qualcomm Technologies IEEE 802.11be PCIe devices with WSI interface.
+
+  The ath12k devices (QCN9274) feature WSI support. WSI stands for
+  WLAN Serial Interface. It is used for the exchange of specific
+  control information across radios based on the doorbell mechanism.
+  This WSI connection is essential to exchange control information
+  among these devices.
+
+  The WSI interface includes TX and RX ports, which are used to connect
+  multiple WSI-supported devices together, forming a WSI group.
+
+  Diagram to represent one WSI connection (one WSI group) among
+  three devices.
+
+           +-------+        +-------+        +-------+
+           | pcie1 |        | pcie2 |        | pcie3 |
+           |       |        |       |        |       |
+    +----->|  wsi  |------->|  wsi  |------->|  wsi  |-----+
+    |      | grp 0 |        | grp 0 |        | grp 0 |     |
+    |      +-------+        +-------+        +-------+     |
+    +------------------------------------------------------+
+
+  Diagram to represent two WSI connections (two separate WSI groups)
+  among four devices.
+
+       +-------+    +-------+          +-------+    +-------+
+       | pcie0 |    | pcie1 |          | pcie2 |    | pcie3 |
+       |       |    |       |          |       |    |       |
+   +-->|  wsi  |--->|  wsi  |--+   +-->|  wsi  |--->|  wsi  |--+
+   |   | grp 0 |    | grp 0 |  |   |   | grp 1 |    | grp 1 |  |
+   |   +-------+    +-------+  |   |   +-------+    +-------+  |
+   +---------------------------+   +---------------------------+
+
+properties:
+  compatible:
+    enum:
+      - pci17cb,1109  # QCN9274
+
+  reg:
+    maxItems: 1
+
+  qcom,ath12k-calibration-variant:
+    $ref: /schemas/types.yaml#/definitions/string
+    description:
+      String to uniquely identify variant of the calibration data for designs
+      with colliding bus and device ids
+
+  qcom,wsi-controller:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The WSI controller device in the WSI group aids (is capable) to
+      synchronize the Timing Synchronization Function (TSF) clock across
+      all devices in the WSI group.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          This is the TX port of WSI interface. It is attached to the RX
+          port of the next device in the WSI connection.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          This is the RX port of WSI interface. It is attached to the TX
+          port of the previous device in the WSI connection.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie {
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        pcie@0 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_1";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi1_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi2_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi1_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi3_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+
+        pcie@1 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x1 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_2";
+                qcom,wsi-controller;
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi2_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi3_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi2_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi1_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+
+        pcie@2 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x2 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_3";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi3_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi1_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi3_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi2_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
index 1b5884015b1..9e557cb838c 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
@@ -9,7 +9,6 @@ title: Qualcomm Technologies ath12k wireless devices (PCIe)
 
 maintainers:
   - Jeff Johnson <quic_jjohnson@quicinc.com>
-  - Kalle Valo <kvalo@kernel.org>
 
 description:
   Qualcomm Technologies IEEE 802.11be PCIe devices.
diff --git a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
index 80845c722ae..39c209249c9 100644
--- a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
+++ b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
@@ -20,18 +20,23 @@ properties:
           - qcom,apq8064-qfprom
           - qcom,apq8084-qfprom
           - qcom,ipq5332-qfprom
+          - qcom,ipq5424-qfprom
           - qcom,ipq6018-qfprom
           - qcom,ipq8064-qfprom
           - qcom,ipq8074-qfprom
           - qcom,ipq9574-qfprom
           - qcom,msm8226-qfprom
           - qcom,msm8916-qfprom
+          - qcom,msm8917-qfprom
           - qcom,msm8974-qfprom
           - qcom,msm8976-qfprom
           - qcom,msm8996-qfprom
           - qcom,msm8998-qfprom
           - qcom,qcm2290-qfprom
           - qcom,qcs404-qfprom
+          - qcom,qcs615-qfprom
+          - qcom,qcs8300-qfprom
+          - qcom,sar2130p-qfprom
           - qcom,sc7180-qfprom
           - qcom,sc7280-qfprom
           - qcom,sc8280xp-qfprom
diff --git a/dts/upstream/Bindings/nvmem/rmem.yaml b/dts/upstream/Bindings/nvmem/rmem.yaml
index 1ec0d09bcaf..85f9f5de390 100644
--- a/dts/upstream/Bindings/nvmem/rmem.yaml
+++ b/dts/upstream/Bindings/nvmem/rmem.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     items:
       - enum:
+          - mobileye,eyeq5-bootloader-config
           - raspberrypi,bootloader-config
           - raspberrypi,bootloader-public-key
       - const: nvmem-rmem
diff --git a/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml b/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
index dc25fe3d184..8672bde24a9 100644
--- a/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
+++ b/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
@@ -36,33 +36,4 @@ allOf:
   - $ref: nvmem-deprecated-cells.yaml#
 
 unevaluatedProperties: false
-
-examples:
-  - |
-    pmic {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      efuse@380 {
-        compatible = "sprd,sc2731-efuse";
-        reg = <0x380>;
-        hwlocks = <&hwlock 12>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        /* Data cells */
-        fgu_calib: calib@6 {
-          reg = <0x6 0x2>;
-          bits = <0 9>;
-        };
-
-        adc_big_scale: calib@24 {
-          reg = <0x24 0x2>;
-        };
-
-        adc_small_scale: calib@26 {
-          reg = <0x26 0x2>;
-        };
-      };
-    };
 ...
diff --git a/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
index ec5e424bb3c..75ab552f6ec 100644
--- a/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+++ b/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
@@ -22,6 +22,7 @@ allOf:
 properties:
   compatible:
     enum:
+      - allwinner,sun50i-a100-operating-points
       - allwinner,sun50i-h6-operating-points
       - allwinner,sun50i-h616-operating-points
 
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
index a8b34f58f8f..cddbe21f99f 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
@@ -17,11 +17,11 @@ description:
 properties:
   clocks:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   clock-names:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   num-lanes:
     const: 1
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
index 84ca12e8b25..0b3526de1d6 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -22,6 +22,7 @@ properties:
       - fsl,imx8mm-pcie-ep
       - fsl,imx8mq-pcie-ep
       - fsl,imx8mp-pcie-ep
+      - fsl,imx8q-pcie-ep
       - fsl,imx95-pcie-ep
 
   clocks:
@@ -78,6 +79,20 @@ allOf:
       properties:
         compatible:
           enum:
+            - fsl,imx8q-pcie-ep
+    then:
+      properties:
+        reg:
+          maxItems: 2
+        reg-names:
+          items:
+            - const: dbi
+            - const: addr_space
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - fsl,imx95-pcie-ep
     then:
       properties:
@@ -103,13 +118,21 @@ allOf:
       properties:
         clocks:
           minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-    else:
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx8mm-pcie-ep
+            - fsl,imx8mp-pcie-ep
+    then:
       properties:
         clocks:
           maxItems: 3
@@ -119,6 +142,20 @@ allOf:
             - const: pcie_bus
             - const: pcie_aux
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imxq-pcie-ep
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          items:
+            - const: dbi
+            - const: mstr
+            - const: slv
 
 unevaluatedProperties: false
 
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
index 1e05c560d79..4c76cd3f98a 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
@@ -40,10 +40,11 @@ properties:
       - description: PCIe PHY clock.
       - description: Additional required clock entry for imx6sx-pcie,
            imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
+      - description: PCIe reference clock.
 
   clock-names:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   interrupts:
     items:
@@ -127,7 +128,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
@@ -140,11 +141,10 @@ allOf:
         compatible:
           enum:
             - fsl,imx8mq-pcie
-            - fsl,imx95-pcie
     then:
       properties:
         clocks:
-          minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
@@ -200,6 +200,23 @@ allOf:
             - const: mstr
             - const: slv
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx95-pcie
+    then:
+      properties:
+        clocks:
+          maxItems: 5
+        clock-names:
+          items:
+            - const: pcie
+            - const: pcie_bus
+            - const: pcie_phy
+            - const: pcie_aux
+            - const: ref
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt b/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt
deleted file mode 100644
index b40fb5d15d3..00000000000
--- a/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-NXP Layerscape PCIe Gen4 controller
-
-This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
-the common properties defined in mobiveil-pcie.txt.
-
-Required properties:
-- compatible: should contain the platform identifier such as:
-  "fsl,lx2160a-pcie"
-- reg: base addresses and lengths of the PCIe controller register blocks.
-  "csr_axi_slave": Bridge config registers
-  "config_axi_slave": PCIe controller registers
-- interrupts: A list of interrupt outputs of the controller. Must contain an
-  entry for each entry in the interrupt-names property.
-- interrupt-names: It could include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
-  "aer": Asserted for aer interrupt when chip support the aer interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
-  "pme": Asserted for pme interrupt when chip support the pme interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
-- dma-coherent: Indicates that the hardware IP block can ensure the coherency
-  of the data transferred from/to the IP block. This can avoid the software
-  cache flush/invalid actions, and improve the performance significantly.
-- msi-parent : See the generic MSI binding described in
-  Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-
-Example:
-
-	pcie@3400000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
-		reg-names = "csr_axi_slave", "config_axi_slave";
-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "aer", "pme", "intr";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		apio-wins = <8>;
-		ppio-wins = <8>;
-		dma-coherent;
-		bus-range = <0x0 0xff>;
-		msi-parent = <&its>;
-		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-	};
diff --git a/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml b/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml
new file mode 100644
index 00000000000..d286b77921e
--- /dev/null
+++ b/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobiveil AXI PCIe Host Bridge
+
+maintainers:
+  - Frank Li <Frank Li@nxp.com>
+
+description:
+  Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
+  has up to 8 outbound and inbound windows for address translation.
+
+  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
+
+properties:
+  compatible:
+    enum:
+      - fsl,lx2160a-pcie
+      - mbvl,gpex40-pcie
+
+  reg:
+    items:
+      - description: PCIe controller registers
+      - description: Bridge config registers
+      - description: GPIO registers to control slot power
+      - description: MSI registers
+    minItems: 2
+
+  reg-names:
+    items:
+      - const: csr_axi_slave
+      - const: config_axi_slave
+      - const: gpio_slave
+      - const: apb_csr
+    minItems: 2
+
+  apio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      number of requested APIO outbound windows
+        1. Config window
+        2. Memory window
+    default: 2
+    maximum: 256
+
+  ppio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: number of requested PPIO inbound windows
+    default: 1
+    maximum: 256
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 3
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 3
+
+  dma-coherent: true
+
+  msi-parent: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+allOf:
+  - $ref: /schemas/pci/pci-host-bridge.yaml#
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,lx2160a-pcie
+    then:
+      properties:
+        reg:
+          maxItems: 2
+
+        reg-names:
+          maxItems: 2
+
+        interrupts:
+          minItems: 3
+
+        interrupt-names:
+          items:
+            - const: aer
+            - const: pme
+            - const: intr
+    else:
+      properties:
+        dma-coherent: false
+        msi-parent: false
+        interrupts:
+          maxItems: 1
+        interrupt-names: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pcie@b0000000 {
+        compatible = "mbvl,gpex40-pcie";
+        reg = <0xb0000000 0x00010000>,
+              <0xa0000000 0x00001000>,
+              <0xff000000 0x00200000>,
+              <0xb0010000 0x00001000>;
+        reg-names = "csr_axi_slave",
+                    "config_axi_slave",
+                    "gpio_slave",
+                    "apb_csr";
+        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        apio-wins = <2>;
+        ppio-wins = <1>;
+        bus-range = <0x00 0xff>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0 0 0 0 &pci_express 0>,
+                        <0 0 0 1 &pci_express 1>,
+                        <0 0 0 2 &pci_express 2>,
+                        <0 0 0 3 &pci_express 3>;
+    };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@3400000 {
+            compatible = "fsl,lx2160a-pcie";
+            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+            reg-names = "csr_axi_slave", "config_axi_slave";
+            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+            interrupt-names = "aer", "pme", "intr";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            apio-wins = <8>;
+            ppio-wins = <8>;
+            dma-coherent;
+            bus-range = <0x00 0xff>;
+            msi-parent = <&its>;
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 7>;
+            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
index 2e154756970..103574d18db 100644
--- a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
+++ b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
@@ -50,6 +50,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-coherent: true
+
   ranges:
     minItems: 1
     maxItems: 3
diff --git a/dts/upstream/Bindings/pci/mobiveil-pcie.txt b/dts/upstream/Bindings/pci/mobiveil-pcie.txt
deleted file mode 100644
index 64156993e05..00000000000
--- a/dts/upstream/Bindings/pci/mobiveil-pcie.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-* Mobiveil AXI PCIe Root Port Bridge DT description
-
-Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
-has up to 8 outbound and inbound windows for the address translation.
-
-Required properties:
-- #address-cells: Address representation for root ports, set to <3>
-- #size-cells: Size representation for root ports, set to <2>
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- compatible: Should contain "mbvl,gpex40-pcie"
-- reg: Should contain PCIe registers location and length
-	Mandatory:
-	"config_axi_slave": PCIe controller registers
-	"csr_axi_slave"	  : Bridge config registers
-	Optional:
-	"gpio_slave"	  : GPIO registers to control slot power
-	"apb_csr"	  : MSI registers
-
-- device_type: must be "pci"
-- apio-wins : number of requested apio outbound windows
-		default 2 outbound windows are configured -
-		1. Config window
-		2. Memory window
-- ppio-wins : number of requested ppio inbound windows
-		default 1 inbound memory window is configured.
-- bus-range: PCI bus numbers covered
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- interrupts: The interrupt line of the PCIe controller
-		last cell of this field is set to 4 to
-		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
-- interrupt-map-mask,
-	interrupt-map: standard PCI properties to define the mapping of the
-	PCI interface to interrupt numbers.
-- ranges: ranges for the PCI memory regions (I/O space region is not
-	supported by hardware)
-	Please refer to the standard PCI bus binding document for a more
-	detailed explanation
-
-
-Example:
-++++++++
-	pcie0: pcie@a0000000 {
-		#address-cells = <3>;
-		#size-cells = <2>;
-		compatible = "mbvl,gpex40-pcie";
-		reg =	<0xa0000000 0x00001000>,
-			<0xb0000000 0x00010000>,
-			<0xff000000 0x00200000>,
-			<0xb0010000 0x00001000>;
-		reg-names =	"config_axi_slave",
-				"csr_axi_slave",
-				"gpio_slave",
-				"apb_csr";
-		device_type = "pci";
-		apio-wins = <2>;
-		ppio-wins = <1>;
-		bus-range = <0x00000000 0x000000ff>;
-		interrupt-controller;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <1>;
-		interrupts = < 0 89 4 >;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 0 &pci_express 0>,
-				<0 0 0 1 &pci_express 1>,
-				<0 0 0 2 &pci_express 2>,
-				<0 0 0 3 &pci_express 3>;
-		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
-
-	};
diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
index 2b5498a35dc..dbce671ba01 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
@@ -57,9 +57,10 @@ properties:
 
   interrupts:
     minItems: 8
-    maxItems: 8
+    maxItems: 9
 
   interrupt-names:
+    minItems: 8
     items:
       - const: msi0
       - const: msi1
@@ -69,6 +70,7 @@ properties:
       - const: msi5
       - const: msi6
       - const: msi7
+      - const: global
 
   resets:
     minItems: 1
@@ -139,9 +141,10 @@ examples:
                          <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                          <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                          <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "msi0", "msi1", "msi2", "msi3",
-                              "msi4", "msi5", "msi6", "msi7";
+                              "msi4", "msi5", "msi6", "msi7", "global";
             #interrupt-cells = <1>;
             interrupt-map-mask = <0 0 0 0x7>;
             interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
diff --git a/dts/upstream/Bindings/pci/qcom,pcie.yaml b/dts/upstream/Bindings/pci/qcom,pcie.yaml
index bd87f6b49d6..7235d6554cf 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie.yaml
@@ -32,6 +32,10 @@ properties:
           - qcom,pcie-sdm845
           - qcom,pcie-sdx55
       - items:
+          - enum:
+              - qcom,pcie-ipq5424
+          - const: qcom,pcie-ipq9574
+      - items:
           - const: qcom,pcie-msm8998
           - const: qcom,pcie-msm8996
 
diff --git a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
index 989fb0fa257..b63a759ec2d 100644
--- a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
+++ b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - xlnx,versal-cpm-host-1.00
       - xlnx,versal-cpm5-host
+      - xlnx,versal-cpm5-host1
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml b/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
index d3cd7997879..1b3de6678c0 100644
--- a/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-naneng-combphy
+      - rockchip,rk3576-naneng-combphy
       - rockchip,rk3588-naneng-combphy
 
   reg:
diff --git a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 58ce2d91d28..f6080468741 100644
--- a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -15,12 +15,21 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,ipq6018-qmp-pcie-phy
-      - qcom,ipq8074-qmp-gen3-pcie-phy
-      - qcom,ipq8074-qmp-pcie-phy
-      - qcom,ipq9574-qmp-gen3x1-pcie-phy
-      - qcom,ipq9574-qmp-gen3x2-pcie-phy
+    oneOf:
+      - enum:
+          - qcom,ipq6018-qmp-pcie-phy
+          - qcom,ipq8074-qmp-gen3-pcie-phy
+          - qcom,ipq8074-qmp-pcie-phy
+          - qcom,ipq9574-qmp-gen3x1-pcie-phy
+          - qcom,ipq9574-qmp-gen3x2-pcie-phy
+      - items:
+          - enum:
+              - qcom,ipq5424-qmp-gen3x1-pcie-phy
+          - const: qcom,ipq9574-qmp-gen3x1-pcie-phy
+      - items:
+          - enum:
+              - qcom,ipq5424-qmp-gen3x2-pcie-phy
+          - const: qcom,ipq9574-qmp-gen3x2-pcie-phy
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml b/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
index 4aed4b5d65e..39851ba9de4 100644
--- a/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
@@ -18,6 +18,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - qcom,ipq5424-qusb2-phy
               - qcom,ipq6018-qusb2-phy
               - qcom,ipq8074-qusb2-phy
               - qcom,ipq9574-qusb2-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 13fdf5f1beb..89391649e0b 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -16,8 +16,10 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,qcs615-qmp-gen3x1-pcie-phy
       - qcom,sa8775p-qmp-gen4x2-pcie-phy
       - qcom,sa8775p-qmp-gen4x4-pcie-phy
+      - qcom,sar2130p-qmp-gen3x2-pcie-phy
       - qcom,sc8180x-qmp-pcie-phy
       - qcom,sc8280xp-qmp-gen3x1-pcie-phy
       - qcom,sc8280xp-qmp-gen3x2-pcie-phy
@@ -32,6 +34,7 @@ properties:
       - qcom,sm8250-qmp-gen3x2-pcie-phy
       - qcom,sm8250-qmp-modem-pcie-phy
       - qcom,sm8350-qmp-gen3x1-pcie-phy
+      - qcom,sm8350-qmp-gen3x2-pcie-phy
       - qcom,sm8450-qmp-gen3x1-pcie-phy
       - qcom,sm8450-qmp-gen4x2-pcie-phy
       - qcom,sm8550-qmp-gen3x2-pcie-phy
@@ -139,6 +142,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,sar2130p-qmp-gen3x2-pcie-phy
               - qcom,sc8180x-qmp-pcie-phy
               - qcom,sdm845-qhp-pcie-phy
               - qcom,sdm845-qmp-pcie-phy
@@ -149,6 +153,7 @@ allOf:
               - qcom,sm8250-qmp-gen3x2-pcie-phy
               - qcom,sm8250-qmp-modem-pcie-phy
               - qcom,sm8350-qmp-gen3x1-pcie-phy
+              - qcom,sm8350-qmp-gen3x2-pcie-phy
               - qcom,sm8450-qmp-gen3x1-pcie-phy
               - qcom,sm8450-qmp-gen3x2-pcie-phy
               - qcom,sm8550-qmp-gen3x2-pcie-phy
@@ -167,6 +172,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs615-qmp-gen3x1-pcie-phy
               - qcom,sc8280xp-qmp-gen3x1-pcie-phy
               - qcom,sc8280xp-qmp-gen3x2-pcie-phy
               - qcom,sc8280xp-qmp-gen3x4-pcie-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index baf5134ea3d..a1b55168e05 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq5424-qmp-usb3-phy
       - qcom,ipq6018-qmp-usb3-phy
       - qcom,ipq8074-qmp-usb3-phy
       - qcom,ipq9574-qmp-usb3-phy
@@ -89,6 +90,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq5424-qmp-usb3-phy
               - qcom,ipq6018-qmp-usb3-phy
               - qcom,ipq8074-qmp-usb3-phy
               - qcom,ipq9574-qmp-usb3-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 2d0d7e9e643..358a6736a95 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,sar2130p-qmp-usb3-dp-phy
       - qcom,sc7180-qmp-usb3-dp-phy
       - qcom,sc7280-qmp-usb3-dp-phy
       - qcom,sc8180x-qmp-usb3-dp-phy
@@ -127,6 +128,7 @@ allOf:
       properties:
         compatible:
           enum:
+            - qcom,sar2130p-qmp-usb3-dp-phy
             - qcom,sc8280xp-qmp-usb43dp-phy
             - qcom,sm6350-qmp-usb3-dp-phy
             - qcom,sm8550-qmp-usb3-dp-phy
diff --git a/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 45024057031..990b7876542 100644
--- a/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -44,6 +44,7 @@ properties:
       - allwinner,sun8i-r40-pinctrl
       - allwinner,sun8i-v3-pinctrl
       - allwinner,sun8i-v3s-pinctrl
+      - allwinner,sun8i-v853-pinctrl
       - allwinner,sun9i-a80-pinctrl
       - allwinner,sun9i-a80-r-pinctrl
       - allwinner,sun20i-d1-pinctrl
@@ -183,6 +184,18 @@ allOf:
       properties:
         compatible:
           enum:
+            - allwinner,sun8i-v853-pinctrl
+
+    then:
+      properties:
+        interrupts:
+          minItems: 8
+          maxItems: 8
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - allwinner,sun20i-d1-pinctrl
 
     then:
diff --git a/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
index 1bb386b4203..a7ede29c144 100644
--- a/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
@@ -145,40 +145,40 @@ additionalProperties:
 
 examples:
   - |
-     #include <dt-bindings/clock/at91.h>
-     #include <dt-bindings/interrupt-controller/irq.h>
-     #include <dt-bindings/pinctrl/at91.h>
-
-     pinctrl@fffff400 {
-       #address-cells = <1>;
-       #size-cells = <1>;
-       compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
-       ranges = <0xfffff400 0xfffff400 0x600>;
-
-       atmel,mux-mask = <
-         /*    A         B     */
-         0xffffffff 0xffc00c3b  /* pioA */
-         0xffffffff 0x7fff3ccf  /* pioB */
-         0xffffffff 0x007fffff  /* pioC */
-         >;
-
-       dbgu {
-         pinctrl_dbgu: dbgu-0 {
-           atmel,pins =
-             <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-              AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
-         };
-       };
-
-       pioA: gpio@fffff400 {
-         compatible = "atmel,at91rm9200-gpio";
-         reg = <0xfffff400 0x200>;
-         interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-         #gpio-cells = <2>;
-         gpio-controller;
-         interrupt-controller;
-         #interrupt-cells = <2>;
-         clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
-       };
-     };
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/pinctrl/at91.h>
+
+    pinctrl@fffff400 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
+        ranges = <0xfffff400 0xfffff400 0x600>;
+
+        atmel,mux-mask = <
+          /*    A         B     */
+          0xffffffff 0xffc00c3b  /* pioA */
+          0xffffffff 0x7fff3ccf  /* pioB */
+          0xffffffff 0x007fffff  /* pioC */
+          >;
+
+        dbgu {
+            dbgu-0 {
+                atmel,pins =
+                  <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                   AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+            };
+        };
+
+        gpio@fffff400 {
+            compatible = "atmel,at91rm9200-gpio";
+            reg = <0xfffff400 0x200>;
+            interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+            #gpio-cells = <2>;
+            gpio-controller;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+            clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
new file mode 100644
index 00000000000..26dfe7e7735
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
@@ -0,0 +1,575 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7988 Pin Controller
+
+maintainers:
+  - Sean Wang <sean.wang@kernel.org>
+
+description:
+  The MediaTek's MT7988 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt7988-pinctrl
+
+  reg:
+    minItems: 7
+    maxItems: 7
+
+  reg-names:
+    items:
+      - const: gpio
+      - const: iocfg_tr
+      - const: iocfg_br
+      - const: iocfg_rb
+      - const: iocfg_lb
+      - const: iocfg_tl
+      - const: eint
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+  gpio-ranges:
+    minItems: 1
+    maxItems: 5
+    description:
+      GPIO valid number range.
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 2
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - gpio-controller
+  - "#gpio-cells"
+
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    properties:
+      mux:
+        type: object
+        additionalProperties: false
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+        description: |
+          pinmux configuration nodes.
+
+          The following table shows the effective values of "group", "function"
+          properties and chip pinout pins
+
+          groups               function           pins (in pin#)
+          ---------------------------------------------------------------------
+          "tops_jtag0_0"       "jtag"             0, 1, 2, 3, 4
+          "wo0_jtag"           "jtag"             50, 51, 52, 53, 54
+          "wo1_jtag"           "jtag"             50, 51, 52, 53, 54
+          "wo2_jtag"           "jtag"             50, 51, 52, 53, 54
+          "jtag"               "jtag"             58, 59, 60, 61, 62
+          "tops_jtag0_1"       "jtag"             58, 59, 60, 61, 62
+          "int_usxgmii"        "int_usxgmii"      2, 3
+          "pwm0"               "pwm"              57
+          "pwm1"               "pwm"              21
+          "pwm2"               "pwm"              80
+          "pwm2_0"             "pwm"              58
+          "pwm3"               "pwm"              81
+          "pwm3_0"             "pwm"              59
+          "pwm4"               "pwm"              82
+          "pwm4_0"             "pwm"              60
+          "pwm5"               "pwm"              83
+          "pwm5_0"             "pwm"              61
+          "pwm6"               "pwm"              69
+          "pwm6_0"             "pwm"              62
+          "pwm7"               "pwm"              70
+          "pwm7_0"             "pwm"              4
+          "dfd"                "dfd"              0, 1, 2, 3, 4
+          "xfi_phy0_i2c0"      "i2c"              0, 1
+          "xfi_phy1_i2c0"      "i2c"              0, 1
+          "xfi_phy_pll_i2c0"   "i2c"              3, 4
+          "xfi_phy_pll_i2c1"   "i2c"              3, 4
+          "i2c0_0"             "i2c"              5, 6
+          "i2c1_sfp"           "i2c"              5, 6
+          "xfi_pextp_phy0_i2c" "i2c"              5, 6
+          "xfi_pextp_phy1_i2c" "i2c"              5, 6
+          "i2c0_1"             "i2c"              15, 16
+          "u30_phy_i2c0"       "i2c"              15, 16
+          "u32_phy_i2c0"       "i2c"              15, 16
+          "xfi_phy0_i2c1"      "i2c"              15, 16
+          "xfi_phy1_i2c1"      "i2c"              15, 16
+          "xfi_phy_pll_i2c2"   "i2c"              15, 16
+          "i2c1_0"             "i2c"              17, 18
+          "u30_phy_i2c1"       "i2c"              17, 18
+          "u32_phy_i2c1"       "i2c"              17, 18
+          "xfi_phy_pll_i2c3"   "i2c"              17, 18
+          "sgmii0_i2c"         "i2c"              17, 18
+          "sgmii1_i2c"         "i2c"              17, 18
+          "i2c1_2"             "i2c"              69, 70
+          "i2c2_0"             "i2c"              69, 70
+          "i2c2_1"             "i2c"              71, 72
+          "mdc_mdio0"          "eth"              5, 6
+          "2p5g_ext_mdio"      "eth"              28, 29
+          "gbe_ext_mdio"       "eth"              30, 31
+          "mdc_mdio1"          "eth"              69, 70
+          "pcie_wake_n0_0"     "pcie"             7
+          "pcie_clk_req_n0_0"  "pcie"             8
+          "pcie_wake_n3_0"     "pcie"             9
+          "pcie_clk_req_n3"    "pcie"             10
+          "pcie_clk_req_n0_1"  "pcie"             10
+          "pcie_p0_phy_i2c"    "pcie"             7, 8
+          "pcie_p1_phy_i2c"    "pcie"             7, 8
+          "pcie_p3_phy_i2c"    "pcie"             9, 10
+          "pcie_p2_phy_i2c"    "pcie"             7, 8
+          "ckm_phy_i2c"        "pcie"             9, 10
+          "pcie_wake_n0_1"     "pcie"             13
+          "pcie_wake_n3_1"     "pcie"             14
+          "pcie_2l_0_pereset"  "pcie"             19
+          "pcie_1l_1_pereset"  "pcie"             20
+          "pcie_clk_req_n2_1"  "pcie"             63
+          "pcie_2l_1_pereset"  "pcie"             73
+          "pcie_1l_0_pereset"  "pcie"             74
+          "pcie_wake_n1_0"     "pcie"             75
+          "pcie_clk_req_n1"    "pcie"             76
+          "pcie_wake_n2_0"     "pcie"             77
+          "pcie_clk_req_n2_0"  "pcie"             78
+          "pcie_wake_n2_1"     "pcie"             79
+          "pmic"               "pmic"             11
+          "watchdog"           "watchdog"         12
+          "spi0_wp_hold"       "spi"              22, 23
+          "spi0"               "spi"              24, 25, 26, 27
+          "spi1"               "spi"              28, 29, 30, 31
+          "spi2"               "spi"              32, 33, 34, 35
+          "spi2_wp_hold"       "spi"              36, 37
+          "snfi"               "flash"            22, 23, 24, 25, 26, 27
+          "emmc_45"            "flash"            21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
+          "sdcard"             "flash"            32, 33, 34, 35, 36, 37
+          "emmc_51"            "flash"            38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49
+          "uart2"              "uart"             0, 1, 2, 3
+          "tops_uart0_0"       "uart"             22, 23
+          "uart2_0"            "uart"             28, 29, 30, 31
+          "uart1_0"            "uart"             32, 33, 34, 35
+          "uart2_1"            "uart"             32, 33, 34, 35
+          "net_wo0_uart_txd_0" "uart"             28
+          "net_wo1_uart_txd_0" "uart"             29
+          "net_wo2_uart_txd_0" "uart"             30
+          "tops_uart1_0"       "uart"             28, 29
+          "tops_uart0_1"       "uart"             30, 31
+          "tops_uart1_1"       "uart"             36, 37
+          "uart0"              "uart"             55, 56
+          "tops_uart0_2"       "uart"             55, 56
+          "uart2_2"            "uart"             50, 51, 52, 53
+          "uart1_1"            "uart"             58, 59, 60, 61
+          "uart2_3"            "uart"             58, 59, 60, 61
+          "uart1_2"            "uart"             80, 81, 82, 83
+          "uart1_2_lite"       "uart"             80, 81
+          "tops_uart1_2"       "uart"             80, 81
+          "net_wo0_uart_txd_1" "uart"             80
+          "net_wo1_uart_txd_1" "uart"             81
+          "net_wo2_uart_txd_1" "uart"             82
+          "udi"                "udi"              32, 33, 34, 35, 36
+          "i2s"                "audio"            50, 51, 52, 53, 54
+          "pcm"                "audio"            50, 51, 52, 53
+          "gbe0_led1"          "led"              58
+          "gbe1_led1"          "led"              59
+          "gbe2_led1"          "led"              60
+          "gbe3_led1"          "led"              61
+          "2p5gbe_led1"        "led"              62
+          "gbe0_led0"          "led"              64
+          "gbe1_led0"          "led"              65
+          "gbe2_led0"          "led"              66
+          "gbe3_led0"          "led"              67
+          "2p5gbe_led0"        "led"              68
+          "drv_vbus_p1"        "usb"              63
+          "drv_vbus"           "usb"              79
+
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi,
+                   uart, udi, usb, watchdog]
+          groups:
+            description:
+              An array of strings. Each string contains the name of a group.
+
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: audio
+            then:
+              properties:
+                groups:
+                  enum: [i2s, pcm]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag]
+          - if:
+              properties:
+                function:
+                  const: int_usxgmii
+            then:
+              properties:
+                groups:
+                  const: int_usxgmii
+          - if:
+              properties:
+                function:
+                  const: dfd
+            then:
+              properties:
+                groups:
+                  const: dfd
+          - if:
+              properties:
+                function:
+                  const: flash
+            then:
+              properties:
+                groups:
+                  enum: [emmc_45, emmc_51, sdcard, snfi]
+          - if:
+              properties:
+                function:
+                  const: eth
+            then:
+              properties:
+                groups:
+                  enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1]
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0,
+                         xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c,
+                         xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0,
+                         xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0,
+                         u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c,
+                         sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1]
+          - if:
+              properties:
+                function:
+                  const: led
+            then:
+              properties:
+                groups:
+                  enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1,
+                         gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1]
+          - if:
+              properties:
+                function:
+                  const: pcie
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0,
+                           pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c,
+                           pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c,
+                           pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset,
+                           pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset,
+                           pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1,
+                           pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1,
+                           pcie_clk_req_n0_1]
+                  maxItems: 3
+          - if:
+              properties:
+                function:
+                  const: pmic
+            then:
+              properties:
+                groups:
+                  const: pmic
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0,
+                           pwm6, pwm6_0, pwm7, pwm7_0]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0,
+                           net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1,
+                           tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0,
+                           tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2,
+                           uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: watchdog
+            then:
+              properties:
+                groups:
+                  const: watchdog
+          - if:
+              properties:
+                function:
+                  const: udi
+            then:
+              properties:
+                groups:
+                  const: udi
+          - if:
+              properties:
+                function:
+                  const: usb
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [drv_vbus, drv_vbus_p1]
+                  maxItems: 1
+
+    patternProperties:
+      '^conf(-[-a-z]*)?$':
+        type: object
+        additionalProperties: false
+        description:
+          pinconf configuration nodes.
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC,
+                     SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N,
+                     PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG,
+                     GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL,
+                     I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1,
+                     SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK,
+                     SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI,
+                     SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL,
+                     EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5,
+                     EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1,
+                     EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK,
+                     PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK,
+                     UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS,
+                     JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C,
+                     LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA,
+                     PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N,
+                     PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N,
+                     PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0,
+                     UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS]
+            maxItems: 84
+
+          bias-disable: true
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+                description: normal pull up.
+              - enum: [100, 101, 102, 103]
+                description:
+                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
+                  dt-bindings/pinctrl/mt65xx.h.
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+                description: normal pull down.
+              - enum: [100, 101, 102, 103]
+                description:
+                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
+                  dt-bindings/pinctrl/mt65xx.h.
+
+          input-enable: true
+
+          input-disable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+          drive-strength:
+            enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+          mediatek,pull-up-adv:
+            description: |
+              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
+              Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
+              are described as below:
+              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+          mediatek,pull-down-adv:
+            description: |
+              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
+              Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
+              are described as below:
+              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+        required:
+          - pins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/pinctrl/mt65xx.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pio: pinctrl@1001f000 {
+        compatible = "mediatek,mt7988-pinctrl";
+        reg = <0 0x1001f000 0 0x1000>,
+        <0 0x11c10000 0 0x1000>,
+        <0 0x11d00000 0 0x1000>,
+        <0 0x11d20000 0 0x1000>,
+        <0 0x11e00000 0 0x1000>,
+        <0 0x11f00000 0 0x1000>,
+        <0 0x1000b000 0 0x1000>;
+        reg-names = "gpio", "iocfg_tr",
+          "iocfg_br", "iocfg_rb",
+          "iocfg_lb", "iocfg_tl", "eint";
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 0 84>;
+        interrupt-controller;
+        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-parent = <&gic>;
+        #interrupt-cells = <2>;
+
+        i2c0_pins: i2c0-g0-pins {
+          mux {
+            function = "i2c";
+            groups = "i2c0_1";
+          };
+        };
+
+        mdio0_pins: mdio0-pins {
+          mux {
+            function = "eth";
+            groups = "mdc_mdio0";
+          };
+
+          conf {
+            pins = "SMI_0_MDC", "SMI_0_MDIO";
+            drive-strength = <8>;
+          };
+        };
+
+        mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+          mux {
+            function = "flash";
+            groups = "emmc_51";
+          };
+        };
+
+        mmc0_pins_sdcard: mmc0-sdcard-pins {
+          mux {
+            function = "flash";
+            groups = "sdcard";
+          };
+        };
+
+        pcie0_pins: pcie0-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+                     "pcie_wake_n0_0";
+          };
+        };
+
+        pcie1_pins: pcie1-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+                     "pcie_wake_n1_0";
+          };
+        };
+
+        pcie2_pins: pcie2-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+                     "pcie_wake_n2_0";
+          };
+        };
+
+        pcie3_pins: pcie3-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+                     "pcie_wake_n3_0";
+          };
+        };
+
+        uart0_pins: uart0-pins {
+          mux {
+            function = "uart";
+            groups =  "uart0";
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
index 5e64a232fc7..df284d3645c 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
@@ -79,8 +79,8 @@ $defs:
                 qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
                 qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
                 qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
-                sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1,
-                wci_txd, wci_rxd, wsi_clk, wsi_data ]
+                sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
+                spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
 
     required:
       - pins
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml
new file mode 100644
index 00000000000..16d0c010e58
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8917 TLMM pin controller
+
+maintainers:
+  - Barnabas Czeman <barnabas.czeman@mainlining.org>
+
+description:
+  Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC.
+
+properties:
+  compatible:
+    const: qcom,msm8917-pinctrl
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 66
+
+  gpio-line-names:
+    maxItems: 134
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-msm8917-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-msm8917-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-msm8917-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$"
+            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
+                      sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
+                      qdsd_data1, qdsd_data2, qdsd_data3 ]
+        minItems: 1
+        maxItems: 16
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
+                atest_char, atest_char0, atest_char1, atest_char2,
+                atest_char3, atest_combodac_to_gpio_native,
+                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native,
+                atest_tsens, atest_wlan0, atest_wlan1, audio_ref,
+                audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi,
+                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
+                blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2,
+                blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
+                blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4,
+                blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo,
+                cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk,
+                cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0,
+                codec_int1, codec_int2, codec_mad, coex_uart, cri_trng,
+                cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data,
+                ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int,
+                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
+                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio,
+                gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en,
+                ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1,
+                m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps,
+                nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo,
+                pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a,
+                pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc,
+                pwr_crypto_enabled_a, pwr_crypto_enabled_b,
+                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
+                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
+                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
+                qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det,
+                sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst,
+                smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk,
+                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
+                uim2_present, uim2_reset, uim_batt, us_emitter, us_euro,
+                wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1,
+                wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ]
+
+    required:
+      - pins
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tlmm: pinctrl@1000000 {
+        compatible = "qcom,msm8917-pinctrl";
+        reg = <0x01000000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        gpio-ranges = <&tlmm 0 0 134>;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+
+        blsp1-uart2-sleep-state {
+            pins = "gpio4", "gpio5";
+            function = "gpio";
+
+            drive-strength = <2>;
+            bias-pull-down;
+        };
+
+        spi1-default-state {
+            spi-pins {
+                pins = "gpio0", "gpio1", "gpio3";
+                function = "blsp_spi1";
+
+                drive-strength = <12>;
+                bias-disable;
+            };
+
+            cs-pins {
+                pins = "gpio2";
+                function = "gpio";
+
+                drive-strength = <16>;
+                bias-disable;
+                output-high;
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
index fc6c65fea73..90bd49d87d2 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
@@ -159,30 +159,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1315e-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1315e-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
index f07361d60ac..b6211c8544c 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
@@ -158,30 +158,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1319d-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1319d-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
index 671e4ec8462..e88bc649cc7 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
@@ -157,30 +157,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1619b-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1619b-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index a1805b6e3f6..768bb3c2b45 100644
--- a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
               - renesas,r9a08g045-pinctrl # RZ/G3S
+              - renesas,r9a09g047-pinctrl # RZ/G3E
               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 
       - items:
@@ -125,7 +126,7 @@ additionalProperties:
         drive-push-pull: true
         renesas,output-impedance:
           description:
-            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
             property corresponds to register bit values that can be set in the PFC_IOLH_mn
             register, which adjusts the drive strength value and is pin-dependent.
           $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g057-pinctrl
+            enum:
+              - renesas,r9a09g047-pinctrl
+              - renesas,r9a09g057-pinctrl
     then:
       properties:
         resets:
diff --git a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
index 6a23d845f1f..80a2b193484 100644
--- a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
@@ -44,6 +44,7 @@ properties:
       - rockchip,rk3328-pinctrl
       - rockchip,rk3368-pinctrl
       - rockchip,rk3399-pinctrl
+      - rockchip,rk3562-pinctrl
       - rockchip,rk3568-pinctrl
       - rockchip,rk3576-pinctrl
       - rockchip,rk3588-pinctrl
diff --git a/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml b/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
index de6c10ba36c..70548cb37ad 100644
--- a/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
+++ b/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
@@ -180,38 +180,31 @@ additionalProperties: false
 examples:
   - |
     #include <dt-bindings/pinctrl/pinctrl-zynq.h>
-    pinctrl0: pinctrl@700 {
-       compatible = "xlnx,pinctrl-zynq";
-       reg = <0x700 0x200>;
-       syscon = <&slcr>;
-
-       pinctrl_uart1_default: uart1-default {
-           mux {
-               groups = "uart1_10_grp";
-               function = "uart1";
-           };
-
-           conf {
-               groups = "uart1_10_grp";
-               slew-rate = <0>;
-               power-source = <IO_STANDARD_LVCMOS18>;
-           };
-
-           conf-rx {
-               pins = "MIO49";
-               bias-high-impedance;
-           };
-
-           conf-tx {
-               pins = "MIO48";
-               bias-disable;
-           };
-       };
+    pinctrl@700 {
+        compatible = "xlnx,pinctrl-zynq";
+        reg = <0x700 0x200>;
+        syscon = <&slcr>;
+
+        uart1-default {
+            mux {
+                groups = "uart1_10_grp";
+                function = "uart1";
+            };
+
+            conf {
+                groups = "uart1_10_grp";
+                slew-rate = <0>;
+                power-source = <IO_STANDARD_LVCMOS18>;
+            };
+
+            conf-rx {
+                pins = "MIO49";
+                bias-high-impedance;
+            };
+
+            conf-tx {
+                pins = "MIO48";
+                bias-disable;
+            };
+        };
     };
-
-    uart1 {
-         pinctrl-names = "default";
-         pinctrl-0 = <&pinctrl_uart1_default>;
-    };
-
-...
diff --git a/dts/upstream/Bindings/power/domain-idle-state.yaml b/dts/upstream/Bindings/power/domain-idle-state.yaml
index ec1f6f669e5..4dd4f59bbbe 100644
--- a/dts/upstream/Bindings/power/domain-idle-state.yaml
+++ b/dts/upstream/Bindings/power/domain-idle-state.yaml
@@ -54,6 +54,11 @@ patternProperties:
           (i.e. idle states node with entry-method property is set to "psci")
           must specify this property.
 
+      idle-state-name:
+        $ref: /schemas/types.yaml#/definitions/string
+        description:
+          A string used as a descriptive name for the idle state.
+
     required:
       - compatible
       - entry-latency-us
diff --git a/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml b/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml
new file mode 100644
index 00000000000..57579f70264
--- /dev/null
+++ b/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/raspberrypi,bcm2835-power.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 power domain
+
+maintainers:
+  - Alexander Aring <alex.aring@gmail.com>
+  - Florian Fainelli <florian.fainelli@broadcom.com>
+
+description:
+  The Raspberry Pi power domain manages power for various subsystems
+  in the Raspberry Pi BCM2835 SoC.
+
+properties:
+  compatible:
+    enum:
+      - raspberrypi,bcm2835-power
+
+  firmware:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Reference to the RPi firmware device node
+
+  "#power-domain-cells":
+    const: 1
+
+required:
+  - compatible
+  - firmware
+  - "#power-domain-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    power-controller {
+      compatible = "raspberrypi,bcm2835-power";
+      firmware = <&firmware>;
+      #power-domain-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml b/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb6..0735ceb7c10 100644
--- a/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -22,6 +22,9 @@ properties:
       - enum:
           - atmel,sama5d2-shdwc
           - microchip,sam9x60-shdwc
+      - items:
+          - const: microchip,sam9x7-shdwc
+          - const: microchip,sam9x60-shdwc
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/bq24190.yaml b/dts/upstream/Bindings/power/supply/bq24190.yaml
index 131b7e57d22..07adf88997b 100644
--- a/dts/upstream/Bindings/power/supply/bq24190.yaml
+++ b/dts/upstream/Bindings/power/supply/bq24190.yaml
@@ -21,6 +21,7 @@ properties:
       - ti,bq24192i
       - ti,bq24196
       - ti,bq24296
+      - ti,bq24297
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/gpio-charger.yaml b/dts/upstream/Bindings/power/supply/gpio-charger.yaml
index 89f8e2bcb2d..25826bfc289 100644
--- a/dts/upstream/Bindings/power/supply/gpio-charger.yaml
+++ b/dts/upstream/Bindings/power/supply/gpio-charger.yaml
@@ -58,6 +58,10 @@ properties:
             charge-current-limit-gpios property. Bit 1 second to last
             GPIO and so on.
 
+  charge-current-limit-default-microamp:
+    description: Default charge current limit. Must be listed in
+      charge-current-limit-mapping.
+
 required:
   - compatible
 
@@ -72,6 +76,7 @@ anyOf:
 dependencies:
   charge-current-limit-gpios: [ charge-current-limit-mapping ]
   charge-current-limit-mapping: [ charge-current-limit-gpios ]
+  charge-current-limit-default-microamp: [charge-current-limit-mapping]
 
 additionalProperties: false
 
@@ -91,4 +96,5 @@ examples:
       charge-current-limit-mapping = <2500000 0x00>, // 2.5 A => both GPIOs low
                                      <700000 0x01>, // 700 mA => GPIO A.12 high
                                      <0 0x02>; // 0 mA => GPIO A.11 high
+      charge-current-limit-default-microamp = <700000>;
     };
diff --git a/dts/upstream/Bindings/power/supply/ltc4162-l.yaml b/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
index 29d53654115..06595a95365 100644
--- a/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
+++ b/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
@@ -17,12 +17,18 @@ description: |
   panels, etc., and a rechargeable Lithium-Ion/Polymer battery.
 
   Specifications about the charger can be found at:
+    https://www.analog.com/en/products/ltc4162-l.html
+    https://www.analog.com/en/products/ltc4162-f.html
     https://www.analog.com/en/products/ltc4162-s.html
+    https://www.analog.com/en/products/ltc4015.html
 
 properties:
   compatible:
     enum:
+      - lltc,ltc4015
+      - lltc,ltc4162-f
       - lltc,ltc4162-l
+      - lltc,ltc4162-s
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/maxim,max17042.yaml b/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
index 085e2504d0d..14242de7fc0 100644
--- a/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
+++ b/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
@@ -19,6 +19,7 @@ properties:
       - maxim,max17047
       - maxim,max17050
       - maxim,max17055
+      - maxim,max77705-battery
       - maxim,max77849-battery
 
   reg:
diff --git a/dts/upstream/Bindings/power/supply/st,stc3117.yaml b/dts/upstream/Bindings/power/supply/st,stc3117.yaml
new file mode 100644
index 00000000000..e486131a27a
--- /dev/null
+++ b/dts/upstream/Bindings/power/supply/st,stc3117.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/st,stc3117.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STC3117 Fuel Gauge Unit Power Supply
+
+maintainers:
+  - Hardevsinh Palaniya <hardevsinh.palaniya@siliconsignals.io>
+  - Bhavin Sharma <bhavin.sharma@siliconsignals.io>
+
+description: |
+  The STC3117 includes the STMicroelectronics OptimGauge algorithm.
+  It provides accurate battery state-of-charge (SOC) monitoring, tracks
+  battery parameter changes with operation conditions, temperature,
+  and aging, and allows the application to get a battery state-of-health
+  (SOH) indication.
+
+  An alarm output signals low SOC or low voltage conditions and also
+  indicates fault conditions like a missing or swapped battery.
+
+  Datasheet is available at
+  https://www.st.com/resource/en/datasheet/stc3117.pdf
+
+allOf:
+  - $ref: power-supply.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stc3117
+
+  reg:
+    maxItems: 1
+
+  monitored-battery:
+    description: |
+      The fuel gauge uses the following battery properties:
+      - charge-full-design-microamp-hours
+      - voltage-min-design-microvolt
+      - voltage-max-design-microvolt
+
+  shunt-resistor-micro-ohms:
+    description: Current sense resistor
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - monitored-battery
+  - shunt-resistor-micro-ohms
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      battery@70 {
+        compatible = "st,stc3117";
+        reg = <0x70>;
+        interrupt-parent = <&gpio0>;
+        interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+        monitored-battery = <&bat>;
+        shunt-resistor-micro-ohms = <10000>;
+      };
+    };
diff --git a/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
index aa35209f74c..45e112d0efb 100644
--- a/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
+++ b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
@@ -41,8 +41,8 @@ unevaluatedProperties: false
 examples:
   - |
     pwm@44b00000 {
-       compatible = "adi,axi-pwmgen-2.00.a";
-       reg = <0x44b00000 0x1000>;
-       clocks = <&spi_clk>;
-       #pwm-cells = <3>;
+        compatible = "adi,axi-pwmgen-2.00.a";
+        reg = <0x44b00000 0x1000>;
+        clocks = <&spi_clk>;
+        #pwm-cells = <3>;
     };
diff --git a/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml b/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
index 119de3d7f9d..44548a9da15 100644
--- a/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
@@ -35,8 +35,8 @@ additionalProperties: false
 examples:
   - |
     pwm: pwm@f0408000 {
-       compatible = "brcm,bcm7038-pwm";
-       reg = <0xf0408000 0x28>;
-       #pwm-cells = <2>;
-       clocks = <&upg_fixed>;
+        compatible = "brcm,bcm7038-pwm";
+        reg = <0xf0408000 0x28>;
+        #pwm-cells = <2>;
+        clocks = <&upg_fixed>;
     };
diff --git a/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml b/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
index e86c8053b36..fd785da5d3d 100644
--- a/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
@@ -43,9 +43,9 @@ examples:
     #include <dt-bindings/clock/bcm281xx.h>
 
     pwm@3e01a000 {
-       compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
-       reg = <0x3e01a000 0xcc>;
-       clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
-       #pwm-cells = <3>;
+        compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+        reg = <0x3e01a000 0xcc>;
+        clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
+        #pwm-cells = <3>;
     };
 ...
diff --git a/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml b/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml
new file mode 100644
index 00000000000..091fec03df1
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/marvell,berlin-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Berlin PWM controller
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+  - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+properties:
+  compatible:
+    const: marvell,berlin-pwm
+
+  reg:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 3
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+allOf:
+  - $ref: pwm.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pwm@f7f20000 {
+        compatible = "marvell,berlin-pwm";
+        reg = <0xf7f20000 0x40>;
+        clocks = <&chip_clk 12>;
+        #pwm-cells = <3>;
+    };
+
diff --git a/dts/upstream/Bindings/pwm/pwm-berlin.txt b/dts/upstream/Bindings/pwm/pwm-berlin.txt
deleted file mode 100644
index f01e993a498..00000000000
--- a/dts/upstream/Bindings/pwm/pwm-berlin.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Berlin PWM controller
-
-Required properties:
-- compatible: should be "marvell,berlin-pwm"
-- reg: physical base address and length of the controller's registers
-- clocks: phandle to the input clock
-- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
-  the cells format.
-
-Example:
-
-pwm: pwm@f7f20000 {
-	compatible = "marvell,berlin-pwm";
-	reg = <0xf7f20000 0x40>;
-	clocks = <&chip_clk CLKID_CFG>;
-	#pwm-cells = <3>;
-}
diff --git a/dts/upstream/Bindings/pwm/pwm-sprd.txt b/dts/upstream/Bindings/pwm/pwm-sprd.txt
deleted file mode 100644
index 87b206fd061..00000000000
--- a/dts/upstream/Bindings/pwm/pwm-sprd.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Spreadtrum PWM controller
-
-Spreadtrum SoCs PWM controller provides 4 PWM channels.
-
-Required properties:
-- compatible : Should be "sprd,ums512-pwm".
-- reg: Physical base address and length of the controller's registers.
-- clocks: The phandle and specifier referencing the controller's clocks.
-- clock-names: Should contain following entries:
-  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
-  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
-- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
-  the cells format.
-
-Optional properties:
-- assigned-clocks: Reference to the PWM clock entries.
-- assigned-clock-parents: The phandle of the parent clock of PWM clock.
-
-Example:
-	pwms: pwm@32260000 {
-		compatible = "sprd,ums512-pwm";
-		reg = <0 0x32260000 0 0x10000>;
-		clock-names = "pwm0", "enable0",
-			"pwm1", "enable1",
-			"pwm2", "enable2",
-			"pwm3", "enable3";
-		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
-		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
-		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
-		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
-		assigned-clocks = <&aon_clk CLK_PWM0>,
-			<&aon_clk CLK_PWM1>,
-			<&aon_clk CLK_PWM2>,
-			<&aon_clk CLK_PWM3>;
-		assigned-clock-parents = <&ext_26m>,
-			<&ext_26m>,
-			<&ext_26m>,
-			<&ext_26m>;
-		#pwm-cells = <2>;
-	};
diff --git a/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml b/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml
new file mode 100644
index 00000000000..c806b676808
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/sprd,ums512-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum/Unisoc UMS512 PWM Controller
+
+maintainers:
+  - Orson Zhai <orsonzhai@gmail.com>
+  - Baolin Wang <baolin.wang@linux.alibaba.com>
+  - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+  compatible:
+    const: sprd,ums512-pwm
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 8
+
+  clock-names:
+    items:
+      - const: pwm0
+      - const: enable0
+      - const: pwm1
+      - const: enable1
+      - const: pwm2
+      - const: enable2
+      - const: pwm3
+      - const: enable3
+
+  '#pwm-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: pwm.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sprd,ums512-clk.h>
+
+    pwm@32260000 {
+      compatible = "sprd,ums512-pwm";
+      reg = <0x32260000 0x10000>;
+      clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
+               <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
+               <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
+               <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
+      clock-names = "pwm0", "enable0",
+                    "pwm1", "enable1",
+                    "pwm2", "enable2",
+                    "pwm3", "enable3";
+      #pwm-cells = <2>;
+    };
+...
diff --git a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
index cd4aa27218a..fa6743bb269 100644
--- a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
@@ -35,10 +35,6 @@ properties:
         $ref: regulator.yaml#
         unevaluatedProperties: false
 
-        properties:
-          regulator-compatible:
-            pattern: "^vbuck[1-4]$"
-
     additionalProperties: false
 
 required:
@@ -56,7 +52,6 @@ examples:
 
       regulators {
         vbuck1 {
-          regulator-compatible = "vbuck1";
           regulator-min-microvolt = <300000>;
           regulator-max-microvolt = <1193750>;
           regulator-enable-ramp-delay = <256>;
@@ -64,7 +59,6 @@ examples:
         };
 
         vbuck3 {
-          regulator-compatible = "vbuck3";
           regulator-min-microvolt = <300000>;
           regulator-max-microvolt = <1193750>;
           regulator-enable-ramp-delay = <256>;
diff --git a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
index f8057bba747..68709a7dc43 100644
--- a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
@@ -29,6 +29,7 @@ properties:
       - nxp,pca9450b
       - nxp,pca9450c
       - nxp,pca9451a
+      - nxp,pca9452
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
index f2fd2df68a9..b7241ce975b 100644
--- a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
@@ -22,7 +22,7 @@ description:
   Each sub-node is identified using the node's name, with valid values listed
   for each of the pmics below.
 
-  For mp5496, s1, s2
+  For mp5496, s1, s2, l2, l5
 
   For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
   l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22
diff --git a/dts/upstream/Bindings/regulator/regulator.yaml b/dts/upstream/Bindings/regulator/regulator.yaml
index 1ef380d1515..77573bcb6b7 100644
--- a/dts/upstream/Bindings/regulator/regulator.yaml
+++ b/dts/upstream/Bindings/regulator/regulator.yaml
@@ -34,6 +34,9 @@ properties:
   regulator-input-current-limit-microamp:
     description: maximum input current regulator allows
 
+  regulator-power-budget-milliwatt:
+    description: power budget of the regulator
+
   regulator-always-on:
     description: boolean, regulator should never be disabled
     type: boolean
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
index 7fe401a0680..a66007951d5 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
@@ -15,12 +15,25 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,sa8775p-adsp-pas
-      - qcom,sa8775p-cdsp0-pas
-      - qcom,sa8775p-cdsp1-pas
-      - qcom,sa8775p-gpdsp0-pas
-      - qcom,sa8775p-gpdsp1-pas
+    oneOf:
+      - items:
+          - enum:
+              - qcom,qcs8300-adsp-pas
+          - const: qcom,sa8775p-adsp-pas
+      - items:
+          - enum:
+              - qcom,qcs8300-cdsp-pas
+          - const: qcom,sa8775p-cdsp0-pas
+      - items:
+          - enum:
+              - qcom,qcs8300-gpdsp-pas
+          - const: qcom,sa8775p-gpdsp0-pas
+      - enum:
+          - qcom,sa8775p-adsp-pas
+          - qcom,sa8775p-cdsp0-pas
+          - qcom,sa8775p-cdsp1-pas
+          - qcom,sa8775p-gpdsp0-pas
+          - qcom,sa8775p-gpdsp1-pas
 
   reg:
     maxItems: 1
@@ -63,8 +76,9 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-adsp-pas
+          contains:
+            enum:
+              - qcom,sa8775p-adsp-pas
     then:
       properties:
         power-domains:
@@ -79,9 +93,10 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-cdsp0-pas
-            - qcom,sa8775p-cdsp1-pas
+          contains:
+            enum:
+              - qcom,sa8775p-cdsp0-pas
+              - qcom,sa8775p-cdsp1-pas
     then:
       properties:
         power-domains:
@@ -98,9 +113,10 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-gpdsp0-pas
-            - qcom,sa8775p-gpdsp1-pas
+          contains:
+            enum:
+              - qcom,sa8775p-gpdsp0-pas
+              - qcom,sa8775p-gpdsp1-pas
     then:
       properties:
         power-domains:
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
index 758adb06c8d..059cb87b4d6 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm SM6115 Peripheral Authentication Service
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
diff --git a/dts/upstream/Bindings/reset/st,stm32-rcc.txt b/dts/upstream/Bindings/reset/st,stm32-rcc.txt
index 01db3437519..384035e8e60 100644
--- a/dts/upstream/Bindings/reset/st,stm32-rcc.txt
+++ b/dts/upstream/Bindings/reset/st,stm32-rcc.txt
@@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller
 
 The RCC IP is both a reset and a clock controller.
 
-Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
diff --git a/dts/upstream/Bindings/riscv/cpus.yaml b/dts/upstream/Bindings/riscv/cpus.yaml
index 8edc8261241..2c72f148a74 100644
--- a/dts/upstream/Bindings/riscv/cpus.yaml
+++ b/dts/upstream/Bindings/riscv/cpus.yaml
@@ -26,6 +26,18 @@ description: |
 allOf:
   - $ref: /schemas/cpu.yaml#
   - $ref: extensions.yaml
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - thead,c906
+                - thead,c910
+                - thead,c920
+    then:
+      properties:
+        thead,vlenb: false
 
 properties:
   compatible:
@@ -46,6 +58,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c908
               - thead,c910
@@ -95,6 +108,13 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
+  thead,vlenb:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      VLEN/8, the vector register length in bytes. This property is required on
+      thead systems where the vector register length is not identical on all harts, or
+      the vlenb CSR is not available.
+
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
diff --git a/dts/upstream/Bindings/riscv/extensions.yaml b/dts/upstream/Bindings/riscv/extensions.yaml
index 9c7dd7e75e0..a63b994e076 100644
--- a/dts/upstream/Bindings/riscv/extensions.yaml
+++ b/dts/upstream/Bindings/riscv/extensions.yaml
@@ -621,6 +621,10 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        # vendor extensions, each extension sorted alphanumerically under the
+        # vendor they belong to. Vendors are sorted alphanumerically as well.
+
+        # Andes
         - const: xandespmu
           description:
             The Andes Technology performance monitor extension for counter overflow
@@ -628,6 +632,12 @@ properties:
             Registers in the AX45MP datasheet.
             https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
 
+        # T-HEAD
+        - const: xtheadvector
+          description:
+            The T-HEAD specific 0.7.1 vector implementation as written in
+            https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
+
     allOf:
       # Zcb depends on Zca
       - if:
diff --git a/dts/upstream/Bindings/riscv/spacemit.yaml b/dts/upstream/Bindings/riscv/spacemit.yaml
new file mode 100644
index 00000000000..52e55077af1
--- /dev/null
+++ b/dts/upstream/Bindings/riscv/spacemit.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT SoC-based boards
+
+maintainers:
+  - Yangyu Chen <cyy@cyyself.name>
+  - Yixun Lan <dlan@gentoo.org>
+
+description:
+  SpacemiT SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - bananapi,bpi-f3
+          - const: spacemit,k1
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/rtc/rtc-mxc.yaml b/dts/upstream/Bindings/rtc/rtc-mxc.yaml
index a14b52178c4..2599b847f40 100644
--- a/dts/upstream/Bindings/rtc/rtc-mxc.yaml
+++ b/dts/upstream/Bindings/rtc/rtc-mxc.yaml
@@ -14,9 +14,13 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - fsl,imx1-rtc
-      - fsl,imx21-rtc
+    oneOf:
+      - const: fsl,imx1-rtc
+      - const: fsl,imx21-rtc
+      - items:
+          - enum:
+              - fsl,imx31-rtc
+          - const: fsl,imx21-rtc
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/serial/8250.yaml b/dts/upstream/Bindings/serial/8250.yaml
index 692aa05500f..0bde2379e86 100644
--- a/dts/upstream/Bindings/serial/8250.yaml
+++ b/dts/upstream/Bindings/serial/8250.yaml
@@ -111,7 +111,9 @@ properties:
               - mediatek,mt7623-btif
           - const: mediatek,mtk-btif
       - items:
-          - const: mrvl,mmp-uart
+          - enum:
+              - mrvl,mmp-uart
+              - spacemit,k1-uart
           - const: intel,xscale-uart
       - items:
           - enum:
diff --git a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
index 88871480018..ab39b95dae4 100644
--- a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
+++ b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
@@ -23,6 +23,8 @@ properties:
     maxItems: 1
 
   interrupts:
+    description:
+      When missing, device driver uses polling instead.
     maxItems: 1
 
   clocks:
@@ -76,7 +78,6 @@ properties:
 required:
   - compatible
   - reg
-  - interrupts
 
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
diff --git a/dts/upstream/Bindings/serial/renesas,scif.yaml b/dts/upstream/Bindings/serial/renesas,scif.yaml
index 51d9fb0f476..8e82999e6ac 100644
--- a/dts/upstream/Bindings/serial/renesas,scif.yaml
+++ b/dts/upstream/Bindings/serial/renesas,scif.yaml
@@ -83,6 +83,11 @@ properties:
 
       - const: renesas,scif-r9a09g057       # RZ/V2H(P)
 
+      - items:
+          - enum:
+              - renesas,scif-r9a09g047      # RZ/G3E
+          - const: renesas,scif-r9a09g057   # RZ/V2H fallback
+
   reg:
     maxItems: 1
 
diff --git a/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml b/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml
new file mode 100644
index 00000000000..d56ff4c05ae
--- /dev/null
+++ b/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA System Manager
+
+maintainers:
+  - Dinh Nguyen <dinguyen@kernel.org>
+
+properties:
+  compatible:
+    oneOf:
+      - description: Cyclone5/Arria5/Arria10
+        const: altr,sys-mgr
+      - description: Stratix10 SoC
+        items:
+          - const: altr,sys-mgr-s10
+          - const: altr,sys-mgr
+
+  reg:
+    maxItems: 1
+
+  cpu1-start-addr:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: CPU1 start address in hex
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,sys-mgr-s10
+    then:
+      properties:
+        cpu1-start-addr: false
+
+additionalProperties: false
+
+examples:
+  - |
+    sysmgr@ffd08000 {
+      compatible = "altr,sys-mgr";
+      reg = <0xffd08000 0x1000>;
+      cpu1-start-addr = <0xffd080c4>;
+    };
diff --git a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
index c6bce40946d..3dc66f1de02 100644
--- a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
+++ b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     items:
       - enum:
+          - amlogic,meson-hhi-sysctrl
           - amlogic,meson-gx-hhi-sysctrl
           - amlogic,meson-gx-ao-sysctrl
           - amlogic,meson-axg-hhi-sysctrl
@@ -40,6 +41,19 @@ allOf:
       properties:
         compatible:
           enum:
+            - amlogic,meson-hhi-sysctrl
+    then:
+      properties:
+        clock-controller:
+          $ref: /schemas/clock/amlogic,meson8-clkc.yaml#
+
+        pinctrl: false
+        phy: false
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - amlogic,meson-gx-hhi-sysctrl
             - amlogic,meson-axg-hhi-sysctrl
     then:
diff --git a/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt b/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt
deleted file mode 100644
index 30942cf7992..00000000000
--- a/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Raspberry Pi power domain driver
-
-Required properties:
-
-- compatible:		Should be "raspberrypi,bcm2835-power".
-- firmware:		Reference to the RPi firmware device node.
-- #power-domain-cells:	Should be <1>, we providing multiple power domains.
-
-The valid defines for power domain are:
-
- RPI_POWER_DOMAIN_I2C0
- RPI_POWER_DOMAIN_I2C1
- RPI_POWER_DOMAIN_I2C2
- RPI_POWER_DOMAIN_VIDEO_SCALER
- RPI_POWER_DOMAIN_VPU1
- RPI_POWER_DOMAIN_HDMI
- RPI_POWER_DOMAIN_USB
- RPI_POWER_DOMAIN_VEC
- RPI_POWER_DOMAIN_JPEG
- RPI_POWER_DOMAIN_H264
- RPI_POWER_DOMAIN_V3D
- RPI_POWER_DOMAIN_ISP
- RPI_POWER_DOMAIN_UNICAM0
- RPI_POWER_DOMAIN_UNICAM1
- RPI_POWER_DOMAIN_CCP2RX
- RPI_POWER_DOMAIN_CSI2
- RPI_POWER_DOMAIN_CPI
- RPI_POWER_DOMAIN_DSI0
- RPI_POWER_DOMAIN_DSI1
- RPI_POWER_DOMAIN_TRANSPOSER
- RPI_POWER_DOMAIN_CCP2TX
- RPI_POWER_DOMAIN_CDP
- RPI_POWER_DOMAIN_ARM
-
-Example:
-
-power: power {
-	compatible = "raspberrypi,bcm2835-power";
-	firmware = <&firmware>;
-	#power-domain-cells = <1>;
-};
-
-Example for using power domain:
-
-&usb {
-       power-domains = <&power RPI_POWER_DOMAIN_USB>;
-};
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
index e63f800c6ca..41fbbe059d8 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-aoss-qmp
           - qcom,qcs8300-aoss-qmp
           - qcom,qdu1000-aoss-qmp
           - qcom,sa8255p-aoss-qmp
diff --git a/dts/upstream/Bindings/soc/renesas/renesas.yaml b/dts/upstream/Bindings/soc/renesas/renesas.yaml
index b7acb65bdec..225c0f07ae9 100644
--- a/dts/upstream/Bindings/soc/renesas/renesas.yaml
+++ b/dts/upstream/Bindings/soc/renesas/renesas.yaml
@@ -360,19 +360,21 @@ properties:
               - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
           - const: renesas,r8a779g0
 
-      - description: R-Car V4H (R8A779G2)
-        items:
-          - enum:
-              - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001)
-          - const: renesas,r8a779g2
-          - const: renesas,r8a779g0
-
       - items:
           - enum:
               - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
           - const: renesas,white-hawk-cpu
           - const: renesas,r8a779g0
 
+      - description: R-Car V4H (R8A779G[23])
+        items:
+          - enum:
+              - renesas,white-hawk-single # White Hawk Single board (RTP8A779G[23]ASKB0F10SA001)
+          - enum:
+              - renesas,r8a779g2 # ES2.x
+              - renesas,r8a779g3 # ES3.x
+          - const: renesas,r8a779g0
+
       - description: R-Car V4M (R8A779H0)
         items:
           - enum:
@@ -525,6 +527,23 @@ properties:
               - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0
           - const: renesas,r9a09g011
 
+      - description: RZ/G3E (R9A09G047)
+        items:
+          - enum:
+              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+          - enum:
+              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
+          - enum:
+              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
+              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
+              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+          - const: renesas,r9a09g047
+
       - description: RZ/V2H(P) (R9A09G057)
         items:
           - enum:
diff --git a/dts/upstream/Bindings/soc/rockchip/grf.yaml b/dts/upstream/Bindings/soc/rockchip/grf.yaml
index 7eca9e1ad6a..61f38b68a4a 100644
--- a/dts/upstream/Bindings/soc/rockchip/grf.yaml
+++ b/dts/upstream/Bindings/soc/rockchip/grf.yaml
@@ -23,6 +23,7 @@ properties:
               - rockchip,rk3576-bigcore-grf
               - rockchip,rk3576-cci-grf
               - rockchip,rk3576-gpu-grf
+              - rockchip,rk3576-hdptxphy-grf
               - rockchip,rk3576-litcore-grf
               - rockchip,rk3576-npu-grf
               - rockchip,rk3576-php-grf
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
index 6cdfe7e059a..8e6d051d8c9 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
@@ -55,6 +55,7 @@ properties:
               - samsung,exynos7885-pmu
               - samsung,exynos8895-pmu
               - samsung,exynos9810-pmu
+              - samsung,exynos990-pmu
               - samsung,exynosautov9-pmu
               - samsung,exynosautov920-pmu
               - tesla,fsd-pmu
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
index f80fcbc3128..5b046932fbc 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
@@ -64,6 +64,7 @@ properties:
 
   samsung,mode:
     $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
     description:
       Selects USI function (which serial protocol to use). Refer to
       <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
diff --git a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 3ca22058289..a75aef24062 100644
--- a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -21,6 +21,10 @@ properties:
               - samsung,exynos3-sysreg
               - samsung,exynos4-sysreg
               - samsung,exynos5-sysreg
+              - samsung,exynos8895-fsys0-sysreg
+              - samsung,exynos8895-fsys1-sysreg
+              - samsung,exynos8895-peric0-sysreg
+              - samsung,exynos8895-peric1-sysreg
               - samsung,exynosautov920-peric0-sysreg
               - samsung,exynosautov920-peric1-sysreg
               - tesla,fsd-cam-sysreg
@@ -79,6 +83,10 @@ allOf:
               - samsung,exynos850-cmgp-sysreg
               - samsung,exynos850-peri-sysreg
               - samsung,exynos850-sysreg
+              - samsung,exynos8895-fsys0-sysreg
+              - samsung,exynos8895-fsys1-sysreg
+              - samsung,exynos8895-peric0-sysreg
+              - samsung,exynos8895-peric1-sysreg
     then:
       required:
         - clocks
diff --git a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
index 3cb1471cc6b..927b3200e29 100644
--- a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
+++ b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
@@ -92,6 +92,16 @@ properties:
     description: |
       This property is as per sci-pm-domain.txt.
 
+  clocks:
+    items:
+      - description: ICSSG_CORE Clock
+      - description: ICSSG_IEP Clock
+      - description: ICSSG_RGMII_MHZ_250 Clock
+      - description: ICSSG_RGMII_MHZ_50 Clock
+      - description: ICSSG_RGMII_MHZ_5 Clock
+      - description: ICSSG_UART Clock
+      - description: ICSSG_ICLK Clock
+
 patternProperties:
 
   memories@[a-f0-9]+$:
diff --git a/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt b/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt
deleted file mode 100644
index 2417b13ba46..00000000000
--- a/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-LogicoreIP designed compatible with Xilinx ZYNQ family.
--------------------------------------------------------
-
-General concept
----------------
-
-LogicoreIP design to provide the isolation between processing system
-and programmable logic. Also provides the list of register set to configure
-the frequency.
-
-Required properties:
-- compatible: shall be one of:
-	"xlnx,vcu"
-	"xlnx,vcu-logicoreip-1.0"
-- reg : The base offset and size of the VCU_PL_SLCR register space.
-- clocks: phandle for aclk and pll_ref clocksource
-- clock-names: The identification string, "aclk", is always required for
-   the axi clock. "pll_ref" is required for pll.
-Example:
-
-	xlnx_vcu: vcu@a0040000 {
-		compatible = "xlnx,vcu-logicoreip-1.0";
-		reg = <0x0 0xa0040000 0x0 0x1000>;
-		clocks = <&si570_1>, <&clkc 71>;
-		clock-names = "pll_ref", "aclk";
-	};
diff --git a/dts/upstream/Bindings/sound/adi,ssm2518.yaml b/dts/upstream/Bindings/sound/adi,ssm2518.yaml
index f3f32540779..f1beae84cad 100644
--- a/dts/upstream/Bindings/sound/adi,ssm2518.yaml
+++ b/dts/upstream/Bindings/sound/adi,ssm2518.yaml
@@ -36,12 +36,14 @@ unevaluatedProperties: false
 
 examples:
   - |
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec@34 {
-       compatible = "adi,ssm2518";
-       reg = <0x34>;
-       gpios = <&gpio 5 0>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        codec@34 {
+            compatible = "adi,ssm2518";
+            reg = <0x34>;
+            gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
index ebc9097f936..ccae64ce307 100644
--- a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
+++ b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
@@ -23,6 +23,7 @@ properties:
       - allwinner,sun8i-h3-codec
       - allwinner,sun8i-v3s-codec
       - allwinner,sun50i-h616-codec
+      - allwinner,suniv-f1c100s-codec
 
   reg:
     maxItems: 1
@@ -77,6 +78,7 @@ properties:
         - MIC1
         - MIC2
         - MIC3
+        - MIC
 
         # Microphone Biases from the SoC
         - HBIAS
@@ -87,6 +89,8 @@ properties:
         - Headset Mic
         - Line In
         - Line Out
+        - Right FM In
+        - Left FM In
         - Mic
         - Speaker
 
@@ -270,6 +274,33 @@ allOf:
             - const: rx
             - const: tx
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - allwinner,suniv-f1c100s-codec
+
+    then:
+      properties:
+        allwinner,audio-routing:
+          items:
+            enum:
+              - HP
+              - HPCOM
+              - LINEIN
+              - LINEOUT
+              - MIC
+              - HBIAS
+              - MBIAS
+              - Headphone
+              - Headset Mic
+              - Line In
+              - Line Out
+              - Right FM In
+              - Left FM In
+              - Mic
+              - Speaker
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/sound/awinic,aw88395.yaml b/dts/upstream/Bindings/sound/awinic,aw88395.yaml
index 3b0b743e49c..6676406bf2d 100644
--- a/dts/upstream/Bindings/sound/awinic,aw88395.yaml
+++ b/dts/upstream/Bindings/sound/awinic,aw88395.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - awinic,aw88081
+      - awinic,aw88083
       - awinic,aw88261
       - awinic,aw88395
       - awinic,aw88399
@@ -58,6 +59,7 @@ allOf:
           contains:
             enum:
               - awinic,aw88081
+              - awinic,aw88083
               - awinic,aw88261
     then:
       properties:
diff --git a/dts/upstream/Bindings/sound/everest,es71x4.yaml b/dts/upstream/Bindings/sound/everest,es71x4.yaml
index fd1b3281222..efe9f3fd377 100644
--- a/dts/upstream/Bindings/sound/everest,es71x4.yaml
+++ b/dts/upstream/Bindings/sound/everest,es71x4.yaml
@@ -53,10 +53,10 @@ unevaluatedProperties: false
 
 examples:
   - |
-   codec {
-       compatible = "everest,es7134";
-       #sound-dai-cells = <0>;
-       VDD-supply = <&vdd_supply>;
-   };
+    codec {
+        compatible = "everest,es7134";
+        #sound-dai-cells = <0>;
+        VDD-supply = <&vdd_supply>;
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/everest,es7241.yaml b/dts/upstream/Bindings/sound/everest,es7241.yaml
index f179af75873..e5cfb40f1ef 100644
--- a/dts/upstream/Bindings/sound/everest,es7241.yaml
+++ b/dts/upstream/Bindings/sound/everest,es7241.yaml
@@ -54,14 +54,15 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   codec {
-       compatible = "everest,es7241";
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-       VDDP-supply = <&vddp_supply>;
-       VDDA-supply = <&vdda_supply>;
-       VDDD-supply = <&vddd_supply>;
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    codec {
+        compatible = "everest,es7241";
+        #sound-dai-cells = <0>;
+        reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+        VDDP-supply = <&vddp_supply>;
+        VDDA-supply = <&vdda_supply>;
+        VDDD-supply = <&vddd_supply>;
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/fsl,easrc.yaml b/dts/upstream/Bindings/sound/fsl,easrc.yaml
index 0782f3f9947..c454110f428 100644
--- a/dts/upstream/Bindings/sound/fsl,easrc.yaml
+++ b/dts/upstream/Bindings/sound/fsl,easrc.yaml
@@ -87,20 +87,20 @@ examples:
     #include <dt-bindings/clock/imx8mn-clock.h>
 
     easrc: easrc@300c0000 {
-           compatible = "fsl,imx8mn-easrc";
-           reg = <0x300c0000 0x10000>;
-           interrupts = <0x0 122 0x4>;
-           clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
-           clock-names = "mem";
-           dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
-                  <&sdma2 18 23 0> , <&sdma2 19 23 0>,
-                  <&sdma2 20 23 0> , <&sdma2 21 23 0>,
-                  <&sdma2 22 23 0> , <&sdma2 23 23 0>;
-           dma-names = "ctx0_rx", "ctx0_tx",
-                       "ctx1_rx", "ctx1_tx",
-                       "ctx2_rx", "ctx2_tx",
-                       "ctx3_rx", "ctx3_tx";
-           firmware-name = "imx/easrc/easrc-imx8mn.bin";
-           fsl,asrc-rate  = <8000>;
-           fsl,asrc-format = <2>;
+        compatible = "fsl,imx8mn-easrc";
+        reg = <0x300c0000 0x10000>;
+        interrupts = <0x0 122 0x4>;
+        clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
+        clock-names = "mem";
+        dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
+               <&sdma2 18 23 0> , <&sdma2 19 23 0>,
+               <&sdma2 20 23 0> , <&sdma2 21 23 0>,
+               <&sdma2 22 23 0> , <&sdma2 23 23 0>;
+        dma-names = "ctx0_rx", "ctx0_tx",
+                    "ctx1_rx", "ctx1_tx",
+                    "ctx2_rx", "ctx2_tx",
+                    "ctx3_rx", "ctx3_tx";
+        firmware-name = "imx/easrc/easrc-imx8mn.bin";
+        fsl,asrc-rate  = <8000>;
+        fsl,asrc-format = <2>;
     };
diff --git a/dts/upstream/Bindings/sound/fsl,micfil.yaml b/dts/upstream/Bindings/sound/fsl,micfil.yaml
index c1e9803fc11..c47b7a09749 100644
--- a/dts/upstream/Bindings/sound/fsl,micfil.yaml
+++ b/dts/upstream/Bindings/sound/fsl,micfil.yaml
@@ -25,6 +25,7 @@ properties:
           - fsl,imx8mm-micfil
           - fsl,imx8mp-micfil
           - fsl,imx93-micfil
+          - fsl,imx943-micfil
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/sound/fsl,mqs.yaml b/dts/upstream/Bindings/sound/fsl,mqs.yaml
index 030ccc17313..8c22e8348b1 100644
--- a/dts/upstream/Bindings/sound/fsl,mqs.yaml
+++ b/dts/upstream/Bindings/sound/fsl,mqs.yaml
@@ -23,6 +23,8 @@ properties:
       - fsl,imx8qm-mqs
       - fsl,imx8qxp-mqs
       - fsl,imx93-mqs
+      - fsl,imx943-aonmix-mqs
+      - fsl,imx943-wakeupmix-mqs
       - fsl,imx95-aonmix-mqs
       - fsl,imx95-netcmix-mqs
 
diff --git a/dts/upstream/Bindings/sound/fsl,xcvr.yaml b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
index 5e280101422..f68d0e0ecfe 100644
--- a/dts/upstream/Bindings/sound/fsl,xcvr.yaml
+++ b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
@@ -140,21 +140,21 @@ examples:
     #include <dt-bindings/reset/imx8mp-reset.h>
 
     xcvr: xcvr@30cc0000 {
-           compatible = "fsl,imx8mp-xcvr";
-           reg = <0x30cc0000 0x800>,
-                 <0x30cc0800 0x400>,
-                 <0x30cc0c00 0x080>,
-                 <0x30cc0e00 0x080>;
-           reg-names = "ram", "regs", "rxfifo", "txfifo";
-           interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
-           clock-names = "ipg", "phy", "spba", "pll_ipg";
-           dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
-           dma-names = "rx", "tx";
-           resets = <&audiomix_reset 0>;
+        compatible = "fsl,imx8mp-xcvr";
+        reg = <0x30cc0000 0x800>,
+              <0x30cc0800 0x400>,
+              <0x30cc0c00 0x080>,
+              <0x30cc0e00 0x080>;
+        reg-names = "ram", "regs", "rxfifo", "txfifo";
+        interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+        clock-names = "ipg", "phy", "spba", "pll_ipg";
+        dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+        dma-names = "rx", "tx";
+        resets = <&audiomix_reset 0>;
     };
diff --git a/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml b/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
index 76b6f2cf25d..dca61786093 100644
--- a/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
+++ b/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
@@ -72,19 +72,19 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/interrupt-controller/arm-gic.h>
-     #include <dt-bindings/interrupt-controller/irq.h>
-     #define KEEM_BAY_PSS_AUX_I2S3
-     #define KEEM_BAY_PSS_I2S3
-     i2s3: i2s@20140000 {
-         compatible = "intel,keembay-i2s";
-         #sound-dai-cells = <0>;
-         reg = <0x20140000 0x200>, /* I2S registers */
-               <0x202a00a4 0x4>; /* I2S gen configuration */
-         reg-names = "i2s-regs", "i2s_gen_cfg";
-         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-         clock-names = "osc", "apb_clk";
-         clocks = <&scmi_clk KEEM_BAY_PSS_AUX_I2S3>, <&scmi_clk KEEM_BAY_PSS_I2S3>;
-         dmas = <&axi_dma0 29>, <&axi_dma0 33>;
-         dma-names = "tx", "rx";
-     };
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #define KEEM_BAY_PSS_AUX_I2S3
+    #define KEEM_BAY_PSS_I2S3
+    i2s@20140000 {
+        compatible = "intel,keembay-i2s";
+        #sound-dai-cells = <0>;
+        reg = <0x20140000 0x200>, /* I2S registers */
+              <0x202a00a4 0x4>; /* I2S gen configuration */
+        reg-names = "i2s-regs", "i2s_gen_cfg";
+        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "osc", "apb_clk";
+        clocks = <&scmi_clk KEEM_BAY_PSS_AUX_I2S3>, <&scmi_clk KEEM_BAY_PSS_I2S3>;
+        dmas = <&axi_dma0 29>, <&axi_dma0 33>;
+        dma-names = "tx", "rx";
+    };
diff --git a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
index ba482747f0e..362e729b51b 100644
--- a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
+++ b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
@@ -14,11 +14,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8188-es8326
-      - mediatek,mt8188-mt6359-evb
-      - mediatek,mt8188-nau8825
-      - mediatek,mt8188-rt5682s
+    oneOf:
+      - enum:
+          - mediatek,mt8188-es8326
+          - mediatek,mt8188-mt6359-evb
+          - mediatek,mt8188-nau8825
+          - mediatek,mt8188-rt5682s
+      - items:
+          - const: mediatek,mt8390-mt6359-evk
+          - const: mediatek,mt8188-mt6359-evb
 
   audio-routing:
     description:
@@ -56,6 +60,8 @@ patternProperties:
             - ETDM2_OUT_BE
             - ETDM3_OUT_BE
             - PCM1_BE
+            - DL_SRC_BE
+            - UL_SRC_BE
 
       codec:
         description: Holds subnode which indicates codec dai.
diff --git a/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml b/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
index 952768b3590..6946177e391 100644
--- a/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
+++ b/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
@@ -55,16 +55,18 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     audio-codec@2a {
-       compatible = "neofidelity,ntp8918";
-       #sound-dai-cells = <0>;
-       reg = <0x2a>;
-       clocks = <&clkc 150>, <&clkc 151>, <&clkc 152>;
-       clock-names =  "wck", "scl", "bck";
-       reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@2a {
+            compatible = "neofidelity,ntp8918";
+            #sound-dai-cells = <0>;
+            reg = <0x2a>;
+            clocks = <&clkc 150>, <&clkc 151>, <&clkc 152>;
+            clock-names =  "wck", "scl", "bck";
+            reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+        };
     };
-   };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5682.yaml b/dts/upstream/Bindings/sound/realtek,rt5682.yaml
new file mode 100644
index 00000000000..39333ea0564
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5682.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5682.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek rt5682 and rt5682i codecs
+
+maintainers:
+  - Bard Liao <bardliao@realtek.com>
+
+allOf:
+  - $ref: dai-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - realtek,rt5682
+      - realtek,rt5682i
+
+  reg:
+    maxItems: 1
+    description: I2C address of the device.
+
+  interrupts:
+    maxItems: 1
+    description: The CODEC's interrupt output.
+
+  realtek,dmic1-data-pin:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # dmic1 data is not used
+      - 1 # using GPIO2 pin as dmic1 data pin
+      - 2 # using GPIO5 pin as dmic1 data pin
+    description:
+      Specify which GPIO pin be used as DMIC1 data pin.
+
+  realtek,dmic1-clk-pin:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # using GPIO1 pin as dmic1 clock pin
+      - 1 # using GPIO3 pin as dmic1 clock pin
+    description:
+      Specify which GPIO pin be used as DMIC1 clk pin.
+
+  realtek,jd-src:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # No JD is used
+      - 1 # using JD1 as JD source
+    description:
+      Specify which JD source be used.
+
+  realtek,ldo1-en-gpios:
+    description:
+      The GPIO that controls the CODEC's LDO1_EN pin.
+
+  realtek,btndet-delay:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The debounce delay for push button.
+      The delay time is realtek,btndet-delay value multiple of 8.192 ms.
+      If absent, the default is 16.
+
+  realtek,dmic-clk-rate-hz:
+    description:
+      Set the clock rate (hz) for the requirement of the particular DMIC.
+
+  realtek,dmic-delay-ms:
+    description:
+      Set the delay time (ms) for the requirement of the particular DMIC.
+
+  realtek,dmic-clk-driving-high:
+    type: boolean
+    description:
+      Set the high driving of the DMIC clock out.
+
+  clocks:
+    items:
+      - description: phandle and clock specifier for codec MCLK.
+
+  clock-names:
+    items:
+      - const: mclk
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    minItems: 2
+    maxItems: 2
+    description: Name given for DAI word clock and bit clock outputs.
+
+  "#sound-dai-cells":
+    const: 1
+
+  AVDD-supply:
+    description: Regulator supplying analog power through the AVDD pin.
+
+  MICVDD-supply:
+    description: Regulator supplying power for the microphone bias through
+      the MICVDD pin.
+
+  VBAT-supply:
+    description: Regulator supplying battery power through the VBAT pin.
+
+  DBVDD-supply:
+    description: Regulator supplying I/O power through the DBVDD pin.
+
+  LDO1-IN-supply:
+    description: Regulator supplying power to the digital core and charge
+      pump through the LDO1_IN pin.
+
+required:
+  - compatible
+  - reg
+  - AVDD-supply
+  - VBAT-supply
+  - MICVDD-supply
+  - DBVDD-supply
+  - LDO1-IN-supply
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@1a {
+            compatible = "realtek,rt5682";
+            reg = <0x1a>;
+            interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+            realtek,ldo1-en-gpios =
+                <&gpio 2 GPIO_ACTIVE_HIGH>;
+            realtek,dmic1-data-pin = <1>;
+            realtek,dmic1-clk-pin = <1>;
+            realtek,jd-src = <1>;
+
+            #clock-cells = <1>;
+            clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
+
+            clocks = <&osc>;
+            clock-names = "mclk";
+
+            AVDD-supply = <&avdd_reg>;
+            VBAT-supply = <&vbat_reg>;
+            MICVDD-supply = <&micvdd_reg>;
+            DBVDD-supply = <&dbvdd_reg>;
+            LDO1-IN-supply = <&ldo1_in_reg>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/renesas,rsnd.yaml b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
index 6d0d1514cd4..e8a2acb9264 100644
--- a/dts/upstream/Bindings/sound/renesas,rsnd.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
@@ -112,12 +112,6 @@ properties:
     description: List of necessary clock names.
     # details are defined below
 
-  post-init-providers:
-    description: At least if rsnd is using DPCM connection on Audio-Graph-Card2,
-      fw_devlink might doesn't have enough information to break the cycle. rsnd
-      driver will not be probed in such case. Same problem might occur with
-      Multi-CPU/Codec or Codec2Codec.
-
   # ports is below
   port:
     $ref: audio-graph-port.yaml#/definitions/port-base
diff --git a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
index f4610eaed1e..e4cdbf2202b 100644
--- a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
@@ -19,6 +19,7 @@ properties:
           - renesas,r9a07g043-ssi  # RZ/G2UL and RZ/Five
           - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
           - renesas,r9a07g054-ssi  # RZ/V2L
+          - renesas,r9a08g045-ssi  # RZ/G3S
       - const: renesas,rz-ssi
 
   reg:
@@ -57,24 +58,6 @@ properties:
   dmas:
     minItems: 1
     maxItems: 2
-    description:
-      The first cell represents a phandle to dmac.
-      The second cell specifies the encoded MID/RID values of the SSI port
-      connected to the DMA client and the slave channel configuration
-      parameters.
-      bits[0:9]   - Specifies MID/RID value of a SSI channel as below
-                    MID/RID value of SSI rx0 = 0x256
-                    MID/RID value of SSI tx0 = 0x255
-                    MID/RID value of SSI rx1 = 0x25a
-                    MID/RID value of SSI tx1 = 0x259
-                    MID/RID value of SSI rt2 = 0x25f
-                    MID/RID value of SSI rx3 = 0x262
-                    MID/RID value of SSI tx3 = 0x261
-      bit[10]     - HIEN = 1, Detects a request in response to the rising edge
-                    of the signal
-      bit[11]     - LVL = 0, Detects based on the edge
-      bits[12:14] - AM = 2, Bus cycle mode
-      bit[15]     - TM = 0, Single transfer mode
 
   dma-names:
     oneOf:
diff --git a/dts/upstream/Bindings/sound/rt5682.txt b/dts/upstream/Bindings/sound/rt5682.txt
deleted file mode 100644
index 5e1d08de18a..00000000000
--- a/dts/upstream/Bindings/sound/rt5682.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-RT5682 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : "realtek,rt5682" or "realtek,rt5682i"
-
-- reg : The I2C address of the device.
-
-- AVDD-supply: phandle to the regulator supplying analog power through the
-  AVDD pin
-
-- MICVDD-supply: phandle to the regulator supplying power for the microphone
-  bias through the MICVDD pin. Either MICVDD or VBAT should be present.
-
-- VBAT-supply: phandle to the regulator supplying battery power through the
-  VBAT pin. Either MICVDD or VBAT should be present.
-
-- DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
-  pin.
-
-- LDO1-IN-supply: phandle to the regulator supplying power to the digital core
-  and charge pump through the LDO1_IN pin.
-
-Optional properties:
-
-- interrupts : The CODEC's interrupt output.
-
-- realtek,dmic1-data-pin
-  0: dmic1 is not used
-  1: using GPIO2 pin as dmic1 data pin
-  2: using GPIO5 pin as dmic1 data pin
-
-- realtek,dmic1-clk-pin
-  0: using GPIO1 pin as dmic1 clock pin
-  1: using GPIO3 pin as dmic1 clock pin
-
-- realtek,jd-src
-  0: No JD is used
-  1: using JD1 as JD source
-
-- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
-
-- realtek,btndet-delay
-  The debounce delay for push button.
-  The delay time is realtek,btndet-delay value multiple of 8.192 ms.
-  If absent, the default is 16.
-
-- #clock-cells : Should be set to '<1>',  wclk and bclk sources provided.
-- clock-output-names : Name given for DAI clocks output.
-
-- clocks : phandle and clock specifier for codec MCLK.
-- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
-
-- realtek,dmic-clk-rate-hz : Set the clock rate (hz) for the requirement of
-  the particular DMIC.
-
-- realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of
-  the particular DMIC.
-
-- realtek,dmic-clk-driving-high : Set the high driving of the DMIC clock out.
-
-- #sound-dai-cells: Should be set to '<1>'.
-
-Pins on the device (for linking into audio routes) for RT5682:
-
-  * DMIC L1
-  * DMIC R1
-  * IN1P
-  * HPOL
-  * HPOR
-
-Example:
-
-rt5682 {
-	compatible = "realtek,rt5682i";
-	reg = <0x1a>;
-	interrupt-parent = <&gpio>;
-	interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
-	realtek,ldo1-en-gpios =
-		<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
-	realtek,dmic1-data-pin = <1>;
-	realtek,dmic1-clk-pin = <1>;
-	realtek,jd-src = <1>;
-	realtek,btndet-delay = <16>;
-
-	#clock-cells = <1>;
-	clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
-
-	clocks = <&osc>;
-	clock-names = "mclk";
-
-	AVDD-supply = <&avdd_reg>;
-	MICVDD-supply = <&micvdd_reg>;
-	DBVDD-supply = <&dbvdd_reg>;
-	LDO1-IN-supply = <&ldo1_in_reg>;
-};
diff --git a/dts/upstream/Bindings/sound/ti,pcm1681.yaml b/dts/upstream/Bindings/sound/ti,pcm1681.yaml
index 5aa00617291..1f0e6787a74 100644
--- a/dts/upstream/Bindings/sound/ti,pcm1681.yaml
+++ b/dts/upstream/Bindings/sound/ti,pcm1681.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/sound/ti,pcm1681.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Texas Instruments PCM1681 8-channel PWM Processor
+title: Texas Instruments PCM1681 8-channel Digital-to-Analog Converter
 
 maintainers:
   - Shenghao Ding <shenghao-ding@ti.com>
diff --git a/dts/upstream/Bindings/sound/ti,pcm6240.yaml b/dts/upstream/Bindings/sound/ti,pcm6240.yaml
index dd5b08e3d7a..d89b4255b51 100644
--- a/dts/upstream/Bindings/sound/ti,pcm6240.yaml
+++ b/dts/upstream/Bindings/sound/ti,pcm6240.yaml
@@ -159,19 +159,21 @@ additionalProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     /* example for two devices with interrupt support */
-     #address-cells = <1>;
-     #size-cells = <0>;
-     pcm6240: audio-codec@48 {
-       compatible = "ti,pcm6240";
-       reg = <0x48>, /* primary-device */
-             <0x4b>; /* secondary-device */
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <15>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        /* example for two devices with interrupt support */
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@48 {
+            compatible = "ti,pcm6240";
+            reg = <0x48>, /* primary-device */
+                  <0x4b>; /* secondary-device */
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <15>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas2562.yaml b/dts/upstream/Bindings/sound/ti,tas2562.yaml
index 8bc3b0c7531..3763ca16b91 100644
--- a/dts/upstream/Bindings/sound/ti,tas2562.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2562.yaml
@@ -65,17 +65,19 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@4c {
-       compatible = "ti,tas2562";
-       reg = <0x4c>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       shutdown-gpios = <&gpio1 15 0>;
-       ti,imon-slot-no = <0>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@4c {
+            compatible = "ti,tas2562";
+            reg = <0x4c>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/ti,tas2770.yaml b/dts/upstream/Bindings/sound/ti,tas2770.yaml
index 362c2e6154f..5e7aea43ace 100644
--- a/dts/upstream/Bindings/sound/ti,tas2770.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2770.yaml
@@ -69,19 +69,21 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@41 {
-       compatible = "ti,tas2770";
-       reg = <0x41>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       reset-gpio = <&gpio1 15 0>;
-       shutdown-gpios = <&gpio1 14 0>;
-       ti,imon-slot-no = <0>;
-       ti,vmon-slot-no = <2>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@41 {
+            compatible = "ti,tas2770";
+            reg = <0x41>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            reset-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            shutdown-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+            ti,vmon-slot-no = <2>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/ti,tas2781.yaml b/dts/upstream/Bindings/sound/ti,tas2781.yaml
index 97623868924..5ea1cdc593b 100644
--- a/dts/upstream/Bindings/sound/ti,tas2781.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2781.yaml
@@ -101,22 +101,24 @@ additionalProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     /* example with quad tas2781s, such as tablet or pad device */
-     #address-cells = <1>;
-     #size-cells = <0>;
-     quad_tas2781: tas2781@38 {
-       compatible = "ti,tas2781";
-       reg = <0x38>, /* Audio slot 0 */
-             <0x3a>, /* Audio slot 1 */
-             <0x39>, /* Audio slot 2 */
-             <0x3b>; /* Audio slot 3 */
-
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <15>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        /* example with quad tas2781s, such as tablet or pad device */
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@38 {
+            compatible = "ti,tas2781";
+            reg = <0x38>, /* Audio slot 0 */
+                  <0x3a>, /* Audio slot 1 */
+                  <0x39>, /* Audio slot 2 */
+                  <0x3b>; /* Audio slot 3 */
+
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <15>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas27xx.yaml b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
index 530bc393784..5447482179c 100644
--- a/dts/upstream/Bindings/sound/ti,tas27xx.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
@@ -62,21 +62,23 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@38 {
-       compatible = "ti,tas2764";
-       reg = <0x38>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       reset-gpios = <&gpio1 15 0>;
-       shutdown-gpios = <&gpio1 15 0>;
-       ti,imon-slot-no = <0>;
-       ti,vmon-slot-no = <2>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@38 {
+            compatible = "ti,tas2764";
+            reg = <0x38>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+            ti,vmon-slot-no = <2>;
+        };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas57xx.yaml b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
index 2f917238db9..74f7d02b424 100644
--- a/dts/upstream/Bindings/sound/ti,tas57xx.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
@@ -112,22 +112,24 @@ unevaluatedProperties: false
 
 examples:
   - |
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-
-     codec@2a {
-       compatible = "ti,tas5717";
-       reg = <0x2a>;
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 15 0>;
-       pdn-gpios = <&gpio1 15 0>;
-       AVDD-supply = <&avdd_supply>;
-       DVDD-supply = <&dvdd_supply>;
-       HPVDD-supply = <&hpvdd_supply>;
-       PVDD_AB-supply = <&pvdd_ab_supply>;
-       PVDD_CD-supply = <&pvdd_cd_supply>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@2a {
+            compatible = "ti,tas5717";
+            reg = <0x2a>;
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            pdn-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            AVDD-supply = <&avdd_supply>;
+            DVDD-supply = <&dvdd_supply>;
+            HPVDD-supply = <&hpvdd_supply>;
+            PVDD_AB-supply = <&pvdd_ab_supply>;
+            PVDD_CD-supply = <&pvdd_cd_supply>;
+        };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml b/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
index d48ecd6cd5a..b6bc71d1928 100644
--- a/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
+++ b/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
@@ -68,6 +68,7 @@ properties:
       - items:
           - enum:
               - amd,pensando-elba-qspi
+              - amd,versal2-ospi
               - intel,lgm-qspi
               - intel,socfpga-qspi
               - mobileye,eyeq5-ospi
diff --git a/dts/upstream/Bindings/spi/spi-controller.yaml b/dts/upstream/Bindings/spi/spi-controller.yaml
index 093150c0cb8..82d051f7bd6 100644
--- a/dts/upstream/Bindings/spi/spi-controller.yaml
+++ b/dts/upstream/Bindings/spi/spi-controller.yaml
@@ -69,6 +69,11 @@ properties:
          Should be generally avoided and be replaced by
          spi-cs-high + ACTIVE_HIGH.
 
+      The simplest way to obtain an active-high CS signal is to configure the
+      controller's cs-gpio property with the ACTIVE_HIGH flag and set the
+      peripheral's spi-cs-high property. See example below for a better
+      understanding.
+
   fifo-depth:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
@@ -189,3 +194,23 @@ examples:
             stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
         };
     };
+
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi@20204000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "brcm,bcm2835-spi";
+        reg = <0x7e204000 0x1000>;
+        interrupts = <2 22>;
+        clocks = <&clk_spi>;
+        cs-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+
+        display@0 {
+            compatible = "lg,lg4573";
+            spi-max-frequency = <1000000>;
+            reg = <0>;
+            spi-cs-high;
+        };
+    };
diff --git a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
index d9322704f35..a7236f7db4e 100644
--- a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
+++ b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
@@ -47,7 +47,9 @@ properties:
           - const: allwinner,sun8i-v3s-system-control
           - const: allwinner,sun8i-h3-system-control
       - items:
-          - const: allwinner,sun50i-h6-system-control
+          - enum:
+              - allwinner,sun50i-a100-system-control
+              - allwinner,sun50i-h6-system-control
           - const: allwinner,sun50i-a64-system-control
 
   reg:
diff --git a/dts/upstream/Bindings/sram/qcom,imem.yaml b/dts/upstream/Bindings/sram/qcom,imem.yaml
index 9b06bcd0195..2711f90d966 100644
--- a/dts/upstream/Bindings/sram/qcom,imem.yaml
+++ b/dts/upstream/Bindings/sram/qcom,imem.yaml
@@ -20,6 +20,7 @@ properties:
           - qcom,apq8064-imem
           - qcom,msm8226-imem
           - qcom,msm8974-imem
+          - qcom,msm8976-imem
           - qcom,qcs404-imem
           - qcom,qcs8300-imem
           - qcom,qdu1000-imem
diff --git a/dts/upstream/Bindings/thermal/qcom-tsens.yaml b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
index ed5de0f92a9..b9829bb22cc 100644
--- a/dts/upstream/Bindings/thermal/qcom-tsens.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
@@ -80,6 +80,7 @@ properties:
       - description: v2 of TSENS with combined interrupt
         items:
           - enum:
+              - qcom,ipq6018-tsens
               - qcom,ipq9574-tsens
           - const: qcom,ipq8074-tsens
 
diff --git a/dts/upstream/Bindings/timer/fsl,imxgpt.yaml b/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
index e2607377cba..9898dc7ea97 100644
--- a/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
+++ b/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
@@ -21,6 +21,7 @@ properties:
       - items:
           - enum:
               - fsl,imx25-gpt
+              - fsl,imx35-gpt
               - fsl,imx50-gpt
               - fsl,imx51-gpt
               - fsl,imx53-gpt
@@ -31,6 +32,7 @@ properties:
           - enum:
               - fsl,imx6sl-gpt
               - fsl,imx6sx-gpt
+              - fsl,imx7d-gpt
               - fsl,imx8mp-gpt
               - fsl,imxrt1050-gpt
               - fsl,imxrt1170-gpt
@@ -38,7 +40,6 @@ properties:
       - items:
           - enum:
               - fsl,imx6ul-gpt
-              - fsl,imx7d-gpt
           - const: fsl,imx6sx-gpt
 
   reg:
diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml
index b42d43d2de4..76d83aea4e2 100644
--- a/dts/upstream/Bindings/timer/sifive,clint.yaml
+++ b/dts/upstream/Bindings/timer/sifive,clint.yaml
@@ -31,6 +31,7 @@ properties:
           - enum:
               - canaan,k210-clint       # Canaan Kendryte K210
               - sifive,fu540-c000-clint # SiFive FU540
+              - spacemit,k1-clint       # SpacemiT K1
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
diff --git a/dts/upstream/Bindings/trivial-devices.yaml b/dts/upstream/Bindings/trivial-devices.yaml
index 88abb5c174f..fadbd3c041c 100644
--- a/dts/upstream/Bindings/trivial-devices.yaml
+++ b/dts/upstream/Bindings/trivial-devices.yaml
@@ -55,8 +55,6 @@ properties:
           - atmel,atsha204a
             # BPA-RS600: Power Supply
           - blutek,bpa-rs600
-            # Bosch Sensortec pressure, temperature, humididty and VOC sensor
-          - bosch,bme680
             # CM32181: Ambient Light Sensor
           - capella,cm32181
             # CM3232: Ambient Light Sensor
@@ -147,8 +145,12 @@ properties:
           - injoinic,ip5207
             # Injoinic IP5209 2.4A Power Bank IC with I2C
           - injoinic,ip5209
+            # Injoinic IP5306 2.1A Power Bank IC with I2C option
+          - injoinic,ip5306
             # Inspur Power System power supply unit version 1
           - inspur,ipsps1
+            # Intel common redudant power supply crps185
+          - intel,crps185
             # Intersil ISL29028 Ambient Light and Proximity Sensor
           - isil,isl29028
             # Intersil ISL29030 Ambient Light and Proximity Sensor
diff --git a/dts/upstream/Bindings/ufs/qcom,ufs.yaml b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
index cde334e3206..a03fff5df5e 100644
--- a/dts/upstream/Bindings/ufs/qcom,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
@@ -26,6 +26,7 @@ properties:
           - qcom,msm8994-ufshc
           - qcom,msm8996-ufshc
           - qcom,msm8998-ufshc
+          - qcom,qcs615-ufshc
           - qcom,qcs8300-ufshc
           - qcom,sa8775p-ufshc
           - qcom,sc7180-ufshc
@@ -243,6 +244,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs615-ufshc
               - qcom,sm6115-ufshc
               - qcom,sm6125-ufshc
     then:
diff --git a/dts/upstream/Bindings/ufs/renesas,ufs.yaml b/dts/upstream/Bindings/ufs/renesas,ufs.yaml
index f04f9f61fa9..1949a15e73d 100644
--- a/dts/upstream/Bindings/ufs/renesas,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/renesas,ufs.yaml
@@ -50,12 +50,12 @@ examples:
     #include <dt-bindings/power/r8a779f0-sysc.h>
 
     ufs: ufs@e686000 {
-            compatible = "renesas,r8a779f0-ufs";
-            reg = <0xe6860000 0x100>;
-            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
-            clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
-            clock-names = "fck", "ref_clk";
-            freq-table-hz = <200000000 200000000>, <38400000 38400000>;
-            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-            resets = <&cpg 1514>;
+        compatible = "renesas,r8a779f0-ufs";
+        reg = <0xe6860000 0x100>;
+        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+        clock-names = "fck", "ref_clk";
+        freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+        resets = <&cpg 1514>;
     };
diff --git a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
index 720879820f6..b4e744ebffd 100644
--- a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
+++ b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
@@ -112,19 +112,19 @@ examples:
     #include <dt-bindings/clock/exynos7-clk.h>
 
     ufs: ufs@15570000 {
-       compatible = "samsung,exynos7-ufs";
-       reg = <0x15570000 0x100>,
-             <0x15570100 0x100>,
-             <0x15571000 0x200>,
-             <0x15572000 0x300>;
-       reg-names = "hci", "vs_hci", "unipro", "ufsp";
-       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
-       clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
-                <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
-       clock-names = "core_clk", "sclk_unipro_main";
-       pinctrl-names = "default";
-       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
-       phys = <&ufs_phy>;
-       phy-names = "ufs-phy";
+        compatible = "samsung,exynos7-ufs";
+        reg = <0x15570000 0x100>,
+              <0x15570100 0x100>,
+              <0x15571000 0x200>,
+              <0x15572000 0x300>;
+        reg-names = "hci", "vs_hci", "unipro", "ufsp";
+        interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
+                 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
+        clock-names = "core_clk", "sclk_unipro_main";
+        pinctrl-names = "default";
+        pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+        phys = <&ufs_phy>;
+        phy-names = "ufs-phy";
     };
 ...
diff --git a/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml b/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
index a86bcd95100..7f22f9c031b 100644
--- a/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
+++ b/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
@@ -113,27 +113,27 @@ examples:
   - |
     #include <dt-bindings/clock/aspeed-clock.h>
     vhub: usb-vhub@1e6a0000 {
-            compatible = "aspeed,ast2500-usb-vhub";
-            reg = <0x1e6a0000 0x300>;
-            interrupts = <5>;
-            clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
-            aspeed,vhub-downstream-ports = <5>;
-            aspeed,vhub-generic-endpoints = <15>;
-            pinctrl-names = "default";
-            pinctrl-0 = <&pinctrl_usb2ad_default>;
-
-            vhub-vendor-id = <0x1d6b>;
-            vhub-product-id = <0x0107>;
-            vhub-device-revision = <0x0100>;
-            vhub-strings {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                string@409 {
-                        reg = <0x409>;
-                        manufacturer = "ASPEED";
-                        product = "USB Virtual Hub";
-                        serial-number = "0000";
-                };
+        compatible = "aspeed,ast2500-usb-vhub";
+        reg = <0x1e6a0000 0x300>;
+        interrupts = <5>;
+        clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+        aspeed,vhub-downstream-ports = <5>;
+        aspeed,vhub-generic-endpoints = <15>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb2ad_default>;
+
+        vhub-vendor-id = <0x1d6b>;
+        vhub-product-id = <0x0107>;
+        vhub-device-revision = <0x0100>;
+        vhub-strings {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            string@409 {
+                reg = <0x409>;
+                manufacturer = "ASPEED";
+                product = "USB Virtual Hub";
+                serial-number = "0000";
             };
+        };
     };
diff --git a/dts/upstream/Bindings/usb/brcm,bdc.yaml b/dts/upstream/Bindings/usb/brcm,bdc.yaml
index 9e561fee98f..f9375c69e86 100644
--- a/dts/upstream/Bindings/usb/brcm,bdc.yaml
+++ b/dts/upstream/Bindings/usb/brcm,bdc.yaml
@@ -41,10 +41,10 @@ additionalProperties: false
 
 examples:
   - |
-        usb@f0b02000 {
-                compatible = "brcm,bdc-udc-v2";
-                reg = <0xf0b02000 0xfc4>;
-                interrupts = <0x0 0x60 0x0>;
-                phys = <&usbphy_0 0x0>;
-                clocks = <&sw_usbd>;
-        };
+    usb@f0b02000 {
+        compatible = "brcm,bdc-udc-v2";
+        reg = <0xf0b02000 0xfc4>;
+        interrupts = <0x0 0x60 0x0>;
+        phys = <&usbphy_0 0x0>;
+        clocks = <&sw_usbd>;
+    };
diff --git a/dts/upstream/Bindings/usb/cypress,hx3.yaml b/dts/upstream/Bindings/usb/cypress,hx3.yaml
index e44e88d993d..1033b7a4b8f 100644
--- a/dts/upstream/Bindings/usb/cypress,hx3.yaml
+++ b/dts/upstream/Bindings/usb/cypress,hx3.yaml
@@ -56,21 +56,21 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb4b4,6504";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
-          vdd-supply = <&reg_1v2_usb>;
-          vdd2-supply = <&reg_3v3_usb>;
+            compatible = "usb4b4,6504";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            vdd-supply = <&reg_1v2_usb>;
+            vdd2-supply = <&reg_3v3_usb>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb4b4,6506";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
-          vdd-supply = <&reg_1v2_usb>;
-          vdd2-supply = <&reg_3v3_usb>;
+            compatible = "usb4b4,6506";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            vdd-supply = <&reg_1v2_usb>;
+            vdd2-supply = <&reg_3v3_usb>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/dwc2.yaml b/dts/upstream/Bindings/usb/dwc2.yaml
index a5f2e3442a0..e83d30a91b8 100644
--- a/dts/upstream/Bindings/usb/dwc2.yaml
+++ b/dts/upstream/Bindings/usb/dwc2.yaml
@@ -192,7 +192,7 @@ unevaluatedProperties: false
 
 examples:
   - |
-      usb@101c0000 {
+    usb@101c0000 {
         compatible = "rockchip,rk3066-usb", "snps,dwc2";
         reg = <0x10180000 0x40000>;
         interrupts = <18>;
@@ -200,6 +200,6 @@ examples:
         clock-names = "otg";
         phys = <&usbphy>;
         phy-names = "usb2-phy";
-      };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/usb/fcs,fsa4480.yaml b/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
index 8b25b9a01ce..e3a7df91f7f 100644
--- a/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
+++ b/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
@@ -87,21 +87,21 @@ examples:
         #size-cells = <0>;
 
         typec-mux@42 {
-          compatible = "fcs,fsa4480";
-          reg = <0x42>;
+            compatible = "fcs,fsa4480";
+            reg = <0x42>;
 
-          interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;
+            interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;
 
-          vcc-supply = <&vreg_bob>;
+            vcc-supply = <&vreg_bob>;
 
-          mode-switch;
-          orientation-switch;
+            mode-switch;
+            orientation-switch;
 
-          port {
-            fsa4480_ept: endpoint {
-              remote-endpoint = <&typec_controller>;
+            port {
+                fsa4480_ept: endpoint {
+                    remote-endpoint = <&typec_controller>;
+                };
             };
-          };
         };
     };
 ...
diff --git a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
index 8a5f837eff9..e588514fab2 100644
--- a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
+++ b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
@@ -20,6 +20,7 @@ properties:
     items:
       - enum:
           - nxp,cbdtu02043
+          - onnn,fsusb42
           - onnn,fsusb43l10x
           - pericom,pi3usb102
           - ti,tmuxhs4212
diff --git a/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml b/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
index d3511f48cd5..1a75544a8c3 100644
--- a/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
+++ b/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
@@ -58,20 +58,20 @@ examples:
     #define KEEM_BAY_A53_AUX_USB_SUSPEND
 
     usb {
-          compatible = "intel,keembay-dwc3";
-          clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>;
-          clock-names = "async_master", "ref", "alt_ref", "suspend";
-          ranges;
-          #address-cells = <1>;
-          #size-cells = <1>;
-
-          usb@34000000 {
-                compatible = "snps,dwc3";
-                reg = <0x34000000 0x10000>;
-                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                dr_mode = "peripheral";
-          };
+        compatible = "intel,keembay-dwc3";
+        clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>;
+        clock-names = "async_master", "ref", "alt_ref", "suspend";
+        ranges;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        usb@34000000 {
+            compatible = "snps,dwc3";
+            reg = <0x34000000 0x10000>;
+            interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+            dr_mode = "peripheral";
+        };
     };
diff --git a/dts/upstream/Bindings/usb/ite,it5205.yaml b/dts/upstream/Bindings/usb/ite,it5205.yaml
index 36ec4251b5f..889710733de 100644
--- a/dts/upstream/Bindings/usb/ite,it5205.yaml
+++ b/dts/upstream/Bindings/usb/ite,it5205.yaml
@@ -54,19 +54,19 @@ examples:
         #size-cells = <0>;
 
         typec-mux@48 {
-          compatible = "ite,it5205";
-          reg = <0x48>;
+            compatible = "ite,it5205";
+            reg = <0x48>;
 
-          mode-switch;
-          orientation-switch;
+            mode-switch;
+            orientation-switch;
 
-          vcc-supply = <&mt6359_vibr_ldo_reg>;
+            vcc-supply = <&mt6359_vibr_ldo_reg>;
 
-          port {
-            it5205_usbss_sbu: endpoint {
-              remote-endpoint = <&typec_controller>;
+            port {
+                it5205_usbss_sbu: endpoint {
+                    remote-endpoint = <&typec_controller>;
+                };
             };
-          };
         };
     };
 ...
diff --git a/dts/upstream/Bindings/usb/maxim,max33359.yaml b/dts/upstream/Bindings/usb/maxim,max33359.yaml
index 20b62228371..3de4dc40b79 100644
--- a/dts/upstream/Bindings/usb/maxim,max33359.yaml
+++ b/dts/upstream/Bindings/usb/maxim,max33359.yaml
@@ -13,8 +13,12 @@ description: Maxim TCPCI Type-C PD controller
 
 properties:
   compatible:
-    enum:
-      - maxim,max33359
+    oneOf:
+      - enum:
+          - maxim,max33359
+      - items:
+          - const: maxim,max77759-tcpci
+          - const: maxim,max33359
 
   reg:
     maxItems: 1
@@ -70,6 +74,7 @@ examples:
                                        PDO_FIXED_DUAL_ROLE)
                                        PDO_FIXED(9000, 2000, 0)>;
                 sink-bc12-completion-time-ms = <500>;
+                pd-revision = /bits/ 8 <0x03 0x01 0x01 0x08>;
             };
         };
     };
diff --git a/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml b/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
index 8e0f4ecc010..6edb1fc5044 100644
--- a/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
+++ b/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
@@ -50,18 +50,18 @@ additionalProperties: false
 
 examples:
   - |
-      #include <dt-bindings/gpio/gpio.h>
-      #include <dt-bindings/interrupt-controller/irq.h>
-      spi {
-            #address-cells = <1>;
-            #size-cells = <0>;
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
 
-            udc@0 {
-                  compatible = "maxim,max3420-udc";
-                  reg = <0>;
-                  interrupt-parent = <&gpio>;
-                  interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
-                  interrupt-names = "udc", "vbus";
-                  spi-max-frequency = <12500000>;
-            };
-      };
+        udc@0 {
+            compatible = "maxim,max3420-udc";
+            reg = <0>;
+            interrupt-parent = <&gpio>;
+            interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
+            interrupt-names = "udc", "vbus";
+            spi-max-frequency = <12500000>;
+        };
+    };
diff --git a/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml b/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
index 90296613b3a..c0e313c70bb 100644
--- a/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
+++ b/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
@@ -189,7 +189,7 @@ examples:
         #size-cells = <0>;
 
         ethernet@1 {
-                compatible = "usb955,9ff";
-                reg = <1>;
+            compatible = "usb955,9ff";
+            reg = <1>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/qcom,dwc3.yaml b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
index 935e204b607..a2b3cf625e5 100644
--- a/dts/upstream/Bindings/usb/qcom,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
@@ -16,6 +16,7 @@ properties:
           - qcom,ipq4019-dwc3
           - qcom,ipq5018-dwc3
           - qcom,ipq5332-dwc3
+          - qcom,ipq5424-dwc3
           - qcom,ipq6018-dwc3
           - qcom,ipq8064-dwc3
           - qcom,ipq8074-dwc3
@@ -26,6 +27,7 @@ properties:
           - qcom,msm8998-dwc3
           - qcom,qcm2290-dwc3
           - qcom,qcs404-dwc3
+          - qcom,qcs615-dwc3
           - qcom,qcs8300-dwc3
           - qcom,qdu1000-dwc3
           - qcom,sa8775p-dwc3
@@ -341,6 +343,7 @@ allOf:
           contains:
             enum:
               - qcom,qcm2290-dwc3
+              - qcom,qcs615-dwc3
               - qcom,sar2130p-dwc3
               - qcom,sc8180x-dwc3
               - qcom,sc8180x-dwc3-mp
@@ -453,8 +456,10 @@ allOf:
     then:
       properties:
         interrupts:
+          minItems: 3
           maxItems: 4
         interrupt-names:
+          minItems: 3
           items:
             - const: pwr_event
             - const: dp_hs_phy_irq
@@ -469,6 +474,7 @@ allOf:
               - qcom,ipq4019-dwc3
               - qcom,ipq8064-dwc3
               - qcom,msm8994-dwc3
+              - qcom,qcs615-dwc3
               - qcom,qcs8300-dwc3
               - qcom,qdu1000-dwc3
               - qcom,sa8775p-dwc3
diff --git a/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml b/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
index ff625600d9a..b87e139c29e 100644
--- a/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
+++ b/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
@@ -104,26 +104,26 @@ examples:
         #size-cells = <1>;
 
         usb3host: usb@85060000 {
-           compatible = "renesas,r9a09g011-xhci",
-                        "renesas,rzv2m-xhci";
-           reg = <0x85060000 0x2000>;
-           interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
-                    <&cpg CPG_MOD R9A09G011_USB_PCLK>;
-           clock-names = "axi", "reg";
-           power-domains = <&cpg>;
-           resets = <&cpg R9A09G011_USB_ARESETN_H>;
+            compatible = "renesas,r9a09g011-xhci",
+                         "renesas,rzv2m-xhci";
+            reg = <0x85060000 0x2000>;
+            interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
+                     <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+            clock-names = "axi", "reg";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A09G011_USB_ARESETN_H>;
         };
 
         usb3peri: usb3peri@85070000 {
-           compatible = "renesas,r9a09g011-usb3-peri",
-                        "renesas,rzv2m-usb3-peri";
-           reg = <0x85070000 0x400>;
-           interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
-                    <&cpg CPG_MOD R9A09G011_USB_PCLK>;
-           clock-names = "axi", "reg";
-           power-domains = <&cpg>;
-           resets = <&cpg R9A09G011_USB_ARESETN_P>;
+            compatible = "renesas,r9a09g011-usb3-peri",
+                         "renesas,rzv2m-usb3-peri";
+            reg = <0x85070000 0x400>;
+            interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
+                     <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+            clock-names = "axi", "reg";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A09G011_USB_ARESETN_P>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml b/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
index b2b811a0ade..4e56e4ffeaf 100644
--- a/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
+++ b/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
@@ -132,19 +132,19 @@ examples:
         usb-role-switch;
 
         ports {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        usb3_hs_ep: endpoint {
-                                remote-endpoint = <&hs_ep>;
-                        };
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+                usb3_hs_ep: endpoint {
+                    remote-endpoint = <&hs_ep>;
                 };
-                port@1 {
-                        reg = <1>;
-                        usb3_role_switch: endpoint {
-                                remote-endpoint = <&hd3ss3220_out_ep>;
-                        };
+            };
+            port@1 {
+                reg = <1>;
+                usb3_role_switch: endpoint {
+                    remote-endpoint = <&hd3ss3220_out_ep>;
                 };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/usb/renesas,usbhs.yaml b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
index b23ef29bf79..980f325341d 100644
--- a/dts/upstream/Bindings/usb/renesas,usbhs.yaml
+++ b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
@@ -26,6 +26,7 @@ properties:
               - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five
               - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
               - renesas,usbhs-r9a07g054 # RZ/V2L
+              - renesas,usbhs-r9a08g045 # RZ/G3S
           - const: renesas,rzg2l-usbhs
 
       - items:
@@ -130,6 +131,7 @@ allOf:
               - renesas,usbhs-r9a07g043
               - renesas,usbhs-r9a07g044
               - renesas,usbhs-r9a07g054
+              - renesas,usbhs-r9a08g045
     then:
       properties:
         interrupts:
diff --git a/dts/upstream/Bindings/usb/snps,dwc3-common.yaml b/dts/upstream/Bindings/usb/snps,dwc3-common.yaml
new file mode 100644
index 00000000000..c956053fd03
--- /dev/null
+++ b/dts/upstream/Bindings/usb/snps,dwc3-common.yaml
@@ -0,0 +1,415 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare USB3 Controller common properties
+
+maintainers:
+  - Felipe Balbi <balbi@kernel.org>
+
+description:
+  Defines the properties of the DWC3 core as being embedded in either an
+  vendor-specific implementation or as a standalone component.
+
+allOf:
+  - $ref: usb-drd.yaml#
+  - if:
+      properties:
+        dr_mode:
+          const: peripheral
+
+      required:
+        - dr_mode
+    then:
+      $ref: usb.yaml#
+    else:
+      $ref: usb-xhci.yaml#
+
+properties:
+  extcon:
+    maxItems: 1
+    deprecated: true
+
+  usb-phy:
+    minItems: 1
+    items:
+      - description: USB2/HS PHY
+      - description: USB3/SS PHY
+
+  phys:
+    minItems: 1
+    maxItems: 19
+
+  phy-names:
+    minItems: 1
+    maxItems: 19
+    oneOf:
+      - items:
+          enum: [ usb2-phy, usb3-phy ]
+      - items:
+          pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
+
+  snps,usb2-lpm-disable:
+    description: Indicate if we don't want to enable USB2 HW LPM for host
+      mode.
+    type: boolean
+
+  snps,usb3_lpm_capable:
+    description: Determines if platform is USB3 LPM capable
+    type: boolean
+
+  snps,usb2-gadget-lpm-disable:
+    description: Indicate if we don't want to enable USB2 HW LPM for gadget
+      mode.
+    type: boolean
+
+  snps,dis-start-transfer-quirk:
+    description:
+      When set, disable isoc START TRANSFER command failure SW work-around
+      for DWC_usb31 version 1.70a-ea06 and prior.
+    type: boolean
+
+  snps,disable_scramble_quirk:
+    description:
+      True when SW should disable data scrambling. Only really useful for FPGA
+      builds.
+    type: boolean
+
+  snps,has-lpm-erratum:
+    description: True when DWC3 was configured with LPM Erratum enabled
+    type: boolean
+
+  snps,lpm-nyet-threshold:
+    description: LPM NYET threshold
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  snps,u2exit_lfps_quirk:
+    description: Set if we want to enable u2exit lfps quirk
+    type: boolean
+
+  snps,u2ss_inp3_quirk:
+    description: Set if we enable P3 OK for U2/SS Inactive quirk
+    type: boolean
+
+  snps,req_p1p2p3_quirk:
+    description:
+      When set, the core will always request for P1/P2/P3 transition sequence.
+    type: boolean
+
+  snps,del_p1p2p3_quirk:
+    description:
+      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
+      occur.
+    type: boolean
+
+  snps,del_phy_power_chg_quirk:
+    description: When set core will delay PHY power change from P0 to P1/P2/P3.
+    type: boolean
+
+  snps,lfps_filter_quirk:
+    description: When set core will filter LFPS reception.
+    type: boolean
+
+  snps,rx_detect_poll_quirk:
+    description:
+      when set core will disable a 400us delay to start Polling LFPS after
+      RX.Detect.
+    type: boolean
+
+  snps,tx_de_emphasis_quirk:
+    description: When set core will set Tx de-emphasis value
+    type: boolean
+
+  snps,tx_de_emphasis:
+    description:
+      The value driven to the PHY is controlled by the LTSSM during USB3
+      Compliance mode.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum:
+      - 0 # -6dB de-emphasis
+      - 1 # -3.5dB de-emphasis
+      - 2 # No de-emphasis
+
+  snps,dis_u3_susphy_quirk:
+    description: When set core will disable USB3 suspend phy
+    type: boolean
+
+  snps,dis_u2_susphy_quirk:
+    description: When set core will disable USB2 suspend phy
+    type: boolean
+
+  snps,dis_enblslpm_quirk:
+    description:
+      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
+      to the PHY.
+    type: boolean
+
+  snps,dis-u1-entry-quirk:
+    description: Set if link entering into U1 needs to be disabled
+    type: boolean
+
+  snps,dis-u2-entry-quirk:
+    description: Set if link entering into U2 needs to be disabled
+    type: boolean
+
+  snps,dis_rxdet_inp3_quirk:
+    description:
+      When set core will disable receiver detection in PHY P3 power state.
+    type: boolean
+
+  snps,dis-u2-freeclk-exists-quirk:
+    description:
+      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
+      PHY doesn't provide a free-running PHY clock.
+    type: boolean
+
+  snps,dis-del-phy-power-chg-quirk:
+    description:
+      When set core will change PHY power from P0 to P1/P2/P3 without delay.
+    type: boolean
+
+  snps,dis-tx-ipgap-linecheck-quirk:
+    description: When set, disable u2mac linestate check during HS transmit
+    type: boolean
+
+  snps,parkmode-disable-ss-quirk:
+    description:
+      When set, all SuperSpeed bus instances in park mode are disabled.
+    type: boolean
+
+  snps,parkmode-disable-hs-quirk:
+    description:
+      When set, all HighSpeed bus instances in park mode are disabled.
+    type: boolean
+
+  snps,dis_metastability_quirk:
+    description:
+      When set, disable metastability workaround. CAUTION! Use only if you are
+      absolutely sure of it.
+    type: boolean
+
+  snps,dis-split-quirk:
+    description:
+      When set, change the way URBs are handled by the driver. Needed to
+      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
+    type: boolean
+
+  snps,gfladj-refclk-lpm-sel-quirk:
+    description:
+      When set, run the SOF/ITP counter based on ref_clk.
+    type: boolean
+
+  snps,resume-hs-terminations:
+    description:
+      Fix the issue of HS terminations CRC error on resume by enabling this
+      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
+      of resume. This option is to support certain legacy ULPI PHYs.
+    type: boolean
+
+  snps,ulpi-ext-vbus-drv:
+    description:
+      Some ULPI USB PHY does not support internal VBUS supply, and driving
+      the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
+      bit. When set, the xhci host will configure the USB2 PHY drives VBUS
+      with an external supply.
+    type: boolean
+
+  snps,is-utmi-l1-suspend:
+    description:
+      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
+      asserts utmi_sleep_n.
+    type: boolean
+
+  snps,hird-threshold:
+    description: HIRD threshold
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  snps,hsphy_interface:
+    description:
+      High-Speed PHY interface selection between UTMI+ and ULPI when the
+      DWC_USB3_HSPHY_INTERFACE has value 3.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [utmi, ulpi]
+
+  snps,quirk-frame-length-adjustment:
+    description:
+      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
+      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
+      incorrect.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 0x3f
+
+  snps,ref-clock-period-ns:
+    description:
+      Value for REFCLKPER field of GUCTL register for reference clock period in
+      nanoseconds, when the hardware set default does not match the actual
+      clock.
+
+      This binding is deprecated. Instead, provide an appropriate reference clock.
+    minimum: 8
+    maximum: 62
+    deprecated: true
+
+  snps,rx-thr-num-pkt:
+    description:
+      USB RX packet threshold count. In host mode, this field specifies
+      the space that must be available in the RX FIFO before the core can
+      start the corresponding USB RX transaction (burst).
+      In device mode, this field specifies the space that must be
+      available in the RX FIFO before the core can send ERDY for a
+      flow-controlled endpoint. It is only used for SuperSpeed.
+      The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
+      USB 3.0 Controller Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 15
+
+  snps,rx-max-burst:
+    description:
+      Max USB RX burst size. In host mode, this field specifies the
+      Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
+      bus is slower than the USB, RX FIFO can overrun during a long burst.
+      You can program a smaller value to this field to limit the RX burst
+      size that the core can perform. It only applies to SS Bulk,
+      Isochronous, and Interrupt IN endpoints in the host mode.
+      In device mode, this field specifies the NUMP value that is sent in
+      ERDY for an OUT endpoint.
+      The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
+      USB 3.0 Controller Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-thr-num-pkt:
+    description:
+      USB TX packet threshold count. This field specifies the number of
+      packets that must be in the TXFIFO before the core can start
+      transmission for the corresponding USB transaction (burst).
+      This count is valid in both host and device modes. It is only used
+      for SuperSpeed operation.
+      Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
+      Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 15
+
+  snps,tx-max-burst:
+    description:
+      Max USB TX burst size. When the system bus is slower than the USB,
+      TX FIFO can underrun during a long burst. Program a smaller value
+      to this field to limit the TX burst size that the core can execute.
+      In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
+      OUT endpoints. This value is not used in device mode.
+      Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
+      Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,rx-thr-num-pkt-prd:
+    description:
+      Periodic ESS RX packet threshold count (host mode only). Set this and
+      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.4) to enable periodic ESS RX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,rx-max-burst-prd:
+    description:
+      Max periodic ESS RX burst size (host mode only). Set this and
+      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.4) to enable periodic ESS RX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-thr-num-pkt-prd:
+    description:
+      Periodic ESS TX packet threshold count (host mode only). Set this and
+      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.3) to enable periodic ESS TX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-max-burst-prd:
+    description:
+      Max periodic ESS TX burst size (host mode only). Set this and
+      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.3) to enable periodic ESS TX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  tx-fifo-resize:
+    description: Determines if the TX fifos can be dynamically resized depending
+      on the number of IN endpoints used and if bursting is supported.  This
+      may help improve bandwidth on platforms with higher system latencies, as
+      increased fifo space allows for the controller to prefetch data into its
+      internal memory.
+    type: boolean
+
+  tx-fifo-max-num:
+    description: Specifies the max number of packets the txfifo resizing logic
+      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
+      higher the number, the more fifo space the txfifo resizing logic will
+      allocate for that endpoint.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 3
+
+  snps,incr-burst-type-adjustment:
+    description:
+      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
+      burst type enable and INCRx type. A single value means INCRX burst mode
+      enabled. If more than one value specified, undefined length INCR burst
+      type will be enabled with burst lengths utilized up to the maximum
+      of the values passed in this property.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 8
+    uniqueItems: true
+    items:
+      enum: [1, 4, 8, 16, 32, 64, 128, 256]
+
+  num-hc-interrupters:
+    maximum: 8
+    default: 1
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      This port is used with the 'usb-role-switch' property  to connect the
+      dwc3 to type C connector.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Those ports should be used with any connector to the data bus of this
+      controller using the OF graph bindings specified if the "usb-role-switch"
+      property is used.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: High Speed (HS) data bus.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Super Speed (SS) data bus.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable USB remote wakeup.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: true
+...
+
diff --git a/dts/upstream/Bindings/usb/snps,dwc3.yaml b/dts/upstream/Bindings/usb/snps,dwc3.yaml
index 1cd0ca90127..4380bb6fa2f 100644
--- a/dts/upstream/Bindings/usb/snps,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/snps,dwc3.yaml
@@ -15,18 +15,7 @@ description:
   compatible string.
 
 allOf:
-  - $ref: usb-drd.yaml#
-  - if:
-      properties:
-        dr_mode:
-          const: peripheral
-
-      required:
-        - dr_mode
-    then:
-      $ref: usb.yaml#
-    else:
-      $ref: usb-xhci.yaml#
+  - $ref: snps,dwc3-common.yaml#
 
 properties:
   compatible:
@@ -70,32 +59,9 @@ properties:
 
   dma-coherent: true
 
-  extcon:
-    maxItems: 1
-    deprecated: true
-
   iommus:
     maxItems: 1
 
-  usb-phy:
-    minItems: 1
-    items:
-      - description: USB2/HS PHY
-      - description: USB3/SS PHY
-
-  phys:
-    minItems: 1
-    maxItems: 19
-
-  phy-names:
-    minItems: 1
-    maxItems: 19
-    oneOf:
-      - items:
-          enum: [ usb2-phy, usb3-phy ]
-      - items:
-          pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
-
   power-domains:
     description:
       The DWC3 has 2 power-domains. The power management unit (PMU) and
@@ -109,361 +75,6 @@ properties:
   resets:
     minItems: 1
 
-  snps,usb2-lpm-disable:
-    description: Indicate if we don't want to enable USB2 HW LPM for host
-      mode.
-    type: boolean
-
-  snps,usb3_lpm_capable:
-    description: Determines if platform is USB3 LPM capable
-    type: boolean
-
-  snps,usb2-gadget-lpm-disable:
-    description: Indicate if we don't want to enable USB2 HW LPM for gadget
-      mode.
-    type: boolean
-
-  snps,dis-start-transfer-quirk:
-    description:
-      When set, disable isoc START TRANSFER command failure SW work-around
-      for DWC_usb31 version 1.70a-ea06 and prior.
-    type: boolean
-
-  snps,disable_scramble_quirk:
-    description:
-      True when SW should disable data scrambling. Only really useful for FPGA
-      builds.
-    type: boolean
-
-  snps,has-lpm-erratum:
-    description: True when DWC3 was configured with LPM Erratum enabled
-    type: boolean
-
-  snps,lpm-nyet-threshold:
-    description: LPM NYET threshold
-    $ref: /schemas/types.yaml#/definitions/uint8
-
-  snps,u2exit_lfps_quirk:
-    description: Set if we want to enable u2exit lfps quirk
-    type: boolean
-
-  snps,u2ss_inp3_quirk:
-    description: Set if we enable P3 OK for U2/SS Inactive quirk
-    type: boolean
-
-  snps,req_p1p2p3_quirk:
-    description:
-      When set, the core will always request for P1/P2/P3 transition sequence.
-    type: boolean
-
-  snps,del_p1p2p3_quirk:
-    description:
-      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
-      occur.
-    type: boolean
-
-  snps,del_phy_power_chg_quirk:
-    description: When set core will delay PHY power change from P0 to P1/P2/P3.
-    type: boolean
-
-  snps,lfps_filter_quirk:
-    description: When set core will filter LFPS reception.
-    type: boolean
-
-  snps,rx_detect_poll_quirk:
-    description:
-      when set core will disable a 400us delay to start Polling LFPS after
-      RX.Detect.
-    type: boolean
-
-  snps,tx_de_emphasis_quirk:
-    description: When set core will set Tx de-emphasis value
-    type: boolean
-
-  snps,tx_de_emphasis:
-    description:
-      The value driven to the PHY is controlled by the LTSSM during USB3
-      Compliance mode.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    enum:
-      - 0 # -6dB de-emphasis
-      - 1 # -3.5dB de-emphasis
-      - 2 # No de-emphasis
-
-  snps,dis_u3_susphy_quirk:
-    description: When set core will disable USB3 suspend phy
-    type: boolean
-
-  snps,dis_u2_susphy_quirk:
-    description: When set core will disable USB2 suspend phy
-    type: boolean
-
-  snps,dis_enblslpm_quirk:
-    description:
-      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
-      to the PHY.
-    type: boolean
-
-  snps,dis-u1-entry-quirk:
-    description: Set if link entering into U1 needs to be disabled
-    type: boolean
-
-  snps,dis-u2-entry-quirk:
-    description: Set if link entering into U2 needs to be disabled
-    type: boolean
-
-  snps,dis_rxdet_inp3_quirk:
-    description:
-      When set core will disable receiver detection in PHY P3 power state.
-    type: boolean
-
-  snps,dis-u2-freeclk-exists-quirk:
-    description:
-      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
-      PHY doesn't provide a free-running PHY clock.
-    type: boolean
-
-  snps,dis-del-phy-power-chg-quirk:
-    description:
-      When set core will change PHY power from P0 to P1/P2/P3 without delay.
-    type: boolean
-
-  snps,dis-tx-ipgap-linecheck-quirk:
-    description: When set, disable u2mac linestate check during HS transmit
-    type: boolean
-
-  snps,parkmode-disable-ss-quirk:
-    description:
-      When set, all SuperSpeed bus instances in park mode are disabled.
-    type: boolean
-
-  snps,parkmode-disable-hs-quirk:
-    description:
-      When set, all HighSpeed bus instances in park mode are disabled.
-    type: boolean
-
-  snps,dis_metastability_quirk:
-    description:
-      When set, disable metastability workaround. CAUTION! Use only if you are
-      absolutely sure of it.
-    type: boolean
-
-  snps,dis-split-quirk:
-    description:
-      When set, change the way URBs are handled by the driver. Needed to
-      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
-    type: boolean
-
-  snps,gfladj-refclk-lpm-sel-quirk:
-    description:
-      When set, run the SOF/ITP counter based on ref_clk.
-    type: boolean
-
-  snps,resume-hs-terminations:
-    description:
-      Fix the issue of HS terminations CRC error on resume by enabling this
-      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
-      of resume. This option is to support certain legacy ULPI PHYs.
-    type: boolean
-
-  snps,ulpi-ext-vbus-drv:
-    description:
-      Some ULPI USB PHY does not support internal VBUS supply, and driving
-      the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
-      bit. When set, the xhci host will configure the USB2 PHY drives VBUS
-      with an external supply.
-    type: boolean
-
-  snps,is-utmi-l1-suspend:
-    description:
-      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
-      asserts utmi_sleep_n.
-    type: boolean
-
-  snps,hird-threshold:
-    description: HIRD threshold
-    $ref: /schemas/types.yaml#/definitions/uint8
-
-  snps,hsphy_interface:
-    description:
-      High-Speed PHY interface selection between UTMI+ and ULPI when the
-      DWC_USB3_HSPHY_INTERFACE has value 3.
-    $ref: /schemas/types.yaml#/definitions/string
-    enum: [utmi, ulpi]
-
-  snps,quirk-frame-length-adjustment:
-    description:
-      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
-      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
-      incorrect.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 0x3f
-
-  snps,ref-clock-period-ns:
-    description:
-      Value for REFCLKPER field of GUCTL register for reference clock period in
-      nanoseconds, when the hardware set default does not match the actual
-      clock.
-
-      This binding is deprecated. Instead, provide an appropriate reference clock.
-    minimum: 8
-    maximum: 62
-    deprecated: true
-
-  snps,rx-thr-num-pkt:
-    description:
-      USB RX packet threshold count. In host mode, this field specifies
-      the space that must be available in the RX FIFO before the core can
-      start the corresponding USB RX transaction (burst).
-      In device mode, this field specifies the space that must be
-      available in the RX FIFO before the core can send ERDY for a
-      flow-controlled endpoint. It is only used for SuperSpeed.
-      The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
-      USB 3.0 Controller Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 15
-
-  snps,rx-max-burst:
-    description:
-      Max USB RX burst size. In host mode, this field specifies the
-      Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
-      bus is slower than the USB, RX FIFO can overrun during a long burst.
-      You can program a smaller value to this field to limit the RX burst
-      size that the core can perform. It only applies to SS Bulk,
-      Isochronous, and Interrupt IN endpoints in the host mode.
-      In device mode, this field specifies the NUMP value that is sent in
-      ERDY for an OUT endpoint.
-      The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
-      USB 3.0 Controller Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-thr-num-pkt:
-    description:
-      USB TX packet threshold count. This field specifies the number of
-      packets that must be in the TXFIFO before the core can start
-      transmission for the corresponding USB transaction (burst).
-      This count is valid in both host and device modes. It is only used
-      for SuperSpeed operation.
-      Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
-      Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 15
-
-  snps,tx-max-burst:
-    description:
-      Max USB TX burst size. When the system bus is slower than the USB,
-      TX FIFO can underrun during a long burst. Program a smaller value
-      to this field to limit the TX burst size that the core can execute.
-      In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
-      OUT endpoints. This value is not used in device mode.
-      Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
-      Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,rx-thr-num-pkt-prd:
-    description:
-      Periodic ESS RX packet threshold count (host mode only). Set this and
-      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.4) to enable periodic ESS RX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,rx-max-burst-prd:
-    description:
-      Max periodic ESS RX burst size (host mode only). Set this and
-      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.4) to enable periodic ESS RX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-thr-num-pkt-prd:
-    description:
-      Periodic ESS TX packet threshold count (host mode only). Set this and
-      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.3) to enable periodic ESS TX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-max-burst-prd:
-    description:
-      Max periodic ESS TX burst size (host mode only). Set this and
-      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.3) to enable periodic ESS TX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  tx-fifo-resize:
-    description: Determines if the TX fifos can be dynamically resized depending
-      on the number of IN endpoints used and if bursting is supported.  This
-      may help improve bandwidth on platforms with higher system latencies, as
-      increased fifo space allows for the controller to prefetch data into its
-      internal memory.
-    type: boolean
-
-  tx-fifo-max-num:
-    description: Specifies the max number of packets the txfifo resizing logic
-      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
-      higher the number, the more fifo space the txfifo resizing logic will
-      allocate for that endpoint.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 3
-
-  snps,incr-burst-type-adjustment:
-    description:
-      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
-      burst type enable and INCRx type. A single value means INCRX burst mode
-      enabled. If more than one value specified, undefined length INCR burst
-      type will be enabled with burst lengths utilized up to the maximum
-      of the values passed in this property.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-    minItems: 1
-    maxItems: 8
-    uniqueItems: true
-    items:
-      enum: [1, 4, 8, 16, 32, 64, 128, 256]
-
-  num-hc-interrupters:
-    maximum: 8
-    default: 1
-
-  port:
-    $ref: /schemas/graph.yaml#/properties/port
-    description:
-      This port is used with the 'usb-role-switch' property  to connect the
-      dwc3 to type C connector.
-
-  ports:
-    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      Those ports should be used with any connector to the data bus of this
-      controller using the OF graph bindings specified if the "usb-role-switch"
-      property is used.
-
-    properties:
-      port@0:
-        $ref: /schemas/graph.yaml#/properties/port
-        description: High Speed (HS) data bus.
-
-      port@1:
-        $ref: /schemas/graph.yaml#/properties/port
-        description: Super Speed (SS) data bus.
-
-  wakeup-source:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Enable USB remote wakeup.
-
 unevaluatedProperties: false
 
 required:
diff --git a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
index 54c6586cb56..bec1c8047bc 100644
--- a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
+++ b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
@@ -56,26 +56,26 @@ examples:
         #size-cells = <0>;
 
         hd3ss3220@47 {
-                compatible = "ti,hd3ss3220";
-                reg = <0x47>;
-                interrupt-parent = <&gpio6>;
-                interrupts = <3>;
+            compatible = "ti,hd3ss3220";
+            reg = <0x47>;
+            interrupt-parent = <&gpio6>;
+            interrupts = <3>;
 
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        port@0 {
-                                reg = <0>;
-                                hd3ss3220_in_ep: endpoint {
-                                        remote-endpoint = <&ss_ep>;
-                                };
-                        };
-                        port@1 {
-                                reg = <1>;
-                                hd3ss3220_out_ep: endpoint {
-                                        remote-endpoint = <&usb3_role_switch>;
-                                };
-                        };
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                    reg = <0>;
+                    hd3ss3220_in_ep: endpoint {
+                        remote-endpoint = <&ss_ep>;
+                    };
                 };
+                port@1 {
+                    reg = <1>;
+                    hd3ss3220_out_ep: endpoint {
+                        remote-endpoint = <&usb3_role_switch>;
+                    };
+                };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml b/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
index ddda734f36f..c4a91b3d661 100644
--- a/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
+++ b/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
@@ -48,8 +48,8 @@ examples:
         device_type = "pci";
 
         usb@0 {
-              compatible = "pci104c,8241";
-              reg = <0x0 0x0 0x0 0x0 0x0>;
-              ti,pwron-active-high;
+            compatible = "pci104c,8241";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            ti,pwron-active-high;
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,usb8020b.yaml b/dts/upstream/Bindings/usb/ti,usb8020b.yaml
index 8ef117793e1..61217da8b2f 100644
--- a/dts/upstream/Bindings/usb/ti,usb8020b.yaml
+++ b/dts/upstream/Bindings/usb/ti,usb8020b.yaml
@@ -51,19 +51,19 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb451,8027";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-          vdd-supply = <&usb_hub_fixed_3v3>;
+            compatible = "usb451,8027";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&usb_hub_fixed_3v3>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb451,8025";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-          vdd-supply = <&usb_hub_fixed_3v3>;
+            compatible = "usb451,8025";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&usb_hub_fixed_3v3>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,usb8041.yaml b/dts/upstream/Bindings/usb/ti,usb8041.yaml
index c2e29bd61e1..bce730a5e23 100644
--- a/dts/upstream/Bindings/usb/ti,usb8041.yaml
+++ b/dts/upstream/Bindings/usb/ti,usb8041.yaml
@@ -51,17 +51,17 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb451,8142";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            compatible = "usb451,8142";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb451,8140";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            compatible = "usb451,8140";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
         };
     };
diff --git a/dts/upstream/Bindings/vendor-prefixes.yaml b/dts/upstream/Bindings/vendor-prefixes.yaml
index da01616802c..5079ca6ce1d 100644
--- a/dts/upstream/Bindings/vendor-prefixes.yaml
+++ b/dts/upstream/Bindings/vendor-prefixes.yaml
@@ -218,6 +218,8 @@ patternProperties:
     description: Shenzhen BigTree Tech Co., LTD
   "^bitmain,.*":
     description: Bitmain Technologies
+  "^blaize,.*":
+    description: Blaize, Inc.
   "^blutek,.*":
     description: BluTek Power
   "^boe,.*":
@@ -575,6 +577,8 @@ patternProperties:
     description: Gemtek Technology Co., Ltd.
   "^genesys,.*":
     description: Genesys Logic, Inc.
+  "^genexis,.*":
+    description: Genexis BV/AB
   "^geniatech,.*":
     description: Geniatech, Inc.
   "^giantec,.*":
@@ -1204,6 +1208,8 @@ patternProperties:
     description: PulsedLight, Inc
   "^purism,.*":
     description: Purism, SPC
+  "^puya,.*":
+    description: Puya Semiconductor (Shanghai) Co., Ltd.
   "^qca,.*":
     description: Qualcomm Atheros, Inc.
   "^qcom,.*":
@@ -1336,6 +1342,8 @@ patternProperties:
     description: Siemens AG
   "^sifive,.*":
     description: SiFive, Inc.
+  "^siflower,.*":
+    description: Shanghai Siflower Communication Co.
   "^sigma,.*":
     description: Sigma Designs, Inc.
   "^sii,.*":
@@ -1524,6 +1532,8 @@ patternProperties:
     description: Topeet
   "^topic,.*":
     description: Topic Embedded Systems
+  "^topland,.*":
+    description: Topland Electronics (H.K) Co., Ltd.
   "^toppoly,.*":
     description: TPO (deprecated, use tpo)
     deprecated: true
diff --git a/dts/upstream/Bindings/w1/maxim,ds2482.yaml b/dts/upstream/Bindings/w1/maxim,ds2482.yaml
index 422becc6e1f..fe6b3f9a3f8 100644
--- a/dts/upstream/Bindings/w1/maxim,ds2482.yaml
+++ b/dts/upstream/Bindings/w1/maxim,ds2482.yaml
@@ -25,6 +25,8 @@ properties:
   reg:
     maxItems: 1
 
+  vcc-supply: true
+
 required:
   - compatible
   - reg
diff --git a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
index 34896a39fa9..49e2b807db0 100644
--- a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
@@ -20,6 +20,7 @@ properties:
               - qcom,kpss-wdt-ipq4019
               - qcom,apss-wdt-ipq5018
               - qcom,apss-wdt-ipq5332
+              - qcom,apss-wdt-ipq5424
               - qcom,apss-wdt-ipq9574
               - qcom,apss-wdt-msm8226
               - qcom,apss-wdt-msm8974
diff --git a/dts/upstream/include/dt-bindings/arm/qcom,ids.h b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
index e850dc3a1ad..1b3e0176dcb 100644
--- a/dts/upstream/include/dt-bindings/arm/qcom,ids.h
+++ b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
@@ -284,6 +284,7 @@
 #define QCOM_ID_QCS9100			667
 #define QCOM_ID_QCS8300			674
 #define QCOM_ID_QCS8275			675
+#define QCOM_ID_QCS9075			676
 #define QCOM_ID_QCS615			680
 
 /*
diff --git a/dts/upstream/include/dt-bindings/clock/at91.h b/dts/upstream/include/dt-bindings/clock/at91.h
index 6ede88c3992..f2a7b7d39c0 100644
--- a/dts/upstream/include/dt-bindings/clock/at91.h
+++ b/dts/upstream/include/dt-bindings/clock/at91.h
@@ -42,6 +42,10 @@
 #define PMC_PLLADIV2		(PMC_MAIN + 11)
 #define PMC_LVDSPLL		(PMC_MAIN + 12)
 
+/* SAMA7D65 */
+#define PMC_MCK3		(PMC_MAIN + 13)
+#define PMC_MCK5		(PMC_MAIN + 14)
+
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
@@ -55,4 +59,8 @@
 #define AT91_PMC_GCKRDY		24		/* Generated Clocks */
 #endif
 
+/* Slow clock. */
+#define SCKC_MD_SLCK		0
+#define SCKC_TD_SLCK		1
+
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/en7523-clk.h b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
index 717d23a5e5a..edfa64045f5 100644
--- a/dts/upstream/include/dt-bindings/clock/en7523-clk.h
+++ b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
@@ -12,6 +12,6 @@
 #define EN7523_CLK_CRYPTO	6
 #define EN7523_CLK_PCIE		7
 
-#define EN7523_NUM_CLOCKS	8
+#define EN7581_CLK_EMMC		8
 
 #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
diff --git a/dts/upstream/include/dt-bindings/clock/imx93-clock.h b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
index 6c685067288..c393fad3a34 100644
--- a/dts/upstream/include/dt-bindings/clock/imx93-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
@@ -209,5 +209,6 @@
 #define IMX91_CLK_ENET2_REGULAR     204
 #define IMX91_CLK_ENET2_REGULAR_GATE		205
 #define IMX91_CLK_ENET1_QOS_TSN_GATE		206
+#define IMX93_CLK_SPDIF_IPG		207
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
new file mode 100644
index 00000000000..936e92b3b62
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ9574. */
+#define XO_24MHZ_CLK			1
+#define SLEEP_32KHZ_CLK			2
+#define PCS_31P25MHZ_CLK		3
+#define NSS_1200MHZ_CLK			4
+#define PPE_353MHZ_CLK			5
+#define ETH0_50MHZ_CLK			6
+#define ETH1_50MHZ_CLK			7
+#define ETH2_50MHZ_CLK			8
+#define ETH_25MHZ_CLK			9
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
index 755ce7a71c7..c15ad16923b 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
@@ -12,7 +12,6 @@
 #define GPLL2					2
 #define GPLL2_OUT_MAIN                          3
 #define GCC_SLEEP_CLK_SRC			4
-#define GCC_APSS_DBG_CLK                        5
 #define GCC_USB0_EUD_AT_CLK			6
 #define GCC_PCIE0_AXI_M_CLK_SRC			7
 #define GCC_PCIE0_AXI_M_CLK			8
@@ -152,5 +151,6 @@
 #define GCC_PCIE3_RCHNG_CLK_SRC			142
 #define GCC_PCIE3_RCHNG_CLK			143
 #define GCC_IM_SLEEP_CLK			144
+#define GCC_XO_CLK				145
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 81714fc859c..717431d735c 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,7 @@
 #define VCAP_CLK					124
 #define VCAP_NPL_CLK					125
 #define PLL15						126
+#define DSI2_PIXEL_LVDS_SRC				127
+#define LVDS_CLK					128
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h
new file mode 100644
index 00000000000..9704091636b
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
+
+/* GCC clocks */
+#define GPLL0_OUT_AUX2_DIV					0
+#define GPLL3_OUT_AUX2_DIV					1
+#define GPLL0							2
+#define GPLL3							3
+#define GPLL4							4
+#define GPLL6							5
+#define GPLL6_OUT_MAIN						6
+#define GPLL7							7
+#define GPLL8							8
+#define GPLL8_OUT_MAIN						9
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				10
+#define GCC_AGGRE_USB2_SEC_AXI_CLK				11
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				12
+#define GCC_AHB2PHY_EAST_CLK					13
+#define GCC_AHB2PHY_WEST_CLK					14
+#define GCC_BOOT_ROM_AHB_CLK					15
+#define GCC_CAMERA_AHB_CLK					16
+#define GCC_CAMERA_HF_AXI_CLK					17
+#define GCC_CAMERA_XO_CLK					18
+#define GCC_CE1_AHB_CLK						19
+#define GCC_CE1_AXI_CLK						20
+#define GCC_CE1_CLK						21
+#define GCC_CFG_NOC_USB2_SEC_AXI_CLK				22
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				23
+#define GCC_CPUSS_AHB_CLK					24
+#define GCC_CPUSS_AHB_CLK_SRC					25
+#define GCC_CPUSS_GNOC_CLK					26
+#define GCC_DDRSS_GPU_AXI_CLK					27
+#define GCC_DISP_AHB_CLK					28
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				29
+#define GCC_DISP_HF_AXI_CLK					30
+#define GCC_DISP_XO_CLK						31
+#define GCC_EMAC_AXI_CLK					32
+#define GCC_EMAC_PTP_CLK					33
+#define GCC_EMAC_PTP_CLK_SRC					34
+#define GCC_EMAC_RGMII_CLK					35
+#define GCC_EMAC_RGMII_CLK_SRC					36
+#define GCC_EMAC_SLV_AHB_CLK					37
+#define GCC_GP1_CLK						38
+#define GCC_GP1_CLK_SRC						39
+#define GCC_GP2_CLK						40
+#define GCC_GP2_CLK_SRC						41
+#define GCC_GP3_CLK						42
+#define GCC_GP3_CLK_SRC						43
+#define GCC_GPU_CFG_AHB_CLK					44
+#define GCC_GPU_GPLL0_CLK_SRC					45
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				46
+#define GCC_GPU_IREF_CLK					47
+#define GCC_GPU_MEMNOC_GFX_CLK					48
+#define GCC_GPU_SNOC_DVM_GFX_CLK				49
+#define GCC_PCIE0_PHY_REFGEN_CLK				50
+#define GCC_PCIE_0_AUX_CLK					51
+#define GCC_PCIE_0_AUX_CLK_SRC					52
+#define GCC_PCIE_0_CFG_AHB_CLK					53
+#define GCC_PCIE_0_CLKREF_CLK					54
+#define GCC_PCIE_0_MSTR_AXI_CLK					55
+#define GCC_PCIE_0_PIPE_CLK					56
+#define GCC_PCIE_0_SLV_AXI_CLK					57
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				58
+#define GCC_PCIE_PHY_AUX_CLK					59
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC				60
+#define GCC_PDM2_CLK						61
+#define GCC_PDM2_CLK_SRC					62
+#define GCC_PDM_AHB_CLK						63
+#define GCC_PDM_XO4_CLK						64
+#define GCC_PRNG_AHB_CLK					65
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				66
+#define GCC_QMIP_DISP_AHB_CLK					67
+#define GCC_QMIP_PCIE_AHB_CLK					68
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				69
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				70
+#define GCC_QSPI_CORE_CLK					71
+#define GCC_QSPI_CORE_CLK_SRC					72
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				73
+#define GCC_QUPV3_WRAP0_CORE_CLK				74
+#define GCC_QUPV3_WRAP0_S0_CLK					75
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				76
+#define GCC_QUPV3_WRAP0_S1_CLK					77
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				78
+#define GCC_QUPV3_WRAP0_S2_CLK					79
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				80
+#define GCC_QUPV3_WRAP0_S3_CLK					81
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				82
+#define GCC_QUPV3_WRAP0_S4_CLK					83
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				84
+#define GCC_QUPV3_WRAP0_S5_CLK					85
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				86
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				87
+#define GCC_QUPV3_WRAP1_CORE_CLK				88
+#define GCC_QUPV3_WRAP1_S0_CLK					89
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				90
+#define GCC_QUPV3_WRAP1_S1_CLK					91
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				92
+#define GCC_QUPV3_WRAP1_S2_CLK					93
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				94
+#define GCC_QUPV3_WRAP1_S3_CLK					95
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				96
+#define GCC_QUPV3_WRAP1_S4_CLK					97
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				98
+#define GCC_QUPV3_WRAP1_S5_CLK					99
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				100
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				101
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				102
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				103
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				104
+#define GCC_RX1_USB2_CLKREF_CLK					105
+#define GCC_RX3_USB2_CLKREF_CLK					106
+#define GCC_SDCC1_AHB_CLK					107
+#define GCC_SDCC1_APPS_CLK					108
+#define GCC_SDCC1_APPS_CLK_SRC					109
+#define GCC_SDCC1_ICE_CORE_CLK					110
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				111
+#define GCC_SDCC2_AHB_CLK					112
+#define GCC_SDCC2_APPS_CLK					113
+#define GCC_SDCC2_APPS_CLK_SRC					114
+#define GCC_SDR_CORE_CLK					115
+#define GCC_SDR_CSR_HCLK					116
+#define GCC_SDR_PRI_MI2S_CLK					117
+#define GCC_SDR_SEC_MI2S_CLK					118
+#define GCC_SDR_WR0_MEM_CLK					119
+#define GCC_SDR_WR1_MEM_CLK					120
+#define GCC_SDR_WR2_MEM_CLK					121
+#define GCC_SYS_NOC_CPUSS_AHB_CLK				122
+#define GCC_UFS_CARD_CLKREF_CLK					123
+#define GCC_UFS_MEM_CLKREF_CLK					124
+#define GCC_UFS_PHY_AHB_CLK					125
+#define GCC_UFS_PHY_AXI_CLK					126
+#define GCC_UFS_PHY_AXI_CLK_SRC					127
+#define GCC_UFS_PHY_ICE_CORE_CLK				128
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				129
+#define GCC_UFS_PHY_PHY_AUX_CLK					130
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				131
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				132
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				133
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				134
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				135
+#define GCC_USB20_SEC_MASTER_CLK				136
+#define GCC_USB20_SEC_MASTER_CLK_SRC				137
+#define GCC_USB20_SEC_MOCK_UTMI_CLK				138
+#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC				139
+#define GCC_USB20_SEC_SLEEP_CLK					140
+#define GCC_USB2_PRIM_CLKREF_CLK				141
+#define GCC_USB2_SEC_CLKREF_CLK					142
+#define GCC_USB2_SEC_PHY_AUX_CLK				143
+#define GCC_USB2_SEC_PHY_AUX_CLK_SRC				144
+#define GCC_USB2_SEC_PHY_COM_AUX_CLK				145
+#define GCC_USB2_SEC_PHY_PIPE_CLK				146
+#define GCC_USB30_PRIM_MASTER_CLK				147
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				148
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				149
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			150
+#define GCC_USB30_PRIM_SLEEP_CLK				151
+#define GCC_USB3_PRIM_CLKREF_CLK				152
+#define GCC_USB3_PRIM_PHY_AUX_CLK				153
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				154
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				155
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				156
+#define GCC_USB3_SEC_CLKREF_CLK					157
+#define GCC_VIDEO_AHB_CLK					158
+#define GCC_VIDEO_AXI0_CLK					159
+#define GCC_VIDEO_XO_CLK					160
+#define GCC_VSENSOR_CLK_SRC					161
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			162
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				163
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				164
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				165
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			166
+
+/* GCC Resets */
+#define GCC_EMAC_BCR                                            0
+#define GCC_QUSB2PHY_PRIM_BCR                                   1
+#define GCC_QUSB2PHY_SEC_BCR                                    2
+#define GCC_USB30_PRIM_BCR                                      3
+#define GCC_USB2_PHY_SEC_BCR                                    4
+#define GCC_USB3_DP_PHY_SEC_BCR                                 5
+#define GCC_USB3PHY_PHY_SEC_BCR                                 6
+#define GCC_PCIE_0_BCR                                          7
+#define GCC_PCIE_0_PHY_BCR                                      8
+#define GCC_PCIE_PHY_BCR                                        9
+#define GCC_PCIE_PHY_COM_BCR                                    10
+#define GCC_UFS_PHY_BCR                                         11
+#define GCC_USB20_SEC_BCR                                       12
+#define GCC_USB3_PHY_PRIM_SP0_BCR                               13
+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR                            14
+#define GCC_SDCC1_BCR                                           15
+#define GCC_SDCC2_BCR                                           16
+
+/* GCC power domains */
+#define EMAC_GDSC						0
+#define PCIE_0_GDSC						1
+#define UFS_PHY_GDSC						2
+#define USB20_SEC_GDSC						3
+#define USB30_PRIM_GDSC						4
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC			5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC			6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC			7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC			8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC			10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			11
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h
new file mode 100644
index 00000000000..fc535c84785
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H
+#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H
+
+#include "qcom,sa8775p-camcc.h"
+
+/* QCS8300 introduces below new clocks compared to SA8775P */
+
+/* CAM_CC clocks */
+#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK				86
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h
new file mode 100644
index 00000000000..afa187467b4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H
+#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H
+
+#include "qcom,sa8775p-gpucc.h"
+
+/* QCS8300 introduces below new clocks compared to SA8775P */
+
+/* GPU_CC clocks */
+#define GPU_CC_CX_ACCU_SHIFT_CLK		23
+#define GPU_CC_GX_ACCU_SHIFT_CLK		24
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
new file mode 100644
index 00000000000..799274517c9
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+
+/* LPASS CC */
+#define LPASS_SWR_TX_CONFIG_CGCR		0
+
+/* LPASS_AUDIO CC */
+#define LPASS_AUDIO_SWR_RX_CGCR			0
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h
new file mode 100644
index 00000000000..dafb5069c96
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK					0
+#define DISP_CC_ESYNC0_CLK_SRC					1
+#define DISP_CC_ESYNC1_CLK					2
+#define DISP_CC_ESYNC1_CLK_SRC					3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK				4
+#define DISP_CC_MDSS_AHB1_CLK					5
+#define DISP_CC_MDSS_AHB_CLK					6
+#define DISP_CC_MDSS_AHB_CLK_SRC				7
+#define DISP_CC_MDSS_BYTE0_CLK					8
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				9
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				10
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				11
+#define DISP_CC_MDSS_BYTE1_CLK					12
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				13
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				14
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				15
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				16
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				17
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				18
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				19
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				20
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			21
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			22
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				23
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			24
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				25
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			26
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		27
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				28
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				29
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				30
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				31
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				32
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			33
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			34
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				35
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			36
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				37
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			38
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		39
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				40
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				41
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				42
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				43
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				44
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			45
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			46
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				47
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			48
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				49
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			50
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				51
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				52
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				53
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				54
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				55
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			56
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			57
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				58
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			59
+#define DISP_CC_MDSS_ESC0_CLK					60
+#define DISP_CC_MDSS_ESC0_CLK_SRC				61
+#define DISP_CC_MDSS_ESC1_CLK					62
+#define DISP_CC_MDSS_ESC1_CLK_SRC				63
+#define DISP_CC_MDSS_MDP1_CLK					64
+#define DISP_CC_MDSS_MDP_CLK					65
+#define DISP_CC_MDSS_MDP_CLK_SRC				66
+#define DISP_CC_MDSS_MDP_LUT1_CLK				67
+#define DISP_CC_MDSS_MDP_LUT_CLK				68
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				69
+#define DISP_CC_MDSS_PCLK0_CLK					70
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				71
+#define DISP_CC_MDSS_PCLK1_CLK					72
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				73
+#define DISP_CC_MDSS_PCLK2_CLK					74
+#define DISP_CC_MDSS_PCLK2_CLK_SRC				75
+#define DISP_CC_MDSS_RSCC_AHB_CLK				76
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				77
+#define DISP_CC_MDSS_VSYNC1_CLK					78
+#define DISP_CC_MDSS_VSYNC_CLK					79
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				80
+#define DISP_CC_OSC_CLK						81
+#define DISP_CC_OSC_CLK_SRC					82
+#define DISP_CC_PLL0						83
+#define DISP_CC_PLL1						84
+#define DISP_CC_PLL2						85
+#define DISP_CC_SLEEP_CLK					86
+#define DISP_CC_SLEEP_CLK_SRC					87
+#define DISP_CC_XO_CLK						88
+#define DISP_CC_XO_CLK_SRC					89
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+#define MDSS_INT2_GDSC						1
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h
new file mode 100644
index 00000000000..e234595d7f4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
+#define GCC_BOOT_ROM_AHB_CLK					4
+#define GCC_CAM_BIST_MCLK_AHB_CLK				5
+#define GCC_CAMERA_AHB_CLK					6
+#define GCC_CAMERA_HF_AXI_CLK					7
+#define GCC_CAMERA_SF_AXI_CLK					8
+#define GCC_CAMERA_XO_CLK					9
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				10
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				11
+#define GCC_CNOC_PCIE_SF_AXI_CLK				12
+#define GCC_DDRSS_GPU_AXI_CLK					13
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				14
+#define GCC_DISP_AHB_CLK					15
+#define GCC_DISP_HF_AXI_CLK					16
+#define GCC_EVA_AHB_CLK						17
+#define GCC_EVA_AXI0_CLK					18
+#define GCC_EVA_AXI0C_CLK					19
+#define GCC_EVA_XO_CLK						20
+#define GCC_GP1_CLK						21
+#define GCC_GP1_CLK_SRC						22
+#define GCC_GP2_CLK						23
+#define GCC_GP2_CLK_SRC						24
+#define GCC_GP3_CLK						25
+#define GCC_GP3_CLK_SRC						26
+#define GCC_GPLL0						27
+#define GCC_GPLL0_OUT_EVEN					28
+#define GCC_GPLL1						29
+#define GCC_GPLL4						30
+#define GCC_GPLL7						31
+#define GCC_GPLL9						32
+#define GCC_GPU_CFG_AHB_CLK					33
+#define GCC_GPU_GEMNOC_GFX_CLK					34
+#define GCC_GPU_GPLL0_CLK_SRC					35
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				36
+#define GCC_PCIE_0_AUX_CLK					37
+#define GCC_PCIE_0_AUX_CLK_SRC					38
+#define GCC_PCIE_0_CFG_AHB_CLK					39
+#define GCC_PCIE_0_MSTR_AXI_CLK					40
+#define GCC_PCIE_0_PHY_RCHNG_CLK				41
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				42
+#define GCC_PCIE_0_PIPE_CLK					43
+#define GCC_PCIE_0_PIPE_CLK_SRC					44
+#define GCC_PCIE_0_SLV_AXI_CLK					45
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				46
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				47
+#define GCC_PCIE_RSCC_XO_CLK					48
+#define GCC_PDM2_CLK						49
+#define GCC_PDM2_CLK_SRC					50
+#define GCC_PDM_AHB_CLK						51
+#define GCC_PDM_XO4_CLK						52
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK				53
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				54
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				55
+#define GCC_QMIP_GPU_AHB_CLK					56
+#define GCC_QMIP_PCIE_AHB_CLK					57
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				58
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				59
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				60
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				61
+#define GCC_QUPV3_I2C_CORE_CLK					62
+#define GCC_QUPV3_I2C_S0_CLK					63
+#define GCC_QUPV3_I2C_S0_CLK_SRC				64
+#define GCC_QUPV3_I2C_S1_CLK					65
+#define GCC_QUPV3_I2C_S1_CLK_SRC				66
+#define GCC_QUPV3_I2C_S2_CLK					67
+#define GCC_QUPV3_I2C_S2_CLK_SRC				68
+#define GCC_QUPV3_I2C_S3_CLK					69
+#define GCC_QUPV3_I2C_S3_CLK_SRC				70
+#define GCC_QUPV3_I2C_S4_CLK					71
+#define GCC_QUPV3_I2C_S4_CLK_SRC				72
+#define GCC_QUPV3_I2C_S5_CLK					73
+#define GCC_QUPV3_I2C_S5_CLK_SRC				74
+#define GCC_QUPV3_I2C_S6_CLK					75
+#define GCC_QUPV3_I2C_S6_CLK_SRC				76
+#define GCC_QUPV3_I2C_S7_CLK					77
+#define GCC_QUPV3_I2C_S7_CLK_SRC				78
+#define GCC_QUPV3_I2C_S8_CLK					79
+#define GCC_QUPV3_I2C_S8_CLK_SRC				80
+#define GCC_QUPV3_I2C_S9_CLK					81
+#define GCC_QUPV3_I2C_S9_CLK_SRC				82
+#define GCC_QUPV3_I2C_S_AHB_CLK					83
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				84
+#define GCC_QUPV3_WRAP1_CORE_CLK				85
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				86
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			87
+#define GCC_QUPV3_WRAP1_S0_CLK					88
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				89
+#define GCC_QUPV3_WRAP1_S1_CLK					90
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				91
+#define GCC_QUPV3_WRAP1_S2_CLK					92
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				93
+#define GCC_QUPV3_WRAP1_S3_CLK					94
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				95
+#define GCC_QUPV3_WRAP1_S4_CLK					96
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_S5_CLK					98
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				99
+#define GCC_QUPV3_WRAP1_S6_CLK					100
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				101
+#define GCC_QUPV3_WRAP1_S7_CLK					102
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				103
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				104
+#define GCC_QUPV3_WRAP2_CORE_CLK				105
+#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC			106
+#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK				107
+#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK				108
+#define GCC_QUPV3_WRAP2_S0_CLK					109
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				110
+#define GCC_QUPV3_WRAP2_S1_CLK					111
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				112
+#define GCC_QUPV3_WRAP2_S2_CLK					113
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				114
+#define GCC_QUPV3_WRAP2_S3_CLK					115
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				116
+#define GCC_QUPV3_WRAP2_S4_CLK					117
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				118
+#define GCC_QUPV3_WRAP2_S5_CLK					119
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				120
+#define GCC_QUPV3_WRAP2_S6_CLK					121
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				122
+#define GCC_QUPV3_WRAP2_S7_CLK					123
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				124
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				125
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				126
+#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK				127
+#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK				128
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				129
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				130
+#define GCC_SDCC2_AHB_CLK					131
+#define GCC_SDCC2_APPS_CLK					132
+#define GCC_SDCC2_APPS_CLK_SRC					133
+#define GCC_SDCC4_AHB_CLK					134
+#define GCC_SDCC4_APPS_CLK					135
+#define GCC_SDCC4_APPS_CLK_SRC					136
+#define GCC_UFS_PHY_AHB_CLK					137
+#define GCC_UFS_PHY_AXI_CLK					138
+#define GCC_UFS_PHY_AXI_CLK_SRC					139
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				140
+#define GCC_UFS_PHY_ICE_CORE_CLK				141
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				142
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				143
+#define GCC_UFS_PHY_PHY_AUX_CLK					144
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				145
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				146
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				147
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				148
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				149
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				150
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				151
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				152
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				153
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				154
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			155
+#define GCC_USB30_PRIM_MASTER_CLK				156
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				157
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				158
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			159
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		160
+#define GCC_USB30_PRIM_SLEEP_CLK				161
+#define GCC_USB3_PRIM_PHY_AUX_CLK				162
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				163
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				164
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				165
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				166
+#define GCC_VIDEO_AHB_CLK					167
+#define GCC_VIDEO_AXI0_CLK					168
+#define GCC_VIDEO_AXI1_CLK					169
+#define GCC_VIDEO_XO_CLK					170
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC						0
+#define GCC_PCIE_0_PHY_GDSC					1
+#define GCC_UFS_MEM_PHY_GDSC					2
+#define GCC_UFS_PHY_GDSC					3
+#define GCC_USB30_PRIM_GDSC					4
+#define GCC_USB3_PHY_GDSC					5
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_EVA_BCR						2
+#define GCC_GPU_BCR						3
+#define GCC_PCIE_0_BCR						4
+#define GCC_PCIE_0_LINK_DOWN_BCR				5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
+#define GCC_PCIE_0_PHY_BCR					7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
+#define GCC_PCIE_PHY_BCR					9
+#define GCC_PCIE_PHY_CFG_AHB_BCR				10
+#define GCC_PCIE_PHY_COM_BCR					11
+#define GCC_PCIE_RSCC_BCR					12
+#define GCC_PDM_BCR						13
+#define GCC_QUPV3_WRAPPER_1_BCR					14
+#define GCC_QUPV3_WRAPPER_2_BCR					15
+#define GCC_QUPV3_WRAPPER_I2C_BCR				16
+#define GCC_QUSB2PHY_PRIM_BCR					17
+#define GCC_QUSB2PHY_SEC_BCR					18
+#define GCC_SDCC2_BCR						19
+#define GCC_SDCC4_BCR						20
+#define GCC_UFS_PHY_BCR						21
+#define GCC_USB30_PRIM_BCR					22
+#define GCC_USB3_DP_PHY_PRIM_BCR				23
+#define GCC_USB3_DP_PHY_SEC_BCR					24
+#define GCC_USB3_PHY_PRIM_BCR					25
+#define GCC_USB3_PHY_SEC_BCR					26
+#define GCC_USB3PHY_PHY_PRIM_BCR				27
+#define GCC_USB3PHY_PHY_SEC_BCR					28
+#define GCC_VIDEO_AXI0_CLK_ARES					29
+#define GCC_VIDEO_AXI1_CLK_ARES					30
+#define GCC_VIDEO_BCR						31
+#define GCC_EVA_AXI0_CLK_ARES					32
+#define GCC_EVA_AXI0C_CLK_ARES					33
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h
new file mode 100644
index 00000000000..1c502ac7c7f
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
+
+/* TCSR_CC clocks */
+#define TCSR_PCIE_0_CLKREF_EN				0
+#define TCSR_UFS_CLKREF_EN				1
+#define TCSR_USB2_CLKREF_EN				2
+#define TCSR_USB3_CLKREF_EN				3
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
index 61a3a8f3ac4..27b8f50541f 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
@@ -33,9 +33,22 @@
 #define GPU_CC_SLEEP_CLK					23
 #define GPU_CC_XO_CLK_SRC					24
 #define GPU_CC_XO_DIV_CLK_SRC					25
+#define GPU_CC_CX_ACCU_SHIFT_CLK				26
+#define GPU_CC_GX_ACCU_SHIFT_CLK				27
 
 /* GDSCs */
 #define GPU_CX_GDSC						0
 #define GPU_GX_GDSC						1
 
+/* GPU_CC resets */
+#define GPU_CC_ACD_BCR                                          0
+#define GPU_CC_CB_BCR                                           1
+#define GPU_CC_CX_BCR                                           2
+#define GPU_CC_FAST_HUB_BCR                                     3
+#define GPU_CC_FF_BCR                                           4
+#define GPU_CC_GFX3D_AON_BCR                                    5
+#define GPU_CC_GMU_BCR                                          6
+#define GPU_CC_GX_BCR                                           7
+#define GPU_CC_XO_BCR                                           8
+
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
index 67774eafad0..4cc8fc34b23 100644
--- a/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
+++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
@@ -2,12 +2,12 @@
  *
  * Copyright (C) 2024 Renesas Electronics Corp.
  */
-#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
-#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
 
 #define VBATTB_XC		0
 #define VBATTB_XBYP		1
 #define VBATTB_MUX		2
 #define VBATTB_VBATTCLK		3
 
-#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
new file mode 100644
index 00000000000..1d031bf6bf0
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G047_SYS_0_PCLK			0
+#define R9A09G047_CA55_0_CORECLK0		1
+#define R9A09G047_CA55_0_CORECLK1		2
+#define R9A09G047_CA55_0_CORECLK2		3
+#define R9A09G047_CA55_0_CORECLK3		4
+#define R9A09G047_CA55_0_PERIPHCLK		5
+#define R9A09G047_CM33_CLK0			6
+#define R9A09G047_CST_0_SWCLKTCK		7
+#define R9A09G047_IOTOP_0_SHCLK			8
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h b/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h
new file mode 100644
index 00000000000..307215a3f3e
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
+ *
+ * Device Tree binding constants for Exynos990 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SHARED4_PLL		5
+#define CLK_FOUT_G3D_PLL		6
+#define CLK_FOUT_MMC_PLL		7
+#define CLK_MOUT_PLL_SHARED0		8
+#define CLK_MOUT_PLL_SHARED1		9
+#define CLK_MOUT_PLL_SHARED2		10
+#define CLK_MOUT_PLL_SHARED3		11
+#define CLK_MOUT_PLL_SHARED4		12
+#define CLK_MOUT_PLL_MMC		13
+#define CLK_MOUT_PLL_G3D		14
+#define CLK_MOUT_CMU_APM_BUS		15
+#define CLK_MOUT_CMU_AUD_CPU		16
+#define CLK_MOUT_CMU_BUS0_BUS		17
+#define CLK_MOUT_CMU_BUS1_BUS		18
+#define CLK_MOUT_CMU_BUS1_SSS		19
+#define CLK_MOUT_CMU_CIS_CLK0		20
+#define CLK_MOUT_CMU_CIS_CLK1		21
+#define CLK_MOUT_CMU_CIS_CLK2		22
+#define CLK_MOUT_CMU_CIS_CLK3		23
+#define CLK_MOUT_CMU_CIS_CLK4		24
+#define CLK_MOUT_CMU_CIS_CLK5		25
+#define CLK_MOUT_CMU_CMU_BOOST		26
+#define CLK_MOUT_CMU_CORE_BUS		27
+#define CLK_MOUT_CMU_CPUCL0_DBG_BUS	28
+#define CLK_MOUT_CMU_CPUCL0_SWITCH	29
+#define CLK_MOUT_CMU_CPUCL1_SWITCH	30
+#define CLK_MOUT_CMU_CPUCL2_BUSP	31
+#define CLK_MOUT_CMU_CPUCL2_SWITCH	32
+#define CLK_MOUT_CMU_CSIS_BUS		33
+#define CLK_MOUT_CMU_CSIS_OIS_MCU	34
+#define CLK_MOUT_CMU_DNC_BUS		35
+#define CLK_MOUT_CMU_DNC_BUSM		36
+#define CLK_MOUT_CMU_DNS_BUS		37
+#define CLK_MOUT_CMU_DPU		38
+#define CLK_MOUT_CMU_DPU_ALT		39
+#define CLK_MOUT_CMU_DSP_BUS		40
+#define CLK_MOUT_CMU_G2D_G2D		41
+#define CLK_MOUT_CMU_G2D_MSCL		42
+#define CLK_MOUT_CMU_HPM		43
+#define CLK_MOUT_CMU_HSI0_BUS		44
+#define CLK_MOUT_CMU_HSI0_DPGTC		45
+#define CLK_MOUT_CMU_HSI0_USB31DRD	46
+#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG	47
+#define CLK_MOUT_CMU_HSI1_BUS		48
+#define CLK_MOUT_CMU_HSI1_MMC_CARD	49
+#define CLK_MOUT_CMU_HSI1_PCIE		50
+#define CLK_MOUT_CMU_HSI1_UFS_CARD	51
+#define CLK_MOUT_CMU_HSI1_UFS_EMBD	52
+#define CLK_MOUT_CMU_HSI2_BUS		53
+#define CLK_MOUT_CMU_HSI2_PCIE		54
+#define CLK_MOUT_CMU_IPP_BUS		55
+#define CLK_MOUT_CMU_ITP_BUS		56
+#define CLK_MOUT_CMU_MCSC_BUS		57
+#define CLK_MOUT_CMU_MCSC_GDC		58
+#define CLK_MOUT_CMU_CMU_BOOST_CPU	59
+#define CLK_MOUT_CMU_MFC0_MFC0		60
+#define CLK_MOUT_CMU_MFC0_WFD		61
+#define CLK_MOUT_CMU_MIF_BUSP		62
+#define CLK_MOUT_CMU_MIF_SWITCH		63
+#define CLK_MOUT_CMU_NPU_BUS		64
+#define CLK_MOUT_CMU_PERIC0_BUS		65
+#define CLK_MOUT_CMU_PERIC0_IP		66
+#define CLK_MOUT_CMU_PERIC1_BUS		67
+#define CLK_MOUT_CMU_PERIC1_IP		68
+#define CLK_MOUT_CMU_PERIS_BUS		69
+#define CLK_MOUT_CMU_SSP_BUS		70
+#define CLK_MOUT_CMU_TNR_BUS		71
+#define CLK_MOUT_CMU_VRA_BUS		72
+#define CLK_DOUT_CMU_APM_BUS		73
+#define CLK_DOUT_CMU_AUD_CPU		74
+#define CLK_DOUT_CMU_BUS0_BUS		75
+#define CLK_DOUT_CMU_BUS1_BUS		76
+#define CLK_DOUT_CMU_BUS1_SSS		77
+#define CLK_DOUT_CMU_CIS_CLK0		78
+#define CLK_DOUT_CMU_CIS_CLK1		79
+#define CLK_DOUT_CMU_CIS_CLK2		80
+#define CLK_DOUT_CMU_CIS_CLK3		81
+#define CLK_DOUT_CMU_CIS_CLK4		82
+#define CLK_DOUT_CMU_CIS_CLK5		83
+#define CLK_DOUT_CMU_CMU_BOOST		84
+#define CLK_DOUT_CMU_CORE_BUS		85
+#define CLK_DOUT_CMU_CPUCL0_DBG_BUS	86
+#define CLK_DOUT_CMU_CPUCL0_SWITCH	87
+#define CLK_DOUT_CMU_CPUCL1_SWITCH	88
+#define CLK_DOUT_CMU_CPUCL2_BUSP	89
+#define CLK_DOUT_CMU_CPUCL2_SWITCH	90
+#define CLK_DOUT_CMU_CSIS_BUS		91
+#define CLK_DOUT_CMU_CSIS_OIS_MCU	92
+#define CLK_DOUT_CMU_DNC_BUS		93
+#define CLK_DOUT_CMU_DNC_BUSM		94
+#define CLK_DOUT_CMU_DNS_BUS		95
+#define CLK_DOUT_CMU_DSP_BUS		96
+#define CLK_DOUT_CMU_G2D_G2D		97
+#define CLK_DOUT_CMU_G2D_MSCL		98
+#define CLK_DOUT_CMU_G3D_SWITCH		99
+#define CLK_DOUT_CMU_HPM		100
+#define CLK_DOUT_CMU_HSI0_BUS		101
+#define CLK_DOUT_CMU_HSI0_DPGTC		102
+#define CLK_DOUT_CMU_HSI0_USB31DRD	103
+#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG	104
+#define CLK_DOUT_CMU_HSI1_BUS		105
+#define CLK_DOUT_CMU_HSI1_MMC_CARD	106
+#define CLK_DOUT_CMU_HSI1_PCIE		107
+#define CLK_DOUT_CMU_HSI1_UFS_CARD	108
+#define CLK_DOUT_CMU_HSI1_UFS_EMBD	109
+#define CLK_DOUT_CMU_HSI2_BUS		110
+#define CLK_DOUT_CMU_HSI2_PCIE		111
+#define CLK_DOUT_CMU_IPP_BUS		112
+#define CLK_DOUT_CMU_ITP_BUS		113
+#define CLK_DOUT_CMU_MCSC_BUS		114
+#define CLK_DOUT_CMU_MCSC_GDC		115
+#define CLK_DOUT_CMU_CMU_BOOST_CPU	116
+#define CLK_DOUT_CMU_MFC0_MFC0		117
+#define CLK_DOUT_CMU_MFC0_WFD		118
+#define CLK_DOUT_CMU_MIF_BUSP		119
+#define CLK_DOUT_CMU_NPU_BUS		120
+#define CLK_DOUT_CMU_OTP		121
+#define CLK_DOUT_CMU_PERIC0_BUS		122
+#define CLK_DOUT_CMU_PERIC0_IP		123
+#define CLK_DOUT_CMU_PERIC1_BUS		124
+#define CLK_DOUT_CMU_PERIC1_IP		125
+#define CLK_DOUT_CMU_PERIS_BUS		126
+#define CLK_DOUT_CMU_SSP_BUS		127
+#define CLK_DOUT_CMU_TNR_BUS		128
+#define CLK_DOUT_CMU_VRA_BUS		129
+#define CLK_DOUT_CMU_DPU		130
+#define CLK_DOUT_CMU_DPU_ALT		131
+#define CLK_DOUT_CMU_SHARED0_DIV2	132
+#define CLK_DOUT_CMU_SHARED0_DIV3	133
+#define CLK_DOUT_CMU_SHARED0_DIV4	134
+#define CLK_DOUT_CMU_SHARED1_DIV2	135
+#define CLK_DOUT_CMU_SHARED1_DIV3	136
+#define CLK_DOUT_CMU_SHARED1_DIV4	137
+#define CLK_DOUT_CMU_SHARED2_DIV2	138
+#define CLK_DOUT_CMU_SHARED4_DIV2	139
+#define CLK_DOUT_CMU_SHARED4_DIV3	140
+#define CLK_DOUT_CMU_SHARED4_DIV4	141
+#define CLK_GOUT_CMU_G3D_BUS		142
+#define CLK_GOUT_CMU_MIF_SWITCH		143
+#define CLK_GOUT_CMU_APM_BUS		144
+#define CLK_GOUT_CMU_AUD_CPU		145
+#define CLK_GOUT_CMU_BUS0_BUS		146
+#define CLK_GOUT_CMU_BUS1_BUS		147
+#define CLK_GOUT_CMU_BUS1_SSS		148
+#define CLK_GOUT_CMU_CIS_CLK0		149
+#define CLK_GOUT_CMU_CIS_CLK1		150
+#define CLK_GOUT_CMU_CIS_CLK2		151
+#define CLK_GOUT_CMU_CIS_CLK3		152
+#define CLK_GOUT_CMU_CIS_CLK4		153
+#define CLK_GOUT_CMU_CIS_CLK5		154
+#define CLK_GOUT_CMU_CORE_BUS		155
+#define CLK_GOUT_CMU_CPUCL0_DBG_BUS	156
+#define CLK_GOUT_CMU_CPUCL0_SWITCH	157
+#define CLK_GOUT_CMU_CPUCL1_SWITCH	158
+#define CLK_GOUT_CMU_CPUCL2_BUSP	159
+#define CLK_GOUT_CMU_CPUCL2_SWITCH	160
+#define CLK_GOUT_CMU_CSIS_BUS		161
+#define CLK_GOUT_CMU_CSIS_OIS_MCU	162
+#define CLK_GOUT_CMU_DNC_BUS		163
+#define CLK_GOUT_CMU_DNC_BUSM		164
+#define CLK_GOUT_CMU_DNS_BUS		165
+#define CLK_GOUT_CMU_DPU		166
+#define CLK_GOUT_CMU_DPU_BUS		167
+#define CLK_GOUT_CMU_DSP_BUS		168
+#define CLK_GOUT_CMU_G2D_G2D		169
+#define CLK_GOUT_CMU_G2D_MSCL		170
+#define CLK_GOUT_CMU_G3D_SWITCH		171
+#define CLK_GOUT_CMU_HPM		172
+#define CLK_GOUT_CMU_HSI0_BUS		173
+#define CLK_GOUT_CMU_HSI0_DPGTC		174
+#define CLK_GOUT_CMU_HSI0_USB31DRD	175
+#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG	176
+#define CLK_GOUT_CMU_HSI1_BUS		177
+#define CLK_GOUT_CMU_HSI1_MMC_CARD	178
+#define CLK_GOUT_CMU_HSI1_PCIE		179
+#define CLK_GOUT_CMU_HSI1_UFS_CARD	180
+#define CLK_GOUT_CMU_HSI1_UFS_EMBD	181
+#define CLK_GOUT_CMU_HSI2_BUS		182
+#define CLK_GOUT_CMU_HSI2_PCIE		183
+#define CLK_GOUT_CMU_IPP_BUS		184
+#define CLK_GOUT_CMU_ITP_BUS		185
+#define CLK_GOUT_CMU_MCSC_BUS		186
+#define CLK_GOUT_CMU_MCSC_GDC		187
+#define CLK_GOUT_CMU_MFC0_MFC0		188
+#define CLK_GOUT_CMU_MFC0_WFD		189
+#define CLK_GOUT_CMU_MIF_BUSP		190
+#define CLK_GOUT_CMU_NPU_BUS		191
+#define CLK_GOUT_CMU_PERIC0_BUS		192
+#define CLK_GOUT_CMU_PERIC0_IP		193
+#define CLK_GOUT_CMU_PERIC1_BUS		194
+#define CLK_GOUT_CMU_PERIC1_IP		195
+#define CLK_GOUT_CMU_PERIS_BUS		196
+#define CLK_GOUT_CMU_SSP_BUS		197
+#define CLK_GOUT_CMU_TNR_BUS		198
+#define CLK_GOUT_CMU_VRA_BUS		199
+
+/* CMU_HSI0 */
+#define CLK_MOUT_HSI0_BUS_USER				1
+#define CLK_MOUT_HSI0_USB31DRD_USER			2
+#define CLK_MOUT_HSI0_USBDP_DEBUG_USER			3
+#define CLK_MOUT_HSI0_DPGTC_USER			4
+#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK		5
+#define CLK_GOUT_HSI0_DP_LINK_PCLK			6
+#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK			7
+#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK		8
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK		9
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK		10
+#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK			11
+#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2			12
+#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK			13
+#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL		14
+#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY		15
+#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40	16
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL	17
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB		18
+#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK		19
+#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK		20
+#define CLK_GOUT_HSI0_CMU_HSI0_PCLK			21
+#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK			22
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h b/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
index e5dad050d51..b6ff9c68cb3 100644
--- a/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
@@ -10,7 +10,7 @@
  * List of clocks which are not derived from system clock (SYSCLOCK)
  *
  * The index of these clocks is the secondary index of DT bindings
- * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
+ * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml)
  *
  * e.g:
 	<assigned-clocks = <&rcc 1 CLK_LSE>;
diff --git a/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h b/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
index 175892189e9..4f220ea7a23 100644
--- a/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -44,7 +44,9 @@
 #define _DT_BINDINGS_CLK_SUN50I_A64_H_
 
 #define CLK_PLL_VIDEO0		7
+#define CLK_PLL_VIDEO0_2X	8
 #define CLK_PLL_PERIPH0		11
+#define CLK_PLL_MIPI		17
 
 #define CLK_CPUX		21
 #define CLK_BUS_MIPI_DSI	28
diff --git a/dts/upstream/include/dt-bindings/iio/adi,ad4695.h b/dts/upstream/include/dt-bindings/iio/adc/adi,ad4695.h
index 9fbef542bf6..9fbef542bf6 100644
--- a/dts/upstream/include/dt-bindings/iio/adi,ad4695.h
+++ b/dts/upstream/include/dt-bindings/iio/adc/adi,ad4695.h
diff --git a/dts/upstream/include/dt-bindings/input/linux-event-codes.h b/dts/upstream/include/dt-bindings/input/linux-event-codes.h
index a4206723f50..5a199f3d4a2 100644
--- a/dts/upstream/include/dt-bindings/input/linux-event-codes.h
+++ b/dts/upstream/include/dt-bindings/input/linux-event-codes.h
@@ -519,6 +519,7 @@
 #define KEY_NOTIFICATION_CENTER	0x1bc	/* Show/hide the notification center */
 #define KEY_PICKUP_PHONE	0x1bd	/* Answer incoming call */
 #define KEY_HANGUP_PHONE	0x1be	/* Decline incoming call */
+#define KEY_LINK_PHONE		0x1bf   /* AL Phone Syncing */
 
 #define KEY_DEL_EOL		0x1c0
 #define KEY_DEL_EOS		0x1c1
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h
new file mode 100644
index 00000000000..a770356112e
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ5424_H
+#define INTERCONNECT_QCOM_IPQ5424_H
+
+#define MASTER_ANOC_PCIE0		0
+#define SLAVE_ANOC_PCIE0		1
+#define MASTER_CNOC_PCIE0		2
+#define SLAVE_CNOC_PCIE0		3
+#define MASTER_ANOC_PCIE1		4
+#define SLAVE_ANOC_PCIE1		5
+#define MASTER_CNOC_PCIE1		6
+#define SLAVE_CNOC_PCIE1		7
+#define MASTER_ANOC_PCIE2		8
+#define SLAVE_ANOC_PCIE2		9
+#define MASTER_CNOC_PCIE2		10
+#define SLAVE_CNOC_PCIE2		11
+#define MASTER_ANOC_PCIE3		12
+#define SLAVE_ANOC_PCIE3		13
+#define MASTER_CNOC_PCIE3		14
+#define SLAVE_CNOC_PCIE3		15
+#define MASTER_CNOC_USB			16
+#define SLAVE_CNOC_USB			17
+
+#endif /* INTERCONNECT_QCOM_IPQ5424_H */
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
new file mode 100644
index 00000000000..30563952a64
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_1				1
+#define MASTER_QUP_3				2
+#define MASTER_SDCC_4				3
+#define MASTER_UFS_MEM				4
+#define MASTER_USB3_0				5
+#define SLAVE_A1NOC_SNOC			6
+
+#define MASTER_QDSS_BAM				0
+#define MASTER_QUP_2				1
+#define MASTER_CRYPTO				2
+#define MASTER_IPA				3
+#define MASTER_SOCCP_AGGR_NOC			4
+#define MASTER_SP				5
+#define MASTER_QDSS_ETR				6
+#define MASTER_QDSS_ETR_1			7
+#define MASTER_SDCC_2				8
+#define SLAVE_A2NOC_SNOC			9
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_2			2
+#define SLAVE_QUP_CORE_0			3
+#define SLAVE_QUP_CORE_1			4
+#define SLAVE_QUP_CORE_2			5
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_CRYPTO_0_CFG			5
+#define SLAVE_DISPLAY_CFG			6
+#define SLAVE_EVA_CFG				7
+#define SLAVE_GFX3D_CFG				8
+#define SLAVE_I2C				9
+#define SLAVE_I3C_IBI0_CFG			10
+#define SLAVE_I3C_IBI1_CFG			11
+#define SLAVE_IMEM_CFG				12
+#define SLAVE_CNOC_MSS				13
+#define SLAVE_PCIE_CFG				14
+#define SLAVE_PRNG				15
+#define SLAVE_QDSS_CFG				16
+#define SLAVE_QSPI_0				17
+#define SLAVE_QUP_3				18
+#define SLAVE_QUP_1				19
+#define SLAVE_QUP_2				20
+#define SLAVE_SDCC_2				21
+#define SLAVE_SDCC_4				22
+#define SLAVE_SPSS_CFG				23
+#define SLAVE_TCSR				24
+#define SLAVE_TLMM				25
+#define SLAVE_UFS_MEM_CFG			26
+#define SLAVE_USB3_0				27
+#define SLAVE_VENUS_CFG				28
+#define SLAVE_VSENSE_CTRL_CFG			29
+#define SLAVE_CNOC_MNOC_CFG			30
+#define SLAVE_PCIE_ANOC_CFG			31
+#define SLAVE_QDSS_STM				32
+#define SLAVE_TCU				33
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_IPA_CFG				3
+#define SLAVE_IPC_ROUTER_CFG			4
+#define SLAVE_SOCCP				5
+#define SLAVE_TME_CFG				6
+#define SLAVE_APPSS				7
+#define SLAVE_CNOC_CFG				8
+#define SLAVE_DDRSS_CFG				9
+#define SLAVE_BOOT_IMEM				10
+#define SLAVE_IMEM				11
+#define SLAVE_BOOT_IMEM_2			12
+#define SLAVE_SERVICE_CNOC			13
+#define SLAVE_PCIE_0				14
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_LPASS_GEM_NOC			4
+#define MASTER_MSS_PROC				5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC			10
+#define MASTER_UBWC_P				11
+#define MASTER_GIC				12
+#define SLAVE_UBWC_P				13
+#define SLAVE_GEM_NOC_CNOC			14
+#define SLAVE_LLCC				15
+#define SLAVE_MEM_NOC_PCIE_SNOC			16
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_NRT_ICP_SF		1
+#define MASTER_CAMNOC_RT_CDM_SF			2
+#define MASTER_CAMNOC_SF			3
+#define MASTER_MDP				4
+#define MASTER_CDSP_HCP				5
+#define MASTER_VIDEO_CV_PROC			6
+#define MASTER_VIDEO_EVA			7
+#define MASTER_VIDEO_MVP			8
+#define MASTER_VIDEO_V_PROC			9
+#define MASTER_CNOC_MNOC_CFG			10
+#define SLAVE_MNOC_HF_MEM_NOC			11
+#define SLAVE_MNOC_SF_MEM_NOC			12
+#define SLAVE_SERVICE_MNOC			13
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+#define SLAVE_SERVICE_PCIE_ANOC			3
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define SLAVE_SNOC_GEM_NOC_SF			2
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/media/video-interfaces.h b/dts/upstream/include/dt-bindings/media/video-interfaces.h
index 68ac4e05e37..88b9d05d807 100644
--- a/dts/upstream/include/dt-bindings/media/video-interfaces.h
+++ b/dts/upstream/include/dt-bindings/media/video-interfaces.h
@@ -13,4 +13,11 @@
 #define MEDIA_BUS_TYPE_PARALLEL			5
 #define MEDIA_BUS_TYPE_BT656			6
 
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC	0
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB	1
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC	2
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA	3
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB	4
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA	5
+
 #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
diff --git a/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
new file mode 100644
index 00000000000..5917096720b
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3E_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZG3E_P0	0
+#define RZG3E_P1	1
+#define RZG3E_P2	2
+#define RZG3E_P3	3
+#define RZG3E_P4	4
+#define RZG3E_P5	5
+#define RZG3E_P6	6
+#define RZG3E_P7	7
+#define RZG3E_P8	8
+#define RZG3E_PA	10
+#define RZG3E_PB	11
+#define RZG3E_PC	12
+#define RZG3E_PD	13
+#define RZG3E_PE	14
+#define RZG3E_PF	15
+#define RZG3E_PG	16
+#define RZG3E_PH	17
+#define RZG3E_PJ	19
+#define RZG3E_PK	20
+#define RZG3E_PL	21
+#define RZG3E_PM	22
+#define RZG3E_PS	28
+
+#define RZG3E_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
+#define RZG3E_GPIO(port, pin)		RZG2L_GPIO(RZG3E_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
diff --git a/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
new file mode 100644
index 00000000000..2e83bf43160
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZV2H_P0	0
+#define RZV2H_P1	1
+#define RZV2H_P2	2
+#define RZV2H_P3	3
+#define RZV2H_P4	4
+#define RZV2H_P5	5
+#define RZV2H_P6	6
+#define RZV2H_P7	7
+#define RZV2H_P8	8
+#define RZV2H_P9	9
+#define RZV2H_PA	10
+#define RZV2H_PB	11
+
+#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
+#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
diff --git a/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 00000000000..7693552f150
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB	0
+#define AUD_RESET_TDMIN_A	1
+#define AUD_RESET_TDMIN_B	2
+#define AUD_RESET_TDMIN_LB	3
+#define AUD_RESET_LOOPBACK	4
+#define AUD_RESET_TDMOUT_A	5
+#define AUD_RESET_TDMOUT_B	6
+#define AUD_RESET_FRDDR_A	7
+#define AUD_RESET_FRDDR_B	8
+#define AUD_RESET_TODDR_A	9
+#define AUD_RESET_TODDR_B	10
+#define AUD_RESET_SPDIFIN	11
+#define AUD_RESET_RESAMPLE	12
+#define AUD_RESET_EQDRC		13
+#define AUD_RESET_LOCKER	14
+#define AUD_RESET_TOACODEC	30
+#define AUD_RESET_CLKTREE	31
+
+#define AUD_VAD_RESET_DDRARB	0
+#define AUD_VAD_RESET_PDM	1
+#define AUD_VAD_RESET_TDMIN_VAD	2
+#define AUD_VAD_RESET_TODDR_VAD	3
+#define AUD_VAD_RESET_TOVAD	4
+#define AUD_VAD_RESET_CLKTREE	5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
diff --git a/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h b/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
index f5e9f1db091..4fc68aeb9e0 100644
--- a/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
+++ b/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
@@ -10,6 +10,5 @@
 #define AIF3_PB                 4
 #define AIF3_CAP                5
 #define AIF4_PB                 6
-#define NUM_CODEC_DAIS          7
 
 #endif
diff --git a/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts b/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
index 43896723a99..472ded0aafc 100644
--- a/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
+++ b/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
@@ -62,6 +62,14 @@
 	status = "okay";
 };
 
+&codec {
+	allwinner,audio-routing =
+		"Headphone", "HP",
+		"Headphone", "HPCOM",
+		"MIC", "Mic";
+	status = "okay";
+};
+
 &usb_otg {
 	dr_mode = "otg";
 	status = "okay";
diff --git a/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi b/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
index 3c61d59ab5f..e4b41bc9385 100644
--- a/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
+++ b/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+#include <dt-bindings/dma/sun4i-a10.h>
 
 / {
 	#address-cells = <1>;
@@ -159,6 +160,15 @@
 			status = "disabled";
 		};
 
+		dma: dma-controller@1c02000 {
+			compatible = "allwinner,suniv-f1c100s-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <18>;
+			clocks = <&ccu CLK_BUS_DMA>;
+			resets = <&ccu RST_BUS_DMA>;
+			#dma-cells = <2>;
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
@@ -326,5 +336,19 @@
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
+
+		codec: codec@1c23c00 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,suniv-f1c100s-codec";
+			reg = <0x01c23c00 0x400>;
+			interrupts = <21>;
+			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
+			clock-names = "apb", "codec";
+			dmas = <&dma SUN4I_DMA_NORMAL 12>,
+			       <&dma SUN4I_DMA_NORMAL 12>;
+			dma-names = "rx", "tx";
+			resets = <&ccu RST_BUS_CODEC>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/amlogic/meson.dtsi b/dts/upstream/src/arm/amlogic/meson.dtsi
index 8cb0fc78b2a..28ec2c821cd 100644
--- a/dts/upstream/src/arm/amlogic/meson.dtsi
+++ b/dts/upstream/src/arm/amlogic/meson.dtsi
@@ -255,8 +255,6 @@
 
 		usb0: usb@c9040000 {
 			compatible = "snps,dwc2";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0xc9040000 0x40000>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usb0_phy>;
@@ -270,8 +268,6 @@
 
 		usb1: usb@c90c0000 {
 			compatible = "snps,dwc2";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0xc90c0000 0x40000>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usb1_phy>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts
new file mode 100644
index 00000000000..c435359a4bd
--- /dev/null
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright 2024 Ampere Computing LLC.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "Ampere Mt. Jefferson BMC";
+	compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600";
+
+	aliases {
+		i2c20 = &i2c4_bus70_chn0;
+		i2c22 = &i2c4_bus70_chn2;
+
+		/*
+		 *  I2C OCP alias port
+		 */
+		i2c30 = &ocpslot;
+
+		/*
+		 *  I2C NVMe alias port
+		 */
+		i2c48 = &nvmeslot_0;
+		i2c49 = &nvmeslot_1;
+		i2c50 = &nvmeslot_2;
+		i2c51 = &nvmeslot_3;
+		i2c52 = &nvmeslot_4;
+		i2c53 = &nvmeslot_5;
+		i2c54 = &nvmeslot_6;
+		i2c55 = &nvmeslot_7;
+		i2c56 = &nvmeslot_8;
+		i2c57 = &nvmeslot_9;
+		i2c58 = &nvmeslot_10;
+		i2c59 = &nvmeslot_11;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+
+		video_engine_memory: video {
+			size = <0x04000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+
+		vga_memory: region@bf000000 {
+			no-map;
+			compatible = "shared-dma-pool";
+			reg = <0xbf000000 0x01000000>;  /* 16M */
+		};
+	};
+
+	voltage_mon_reg: voltage-mon-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "ltc2497_reg";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-bmc-ready {
+			gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>;
+		};
+
+		led-sw-heartbeat {
+			gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
+		};
+
+		led-identify {
+			gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+		};
+
+		led-fault {
+			gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels =   <&adc0 0>, <&adc0 1>, <&adc0 2>,
+				<&adc_i2c_2 0>, <&adc_i2c_2 1>,
+				<&adc_i2c_2 2>, <&adc_i2c_2 3>,
+				<&adc_i2c_2 4>, <&adc_i2c_2 5>,
+				<&adc_i2c_2 6>, <&adc_i2c_2 7>,
+				<&adc_i2c_2 8>, <&adc_i2c_2 9>,
+				<&adc_i2c_2 10>, <&adc_i2c_2 11>,
+				<&adc_i2c_2 12>, <&adc_i2c_2 13>,
+				<&adc_i2c_2 14>, <&adc_i2c_2 15>,
+				<&adc_i2c_0 0>, <&adc_i2c_0 1>,
+				<&adc_i2c_0 2>, <&adc_i2c_0 3>,
+				<&adc_i2c_0 4>, <&adc_i2c_0 5>,
+				<&adc_i2c_0 6>, <&adc_i2c_0 7>,
+				<&adc_i2c_0 8>, <&adc_i2c_0 9>,
+				<&adc_i2c_0 10>, <&adc_i2c_0 11>,
+				<&adc_i2c_0 12>;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&mac0 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+&mac3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rmii4_default>;
+	use-ncsi;
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+
+	flash@1 {
+		status = "okay";
+		m25p,fast-read;
+		label = "alt-bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+	};
+};
+
+&spi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default>;
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "pnor";
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+	bus-frequency = <1000000>;
+	multi-master;
+	mctp-controller;
+
+	mctp@10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+
+		i2c4_bus70_chn0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			eeprom@52 {
+				compatible = "atmel,24c256";
+				reg = <0x52>;
+				pagesize = <32>;
+			};
+			temperature-sensor@48 {
+				compatible = "ti,tmp75";
+				reg = <0x48>;
+			};
+			temperature-sensor@49 {
+				compatible = "ti,tmp75";
+				reg = <0x49>;
+			};
+			temperature-sensor@4a{
+				compatible = "ti,tmp75";
+				reg = <0x4a>;
+			};
+			temperature-sensor@4b {
+				compatible = "ti,tmp464";
+				reg = <0x4b>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				channel@0 {
+					reg = <0x0>;
+					status = "disabled";
+				};
+				channel@1 {
+					reg = <0x1>;
+					status = "disabled";
+				};
+				channel@2 {
+					reg = <0x2>;
+					status = "disabled";
+				};
+				channel@3 {
+					reg = <0x3>;
+					status = "disabled";
+				};
+				channel@4 {
+					reg = <0x4>;
+				};
+			};
+			temperature-sensor@4d {
+				compatible = "ti,tmp75";
+				reg = <0x4d>;
+			};
+			temperature-sensor@4e {
+				compatible = "ti,tmp75";
+				reg = <0x4e>;
+			};
+			temperature-sensor@4f {
+				compatible = "ti,tmp75";
+				reg = <0x4f>;
+			};
+			temperature-sensor@28 {
+				compatible = "nuvoton,nct7802";
+				reg = <0x28>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel@1 { /* RTD1 */
+					reg = <1>;
+					sensor-type = "temperature";
+					temperature-mode = "thermistor";
+				};
+			};
+			adc_i2c_0: adc@14 {
+				compatible = "lltc,ltc2497";
+				reg = <0x14>;
+				vref-supply = <&voltage_mon_reg>;
+				#io-channel-cells = <1>;
+			};
+		};
+
+		i2c4_bus70_chn2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			adc_i2c_2: adc@14 {
+				compatible = "lltc,ltc2497";
+				reg = <0x14>;
+				vref-supply = <&voltage_mon_reg>;
+				#io-channel-cells = <1>;
+			};
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			i2c-mux@71 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x71>;
+				i2c-mux-idle-disconnect;
+
+				nvmeslot_8: i2c@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+				};
+				nvmeslot_9: i2c@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x1>;
+				};
+				nvmeslot_10: i2c@2 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x2>;
+				};
+				nvmeslot_11: i2c@3 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x3>;
+				};
+			};
+
+			i2c-mux@72 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72>;
+				i2c-mux-idle-disconnect;
+
+				nvmeslot_4: i2c@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4>;
+				};
+				nvmeslot_5: i2c@5 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x5>;
+				};
+				nvmeslot_6: i2c@6 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x6>;
+				};
+				nvmeslot_7: i2c@7 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x7>;
+				};
+			};
+
+			i2c-mux@74 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x74>;
+				i2c-mux-idle-disconnect;
+
+				ocpslot: i2c@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+
+					ocpslot_temp: temperature-sensor@1f {
+						compatible = "ti,tmp421";
+						reg = <0x1f>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						channel@0 {
+							reg = <0x0>;
+							status = "disabled";
+						};
+						channel@1 {
+							reg = <0x1>;
+						};
+					};
+				};
+
+				nvmeslot_0: i2c@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4>;
+				};
+				nvmeslot_1: i2c@5 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x5>;
+				};
+				nvmeslot_2: i2c@6 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x6>;
+				};
+				nvmeslot_3: i2c@7 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x7>;
+				};
+			};
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	temperature-sensor@4f {
+		compatible = "ti,tmp75";
+		reg = <0x4f>;
+	};
+};
+
+&i2c8 {
+	status = "okay";
+
+	fan-controller@5c {
+		compatible = "onnn,adt7462";
+		reg = <0x5c>;
+	};
+};
+
+&i2c9 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+	};
+
+	temperature-sensor@18 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x18>;
+	};
+
+	temperature-sensor@1a {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x1a>;
+	};
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+	ssif-bmc@10 {
+		compatible = "ssif-bmc";
+		reg = <0x10>;
+	};
+};
+
+&i2c14 {
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	bmc_ast2600_cpu: temperature-sensor@48 {
+		compatible = "ti,tmp75";
+		reg = <0x48>;
+	};
+};
+
+&i2c15 {
+	status = "okay";
+	gpio_expander1: gpio-expander@22 {
+		compatible = "nxp,pca9535";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"presence-ocp1","presence-ocp2",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","";
+	};
+};
+
+&adc0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+		&pinctrl_adc2_default>;
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	status = "okay";
+	memory-region = <&video_engine_memory>;
+};
+
+&gpio0 {
+	gpio-line-names =
+	/*A0-A7*/	"","","","","cpu-type-detect","i2c2-reset-n","i2c6-reset-n","i2c5-reset-n",
+	/*B0-B7*/	"","","","","host0-sysreset-n","host0-pmin-n","fru-rd-complete",
+			"chassis-id-sel",
+	/*C0-C7*/	"s0-vrd-fault-n","","bmc-debug-mode","","cpld-3v3-irq-n","","vrd-sel",
+			"spd-sel",
+	/*D0-D7*/	"presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
+			"","","","",
+	/*E0-E7*/	"eth-phy-rst-n","eth-phy-int-n","","","","","","",
+	/*F0-F7*/	"s0-pcp-oc-warn-n","","power-chassis-control",
+			"cpu-bios-recover","s0-heartbeat","hs-scout-proc-hot","s0-vr-hot-n","",
+	/*G0-G7*/	"","","hsc-12vmain-alt1-n","","","bp-cpld-program-en","led-fp-sta-gr",
+			"led-fp-sta-amb",
+	/*H0-H7*/	"jtag-program-sel","jtag-cmpl2","wd-disable-n","power-chassis-good","","",
+			"","",
+	/*I0-I7*/	"","","","","","","power-button","rtc-battery-voltage-read-enable",
+	/*J0-J7*/	"","","","","","","","",
+	/*K0-K7*/	"","","","","","","","",
+	/*L0-L7*/	"","","","","reset-button","","","",
+	/*M0-M7*/	"nmi-n","s0-ddr-save","soc-spi-nor-access","presence-cpu0","s0-rtc-lock",
+			"","","",
+	/*N0-N7*/	"hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
+			"jtag-dbgr-prsnt-n","","","",
+	/*O0-O7*/	"","","","","","","","",
+	/*P0-P7*/	"ps0-ac-loss-n","ps1-ac-loss-n","","","led-fault","user-mode","jtag-srst-n",
+			"led-bmc-hb",
+	/*Q0-Q7*/	"","","","","","","","",
+	/*R0-R7*/	"","","","","","","","",
+	/*S0-S7*/	"","","identify-button","led-identify","","spi-nor-access","host0-ready","",
+	/*T0-T7*/	"","","","","","","","",
+	/*U0-U7*/	"","","","","","","","",
+	/*V0-V7*/	"s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
+			"host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n",
+			"host0-shd-ack-n","s0-overtemp-n",
+	/*W0-W7*/	"ocp-aux-pwren","ocp-main-pwren","ocp-pgood","",
+			"bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
+	/*X0-X7*/	"","","","","","","","",
+	/*Y0-Y7*/	"","","","vrd-prg-en-n","","","","host0-special-boot",
+	/*Z0-Z7*/	"","ps0-pgood","ps1-pgood","","","","","";
+
+	ocp-aux-pwren-hog {
+		gpio-hog;
+		gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "ocp-aux-pwren";
+	};
+
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*18A0-18A7*/	"","","","","","","","",
+	/*18B0-18B7*/	"","","","","s0-soc-pgood","vga-ft-press-n","emmc-rst-n","s01-uart1-sel",
+	/*18C0-18C7*/	"uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
+			"","","","",
+	/*18D0-18D7*/	"","","","","","","","",
+	/*18E0-18E3*/	"","","","";
+};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
index 0295f5adcfb..2b336aa0146 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
@@ -677,6 +677,12 @@
 		#size-cells = <0>;
 		#gpio-cells = <2>;
 
+		gpio-line-names =
+		"ext-vref-sel","","presence-hdd-bp5-n","presence-hdd-bp6-n",
+		"","bmc-riser-en-n","bmc-ocp1-en-n","bmc-ocp0-en-n",
+		"","","","",
+		"","","","";
+
 		bmc-ocp0-en-hog {
 			gpio-hog;
 			gpios = <7 GPIO_ACTIVE_LOW>;
@@ -684,6 +690,16 @@
 			line-name = "bmc-ocp0-en-n";
 		};
 	};
+
+	fan-controller0@20 {
+		compatible = "maxim,max31790";
+		reg = <0x20>;
+	};
+
+	fan-controller1@2f {
+		compatible = "maxim,max31790";
+		reg = <0x2f>;
+	};
 };
 
 &i2c9 {
@@ -958,7 +974,7 @@
 			"fan-fault","psu-fault",
 			"","",
 			"","",
-			"","",
+			"gpi0","gpi1",
 			"","",
 			"","",
 			"","",
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
index 82835e96317..c151984289b 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
@@ -50,14 +50,14 @@
 		i2c45 = &i2c0mux5ch1;
 		i2c46 = &i2c0mux5ch2;
 		i2c47 = &i2c0mux5ch3;
-		i2c48 = &i2c30mux0ch0;
-		i2c49 = &i2c30mux0ch1;
-		i2c50 = &i2c30mux0ch2;
-		i2c51 = &i2c30mux0ch3;
-		i2c52 = &i2c30mux0ch4;
-		i2c53 = &i2c30mux0ch5;
-		i2c54 = &i2c30mux0ch6;
-		i2c55 = &i2c30mux0ch7;
+		i2c48 = &i2c5mux0ch0;
+		i2c49 = &i2c5mux0ch1;
+		i2c50 = &i2c5mux0ch2;
+		i2c51 = &i2c5mux0ch3;
+		i2c52 = &i2c5mux0ch4;
+		i2c53 = &i2c5mux0ch5;
+		i2c54 = &i2c5mux0ch6;
+		i2c55 = &i2c5mux0ch7;
 	};
 
 	chosen {
@@ -153,6 +153,13 @@
 	status = "okay";
 };
 
+&mac2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ncsi3_default>;
+	use-ncsi;
+};
+
 &mac3 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -185,6 +192,7 @@
 		reg = <0x71>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux0ch0: i2c@0 {
 			#address-cells = <1>;
@@ -213,6 +221,7 @@
 		reg = <0x72>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux1ch0: i2c@0 {
 			#address-cells = <1>;
@@ -242,79 +251,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
-			i2c-mux@70 {
-				compatible = "nxp,pca9548";
-				reg = <0x70>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				i2c30mux0ch0: i2c@0 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <0>;
-				};
-				i2c30mux0ch1: i2c@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <1>;
-				};
-				i2c30mux0ch2: i2c@2 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <2>;
-				};
-				i2c30mux0ch3: i2c@3 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <3>;
-				};
-				i2c30mux0ch4: i2c@4 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <4>;
-				};
-				i2c30mux0ch5: i2c@5 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <5>;
-				};
-				i2c30mux0ch6: i2c@6 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <6>;
-					// HDD FRU EEPROM
-					eeprom@52 {
-						compatible = "atmel,24c64";
-						reg = <0x52>;
-					};
-				};
-				i2c30mux0ch7: i2c@7 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <7>;
-
-					power-sensor@40 {
-						compatible = "ti,ina230";
-						reg = <0x40>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@41 {
-						compatible = "ti,ina230";
-						reg = <0x41>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@44 {
-						compatible = "ti,ina230";
-						reg = <0x44>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@45 {
-						compatible = "ti,ina230";
-						reg = <0x45>;
-						shunt-resistor = <2000>;
-					};
-				};
-			};
 		};
 		i2c0mux1ch3: i2c@3 {
 			#address-cells = <1>;
@@ -328,6 +264,7 @@
 		reg = <0x73>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux2ch0: i2c@0 {
 			#address-cells = <1>;
@@ -356,6 +293,7 @@
 		reg = <0x75>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux3ch0: i2c@0 {
 			#address-cells = <1>;
@@ -384,6 +322,7 @@
 		reg = <0x76>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux4ch0: i2c@0 {
 			#address-cells = <1>;
@@ -426,6 +365,7 @@
 		reg = <0x77>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux5ch0: i2c@0 {
 			#address-cells = <1>;
@@ -512,12 +452,12 @@
 			power-monitor@42 {
 				compatible = "lltc,ltc4287";
 				reg = <0x42>;
-				shunt-resistor-micro-ohms = <200>;
+				shunt-resistor-micro-ohms = <100>;
 			};
 			power-monitor@43 {
 				compatible = "lltc,ltc4287";
 				reg = <0x43>;
-				shunt-resistor-micro-ohms = <200>;
+				shunt-resistor-micro-ohms = <100>;
 			};
 		};
 		i2c1mux0ch5: i2c@5 {
@@ -593,8 +533,6 @@
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// Module 1 IOEXP
@@ -603,8 +541,6 @@
 		reg = <0x21>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// HMC IOEXP
@@ -613,8 +549,6 @@
 		reg = <0x27>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// Module 0 EEPROM
@@ -640,6 +574,81 @@
 
 &i2c5 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c5mux0ch0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+		i2c5mux0ch1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+		i2c5mux0ch2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+		i2c5mux0ch3: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+		i2c5mux0ch4: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+		};
+		i2c5mux0ch5: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+		};
+		i2c5mux0ch6: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			// HDD FRU EEPROM
+			eeprom@52 {
+				compatible = "atmel,24c64";
+				reg = <0x52>;
+			};
+		};
+		i2c5mux0ch7: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+
+			power-sensor@40 {
+				compatible = "ti,ina230";
+				reg = <0x40>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@41 {
+				compatible = "ti,ina230";
+				reg = <0x41>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@44 {
+				compatible = "ti,ina230";
+				reg = <0x44>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@45 {
+				compatible = "ti,ina230";
+				reg = <0x45>;
+				shunt-resistor = <2000>;
+			};
+		};
+	};
 };
 
 &i2c6 {
@@ -834,9 +843,9 @@
 	};
 
 	// OCP NIC1 FRU EEPROM
-	eeprom@50 {
+	eeprom@52 {
 		compatible = "atmel,24c64";
-		reg = <0x50>;
+		reg = <0x52>;
 	};
 };
 
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
index cf3f807a38f..9cb511a846e 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
@@ -135,10 +135,6 @@
 	use-ncsi;
 };
 
-&rtc {
-	status = "okay";
-};
-
 &fmc {
 	status = "okay";
 
@@ -397,12 +393,6 @@
 		reg = <0x31>;
 		gpio-controller;
 		#gpio-cells = <2>;
-
-		gpio-line-names =
-		"","","","",
-		"","","presence-cmm","",
-		"","","","",
-		"","","","";
 	};
 
 	// PTTV FRU
@@ -426,12 +416,6 @@
 		reg = <0x31>;
 		gpio-controller;
 		#gpio-cells = <2>;
-
-		gpio-line-names =
-		"","","","",
-		"","","presence-cmm","",
-		"","","","",
-		"","","","";
 	};
 
 	// Aegis FRU
@@ -506,6 +490,11 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <3>;
+
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
 		};
 	};
 };
@@ -565,7 +554,7 @@
 	/*B0-B7*/	"","","","",
 			"bmc-spi-mux-select-0","led-identify","","",
 	/*C0-C7*/	"reset-cause-platrst","","","","",
-			"cpu0-err-alert","","",
+			"power-hsc-good","power-chassis-good","",
 	/*D0-D7*/	"","","sol-uart-select","","","","","",
 	/*E0-E7*/	"","","","","","","","",
 	/*F0-F7*/	"","","","","","","","",
@@ -584,14 +573,16 @@
 	/*O0-O7*/	"","","","","","","","",
 	/*P0-P7*/	"power-button","power-host-control",
 			"reset-button","","led-power","","","",
-	/*Q0-Q7*/	"","","","","","power-chassis-control","","",
+	/*Q0-Q7*/
+			"","","","",
+			"","power-chassis-control","","uart-switch-button",
 	/*R0-R7*/	"","","","","","","","",
 	/*S0-S7*/	"","","","","","","","",
 	/*T0-T7*/	"","","","","","","","",
 	/*U0-U7*/	"","","","","","","led-identify-gate","",
 	/*V0-V7*/	"","","","",
 			"rtc-battery-voltage-read-enable","",
-			"power-chassis-good","",
+			"","",
 	/*W0-W7*/	"","","","","","","","",
 	/*X0-X7*/	"","","","","","","","",
 	/*Y0-Y7*/	"","","","","","","","",
@@ -672,7 +663,7 @@
 	"presence-asic-modules-0","rt-cpu0-p1-force-enable",
 	"presence-asic-modules-1","bios-debug-msg-disable",
 	"","uart-control-buffer-select",
-	"","ac-control-n",
+	"presence-cmm","ac-control-n",
 	/*G0-G3 line 96-103*/
 	"FM_CPU_CORETYPE2","",
 	"FM_CPU_CORETYPE1","",
@@ -684,7 +675,7 @@
 	"FM_BOARD_REV_ID2","",
 	"FM_BOARD_REV_ID1","",
 	/*H0-H3 line 112-119*/
-	"FM_BOARD_REV_ID0","",
+	"FM_BOARD_REV_ID0","reset-control-cmos-clear",
 	"","","","","","",
 	/*H4-H7 line 120-127*/
 	"","",
@@ -699,7 +690,7 @@
 	/*I4-I7 line 136-143*/
 	"","","","","","","","",
 	/*J0-J3 line 144-151*/
-	"","","","","","","","",
+	"","","power-card-enable","","","","","",
 	/*J4-J7 line 152-159*/
 	"SLOT_ID_BCB_0","",
 	"SLOT_ID_BCB_1","",
@@ -715,9 +706,15 @@
 	"cpu0-thermtrip-alert","",
 	"reset-cause-pcie","",
 	/*L4-L7 line 184-191*/
-	"pvdd11-ocp-alert","","","","","","","",
+	"pvdd11-ocp-alert","",
+	"power-fault-n","",
+	"asic0-card-type-detection0-n","",
+	"asic0-card-type-detection1-n","",
 	/*M0-M3 line 192-199*/
-	"","","","","","","","",
+	"asic0-card-type-detection2-n","",
+	"uart-switch-lsb","",
+	"uart-switch-msb","",
+	"","",
 	/*M4-M7 line 200-207*/
 	"","","","","","","","",
 	/*N0-N3 line 208-215*/
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
index 41e2246cfbd..ef96b17becb 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
@@ -23,6 +23,32 @@
 		i2c19 = &imux19;
 		i2c20 = &imux20;
 		i2c21 = &imux21;
+		i2c22 = &imux22;
+		i2c23 = &imux23;
+		i2c24 = &imux24;
+		i2c25 = &imux25;
+		i2c26 = &imux26;
+		i2c27 = &imux27;
+		i2c28 = &imux28;
+		i2c29 = &imux29;
+		i2c30 = &imux30;
+		i2c31 = &imux31;
+		i2c32 = &imux32;
+		i2c33 = &imux33;
+		i2c34 = &imux34;
+		i2c35 = &imux35;
+		i2c36 = &imux36;
+		i2c37 = &imux37;
+		i2c38 = &imux38;
+		i2c39 = &imux39;
+		i2c40 = &imux40;
+		i2c41 = &imux41;
+		i2c42 = &imux42;
+		i2c43 = &imux43;
+		i2c44 = &imux44;
+		i2c45 = &imux45;
+		i2c46 = &imux46;
+		i2c47 = &imux47;
 
 		spi1 = &spi_gpio;
 	};
@@ -75,6 +101,11 @@
 			gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
+
+		led-5 {
+			label = "bmc_ready_noled";
+			gpios = <&sgpiom0 141 (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>;
+		};
 	};
 
 	spi_gpio: spi {
@@ -182,6 +213,63 @@
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
+
+	gpio@11 {
+		compatible = "nxp,pca9555";
+		reg = <0x11>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <238 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"PWRGD_P24V_SMPWROK", "P1V5_PWROK",
+		"P3V3_PWROK", "P5V_PWROK",
+		"P12V_SCM_PWROK", "P12V_PWROK",
+		"P24V_PWROK", "P48V_HSC_PWROK",
+		"ERR_GPIO_IRQ", "TMP75_ALERT_N",
+		"BMC_PWROK", "P12V_INA230_ALERT_N",
+		"P24V_INA230_ALERT_N","",
+		"P48V_HSC_ALERT_N", "P1V05_PWROK";
+	};
+
+	gpio@12 {
+		compatible = "nxp,pca9555";
+		reg = <0x12>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <240 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"P1V05_PWR_FAIL", "P1V5_PWR_FAIL",
+		"P24V_PWR_FAIL", "P24V_SM_PWR_FAIL",
+		"IRQ_NW0/1/2_N", "IRQ_NW3/4/5_N",
+		"RTC_INT_N_R", "ERR_GPIO_IRQ",
+		"", "",
+		"", "",
+		"", "",
+		"", "";
+	};
+
+	gpio@13 {
+		compatible = "nxp,pca9555";
+		reg = <0x13>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <242 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"", "",
+		"", "",
+		"", "",
+		"", "",
+		"RACKMON_A_1", "RACKMON_A_2",
+		"RACKMON_B_1", "RACKMON_B_2",
+		"", "",
+		"", "";
+	};
 };
 
 &i2c1 {
@@ -213,10 +301,11 @@
 		#size-cells = <0>;
 		i2c-mux-idle-disconnect;
 
-		imux16: i2c@0 {
+		// FCB 1
+		imux16: i2c@1 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			reg = <1>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -258,12 +347,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux17: i2c@1 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN1_PWRGD_R", "P48V_FAN2_PWRGD_R",
+				"P48V_FAN3_PWRGD_R", "P48V_FAN4_PWRGD_R",
+				"FCB_1_P48V_ZONE0_PWRGD_R", "FCB_1_P48V_ZONE1_PWRGD_R",
+				"FCB_1_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN1_ALERT_N", "INA238_FAN2_ALERT_N",
+				"INA238_FAN3_ALERT_N", "INA238_FAN4_ALERT_N",
+				"FCB_1_TMP75_ALERT_N", "",
+				"", "",
+				"FAN1_PRSNT", "FAN2_PRSNT",
+				"FAN3_PRSNT", "FAN4_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN1_IL_TACH_ALERT", "FAN1_OL_TACH_ALERT",
+				"FAN2_IL_TACH_ALERT", "FAN2_OL_TACH_ALERT",
+				"FAN3_IL_TACH_ALERT", "FAN3_OL_TACH_ALERT",
+				"FAN4_IL_TACH_ALERT", "FAN4_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_1_P1V0_POWER_FAIL", "FCB_1_P1V8_POWER_FAIL",
+				"FCB_1_P48V_ZONE0_POWER_FAIL", "FAN1_POWER_FAIL",
+				"FAN2_POWER_FAIL", "FAN3_POWER_FAIL",
+				"FAN4_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 2
+		imux17: i2c@0 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <1>;
+			reg = <0>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -305,12 +470,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux18: i2c@2 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN5_PWRGD_R", "P48V_FAN6_PWRGD_R",
+				"P48V_FAN7_PWRGD_R", "P48V_FAN8_PWRGD_R",
+				"FCB_2_P48V_ZONE0_PWRGD_R", "FCB_2_P48V_ZONE1_PWRGD_R",
+				"FCB_2_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN5_ALERT_N", "INA238_FAN6_ALERT_N",
+				"INA238_FAN7_ALERT_N", "INA238_FAN8_ALERT_N",
+				"FCB_2_TMP75_ALERT_N", "",
+				"", "",
+				"FAN5_PRSNT", "FAN6_PRSNT",
+				"FAN7_PRSNT", "FAN8_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN5_IL_TACH_ALERT", "FAN5_OL_TACH_ALERT",
+				"FAN6_IL_TACH_ALERT", "FAN6_OL_TACH_ALERT",
+				"FAN7_IL_TACH_ALERT", "FAN7_OL_TACH_ALERT",
+				"FAN8_IL_TACH_ALERT", "FAN8_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_2_P1V0_POWER_FAIL", "FCB_2_P1V8_POWER_FAIL",
+				"FCB_2_P48V_ZONE0_POWER_FAIL", "FAN5_POWER_FAIL",
+				"FAN6_POWER_FAIL", "FAN7_POWER_FAIL",
+				"FAN8_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 3
+		imux18: i2c@3 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <2>;
+			reg = <3>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -352,12 +593,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux19: i2c@3 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN9_PWRGD_R", "P48V_FAN10_PWRGD_R",
+				"P48V_FAN11_PWRGD_R", "P48V_FAN12_PWRGD_R",
+				"FCB_3_P48V_ZONE0_PWRGD_R", "FCB_3_P48V_ZONE1_PWRGD_R",
+				"FCB_3_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN9_ALERT_N", "INA238_FAN10_ALERT_N",
+				"INA238_FAN11_ALERT_N", "INA238_FAN12_ALERT_N",
+				"FCB_3_TMP75_ALERT_N", "",
+				"", "",
+				"FAN9_PRSNT", "FAN10_PRSNT",
+				"FAN11_PRSNT", "FAN12_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN9_IL_TACH_ALERT", "FAN9_OL_TACH_ALERT",
+				"FAN10_IL_TACH_ALERT", "FAN10_OL_TACH_ALERT",
+				"FAN11_IL_TACH_ALERT", "FAN11_OL_TACH_ALERT",
+				"FAN12_IL_TACH_ALERT", "FAN12_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_3_P1V0_POWER_FAIL", "FCB_3_P1V8_POWER_FAIL",
+				"FCB_3_P48V_ZONE0_POWER_FAIL", "FAN9_POWER_FAIL",
+				"FAN10_POWER_FAIL", "FAN11_POWER_FAIL",
+				"FAN12_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 4
+		imux19: i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <3>;
+			reg = <2>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -399,9 +716,85 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux20: i2c@5 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN13_PWRGD_R", "P48V_FAN14_PWRGD_R",
+				"P48V_FAN15_PWRGD_R", "P48V_FAN16_PWRGD_R",
+				"FCB_4_P48V_ZONE0_PWRGD_R", "FCB_4_P48V_ZONE1_PWRGD_R",
+				"FCB_4_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN13_ALERT_N", "INA238_FAN14_ALERT_N",
+				"INA238_FAN15_ALERT_N", "INA238_FAN16_ALERT_N",
+				"FCB_4_TMP75_ALERT_N", "",
+				"", "",
+				"FAN13_PRSNT", "FAN14_PRSNT",
+				"FAN15_PRSNT", "FAN16_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN13_IL_TACH_ALERT", "FAN13_OL_TACH_ALERT",
+				"FAN14_IL_TACH_ALERT", "FAN14_OL_TACH_ALERT",
+				"FAN15_IL_TACH_ALERT", "FAN15_OL_TACH_ALERT",
+				"FAN16_IL_TACH_ALERT", "FAN16_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_4_P1V0_POWER_FAIL", "FCB_4_P1V8_POWER_FAIL",
+				"FCB_4_P48V_ZONE0_POWER_FAIL", "FAN13_POWER_FAIL",
+				"FAN14_POWER_FAIL", "FAN15_POWER_FAIL",
+				"FAN16_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 5
+		imux20: i2c@4 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
@@ -445,9 +838,85 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux21: i2c@4 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN20_PWRGD_R", "P48V_FAN19_PWRGD_R",
+				"P48V_FAN18_PWRGD_R", "P48V_FAN17_PWRGD_R",
+				"FCB_5_P48V_ZONE0_PWRGD_R", "FCB_5_P48V_ZONE1_PWRGD_R",
+				"FCB_5_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN20_ALERT_N", "INA238_FAN19_ALERT_N",
+				"INA238_FAN18_ALERT_N", "INA238_FAN17_ALERT_N",
+				"FCB_5_TMP75_ALERT_N", "",
+				"", "",
+				"FAN20_PRSNT", "FAN19_PRSNT",
+				"FAN18_PRSNT", "FAN17_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN20_IL_TACH_ALERT", "FAN20_OL_TACH_ALERT",
+				"FAN19_IL_TACH_ALERT", "FAN19_OL_TACH_ALERT",
+				"FAN18_IL_TACH_ALERT", "FAN18_OL_TACH_ALERT",
+				"FAN17_IL_TACH_ALERT", "FAN17_OL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_5_P1V0_POWER_FAIL", "FCB_5_P1V8_POWER_FAIL",
+				"FCB_5_P48V_ZONE0_POWER_FAIL", "FAN20_POWER_FAIL",
+				"FAN19_POWER_FAIL", "FAN18_POWER_FAIL",
+				"FAN17_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 6
+		imux21: i2c@5 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <5>;
@@ -491,24 +960,316 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
+
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN24_PWRGD_R", "P48V_FAN23_PWRGD_R",
+				"P48V_FAN22_PWRGD_R", "P48V_FAN21_PWRGD_R",
+				"FCB_6_P48V_ZONE0_PWRGD_R", "FCB_6_P48V_ZONE1_PWRGD_R",
+				"FCB_6_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN24_ALERT_N", "INA238_FAN23_ALERT_N",
+				"INA238_FAN22_ALERT_N", "INA238_FAN21_ALERT_N",
+				"FCB_6_TMP75_ALERT_N", "",
+				"", "",
+				"FAN24_PRSNT", "FAN23_PRSNT",
+				"FAN22_PRSNT", "FAN21_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN24_IL_TACH_ALERT", "FAN24_OL_TACH_ALERT",
+				"FAN23_IL_TACH_ALERT", "FAN23_OL_TACH_ALERT",
+				"FAN22_IL_TACH_ALERT", "FAN22_OL_TACH_ALERT",
+				"FAN21_IL_TACH_ALERT", "FAN21_OL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_6_P1V0_POWER_FAIL", "FCB_6_P1V8_POWER_FAIL",
+				"FCB_6_P48V_ZONE0_POWER_FAIL", "FAN24_POWER_FAIL",
+				"FAN23_POWER_FAIL", "FAN22_POWER_FAIL",
+				"FAN21_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		imux22: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+		};
+
+		imux23: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
 		};
 	};
 };
 
 &i2c3 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux24: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux25: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux26: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux27: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c4 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux28: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux29: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux30: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux31: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c5 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux32: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux33: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux34: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux35: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c6 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux36: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux37: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux38: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux39: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c7 {
@@ -531,14 +1292,111 @@
 		compatible = "nxp,pcf8563";
 		reg = <0x51>;
 	};
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
 };
 
 &i2c12 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux40: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux41: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux42: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux43: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
 };
 
 &i2c13 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux44: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux45: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux46: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux47: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
 };
 
 &i2c14 {
@@ -627,7 +1485,6 @@
 	gpio-line-names =
 	/*"input pin","output pin"*/
 	/*A0 - A7*/
-	"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
 	"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
 	"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
 	"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
@@ -635,8 +1492,8 @@
 	"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
 	"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
 	"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
-	/*B0 - B7*/
 	"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
+	/*B0 - B7*/
 	"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
 	"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
 	"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
@@ -644,80 +1501,80 @@
 	"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
 	"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
 	"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
+	"PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N",
 	/*C0 - C7*/
-	"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
 	"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
 	"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
 	"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
 	"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
 	"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
-	"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
-	"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+	"PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N",
+	"PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+	"PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N",
 	/*D0 - D7*/
-	"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
-	"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
-	"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
-	"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
-	"PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
+	"PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N",
+	"PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N",
+	"PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N",
+	"PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N",
 	"PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
 	"PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
 	"PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
-	/*E0 - E7*/
 	"PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
+	/*E0 - E7*/
 	"PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
 	"PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
 	"PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
 	"PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
 	"PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
-	"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
+	"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N",
 	"PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
-	/*F0 - F7*/
 	"PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
+	/*F0 - F7*/
 	"PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
 	"PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
 	"PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
-	"PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
-	"PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
-	"PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
-	"PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
+	"PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N",
+	"PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N",
+	"PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N",
+	"PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N",
+	"PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N",
 	/*G0 - G7*/
-	"PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
-	"PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
-	"PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
-	"PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
-	"PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
-	"PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
-	"PWRGD_FCB_BOTTOM_1_PWROK_N","",
-	"PWRGD_FCB_BOTTOM_0_PWROK_N","",
+	"PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N",
+	"PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N",
+	"PWRGD_FCB_1","FM_BMC_RST_RTCRST_R",
+	"PWRGD_FCB_2","",
+	"PWRGD_FCB_3","FM_MDIO_SW_SEL",
+	"PWRGD_FCB_4","FM_P24V_SMPWR_EN",
+	"PWRGD_FCB_6","",
+	"PWRGD_FCB_5","",
 	/*H0 - H7*/
-	"LEAK_DETECT_MTIA_BLADE0_N","",
 	"LEAK_DETECT_MTIA_BLADE1_N","",
 	"LEAK_DETECT_MTIA_BLADE2_N","",
 	"LEAK_DETECT_MTIA_BLADE3_N","",
 	"LEAK_DETECT_MTIA_BLADE4_N","",
 	"LEAK_DETECT_MTIA_BLADE5_N","",
 	"LEAK_DETECT_MTIA_BLADE6_N","",
-	"LEAK_DETECT_MTIA_BLADE7_N","",
+	"LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N",
+	"LEAK_DETECT_MTIA_BLADE8_N","",
 	/*I0 - I7*/
-	"LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
-	"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
-	"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
-	"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
-	"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
-	"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
-	"LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
-	"LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
+	"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N",
+	"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N",
+	"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N",
+	"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N",
+	"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N",
+	"LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N",
+	"LEAK_DETECT_MTIA_BLADE15_N","BMC_READY",
+	"LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N",
 	/*J0 - J7*/
-	"LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
-	"LEAK_DETECT_NW_BLADE1_N","",
+	"LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N",
 	"LEAK_DETECT_NW_BLADE2_N","",
 	"LEAK_DETECT_NW_BLADE3_N","",
 	"LEAK_DETECT_NW_BLADE4_N","",
 	"LEAK_DETECT_NW_BLADE5_N","",
-	"PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
+	"LEAK_DETECT_NW_BLADE6_N","",
 	"PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
-	/*K0 - K7*/
 	"PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
+	/*K0 - K7*/
 	"PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
@@ -725,49 +1582,50 @@
 	"PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
-	/*L0 - L7*/
 	"PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
+	/*L0 - L7*/
 	"PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
-	"PWRGD_NW_BLADE0_HSC_PWROK_N","",
+	"PWRGD_MTIA_BLADE16_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE1_HSC_PWROK_N","",
-	/*M0 - M7*/
 	"PWRGD_NW_BLADE2_HSC_PWROK_N","",
+	/*M0 - M7*/
 	"PWRGD_NW_BLADE3_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE4_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE5_HSC_PWROK_N","",
+	"PWRGD_NW_BLADE6_HSC_PWROK_N","",
 	"RPU_READY","",
 	"IT_GEAR_RPU_LINK_N","",
 	"IT_GEAR_LEAK","",
 	"WATER_VALVE_CLOSED_N","",
 	/*N0 - N7*/
-	"VALVE_STS0","",
-	"VALVE_STS1","",
-	"PCA9555_IRQ0_N","",
+	"VALVE_STATUS_0","",
+	"VALVE_STATUS_1","",
 	"PCA9555_IRQ1_N","",
+	"PCA9555_IRQ2_N","",
 	"CR_TOGGLE_BOOT_N","",
-	"IRQ_FCB_TOP0_N","",
-	"IRQ_FCB_TOP1_N","",
+	"IRQ_FCB_1_N","",
+	"IRQ_FCB_2_N","",
 	"CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
 	/*O0 - O7*/
 	"CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
 	"BOT_BCB_CABLE_PRSNT_N","",
 	"TOP_BCB_CABLE_PRSNT_N","",
-	"IRQ_FCB_MID0_N","",
-	"IRQ_FCB_MID1_N","",
+	"IRQ_FCB_3_N","",
+	"IRQ_FCB_4_N","",
 	"CHASSIS_LEAK0_DETECT_N","",
 	"CHASSIS_LEAK1_DETECT_N","",
-	"VALVE_RMON_A_1","",
+	"PCA9555_IRQ3_N","",
 	/*P0 - P7*/
-	"VALVE_RMON_A_2","",
-	"VALVE_RMON_B_1","",
-	"VALVE_RMON_B_2","",
+	"PCA9555_IRQ4_N","",
+	"PCA9555_IRQ5_N","",
+	"CMM_AC_PWR_BTN_N","",
 	"RPU_READY_SPARE","",
 	"IT_GEAR_LEAK_SPARE","",
 	"IT_GEAR_RPU_LINK_SPARE_N","",
-	"IRQ_FCB_BOT0_N","",
-	"IRQ_FCB_BOT0_N","";
+	"IRQ_FCB_6_N","",
+	"IRQ_FCB_5_N","";
 };
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 98477792aa0..29f224bccd6 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -17,6 +17,27 @@
 		serial6 = &uart7;
 		serial7 = &uart8;
 		serial8 = &uart9;
+
+		i2c16 = &imux16;
+		i2c17 = &imux17;
+		i2c18 = &imux18;
+		i2c19 = &imux19;
+		i2c20 = &imux20;
+		i2c21 = &imux21;
+		i2c22 = &imux22;
+		i2c23 = &imux23;
+		i2c24 = &imux24;
+		i2c25 = &imux25;
+		i2c26 = &imux26;
+		i2c27 = &imux27;
+		i2c28 = &imux28;
+		i2c29 = &imux29;
+		i2c30 = &imux30;
+		i2c31 = &imux31;
+		i2c32 = &imux32;
+		i2c33 = &imux33;
+		i2c34 = &imux34;
+		i2c35 = &imux35;
 	};
 
 	chosen {
@@ -32,7 +53,25 @@
 		compatible = "iio-hwmon";
 		io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
 				<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
-				<&adc1 0>, <&adc1 1>;
+				<&adc1 0>, <&adc1 1>, <&adc1 7>;
+	};
+
+	spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+		miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+
+		tpm@0 {
+			compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+			reg = <0>;
+			spi-max-frequency = <33000000>;
+		};
 	};
 };
 
@@ -83,6 +122,13 @@
 	aspeed,ext-pulse-duration = <256>;
 };
 
+&wdt2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdtrst2_default>;
+	aspeed,reset-type = "system";
+};
+
 &mac2 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -105,15 +151,17 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
 	};
 	flash@1 {
 		status = "okay";
 		m25p,fast-read;
-		label = "bmc2";
-		spi-rx-bus-width = <4>;
+		label = "alt-bmc";
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
 	};
 };
@@ -129,9 +177,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -146,9 +223,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -163,9 +269,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -180,9 +315,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -197,9 +361,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -214,9 +407,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -231,9 +453,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -248,48 +499,363 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
 &i2c8 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	i2c-mux@70 {
 		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
 		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux16: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux17: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux18: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux19: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
 	};
 };
 
 &i2c9 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	i2c-mux@71 {
 		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
 		reg = <0x71>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux20: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux21: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux22: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux23: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
 	};
 };
 
 &i2c10 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
+	i2c-mux@74 {
+		compatible = "nxp,pca9544";
+		reg = <0x74>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux28: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio@20 {
+				compatible = "nxp,pca9506";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@21 {
+				compatible = "nxp,pca9506";
+				reg = <0x21>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@22 {
+				compatible = "nxp,pca9506";
+				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@23 {
+				compatible = "nxp,pca9506";
+				reg = <0x23>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@24 {
+				compatible = "nxp,pca9506";
+				reg = <0x24>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-line-names = "","","","",
+						  "NIC0_MAIN_PWR_EN",
+						  "NIC1_MAIN_PWR_EN",
+						  "NIC2_MAIN_PWR_EN",
+						  "NIC3_MAIN_PWR_EN",
+						  "","","","","","","","",
+						  "","","","","","","","",
+						  "","","","","","","","";
+			};
+		};
+
+		imux29: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
 };
 
 &i2c11 {
 	status = "okay";
 	power-sensor@10 {
-		compatible = "adi, adm1272";
+		compatible = "adi,adm1272";
 		reg = <0x10>;
 	};
 
 	power-sensor@12 {
-		compatible = "adi, adm1272";
+		compatible = "adi,adm1272";
 		reg = <0x12>;
 	};
 
@@ -298,6 +864,20 @@
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "P48V_OCP_GPIO1", "P48V_OCP_GPIO2",
+				  "P48V_OCP_GPIO3", "FAN_BOARD_0_REVISION_0_R",
+				  "FAN_BOARD_0_REVISION_1_R",
+				  "FAN_BOARD_1_REVISION_0_R",
+				  "FAN_BOARD_1_REVISION_1_R", "RST_MUX_R_N",
+				  "RST_LED_CONTROL_FAN_BOARD_0_N",
+				  "RST_LED_CONTROL_FAN_BOARD_1_N",
+				  "RST_IOEXP_FAN_BOARD_0_N",
+				  "RST_IOEXP_FAN_BOARD_1_N",
+				  "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R",
+				  "PWRGD_LOAD_SWITCH_FAN_BOARD_1_R",
+				  "", "";
 	};
 
 	gpio@21 {
@@ -305,6 +885,19 @@
 		reg = <0x21>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "HSC_OCP_SLOT_ODD_GPIO1",
+				  "HSC_OCP_SLOT_ODD_GPIO2",
+				  "HSC_OCP_SLOT_ODD_GPIO3",
+				  "HSC_OCP_SLOT_EVEN_GPIO1",
+				  "HSC_OCP_SLOT_EVEN_GPIO2",
+				  "HSC_OCP_SLOT_EVEN_GPIO3",
+				  "ADC_TYPE_0_R", "ADC_TYPE_1_R",
+				  "MEDUSA_BOARD_REV_0", "MEDUSA_BOARD_REV_1",
+				  "MEDUSA_BOARD_REV_2", "MEDUSA_BOARD_TYPE",
+				  "DELTA_MODULE_TYPE", "P12V_HSC_TYPE",
+				  "", "";
 	};
 
 	gpio@22 {
@@ -312,6 +905,16 @@
 		reg = <0x22>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "CARD_TYPE_SLOT1", "CARD_TYPE_SLOT2",
+				  "CARD_TYPE_SLOT3", "CARD_TYPE_SLOT4",
+				  "CARD_TYPE_SLOT5", "CARD_TYPE_SLOT6",
+				  "CARD_TYPE_SLOT7", "CARD_TYPE_SLOT8",
+				  "OC_P48V_HSC_0_N", "FLT_P48V_HSC_0_N",
+				  "OC_P48V_HSC_1_N", "FLT_P48V_HSC_1_N",
+				  "EN_P48V_AUX_0", "EN_P48V_AUX_1",
+				  "PWRGD_P12V_AUX_0", "PWRGD_P12V_AUX_1";
 	};
 
 	gpio@23 {
@@ -319,6 +922,16 @@
 		reg = <0x23>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "HSC1_ALERT1_R_N", "HSC2_ALERT1_R_N",
+				  "HSC3_ALERT1_R_N", "HSC4_ALERT1_R_N",
+				  "HSC5_ALERT1_R_N", "HSC6_ALERT1_R_N",
+				  "HSC7_ALERT1_R_N", "HSC8_ALERT1_R_N",
+				  "HSC1_ALERT2_R_N", "HSC2_ALERT2_R_N",
+				  "HSC3_ALERT2_R_N", "HSC4_ALERT2_R_N",
+				  "HSC5_ALERT2_R_N", "HSC6_ALERT2_R_N",
+				  "HSC7_ALERT2_R_N", "HSC8_ALERT2_R_N";
 	};
 
 	temperature-sensor@48 {
@@ -331,39 +944,84 @@
 		reg = <0x49>;
 	};
 
-	temperature-sensor@4a {
-		compatible = "ti,tmp75";
-		reg = <0x4a>;
-	};
-
-	temperature-sensor@4b {
-		compatible = "ti,tmp75";
-		reg = <0x4b>;
-	};
-
 	eeprom@54 {
-		compatible = "atmel,24c256";
+		compatible = "atmel,24c128";
 		reg = <0x54>;
 	};
 };
 
 &i2c12 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 
-	temperature-sensor@48 {
-		compatible = "ti,tmp75";
-		reg = <0x48>;
-	};
+	i2c-mux@70 {
+		compatible = "nxp,pca9544";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
-	eeprom@50 {
-		compatible = "atmel,24c128";
-		reg = <0x50>;
-	};
+		imux34: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			temperature-sensor@48 {
+				compatible = "ti,tmp75";
+				reg = <0x48>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c64";
+				reg = <0x54>;
+			};
+
+			rtc@6f {
+				compatible = "nuvoton,nct3018y";
+				reg = <0x6f>;
+			};
 
-	rtc@6f {
-		compatible = "nuvoton,nct3018y";
-		reg = <0x6f>;
+			gpio@20 {
+				compatible = "nxp,pca9506";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@21 {
+				compatible = "nxp,pca9506";
+				reg = <0x21>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@22 {
+				compatible = "nxp,pca9506";
+				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@23 {
+				compatible = "nxp,pca9506";
+				reg = <0x23>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		imux35: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
 
@@ -380,24 +1038,26 @@
 };
 
 &i2c14 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	adc@1d {
 		compatible = "ti,adc128d818";
 		reg = <0x1d>;
-		ti,mode = /bits/ 8 <2>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
-	adc@35 {
+	adc@36 {
 		compatible = "ti,adc128d818";
-		reg = <0x35>;
-		ti,mode = /bits/ 8 <2>;
+		reg = <0x36>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
 	adc@37 {
 		compatible = "ti,adc128d818";
 		reg = <0x37>;
-		ti,mode = /bits/ 8 <2>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
 	power-sensor@40 {
@@ -440,43 +1100,67 @@
 		reg = <0x51>;
 	};
 
-	i2c-mux@71 {
-		compatible = "nxp,pca9846";
+	i2c-mux@73 {
+		compatible = "nxp,pca9544";
+		reg = <0x73>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-
-		idle-state = <0>;
 		i2c-mux-idle-disconnect;
-		reg = <0x71>;
 
-		i2c@0 {
+		imux32: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			adc@35 {
+				compatible = "maxim,max11617";
+				reg = <0x35>;
+			};
+		};
+
+		imux33: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			adc@35 {
+				compatible = "maxim,max11617";
+				reg = <0x35>;
+			};
+		};
+	};
+
+	i2c-mux@74 {
+		compatible = "nxp,pca9546";
+		reg = <0x74>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux30: i2c@0 {
 			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
 			adc@1f {
 				compatible = "ti,adc128d818";
 				reg = <0x1f>;
-				ti,mode = /bits/ 8 <2>;
+				ti,mode = /bits/ 8 <1>;
 			};
 
 			pwm@20{
-				compatible = "max31790";
+				compatible = "maxim,max31790";
 				reg = <0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 			};
 
 			gpio@22{
 				compatible = "ti,tca6424";
 				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			pwm@23{
-				compatible = "max31790";
-				reg = <0x23>;
-				#address-cells = <1>;
-				#size-cells = <0>;
+			pwm@2f{
+				compatible = "maxim,max31790";
+				reg = <0x2f>;
 			};
 
 			adc@33 {
@@ -499,34 +1183,32 @@
 			};
 		};
 
-		i2c@1 {
+		imux31: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
 
 			adc@1f {
 				compatible = "ti,adc128d818";
 				reg = <0x1f>;
-				ti,mode = /bits/ 8 <2>;
+				ti,mode = /bits/ 8 <1>;
 			};
 
 			pwm@20{
-				compatible = "max31790";
+				compatible = "maxim,max31790";
 				reg = <0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 			};
 
 			gpio@22{
 				compatible = "ti,tca6424";
 				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			pwm@23{
-				compatible = "max31790";
-				reg = <0x23>;
-				#address-cells = <1>;
-				#size-cells = <0>;
+			pwm@2f{
+				compatible = "maxim,max31790";
+				reg = <0x2f>;
 			};
 
 			adc@33 {
@@ -549,56 +1231,89 @@
 			};
 		};
 	};
+};
 
-	i2c-mux@73 {
+&i2c15 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	multi-master;
+	bus-frequency = <400000>;
+
+	mctp@10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	i2c-mux@72 {
 		compatible = "nxp,pca9544";
+		reg = <0x72>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
-		reg = <0x73>;
-
-		i2c@0 {
+		imux24: i2c@0 {
+			reg = <0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-			adc@35 {
-				compatible = "maxim,max11617";
-				reg = <0x35>;
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
 			};
 		};
 
-		i2c@1 {
+		imux25: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-			adc@35 {
-				compatible = "maxim,max11617";
-				reg = <0x35>;
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
 			};
 		};
-	};
-};
 
-&i2c15 {
-	status = "okay";
-	mctp-controller;
-	multi-master;
-	bus-frequency = <400000>;
+		imux26: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-	mctp@10 {
-		compatible = "mctp-i2c-controller";
-		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
-	};
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
 
-	i2c-mux@72 {
-		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
-		reg = <0x72>;
+		imux27: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
 	};
 };
 
@@ -612,10 +1327,10 @@
 
 &adc1 {
 	status = "okay";
-	pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
+	pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+			&pinctrl_adc15_default>;
 };
 
-
 &ehci0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
index dfe5cc3edb5..bc4c4623542 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
@@ -207,7 +207,8 @@
 	/*F0-F7*/	"","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","",
 			"factory-reset-toggle","",
 	/*G0-G7*/	"","","","","","","","",
-	/*H0-H7*/	"","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","",
+	/*H0-H7*/	"","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","",
+			"",
 	/*I0-I7*/	"","","","","","","bmc-secure-boot","",
 	/*J0-J7*/	"","","","","","","","",
 	/*K0-K7*/	"","","","","","","","",
@@ -215,7 +216,7 @@
 	/*M0-M7*/	"","","","","","","","",
 	/*N0-N7*/	"","","","","","","","",
 	/*O0-O7*/	"","","","usb-power","","","","",
-	/*P0-P7*/	"","","","","pcieslot-power","","","",
+	/*P0-P7*/	"","","","","led-pcieslot-power","","","",
 	/*Q0-Q7*/	"cfam-reset","","regulator-standby-faulted","","","","","",
 	/*R0-R7*/	"bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","",
 			"",
@@ -739,7 +740,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm10";
@@ -747,7 +748,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm11";
@@ -755,7 +756,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm12";
@@ -763,7 +764,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm13";
@@ -771,7 +772,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm14";
@@ -779,7 +780,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm15";
@@ -876,7 +877,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm26";
@@ -884,7 +885,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm27";
@@ -892,7 +893,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm28";
@@ -900,7 +901,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm29";
@@ -908,7 +909,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm30";
@@ -916,7 +917,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm31";
@@ -1005,7 +1006,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "pcieslot7";
@@ -1013,7 +1014,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "pcieslot8";
@@ -1021,7 +1022,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "pcieslot9";
@@ -1029,7 +1030,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "pcieslot10";
@@ -1037,7 +1038,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "pcieslot11";
@@ -1045,7 +1046,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "tpm-wilson";
@@ -1231,8 +1232,9 @@
 		#gpio-cells = <2>;
 
 		gpio-line-names =
-			"", "", "", "", "", "", "", "",
-			"", "", "", "", "", "", "power-config-full-load", "";
+			"", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES",
+			"", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N",
+			"power-config-full-load", "";
 	};
 
 	led-controller@61 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
index 513077a1f4b..9961508ee87 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
@@ -353,6 +353,33 @@
 			"presence-base-op",
 			"";
 	};
+
+	led-controller@63 {
+		compatible = "nxp,pca9552";
+		reg = <0x63>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"presence-vrm-c12",
+			"presence-vrm-c13",
+			"presence-vrm-c15",
+			"presence-vrm-c16",
+			"presence-vrm-c17",
+			"presence-vrm-c18",
+			"presence-vrm-c20",
+			"presence-vrm-c21",
+			"presence-vrm-c54",
+			"presence-vrm-c55",
+			"presence-vrm-c57",
+			"presence-vrm-c58",
+			"presence-vrm-c59",
+			"presence-vrm-c60",
+			"presence-vrm-c62",
+			"presence-vrm-c63";
+	};
 };
 
 &i2c1 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
index c24e464e5fa..9a43fc7bceb 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
@@ -355,6 +355,33 @@
 			"presence-base-op",
 			"";
 	};
+
+	led-controller@63 {
+		compatible = "nxp,pca9552";
+		reg = <0x63>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"presence-vrm-c12",
+			"presence-vrm-c13",
+			"presence-vrm-c15",
+			"presence-vrm-c16",
+			"presence-vrm-c17",
+			"presence-vrm-c18",
+			"presence-vrm-c20",
+			"presence-vrm-c21",
+			"presence-vrm-c54",
+			"presence-vrm-c55",
+			"presence-vrm-c57",
+			"presence-vrm-c58",
+			"presence-vrm-c59",
+			"presence-vrm-c60",
+			"presence-vrm-c62",
+			"presence-vrm-c63";
+	};
 };
 
 &i2c1 {
@@ -949,7 +976,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "pcieslot-c10";
@@ -957,7 +984,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "pcieslot-c11";
@@ -1058,7 +1085,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm10";
@@ -1066,7 +1093,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm11";
@@ -1074,7 +1101,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm12";
@@ -1082,7 +1109,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm13";
@@ -1090,7 +1117,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm14";
@@ -1098,7 +1125,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm15";
@@ -1195,7 +1222,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm26";
@@ -1203,7 +1230,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm27";
@@ -1211,7 +1238,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm28";
@@ -1219,7 +1246,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm29";
@@ -1227,7 +1254,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm30";
@@ -1235,7 +1262,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm31";
@@ -1332,7 +1359,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm42";
@@ -1340,7 +1367,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm43";
@@ -1348,7 +1375,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm44";
@@ -1356,7 +1383,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm45";
@@ -1364,7 +1391,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm46";
@@ -1372,7 +1399,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm47";
@@ -1469,7 +1496,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm58";
@@ -1477,7 +1504,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm59";
@@ -1485,7 +1512,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm60";
@@ -1493,7 +1520,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm61";
@@ -1501,7 +1528,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm62";
@@ -1509,7 +1536,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm63";
@@ -1598,7 +1625,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "vrm6";
@@ -1606,7 +1633,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "vrm7";
@@ -1614,7 +1641,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "vrm12";
@@ -1622,7 +1649,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "vrm13";
@@ -1630,7 +1657,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "vrm14";
@@ -1638,7 +1665,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "vrm15";
@@ -1727,7 +1754,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "vrm2";
@@ -1735,7 +1762,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "vrm3";
@@ -1743,7 +1770,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "vrm8";
@@ -1751,7 +1778,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "vrm9";
@@ -1759,7 +1786,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "vrm10";
@@ -1767,7 +1794,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "vrm11";
@@ -2118,7 +2145,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@10 {
+				led@a {
 					reg = <10>;
 					default-state = "keep";
 					label = "fan0";
@@ -2126,7 +2153,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@11 {
+				led@b {
 					reg = <11>;
 					default-state = "keep";
 					label = "fan1";
@@ -2134,7 +2161,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@12 {
+				led@c {
 					reg = <12>;
 					default-state = "keep";
 					label = "fan2";
@@ -2142,7 +2169,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@13 {
+				led@d {
 					reg = <13>;
 					default-state = "keep";
 					label = "fan3";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
index 0776b72c219..638a2c1c789 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
@@ -109,22 +109,22 @@
 		compatible = "gpio-leds";
 
 		/* BMC Card fault LED at the back */
-		bmc-ingraham0 {
+		led-bmc-ingraham0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
 		};
 
 		/* Enclosure ID LED at the back */
-		rear-enc-id0 {
+		led-rear-enc-id0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
 		};
 
 		/* Enclosure fault LED at the back */
-		rear-enc-fault0 {
+		led-rear-enc-fault0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
 		};
 
 		/* PCIE slot power LED */
-		pcieslot-power {
+		led-pcieslot-power {
 			gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -203,7 +203,7 @@
 	/*E0-E7*/	"","","","","","","","",
 	/*F0-F7*/	"","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","",
 	/*G0-G7*/	"","","","","","","","",
-	/*H0-H7*/	"","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","",
+	/*H0-H7*/	"","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","","",
 	/*I0-I7*/	"","","","","","","bmc-secure-boot","",
 	/*J0-J7*/	"","","","","","","","",
 	/*K0-K7*/	"","","","","","","","",
@@ -211,7 +211,7 @@
 	/*M0-M7*/	"","","","","","","","",
 	/*N0-N7*/	"","","","","","","","",
 	/*O0-O7*/	"","","","usb-power","","","","",
-	/*P0-P7*/	"","","","","pcieslot-power","","","",
+	/*P0-P7*/	"","","","","led-pcieslot-power","","","",
 	/*Q0-Q7*/	"cfam-reset","","regulator-standby-faulted","","","","","",
 	/*R0-R7*/	"bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
 	/*S0-S7*/	"presence-ps0","presence-ps1","presence-ps2","presence-ps3",
@@ -1280,8 +1280,9 @@
 		#gpio-cells = <2>;
 
 		gpio-line-names =
-			"", "", "", "", "", "", "", "",
-			"", "", "", "", "", "", "power-config-full-load", "";
+			"", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES",
+			"", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N",
+			"power-config-full-load", "";
 	};
 
 	pca_pres2: pca9552@61 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts
new file mode 100644
index 00000000000..8d98be3d5f2
--- /dev/null
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts
@@ -0,0 +1,6086 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2024 IBM Corp.
+/dts-v1/;
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/i2c/i2c.h>
+#include "aspeed-g6.dtsi"
+
+/ {
+	model = "IBM SBP1";
+	compatible = "ibm,sbp1-bmc", "aspeed,ast2600";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+		device_type = "memory";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-power {
+			label = "LED_BMC_READY";
+			gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			retain-state-suspended;
+			panic-indicator;
+		};
+
+		led-id-tpm {
+			label = "LED_ID_TPM";
+			gpios = <&smb_pex_vr_ctrl 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-bat {
+			label = "LED_ID_BAT";
+			gpios = <&smb_pex_vr_ctrl 16 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-mgmt-port2 {
+			label = "LED_ID_MGMT_PORT2";
+			gpios = <&smb_pex_vr_ctrl 17 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-mgmt-port1 {
+			label = "LED_ID_MGMT_PORT1";
+			gpios = <&smb_pex_vr_ctrl 18 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic1-port1 {
+			label = "LED_ID_NIC1_PORT1";
+			gpios = <&smb_pex_vr_ctrl 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic1-port2 {
+			label = "LED_ID_NIC1_PORT2";
+			gpios = <&smb_pex_vr_ctrl 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic2-port1 {
+			label = "LED_ID_NIC2_PORT1";
+			gpios = <&smb_pex_vr_ctrl 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic2-port2 {
+			label = "LED_ID_NIC2_PORT2";
+			gpios = <&smb_pex_vr_ctrl 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-m2-ssd2 {
+			label = "LED_ID_M2_SSD2";
+			gpios = <&smb_pex_vr_ctrl 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-m2-ssd1 {
+			label = "LED_ID_M2_SSD1";
+			gpios = <&smb_pex_vr_ctrl 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dwr-frnt-p {
+			label = "LED_ID_DWR_FRNT_P";
+			gpios = <&smb_svc_pex_cpu3_led 37 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_BLUE>;
+
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-pwr-dwr-frnt {
+			label = "LED_PWR_DWR_FRNT";
+			gpios = <&smb_svc_pex_cpu3_led 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-pwr-dwr-back {
+			label = "LED_PWR_DWR_BACK";
+			gpios = <&smb_pex_vr_ctrl 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-id-dwr-back-p {
+			label = "LED_ID_DWR_BACK_P";
+			gpios = <&smb_pex_vr_ctrl 35 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_BLUE>;
+
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-id-cpu0 {
+			label = "LED_ID_CPU0";
+			gpios = <&smb_svc_pex_cpu0_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu1 {
+			label = "LED_ID_CPU1";
+			gpios = <&smb_svc_pex_cpu1_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu2 {
+			label = "LED_ID_CPU2";
+			gpios = <&smb_svc_pex_cpu2_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu3 {
+			label = "LED_ID_CPU3";
+			gpios = <&smb_svc_pex_cpu3_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0e2 {
+			label = "LED_ID_DIMM_C0E2";
+			gpios = <&smb_svc_pex_cpu0_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0e1 {
+			label = "LED_ID_DIMM_C0E1";
+			gpios = <&smb_svc_pex_cpu0_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0f2 {
+			label = "LED_ID_DIMM_C0F2";
+			gpios = <&smb_svc_pex_cpu0_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0f1 {
+			label = "LED_ID_DIMM_C0F1";
+			gpios = <&smb_svc_pex_cpu0_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0g2 {
+			label = "LED_ID_DIMM_C0G2";
+			gpios = <&smb_svc_pex_cpu0_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0g1 {
+			label = "LED_ID_DIMM_C0G1";
+			gpios = <&smb_svc_pex_cpu0_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0h2 {
+			label = "LED_ID_DIMM_C0H2";
+			gpios = <&smb_svc_pex_cpu0_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0h1 {
+			label = "LED_ID_DIMM_C0H1";
+			gpios = <&smb_svc_pex_cpu0_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0a2 {
+			label = "LED_ID_DIMM_C0A2";
+			gpios = <&smb_svc_pex_cpu0_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0a1 {
+			label = "LED_ID_DIMM_C0A1";
+			gpios = <&smb_svc_pex_cpu0_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0b2 {
+			label = "LED_ID_DIMM_C0B2";
+			gpios = <&smb_svc_pex_cpu0_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0b1 {
+			label = "LED_ID_DIMM_C0B1";
+			gpios = <&smb_svc_pex_cpu0_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0c2 {
+			label = "LED_ID_DIMM_C0C2";
+			gpios = <&smb_svc_pex_cpu0_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0c1 {
+			label = "LED_ID_DIMM_C0C1";
+			gpios = <&smb_svc_pex_cpu0_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0d2 {
+			label = "LED_ID_DIMM_C0D2";
+			gpios = <&smb_svc_pex_cpu0_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0d1 {
+			label = "LED_ID_DIMM_C0D1";
+			gpios = <&smb_svc_pex_cpu0_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1e2 {
+			label = "LED_ID_DIMM_C1E2";
+			gpios = <&smb_svc_pex_cpu1_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1e1 {
+			label = "LED_ID_DIMM_C1E1";
+			gpios = <&smb_svc_pex_cpu1_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1f2 {
+			label = "LED_ID_DIMM_C1F2";
+			gpios = <&smb_svc_pex_cpu1_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1f1 {
+			label = "LED_ID_DIMM_C1F1";
+			gpios = <&smb_svc_pex_cpu1_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1g2 {
+			label = "LED_ID_DIMM_C1G2";
+			gpios = <&smb_svc_pex_cpu1_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1g1 {
+			label = "LED_ID_DIMM_C1G1";
+			gpios = <&smb_svc_pex_cpu1_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1h2 {
+			label = "LED_ID_DIMM_C1H2";
+			gpios = <&smb_svc_pex_cpu1_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1h1 {
+			label = "LED_ID_DIMM_C1H1";
+			gpios = <&smb_svc_pex_cpu1_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1a2 {
+			label = "LED_ID_DIMM_C1A2";
+			gpios = <&smb_svc_pex_cpu1_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1a1 {
+			label = "LED_ID_DIMM_C1A1";
+			gpios = <&smb_svc_pex_cpu1_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1b2 {
+			label = "LED_ID_DIMM_C1B2";
+			gpios = <&smb_svc_pex_cpu1_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1b1 {
+			label = "LED_ID_DIMM_C1B1";
+			gpios = <&smb_svc_pex_cpu1_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1c2 {
+			label = "LED_ID_DIMM_C1C2";
+			gpios = <&smb_svc_pex_cpu1_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1c1 {
+			label = "LED_ID_DIMM_C1C1";
+			gpios = <&smb_svc_pex_cpu1_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1d2 {
+			label = "LED_ID_DIMM_C1D2";
+			gpios = <&smb_svc_pex_cpu1_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1d1 {
+			label = "LED_ID_DIMM_C1D1";
+			gpios = <&smb_svc_pex_cpu1_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2e2 {
+			label = "LED_ID_DIMM_C2E2";
+			gpios = <&smb_svc_pex_cpu2_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2e1 {
+			label = "LED_ID_DIMM_C2E1";
+			gpios = <&smb_svc_pex_cpu2_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2f2 {
+			label = "LED_ID_DIMM_C2F2";
+			gpios = <&smb_svc_pex_cpu2_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2f1 {
+			label = "LED_ID_DIMM_C2F1";
+			gpios = <&smb_svc_pex_cpu2_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2g2 {
+			label = "LED_ID_DIMM_C2G2";
+			gpios = <&smb_svc_pex_cpu2_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2g1 {
+			label = "LED_ID_DIMM_C2G1";
+			gpios = <&smb_svc_pex_cpu2_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2h2 {
+			label = "LED_ID_DIMM_C2H2";
+			gpios = <&smb_svc_pex_cpu2_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2h1 {
+			label = "LED_ID_DIMM_C2H1";
+			gpios = <&smb_svc_pex_cpu2_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2a2 {
+			label = "LED_ID_DIMM_C2A2";
+			gpios = <&smb_svc_pex_cpu2_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2a1 {
+			label = "LED_ID_DIMM_C2A1";
+			gpios = <&smb_svc_pex_cpu2_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2b2 {
+			label = "LED_ID_DIMM_C2B2";
+			gpios = <&smb_svc_pex_cpu2_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2b1 {
+			label = "LED_ID_DIMM_C2B1";
+			gpios = <&smb_svc_pex_cpu2_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2c2 {
+			label = "LED_ID_DIMM_C2C2";
+			gpios = <&smb_svc_pex_cpu2_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2c1 {
+			label = "LED_ID_DIMM_C2C1";
+			gpios = <&smb_svc_pex_cpu2_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2d2 {
+			label = "LED_ID_DIMM_C2D2";
+			gpios = <&smb_svc_pex_cpu2_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2d1 {
+			label = "LED_ID_DIMM_C2D1";
+			gpios = <&smb_svc_pex_cpu2_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3e2 {
+			label = "LED_ID_DIMM_C3E2";
+			gpios = <&smb_svc_pex_cpu3_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3e1 {
+			label = "LED_ID_DIMM_C3E1";
+			gpios = <&smb_svc_pex_cpu3_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3f2 {
+			label = "LED_ID_DIMM_C3F2";
+			gpios = <&smb_svc_pex_cpu3_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3f1 {
+			label = "LED_ID_DIMM_C3F1";
+			gpios = <&smb_svc_pex_cpu3_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3g2 {
+			label = "LED_ID_DIMM_C3G2";
+			gpios = <&smb_svc_pex_cpu3_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3g1 {
+			label = "LED_ID_DIMM_C3G1";
+			gpios = <&smb_svc_pex_cpu3_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3h2 {
+			label = "LED_ID_DIMM_C3H2";
+			gpios = <&smb_svc_pex_cpu3_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3h1 {
+			label = "LED_ID_DIMM_C3H1";
+			gpios = <&smb_svc_pex_cpu3_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3a2 {
+			label = "LED_ID_DIMM_C3A2";
+			gpios = <&smb_svc_pex_cpu3_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3a1 {
+			label = "LED_ID_DIMM_C3A1";
+			gpios = <&smb_svc_pex_cpu3_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3b2 {
+			label = "LED_ID_DIMM_C3B2";
+			gpios = <&smb_svc_pex_cpu3_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3b1 {
+			label = "LED_ID_DIMM_C3B1";
+			gpios = <&smb_svc_pex_cpu3_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3c2 {
+			label = "LED_ID_DIMM_C3C2";
+			gpios = <&smb_svc_pex_cpu3_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3c1 {
+			label = "LED_ID_DIMM_C3C1";
+			gpios = <&smb_svc_pex_cpu3_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3d2 {
+			label = "LED_ID_DIMM_C3D2";
+			gpios = <&smb_svc_pex_cpu3_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3d1 {
+			label = "LED_ID_DIMM_C3D1";
+			gpios = <&smb_svc_pex_cpu3_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd01 {
+			label = "LED_ID_RSSD01";
+			gpios = <&smb_svc_pex_rssd01_16 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd02 {
+			label = "LED_ID_RSSD02";
+			gpios = <&smb_svc_pex_rssd01_16 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd03 {
+			label = "LED_ID_RSSD03";
+			gpios = <&smb_svc_pex_rssd01_16 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd04 {
+			label = "LED_ID_RSSD04";
+			gpios = <&smb_svc_pex_rssd01_16 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd05 {
+			label = "LED_ID_RSSD05";
+			gpios = <&smb_svc_pex_rssd01_16 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd06 {
+			label = "LED_ID_RSSD06";
+			gpios = <&smb_svc_pex_rssd01_16 5 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd07 {
+			label = "LED_ID_RSSD07";
+			gpios = <&smb_svc_pex_rssd01_16 6 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd08 {
+			label = "LED_ID_RSSD08";
+			gpios = <&smb_svc_pex_rssd01_16 7 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd09 {
+			label = "LED_ID_RSSD09";
+			gpios = <&smb_svc_pex_rssd01_16 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd10 {
+			label = "LED_ID_RSSD10";
+			gpios = <&smb_svc_pex_rssd01_16 9 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd11 {
+			label = "LED_ID_RSSD11";
+			gpios = <&smb_svc_pex_rssd01_16 10 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd12 {
+			label = "LED_ID_RSSD12";
+			gpios = <&smb_svc_pex_rssd01_16 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd13 {
+			label = "LED_ID_RSSD13";
+			gpios = <&smb_svc_pex_rssd01_16 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd14 {
+			label = "LED_ID_RSSD14";
+			gpios = <&smb_svc_pex_rssd01_16 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd15 {
+			label = "LED_ID_RSSD15";
+			gpios = <&smb_svc_pex_rssd01_16 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd16 {
+			label = "LED_ID_RSSD16";
+			gpios = <&smb_svc_pex_rssd01_16 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd17 {
+			label = "LED_ID_RSSD17";
+			gpios = <&smb_svc_pex_rssd17_32 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd18 {
+			label = "LED_ID_RSSD18";
+			gpios = <&smb_svc_pex_rssd17_32 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd19 {
+			label = "LED_ID_RSSD19";
+			gpios = <&smb_svc_pex_rssd17_32 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd20 {
+			label = "LED_ID_RSSD20";
+			gpios = <&smb_svc_pex_rssd17_32 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd21 {
+			label = "LED_ID_RSSD21";
+			gpios = <&smb_svc_pex_rssd17_32 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd22 {
+			label = "LED_ID_RSSD22";
+			gpios = <&smb_svc_pex_rssd17_32 5 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd23 {
+			label = "LED_ID_RSSD23";
+			gpios = <&smb_svc_pex_rssd17_32 6 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd24 {
+			label = "LED_ID_RSSD24";
+			gpios = <&smb_svc_pex_rssd17_32 7 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd25 {
+			label = "LED_ID_RSSD25";
+			gpios = <&smb_svc_pex_rssd17_32 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd26 {
+			label = "LED_ID_RSSD26";
+			gpios = <&smb_svc_pex_rssd17_32 9 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd27 {
+			label = "LED_ID_RSSD27";
+			gpios = <&smb_svc_pex_rssd17_32 10 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd28 {
+			label = "LED_ID_RSSD28";
+			gpios = <&smb_svc_pex_rssd17_32 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd29 {
+			label = "LED_ID_RSSD29";
+			gpios = <&smb_svc_pex_rssd17_32 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd30 {
+			label = "LED_ID_RSSD30";
+			gpios = <&smb_svc_pex_rssd17_32 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd31 {
+			label = "LED_ID_RSSD31";
+			gpios = <&smb_svc_pex_rssd17_32 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd32 {
+			label = "LED_ID_RSSD32";
+			gpios = <&smb_svc_pex_rssd17_32 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm01 {
+			label = "LED_ID_FAN_ASM01";
+			gpios = <&smb_svc_pex_rssd01_16 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm02 {
+			label = "LED_ID_FAN_ASM02";
+			gpios = <&smb_svc_pex_rssd01_16 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm03 {
+			label = "LED_ID_FAN_ASM03";
+			gpios = <&smb_svc_pex_rssd01_16 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm04 {
+			label = "LED_ID_FAN_ASM04";
+			gpios = <&smb_svc_pex_rssd01_16 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm05 {
+			label = "LED_ID_FAN_ASM05";
+			gpios = <&smb_svc_pex_rssd01_16 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm06 {
+			label = "LED_ID_FAN_ASM06";
+			gpios = <&smb_svc_pex_rssd01_16 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm07 {
+			label = "LED_ID_FAN_ASM07";
+			gpios = <&smb_svc_pex_rssd17_32 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm08 {
+			label = "LED_ID_FAN_ASM08";
+			gpios = <&smb_svc_pex_rssd17_32 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm09 {
+			label = "LED_ID_FAN_ASM09";
+			gpios = <&smb_svc_pex_rssd17_32 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm10 {
+			label = "LED_ID_FAN_ASM10";
+			gpios = <&smb_svc_pex_rssd17_32 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm11 {
+			label = "LED_ID_FAN_ASM11";
+			gpios = <&smb_svc_pex_rssd17_32 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm12 {
+			label = "LED_ID_FAN_ASM12";
+			gpios = <&smb_svc_pex_rssd17_32 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&p12v_vd 0>, <&p5v_aux_vd 0>, <&p5v_bmc_aux_vd 0>, <&p3v3_aux_vd 0>,
+			<&p3v3_bmc_aux_vd 0>, <&p1v8_bmc_aux_vd 0>, <&adc1 4>, <&adc0 2>, <&adc1 0>,
+			<&p2V5_aux_vd 0>, <&p3v3_rtc_vd 0>;
+	};
+
+	p12v_vd: voltage-divider1 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 3>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1127/127 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <15>;
+		full-ohms = <133>;
+	};
+
+	p5v_aux_vd: voltage-divider2 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 5>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1365/365 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <50>;
+		full-ohms = <187>;
+	};
+
+	p5v_bmc_aux_vd: voltage-divider3 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 3>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1365/365 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <50>;
+		full-ohms = <187>;
+	};
+
+	p3v3_aux_vd: voltage-divider4 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 2>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1698/698 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <14>;
+		full-ohms = <34>;
+	};
+
+	p3v3_bmc_aux_vd: voltage-divider5 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 7>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1698/698 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <14>;
+		full-ohms = <34>;
+	};
+
+	p1v8_bmc_aux_vd: voltage-divider6 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 6>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 4000/3000 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <3>;
+		full-ohms = <4>;
+	};
+
+	p2V5_aux_vd: voltage-divider7 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 1>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 2100/1100 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <11>;
+		full-ohms = <21>;
+	};
+
+	p3v3_rtc_vd: voltage-divider8 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 7>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 231000/100000 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <100>;
+		full-ohms = <231>;
+	};
+
+	thermistor0: thermistor-0 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 0>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor1: thermistor-1 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 1>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor2: thermistor-2 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 4>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor3: thermistor-3 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 5>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	p12v: fixedregulator-p12v {
+		compatible = "regulator-fixed";
+		regulator-name = "p12v";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p3v3_bmc_aux: fixedregulator-p3v3-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p3v3_bmc_aux";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p1v8_bmc_aux: fixedregulator-p1v8-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p1v8_bmc_aux";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	p1v2_bmc_aux: fixedregulator-p1v2-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p1v2_bmc_aux";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p12v-a-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_a>;
+	};
+
+	p12v-b-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_b>;
+	};
+
+	p12v-c-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_c>;
+	};
+
+	p12v-d-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_d>;
+	};
+
+	pvccinfaon-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu0>;
+	};
+
+	pvccfa-ehv-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu0>;
+	};
+
+	pvnn-main-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu0>;
+	};
+
+	pvccin-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu0>;
+	};
+
+	pvccfa-ehv-fivra-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu0>;
+	};
+
+	pvccd-hv-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu0>;
+	};
+
+	pvpp-hbm-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu0>;
+	};
+
+	pvccinfaon-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu1>;
+	};
+
+	pvccfa-ehv-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu1>;
+	};
+
+	pvnn-main-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu1>;
+	};
+
+	pvccin-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu1>;
+	};
+
+	pvccfa-ehv-fivra-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu1>;
+	};
+
+	pvccd-hv-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu1>;
+	};
+
+	pvpp-hbm-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu1>;
+	};
+
+	pvccinfaon-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu2>;
+	};
+
+	pvccfa-ehv-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu2>;
+	};
+
+	pvnn-main-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu2>;
+	};
+
+	pvccin-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu2>;
+	};
+
+	pvccfa-ehv-fivra-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu2>;
+	};
+
+	pvccd-hv-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu2>;
+	};
+
+	pvpp-hbm-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu2>;
+	};
+
+	pvccinfaon-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu3>;
+	};
+
+	pvccfa-ehv-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu3>;
+	};
+
+	pvnn-main-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu3>;
+	};
+
+	pvccin-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu3>;
+	};
+
+	pvccfa-ehv-fivra-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu3>;
+	};
+
+	pvccd-hv-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu3>;
+	};
+
+	pvpp-hbm-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu3>;
+	};
+
+	p1v05-pch-aux-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v05_pch_aux>;
+	};
+
+	p1v8-pch-aux-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v8_pch_aux>;
+	};
+
+	p3v3-pch-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p3v3_pch>;
+	};
+
+	p5v-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p5v>;
+	};
+
+	smb-m2-ssb-ssd2 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_smb_m2_ssb_ssd2>;
+	};
+
+	smb-m2-ssb-ssd1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_smb_m2_ssb_ssd1>;
+	};
+
+	ssb-rssd01-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd01>;
+	};
+
+	ssb-rssd01-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd01>;
+	};
+
+	ssb-rssd02-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd02>;
+	};
+
+	ssb-rssd02-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd02>;
+	};
+
+	ssb-rssd03-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd03>;
+	};
+
+	ssb-rssd03-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd03>;
+	};
+
+	ssb-rssd04-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd04>;
+	};
+
+	ssb-rssd04-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd04>;
+	};
+
+	ssb-rssd05-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd05>;
+	};
+
+	ssb-rssd05-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd05>;
+	};
+
+	ssb-rssd06-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd06>;
+	};
+
+	ssb-rssd06-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd06>;
+	};
+
+	ssb-rssd07-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd07>;
+	};
+
+	ssb-rssd07-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd07>;
+	};
+
+	ssb-rssd08-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd08>;
+	};
+
+	ssb-rssd08-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd08>;
+	};
+
+	ssb-rssd09-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd09>;
+	};
+
+	ssb-rssd09-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd09>;
+	};
+
+	ssb-rssd10-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd10>;
+	};
+
+	ssb-rssd10-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd10>;
+	};
+
+	ssb-rssd11-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd11>;
+	};
+
+	ssb-rssd11-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd11>;
+	};
+
+	ssb-rssd12-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd12>;
+	};
+
+	ssb-rssd12-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd12>;
+	};
+
+	ssb-rssd13-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd13>;
+	};
+
+	ssb-rssd13-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd13>;
+	};
+
+	ssb-rssd14-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd14>;
+	};
+
+	ssb-rssd14-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd14>;
+	};
+
+	ssb-rssd15-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd15>;
+	};
+
+	ssb-rssd15-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd15>;
+	};
+
+	ssb-rssd16-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd16>;
+	};
+
+	ssb-rssd16-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd16>;
+	};
+
+	ssb-rssd17-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd17>;
+	};
+
+	ssb-rssd17-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd17>;
+	};
+
+	ssb-rssd18-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd18>;
+	};
+
+	ssb-rssd18-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd18>;
+	};
+
+	ssb-rssd19-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd19>;
+	};
+
+	ssb-rssd19-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd19>;
+	};
+
+	ssb-rssd20-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd20>;
+	};
+
+	ssb-rssd20-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd20>;
+	};
+
+	ssb-rssd21-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd21>;
+	};
+
+	ssb-rssd21-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd21>;
+	};
+
+	ssb-rssd22-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd22>;
+	};
+
+	ssb-rssd22-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd22>;
+	};
+
+	ssb-rssd23-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd23>;
+	};
+
+	ssb-rssd23-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd23>;
+	};
+
+	ssb-rssd24-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd24>;
+	};
+
+	ssb-rssd24-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd24>;
+	};
+
+	ssb-rssd25-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd25>;
+	};
+
+	ssb-rssd25-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd25>;
+	};
+
+	ssb-rssd26-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd26>;
+	};
+
+	ssb-rssd26-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd26>;
+	};
+
+	ssb-rssd27-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd27>;
+	};
+
+	ssb-rssd27-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd27>;
+	};
+
+	ssb-rssd28-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd28>;
+	};
+
+	ssb-rssd28-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd28>;
+	};
+
+	ssb-rssd29-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd29>;
+	};
+
+	ssb-rssd29-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd29>;
+	};
+
+	ssb-rssd30-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd30>;
+	};
+
+	ssb-rssd30-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd30>;
+	};
+
+	ssb-rssd31-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd31>;
+	};
+
+	ssb-rssd31-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd31>;
+	};
+
+	ssb-rssd32-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd32>;
+	};
+
+	ssb-rssd32-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd32>;
+	};
+
+	p3v3-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p3v3_nic>;
+	};
+
+	p1v8-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v8_nic>;
+	};
+
+	p1v2-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v2_nic>;
+	};
+
+	pvcore-nic1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvcore_nic1>;
+	};
+
+	pvcore-nic2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvcore_nic2>;
+	};
+};
+
+&peci0 {
+	status = "okay";
+};
+
+&vuart1 {
+	status = "okay";
+};
+
+&lpc_snoop {
+	status = "okay";
+	snoop-ports = <0x80>, <0x81>;
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+
+	flash@1 {
+		status = "okay";
+		m25p,fast-read;
+		label = "alt-bmc";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_txd1_default
+			&pinctrl_rxd1_default
+			&pinctrl_nrts1_default
+			&pinctrl_ndtr1_default
+			&pinctrl_ndsr1_default
+			&pinctrl_ncts1_default
+			&pinctrl_ndcd1_default
+			&pinctrl_nri1_default>;
+};
+
+&uart5 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&video {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default>;
+};
+
+&mdio2 {
+	status = "okay";
+
+	ethphy2: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(V, 7) GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&mdio3 {
+	status = "okay";
+
+	ethphy3: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&mac2 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy2>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy3>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii4_default>;
+};
+
+&adc0 {
+	status = "okay";
+	vref-supply = <&p1v8_bmc_aux>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_default
+		     &pinctrl_adc1_default
+		     &pinctrl_adc2_default
+		     &pinctrl_adc3_default
+		     &pinctrl_adc4_default
+		     &pinctrl_adc5_default
+		     &pinctrl_adc6_default
+		     &pinctrl_adc7_default>;
+};
+
+&adc1 {
+	status = "okay";
+	vref-supply = <&p1v8_bmc_aux>;
+	aspeed,battery-sensing;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc8_default
+		     &pinctrl_adc9_default
+		     &pinctrl_adc10_default
+		     &pinctrl_adc11_default
+		     &pinctrl_adc12_default
+		     &pinctrl_adc13_default
+		     &pinctrl_adc15_default>;
+};
+
+&kcs3 {
+	status = "okay";
+	aspeed,lpc-io-reg = <0xca2>;
+};
+
+&gpio0 {
+	status = "okay";
+	gpio-line-names =
+	/* A0 - A7 */
+	"", "", "", "", "", "", "", "",
+	/* B0 - B7 */
+	"", "", "FM_ADR_TRIGGER_R_N", "RST_PLTRST_BUF_N", "BMC_TPM_RESET_N", "BMC_TPM_IRQ_N",
+	"PCH_TPM_RESET_N", "PCH_TPM_IRQ_N",
+	/* C0 - C7 */
+	"", "", "", "", "", "", "", "",
+	/* D0 - D7 */
+	"", "", "", "", "", "", "", "",
+	/* E0 - E7 */
+	"", "", "", "", "", "", "", "",
+	/* F0 - F7 */
+	"", "", "", "BMC_MUX_CPU1_RST_INT_N", "BMC_MUX_CPU2_RST_INT_N", "", "", "",
+	/* G0 - G7 */
+	"FM_SSD_CLK_DRVR1_EN", "FM_CK440Q_DEV_EN", "BMC_MAC1_RESET_N", "FM_DB2000_DEV_EN",
+	"FM_CPU_RMCA_LVT3_N", "FM_CPU_CATERR_LVT3_N", "FM_DBP_PRESENT_N", "",
+	/* H0 - H7 */
+	"SMB_SVC_PEX_RSSD17_32_INT", "LED_BMC_RDY", "RST_DBP_N", "", "", "", "", "",
+	/* I0 - I7 */
+	"JTAG_MUX_MODE_SEL", "JTAG_MUX_TRANS_ENBL", "JTAG_MUX_LSP_SEL5", "JTAG_MUX_MSTR_SEL",
+	"JTAG_MUX_LSP_SEL3", "", "JTAG_MUX_ENBL_N", "JTAG_MUX_RST_N",
+	/* J0 - J7 */
+	"", "", "", "", "", "", "", "",
+	/* K0 - K7 */
+	"", "", "", "", "", "", "", "",
+	/* L0 - L7 */
+	"", "", "", "", "RST_RTCRST_N", "RST_SRTCRST_N", "", "",
+	/* M0 - M7 */
+	"BMC_UART1_CTS_N", "BMC_UART1_DCD_N", "BMC_UART1_DSR_N", "BMC_UART1_RI_N",
+	"BMC_UART1_DTR_N", "BMC_UART1_RTS_N", "", "",
+	/* N0 - N7 */
+	"IRQ_BMC_PCH_NMI", "", "FM_PCH_BMC_THERMTRIP_N", "FM_BIOS_POST_CMPLT_N", "RST_PLTRST_N",
+	"FM_FLASH_SEC_OVRD", "FM_SMI_ACTIVE_N", "PWRGD_DBP",
+	/* O0 - O7 */
+	"CATERR_CPU2_EN", "H_LVT1_THERMTRIP_N", "CATERR_CPU3_EN", "SMB_SVC_PEX_CPU0_LED_INT",
+	"H_LVT1_MEMTRIP_N", "", "CATERR_CPU1_EN", "FM_PCH_ADR_COMPLETE_N",
+	/* P0 - P7 */
+	"PWRGD_SYS_PWROK", "PWRGD_PCH_PWROK", "BMC_MUX_CPU3_RST_INT_N", "BMC_MUX_SVC_RSSD_INT",
+	"FM_SLPS4_N", "IRQ_SML0_ALERT_N", "FM_SLPS3_N", "LED_BMC_HB",
+	/* Q0 - Q7 */
+	"", "PEX_BMC_RST", "PEX_VR_CTRL_RST", "PEX_NIC_RST", "PEX_CPU0_LED_RST", "PEX_CPU1_LED_RST",
+	"PEX_CPU2_LED_RST", "PEX_CPU3_LED_RST",
+	/* R0 - R7 */
+	"BMC_MUX_FANSSB_RSSD17_32_RST_INT_N", "BMC_MUX_FANPWM_RSSD01_16_RST_INT_N",
+	"BMC_MUX_SVC_VR_RST_INT_N", "BMC_MUX_NIC_RST_INT_N", "BMC_MUX_SVC_EXP_RST_INT_N",
+	"FM_CPU_ERR2_LVT3_N", "BMC_MUX_CPU0_RST_INT_N", "BMC_MUX_M2_RST_INT_N",
+	/* S0 - S7 */
+	"SMB_SVC_PEX_RSSD01_16_INT", "RST_PCH_RSMRST_R_N", "", "", "BMC_ROT_FPGA_RESET_N",
+	"FM_SSD_CLK_DRVR0_EN", "", "",
+	/* T0 - T7 */
+	"", "", "", "", "", "", "", "",
+	/* U0 - U7 */
+	"", "", "", "", "", "", "", "",
+	/* V0 - V7 */
+	"BMC_PEX_IRQ_INT", "RTC_BATT_TEST", "SMB_PEX_VR_CTRL_INT", "SMB_SVC_PEX_CPU3_LED_INT",
+	"PWRGD_CPUPWRGD", "SMB_SVC_PEX_CPU2_LED_INT", "SMB_SVC_PEX_CPU1_LED_INT",
+	"BMC_MAC0_RESET_N",
+	/* W0 - W7 */
+	"", "", "", "", "", "", "", "",
+	/* X0 - X7 */
+	"", "", "", "", "", "", "", "",
+	/* Y0 - Y7 */
+	"FM_THROTTLE_N", "FM_PASSWORD_CLEAR_N", "H_LVT3_CATERR_DLY_N", "FM_CPU_OL_INT_R_N", "", "",
+	"", "",
+	/* Z0 - Z7 */
+	"FM_CPU_ERR0_LVT3_N", "FM_CPU_ERR1_LVT3_N", "BMC_MUX_VR_PCH_CPU_RST_INT_N",
+	"JTAG_MUX_LSP_SEL1", "", "JTAG_MUX_LSP_SEL4", "JTAG_MUX_LSP_SEL2", "";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio0_unbiased_default>;
+};
+
+&pinctrl {
+	pinctrl_gpio0_unbiased_default: gpio_default {
+		pins = "AB15", "AD14", "R23", "A18", "AD24", "AD15", "AE14", "AC15", "U25", "AA24",
+		       "V24", "W26", "AA23", "V26", "U24", "V25", "AE15", "C15", "F15";
+		bias-disable;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	bmc_mux_nic: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_nic: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&gpio0 ASPEED_GPIO(Q, 3) GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <19 1>, <22 6>, <30 6>, <38 2>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"IRQ_NIC2_OVT_WRNG", "FM_NIC2_ALLSTANDBY_N", "IRQ_NIC2_OVT_SHTDN",
+				"SMB_VR_PVCORE_NIC2_ALERT_N", "FM_NIC2_PERST1_N",
+				"SMB_NIC2_ALERT_N", "FM_NIC2_PERST3_N", "FM_NIC2_PERST2_N",
+				/* GPORT1 */
+				"FM_NIC1_RST_N", "FM_NIC1_PERST0_N", "FM_NIC1_PERST2_N",
+				"FM_NIC1_PERST3_N", "SMB_NIC1_ALERT_N", "FM_NIC1_PERST1_N",
+				"SMB_VR_PVCORE_NIC1_ALERT_N", "IRQ_NIC1_OVT_SHTDN",
+				/* GPORT2 */
+				"SMB_VR_P3V3_NIC_ALERT_N", "FM_NIC2_FLASH_PRSNT",
+				"FM_NIC1_FLASH_PRSNT", "",
+				/* GPORT3 */
+				"FM_NIC2_PERST0_N", "FM_NIC2_RST_N", "", "", "", "", "", "",
+				/* GPORT4 */
+				"FM_NIC1_ALLSTANDBY_N", "IRQ_NIC1_OVT_WRNG", "", "", "", "", "", "",
+				/* GPORT5 */
+				"SMB_VR_P1V8_NIC_ALERT_N", "SMB_VR_P1V2_NIC_ALERT_N", "", "";
+
+				pinctrl-0 = <&U62160_pins>;
+				pinctrl-names = "default";
+				U62160_pins: cfg-pins {
+					pins = "gp03", "gp16", "gp20", "gp50", "gp51";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvcore_nic2: ir38263-pvcore-nic2@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "pvcore_nic2";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvcore_nic1: ir38263-pvcore-nic1@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "pvcore_nic1";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p3v3_nic: ir38263-p3v3-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p3v3_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v2_nic: ir38263-p1v2-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v2_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v8_nic: ir38263-p1v8-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v8_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	i2cmux1: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 7) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_m2_ssb_ssd1: regulator@3a {
+				compatible = "maxim,max5978";
+				reg = <0x3a>;
+				vss1-supply = <&p3v3_aux>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+				leds {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						label = "m2_ssb_ssd1:green:power";
+						default-state = "off";
+					};
+				};
+
+				regulators {
+					sw0_smb_m2_ssb_ssd1: sw0 {
+						shunt-resistor-micro-ohms = <12000>;
+						regulator-over-current-protection;
+						regulator-oc-protection-microamp = <2800000>;
+						regulator-name = "p3v3_m2_ssd1";
+						regulator-enable-ramp-delay = <10000>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_m2_ssb_ssd2: regulator@3a {
+				compatible = "maxim,max5978";
+				reg = <0x3a>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <39 IRQ_TYPE_LEVEL_LOW>;
+				vss1-supply = <&p3v3_aux>;
+				leds {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						label = "m2_ssb_ssd2:green:power";
+						default-state = "off";
+					};
+				};
+
+				regulators {
+					sw0_smb_m2_ssb_ssd2: sw0 {
+						shunt-resistor-micro-ohms = <12000>;
+						regulator-over-current-protection;
+						regulator-oc-protection-microamp = <2800000>;
+						regulator-name = "p3v3_m2_ssd2";
+						regulator-enable-ramp-delay = <10000>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	multi-master;
+	bus-frequency = <1000000>;
+
+	bmc-slave@10 {
+		compatible = "ipmb-dev";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+
+		i2c-protocol;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	i2cmux2: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(Z, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v05_pch_aux: ir38263-p1v05-pch-aux@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v05_pch_aux";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v8_pch_aux: ir38060-p1v8-pch-aux@40 {
+				compatible = "infineon,ir38060";
+				reg = <0x40>;
+
+				regulator-name = "p1v8_pch_aux";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c14 {
+	status = "okay";
+
+	i2cmux13: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 6) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu0_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu0_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU0", "PWRGD_CHC_CPU0",
+				"PWRGD_CHB_CPU0", "PWRGD_CHA_CPU0",
+				"PWRGD_CHE_CPU0", "PWRGD_CHF_CPU0",
+				"PWRGD_CHG_CPU0", "PWRGD_CHH_CPU0",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU0_ALERT_N", "SMB_VR_PVCCINFAON_CPU0_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU0_ALERT_N", "SMB_VR_PVCCD_HV_CPU0_ALERT_N",
+				"SMB_VR_PVCCIN_CPU0_ALERT_N", "SEL_SMB_DIMM_CPU0",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU0_AB_DRAM_G", "PWRGD_LVC3_CPU0_CD_DRAM_G",
+				"PWRGD_LVC3_CPU0_EF_DRAM_G", "PWRGD_LVC3_CPU0_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU0_DISABLE_COD_N", "",
+				"RST_LVC3_CPU0_RESET_N", "PWRGD_LVC3_CPU0_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU0_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU0_PROCHOT_N", "H_LVT3_CPU0_MEMHOT_IN_N",
+				"H_LVT3_CPU0_MEMHOT_OUT_N", "H_LVT3_CPU0_MEMTRIP_OUT_N",
+				"H_LVT3_CPU0_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU0_NMI", "FM_S3M_CPU0_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU0_PKG_ID0", "FM_CPU0_PKG_ID1",
+				"FM_CPU0_PROC_ID0", "FM_CPU0_PROC_ID1";
+
+				pinctrl-0 = <&U62080_pins>;
+				pinctrl-names = "default";
+				U62080_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu0@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu0: vout0 {
+						regulator-name = "pvccinfaon_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu0: vout1 {
+						regulator-name = "pvccfa_ehv_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu0: vout {
+						regulator-name = "pvnn_main_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu0@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu0: vout0 {
+						regulator-name = "pvccin_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu0: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu0: vout {
+						regulator-name = "pvccd_hv_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu0: vout {
+						regulator-name = "pvpp_hbm_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	i2cmux4: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(F, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu1_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu1_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU1", "PWRGD_CHC_CPU1",
+				"PWRGD_CHB_CPU1", "PWRGD_CHA_CPU1",
+				"PWRGD_CHE_CPU1", "PWRGD_CHF_CPU1",
+				"PWRGD_CHG_CPU1", "PWRGD_CHH_CPU1",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU1_ALERT_N", "SMB_VR_PVCCINFAON_CPU1_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU1_ALERT_N", "SMB_VR_PVCCD_HV_CPU1_ALERT_N",
+				"SMB_VR_PVCCIN_CPU1_ALERT_N", "SEL_SMB_DIMM_CPU1",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU1_AB_DRAM_G", "PWRGD_LVC3_CPU1_CD_DRAM_G",
+				"PWRGD_LVC3_CPU1_EF_DRAM_G", "PWRGD_LVC3_CPU1_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU1_DISABLE_COD_N", "",
+				"RST_LVC3_CPU1_RESET_N", "PWRGD_LVC3_CPU1_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU1_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU1_PROCHOT_N", "H_LVT3_CPU1_MEMHOT_IN_N",
+				"H_LVT3_CPU1_MEMHOT_OUT_N", "H_LVT3_CPU1_MEMTRIP_OUT_N",
+				"H_LVT3_CPU1_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU1_NMI", "FM_S3M_CPU1_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU1_PKG_ID0", "FM_CPU1_PKG_ID1",
+				"FM_CPU1_PROC_ID0", "FM_CPU1_PROC_ID1";
+
+				pinctrl-0 = <&U62090_pins>;
+				pinctrl-names = "default";
+				U62090_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu1@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu1: vout0 {
+						regulator-name = "pvccinfaon_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu1: vout1 {
+						regulator-name = "pvccfa_ehv_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu1: vout {
+						regulator-name = "pvnn_main_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu1@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu1: vout0 {
+						regulator-name = "pvccin_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu1: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu1: vout {
+						regulator-name = "pvccd_hv_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu1: vout {
+						regulator-name = "pvpp_hbm_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	i2cmux3: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu2_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu2_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU2", "PWRGD_CHC_CPU2",
+				"PWRGD_CHB_CPU2", "PWRGD_CHA_CPU2",
+				"PWRGD_CHE_CPU2", "PWRGD_CHF_CPU2",
+				"PWRGD_CHG_CPU2", "PWRGD_CHH_CPU2",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU2_ALERT_N", "SMB_VR_PVCCINFAON_CPU2_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU2_ALERT_N", "SMB_VR_PVCCD_HV_CPU2_ALERT_N",
+				"SMB_VR_PVCCIN_CPU2_ALERT_N", "SEL_SMB_DIMM_CPU2",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU2_AB_DRAM_G", "PWRGD_LVC3_CPU2_CD_DRAM_G",
+				"PWRGD_LVC3_CPU2_EF_DRAM_G", "PWRGD_LVC3_CPU2_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU2_DISABLE_COD_N", "",
+				"RST_LVC3_CPU2_RESET_N", "PWRGD_LVC3_CPU2_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU2_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU2_PROCHOT_N", "H_LVT3_CPU2_MEMHOT_IN_N",
+				"H_LVT3_CPU2_MEMHOT_OUT_N", "H_LVT3_CPU2_MEMTRIP_OUT_N",
+				"H_LVT3_CPU2_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU2_NMI", "FM_S3M_CPU2_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU2_PKG_ID0", "FM_CPU2_PKG_ID1",
+				"FM_CPU2_PROC_ID0", "FM_CPU2_PROC_ID1";
+
+				pinctrl-0 = <&U62100_pins>;
+				pinctrl-names = "default";
+				U62100_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu2@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu2: vout0 {
+						regulator-name = "pvccinfaon_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu2: vout1 {
+						regulator-name = "pvccfa_ehv_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu2: vout {
+						regulator-name = "pvnn_main_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu2@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu2: vout0 {
+						regulator-name = "pvccin_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu2: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu2: vout {
+						regulator-name = "pvccd_hv_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu2: vout {
+						regulator-name = "pvpp_hbm_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c12 {
+	status = "okay";
+
+	i2cmux22: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(P, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu3_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu3_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU3", "PWRGD_CHC_CPU3",
+				"PWRGD_CHB_CPU3", "PWRGD_CHA_CPU3",
+				"PWRGD_CHE_CPU3", "PWRGD_CHF_CPU3",
+				"PWRGD_CHG_CPU3", "PWRGD_CHH_CPU3",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU3_ALERT_N", "SMB_VR_PVCCINFAON_CPU3_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU3_ALERT_N", "SMB_VR_PVCCD_HV_CPU3_ALERT_N",
+				"SMB_VR_PVCCIN_CPU3_ALERT_N", "SEL_SMB_DIMM_CPU3",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU3_AB_DRAM_G", "PWRGD_LVC3_CPU3_CD_DRAM_G",
+				"PWRGD_LVC3_CPU3_EF_DRAM_G", "PWRGD_LVC3_CPU3_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU3_DISABLE_COD_N", "",
+				"RST_LVC3_CPU3_RESET_N", "PWRGD_LVC3_CPU3_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU3_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU3_PROCHOT_N", "H_LVT3_CPU3_MEMHOT_IN_N",
+				"H_LVT3_CPU3_MEMHOT_OUT_N", "H_LVT3_CPU3_MEMTRIP_OUT_N",
+				"H_LVT3_CPU3_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU3_NMI", "FM_S3M_CPU3_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU3_PKG_ID0", "FM_CPU3_PKG_ID1",
+				"FM_CPU3_PROC_ID0", "FM_CPU3_PROC_ID1";
+
+				pinctrl-0 = <&U62110_pins>;
+				pinctrl-names = "default";
+				U62110_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu3@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu3: vout0 {
+						regulator-name = "pvccinfaon_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu3: vout1 {
+						regulator-name = "pvccfa_ehv_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu3: vout {
+						regulator-name = "pvnn_main_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu3@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu3: vout0 {
+						regulator-name = "pvccin_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu3: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu3: vout {
+						regulator-name = "pvccd_hv_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu3: vout {
+						regulator-name = "pvpp_hbm_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c15 {
+	status = "okay";
+
+	i2cmux14: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 1) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux15: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 11 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux16: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux17: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux18: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux19: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_rssd17_32: pinctrl@20 {
+				compatible = "cypress,cy8c9560";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&bmc_pex_irq>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&bmc_pex_irq 19 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <48 12>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"RSSD17_SMBRST_N", "RSSD18_SMBRST_N",
+				"RSSD19_SMBRST_N", "RSSD20_SMBRST_N",
+				"RSSD21_SMBRST_N", "RSSD22_SMBRST_N",
+				"RSSD23_SMBRST_N", "RSSD24_SMBRST_N",
+				/* GPORT1 */
+				"RSSD25_SMBRST_N", "RSSD26_SMBRST_N",
+				"RSSD27_SMBRST_N", "RSSD28_SMBRST_N",
+				"RSSD29_SMBRST_N", "RSSD30_SMBRST_N",
+				"RSSD31_SMBRST_N", "RSSD32_SMBRST_N",
+				/* GPORT2 */
+				"RSSD17_PWRDIS", "RSSD18_PWRDIS",
+				"RSSD19_PWRDIS", "RSSD20_PWRDIS",
+				/* GPORT3 */
+				"RSSD21_PWRDIS", "RSSD22_PWRDIS",
+				"RSSD23_PWRDIS", "RSSD24_PWRDIS",
+				"RSSD25_PWRDIS", "RSSD26_PWRDIS",
+				"RSSD27_PWRDIS", "RSSD28_PWRDIS",
+				/* GPORT4 */
+				"RSSD29_PWRDIS", "RSSD30_PWRDIS",
+				"RSSD31_PWRDIS", "RSSD32_PWRDIS",
+				"RSSD17_RESET_N", "RSSD18_RESET_N",
+				"RSSD19_RESET_N", "RSSD20_RESET_N",
+				/* GPORT5 */
+				"RSSD21_RESET_N", "RSSD22_RESET_N",
+				"RSSD23_RESET_N", "RSSD24_RESET_N",
+				"RSSD25_RESET_N", "RSSD26_RESET_N",
+				"RSSD27_RESET_N", "RSSD28_RESET_N",
+				/* GPORT6 */
+				"RSSD29_RESET_N", "RSSD30_RESET_N",
+				"RSSD31_RESET_N", "RSSD32_RESET_N",
+				"", "",
+				"", "",
+				/* GPORT7 */
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux20: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 4 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux21: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+	};
+};
+
+&i2c8 {
+	status = "okay";
+
+	i2cmux5: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 0) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux6: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux7: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux8: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux9: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux10: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_rssd_01_16: pinctrl@20 {
+				compatible = "cypress,cy8c9560";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&bmc_pex_irq>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&bmc_pex_irq 18 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <48 12>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"RSSD01_SMBRST_N", "RSSD02_SMBRST_N",
+				"RSSD03_SMBRST_N", "RSSD04_SMBRST_N",
+				"RSSD05_SMBRST_N", "RSSD06_SMBRST_N",
+				"RSSD07_SMBRST_N", "RSSD08_SMBRST_N",
+				/* GPORT1 */
+				"RSSD09_SMBRST_N", "RSSD10_SMBRST_N",
+				"RSSD11_SMBRST_N", "RSSD12_SMBRST_N",
+				"RSSD13_SMBRST_N", "RSSD14_SMBRST_N",
+				"RSSD15_SMBRST_N", "RSSD16_SMBRST_N",
+				/* GPORT2 */
+				"RSSD01_PWRDIS", "RSSD02_PWRDIS",
+				"RSSD03_PWRDIS", "RSSD04_PWRDIS",
+				/* GPORT3 */
+				"RSSD05_PWRDIS", "RSSD06_PWRDIS",
+				"RSSD07_PWRDIS", "RSSD08_PWRDIS",
+				"RSSD09_PWRDIS", "RSSD10_PWRDIS",
+				"RSSD11_PWRDIS", "RSSD12_PWRDIS",
+				/* GPORT4 */
+				"RSSD13_PWRDIS", "RSSD14_PWRDIS",
+				"RSSD15_PWRDIS", "RSSD16_PWRDIS",
+				"RSSD01_RESET_N", "RSSD02_RESET_N",
+				"RSSD03_RESET_N", "RSSD04_RESET_N",
+				/* GPORT5 */
+				"RSSD05_RESET_N", "RSSD06_RESET_N",
+				"RSSD07_RESET_N", "RSSD08_RESET_N",
+				"RSSD09_RESET_N", "RSSD10_RESET_N",
+				"RSSD11_RESET_N", "RSSD12_RESET_N",
+				/* GPORT6 */
+				"RSSD13_RESET_N", "RSSD14_RESET_N",
+				"RSSD15_RESET_N", "RSSD16_RESET_N",
+				"", "",
+				"", "",
+				/* GPORT7 */
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux11: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux12: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 14 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+	};
+};
+
+&i2c13 {
+	status = "okay";
+
+	i2cmux23: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 4) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_bmc_aux>;
+	};
+};
+
+&i2cmux23 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_pex_vr_ctrl: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 2) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"BCM0_INPUT_DISABLE_N", "SMB_VR_P3V3_AUX_ALERT_N",
+			"SMB_PEX_CPU1_EVENT_INT", "SMB_PEX_CPU2_EVENT_INT",
+			"DPIC0_VOLTAGE_DETECTB_N", "DPIC0_VOLTAGE_DETECTA_N",
+			"DPIC1_VOLTAGE_DETECTA_N", "DPIC1_VOLTAGE_DETECTB_N",
+			/* GPORT1 */
+			"SMB_PEX_NIC_INT", "SMB_VR_P1V05_PCH_AUX_ALERT_N",
+			"SMB_PEX_CPU0_EVENT_INT", "SMB_PEX_CPU3_EVENT_INT",
+			"LED_ID_TPM", "PLUG_DETECT_TPM",
+			"PLUG_DETECT_M2_SSD_CARRIER1", "RST_M2_SSD1_PERST_N",
+			/* GPORT2 */
+			"LED_ID_BAT", "LED_ID_MGMT_PORT2",
+			"LED_ID_MGMT_PORT1", "SMB_VR_P5V_AUX_ALERT_N",
+			/* GPORT3 */
+			"SMB_VR_AUX_SSB_ALERT_N", "BCM1_INPUT_DISABLE_N",
+			"LED_ID_NIC1_PORT1", "LED_ID_NIC1_PORT2",
+			"LED_ID_NIC2_PORT1", "LED_ID_NIC2_PORT2",
+			"RST_M2_SSD2_PERST_N", "PLUG_DETECT_M2_SSD2",
+			/* GPORT4 */
+			"PLUG_DETECT_BAT", "PLUG_DETECT_M2_SSD1",
+			"M2_SSD1_SSB_ALERT_N", "BCM2_INPUT_DISABLE_N",
+			"SMB_VR_P1V8_PCH_AUX_ALERT_N", "BCM3_INPUT_DISABLE_N",
+			"LED_PWR_DWR_BACK", "LED_ID_DWR_BACK_P",
+			/* GPORT5 */
+			"LED_ID_M2_SSD2", "LED_ID_M2_SSD1",
+			"PLUG_DETECT_M2_SSD_CARRIER2", "M2_SSD2_SSB_ALERT_N";
+
+			pinctrl-0 = <&U62120_input &U62120_input_pullup>;
+			pinctrl-names = "default";
+			U62120_input: input-pins {
+				pins = "gp10";
+				function = "gpio";
+				input-enable;
+				bias-disable;
+			};
+			U62120_input_pullup: input-pullup-pins {
+				pins = "gp01", "gp02", "gp03", "gp11", "gp12", "gp13",
+				"gp23", "gp30", "gp40", "gp42", "gp44", "gp53";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		bmc_pex_irq: pinctrl@20 {
+			compatible = "cypress,cy8c9520";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"SMB_MUX_PWM_FANGRP2_RST_INT_N", "SMB_MUX_SSB_FANGRP2_RST_INT_N",
+			"SMB_MUX_PWM_FANGRP1_RST_INT_N", "SMB_MUX_SSB_RSSD01_08_RST_INT_N",
+			"SMB_MUX_RSSD01_08_RST_INT_N", "SMB_MUX_RSSD09_16_RST_INT_N",
+			"SMB_PEX_RSSD01_16_INT", "SMB_MUX_SSB_FANGRP1_RST_INT_N",
+			/* GPORT1 */
+			"SMB_SVC_PEX_FAN_ALERT_INT", "SMB_MUX_SSB_RSSD09_16_RST_INT_N",
+			"SMB_MUX_SSB_RSSD17_24_RST_INT_N", "SMB_MUX_PWM_FANGRP0_RST_INT_N",
+			"SMB_MUX_RSSD17_24_RST_INT_N", "SMB_PEX_RSSD17_32_INT",
+			"SMB_MUX_RSSD25_32_RST_INT_N", "SMB_MUX_SSB_RSSD25_32_RST_INT_N",
+			/* GPORT2 */
+			"SMB_MUX_SSB_FANGRP0_RST_INT_N", "PEX_FAN_ALERT_RST",
+			"PEX_RSSD01_16_RST", "PEX_RSSD17_32_RST";
+			pinctrl-0 = <&U60000_pins>;
+			pinctrl-names = "default";
+			U60000_pins: cfg-pins {
+				pins = "gp06", "gp10", "gp15";
+				function = "gpio";
+				input-enable;
+				bias-disable;
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2cmux24: mux@70 {
+			compatible = "maxim,max7357";
+			reg = <0x70>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdd-supply = <&p3v3_bmc_aux>;
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		eeprom@51 {
+			compatible = "atmel,24c32";
+			reg = <0x51>;
+			pagesize = <32>;
+			vcc-supply = <&p3v3_bmc_aux>;
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2cmux25: mux@70 {
+			compatible = "maxim,max7357";
+			reg = <0x70>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2cmux25 {
+	reset-gpios = <&gpio0 ASPEED_GPIO(R, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+	vdd-supply = <&p3v3_bmc_aux>;
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		p5v_aux: ir38263-p5v-aux@40 {
+			compatible = "infineon,ir38263";
+			reg = <0x40>;
+
+			regulator-name = "p5v_aux";
+			regulator-enable-ramp-delay = <2000>;
+			vin-supply = <&p12v>;
+			vbus-supply = <&p3v3_bmc_aux>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		p3v3_aux: ir38263-p3v3-aux@40 {
+			compatible = "infineon,ir38263";
+			reg = <0x40>;
+
+			vin-supply = <&p12v>;
+			regulator-name = "p3v3_aux";
+			/*
+			 * 2msec for regulator + 18msec for board capacitance
+			 * Note: Every IC has a PTC which slowly charges the bypass
+			 * cap.
+			 */
+			regulator-enable-ramp-delay = <200000>;
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		aux_ssb: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_pex_vr_ctrl>;
+			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+			vss1-supply = <&p5v_aux>;
+			vss2-supply = <&p3v3_aux>;
+			regulators {
+				p5v: sw0 {
+					regulator-name = "p5v";
+					shunt-resistor-micro-ohms = <12000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <100000>;
+				};
+				p3v3_pch: sw1 {
+					regulator-name = "p3v3_pch";
+					shunt-resistor-micro-ohms = <12000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <100000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_a: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_a: vout2 {
+					regulator-name = "bcm0";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_b: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_b: vout2 {
+					regulator-name = "bcm1";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_c: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_c: vout2 {
+					regulator-name = "bcm2";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_d: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_d: vout2 {
+					regulator-name = "bcm3";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux24 {
+
+	reset-gpios = <&gpio0 ASPEED_GPIO(P, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		smb_svc_pex_rssd01_16: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&smb_svc_pex_cpu0_led 17 GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"LED_ID_RSSD01", "LED_ID_RSSD02",
+			"LED_ID_RSSD03", "LED_ID_RSSD04",
+			"LED_ID_RSSD05", "LED_ID_RSSD06",
+			"LED_ID_RSSD07", "LED_ID_RSSD08",
+			/* GPORT1 */
+			"LED_ID_RSSD09", "LED_ID_RSSD10",
+			"LED_ID_RSSD11", "LED_ID_RSSD12",
+			"LED_ID_RSSD13", "LED_ID_RSSD14",
+			"LED_ID_RSSD15", "LED_ID_RSSD16",
+			/* GPORT2 */
+			"RSSD01_PRESENT_N", "RSSD02_PRESENT_N",
+			"RSSD03_PRESENT_N", "RSSD04_PRESENT_N",
+			/* GPORT3 */
+			"RSSD05_PRESENT_N", "RSSD06_PRESENT_N",
+			"RSSD07_PRESENT_N", "RSSD08_PRESENT_N",
+			"RSSD09_PRESENT_N", "RSSD10_PRESENT_N",
+			"RSSD11_PRESENT_N", "RSSD12_PRESENT_N",
+			/* GPORT4 */
+			"RSSD13_PRESENT_N", "RSSD14_PRESENT_N",
+			"RSSD15_PRESENT_N", "RSSD16_PRESENT_N",
+			"LED_ID_FAN_ASM01", "LED_ID_FAN_ASM02",
+			"LED_ID_FAN_ASM03", "LED_ID_FAN_ASM04",
+			/* GPORT5 */
+			"LED_ID_FAN_ASM05", "LED_ID_FAN_ASM06",
+			"PLUG_DETECT_FAN_ASM01", "PLUG_DETECT_FAN_ASM02",
+			"PLUG_DETECT_FAN_ASM03", "PLUG_DETECT_FAN_ASM04",
+			"PLUG_DETECT_FAN_ASM05", "PLUG_DETECT_FAN_ASM06",
+			/* GPORT6 */
+			"SSB_RSSD01_ALERT_N", "SSB_RSSD02_ALERT_N",
+			"SSB_RSSD03_ALERT_N", "SSB_RSSD04_ALERT_N",
+			"SSB_RSSD05_ALERT_N", "SSB_RSSD06_ALERT_N",
+			"SSB_RSSD07_ALERT_N", "SSB_RSSD08_ALERT_N",
+			/* GPORT7 */
+			"SSB_RSSD09_ALERT_N", "SSB_RSSD10_ALERT_N",
+			"SSB_RSSD11_ALERT_N", "SSB_RSSD12_ALERT_N",
+			"SSB_RSSD13_ALERT_N", "SSB_RSSD14_ALERT_N",
+			"SSB_RSSD15_ALERT_N", "SSB_RSSD16_ALERT_N";
+			pinctrl-0 = <&U65200_pins>;
+			pinctrl-names = "default";
+			U65200_pins: cfg-pins {
+				pins =  "gp60", "gp61", "gp62",
+				"gp63", "gp64", "gp65", "gp66",
+				"gp67", "gp70", "gp71", "gp72",
+				"gp73", "gp74", "gp75", "gp76", "gp77";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_rssd17_32: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(H, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&smb_svc_pex_cpu1_led 17 GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"LED_ID_RSSD17", "LED_ID_RSSD18",
+			"LED_ID_RSSD19", "LED_ID_RSSD20",
+			"LED_ID_RSSD21", "LED_ID_RSSD22",
+			"LED_ID_RSSD23", "LED_ID_RSSD24",
+			/* GPORT1 */
+			"LED_ID_RSSD25", "LED_ID_RSSD26",
+			"LED_ID_RSSD27", "LED_ID_RSSD28",
+			"LED_ID_RSSD29", "LED_ID_RSSD30",
+			"LED_ID_RSSD31", "LED_ID_RSSD32",
+			/* GPORT2 */
+			"RSSD17_PRESENT_N", "RSSD18_PRESENT_N",
+			"RSSD19_PRESENT_N", "RSSD20_PRESENT_N",
+			/* GPORT3 */
+			"RSSD21_PRESENT_N", "RSSD22_PRESENT_N",
+			"RSSD23_PRESENT_N", "RSSD24_PRESENT_N",
+			"RSSD25_PRESENT_N", "RSSD26_PRESENT_N",
+			"RSSD27_PRESENT_N", "RSSD28_PRESENT_N",
+			/* GPORT4 */
+			"RSSD29_PRESENT_N", "RSSD30_PRESENT_N",
+			"RSSD31_PRESENT_N", "RSSD32_PRESENT_N",
+			"LED_ID_FAN_ASM07", "LED_ID_FAN_ASM08",
+			"LED_ID_FAN_ASM09", "LED_ID_FAN_ASM10",
+			/* GPORT5 */
+			"LED_ID_FAN_ASM11", "LED_ID_FAN_ASM12",
+			"PLUG_DETECT_FAN_ASM07", "PLUG_DETECT_FAN_ASM08",
+			"PLUG_DETECT_FAN_ASM09", "PLUG_DETECT_FAN_ASM10",
+			"PLUG_DETECT_FAN_ASM11", "PLUG_DETECT_FAN_ASM12",
+			/* GPORT6 */
+			"SSB_RSSD17_ALERT_N", "SSB_RSSD18_ALERT_N",
+			"SSB_RSSD19_ALERT_N", "SSB_RSSD20_ALERT_N",
+			"SSB_RSSD21_ALERT_N", "SSB_RSSD22_ALERT_N",
+			"SSB_RSSD23_ALERT_N", "SSB_RSSD24_ALERT_N",
+			/* GPORT7 */
+			"SSB_RSSD25_ALERT_N", "SSB_RSSD26_ALERT_N",
+			"SSB_RSSD27_ALERT_N", "SSB_RSSD28_ALERT_N",
+			"SSB_RSSD29_ALERT_N", "SSB_RSSD30_ALERT_N",
+			"SSB_RSSD31_ALERT_N", "SSB_RSSD32_ALERT_N";
+			pinctrl-0 = <&U65300_pins>;
+			pinctrl-names = "default";
+			U65300_pins: cfg-pins {
+				pins = "gp60", "gp61", "gp62",
+				"gp63", "gp64", "gp65", "gp66",
+				"gp67", "gp70", "gp71", "gp72",
+				"gp73", "gp74", "gp75", "gp76",
+				"gp77";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu1_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 6) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <18 2>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C1E2", "PLUG_DETECT_DIMM_C1E1",
+			"PLUG_DETECT_DIMM_C1F2", "PLUG_DETECT_DIMM_C1F1",
+			"PLUG_DETECT_DIMM_C1G2", "PLUG_DETECT_DIMM_C1G1",
+			"PLUG_DETECT_DIMM_C1H2", "PLUG_DETECT_DIMM_C1H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C1D1", "PLUG_DETECT_DIMM_C1D2",
+			"PLUG_DETECT_DIMM_C1C1", "PLUG_DETECT_DIMM_C1C2",
+			"PLUG_DETECT_DIMM_C1B1", "PLUG_DETECT_DIMM_C1B2",
+			"PLUG_DETECT_DIMM_C1A1", "PLUG_DETECT_DIMM_C1A2",
+			/* GPORT2 */
+			"PEX_CPU1_EVENT_RST", "SVC_PEX_RSSD17_32_RST",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C1E2", "LED_ID_DIMM_C1E1",
+			"LED_ID_DIMM_C1F2", "LED_ID_DIMM_C1F1",
+			"LED_ID_DIMM_C1G2", "LED_ID_DIMM_C1G1",
+			"LED_ID_DIMM_C1H2", "LED_ID_DIMM_C1H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C1A2", "LED_ID_DIMM_C1A1",
+			"LED_ID_DIMM_C1B2", "LED_ID_DIMM_C1B1",
+			"LED_ID_DIMM_C1C2", "LED_ID_DIMM_C1C1",
+			"LED_ID_DIMM_C1D2", "LED_ID_DIMM_C1D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU1_SKTOCC_N", "LED_ID_CPU1";
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_fan_alert: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&bmc_pex_irq>;
+			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_aux>;
+			reset-gpios = <&bmc_pex_irq 17 GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <24 3>, <51 9>;
+			gpio-line-names =
+			/* GPORT0 */
+			"FAN01_SSB_ALERT_N", "FAN02_SSB_ALERT_N",
+			"FAN03_SSB_ALERT_N", "FAN04_SSB_ALERT_N",
+			"FAN05_SSB_ALERT_N", "FAN06_SSB_ALERT_N",
+			"FAN07_SSB_ALERT_N", "FAN08_SSB_ALERT_N",
+			/* GPORT1 */
+			"FAN09_SSB_ALERT_N", "FAN10_SSB_ALERT_N",
+			"FAN11_SSB_ALERT_N", "FAN12_SSB_ALERT_N",
+			"FAN13_SSB_ALERT_N", "FAN14_SSB_ALERT_N",
+			"FAN15_SSB_ALERT_N", "FAN16_SSB_ALERT_N",
+			/* GPORT2 */
+			"FAN17_SSB_ALERT_N", "FAN18_SSB_ALERT_N",
+			"FAN19_SSB_ALERT_N", "FAN20_SSB_ALERT_N",
+			/* GPORT3 */
+			"FAN21_SSB_ALERT_N", "FAN22_SSB_ALERT_N",
+			"FAN23_SSB_ALERT_N", "FAN24_SSB_ALERT_N",
+			"", "",
+			"", "FAN01_PWM_ALERT_N",
+			/* GPORT4 */
+			"FAN02_PWM_ALERT_N", "FAN03_PWM_ALERT_N",
+			"FAN04_PWM_ALERT_N", "FAN05_PWM_ALERT_N",
+			"FAN06_PWM_ALERT_N", "FAN07_PWM_ALERT_N",
+			"FAN08_PWM_ALERT_N", "FAN09_PWM_ALERT_N",
+			/* GPORT5 */
+			"FAN10_PWM_ALERT_N", "FAN11_PWM_ALERT_N",
+			"FAN12_PWM_ALERT_N", "FAN13_PWM_ALERT_N",
+			"FAN14_PWM_ALERT_N", "FAN15_PWM_ALERT_N",
+			"FAN16_PWM_ALERT_N", "FAN17_PWM_ALERT_N",
+			/* GPORT6 */
+			"FAN18_PWM_ALERT_N", "FAN19_PWM_ALERT_N",
+			"FAN20_PWM_ALERT_N", "FAN21_PWM_ALERT_N",
+			"FAN22_PWM_ALERT_N", "FAN23_PWM_ALERT_N",
+			"FAN24_PWM_ALERT_N", "",
+			/* GPORT7 */
+			"", "",
+			"", "",
+			"", "",
+			"", "";
+			pinctrl-0 = <&U65600_pins>;
+			pinctrl-names = "default";
+			U65600_pins: cfg-pins {
+				pins = "gp00", "gp01", "gp02",
+				"gp03", "gp04", "gp05", "gp06",
+				"gp07", "gp10", "gp11", "gp12",
+				"gp13", "gp14", "gp15", "gp16",
+				"gp17", "gp20", "gp21", "gp22",
+				"gp23", "gp30", "gp31", "gp32",
+				"gp33", "gp37", "gp40", "gp41",
+				"gp42", "gp43", "gp44", "gp45",
+				"gp46", "gp47", "gp50", "gp51",
+				"gp52", "gp53", "gp54", "gp55",
+				"gp56", "gp57", "gp60", "gp61",
+				"gp62", "gp63", "gp64", "gp65",
+				"gp66";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu2_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 5) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <17 3>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C2E2", "PLUG_DETECT_DIMM_C2E1",
+			"PLUG_DETECT_DIMM_C2F2", "PLUG_DETECT_DIMM_C2F1",
+			"PLUG_DETECT_DIMM_C2G2", "PLUG_DETECT_DIMM_C2G1",
+			"PLUG_DETECT_DIMM_C2H2", "PLUG_DETECT_DIMM_C2H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C2D1", "PLUG_DETECT_DIMM_C2D2",
+			"PLUG_DETECT_DIMM_C2C1", "PLUG_DETECT_DIMM_C2C2",
+			"PLUG_DETECT_DIMM_C2B1", "PLUG_DETECT_DIMM_C2B2",
+			"PLUG_DETECT_DIMM_C2A1", "PLUG_DETECT_DIMM_C2A2",
+			/* GPORT2 */
+			"PEX_CPU2_EVENT_RST", "",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C2E2", "LED_ID_DIMM_C2E1",
+			"LED_ID_DIMM_C2F2", "LED_ID_DIMM_C2F1",
+			"LED_ID_DIMM_C2G2", "LED_ID_DIMM_C2G1",
+			"LED_ID_DIMM_C2H2", "LED_ID_DIMM_C2H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C2A2", "LED_ID_DIMM_C2A1",
+			"LED_ID_DIMM_C2B2", "LED_ID_DIMM_C2B1",
+			"LED_ID_DIMM_C2C2", "LED_ID_DIMM_C2C1",
+			"LED_ID_DIMM_C2D2", "LED_ID_DIMM_C2D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU2_SKTOCC_N", "LED_ID_CPU2";
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		smb_svc_pex_cpu3_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 3) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <17 3>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C3E2", "PLUG_DETECT_DIMM_C3E1",
+			"PLUG_DETECT_DIMM_C3F2", "PLUG_DETECT_DIMM_C3F1",
+			"PLUG_DETECT_DIMM_C3G2", "PLUG_DETECT_DIMM_C3G1",
+			"PLUG_DETECT_DIMM_C3H2", "PLUG_DETECT_DIMM_C3H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C3D1", "PLUG_DETECT_DIMM_C3D2",
+			"PLUG_DETECT_DIMM_C3C1", "PLUG_DETECT_DIMM_C3C2",
+			"PLUG_DETECT_DIMM_C3B1", "PLUG_DETECT_DIMM_C3B2",
+			"PLUG_DETECT_DIMM_C3A1", "PLUG_DETECT_DIMM_C3A2",
+			/* GPORT2 */
+			"PEX_CPU3_EVENT_RST", "",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C3E2", "LED_ID_DIMM_C3E1",
+			"LED_ID_DIMM_C3F2", "LED_ID_DIMM_C3F1",
+			"LED_ID_DIMM_C3G2", "LED_ID_DIMM_C3G1",
+			"LED_ID_DIMM_C3H2", "LED_ID_DIMM_C3H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C3A2", "LED_ID_DIMM_C3A1",
+			"LED_ID_DIMM_C3B2", "LED_ID_DIMM_C3B1",
+			"LED_ID_DIMM_C3C2", "LED_ID_DIMM_C3C1",
+			"LED_ID_DIMM_C3D2", "LED_ID_DIMM_C3D1",
+			/* GPORT5 */
+			"LED_PWR_DWR_FRNT", "LED_ID_DWR_FRNT_P",
+			"FM_CPU3_SKTOCC_N", "LED_ID_CPU3";
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu0_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(O, 3) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <18 2>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C0E2", "PLUG_DETECT_DIMM_C0E1",
+			"PLUG_DETECT_DIMM_C0F2", "PLUG_DETECT_DIMM_C0F1",
+			"PLUG_DETECT_DIMM_C0G2", "PLUG_DETECT_DIMM_C0G1",
+			"PLUG_DETECT_DIMM_C0H2", "PLUG_DETECT_DIMM_C0H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C0D1", "PLUG_DETECT_DIMM_C0D2",
+			"PLUG_DETECT_DIMM_C0C1", "PLUG_DETECT_DIMM_C0C2",
+			"PLUG_DETECT_DIMM_C0B1", "PLUG_DETECT_DIMM_C0B2",
+			"PLUG_DETECT_DIMM_C0A1", "PLUG_DETECT_DIMM_C0A2",
+			/* GPORT2 */
+			"PEX_CPU0_EVENT_RST", "SVC_PEX_RSSD01_16_RST",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C0E2", "LED_ID_DIMM_C0E1",
+			"LED_ID_DIMM_C0F2", "LED_ID_DIMM_C0F1",
+			"LED_ID_DIMM_C0G2", "LED_ID_DIMM_C0G1",
+			"LED_ID_DIMM_C0H2", "LED_ID_DIMM_C0H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C0A2", "LED_ID_DIMM_C0A1",
+			"LED_ID_DIMM_C0B2", "LED_ID_DIMM_C0B1",
+			"LED_ID_DIMM_C0C2", "LED_ID_DIMM_C0C1",
+			"LED_ID_DIMM_C0D2", "LED_ID_DIMM_C0D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU0_SKTOCC_N", "LED_ID_CPU0";
+		};
+	};
+};
+
+&i2c9 {
+	status = "okay";
+
+	p1v2_bmc_aux_mon: pmic@60 {
+		compatible = "maxim,max8952";
+		reg = <0x60>;
+		max8952,default-mode = <3>;
+		max8952,dvs-mode-microvolt = <1100000>, <1100000>,
+					     <1100000>, <1100000>;
+		max8952,sync-freq = <0>;
+		max8952,ramp-speed = <0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&i2cmux8 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan10_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan10_ssb: sw0 {
+					regulator-name = "fan10_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan12_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan12_ssb: sw0 {
+					regulator-name = "fan12_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan14_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan14_ssb: sw0 {
+					regulator-name = "fan14_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan16_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan16_ssb: sw0 {
+					regulator-name = "fan16_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan18_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan18_ssb: sw0 {
+					regulator-name = "fan18_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan20_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan20_ssb: sw0 {
+					regulator-name = "fan20_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan22_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan22_ssb: sw0 {
+					regulator-name = "fan22_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan24_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan24_ssb: sw0 {
+					regulator-name = "fan24_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux7 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan17_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan17_ssb: sw0 {
+					regulator-name = "fan17_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan19_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan19_ssb: sw0 {
+					regulator-name = "fan19_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan21_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan21_ssb: sw0 {
+					regulator-name = "fan21_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan23_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan23_ssb: sw0 {
+					regulator-name = "fan23_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan02_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan02_ssb: sw0 {
+					regulator-name = "fan02_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan04_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan04_ssb: sw0 {
+					regulator-name = "fan04_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan06_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan06_ssb: sw0 {
+					regulator-name = "fan06_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan08_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan08_ssb: sw0 {
+					regulator-name = "fan08_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux6 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan01_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan01_ssb: sw0 {
+					regulator-name = "fan01_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan03_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan03_ssb: sw0 {
+					regulator-name = "fan03_supply";
+
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan05_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan05_ssb: sw0 {
+					regulator-name = "fan05_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan07_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan07_ssb: sw0 {
+					regulator-name = "fan07_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan09_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan09_ssb: sw0 {
+					regulator-name = "fan09_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan11_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan11_ssb: sw0 {
+					regulator-name = "fan11_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan13_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan13_ssb: sw0 {
+					regulator-name = "fan13_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan15_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan15_ssb: sw0 {
+					regulator-name = "fan15_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+};
+
+&i2cmux9 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd19: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd19:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd19: sw0 {
+					regulator-name = "rssd19_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd19: sw1 {
+					regulator-name = "rssd19_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd18: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd18:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd18: sw0 {
+					regulator-name = "rssd18_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd18: sw1 {
+					regulator-name = "rssd18_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd17: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd17:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd17: sw0 {
+					regulator-name = "rssd17_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd17: sw1 {
+					regulator-name = "rssd17_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd20: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd20:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd20: sw0 {
+					regulator-name = "rssd20_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd20: sw1 {
+					regulator-name = "rssd20_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd21: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <48 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd21:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd21: sw0 {
+					regulator-name = "rssd21_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd21: sw1 {
+					regulator-name = "rssd21_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd22: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <49 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd22:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd22: sw0 {
+					regulator-name = "rssd22_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd22: sw1 {
+					regulator-name = "rssd22_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd24: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd24:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd24: sw0 {
+					regulator-name = "rssd24_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd24: sw1 {
+					regulator-name = "rssd24_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd23: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd23:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd23: sw0 {
+					regulator-name = "rssd23_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd23: sw1 {
+					regulator-name = "rssd23_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux10 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd25: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <52 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd25:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd25: sw0 {
+					regulator-name = "rssd25_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd25: sw1 {
+					regulator-name = "rssd25_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd26: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <53 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd26:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd26: sw0 {
+					regulator-name = "rssd26_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd26: sw1 {
+					regulator-name = "rssd26_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd27: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd27:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd27: sw0 {
+					regulator-name = "rssd27_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd27: sw1 {
+					regulator-name = "rssd27_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd32: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <59 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd32:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd32: sw0 {
+					regulator-name = "rssd32_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd32: sw1 {
+					regulator-name = "rssd32_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd31: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <58 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd31:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd31: sw0 {
+					regulator-name = "rssd31_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd31: sw1 {
+					regulator-name = "rssd31_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd30: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <57 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd30:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd30: sw0 {
+					regulator-name = "rssd30_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd30: sw1 {
+					regulator-name = "rssd30_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd29: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd29:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd29: sw0 {
+					regulator-name = "rssd29_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd29: sw1 {
+					regulator-name = "rssd29_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd28: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd28:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd28: sw0 {
+					regulator-name = "rssd28_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd28: sw1 {
+					regulator-name = "rssd28_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux18 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd03: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd03:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd03: sw0 {
+					regulator-name = "rssd03_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd03: sw1 {
+					regulator-name = "rssd03_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd02: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd02:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd02: sw0 {
+					regulator-name = "rssd02_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd02: sw1 {
+					regulator-name = "rssd02_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd01: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd01:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd01: sw0 {
+					regulator-name = "rssd01_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd01: sw1 {
+					regulator-name = "rssd01_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd04: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd04:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd04: sw0 {
+					regulator-name = "rssd04_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd04: sw1 {
+					regulator-name = "rssd04_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd05: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <48 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd05:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd05: sw0 {
+					regulator-name = "rssd05_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd05: sw1 {
+					regulator-name = "rssd05_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd08: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd08:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd08: sw0 {
+					regulator-name = "rssd08_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd08: sw1 {
+					regulator-name = "rssd08_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd07: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd07:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd07: sw0 {
+					regulator-name = "rssd07_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd07: sw1 {
+					regulator-name = "rssd07_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd06: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <49 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd06:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd06: sw0 {
+					regulator-name = "rssd06_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd06: sw1 {
+					regulator-name = "rssd06_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux19 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd14: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <57 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd14:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd14: sw0 {
+					regulator-name = "rssd14_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd14: sw1 {
+					regulator-name = "rssd14_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd13: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd13:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd13: sw0 {
+					regulator-name = "rssd13_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd13: sw1 {
+					regulator-name = "rssd13_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd12: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd12:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd12: sw0 {
+					regulator-name = "rssd12_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd12: sw1 {
+					regulator-name = "rssd12_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd11: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd11:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd11: sw0 {
+					regulator-name = "rssd11_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd11: sw1 {
+					regulator-name = "rssd11_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd10: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <53 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd10:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd10: sw0 {
+					regulator-name = "rssd10_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd10: sw1 {
+					regulator-name = "rssd10_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd09: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <52 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd09:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd09: sw0 {
+					regulator-name = "rssd09_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd09: sw1 {
+					regulator-name = "rssd09_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd15: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <58 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd15:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd15: sw0 {
+					regulator-name = "rssd15_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd15: sw1 {
+					regulator-name = "rssd15_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd16: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <59 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd16:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd16: sw0 {
+					regulator-name = "rssd16_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd16: sw1 {
+					regulator-name = "rssd16_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
index f3efecc7eb8..360b9ce3c85 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
@@ -370,17 +370,17 @@
 	/*K0-K7*/	"","","","","","","","",
 	/*L0-L7*/	"","","","","","","","bmc-ready",
 	/*M0-M7*/	"","","","","","","","",
-	/*N0-N7*/	"","","","","","","","",
+	/*N0-N7*/	"fpga-debug-enable","","","","","","","",
 	/*O0-O7*/	"","","","","","","","",
 	/*P0-P7*/	"","","","","","","","bmc-hb",
-	/*Q0-Q7*/	"","","","","","","","",
+	/*Q0-Q7*/	"","","","","","","pch-ready","",
 	/*R0-R7*/	"","","","","","","","",
 	/*S0-S7*/	"","","","","","","rear-enc-fault0","rear-enc-id0",
 	/*T0-T7*/	"","","","","","","","",
 	/*U0-U7*/	"","","","","","","","",
 	/*V0-V7*/	"","rtc-battery-voltage-read-enable","","power-chassis-control","","","","",
 	/*W0-W7*/	"","","","","","","","",
-	/*X0-X7*/	"","power-chassis-good","","","","","","",
+	/*X0-X7*/	"fpga-pgood","power-chassis-good","pch-pgood","","","","","",
 	/*Y0-Y7*/	"","","","","","","","",
 	/*Z0-Z7*/	"","","","","","","","";
 };
@@ -398,6 +398,12 @@
 	clk-phase-mmc-hs200 = <180>, <180>;
 };
 
+&sgpiom0 {
+	status = "okay";
+	ngpios = <128>;
+	bus-frequency = <1000000>;
+};
+
 &ibt {
 	status = "okay";
 };
@@ -464,6 +470,15 @@
 	aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 };
 
+&peci0 {
+	status = "okay";
+};
+
+&lpc_snoop {
+	status = "okay";
+	snoop-ports = <0x80>, <0x81>;
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -666,22 +681,22 @@
 	status = "okay";
 
 	power-supply@58 {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x58>;
 	};
 
 	power-supply@59 {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x59>;
 	};
 
 	power-supply@5a {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x5a>;
 	};
 
 	power-supply@5b {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x5b>;
 	};
 };
@@ -1007,6 +1022,7 @@
 
 &i2c8 {
 	status = "okay";
+	bus-frequency = <400000>;
 
 	i2c-mux@71 {
 		compatible = "nxp,pca9548";
@@ -1468,6 +1484,7 @@
 
 &i2c15 {
 	status = "okay";
+	bus-frequency = <400000>;
 
 	i2c-mux@71 {
 		compatible = "nxp,pca9548";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
index 983853eedae..fd361cf073c 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
@@ -381,7 +381,7 @@
 			#size-cells = <0>;
 			reg = <5>;
 
-			U190_fru@51 {
+			eeprom@51 {
 				compatible = "atmel,24c128";
 				reg = <0x51>;
 				pagesize = <32>;
@@ -460,7 +460,7 @@
 	status = "okay";
 
 	/* MB FRU (U173) @ 0xA2 */
-	mb_fru: mb_fru@51 {
+	mb_fru: eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <32>;
@@ -472,7 +472,7 @@
 		reg = <0x4a>;
 	};
 
-	FP_U4_fru@52 {
+	eeprom@52 {
 		compatible = "atmel,24c02";
 		reg = <0x52>;
 		pagesize = <16>;
@@ -593,7 +593,7 @@
 	status = "okay";
 
 	/* SCM FRU (U19) @ 0xA2 */
-	scm_fru: scm_fru@51 {
+	scm_fru: eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <32>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
index b8f0b08018a..98f3e043770 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
@@ -154,7 +154,7 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <7>;
-					at24@50 {
+					eeprom@50 {
 						compatible = "atmel,24c64";
 						reg = <0x50>;
 						pagesize = <32>;
@@ -196,7 +196,7 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <7>;
-					at24@50 {
+					eeprom@50 {
 						compatible = "atmel,24c64";
 						reg = <0x50>;
 						pagesize = <32>;
@@ -205,7 +205,7 @@
 					};
 				};
 			};
-			at24@50 {
+			eeprom@50 {
 				compatible = "atmel,24c64";
 				reg = <0x50>;
 				pagesize = <32>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
index 1a5b25b2ea2..16815eede71 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
@@ -291,7 +291,7 @@
 	/* SMB_BMC_MGMT_LVC3 */
 	status = "okay";
 
-	at24@50 {
+	eeprom@50 {
 		compatible = "atmel,24c64";
 		reg = <0x50>;
 		pagesize = <32>;
diff --git a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
index 6bf4241fe3b..c78ed064d16 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "bcm2835-rpi.dtsi"
 
-#include <dt-bindings/power/raspberrypi-power.h>
 #include <dt-bindings/reset/raspberrypi,firmware-reset.h>
 
 / {
@@ -101,7 +100,3 @@
 &vchiq {
 	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 };
-
-&xhci {
-	power-domains = <&power RPI_POWER_DOMAIN_USB>;
-};
diff --git a/dts/upstream/src/arm/broadcom/bcm2711.dtsi b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
index e4e42af21ef..c06d9f5e53c 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
@@ -134,7 +134,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -145,7 +145,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -156,7 +156,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -167,7 +167,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -451,8 +451,6 @@
 					  IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 					  IRQ_TYPE_LEVEL_LOW)>;
-		/* This only applies to the ARMv7 stub */
-		arm,cpu-registers-not-fw-configured;
 	};
 
 	cpus: cpus {
@@ -610,6 +608,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pm BCM2835_POWER_DOMAIN_USB>;
 			/* DWC2 and this IP block share the same USB PHY,
 			 * enabling both at the same time results in lockups.
 			 * So keep this node disabled and let the bootloader
@@ -1177,6 +1176,7 @@
 };
 
 &uart0 {
+	arm,primecell-periphid = <0x00341011>;
 	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 };
 
diff --git a/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts b/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
index 53cb0c58f6d..3da2daee0c8 100644
--- a/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
+++ b/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
@@ -124,19 +124,19 @@
 		};
 
 		port@1 {
-			label = "lan1";
+			label = "lan4";
 		};
 
 		port@2 {
-			label = "lan2";
+			label = "lan3";
 		};
 
 		port@3 {
-			label = "lan3";
+			label = "lan2";
 		};
 
 		port@4 {
-			label = "lan4";
+			label = "lan1";
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts b/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
index 6c666dc7ad2..01ec8c03686 100644
--- a/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
+++ b/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
@@ -126,11 +126,11 @@
 
 	ports {
 		port@0 {
-			label = "lan4";
+			label = "wan";
 		};
 
 		port@1 {
-			label = "lan3";
+			label = "lan1";
 		};
 
 		port@2 {
@@ -138,11 +138,11 @@
 		};
 
 		port@3 {
-			label = "lan1";
+			label = "lan3";
 		};
 
 		port@4 {
-			label = "wan";
+			label = "lan4";
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts b/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
index 0bf5106f701..08abfdc63d1 100644
--- a/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
+++ b/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
@@ -59,6 +59,9 @@
 
 &gmac0 {
 	status = "okay";
+
+	nvmem-cells = <&macaddr_board_config_66>;
+	nvmem-cell-names = "mac-address";
 };
 
 &gmac1 {
@@ -102,8 +105,25 @@
 		};
 
 		partition@800000 {
+			compatible = "linux,ubi";
 			label = "ubi";
 			reg = <0x800000 0x7780000>;
+
+			volumes {
+				ubi-volume-board-config {
+					volname = "board-config";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_board_config_66: macaddr@66 {
+							reg = <0x66 0x6>;
+						};
+					};
+				};
+			};
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts b/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
index 975f854f652..08cf1220b65 100644
--- a/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
+++ b/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
@@ -32,7 +32,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 
 	flash: flash@0 {
 		compatible = "m25p80";
diff --git a/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts b/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts
new file mode 100644
index 00000000000..a3616fb7b3a
--- /dev/null
+++ b/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "bcm6846.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Genexis XG6846B Ethernet layer 2/3 router";
+	compatible = "genexis,xg6846b", "brcm,bcm6846", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* Micron D9PTK 256 MB RAM */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		secondary-boot@0 {
+			no-map;
+			reg = <0x00000000 0x00008000>;
+		};
+		pmc3-firmware@8000 {
+			no-map;
+			reg = <0x00008000 0x00100000>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20000>;
+
+		/* Called "canyon rescue button" in the vendor DTB */
+		button-restart {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 41 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+	/* Totally 79 GPIOs are available */
+	ngpios = <15>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&leds {
+	status = "okay";
+	brcm,serial-shift-bits = <16>;
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		function = "ext";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		function = "ext";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@5 {
+		reg = <5>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@6 {
+		reg = <6>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@15 {
+		reg = <15>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@7 {
+		/* Activity 03 */
+		reg = <7>;
+		active-low;
+		function = "lan1";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@8 {
+		/* Activity 04 */
+		reg = <8>;
+		active-low;
+		function = "lan1";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@9 {
+		/* Activity 03 */
+		reg = <9>;
+		active-low;
+		function = "lan2";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@10 {
+		/* Activity 04 */
+		reg = <10>;
+		active-low;
+		function = "lan2";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@11 {
+		/* Activity 03 */
+		reg = <11>;
+		active-low;
+		function = "lan3";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@12 {
+		/* Activity 04 */
+		reg = <12>;
+		active-low;
+		function = "lan3";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@13 {
+		/* Activity 03 */
+		reg = <13>;
+		active-low;
+		function = "lan4";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@14 {
+		/* Activity 04 */
+		reg = <14>;
+		active-low;
+		function = "lan4";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+};
+
+&nand_controller {
+	brcm,wp-not-connected;
+	status = "okay";
+};
+
+&nandcs {
+	nand-on-flash-bbt;
+	brcm,nand-ecc-use-strap;
+
+	/* Winbond W29N02GV, 256MB with 128KB erase blocks */
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		loader@0 {
+			label = "loader";
+			reg = <0x00000000 0x00400000>;
+		};
+		image@400000 {
+			label = "image";
+			reg = <0x00400000 0x0fb00000>;
+		};
+		/* 0x00ff0000-0x00ffffff: bad block list */
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+	};
+	phy21: ethernet-phy@21 {
+		reg = <21>;
+	};
+};
diff --git a/dts/upstream/src/arm/broadcom/bcm6846.dtsi b/dts/upstream/src/arm/broadcom/bcm6846.dtsi
index ee361cb00b7..e0e06af3fe8 100644
--- a/dts/upstream/src/arm/broadcom/bcm6846.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm6846.dtsi
@@ -99,6 +99,91 @@
 		#size-cells = <1>;
 		ranges = <0 0xff800000 0x800000>;
 
+		watchdog@480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x480 0x10>;
+		};
+
+		/* GPIOs 0 .. 31 */
+		gpio0: gpio@500 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x500 0x04>, <0x520 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 32 .. 63 */
+		gpio1: gpio@504 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x504 0x04>, <0x524 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 64 .. 95 */
+		gpio2: gpio@508 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x508 0x04>, <0x528 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 96 .. 127 */
+		gpio3: gpio@50c {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x50c 0x04>, <0x52c 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 128 .. 159 */
+		gpio4: gpio@510 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x510 0x04>, <0x530 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 160 .. 191 */
+		gpio5: gpio@514 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x514 0x04>, <0x534 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 192 .. 223 */
+		gpio6: gpio@518 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x518 0x04>, <0x538 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 224 .. 255 */
+		gpio7: gpio@51c {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x51c 0x04>, <0x53c 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
 		uart0: serial@640 {
 			compatible = "brcm,bcm6345-uart";
 			reg = <0x640 0x1b>;
@@ -108,6 +193,19 @@
 			status = "disabled";
 		};
 
+		rng@b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xb80 0x28>;
+		};
+
+		leds: led-controller@800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm63138-leds";
+			reg = <0x800 0xdc>;
+			status = "disabled";
+		};
+
 		hsspi: spi@1000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -133,5 +231,27 @@
 				reg = <0>;
 			};
 		};
+
+		mdio: mdio@2060 {
+			compatible = "brcm,bcm6846-mdio";
+			reg = <0x02060 0x10>, <0x5a068 0x4>;
+			reg-names = "mdio", "mdio_indir_rw";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pl081_dma: dma-controller@59000 {
+			compatible = "arm,pl081", "arm,primecell";
+			// The magic B105F00D info is missing
+			arm,primecell-periphid = <0x00041081>;
+			reg = <0x59000 0x1000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			clocks = <&periph_clk>;
+			clock-names = "apb_pclk";
+			#dma-cells = <2>;
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm953012hr.dts b/dts/upstream/src/arm/broadcom/bcm953012hr.dts
index b070b69466b..b728cd54715 100644
--- a/dts/upstream/src/arm/broadcom/bcm953012hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm953012hr.dts
@@ -74,7 +74,6 @@
 &spi_nor {
 	status = "okay";
 	spi-max-frequency = <62500000>;
-	m25p,default-addr-width = <3>;
 
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm953012k.dts b/dts/upstream/src/arm/broadcom/bcm953012k.dts
index f1e6bcaa1ed..27c0992f185 100644
--- a/dts/upstream/src/arm/broadcom/bcm953012k.dts
+++ b/dts/upstream/src/arm/broadcom/bcm953012k.dts
@@ -84,7 +84,6 @@
 &spi_nor {
 	status = "okay";
 	spi-max-frequency = <62500000>;
-	m25p,default-addr-width = <3>;
 
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958522er.dts b/dts/upstream/src/arm/broadcom/bcm958522er.dts
index 15f023656df..2f20f86bd31 100644
--- a/dts/upstream/src/arm/broadcom/bcm958522er.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958522er.dts
@@ -135,7 +135,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958525er.dts b/dts/upstream/src/arm/broadcom/bcm958525er.dts
index 9b9c225a1fb..980c03f74a1 100644
--- a/dts/upstream/src/arm/broadcom/bcm958525er.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958525er.dts
@@ -135,7 +135,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958525xmc.dts b/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
index ca931145273..440bb2d617f 100644
--- a/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
@@ -151,7 +151,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958622hr.dts b/dts/upstream/src/arm/broadcom/bcm958622hr.dts
index 9db3c851451..116f3a7c3bc 100644
--- a/dts/upstream/src/arm/broadcom/bcm958622hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958622hr.dts
@@ -139,7 +139,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958623hr.dts b/dts/upstream/src/arm/broadcom/bcm958623hr.dts
index 32786e7c4e1..fc6ab73ecf5 100644
--- a/dts/upstream/src/arm/broadcom/bcm958623hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958623hr.dts
@@ -143,7 +143,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958625hr.dts b/dts/upstream/src/arm/broadcom/bcm958625hr.dts
index 74263d98de7..a9b6aa04d57 100644
--- a/dts/upstream/src/arm/broadcom/bcm958625hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958625hr.dts
@@ -150,7 +150,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958625k.dts b/dts/upstream/src/arm/broadcom/bcm958625k.dts
index 69ebc7a913a..7996116fc92 100644
--- a/dts/upstream/src/arm/broadcom/bcm958625k.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958625k.dts
@@ -154,7 +154,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm988312hr.dts b/dts/upstream/src/arm/broadcom/bcm988312hr.dts
index e96bc3f2d5c..663a3f27b6e 100644
--- a/dts/upstream/src/arm/broadcom/bcm988312hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm988312hr.dts
@@ -139,7 +139,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
index 6b6e77596ff..b108265e9bd 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
@@ -440,7 +440,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
@@ -460,7 +460,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
@@ -480,7 +480,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
index ceaec29770c..c1e1264bcb0 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
@@ -50,8 +50,6 @@
 
 	stmpe1: stmpe811@41 {
 		compatible = "st,stmpe811";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		reg = <0x41>;
 		id = <0>;
 		blocks = <0x5>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
index d37a982e857..97622febc44 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
@@ -151,12 +151,6 @@
 
 &spi0 {
 	status = "okay";
-
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		reg = <0>;
-		spi-max-frequency = <1000000>;
-	};
 };
 
 &usb1 {
diff --git a/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts b/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
index 55ea87870af..86c425b72fa 100644
--- a/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
+++ b/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
@@ -113,8 +113,8 @@
 			  "Headphones", "HPOR",
 			  "MIC2", "Mic Jack";
 		widgets = "Headphone", "Headphones", "Microphone", "Mic Jack";
-		hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>;
-		mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>;
+		hp-det-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
+		mic-det-gpios = <&gpio 96 GPIO_ACTIVE_HIGH>;
 	};
 
 	soc {
diff --git a/dts/upstream/src/arm/mediatek/mt7623.dtsi b/dts/upstream/src/arm/mediatek/mt7623.dtsi
index 814586abc29..fd7a89cc337 100644
--- a/dts/upstream/src/arm/mediatek/mt7623.dtsi
+++ b/dts/upstream/src/arm/mediatek/mt7623.dtsi
@@ -308,7 +308,7 @@
 		clock-names = "spi", "wrap";
 	};
 
-	cir: cir@10013000 {
+	cir: ir-receiver@10013000 {
 		compatible = "mediatek,mt7623-cir";
 		reg = <0 0x10013000 0 0x1000>;
 		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
index 87b6ea97590..1a6a909a504 100644
--- a/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
+++ b/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
@@ -88,8 +88,6 @@
 };
 
 &i2c6 {
-	#address-cells = <1>;
-	#size-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flx6_default>;
 	i2c-analog-filter;
@@ -200,6 +198,52 @@
 	};
 };
 
+&flx7 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+};
+
+&i2c7 {
+	dmas = <0>, <0>;
+	i2c-analog-filter;
+	i2c-digital-filter;
+	i2c-digital-filter-width-ns = <35>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx7_default>;
+	status = "okay";
+
+	power-monitor@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@1 {
+			reg = <0x1>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDD3V3";
+		};
+
+		channel@2 {
+			reg = <0x2>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "DCDC4";
+		};
+
+		channel@3 {
+			reg = <0x3>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDCORE";
+		};
+
+		channel@4 {
+			reg = <0x4>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDIODDR";
+		};
+	};
+};
+
 &i2s {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2s_default>;
@@ -233,6 +277,12 @@
 				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
 				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
 		};
+
+		pinctrl_flx7_default: flx7-default {
+			atmel,pins =
+				<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
 	};
 
 	gpio-keys {
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
index 15239834d88..35a933eec57 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
@@ -197,6 +197,7 @@
 
 &sdmmc0 {
 	bus-width = <4>;
+	no-1-8-v;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdmmc0_default>;
 	status = "okay";
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
index b6684bf67d3..7be21578154 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
@@ -514,6 +514,7 @@
 
 &sdmmc0 {
 	bus-width = <4>;
+	no-1-8-v;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdmmc0_default>;
 	disable-wp;
diff --git a/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts
new file mode 100644
index 00000000000..0f86360fb73
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *  at91-sama7d65_curiosity.dts - Device Tree file for SAMA7D65 Curiosity board
+ *
+ *  Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ *  Author: Romain Sioen <romain.sioen@microchip.com>
+ *
+ */
+/dts-v1/;
+#include "sama7d65-pinfunc.h"
+#include "sama7d65.dtsi"
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+	model = "Microchip SAMA7D65 Curiosity";
+	compatible = "microchip,sama7d65-curiosity", "microchip,sama7d65",
+		     "microchip,sama7d6", "microchip,sama7";
+
+	aliases {
+		serial0 = &uart6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6_default>;
+	status = "okay";
+};
+
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
+&pioa {
+	pinctrl_sdmmc1_default: sdmmc1-default {
+		cmd-data {
+			pinmux = <PIN_PB22__SDMMC1_CMD>,
+				 <PIN_PB24__SDMMC1_DAT0>,
+				 <PIN_PB25__SDMMC1_DAT1>,
+				 <PIN_PB26__SDMMC1_DAT2>,
+				 <PIN_PB27__SDMMC1_DAT3>;
+			slew-rate = <0>;
+			bias-disable;
+		};
+
+		ck-cd-rstn-vddsel {
+			pinmux = <PIN_PB23__SDMMC1_CK>,
+				 <PIN_PB21__SDMMC1_RSTN>,
+				 <PIN_PB30__SDMMC1_1V8SEL>,
+				 <PIN_PB29__SDMMC1_CD>,
+				 <PIN_PB28__SDMMC1_WP>;
+			slew-rate = <0>;
+			bias-disable;
+		};
+	};
+
+	pinctrl_uart6_default: uart6-default {
+		pinmux = <PIN_PD18__FLEXCOM6_IO0>,
+			 <PIN_PD19__FLEXCOM6_IO1>;
+		bias-disable;
+	};
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc1_default>;
+	status = "okay";
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
diff --git a/dts/upstream/src/arm/microchip/sam9x60.dtsi b/dts/upstream/src/arm/microchip/sam9x60.dtsi
index 36944e18a32..b8b2c1ddf3f 100644
--- a/dts/upstream/src/arm/microchip/sam9x60.dtsi
+++ b/dts/upstream/src/arm/microchip/sam9x60.dtsi
@@ -197,6 +197,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -268,6 +270,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -768,6 +772,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -839,6 +845,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -910,6 +918,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -981,6 +991,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
diff --git a/dts/upstream/src/arm/microchip/sam9x7.dtsi b/dts/upstream/src/arm/microchip/sam9x7.dtsi
index beb1f34b38d..b217a908f52 100644
--- a/dts/upstream/src/arm/microchip/sam9x7.dtsi
+++ b/dts/upstream/src/arm/microchip/sam9x7.dtsi
@@ -132,6 +132,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -151,6 +153,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -201,6 +205,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -220,6 +226,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -312,6 +320,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -362,6 +372,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -533,6 +545,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -583,6 +597,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -633,6 +649,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -683,6 +701,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -702,6 +722,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -752,6 +774,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -771,6 +795,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -821,6 +847,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -840,6 +868,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -890,6 +920,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -909,6 +941,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -984,6 +1018,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -1034,6 +1070,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
diff --git a/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h b/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h
new file mode 100644
index 00000000000..c591f333cac
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h
@@ -0,0 +1,947 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#define PINMUX_PIN(no, func, ioset) \
+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
+
+#define PIN_PA0				0
+#define PIN_PA0__GPIO			PINMUX_PIN(PIN_PA0, 0, 0)
+#define PIN_PA0__SDMMC0_CK		PINMUX_PIN(PIN_PA0, 1, 1)
+#define PIN_PA0__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA0, 2, 1)
+#define PIN_PA0__NWER0			PINMUX_PIN(PIN_PA0, 3, 1)
+
+#define PIN_PA1				1
+#define PIN_PA1__GPIO			PINMUX_PIN(PIN_PA1, 0, 0)
+#define PIN_PA1__SDMMC0_CMD		PINMUX_PIN(PIN_PA1, 1, 1)
+#define PIN_PA1__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA1, 2, 1)
+#define PIN_PA1__A21			PINMUX_PIN(PIN_PA1, 3, 1)
+
+#define PIN_PA2				2
+#define PIN_PA2__GPIO			PINMUX_PIN(PIN_PA2, 0, 0)
+#define PIN_PA2__SDMMC0_RSTN		PINMUX_PIN(PIN_PA2, 1, 1)
+#define PIN_PA2__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA2, 2, 1)
+#define PIN_PA2__A22			PINMUX_PIN(PIN_PA2, 3, 1)
+
+#define PIN_PA3				3
+#define PIN_PA3__GPIO			PINMUX_PIN(PIN_PA3, 0, 0)
+#define PIN_PA3__SDMMC0_DAT0		PINMUX_PIN(PIN_PA3, 1, 1)
+#define PIN_PA3__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA3, 2, 1)
+#define PIN_PA3__D0			PINMUX_PIN(PIN_PA3, 3, 1)
+
+#define PIN_PA4				4
+#define PIN_PA4__GPIO			PINMUX_PIN(PIN_PA4, 0, 0)
+#define PIN_PA4__SDMMC0_DAT1		PINMUX_PIN(PIN_PA4, 1, 1)
+#define PIN_PA4__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA4, 2, 1)
+#define PIN_PA4__D1			PINMUX_PIN(PIN_PA4, 3, 1)
+
+#define PIN_PA5				5
+#define PIN_PA5__GPIO			PINMUX_PIN(PIN_PA5, 0, 0)
+#define PIN_PA5__SDMMC0_DAT4		PINMUX_PIN(PIN_PA5, 1, 1)
+#define PIN_PA5__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA5, 2, 3)
+#define PIN_PA5__D4			PINMUX_PIN(PIN_PA5, 3, 1)
+#define PIN_PA5__TCLK4			PINMUX_PIN(PIN_PA5, 6, 3)
+
+#define PIN_PA6				6
+#define PIN_PA6__GPIO			PINMUX_PIN(PIN_PA6, 0, 0)
+#define PIN_PA6__SDMMC0_DAT5		PINMUX_PIN(PIN_PA6, 1, 1)
+#define PIN_PA6__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA6, 2, 3)
+#define PIN_PA6__D5			PINMUX_PIN(PIN_PA6, 3, 1)
+#define PIN_PA6__TIOB4			PINMUX_PIN(PIN_PA6, 6, 3)
+
+#define PIN_PA7				7
+#define PIN_PA7__GPIO			PINMUX_PIN(PIN_PA7, 0, 0)
+#define PIN_PA7__SDMMC0_DAT6		PINMUX_PIN(PIN_PA7, 1, 1)
+#define PIN_PA7__FLEXCOM2_IO2		PINMUX_PIN(PIN_PA7, 2, 3)
+#define PIN_PA7__D6			PINMUX_PIN(PIN_PA7, 3, 1)
+#define PIN_PA7__TIOA4			PINMUX_PIN(PIN_PA7, 6, 3)
+
+#define PIN_PA8				8
+#define PIN_PA8__GPIO			PINMUX_PIN(PIN_PA8, 0, 0)
+#define PIN_PA8__SDMMC0_DAT7		PINMUX_PIN(PIN_PA8, 1, 1)
+#define PIN_PA8__FLEXCOM2_IO3		PINMUX_PIN(PIN_PA8, 2, 3)
+#define PIN_PA8__D7			PINMUX_PIN(PIN_PA8, 3, 1)
+#define PIN_PA8__TIOA5			PINMUX_PIN(PIN_PA8, 6, 3)
+
+#define PIN_PA9				9
+#define PIN_PA9__GPIO			PINMUX_PIN(PIN_PA9, 0, 0)
+#define PIN_PA9__SDMMC0_DAT2		PINMUX_PIN(PIN_PA9, 1, 1)
+#define PIN_PA9__FLEXCOM0_IO2		PINMUX_PIN(PIN_PA9, 2, 1)
+#define PIN_PA9__D2			PINMUX_PIN(PIN_PA9, 3, 1)
+#define PIN_PA9__TIOB5			PINMUX_PIN(PIN_PA9, 6, 3)
+
+#define PIN_PA10			10
+#define PIN_PA10__GPIO			PINMUX_PIN(PIN_PA10, 0, 0)
+#define PIN_PA10__SDMMC0_DAT3		PINMUX_PIN(PIN_PA10, 1, 1)
+#define PIN_PA10__FLEXCOM0_IO3		PINMUX_PIN(PIN_PA10, 2, 1)
+#define PIN_PA10__D3			PINMUX_PIN(PIN_PA10, 3, 1)
+#define PIN_PA10__TCLK5			PINMUX_PIN(PIN_PA10, 6, 3)
+
+#define PIN_PA11			11
+#define PIN_PA11__GPIO			PINMUX_PIN(PIN_PA11, 0, 0)
+#define PIN_PA11__SDMMC0_DS		PINMUX_PIN(PIN_PA11, 1, 1)
+#define PIN_PA11__FLEXCOM0_IO4		PINMUX_PIN(PIN_PA11, 2, 1)
+#define PIN_PA11__NANDRDY		PINMUX_PIN(PIN_PA11, 3, 1)
+#define PIN_PA11__TIOB3			PINMUX_PIN(PIN_PA11, 6, 3)
+
+#define PIN_PA12			12
+#define PIN_PA12__GPIO			PINMUX_PIN(PIN_PA12, 0, 0)
+#define PIN_PA12__FLEXCOM0_IO0		PINMUX_PIN(PIN_PA12, 2, 1)
+#define PIN_PA12__NRD			PINMUX_PIN(PIN_PA12, 3, 1)
+#define PIN_PA12__PCK0			PINMUX_PIN(PIN_PA12, 4, 1)
+#define PIN_PA12__EXT_IRQ0		PINMUX_PIN(PIN_PA12, 5, 1)
+#define PIN_PA12__TIOA3			PINMUX_PIN(PIN_PA12, 6, 3)
+
+#define PIN_PA13			13
+#define PIN_PA13__GPIO			PINMUX_PIN(PIN_PA13, 0, 0)
+#define PIN_PA13__FLEXCOM0_IO1		PINMUX_PIN(PIN_PA13, 2, 1)
+#define PIN_PA13__NCS0			PINMUX_PIN(PIN_PA13, 3, 1)
+#define PIN_PA13__PCK1			PINMUX_PIN(PIN_PA13, 4, 1)
+#define PIN_PA13__TCLK3			PINMUX_PIN(PIN_PA13, 6, 3)
+
+#define PIN_PA14			14
+#define PIN_PA14__GPIO			PINMUX_PIN(PIN_PA14, 0, 0)
+#define PIN_PA14__FLEXCOM4_IO4		PINMUX_PIN(PIN_PA14, 1, 1)
+#define PIN_PA14__SDMMC0_WP		PINMUX_PIN(PIN_PA14, 2, 1)
+#define PIN_PA14__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA14, 3, 4)
+
+#define PIN_PA15			15
+#define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
+#define PIN_PA15__FLEXCOM4_IO3		PINMUX_PIN(PIN_PA15, 1, 1)
+#define PIN_PA15__SDMMC0_1V8SEL		PINMUX_PIN(PIN_PA15, 2, 1)
+#define PIN_PA15__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA15, 3, 4)
+
+#define PIN_PA16			16
+#define PIN_PA16__GPIO			PINMUX_PIN(PIN_PA16, 0, 0)
+#define PIN_PA16__FLEXCOM4_IO2		PINMUX_PIN(PIN_PA16, 1, 1)
+#define PIN_PA16__SDMMCo_CD		PINMUX_PIN(PIN_PA16, 2, 1)
+#define PIN_PA16__PCK2			PINMUX_PIN(PIN_PA16, 4, 1)
+#define PIN_PA16__EXT_IRQ1		PINMUX_PIN(PIN_PA16, 5, 1)
+
+#define PIN_PA17			17
+#define PIN_PA17__GPIO			PINMUX_PIN(PIN_PA17, 0, 0)
+#define PIN_PA17__FLEXCOM4_IO1		PINMUX_PIN(PIN_PA17, 1, 1)
+
+#define PIN_PA18			18
+#define PIN_PA18__GPIO			PINMUX_PIN(PIN_PA18, 0, 0)
+#define PIN_PA18__FLEXCOM4_IO0		PINMUX_PIN(PIN_PA18, 1, 1)
+
+#define PIN_PA19			19
+#define PIN_PA19__GPIO			PINMUX_PIN(PIN_PA19, 0, 0)
+#define PIN_PA19__TK0			PINMUX_PIN(PIN_PA19, 1, 1)
+#define PIN_PA19__FLEXCOM4_IO5		PINMUX_PIN(PIN_PA19, 3, 1)
+#define PIN_PA19__PWML0			PINMUX_PIN(PIN_PA19, 4, 3)
+
+#define PIN_PA20			20
+#define PIN_PA20__GPIO			PINMUX_PIN(PIN_PA20, 0, 0)
+#define PIN_PA20__TD0			PINMUX_PIN(PIN_PA20, 1, 1)
+#define PIN_PA20__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA20, 2, 2)
+#define PIN_PA20__FLEXCOM4_IO6		PINMUX_PIN(PIN_PA20, 3, 1)
+#define PIN_PA20__PWMH0			PINMUX_PIN(PIN_PA20, 4, 3)
+
+#define PIN_PA21			21
+#define PIN_PA21__GPIO			PINMUX_PIN(PIN_PA21, 0, 0)
+#define PIN_PA21__TF0			PINMUX_PIN(PIN_PA21, 1, 1)
+#define PIN_PA21__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA21, 2, 2)
+#define PIN_PA21__PWML1			PINMUX_PIN(PIN_PA21, 4, 3)
+
+#define PIN_PA22			22
+#define PIN_PA22__GPIO			PINMUX_PIN(PIN_PA22, 0, 0)
+#define PIN_PA22__RD0			PINMUX_PIN(PIN_PA22, 1, 1)
+#define PIN_PA22__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA22, 2, 2)
+#define PIN_PA22__PDMC0_DS1		PINMUX_PIN(PIN_PA22, 3, 1)
+#define PIN_PA22__PWMH1			PINMUX_PIN(PIN_PA22, 4, 3)
+
+#define PIN_PA23			23
+#define PIN_PA23__GPIO			PINMUX_PIN(PIN_PA23, 0, 0)
+#define PIN_PA23__RK0			PINMUX_PIN(PIN_PA23, 1, 1)
+#define PIN_PA23__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA23, 2, 2)
+#define PIN_PA23__PDMC0_CLK		PINMUX_PIN(PIN_PA23, 3, 1)
+#define PIN_PA23__PWML2			PINMUX_PIN(PIN_PA23, 4, 3)
+
+#define PIN_PA24			24
+#define PIN_PA24__GPIO			PINMUX_PIN(PIN_PA24, 0, 0)
+#define PIN_PA24__RF0			PINMUX_PIN(PIN_PA24, 1, 1)
+#define PIN_PA24__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA24, 2, 2)
+#define PIN_PA24__PDMC0_DS0		PINMUX_PIN(PIN_PA24, 3, 1)
+#define PIN_PA24__PWMH2			PINMUX_PIN(PIN_PA24, 4, 3)
+
+#define PIN_PA25			25
+#define PIN_PA25__GPIO			PINMUX_PIN(PIN_PA25, 0, 0)
+#define PIN_PA25__G0_TXCTL		PINMUX_PIN(PIN_PA25, 1, 1)
+#define PIN_PA25__FLEXCOM6_IO2		PINMUX_PIN(PIN_PA25, 2, 1)
+
+#define PIN_PA26			26
+#define PIN_PA26__GPIO			PINMUX_PIN(PIN_PA26, 0, 0)
+#define PIN_PA26__G0_TX0		PINMUX_PIN(PIN_PA26, 1, 1)
+#define PIN_PA26__FLEXCOM6_IO3		PINMUX_PIN(PIN_PA26, 2, 1)
+
+#define PIN_PA27			27
+#define PIN_PA27__GPIO			PINMUX_PIN(PIN_PA27, 0, 0)
+#define PIN_PA27__G0_TX1		PINMUX_PIN(PIN_PA27, 1, 1)
+#define PIN_PA27__FLEXCOM6_IO4		PINMUX_PIN(PIN_PA27, 2, 1)
+
+#define PIN_PA28			28
+#define PIN_PA28__GPIO			PINMUX_PIN(PIN_PA28, 0, 0)
+#define PIN_PA28__G0_RXCTL		PINMUX_PIN(PIN_PA28, 1, 1)
+#define PIN_PA28__FLEXCOM6_IO0		PINMUX_PIN(PIN_PA28, 2, 1)
+
+#define PIN_PA29			29
+#define PIN_PA29__GPIO			PINMUX_PIN(PIN_PA29, 0, 0)
+#define PIN_PA29__G0_RX0		PINMUX_PIN(PIN_PA29, 1, 1)
+#define PIN_PA29__FLEXCOM6_IO1		PINMUX_PIN(PIN_PA29, 2, 1)
+
+#define PIN_PA30			30
+#define PIN_PA30__GPIO			PINMUX_PIN(PIN_PA30, 0, 0)
+#define PIN_PA30__G0_RX1		PINMUX_PIN(PIN_PA30, 1, 1)
+#define PIN_PA30__FLEXCOM8_IO0		PINMUX_PIN(PIN_PA30, 2, 1)
+
+#define PIN_PA31			31
+#define PIN_PA31__GPIO			PINMUX_PIN(PIN_PA31, 0, 0)
+#define PIN_PA31__G0_MDC		PINMUX_PIN(PIN_PA31, 1, 1)
+#define PIN_PA31__FLEXCOM8_IO1		PINMUX_PIN(PIN_PA31, 2, 1)
+
+#define PIN_PB0				32
+#define PIN_PB0__GPIO			PINMUX_PIN(PIN_PB0, 0, 0)
+#define PIN_PB0__G0_MDIO		PINMUX_PIN(PIN_PB0, 1, 1)
+#define PIN_PB0__FLEXCOM8_IO3		PINMUX_PIN(PIN_PB0, 2, 2)
+
+#define PIN_PB1				33
+#define PIN_PB1__GPIO			PINMUX_PIN(PIN_PB1, 0, 0)
+#define PIN_PB1__G0_REFCK		PINMUX_PIN(PIN_PB1, 1, 2)
+#define PIN_PB1__FLEXCOM8_IO2		PINMUX_PIN(PIN_PB1, 2, 1)
+
+#define PIN_PB2				34
+#define PIN_PB2__GPIO			PINMUX_PIN(PIN_PB2, 0, 0)
+#define PIN_PB2__G0_RX2			PINMUX_PIN(PIN_PB2, 1, 1)
+#define PIN_PB2__FLEXCOM8_IO4		PINMUX_PIN(PIN_PB2, 2, 1)
+#define PIN_PB2__G0_RXER		PINMUX_PIN(PIN_PB2, 3, 2)
+#define PIN_PB2__RK0			PINMUX_PIN(PIN_PB2, 4, 2)
+
+#define PIN_PB3				35
+#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
+#define PIN_PB3__G0_RXCK		PINMUX_PIN(PIN_PB3, 1, 1)
+#define PIN_PB3__FLEXCOM10_IO2		PINMUX_PIN(PIN_PB3, 2, 2)
+#define PIN_PB3__TK0			PINMUX_PIN(PIN_PB3, 4, 2)
+
+#define PIN_PB4				36
+#define PIN_PB4__GPIO			PINMUX_PIN(PIN_PB4, 0, 0)
+#define PIN_PB4__G0_TX2			PINMUX_PIN(PIN_PB4, 1, 1)
+#define PIN_PB4__FLEXCOM10_IO3		PINMUX_PIN(PIN_PB4, 2, 2)
+#define PIN_PB4__TF0			PINMUX_PIN(PIN_PB4, 4, 2)
+
+#define PIN_PB5				37
+#define PIN_PB5__GPIO			PINMUX_PIN(PIN_PB5, 0, 0)
+#define PIN_PB5__G0_TX3			PINMUX_PIN(PIN_PB5, 1, 1)
+#define PIN_PB5__FLEXCOM10_IO4		PINMUX_PIN(PIN_PB5, 2, 1)
+#define PIN_PB5__TD0			PINMUX_PIN(PIN_PB5, 4, 2)
+
+#define PIN_PB6				38
+#define PIN_PB6__GPIO			PINMUX_PIN(PIN_PB6, 0, 0)
+#define PIN_PB6__G0_RX3			PINMUX_PIN(PIN_PB6, 1, 1)
+#define PIN_PB6__FLEXCOM10_IO0		PINMUX_PIN(PIN_PB6, 2, 2)
+#define PIN_PB6__RD0			PINMUX_PIN(PIN_PB6, 4, 2)
+
+#define PIN_PB7				39
+#define PIN_PB7__GPIO			PINMUX_PIN(PIN_PB7, 0, 0)
+#define PIN_PB7__G0_TSUCOMP		PINMUX_PIN(PIN_PB7, 1, 1)
+#define PIN_PB7__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB7, 2, 2)
+#define PIN_PB7__ADTRG			PINMUX_PIN(PIN_PB7, 3, 1)
+#define PIN_PB7__RF0			PINMUX_PIN(PIN_PB7, 4, 2)
+
+#define PIN_PB8				40
+#define PIN_PB8__GPIO			PINMUX_PIN(PIN_PB8, 0, 0)
+#define PIN_PB8__QSPI0_IO3		PINMUX_PIN(PIN_PB8, 1, 1)
+#define PIN_PB8__PCK3			PINMUX_PIN(PIN_PB8, 2, 1)
+#define PIN_PB8__FLEXCOM2_IO1		PINMUX_PIN(PIN_PB8, 4, 2)
+
+#define PIN_PB9				41
+#define PIN_PB9__GPIO			PINMUX_PIN(PIN_PB9, 0, 0)
+#define PIN_PB9__QSPI0_IO2		PINMUX_PIN(PIN_PB9, 1, 1)
+#define PIN_PB9__FLEXCOM2_IO0		PINMUX_PIN(PIN_PB9, 4, 2)
+#define PIN_PB9__PWMEXTRG0		PINMUX_PIN(PIN_PB9, 5, 1)
+
+#define PIN_PB10			42
+#define PIN_PB10__GPIO			PINMUX_PIN(PIN_PB10, 0, 0)
+#define PIN_PB10__QSPI0_IO1		PINMUX_PIN(PIN_PB10, 1, 1)
+#define PIN_PB10__FLEXCOM2_IO4		PINMUX_PIN(PIN_PB10, 4, 2)
+#define PIN_PB10__PWMEXTRG1		PINMUX_PIN(PIN_PB10, 5, 1)
+
+#define PIN_PB11			43
+#define PIN_PB11__GPIO			PINMUX_PIN(PIN_PB11, 0, 0)
+#define PIN_PB11__QSPI0_IO0		PINMUX_PIN(PIN_PB11, 1, 1)
+#define PIN_PB11__FLEXCOM2_IO5		PINMUX_PIN(PIN_PB11, 4, 2)
+#define PIN_PB11__PWML3			PINMUX_PIN(PIN_PB11, 5, 1)
+#define PIN_PB11__TIOB3			PINMUX_PIN(PIN_PB11, 6, 2)
+
+#define PIN_PB12			44
+#define PIN_PB12__GPIO			PINMUX_PIN(PIN_PB12, 0, 0)
+#define PIN_PB12__QSPI0_CS		PINMUX_PIN(PIN_PB12, 1, 1)
+#define PIN_PB12__FLEXCOM2_IO3		PINMUX_PIN(PIN_PB12, 4, 2)
+#define PIN_PB12__PWMFI1		PINMUX_PIN(PIN_PB12, 6, 1)
+#define PIN_PB12__TIOA3			PINMUX_PIN(PIN_PB12, 6, 2)
+
+#define PIN_PB13			45
+#define PIN_PB13__GPIO			PINMUX_PIN(PIN_PB13, 0, 0)
+#define PIN_PB13__QSPI0_SCK		PINMUX_PIN(PIN_PB13, 1, 1)
+#define PIN_PB13__FLEXCOM2_IO2		PINMUX_PIN(PIN_PB13, 4, 2)
+#define PIN_PB13__PWMFI0		PINMUX_PIN(PIN_PB13, 5, 1)
+#define PIN_PB13__TCLK3			PINMUX_PIN(PIN_PB13, 6, 2)
+
+#define PIN_PB14			46
+#define PIN_PB14__GPIO			PINMUX_PIN(PIN_PB14, 0, 0)
+#define PIN_PB14__QSPI0_SCKN		PINMUX_PIN(PIN_PB14, 1, 1)
+#define PIN_PB14__QSPI1_SCK		PINMUX_PIN(PIN_PB14, 2, 1)
+#define PIN_PB14__I2SMCC0_CK		PINMUX_PIN(PIN_PB14, 3, 3)
+#define PIN_PB14__FLEXCOM10_IO5		PINMUX_PIN(PIN_PB14, 4, 1)
+#define PIN_PB14__PWMH3			PINMUX_PIN(PIN_PB14, 5, 1)
+#define PIN_PB14__FLEXCOM2_IO1		PINMUX_PIN(PIN_PB14, 7, 4)
+
+#define PIN_PB15			47
+#define PIN_PB15__GPIO			PINMUX_PIN(PIN_PB15, 0, 0)
+#define PIN_PB15__QSPI0_IO4		PINMUX_PIN(PIN_PB15, 1, 1)
+#define PIN_PB15__QSPI1_IO0		PINMUX_PIN(PIN_PB15, 2, 1)
+#define PIN_PB15__I2SMCC0_WS		PINMUX_PIN(PIN_PB15, 3, 3)
+#define PIN_PB15__FLEXCOM10_IO6		PINMUX_PIN(PIN_PB15, 4, 1)
+#define PIN_PB15__PWML0			PINMUX_PIN(PIN_PB15, 5, 1)
+#define PIN_PB15__TCLK4			PINMUX_PIN(PIN_PB15, 6, 2)
+#define PIN_PB15__FLEXCOM2_IO0		PINMUX_PIN(PIN_PB15, 7, 4)
+
+#define PIN_PB16			48
+#define PIN_PB16__GPIO			PINMUX_PIN(PIN_PB16, 0, 0)
+#define PIN_PB16__QSPI0_IO5		PINMUX_PIN(PIN_PB16, 1, 1)
+#define PIN_PB16__QSPI1_IO1		PINMUX_PIN(PIN_PB16, 2, 1)
+#define PIN_PB16__I2SMCC0_DIN0		PINMUX_PIN(PIN_PB16, 3, 3)
+#define PIN_PB16__FLEXCOM10_IO4		PINMUX_PIN(PIN_PB16, 4, 1)
+#define PIN_PB16__PWMH0			PINMUX_PIN(PIN_PB16, 5, 1)
+#define PIN_PB16__TIOB4			PINMUX_PIN(PIN_PB16, 6, 2)
+
+#define PIN_PB17			49
+#define PIN_PB17__GPIO			PINMUX_PIN(PIN_PB17, 0, 0)
+#define PIN_PB17__QSPI0_IO6		PINMUX_PIN(PIN_PB17, 1, 1)
+#define PIN_PB17__QSPI1_IO2		PINMUX_PIN(PIN_PB17, 2, 1)
+#define PIN_PB17__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PB17, 3, 3)
+#define PIN_PB17__FLEXCOM10_IO3		PINMUX_PIN(PIN_PB17, 4, 1)
+#define PIN_PB17__PWML1			PINMUX_PIN(PIN_PB17, 5, 1)
+#define PIN_PB17__TIOA4			PINMUX_PIN(PIN_PB17, 6, 2)
+
+#define PIN_PB18			50
+#define PIN_PB18__GPIO			PINMUX_PIN(PIN_PB18, 0, 0)
+#define PIN_PB18__QSPI0_IO7		PINMUX_PIN(PIN_PB18, 1, 1)
+#define PIN_PB18__QSPI1_IO3		PINMUX_PIN(PIN_PB18, 2, 1)
+#define PIN_PB18__I2SMCC0_MCK		PINMUX_PIN(PIN_PB18, 3, 3)
+#define PIN_PB18__FLEXCOM10_IO2		PINMUX_PIN(PIN_PB18, 4, 1)
+#define PIN_PB18__PWMH1			PINMUX_PIN(PIN_PB18, 5, 1)
+#define PIN_PB18__TIOA5			PINMUX_PIN(PIN_PB18, 6, 2)
+
+#define PIN_PB19			51
+#define PIN_PB19__GPIO			PINMUX_PIN(PIN_PB19, 0, 0)
+#define PIN_PB19__QSPI0_DQS		PINMUX_PIN(PIN_PB19, 1, 1)
+#define PIN_PB19__EXT_IRQ1		PINMUX_PIN(PIN_PB19, 2, 2)
+#define PIN_PB19__PCK4			PINMUX_PIN(PIN_PB19, 3, 1)
+#define PIN_PB19__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB19, 4, 1)
+#define PIN_PB19__PWML2			PINMUX_PIN(PIN_PB19, 5, 1)
+#define PIN_PB19__TIOB5			PINMUX_PIN(PIN_PB19, 6, 2)
+
+#define PIN_PB20			52
+#define PIN_PB20__GPIO			PINMUX_PIN(PIN_PB20, 0, 0)
+#define PIN_PB20__QSPI0_INT		PINMUX_PIN(PIN_PB20, 1, 1)
+#define PIN_PB20__QSPI1_CS		PINMUX_PIN(PIN_PB20, 2, 1)
+#define PIN_PB20__FLEXCOM10_IO0		PINMUX_PIN(PIN_PB20, 4, 1)
+#define PIN_PB20__PWMH2			PINMUX_PIN(PIN_PB20, 5, 1)
+#define PIN_PB20__TCLK5			PINMUX_PIN(PIN_PB20, 6, 2)
+
+#define PIN_PB21			53
+#define PIN_PB21__GPIO			PINMUX_PIN(PIN_PB21, 0, 0)
+#define PIN_PB21__SDMMC1_RSTN		PINMUX_PIN(PIN_PB21, 1, 1)
+#define PIN_PB21__FLEXCOM6_IO4		PINMUX_PIN(PIN_PB21, 2, 2)
+#define PIN_PB21__TIOB2			PINMUX_PIN(PIN_PB21, 3, 2)
+#define PIN_PB21__ADTRG			PINMUX_PIN(PIN_PB21, 4, 2)
+#define PIN_PB21__EXT_IRQ0		PINMUX_PIN(PIN_PB21, 5, 2)
+
+#define PIN_PB22			54
+#define PIN_PB22__GPIO			PINMUX_PIN(PIN_PB22, 0, 0)
+#define PIN_PB22__SDMMC1_CMD		PINMUX_PIN(PIN_PB22, 1, 1)
+#define PIN_PB22__FLEXCOM6_IO3		PINMUX_PIN(PIN_PB22, 2, 2)
+#define PIN_PB22__TCLK2			PINMUX_PIN(PIN_PB22, 3, 2)
+
+#define PIN_PB23			55
+#define PIN_PB23__GPIO			PINMUX_PIN(PIN_PB23, 0, 0)
+#define PIN_PB23__SDMMC1_CK		PINMUX_PIN(PIN_PB23, 1, 1)
+#define PIN_PB23__FLEXCOM6_IO2		PINMUX_PIN(PIN_PB23, 2, 2)
+#define PIN_PB23__TIOA2			PINMUX_PIN(PIN_PB23, 3, 2)
+
+#define PIN_PB24			56
+#define PIN_PB24__GPIO			PINMUX_PIN(PIN_PB24, 0, 0)
+#define PIN_PB24__SDMMC1_DAT0		PINMUX_PIN(PIN_PB24, 1, 1)
+#define PIN_PB24__FLEXCOM6_IO0		PINMUX_PIN(PIN_PB24, 2, 2)
+
+#define PIN_PB25			57
+#define PIN_PB25__GPIO			PINMUX_PIN(PIN_PB25, 0, 0)
+#define PIN_PB25__SDMMC1_DAT1		PINMUX_PIN(PIN_PB25, 1, 1)
+#define PIN_PB25__FLEXCOM6_IO1		PINMUX_PIN(PIN_PB25, 2, 2)
+#define PIN_PB25__TIOB2			PINMUX_PIN(PIN_PB25, 3, 1)
+
+#define PIN_PB26			58
+#define PIN_PB26__GPIO			PINMUX_PIN(PIN_PB26, 0, 0)
+#define PIN_PB26__SDMMC1_DAT2		PINMUX_PIN(PIN_PB26, 1, 1)
+#define PIN_PB26__FLEXCOM8_IO0		PINMUX_PIN(PIN_PB26, 2, 3)
+#define PIN_PB26__TCLK2			PINMUX_PIN(PIN_PB26, 3, 1)
+
+#define PIN_PB27			59
+#define PIN_PB27__GPIO			PINMUX_PIN(PIN_PB27, 0, 0)
+#define PIN_PB27__SDMMC1_DAT3		PINMUX_PIN(PIN_PB27, 1, 1)
+#define PIN_PB27__FLEXCOM8_IO1		PINMUX_PIN(PIN_PB27, 2, 3)
+#define PIN_PB27__TIOA2			PINMUX_PIN(PIN_PB27, 3, 1)
+
+#define PIN_PB28			60
+#define PIN_PB28__GPIO			PINMUX_PIN(PIN_PB28, 0, 0)
+#define PIN_PB28__SDMMC1_WP		PINMUX_PIN(PIN_PB28, 1, 1)
+#define PIN_PB28__FLEXCOM1_IO0		PINMUX_PIN(PIN_PB28, 3, 3)
+#define PIN_PB28__D15			PINMUX_PIN(PIN_PB28, 5, 1)
+
+#define PIN_PB29			61
+#define PIN_PB29__GPIO			PINMUX_PIN(PIN_PB29, 0, 0)
+#define PIN_PB29__SDMMC1_CD		PINMUX_PIN(PIN_PB29, 1, 1)
+#define PIN_PB29__I2SMCC0_MCK		PINMUX_PIN(PIN_PB29, 2, 1)
+#define PIN_PB29__FLEXCOM1_IO1		PINMUX_PIN(PIN_PB29, 3, 3)
+#define PIN_PB29__D14			PINMUX_PIN(PIN_PB29, 5, 2)
+
+#define PIN_PB30			62
+#define PIN_PB30__GPIO			PINMUX_PIN(PIN_PB30, 0, 0)
+#define PIN_PB30__SDMMC1_1V8SEL		PINMUX_PIN(PIN_PB30, 1, 1)
+#define PIN_PB30__I2SMCC1_MCK		PINMUX_PIN(PIN_PB30, 2, 2)
+#define PIN_PB30__FLEXCOM1_IO2		PINMUX_PIN(PIN_PB30, 3, 3)
+#define PIN_PB30__TIOA1			PINMUX_PIN(PIN_PB30, 4, 1)
+#define PIN_PB30__NCS1			PINMUX_PIN(PIN_PB30, 5, 1)
+
+#define PIN_PB31			63
+#define PIN_PB31__GPIO			PINMUX_PIN(PIN_PB31, 0, 0)
+#define PIN_PB31__PCK7			PINMUX_PIN(PIN_PB31, 1, 2)
+#define PIN_PB31__I2SMCC1_DIN1		PINMUX_PIN(PIN_PB31, 2, 1)
+#define PIN_PB31__FLEXCOM1_IO3		PINMUX_PIN(PIN_PB31, 3, 3)
+#define PIN_PB31__TCLK1			PINMUX_PIN(PIN_PB31, 4, 1)
+#define PIN_PB31__NWE			PINMUX_PIN(PIN_PB31, 5, 2)
+
+#define PIN_PC0				64
+#define PIN_PC0__GPIO			PINMUX_PIN(PIN_PC0, 0, 0)
+#define PIN_PC0__PCK6			PINMUX_PIN(PIN_PC0, 1, 2)
+#define PIN_PC0__I2SMCC1_DIN2		PINMUX_PIN(PIN_PC0, 2, 1)
+#define PIN_PC0__FLEXCOM9_IO4		PINMUX_PIN(PIN_PC0, 3, 2)
+#define PIN_PC0__TIOB1			PINMUX_PIN(PIN_PC0, 4, 1)
+#define PIN_PC0__NWR1			PINMUX_PIN(PIN_PC0, 5, 1)
+
+#define PIN_PC1				65
+#define PIN_PC1__GPIO			PINMUX_PIN(PIN_PC1, 0, 0)
+#define PIN_PC1__PCK5			PINMUX_PIN(PIN_PC1, 1, 1)
+#define PIN_PC1__FLEXCOM9_IO2		PINMUX_PIN(PIN_PC1, 3, 2)
+#define PIN_PC1__SMCK			PINMUX_PIN(PIN_PC1, 5, 1)
+
+#define PIN_PC2				66
+#define PIN_PC2__GPIO			PINMUX_PIN(PIN_PC2, 0, 0)
+#define PIN_PC2__EXT_IRQ0		PINMUX_PIN(PIN_PC2, 1, 3)
+#define PIN_PC2__FLEXCOM9_IO3		PINMUX_PIN(PIN_PC2, 3, 2)
+#define PIN_PC2__A11			PINMUX_PIN(PIN_PC2, 5, 1)
+
+#define PIN_PC3				67
+#define PIN_PC3__GPIO			PINMUX_PIN(PIN_PC3, 0, 0)
+#define PIN_PC3__SPDIF_RX		PINMUX_PIN(PIN_PC3, 1, 2)
+#define PIN_PC3__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC3, 3, 2)
+#define PIN_PC3__FLEXCOM0_IO4		PINMUX_PIN(PIN_PC3, 4, 2)
+#define PIN_PC3__A10			PINMUX_PIN(PIN_PC3, 5, 1)
+
+#define PIN_PC4				68
+#define PIN_PC4__GPIO			PINMUX_PIN(PIN_PC4, 0, 0)
+#define PIN_PC4__SPDIF_TX		PINMUX_PIN(PIN_PC4, 1, 2)
+#define PIN_PC4__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC4, 3, 2)
+#define PIN_PC4__FLEXCOM0_IO3		PINMUX_PIN(PIN_PC4, 4, 2)
+#define PIN_PC4__D0			PINMUX_PIN(PIN_PC4, 5, 2)
+
+#define PIN_PC5				69
+#define PIN_PC5__GPIO			PINMUX_PIN(PIN_PC5, 0, 0)
+#define PIN_PC5__I3CC_SDASPUE		PINMUX_PIN(PIN_PC5, 1, 1)
+#define PIN_PC5__I2SMCC1_DIN3		PINMUX_PIN(PIN_PC5, 2, 1)
+#define PIN_PC5__FLEXCOM0_IO2		PINMUX_PIN(PIN_PC5, 4, 2)
+#define PIN_PC5__D1			PINMUX_PIN(PIN_PC5, 5, 2)
+
+#define PIN_PC6				70
+#define PIN_PC6__GPIO			PINMUX_PIN(PIN_PC6, 0, 0)
+#define PIN_PC6__I3CC_SCL		PINMUX_PIN(PIN_PC6, 1, 1)
+#define PIN_PC6__FLEXCOM0_IO1		PINMUX_PIN(PIN_PC6, 4, 2)
+#define PIN_PC6__D4			PINMUX_PIN(PIN_PC6, 5, 2)
+
+#define PIN_PC7				71
+#define PIN_PC7__GPIO			PINMUX_PIN(PIN_PC7, 0, 0)
+#define PIN_PC7__I3CC_SDA		PINMUX_PIN(PIN_PC7, 1, 1)
+#define PIN_PC7__FLEXCOM0_IO0		PINMUX_PIN(PIN_PC7, 4, 2)
+#define PIN_PC7__D5			PINMUX_PIN(PIN_PC7, 5, 2)
+
+#define PIN_PC8				72
+#define PIN_PC8__GPIO			PINMUX_PIN(PIN_PC8, 0, 0)
+#define PIN_PC8__I2SMCC0_DIN1		PINMUX_PIN(PIN_PC8, 1, 1)
+#define PIN_PC8__PDMC0_DS1		PINMUX_PIN(PIN_PC8, 2, 2)
+#define PIN_PC8__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PC8, 3, 1)
+#define PIN_PC8__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC8, 4, 1)
+#define PIN_PC8__D6			PINMUX_PIN(PIN_PC8, 5, 2)
+
+#define PIN_PC9				73
+#define PIN_PC9__GPIO			PINMUX_PIN(PIN_PC9, 0, 0)
+#define PIN_PC9__I2SMCC0_DIN2		PINMUX_PIN(PIN_PC9, 1, 1)
+#define PIN_PC9__PDMC0_CLK		PINMUX_PIN(PIN_PC9, 2, 2)
+#define PIN_PC9__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PC9, 3, 1)
+#define PIN_PC9__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC9, 4, 1)
+#define PIN_PC9__D7			PINMUX_PIN(PIN_PC9, 5, 2)
+
+#define PIN_PC10			74
+#define PIN_PC10__GPIO			PINMUX_PIN(PIN_PC10, 0, 0)
+#define PIN_PC10__I2SMCC0_DIN3		PINMUX_PIN(PIN_PC10, 1, 1)
+#define PIN_PC10__PDMC0_DS0		PINMUX_PIN(PIN_PC10, 2, 2)
+#define PIN_PC10__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PC10, 3, 1)
+#define PIN_PC10__FLEXCOM9_IO2		PINMUX_PIN(PIN_PC10, 4, 1)
+#define PIN_PC10__D2			PINMUX_PIN(PIN_PC10, 5, 2)
+
+#define PIN_PC11			75
+#define PIN_PC11__GPIO			PINMUX_PIN(PIN_PC11, 0, 0)
+#define PIN_PC11__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PC11, 1, 1)
+#define PIN_PC11__PDMC1_DS0		PINMUX_PIN(PIN_PC11, 2, 1)
+#define PIN_PC11__FLEXCOM9_IO3		PINMUX_PIN(PIN_PC11, 4, 1)
+#define PIN_PC10__D3			PINMUX_PIN(PIN_PC10, 5, 2)
+
+#define PIN_PC12			76
+#define PIN_PC12__GPIO			PINMUX_PIN(PIN_PC12, 0, 0)
+#define PIN_PC12__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PC12, 1, 1)
+#define PIN_PC12__PDMC1_CLK		PINMUX_PIN(PIN_PC12, 2, 1)
+#define PIN_PC12__FLEXCOM9_IO4		PINMUX_PIN(PIN_PC12, 4, 1)
+#define PIN_PC12__A9			PINMUX_PIN(PIN_PC12, 5, 1)
+
+#define PIN_PC13			77
+#define PIN_PC13__GPIO			PINMUX_PIN(PIN_PC13, 0, 0)
+#define PIN_PC13__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PC13, 1, 1)
+#define PIN_PC13__PDMC1_DS1		PINMUX_PIN(PIN_PC13, 2, 1)
+#define PIN_PC13__A8			PINMUX_PIN(PIN_PC13, 5, 1)
+
+#define PIN_PC14			78
+#define PIN_PC14__GPIO			PINMUX_PIN(PIN_PC14, 0, 0)
+#define PIN_PC14__I2SMCC1_DIN0		PINMUX_PIN(PIN_PC14, 1, 1)
+#define PIN_PC14__SPDIF_RX		PINMUX_PIN(PIN_PC14, 2, 3)
+#define PIN_PC14__FLEXCOM1_IO0		PINMUX_PIN(PIN_PC14, 3, 2)
+#define PIN_PC14__A7			PINMUX_PIN(PIN_PC14, 5, 1)
+
+#define PIN_PC15			79
+#define PIN_PC15__GPIO			PINMUX_PIN(PIN_PC15, 0, 0)
+#define PIN_PC15__I2SMCC1_WS		PINMUX_PIN(PIN_PC15, 1, 1)
+#define PIN_PC15__PDMC1_DS1		PINMUX_PIN(PIN_PC15, 2, 2)
+#define PIN_PC15__FLEXCOM1_IO1		PINMUX_PIN(PIN_PC15, 3, 2)
+#define PIN_PC15__A6			PINMUX_PIN(PIN_PC15, 5, 1)
+
+#define PIN_PC16			80
+#define PIN_PC16__GPIO			PINMUX_PIN(PIN_PC16, 0, 0)
+#define PIN_PC16__I2SMCC1_CK		PINMUX_PIN(PIN_PC16, 1, 1)
+#define PIN_PC16__PDMC1_CLK		PINMUX_PIN(PIN_PC16, 2, 2)
+#define PIN_PC16__FLEXCOM1_IO2		PINMUX_PIN(PIN_PC16, 3, 2)
+#define PIN_PC16__TIOA1			PINMUX_PIN(PIN_PC16, 4, 2)
+#define PIN_PC16__A5			PINMUX_PIN(PIN_PC16, 5, 1)
+
+#define PIN_PC17			81
+#define PIN_PC17__GPIO			PINMUX_PIN(PIN_PC17, 0, 0)
+#define PIN_PC17__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PC17, 1, 1)
+#define PIN_PC17__PDMC1_DS0		PINMUX_PIN(PIN_PC17, 2, 2)
+#define PIN_PC17__FLEXCOM1_IO3		PINMUX_PIN(PIN_PC17, 3, 2)
+#define PIN_PC17__TCLK1			PINMUX_PIN(PIN_PC17, 4, 2)
+#define PIN_PC17__A4			PINMUX_PIN(PIN_PC17, 5, 1)
+
+#define PIN_PC18			82
+#define PIN_PC18__GPIO			PINMUX_PIN(PIN_PC18, 0, 0)
+#define PIN_PC18__I2SMCC0_DIN0		PINMUX_PIN(PIN_PC18, 1, 1)
+#define PIN_PC18__SPDIF_TX		PINMUX_PIN(PIN_PC18, 2, 3)
+#define PIN_PC18__FLEXCOM1_IO4		PINMUX_PIN(PIN_PC18, 3, 2)
+#define PIN_PC18__TIOB1			PINMUX_PIN(PIN_PC18, 4, 2)
+#define PIN_PC18__A3			PINMUX_PIN(PIN_PC18, 5, 1)
+
+#define PIN_PC19			83
+#define PIN_PC19__GPIO			PINMUX_PIN(PIN_PC19, 0, 0)
+#define PIN_PC19__I2SMCC0_WS		PINMUX_PIN(PIN_PC19, 1, 1)
+#define PIN_PC19__PCK6			PINMUX_PIN(PIN_PC19, 2, 1)
+#define PIN_PC19__A2			PINMUX_PIN(PIN_PC19, 5, 1)
+
+#define PIN_PC20			84
+#define PIN_PC20__GPIO			PINMUX_PIN(PIN_PC20, 0, 0)
+#define PIN_PC20__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PC20, 1, 1)
+#define PIN_PC20__A1			PINMUX_PIN(PIN_PC20, 5, 1)
+
+#define PIN_PC21			85
+#define PIN_PC21__GPIO			PINMUX_PIN(PIN_PC21, 0, 0)
+#define PIN_PC21__I2SMCC0_CK		PINMUX_PIN(PIN_PC21, 1, 1)
+#define PIN_PC21__PCK7			PINMUX_PIN(PIN_PC21, 2, 1)
+#define PIN_PC21__A0			PINMUX_PIN(PIN_PC21, 5, 1)
+
+#define PIN_PC22			86
+#define PIN_PC22__GPIO			PINMUX_PIN(PIN_PC22, 0, 0)
+#define PIN_PC22__NTRST			PINMUX_PIN(PIN_PC22, 1, 1)
+#define PIN_PC22__NWAIT			PINMUX_PIN(PIN_PC22, 5, 1)
+
+#define PIN_PC23			87
+#define PIN_PC23__GPIO			PINMUX_PIN(PIN_PC23, 0, 0)
+#define PIN_PC23__TCK_SWCLK		PINMUX_PIN(PIN_PC23, 1, 1)
+
+#define PIN_PC24			88
+#define PIN_PC24__GPIO			PINMUX_PIN(PIN_PC24, 0, 0)
+#define PIN_PC24__TMS_SWDIO		PINMUX_PIN(PIN_PC24, 1, 1)
+
+#define PIN_PC25			89
+#define PIN_PC25__GPIO			PINMUX_PIN(PIN_PC25, 0, 0)
+#define PIN_PC25__TDI			PINMUX_PIN(PIN_PC25, 1, 1)
+
+#define PIN_PC26			90
+#define PIN_PC26__GPIO			PINMUX_PIN(PIN_PC26, 0, 0)
+#define PIN_PC26__TDO			PINMUX_PIN(PIN_PC26, 1, 1)
+#define PIN_PC26__A15			PINMUX_PIN(PIN_PC26, 5, 1)
+
+#define PIN_PC27			91
+#define PIN_PC27__GPIO			PINMUX_PIN(PIN_PC27, 0, 0)
+#define PIN_PC27__SDMMC2_CMD		PINMUX_PIN(PIN_PC27, 1, 1)
+#define PIN_PC27__FLEXCOM8_IO0		PINMUX_PIN(PIN_PC27, 2, 2)
+#define PIN_PC27__TD1			PINMUX_PIN(PIN_PC27, 4, 2)
+#define PIN_PC27__D8			PINMUX_PIN(PIN_PC27, 5, 1)
+
+#define PIN_PC28			92
+#define PIN_PC28__GPIO			PINMUX_PIN(PIN_PC28, 0, 0)
+#define PIN_PC28__SDMMC2_CK		PINMUX_PIN(PIN_PC28, 1, 1)
+#define PIN_PC28__FLEXCOM8_IO1		PINMUX_PIN(PIN_PC28, 2, 2)
+#define PIN_PC28__TF1			PINMUX_PIN(PIN_PC28, 4, 2)
+#define PIN_PC28__D9			PINMUX_PIN(PIN_PC28, 5, 1)
+
+#define PIN_PC29			93
+#define PIN_PC29__GPIO			PINMUX_PIN(PIN_PC29, 0, 0)
+#define PIN_PC29__SDMMC2_DAT0		PINMUX_PIN(PIN_PC29, 1, 1)
+#define PIN_PC29__FLEXCOM8_IO2		PINMUX_PIN(PIN_PC29, 2, 2)
+#define PIN_PC29__TK1			PINMUX_PIN(PIN_PC29, 4, 2)
+#define PIN_PC29__D10			PINMUX_PIN(PIN_PC29, 5, 1)
+#define PIN_PC29__TCLK0			PINMUX_PIN(PIN_PC29, 6, 1)
+
+#define PIN_PC30			94
+#define PIN_PC30__GPIO			PINMUX_PIN(PIN_PC30, 0, 0)
+#define PIN_PC30__SDMMC2_DAT1		PINMUX_PIN(PIN_PC30, 1, 1)
+#define PIN_PC30__FLEXCOM8_IO3		PINMUX_PIN(PIN_PC30, 2, 2)
+#define PIN_PC30__RD1			PINMUX_PIN(PIN_PC30, 4, 2)
+#define PIN_PC30__D11			PINMUX_PIN(PIN_PC30, 5, 1)
+#define PIN_PC30__TIOA0			PINMUX_PIN(PIN_PC30, 6, 1)
+
+#define PIN_PC31			95
+#define PIN_PC31__GPIO			PINMUX_PIN(PIN_PC31, 0, 0)
+#define PIN_PC31__SDMMC2_DAT2		PINMUX_PIN(PIN_PC31, 1, 1)
+#define PIN_PC31__FLEXCOM8_IO4		PINMUX_PIN(PIN_PC31, 2, 2)
+#define PIN_PC31__PCK0			PINMUX_PIN(PIN_PC31, 3, 2)
+#define PIN_PC31__RK1			PINMUX_PIN(PIN_PC31, 4, 2)
+#define PIN_PC31__D12			PINMUX_PIN(PIN_PC31, 5, 1)
+#define PIN_PC31__TIOB0			PINMUX_PIN(PIN_PC31, 6, 1)
+
+#define PIN_PD0				96
+#define PIN_PD0__GPIO			PINMUX_PIN(PIN_PD0, 0, 0)
+#define PIN_PD0__SDMMC2_DAT3		PINMUX_PIN(PIN_PD0, 1, 1)
+#define PIN_PD0__PCK1			PINMUX_PIN(PIN_PD0, 3, 2)
+#define PIN_PD0__RF1			PINMUX_PIN(PIN_PD0, 4, 2)
+#define PIN_PD0__D13			PINMUX_PIN(PIN_PD0, 5, 1)
+
+#define PIN_PD1				97
+#define PIN_PD1__GPIO			PINMUX_PIN(PIN_PD1, 0, 0)
+#define PIN_PD1__SDMMC2_WP		PINMUX_PIN(PIN_PD1, 1, 1)
+#define PIN_PD1__FLEXCOM1_IO5		PINMUX_PIN(PIN_PD1, 2, 1)
+#define PIN_PD1__LCDC_HSYNC		PINMUX_PIN(PIN_PD1, 3, 2)
+#define PIN_PD1__FLEXCOM3_IO0		PINMUX_PIN(PIN_PD1, 4, 3)
+
+#define PIN_PD2				98
+#define PIN_PD2__GPIO			PINMUX_PIN(PIN_PD2, 0, 0)
+#define PIN_PD2__SDMMC2_CD		PINMUX_PIN(PIN_PD2, 1, 1)
+#define PIN_PD2__FLEXCOM1_IO6		PINMUX_PIN(PIN_PD2, 2, 1)
+#define PIN_PD2__LCDC_VSYNC		PINMUX_PIN(PIN_PD2, 3, 2)
+#define PIN_PD2__FLEXCOM3_IO1		PINMUX_PIN(PIN_PD2, 4, 3)
+
+#define PIN_PD3				99
+#define PIN_PD3__GPIO			PINMUX_PIN(PIN_PD3, 0, 0)
+#define PIN_PD3__SDMMC2_1V8SEL		PINMUX_PIN(PIN_PD3, 1, 1)
+#define PIN_PD3__FLEXCOM1_IO4		PINMUX_PIN(PIN_PD3, 2, 1)
+#define PIN_PD3__TIOA0			PINMUX_PIN(PIN_PD3, 3, 2)
+#define PIN_PD3__FLEXCOM3_IO2		PINMUX_PIN(PIN_PD3, 4, 3)
+#define PIN_PD3__EXT_IRQ1		PINMUX_PIN(PIN_PD3, 5, 3)
+
+#define PIN_PD4				100
+#define PIN_PD4__GPIO			PINMUX_PIN(PIN_PD4, 0, 0)
+#define PIN_PD4__LCDC_HSYNC		PINMUX_PIN(PIN_PD4, 1, 1)
+#define PIN_PD4__FLEXCOM1_IO2		PINMUX_PIN(PIN_PD4, 2, 1)
+#define PIN_PD4__TIOB0			PINMUX_PIN(PIN_PD4, 3, 2)
+#define PIN_PD4__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD4, 4, 3)
+
+#define PIN_PD5				101
+#define PIN_PD5__GPIO			PINMUX_PIN(PIN_PD5, 0, 0)
+#define PIN_PD5__LCDC_VSYNC		PINMUX_PIN(PIN_PD5, 1, 1)
+#define PIN_PD5__FLEXCOM1_IO3		PINMUX_PIN(PIN_PD5, 2, 1)
+#define PIN_PD5__TCLK0			PINMUX_PIN(PIN_PD5, 3, 2)
+#define PIN_PD5__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD5, 4, 3)
+
+#define PIN_PD6				102
+#define PIN_PD6__GPIO			PINMUX_PIN(PIN_PD6, 0, 0)
+#define PIN_PD6__LCDC_PWM		PINMUX_PIN(PIN_PD6, 1, 1)
+#define PIN_PD6__FLEXCOM1_IO1		PINMUX_PIN(PIN_PD6, 2, 1)
+#define PIN_PD6__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD6, 4, 3)
+
+#define PIN_PD7				103
+#define PIN_PD7__GPIO			PINMUX_PIN(PIN_PD7, 0, 0)
+#define PIN_PD7__LCDC_DISP		PINMUX_PIN(PIN_PD7, 1, 1)
+#define PIN_PD7__FLEXCOM1_IO0		PINMUX_PIN(PIN_PD7, 2, 1)
+#define PIN_PD7__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD7, 4, 3)
+
+#define PIN_PD8				104
+#define PIN_PD8__GPIO			PINMUX_PIN(PIN_PD8, 0, 0)
+#define PIN_PD8__CANTX0			PINMUX_PIN(PIN_PD8, 1, 1)
+#define PIN_PD8__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD8, 2, 1)
+
+#define PIN_PD9				105
+#define PIN_PD9__GPIO			PINMUX_PIN(PIN_PD9, 0, 0)
+#define PIN_PD9__CANRX0			PINMUX_PIN(PIN_PD9, 1, 1)
+#define PIN_PD9__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD9, 2, 1)
+
+#define PIN_PD10			106
+#define PIN_PD10__GPIO			PINMUX_PIN(PIN_PD10, 0, 0)
+#define PIN_PD10__CANTX1		PINMUX_PIN(PIN_PD10, 1, 1)
+#define PIN_PD10__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD10, 2, 1)
+#define PIN_PD10__TIOA1			PINMUX_PIN(PIN_PD10, 3, 3)
+
+#define PIN_PD11			107
+#define PIN_PD11__GPIO			PINMUX_PIN(PIN_PD11, 0, 0)
+#define PIN_PD11__CANRX1		PINMUX_PIN(PIN_PD11, 1, 1)
+#define PIN_PD11__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD11, 2, 1)
+#define PIN_PD11__TCLK1			PINMUX_PIN(PIN_PD11, 3, 3)
+
+#define PIN_PD12			108
+#define PIN_PD12__GPIO			PINMUX_PIN(PIN_PD12, 0, 0)
+#define PIN_PD12__CANTX2		PINMUX_PIN(PIN_PD12, 1, 1)
+#define PIN_PD12__FLEXCOM7_IO4		PINMUX_PIN(PIN_PD12, 2, 1)
+#define PIN_PD12__TIOB1			PINMUX_PIN(PIN_PD12, 3, 3)
+#define PIN_PD12__PCK2			PINMUX_PIN(PIN_PD12, 4, 2)
+#define PIN_PD12__FLEXCOM3_IO3		PINMUX_PIN(PIN_PD12, 5, 3)
+
+#define PIN_PD13			109
+#define PIN_PD13__GPIO			PINMUX_PIN(PIN_PD13, 0, 0)
+#define PIN_PD13__CANRX2		PINMUX_PIN(PIN_PD13, 1, 1)
+#define PIN_PD13__FLEXCOM5_IO4		PINMUX_PIN(PIN_PD13, 2, 1)
+#define PIN_PD13__TIOA2			PINMUX_PIN(PIN_PD13, 3, 3)
+#define PIN_PD13__PCK3			PINMUX_PIN(PIN_PD13, 4, 2)
+
+#define PIN_PD14			110
+#define PIN_PD14__GPIO			PINMUX_PIN(PIN_PD14, 0, 0)
+#define PIN_PD14__CANTX3		PINMUX_PIN(PIN_PD14, 1, 1)
+#define PIN_PD14__FLEXCOM5_IO2		PINMUX_PIN(PIN_PD14, 2, 1)
+#define PIN_PD14__TIOB2			PINMUX_PIN(PIN_PD14, 3, 3)
+
+#define PIN_PD15			111
+#define PIN_PD15__GPIO			PINMUX_PIN(PIN_PD15, 0, 0)
+#define PIN_PD15__CANRX3		PINMUX_PIN(PIN_PD15, 1, 1)
+#define PIN_PD15__FLEXCOM5_IO3		PINMUX_PIN(PIN_PD15, 2, 1)
+#define PIN_PD15__TCLK2			PINMUX_PIN(PIN_PD15, 3, 3)
+
+#define PIN_PD16			112
+#define PIN_PD16__GPIO			PINMUX_PIN(PIN_PD16, 0, 0)
+#define PIN_PD16__CANTX4		PINMUX_PIN(PIN_PD16, 1, 1)
+#define PIN_PD16__FLEXCOM5_IO0		PINMUX_PIN(PIN_PD16, 2, 1)
+
+#define PIN_PD17			113
+#define PIN_PD17__GPIO			PINMUX_PIN(PIN_PD17, 0, 0)
+#define PIN_PD17__CANRX4		PINMUX_PIN(PIN_PD17, 1, 1)
+#define PIN_PD17__FLEXCOM5_IO1		PINMUX_PIN(PIN_PD17, 2, 1)
+
+#define PIN_PD18			114
+#define PIN_PD18__GPIO			PINMUX_PIN(PIN_PD18, 0, 0)
+#define PIN_PD18__FLEXCOM6_IO0		PINMUX_PIN(PIN_PD18, 2, 4)
+#define PIN_PD18__CANTX1		PINMUX_PIN(PIN_PD18, 3, 2)
+#define PIN_PD18__PCK4			PINMUX_PIN(PIN_PD18, 4, 2)
+
+#define PIN_PD19			115
+#define PIN_PD19__GPIO			PINMUX_PIN(PIN_PD19, 0, 0)
+#define PIN_PD19__FLEXCOM6_IO1		PINMUX_PIN(PIN_PD19, 2, 4)
+#define PIN_PD19__CANRX1		PINMUX_PIN(PIN_PD19, 3, 2)
+#define PIN_PD19__PCK2			PINMUX_PIN(PIN_PD19, 4, 3)
+
+#define PIN_PD20			116
+#define PIN_PD20__GPIO			PINMUX_PIN(PIN_PD20, 0, 0)
+#define PIN_PD20__PFLEXCOM6_IO2		PINMUX_PIN(PIN_PD20, 2, 4)
+#define PIN_PD20__I2SMCC1_MCK		PINMUX_PIN(PIN_PD20, 3, 2)
+#define PIN_PD20__PCK3			PINMUX_PIN(PIN_PD20, 4, 3)
+
+#define PIN_PD21			117
+#define PIN_PD21__GPIO			PINMUX_PIN(PIN_PD21, 0, 0)
+#define PIN_PD21__G1_TXCTL		PINMUX_PIN(PIN_PD21, 1, 2)
+#define PIN_PD21__FLEXCOM6_IO2		PINMUX_PIN(PIN_PD21, 2, 3)
+#define PIN_PD21__TK1			PINMUX_PIN(PIN_PD21, 3, 1)
+
+#define PIN_PD22			118
+#define PIN_PD22__GPIO			PINMUX_PIN(PIN_PD22, 0, 0)
+#define PIN_PD22__G1_TX0		PINMUX_PIN(PIN_PD22, 1, 1)
+#define PIN_PD22__FLEXCOM6_IO3		PINMUX_PIN(PIN_PD22, 2, 3)
+#define PIN_PD22__TF1			PINMUX_PIN(PIN_PD22, 3, 1)
+
+#define PIN_PD23			119
+#define PIN_PD23__GPIO			PINMUX_PIN(PIN_PD23, 0, 0)
+#define PIN_PD23__G1_TX1		PINMUX_PIN(PIN_PD23, 1, 1)
+#define PIN_PD23__FLEXCOM6_IO4		PINMUX_PIN(PIN_PD23, 2, 3)
+#define PIN_PD23__TD1			PINMUX_PIN(PIN_PD23, 3, 1)
+
+#define PIN_PD24			120
+#define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
+#define PIN_PD24__G1_RXCTL		PINMUX_PIN(PIN_PD24, 1, 1)
+#define PIN_PD24__FLEXCOM6_IO0		PINMUX_PIN(PIN_PD24, 2, 3)
+#define PIN_PD24__RD1			PINMUX_PIN(PIN_PD24, 3, 1)
+#define PIN_PD24__PDMC0_DS1		PINMUX_PIN(PIN_PD24, 5, 3)
+
+#define PIN_PD25			121
+#define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
+#define PIN_PD25__G1_MDC		PINMUX_PIN(PIN_PD25, 1, 1)
+#define PIN_PD25__FLEXCOM6_IO1		PINMUX_PIN(PIN_PD25, 2, 3)
+#define PIN_PD25__RK1			PINMUX_PIN(PIN_PD25, 3, 1)
+#define PIN_PD25__PDMC0_CLK		PINMUX_PIN(PIN_PD25, 5, 3)
+
+#define PIN_PD26			122
+#define PIN_PD26__GPIO			PINMUX_PIN(PIN_PD26, 0, 0)
+#define PIN_PD26__G1_MDIO		PINMUX_PIN(PIN_PD26, 1, 1)
+#define PIN_PD26__FLEXCOM7_IO4		PINMUX_PIN(PIN_PD26, 2, 2)
+#define PIN_PD26__RF1			PINMUX_PIN(PIN_PD26, 3, 1)
+#define PIN_PD26__I2SMCC1_DIN2		PINMUX_PIN(PIN_PD26, 4, 2)
+#define PIN_PD26__PDMC0_DS0		PINMUX_PIN(PIN_PD26, 5, 3)
+
+#define PIN_PD27			123
+#define PIN_PD27__GPIO			PINMUX_PIN(PIN_PD27, 0, 0)
+#define PIN_PD27__G1_RX0		PINMUX_PIN(PIN_PD27, 1, 1)
+#define PIN_PD27__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD27, 2, 2)
+#define PIN_PD27__SPDIF_RX		PINMUX_PIN(PIN_PD27, 3, 1)
+#define PIN_PD27__I2SMCC1_DIN3		PINMUX_PIN(PIN_PD27, 4, 2)
+
+#define PIN_PD28			124
+#define PIN_PD28__GPIO			PINMUX_PIN(PIN_PD28, 0, 0)
+#define PIN_PD28__G1_RX1		PINMUX_PIN(PIN_PD28, 1, 1)
+#define PIN_PD28__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD28, 2, 2)
+#define PIN_PD28__SPDIF_TX		PINMUX_PIN(PIN_PD28, 3, 1)
+#define PIN_PD28__I2SMCC1_DIN1		PINMUX_PIN(PIN_PD28, 4, 2)
+
+#define PIN_PD29			125
+#define PIN_PD29__GPIO			PINMUX_PIN(PIN_PD29, 0, 0)
+#define PIN_PD29__G1_REFCK		PINMUX_PIN(PIN_PD29, 1, 2)
+#define PIN_PD29__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD29, 2, 2)
+#define PIN_PD29__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PD29, 3, 2)
+
+#define PIN_PD30			126
+#define PIN_PD30__GPIO			PINMUX_PIN(PIN_PD30, 0, 0)
+#define PIN_PD30__G1_RX2		PINMUX_PIN(PIN_PD30, 1, 1)
+#define PIN_PD30__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD30, 2, 2)
+#define PIN_PD30__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PD30, 3, 2)
+#define PIN_PD30__PDMC1_DS1		PINMUX_PIN(PIN_PD30, 4, 3)
+#define PIN_PD30__G1_RXER		PINMUX_PIN(PIN_PD30, 5, 2)
+
+#define PIN_PD31			127
+#define PIN_PD31__GPIO			PINMUX_PIN(PIN_PD31, 0, 0)
+#define PIN_PD31__G1_RX3		PINMUX_PIN(PIN_PD31, 1, 1)
+#define PIN_PD31__FLEXCOM5_IO4		PINMUX_PIN(PIN_PD31, 2, 2)
+#define PIN_PD31__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PD31, 3, 3)
+#define PIN_PD31__PDMC1_DS0		PINMUX_PIN(PIN_PD31, 4, 3)
+
+#define PIN_PE0				128
+#define PIN_PE0__GPIO			PINMUX_PIN(PIN_PE0, 0, 0)
+#define PIN_PE0__G1_TX2			PINMUX_PIN(PIN_PE0, 1, 1)
+#define PIN_PE0__FLEXCOM5_IO2		PINMUX_PIN(PIN_PE0, 2, 2)
+#define PIN_PE0__I2SMCC1_DIN0		PINMUX_PIN(PIN_PE0, 3, 2)
+#define PIN_PE0__PDMC1_CLK		PINMUX_PIN(PIN_PE0, 4, 3)
+
+#define PIN_PE1				129
+#define PIN_PE1__GPIO			PINMUX_PIN(PIN_PE1, 0, 0)
+#define PIN_PE1__G1_TX3			PINMUX_PIN(PIN_PE1, 1, 1)
+#define PIN_PE1__FLEXCOM5_IO3		PINMUX_PIN(PIN_PE1, 2, 2)
+#define PIN_PE1__I2SMCC1_WS		PINMUX_PIN(PIN_PE1, 3, 2)
+#define PIN_PE1__PDMC0_DS1		PINMUX_PIN(PIN_PE1, 4, 4)
+
+#define PIN_PE2				130
+#define PIN_PE2__GPIO			PINMUX_PIN(PIN_PE2, 0, 0)
+#define PIN_PE2__G1_RXCK		PINMUX_PIN(PIN_PE2, 1, 1)
+#define PIN_PE2__FLEXCOM5_IO1		PINMUX_PIN(PIN_PE2, 2, 2)
+#define PIN_PE2__I2SMCC1_CK		PINMUX_PIN(PIN_PE2, 3, 2)
+#define PIN_PE2__PDMC0_CLK		PINMUX_PIN(PIN_PE2, 4, 4)
+
+#define PIN_PE3				131
+#define PIN_PE3__GPIO			PINMUX_PIN(PIN_PE3, 0, 0)
+#define PIN_PE3__G1_TSUCOMP		PINMUX_PIN(PIN_PE3, 1, 1)
+#define PIN_PE3__FLEXCOM5_IO0		PINMUX_PIN(PIN_PE3, 2, 2)
+#define PIN_PE3__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PE3, 3, 2)
+#define PIN_PE3__PDMC0_DS0		PINMUX_PIN(PIN_PE3, 4, 4)
+
+#define PIN_PE4				132
+#define PIN_PE4__GPIO			PINMUX_PIN(PIN_PE4, 0, 0)
+#define PIN_PE4__LCDC_DAT0		PINMUX_PIN(PIN_PE4, 1, 1)
+#define PIN_PE4__FLEXCOM2_IO2		PINMUX_PIN(PIN_PE4, 2, 1)
+#define PIN_PE4__PWML0			PINMUX_PIN(PIN_PE4, 3, 2)
+#define PIN_PE4__TIOA3			PINMUX_PIN(PIN_PE4, 4, 1)
+#define PIN_PE4__I2SMCC0_DIN1		PINMUX_PIN(PIN_PE4, 5, 2)
+
+#define PIN_PE5				133
+#define PIN_PE5__GPIO			PINMUX_PIN(PIN_PE5, 0, 0)
+#define PIN_PE5__LCDC_DAT1		PINMUX_PIN(PIN_PE5, 1, 1)
+#define PIN_PE5__FLEXCOM2_IO3		PINMUX_PIN(PIN_PE5, 2, 1)
+#define PIN_PE5__PWMH0			PINMUX_PIN(PIN_PE5, 3, 2)
+#define PIN_PE5__TIOB3			PINMUX_PIN(PIN_PE5, 4, 1)
+#define PIN_PE5__I2SMCC0_DIN2		PINMUX_PIN(PIN_PE5, 5, 2)
+
+#define PIN_PE6				134
+#define PIN_PE6__GPIO			PINMUX_PIN(PIN_PE6, 0, 0)
+#define PIN_PE6__LCDC_DAT2		PINMUX_PIN(PIN_PE6, 1, 1)
+#define PIN_PE6__FLEXCOM2_IO4		PINMUX_PIN(PIN_PE6, 2, 1)
+#define PIN_PE6__PWML1			PINMUX_PIN(PIN_PE6, 3, 2)
+#define PIN_PE6__TCLK3			PINMUX_PIN(PIN_PE6, 4, 1)
+#define PIN_PE6__I2SMCC0_DIN3		PINMUX_PIN(PIN_PE6, 5, 2)
+
+#define PIN_PE7				135
+#define PIN_PE7__GPIO			PINMUX_PIN(PIN_PE7, 0, 0)
+#define PIN_PE7__LCDC_DAT3		PINMUX_PIN(PIN_PE7, 1, 1)
+#define PIN_PE7__FLEXCOM2_IO5		PINMUX_PIN(PIN_PE7, 2, 1)
+#define PIN_PE7__PWMH1			PINMUX_PIN(PIN_PE7, 3, 2)
+#define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 4, 1)
+#define PIN_PE7__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PE7, 5, 2)
+
+#define PIN_PE8				136
+#define PIN_PE8__GPIO			PINMUX_PIN(PIN_PE8, 0, 0)
+#define PIN_PE8__LCDC_DAT4		PINMUX_PIN(PIN_PE8, 1, 1)
+#define PIN_PE8__FLEXCOM2_IO0		PINMUX_PIN(PIN_PE8, 2, 1)
+#define PIN_PE8__PWML2			PINMUX_PIN(PIN_PE8, 3, 2)
+#define PIN_PE8__TIOB4			PINMUX_PIN(PIN_PE8, 4, 1)
+#define PIN_PE8__I2SMCC0_CK		PINMUX_PIN(PIN_PE8, 5, 2)
+
+#define PIN_PE9				137
+#define PIN_PE9__GPIO			PINMUX_PIN(PIN_PE9, 0, 0)
+#define PIN_PE9__LCDC_DAT5		PINMUX_PIN(PIN_PE9, 1, 1)
+#define PIN_PE9__FLEXCOM2_IO1		PINMUX_PIN(PIN_PE9, 2, 1)
+#define PIN_PE9__PWMH2			PINMUX_PIN(PIN_PE9, 3, 2)
+#define PIN_PE9__TCLK4			PINMUX_PIN(PIN_PE9, 4, 1)
+#define PIN_PE9__I2SMCC0_WS		PINMUX_PIN(PIN_PE9, 5, 2)
+
+#define PIN_PE10			138
+#define PIN_PE10__GPIO			PINMUX_PIN(PIN_PE10, 0, 0)
+#define PIN_PE10__LCDC_DAT6		PINMUX_PIN(PIN_PE10, 1, 1)
+#define PIN_PE10__FLEXCOM2_IO6		PINMUX_PIN(PIN_PE10, 2, 1)
+#define PIN_PE10__PWML3			PINMUX_PIN(PIN_PE10, 3, 2)
+#define PIN_PE10__TIOA5			PINMUX_PIN(PIN_PE10, 4, 1)
+#define PIN_PE10__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PE10, 5, 2)
+
+#define PIN_PE11			139
+#define PIN_PE11__GPIO			PINMUX_PIN(PIN_PE11, 0, 0)
+#define PIN_PE11__LCDC_DAT7		PINMUX_PIN(PIN_PE11, 1, 1)
+#define PIN_PE11__PWMH3			PINMUX_PIN(PIN_PE11, 3, 2)
+#define PIN_PE11__TIOB5			PINMUX_PIN(PIN_PE11, 4, 1)
+#define PIN_PE11__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PE11, 5, 2)
+
+#define PIN_PE12			140
+#define PIN_PE12__GPIO			PINMUX_PIN(PIN_PE12, 0, 0)
+#define PIN_PE12__LCDC_DEN		PINMUX_PIN(PIN_PE12, 1, 1)
+#define PIN_PE12__PCK3			PINMUX_PIN(PIN_PE12, 2, 4)
+#define PIN_PE12__PWMEXTRG0		PINMUX_PIN(PIN_PE12, 3, 2)
+#define PIN_PE12__TCLK5			PINMUX_PIN(PIN_PE12, 4, 1)
+#define PIN_PE12__I2SMCC0_DIN0		PINMUX_PIN(PIN_PE12, 5, 2)
+
+#define PIN_PE13			141
+#define PIN_PE13__GPIO			PINMUX_PIN(PIN_PE13, 0, 0)
+#define PIN_PE13__LCDC_PCK		PINMUX_PIN(PIN_PE13, 1, 1)
+#define PIN_PE13__PCK4			PINMUX_PIN(PIN_PE13, 2, 3)
+#define PIN_PE13__PWMEXTRG1		PINMUX_PIN(PIN_PE13, 3, 2)
+#define PIN_PE13__I2SMCC0DOUT0		PINMUX_PIN(PIN_PE13, 5, 2)
diff --git a/dts/upstream/src/arm/microchip/sama7d65.dtsi b/dts/upstream/src/arm/microchip/sama7d65.dtsi
new file mode 100644
index 00000000000..854b30d15dc
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/sama7d65.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *  sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
+ *
+ *  Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ *  Author: Ryan Wanner <Ryan.Wanner@microchip.com>
+ *
+ */
+
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/at91-usart.h>
+
+/ {
+	model = "Microchip SAMA7D65 family SoC";
+	compatible = "microchip,sama7d65";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			device_type = "cpu";
+			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+			clock-names = "cpu";
+		};
+	};
+
+	clocks {
+		main_xtal: clock-mainxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		slow_xtal: clock-slowxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pioa: pinctrl@e0014000 {
+			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
+			reg = <0xe0014000 0x800>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		pmc: clock-controller@e0018000 {
+			compatible = "microchip,sama7d65-pmc", "syscon";
+			reg = <0xe0018000 0x200>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#clock-cells = <2>;
+			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+			clock-names = "td_slck", "md_slck", "main_xtal";
+		};
+
+		clk32k: clock-controller@e001d500 {
+			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
+			reg = <0xe001d500 0x4>;
+			clocks = <&slow_xtal>;
+			#clock-cells = <1>;
+		};
+
+		sdmmc1: mmc@e1208000 {
+			compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
+			reg = <0xe1208000 0x400>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
+			assigned-clock-rates = <200000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
+			status = "disabled";
+		};
+
+		pit64b0: timer@e1800000 {
+			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xe1800000 0x100>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
+			clock-names = "pclk", "gclk";
+		};
+
+		pit64b1: timer@e1804000 {
+			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xe1804000 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
+			clock-names = "pclk", "gclk";
+		};
+
+		flx6: flexcom@e2020000 {
+			compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xe2020000 0x200>;
+			ranges = <0x0 0xe2020000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+			status = "disabled";
+
+			uart6: serial@200 {
+				compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@e8c11000 {
+			compatible = "arm,cortex-a7-gic";
+			reg = <0xe8c11000 0x1000>,
+			      <0xe8c12000 0x2000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
index 9f64c85e1c2..c3501786d60 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
@@ -661,7 +661,7 @@
 	clock-frequency = <100000>;
 	status = "okay";
 
-	mb_fru@50 {
+	eeprom@50 {
 		compatible = "atmel,24c64";
 		reg = <0x50>;
 	};
@@ -704,7 +704,7 @@
 				reg = <0x5d>;
 				status = "okay";
 			};
-			fan_fru@51 {
+			eeprom@51 {
 				compatible = "atmel,24c64";
 				reg = <0x51>;
 			};
@@ -714,7 +714,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <3>;
-			hsbp_fru@52 {
+			eeprom@52 {
 				compatible = "atmel,24c64";
 				reg = <0x52>;
 				status = "okay";
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
index 087f4ac4318..f67ede14820 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
@@ -824,7 +824,7 @@
 		reg = <0x4a>;
 		status = "okay";
 	};
-	m24128_fru@51 {
+	eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <64>;
diff --git a/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi b/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
index 8125c1b3e8d..974c76f007d 100644
--- a/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
@@ -716,6 +716,7 @@
 		regulator-name = "+5V_USB_HS";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
 		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		gpio-open-drain;
@@ -727,6 +728,7 @@
 		regulator-name = "+5V_USB_SS";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
 		gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		gpio-open-drain;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
index 7cd17b43b4b..06545a6052f 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
@@ -160,7 +160,7 @@
 		};
 	};
 
-	mdio_gpio: mdio-gpio {
+	mdio_gpio: mdio {
 		compatible = "virtual,mdio-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_swmdio>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
index 625f9ac671a..26eb7a9506e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
@@ -37,7 +37,7 @@
 		regulator-max-microvolt = <5000000>;
 	};
 
-	mdio_gpio: mdio-gpio {
+	mdio_gpio: mdio {
 		compatible = "virtual,mdio-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_swmdio>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
index c1ae7c47b44..aa1adcc7401 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
@@ -94,7 +94,7 @@
 		mdio-gpio0 = &mdio0;
 	};
 
-	mdio0: mdio-gpio {
+	mdio0: mdio {
 		compatible = "virtual,mdio-gpio";
 		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
 			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
index 1c72da41701..88be29166c1 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
@@ -108,6 +108,11 @@
 		};
 	};
 
+	poweroff {
+		compatible = "regulator-poweroff";
+		cpu-supply = <&vgen2_reg>;
+	};
+
 	reg_module_3v3: regulator-module-3v3 {
 		compatible = "regulator-fixed";
 		regulator-always-on;
@@ -236,10 +241,6 @@
 	status = "disabled";
 };
 
-&clks {
-	fsl,pmic-stby-poweroff;
-};
-
 /* Apalis SPI1 */
 &ecspi1 {
 	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
@@ -527,7 +528,6 @@
 
 	pmic: pmic@8 {
 		compatible = "fsl,pfuze100";
-		fsl,pmic-stby-poweroff;
 		reg = <0x08>;
 
 		regulators {
@@ -691,7 +691,7 @@
 
 	adv_7280: adv7280@21 {
 		compatible = "adi,adv7280";
-		adv,force-bt656-4;
+		adi,force-bt656-4;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_ipu1_csi0>;
 		reg = <0x21>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
index dc8298f6db3..960e83f5e90 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
@@ -113,8 +113,8 @@
 			"DMICDAT", "DMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
-		mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+		mic-det-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	};
 
 	backlight_lvds: backlight-lvds {
@@ -804,6 +804,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg>;
 	disable-over-current;
+	dr_mode = "otg";
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
index d2200c9db25..45bcfd7faf9 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
@@ -711,8 +711,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -806,6 +806,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -814,6 +815,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts b/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
index 55cdfa7ea20..036705b783f 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
@@ -108,7 +108,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
 	};
 
 	panel {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
index 941a2f18505..7381fb7f891 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
@@ -546,8 +546,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -640,6 +640,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -648,6 +649,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts b/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
index 05d6827ea2a..81440148679 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
@@ -157,7 +157,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 	};
 };
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
index 1beac42c1a2..67cf09e63a6 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
@@ -167,7 +167,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <6>;
-		hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 	};
 
 	panel {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
index a9550f115f8..5132b575b00 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
@@ -637,8 +637,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -731,6 +731,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -739,6 +740,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
index b74ee8948a7..0e839bbfea0 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
@@ -68,7 +68,7 @@
 		audio-cpu = <&sai2>;
 		audio-codec = <&codec>;
 		audio-asrc = <&asrc>;
-		hp-det-gpio = <&gpio5 4 0>;
+		hp-det-gpios = <&gpio5 4 0>;
 		audio-routing =
 			"Headphone Jack", "HP_L",
 			"Headphone Jack", "HP_R",
diff --git a/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi b/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
index e1c401f468e..576a7df505d 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
@@ -87,34 +87,6 @@
 			      <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
 	};
 
-	reg_sd1_vmmc: regulator-sd1-vmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC3V3_SD1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	reg_fec1_pwdn: regulator-fec1-pwdn {
-		compatible = "regulator-fixed";
-		regulator-name = "PWDN_FEC1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_fec2_pwdn: regulator-fec2-pwdn {
-		compatible = "regulator-fixed";
-		regulator-name = "PWDN_FEC2";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
 	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "VBUS_USBOTG1";
@@ -141,6 +113,7 @@
 		gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-always-on;
+		vin-supply = <&reg_mba_5v>;
 	};
 
 	reg_mpcie_3v3: regulator-mpcie-3v3 {
@@ -151,6 +124,7 @@
 		gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-always-on;
+		vin-supply = <&reg_mba_3v3>;
 	};
 
 	reg_mba_12v0: regulator-mba-12v0 {
@@ -162,13 +136,18 @@
 		enable-active-high;
 	};
 
-	reg_lvds_transmitter: regulator-lvds-transmitter {
+	reg_mba_5v: regulator-mba-5v {
 		compatible = "regulator-fixed";
-		regulator-name = "#SHTDN_LVDS";
+		regulator-name = "VCC5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_mba_3v3: regulator-mba-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
 	};
 
 	reg_vref_1v8: regulator-vref-1v8 {
@@ -186,14 +165,7 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
-	};
-
-	reg_vcc_3v3: regulator-vcc-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		vin-supply = <&reg_mba_3v3>;
 	};
 
 	sound {
@@ -239,7 +211,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
 	phy-mode = "rgmii-id";
-	phy-supply = <&reg_fec1_pwdn>;
 	phy-handle = <&ethphy1_0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -260,6 +231,8 @@
 			reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <500>;
+			interrupt-parent = <&gpio1>;
+			interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 		};
 	};
 };
@@ -318,7 +291,7 @@
 	lm75: temperature-sensor@49 {
 		compatible = "national,lm75a";
 		reg = <0x49>;
-		vs-supply = <&reg_vcc_3v3>;
+		vs-supply = <&reg_mba_3v3>;
 	};
 };
 
@@ -351,7 +324,7 @@
 		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		vcc-supply = <&reg_vcc_3v3>;
+		vcc-supply = <&reg_mba_3v3>;
 	};
 };
 
@@ -668,7 +641,7 @@
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-	vmmc-supply = <&reg_sd1_vmmc>;
+	vmmc-supply = <&reg_mba_3v3>;
 	bus-width = <4>;
 	no-1-8-v;
 	no-sdio;
diff --git a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
index 028961eb710..aa8f65cd4ad 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
@@ -135,6 +135,7 @@
 	lm75a: temperature-sensor@48 {
 		compatible = "national,lm75a";
 		reg = <0x48>;
+		vs-supply = <&vgen4_reg>;
 	};
 
 	/* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
@@ -150,7 +151,6 @@
 		reg = <0x50>;
 		pagesize = <32>;
 		vcc-supply = <&vgen4_reg>;
-		status = "okay";
 	};
 
 	at24c02: eeprom@56 {
@@ -158,7 +158,6 @@
 		reg = <0x56>;
 		pagesize = <16>;
 		vcc-supply = <&vgen4_reg>;
-		status = "okay";
 	};
 
 	ds1339: rtc@68 {
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts b/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
index 0443faa3dfa..e3ee16f1aaa 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
@@ -21,7 +21,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
 	phy-mode = "rgmii-id";
-	phy-supply = <&reg_fec2_pwdn>;
 	phy-handle = <&ethphy2_0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -42,6 +41,8 @@
 			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <500>;
+			interrupt-parent = <&gpio2>;
+			interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
index f712537fca1..6cde8463690 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
@@ -169,7 +169,7 @@
 		model = "wm8960-audio";
 		audio-cpu = <&sai1>;
 		audio-codec = <&codec>;
-		hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+		hp-det-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
 		audio-routing =
 			"Headphone Jack", "HP_L",
 			"Headphone Jack", "HP_R",
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
index d0f6120b665..39530eb580e 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
@@ -427,8 +427,9 @@
 			interrupt-names = "global",
 					  "doorbell";
 
-			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
-			interconnect-names = "pcie-mem";
+			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
 
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
@@ -613,6 +614,8 @@
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
index 3bc67bb8c1e..6b23ee676c9 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
@@ -335,6 +335,10 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "global", "doorbell";
 
+			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>,
+					<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
 
@@ -526,6 +530,8 @@
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm/renesas/r7s72100.dtsi b/dts/upstream/src/arm/renesas/r7s72100.dtsi
index b831bbc431e..1a866dbaf5e 100644
--- a/dts/upstream/src/arm/renesas/r7s72100.dtsi
+++ b/dts/upstream/src/arm/renesas/r7s72100.dtsi
@@ -238,6 +238,8 @@
 				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+			dmas = <&dmac 0x2d21>, <&dmac 0x2d22>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -253,6 +255,8 @@
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+			dmas = <&dmac 0x2d25>, <&dmac 0x2d26>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -268,6 +272,8 @@
 				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+			dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -283,6 +289,8 @@
 				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+			dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -298,6 +306,8 @@
 				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+			dmas = <&dmac 0x2d31>, <&dmac 0x2d32>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
diff --git a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
index 9bc05961577..70e3091062f 100644
--- a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
+++ b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
@@ -300,12 +300,31 @@
 		regulator-max-microvolt = <2800000>;
 	};
 
+	earmic_bias_reg: voltage-regulator-6 {
+		compatible = "regulator-fixed";
+		regulator-name = "EAR_MICBIAS_LDO_2.8V";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	sound: sound {
 		compatible = "samsung,midas-audio";
 		model = "TAB3";
 		mic-bias-supply = <&mic_bias_reg>;
 		submic-bias-supply = <&submic_bias_reg>;
 
+		lineout-sel-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
+
+		headset-mic-bias-supply = <&earmic_bias_reg>;
+		headset-detect-gpios = <&gpx0 4 GPIO_ACTIVE_LOW>;
+		headset-key-gpios = <&gpx3 6 GPIO_ACTIVE_LOW>;
+		samsung,headset-4pole-threshold-microvolt = <710 2000>;
+		samsung,headset-button-threshold-microvolt = <0 130 260>;
+		io-channel-names = "headset-detect";
+		io-channels = <&adc 0>;
+
 		audio-routing = "HP", "HPOUT1L",
 				"HP", "HPOUT1R",
 
@@ -351,6 +370,11 @@
 	};
 };
 
+&adc {
+	vdd-supply = <&ldo3_reg>;
+	status = "okay";
+};
+
 &bus_acp {
 	devfreq = <&bus_dmc>;
 	status = "okay";
@@ -511,12 +535,11 @@
 	wm1811: audio-codec@1a {
 		compatible = "wlf,wm1811";
 		reg = <0x1a>;
-		clocks = <&pmu_system_controller 0>;
-		clock-names = "MCLK1";
+		clocks = <&pmu_system_controller 0>,
+			 <&s5m8767_osc S2MPS11_CLK_BT>;
+		clock-names = "MCLK1", "MCLK2";
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		interrupt-parent = <&gpx3>;
-		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
 
 		gpio-controller;
 		#gpio-cells = <2>;
diff --git a/dts/upstream/src/arm/st/stih410-b2260.dts b/dts/upstream/src/arm/st/stih410-b2260.dts
index 240b6204000..736b1e059b0 100644
--- a/dts/upstream/src/arm/st/stih410-b2260.dts
+++ b/dts/upstream/src/arm/st/stih410-b2260.dts
@@ -206,5 +206,9 @@
 		sata1: sata@9b28000 {
 			status = "okay";
 		};
+
+		gpu: gpu@9f00000 {
+			status = "okay";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/st/stih410.dtsi b/dts/upstream/src/arm/st/stih410.dtsi
index a69231854f7..d56343f44fd 100644
--- a/dts/upstream/src/arm/st/stih410.dtsi
+++ b/dts/upstream/src/arm/st/stih410.dtsi
@@ -285,5 +285,39 @@
 			resets = <&softreset STIH407_LPM_SOFTRESET>;
 			hdmi-phandle = <&sti_hdmi>;
 		};
+
+		gpu: gpu@9f00000 {
+			compatible = "st,stih410-mali", "arm,mali-400";
+			reg = <0x9f00000 0x10000>;
+			/* LIMA driver needs 2 clocks, use the same for both */
+			clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>,
+				 <&clk_s_c0_flexgen CLK_ICN_GPU>;
+			clock-names = "bus", "core";
+			assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
+			assigned-clock-rates = <400000000>;
+			resets = <&softreset STIH407_GPU_SOFTRESET>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gp",
+					  "gpmmu",
+					  "pp0",
+					  "ppmmu0",
+					  "pp1",
+					  "ppmmu1",
+					  "pp2",
+					  "ppmmu2",
+					  "pp3",
+					  "ppmmu3";
+
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/st/stm32mp131.dtsi b/dts/upstream/src/arm/st/stm32mp131.dtsi
index e1a764d269d..0019d12c3d3 100644
--- a/dts/upstream/src/arm/st/stm32mp131.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp131.dtsi
@@ -261,6 +261,11 @@
 			dma-names = "up";
 			status = "disabled";
 
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+
 			timer@5 {
 				compatible = "st,stm32h7-timer-trigger";
 				reg = <5>;
@@ -281,6 +286,11 @@
 			dma-names = "up";
 			status = "disabled";
 
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+
 			timer@6 {
 				compatible = "st,stm32h7-timer-trigger";
 				reg = <6>;
@@ -1196,6 +1206,11 @@
 				access-controllers = <&etzpc 23>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1221,6 +1236,11 @@
 				access-controllers = <&etzpc 24>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1246,6 +1266,11 @@
 				access-controllers = <&etzpc 25>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1276,6 +1301,11 @@
 				access-controllers = <&etzpc 26>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1304,6 +1334,11 @@
 				access-controllers = <&etzpc 27>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1332,6 +1367,11 @@
 				access-controllers = <&etzpc 28>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
diff --git a/dts/upstream/src/arm/st/stm32mp135f-dk.dts b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
index 3a276589fef..19a32f7d4d7 100644
--- a/dts/upstream/src/arm/st/stm32mp135f-dk.dts
+++ b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
@@ -440,6 +440,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */
 		pinctrl-0 = <&pwm3_pins_a>;
@@ -456,6 +459,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */
 		pinctrl-0 = <&pwm4_pins_a>;
@@ -472,6 +478,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */
 		pinctrl-0 = <&pwm8_pins_a>;
@@ -486,6 +495,9 @@
 
 &timers14 {
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */
 		pinctrl-0 = <&pwm14_pins_a>;
diff --git a/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
index 5edbc790d1d..6236ce2a696 100644
--- a/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
@@ -85,8 +85,8 @@
 
 			vddcpu: buck1 { /* VDD_CPU_1V2 */
 				regulator-name = "vddcpu";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
 				regulator-always-on;
 				regulator-initial-mode = <0>;
 				regulator-over-current-protection;
@@ -201,17 +201,17 @@
 		pagesize = <64>;
 	};
 
-	eeprom0wl: eeprom@58 {
-		compatible = "st,24256e-wl";	/* ST M24256E WL page of 0x50 */
-		pagesize = <64>;
-		reg = <0x58>;
-	};
-
 	rv3032: rtc@51 {
 		compatible = "microcrystal,rv3032";
 		reg = <0x51>;
 		interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
 	};
+
+	eeprom0wl: eeprom@58 {
+		compatible = "st,24256e-wl";	/* ST M24256E WL page of 0x50 */
+		pagesize = <64>;
+		reg = <0x58>;
+	};
 };
 
 &iwdg2 {
diff --git a/dts/upstream/src/arm/st/stm32mp151.dtsi b/dts/upstream/src/arm/st/stm32mp151.dtsi
index b28dc90926b..b9a87fbe971 100644
--- a/dts/upstream/src/arm/st/stm32mp151.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp151.dtsi
@@ -129,7 +129,7 @@
 			reg = <0x4c001000 0x400>;
 			st,proc-id = <0>;
 			interrupts-extended =
-				<&exti 61 1>,
+				<&exti 61 IRQ_TYPE_LEVEL_HIGH>,
 				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "rx", "tx";
 			clocks = <&rcc IPCC>;
@@ -578,6 +578,11 @@
 				access-controllers = <&etzpc 20>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				timer@5 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <5>;
@@ -599,6 +604,11 @@
 				access-controllers = <&etzpc 21>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				timer@6 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <6>;
@@ -618,6 +628,11 @@
 				access-controllers = <&etzpc 22>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -643,6 +658,11 @@
 				access-controllers = <&etzpc 23>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -668,6 +688,11 @@
 				access-controllers = <&etzpc 24>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1116,6 +1141,11 @@
 				access-controllers = <&etzpc 54>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1144,11 +1174,17 @@
 				access-controllers = <&etzpc 55>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
 					status = "disabled";
 				};
+
 				timer@15 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <15>;
@@ -1171,6 +1207,11 @@
 				access-controllers = <&etzpc 56>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
diff --git a/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts b/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts
new file mode 100644
index 00000000000..a40b0eae8da
--- /dev/null
+++ b/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc-lxa-tac.dtsi"
+
+/ {
+	model = "Linux Automation Test Automation Controller (TAC) Gen 3";
+	compatible = "lxa,stm32mp153c-tac-gen3", "oct,stm32mp153x-osd32", "st,stm32mp153";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&v3v3>;
+
+		brightness-levels = <0 31 63 95 127 159 191 223 255>;
+		default-brightness-level = <7>;
+		pwms = <&led_pwm 3 1000000 0>;
+	};
+
+	reg_iobus_12v: regulator-iobus-12v {
+		compatible = "regulator-fixed";
+		vin-supply = <&reg_12v>;
+		gpio = <&gpioh 13 GPIO_ACTIVE_LOW>;
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "12V_IOBUS";
+	};
+
+	led-controller-1 {
+		compatible = "pwm-leds-multicolor";
+
+		multi-led {
+			color = <LED_COLOR_ID_RGB>;
+			function = LED_FUNCTION_STATUS;
+			max-brightness = <65535>;
+
+			led-red {
+				active-low;
+				color = <LED_COLOR_ID_RED>;
+				pwms = <&led_pwm 0 1000000 0>;
+			};
+
+			led-green {
+				active-low;
+				color = <LED_COLOR_ID_GREEN>;
+				pwms = <&led_pwm 2 1000000 0>;
+			};
+
+			led-blue {
+				active-low;
+				color = <LED_COLOR_ID_BLUE>;
+				pwms = <&led_pwm 1 1000000 0>;
+			};
+		};
+	};
+
+	led-controller-2 {
+		compatible = "gpio-leds";
+
+		led-5 {
+			label = "tac:green:iobus";
+			gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-6 {
+			label = "tac:green:can";
+			gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-7 {
+			label = "tac:green:out0";
+			gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-8 {
+			label = "tac:green:out1";
+			gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-9 {
+			label = "tac:green:uarttx";
+			gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-10 {
+			label = "tac:green:uartrx";
+			gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-11 {
+			label = "tac:green:usbh1";
+			gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-12 {
+			label = "tac:green:usbh2";
+			gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-13 {
+			label = "tac:green:usbh3";
+			gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-14 {
+			label = "tac:green:usbg";
+			gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usb-gadget";
+		};
+
+		led-15 {
+			label = "tac:green:dutpwr";
+			gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&board_adc1_ain_pins>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <2 5 9 10 13 14 15 18>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@14 {
+			reg = <14>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+
+		channel@18 {
+			reg = <18>;
+			label = "HOST_2_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
+&gpioa {
+	gpio-line-names = "", "", "", "", "",              /*  0 */
+	"ETH_GPIO1", "ETH_INT", "", "", "",                /*  5 */
+	"", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP",        /* 10 */
+	"";                                                /* 15 */
+};
+
+&gpioc {
+	gpio-line-names = "", "DUT_PWR_DISCH", "", "", "", /*  0 */
+	"", "", "", "", "",                                /*  5 */
+	"", "";                                            /* 10 */
+};
+
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "DUT_PWR_EN", "UART_TX_EN",    /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"POWER_ADC_RESET", "", "", "", "",                           /* 10 */
+	"";                                                          /* 15 */
+};
+
+&m_can2 {
+	termination-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>;
+	termination-ohms = <120>;
+};
+
+&pinctrl {
+	board_adc1_ain_pins: board-adc1-ain-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
+				 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
+				 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
+				 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
+				 <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
+				 <STM32_PINMUX('A', 2, ANALOG)>, /* ADC1_INP14 */
+				 <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
+				 <STM32_PINMUX('A', 4, ANALOG)>; /* ADC1_INP18 */
+		};
+	};
+};
+
+&spi2 {
+	adc@0 {
+		compatible = "ti,lmp92064";
+		reg = <0>;
+
+		reset-gpios = <&gpiog 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		shunt-resistor-micro-ohms = <15000>;
+		spi-max-frequency = <5000000>;
+		vdd-supply = <&reg_pb_3v3>;
+		vdig-supply = <&reg_pb_3v3>;
+	};
+};
+
+&timers8 {
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
+
+	status = "okay";
+
+	led_pwm: pwm {
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pwm8_pins_b>;
+		pinctrl-1 = <&pwm8_sleep_pins_b>;
+		status = "okay";
+	};
+};
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
index 9eb9a1bf4f2..8f99c30f1af 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
@@ -306,6 +306,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm2_pins_a>;
 		pinctrl-1 = <&pwm2_sleep_pins_a>;
@@ -321,6 +324,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm8_pins_a>;
 		pinctrl-1 = <&pwm8_sleep_pins_a>;
@@ -336,6 +342,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm12_pins_a>;
 		pinctrl-1 = <&pwm12_sleep_pins_a>;
diff --git a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
index 81f254fb88b..e72e42eb0eb 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
@@ -35,6 +35,76 @@
 	};
 };
 
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_ain_pins_a>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <0 1 2 5 9 10 13 15>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@0 {
+			reg = <0>;
+			label = "HOST_2_CURR_FB";
+		};
+
+		channel@1 {
+			reg = <1>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
 &gpioa {
 	gpio-line-names = "", "", "STACK_CS2", "", "STACK_CS3", /*  0 */
 	"ETH_GPIO1", "ETH_INT", "", "", "",                     /*  5 */
@@ -48,6 +118,20 @@
 	"", "";                                        /* 10 */
 };
 
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"TP49", "", "", "", "",                                      /* 10 */
+	"";                                                          /* 15 */
+};
+
 &gpu {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
index 4cc17703166..2ae281725a4 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
@@ -121,6 +121,76 @@
 	};
 };
 
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_ain_pins_a>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <0 1 2 5 9 10 13 15>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@0 {
+			reg = <0>;
+			label = "HOST_2_CURR_FB";
+		};
+
+		channel@1 {
+			reg = <1>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
 &gpioa {
 	gpio-line-names = "", "", "DUT_PWR_EN", "", "STACK_CS3", /*  0 */
 	"ETH_GPIO1", "ETH_INT", "", "", "",                      /*  5 */
@@ -134,6 +204,20 @@
 	"", "";                                            /* 10 */
 };
 
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"TP49", "", "", "", "",                                      /* 10 */
+	"";                                                          /* 15 */
+};
+
 &gpu {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
index c87fd96cbd9..be0c355d310 100644
--- a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
@@ -16,12 +16,20 @@
 
 / {
 	aliases {
+		can0 = &m_can1;
+		can1 = &m_can2;
 		ethernet0 = &ethernet0;
 		ethernet1 = &port_uplink;
 		ethernet2 = &port_dut;
+		i2c0 = &i2c1;
+		i2c1 = &i2c4;
+		i2c2 = &i2c5;
 		mmc1 = &sdmmc2;
 		serial0 = &uart4;
 		serial1 = &usart3;
+		spi0 = &spi2;
+		spi1 = &spi4;
+		spi2 = &spi5;
 	};
 
 	chosen {
@@ -142,76 +150,6 @@
 baseboard_eeprom: &sip_eeprom {
 };
 
-&adc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc1_ain_pins_a>;
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vrefbuf>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,adc-channels = <0 1 2 5 9 10 13 15>;
-		st,min-sample-time-nsecs = <5000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		channel@0 {
-			reg = <0>;
-			label = "HOST_2_CURR_FB";
-		};
-
-		channel@1 {
-			reg = <1>;
-			label = "HOST_3_CURR_FB";
-		};
-
-		channel@2 {
-			reg = <2>;
-			label = "OUT_0_FB";
-		};
-
-		channel@5 {
-			reg = <5>;
-			label = "IOBUS_CURR_FB";
-		};
-
-		channel@9 {
-			reg = <9>;
-			label = "IOBUS_VOLT_FB";
-		};
-
-		channel@10 {
-			reg = <10>;
-			label = "OUT_1_FB";
-		};
-
-		channel@13 {
-			reg = <13>;
-			label = "HOST_CURR_FB";
-		};
-
-		channel@15 {
-			reg = <15>;
-			label = "HOST_1_CURR_FB";
-		};
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <12>;
-		st,min-sample-time-nsecs = <500000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		channel@12 {
-			reg = <12>;
-			label = "TEMP_INTERNAL";
-		};
-	};
-};
-
 &crc1 {
 	status = "okay";
 };
@@ -265,13 +203,6 @@ baseboard_eeprom: &sip_eeprom {
 	"ETH_LAB_LEDRN";                          /* 15 */
 };
 
-&gpioe {
-	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
-	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
-	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
-	"TP27";                                             /* 15 */
-};
-
 &gpiof {
 	gpio-line-names = "TP36", "TP37", "", "", "OLED_CS", /*  0 */
 	"", "", "", "", "",                                  /*  5 */
@@ -279,13 +210,6 @@ baseboard_eeprom: &sip_eeprom {
 	"";                                                  /* 15 */
 };
 
-&gpiog {
-	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
-	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
-	"TP49", "", "", "", "",                                      /* 10 */
-	"";                                                          /* 15 */
-};
-
 &gpioh {
 	gpio-line-names = "", "", "OUT_1", "OUT_0", "OLED_RESET", /*  0 */
 	"", "", "", "", "",                                       /*  5 */
@@ -379,10 +303,6 @@ baseboard_eeprom: &sip_eeprom {
 	};
 };
 
-&rtc {
-	status = "okay";
-};
-
 &sdmmc2 {
 	pinctrl-names = "default", "opendrain", "sleep";
 	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
@@ -576,6 +496,10 @@ baseboard_eeprom: &sip_eeprom {
 	vusb_d-supply = <&vdd_usb>;
 	vusb_a-supply = <&reg18>;
 
+	g-rx-fifo-size = <512>;
+	g-np-tx-fifo-size = <32>;
+	g-tx-fifo-size = <128 128 64 16 16 16 16 16>;
+
 	dr_mode = "peripheral";
 
 	status = "okay";
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
index bb4f8a0b937..abe2dfe7063 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
@@ -6,18 +6,6 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pwm/pwm.h>
 
-/ {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
 &adc {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
index 171d7c7658f..0fb4e55843b 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
@@ -7,16 +7,6 @@
 #include <dt-bindings/pwm/pwm.h>
 
 / {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	clk_ext_audio_codec: clock-codec {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
index b5bc53accd6..01c693cc034 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
@@ -7,16 +7,6 @@
 #include <dt-bindings/pwm/pwm.h>
 
 / {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	led {
 		compatible = "gpio-leds";
 
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
index 74a11ccc533..142d4a8731f 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
@@ -14,6 +14,13 @@
 		ethernet1 = &ksz8851;
 		rtc0 = &hwrtc;
 		rtc1 = &rtc;
+		serial0 = &uart4;
+		serial1 = &uart8;
+		serial2 = &usart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory@c0000000 {
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
index f7634c51efb..a5511b1f0ce 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
@@ -570,6 +570,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm1_pins_a>;
 		pinctrl-1 = <&pwm1_sleep_pins_a>;
@@ -585,6 +588,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm3_pins_a>;
 		pinctrl-1 = <&pwm3_sleep_pins_a>;
@@ -600,6 +606,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
 		pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
@@ -615,6 +624,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm5_pins_a>;
 		pinctrl-1 = <&pwm5_sleep_pins_a>;
@@ -630,6 +642,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	timer@5 {
 		status = "okay";
 	};
@@ -639,6 +654,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm12_pins_a>;
 		pinctrl-1 = <&pwm12_sleep_pins_a>;
diff --git a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
index 824b9415ebb..fd4634f8c62 100644
--- a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
+++ b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
@@ -180,8 +180,7 @@
 			      <0x9058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -698,8 +697,7 @@
 			      <0x22058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -726,8 +724,7 @@
 			      <0x24058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1385,8 +1382,7 @@
 			      <0xa6058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1413,8 +1409,7 @@
 			      <0xa8058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1441,8 +1436,7 @@
 			      <0xaa058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
diff --git a/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi b/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
index 6e67d99832a..ba7fdaae9c6 100644
--- a/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
+++ b/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
@@ -12,6 +12,7 @@
 	ranges = <0x00000000 0x4a000000 0x100000>,	/* segment 0 */
 		 <0x00100000 0x4a100000 0x100000>,	/* segment 1 */
 		 <0x00200000 0x4a200000 0x100000>;	/* segment 2 */
+	dma-ranges;
 
 	segment@0 {					/* 0x4a000000 */
 		compatible = "simple-pm-bus";
@@ -557,6 +558,7 @@
 			 <0x0007e000 0x0017e000 0x001000>,	/* ap 124 */
 			 <0x00059000 0x00159000 0x001000>,	/* ap 125 */
 			 <0x0005a000 0x0015a000 0x001000>;	/* ap 126 */
+		dma-ranges;
 
 		target-module@2000 {			/* 0x4a102000, ap 27 3c.0 */
 			compatible = "ti,sysc";
diff --git a/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi b/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
index 2ee3ddd6402..1b18ed8c1f7 100644
--- a/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
+++ b/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
@@ -446,6 +446,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <
 			&hsusb2_2_pins
+			&mcspi3hog_pins
 	>;
 
 	hsusb2_2_pins: hsusb2-2-pins {
@@ -459,6 +460,15 @@
 		>;
 	};
 
+	mcspi3hog_pins: mcspi3hog-pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25dc, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d0 */
+			OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d1 */
+			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d2 */
+			OMAP3630_CORE2_IOPAD(0x25e2, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d3 */
+		>;
+	};
+
 	spi_gpio_pins: spi-gpio-pinmux-pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
@@ -591,8 +601,10 @@
 		interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */
 		gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;	/* GPIO_160 */
 		ti,x-plate-ohms = <600>;
-		touchscreen-size-x = <480>;
-		touchscreen-size-y = <640>;
+		touchscreen-size-x = <0xf00>;
+		touchscreen-size-y = <0xf00>;
+		touchscreen-min-x = <0x100>;
+		touchscreen-min-y = <0x100>;
 		touchscreen-max-pressure = <1000>;
 		touchscreen-fuzz-x = <3>;
 		touchscreen-fuzz-y = <8>;
diff --git a/dts/upstream/src/arm64/airoha/en7581.dtsi b/dts/upstream/src/arm64/airoha/en7581.dtsi
index 55eb1762fb1..f584409e72c 100644
--- a/dts/upstream/src/arm64/airoha/en7581.dtsi
+++ b/dts/upstream/src/arm64/airoha/en7581.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/en7523-clk.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -142,6 +143,13 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		scuclk: clock-controller@1fa20000 {
+			compatible = "airoha,en7581-scu";
+			reg = <0x0 0x1fb00000 0x0 0x970>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		uart1: serial@1fbf0000 {
 			compatible = "ns16550";
 			reg = <0x0 0x1fbf0000 0x0 0x30>;
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
index 29ac7716c7a..a24adba201a 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,39 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0x3fffffff>;
 
+		syscon: syscon@3000000 {
+			compatible = "allwinner,sun50i-a100-system-control",
+				     "allwinner,sun50i-a64-system-control";
+			reg = <0x03000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_a1: sram@20000 {
+				compatible = "mmio-sram";
+				reg = <0x00020000 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00020000 0x4000>;
+			};
+
+			sram_c: sram@24000 {
+				compatible = "mmio-sram";
+				reg = <0x024000 0x21000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x024000 0x21000>;
+			};
+
+			sram_a2: sram@100000 {
+				compatible = "mmio-sram";
+				reg = <0x0100000 0x14000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x0100000 0x14000>;
+			};
+		};
+
 		ccu: clock@3001000 {
 			compatible = "allwinner,sun50i-a100-ccu";
 			reg = <0x03001000 0x1000>;
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
index 379c2c8466f..86d44349e09 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
@@ -390,6 +390,8 @@
 &tcon0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&lcd_rgb666_pins>;
+	assigned-clocks = <&ccu CLK_TCON0>;
+	assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
 
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
index b407e1dd08a..ec055510af8 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
@@ -369,6 +369,8 @@
 &tcon0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&lcd_rgb666_pins>;
+	assigned-clocks = <&ccu CLK_TCON0>;
+	assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
 
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
index a5c3920e0f0..0fecf0abb20 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
@@ -445,6 +445,8 @@
 			clock-names = "ahb", "tcon-ch0";
 			clock-output-names = "tcon-data-clock";
 			#clock-cells = <0>;
+			assigned-clocks = <&ccu CLK_TCON0>;
+			assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
 			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 			reset-names = "lcd", "lvds";
 
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts b/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
index bafd3e80310..17e6aef67aa 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "sun50i-h616.dtsi"
+#include "sun50i-h616-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
index 0d837d3e65a..34ccf8138f7 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
@@ -63,7 +63,6 @@
 	status = "okay";
 	phy-mode = "rgmii";
 	phy-addr = <0xffffffff>;
-	snps,max-mtu = <0x0>;
 };
 
 &gmac1 {
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
index 52d57773a77..1736bd2e96e 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
@@ -178,9 +178,8 @@
 	vmmc-supply = <&vddao_3v3>;
 	vqmmc-supply = <&vddio_boot>;
 
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
index c1470416faa..7dffeb5931c 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
@@ -102,8 +102,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
index 92c425d0259..ff9145d4909 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
@@ -21,8 +21,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
index 7e7dc87ede2..b52a830efcc 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
@@ -134,9 +134,8 @@
 	vmmc-supply = <&vddao_3v3>;
 	vqmmc-supply = <&vddio_boot>;
 
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
index d4858afa0e9..feb31207773 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
@@ -72,8 +72,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
index d02b80d7737..6c8bec1853a 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
@@ -21,8 +21,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts b/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 00000000000..7e3cef2ed35
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+
+/ {
+	model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+	compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	gpio_expander: gpio@74 {
+		compatible = "ti,tca9539";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "RSP_PIN_7",	/* GPIO_0 */
+				  "RSP_PIN_11",	/* GPIO_1 */
+				  "RSP_PIN_13",	/* GPIO_2 */
+				  "RSP_PIN_15",	/* GPIO_3 */
+				  "RSP_PIN_27",	/* GPIO_4 */
+				  "RSP_PIN_29",	/* GPIO_5 */
+				  "RSP_PIN_31",	/* GPIO_6 */
+				  "RSP_PIN_33",	/* GPIO_7 */
+				  "RSP_PIN_37",	/* GPIO_8 */
+				  "RSP_PIN_16",	/* GPIO_9 */
+				  "RSP_PIN_18",	/* GPIO_10 */
+				  "RSP_PIN_22",	/* GPIO_11 */
+				  "RSP_PIN_28",	/* GPIO_12 */
+				  "RSP_PIN_32",	/* GPIO_13 */
+				  "RSP_PIN_36",	/* GPIO_14 */
+				  "TP31";	/* GPIO_15 */
+	};
+
+	gpio_expander_m2: gpio@75 {
+		compatible = "ti,tca9539";
+		reg = <0x75>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "M2_W_DIS1_N",	/* GPIO_0 */
+				  "M2_W_DIS2_N",	/* GPIO_1 */
+				  "M2_UART_WAKE_N",	/* GPIO_2 */
+				  "M2_COEX3",		/* GPIO_3 */
+				  "M2_COEX_RXD",	/* GPIO_4 */
+				  "M2_COEX_TXD",	/* GPIO_5 */
+				  "M2_VENDOR_PIN40",	/* GPIO_6 */
+				  "M2_VENDOR_PIN42",	/* GPIO_7 */
+				  "M2_VENDOR_PIN38",	/* GPIO_8 */
+				  "M2_SDIO_RST_N",	/* GPIO_9 */
+				  "M2_SDIO_WAKE_N",	/* GPIO_10 */
+				  "M2_PETN1",		/* GPIO_11 */
+				  "M2_PERP1",		/* GPIO_12 */
+				  "M2_PERN1",		/* GPIO_13 */
+				  "UIM_SWP",		/* GPIO_14 */
+				  "UART1_TO_RSP";	/* GPIO_15 */
+	};
+};
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi b/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 00000000000..bfdff5953ed
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x1 0x0>;
+	};
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi b/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 00000000000..7d399e6a532
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	firmware {
+		scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82002000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			shmem = <&scmi0_shm>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_rst: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* SCMI reserved buffer space on DDR space */
+		scmi0_shm: scmi-shmem@800 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x800 0x0 0x80>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = /* Physical Secure PPI */
+			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Physical Non-Secure PPI */
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Hypervisor PPI */
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Virtual PPI */
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc@200000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x2 0x0 0x850000>;
+
+		gic: interrupt-controller@410000 {
+			compatible = "arm,gic-400";
+			reg = <0x410000 0x20000>,
+			      <0x420000 0x20000>,
+			      <0x440000 0x20000>,
+			      <0x460000 0x20000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+						 IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		uart0: serial@4d0000 {
+			compatible = "ns16550a";
+			reg = <0x4d0000 0x1000>;
+			clocks = <&scmi_clk 59>;
+			resets = <&scmi_rst 59>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@4e0000 {
+			compatible = "ns16550a";
+			reg = <0x4e0000 0x1000>;
+			clocks = <&scmi_clk 60>;
+			resets = <&scmi_rst 60>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@4f0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x4f0000 0x1000>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 54>;
+			resets = <&scmi_rst 54>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@500000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x500000 0x1000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 55>;
+			resets = <&scmi_rst 55>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@510000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x510000 0x1000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 56>;
+			resets = <&scmi_rst 56>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@520000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x520000 0x1000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 57>;
+			resets = <&scmi_rst 57>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@530000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x530000 0x1000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 58>;
+			resets = <&scmi_rst 58>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		arm_cc712: crypto@550000 {
+			compatible = "arm,cryptocell-712-ree";
+			reg = <0x550000 0x1000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 7>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts b/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts
new file mode 100644
index 00000000000..7de24d60bcd
--- /dev/null
+++ b/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "bcm2712-rpi-5-b.dts"
+
+&gio_aon {
+	brcm,gpio-bank-widths = <15 6>;
+
+	gpio-line-names =
+		"RP1_SDA", // AON_GPIO_00
+		"RP1_SCL", // AON_GPIO_01
+		"RP1_RUN", // AON_GPIO_02
+		"SD_IOVDD_SEL", // AON_GPIO_03
+		"SD_PWR_ON", // AON_GPIO_04
+		"SD_CDET_N", // AON_GPIO_05
+		"SD_FLG_N", // AON_GPIO_06
+		"", // AON_GPIO_07
+		"2712_WAKE", // AON_GPIO_08
+		"2712_STAT_LED", // AON_GPIO_09
+		"", // AON_GPIO_10
+		"", // AON_GPIO_11
+		"PMIC_INT", // AON_GPIO_12
+		"UART_TX_FS", // AON_GPIO_13
+		"UART_RX_FS", // AON_GPIO_14
+		"", // AON_GPIO_15
+		"", // AON_GPIO_16
+
+		// Pad bank0 out to 32 entries
+		"", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+
+		"HDMI0_SCL", // AON_SGPIO_00
+		"HDMI0_SDA", // AON_SGPIO_01
+		"HDMI1_SCL", // AON_SGPIO_02
+		"HDMI1_SDA", // AON_SGPIO_03
+		"PMIC_SCL", // AON_SGPIO_04
+		"PMIC_SDA"; // AON_SGPIO_05
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
index 2bdbb678024..fbc56309660 100644
--- a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
+++ b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
@@ -62,3 +62,45 @@
 	sd-uhs-ddr50;
 	sd-uhs-sdr104;
 };
+
+&soc {
+	firmware: firmware {
+		compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mboxes = <&mailbox>;
+		dma-ranges;
+
+		firmware_clocks: clocks {
+			compatible = "raspberrypi,firmware-clocks";
+			#clock-cells = <1>;
+		};
+
+		reset: reset {
+			compatible = "raspberrypi,firmware-reset";
+			#reset-cells = <1>;
+		};
+	};
+
+	power: power {
+		compatible = "raspberrypi,bcm2835-power";
+		firmware = <&firmware>;
+		#power-domain-cells = <1>;
+	};
+};
+
+&hvs {
+	clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
+	clock-names = "core", "disp";
+};
+
+&hdmi0 {
+	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+	clock-names = "hdmi", "bvb", "audio", "cec";
+};
+
+&hdmi1 {
+	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+	clock-names = "hdmi", "bvb", "audio", "cec";
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712.dtsi b/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
index 26a29e5e507..9e610a89a33 100644
--- a/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
+++ b/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
@@ -221,18 +221,13 @@
 			#mbox-cells = <0>;
 		};
 
-		local_intc: interrupt-controller@7cd00000 {
-			compatible = "brcm,bcm2836-l1-intc";
-			reg = <0x7cd00000 0x100>;
-		};
-
 		uart10: serial@7d001000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x7d001000 0x200>;
 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_uart>, <&clk_vpu>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -265,6 +260,172 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};
+
+		aon_intr: interrupt-controller@7d510600 {
+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+			reg = <0x7d510600 0x30>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		pixelvalve0: pixelvalve@7c410000 {
+			compatible = "brcm,bcm2712-pixelvalve0";
+			reg = <0x7c410000 0x100>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pixelvalve1: pixelvalve@7c411000 {
+			compatible = "brcm,bcm2712-pixelvalve1";
+			reg = <0x7c411000 0x100>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		mop: mop@7c500000 {
+			compatible = "brcm,bcm2712-mop";
+			reg = <0x7c500000 0x28>;
+			interrupt-parent = <&disp_intr>;
+			interrupts = <1>;
+		};
+
+		moplet: moplet@7c501000 {
+			compatible = "brcm,bcm2712-moplet";
+			reg = <0x7c501000 0x20>;
+			interrupt-parent = <&disp_intr>;
+			interrupts = <0>;
+		};
+
+		disp_intr: interrupt-controller@7c502000 {
+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+			reg = <0x7c502000 0x30>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		dvp: clock@7c700000 {
+			compatible = "brcm,brcm2711-dvp";
+			reg = <0x7c700000 0x10>;
+			clocks = <&clk_108MHz>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		ddc0: i2c@7d508200 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x7d508200 0x58>;
+			interrupt-parent = <&bsc_irq>;
+			interrupts = <1>;
+			clock-frequency = <97500>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ddc1: i2c@7d508280 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x7d508280 0x58>;
+			interrupt-parent = <&bsc_irq>;
+			interrupts = <2>;
+			clock-frequency = <97500>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		bsc_irq: interrupt-controller@7d508380 {
+			compatible = "brcm,bcm7271-l2-intc";
+			reg = <0x7d508380 0x10>;
+			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		main_irq: interrupt-controller@7d508400 {
+			compatible = "brcm,bcm7271-l2-intc";
+			reg = <0x7d508400 0x10>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		hdmi0: hdmi@7c701400 {
+			compatible = "brcm,bcm2712-hdmi0";
+			reg = <0x7c701400 0x300>,
+			      <0x7c701000 0x200>,
+			      <0x7c701d00 0x300>,
+			      <0x7c702000 0x80>,
+			      <0x7c703800 0x200>,
+			      <0x7c704000 0x800>,
+			      <0x7c700100 0x80>,
+			      <0x7d510800 0x100>,
+			      <0x7c720000 0x100>;
+			reg-names = "hdmi",
+				    "dvp",
+				    "phy",
+				    "rm",
+				    "packet",
+				    "metadata",
+				    "csc",
+				    "cec",
+				    "hd";
+			resets = <&dvp 1>;
+			interrupt-parent = <&aon_intr>;
+			interrupts = <1>, <2>, <3>,
+				     <7>, <8>;
+			interrupt-names = "cec-tx", "cec-rx", "cec-low",
+					  "hpd-connected", "hpd-removed";
+			ddc = <&ddc0>;
+		};
+
+		hdmi1: hdmi@7c706400 {
+			compatible = "brcm,bcm2712-hdmi1";
+			reg = <0x7c706400 0x300>,
+			      <0x7c706000 0x200>,
+			      <0x7c706d00 0x300>,
+			      <0x7c707000 0x80>,
+			      <0x7c708800 0x200>,
+			      <0x7c709000 0x800>,
+			      <0x7c700180 0x80>,
+			      <0x7d511000 0x100>,
+			      <0x7c720000 0x100>;
+			reg-names = "hdmi",
+				    "dvp",
+				    "phy",
+				    "rm",
+				    "packet",
+				    "metadata",
+				    "csc",
+				    "cec",
+				    "hd";
+			resets = <&dvp 2>;
+			interrupt-parent = <&aon_intr>;
+			interrupts = <11>, <12>, <13>,
+				     <14>, <15>;
+			interrupt-names = "cec-tx", "cec-rx", "cec-low",
+					  "hpd-connected", "hpd-removed";
+			ddc = <&ddc1>;
+		};
+	};
+
+	axi: axi {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x00 0x00000000  0x00 0x00000000  0x10 0x00000000>,
+			 <0x10 0x00000000  0x10 0x00000000  0x01 0x00000000>,
+			 <0x14 0x00000000  0x14 0x00000000  0x04 0x00000000>,
+			 <0x18 0x00000000  0x18 0x00000000  0x04 0x00000000>,
+			 <0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000>;
+
+		dma-ranges = <0x00 0x00000000  0x00 0x00000000  0x10 0x00000000>,
+			     <0x10 0x00000000  0x10 0x00000000  0x01 0x00000000>,
+			     <0x14 0x00000000  0x14 0x00000000  0x04 0x00000000>,
+			     <0x18 0x00000000  0x18 0x00000000  0x04 0x00000000>,
+			     <0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000>;
+
+		vc4: gpu {
+			compatible = "brcm,bcm2712-vc6";
+		};
 	};
 
 	timer {
@@ -280,4 +441,26 @@
 			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
 					  IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	clk_27MHz: clk-27M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+		clock-output-names = "27MHz-clock";
+	};
+
+	clk_108MHz: clk-108M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <108000000>;
+		clock-output-names = "108MHz-clock";
+	};
+
+	hvs: hvs@107c580000 {
+		compatible = "brcm,bcm2712-hvs";
+		reg = <0x10 0x7c580000 0x0 0x1a000>;
+		interrupt-parent = <&disp_intr>;
+		interrupts = <2>, <9>, <16>;
+		interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
+	};
 };
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
index 999d9373024..a5f9ec92bd5 100644
--- a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
@@ -144,16 +144,20 @@
 		#size-cells = <1>;
 
 		partition@0 {
-			compatible = "nvmem-cells";
 			label = "cferom";
 			reg = <0x0 0x100000>;
-
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 0x0 0x100000>;
 
-			base_mac_addr: mac@106a0 {
-				reg = <0x106a0 0x6>;
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				base_mac_addr: mac@106a0 {
+					reg = <0x106a0 0x6>;
+				};
 			};
 		};
 
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts
new file mode 100644
index 00000000000..54e453bd09f
--- /dev/null
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "bcm4906.dtsi"
+
+/ {
+	compatible = "zyxel,ex3510b", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
+	model = "Zyxel EX3510-B";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		key-wps {
+			label = "WPS";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+		};
+
+		key-reset {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&leds {
+	pinctrl-0 = <&pins_led_0_a>, <&pins_led_2_a>, <&pins_led_3_a>,
+		    <&pins_led_4_a>, <&pins_led_10_a>, <&pins_led_12_a>,
+		    <&pins_led_14_a>, <&pins_led_15_a>, <&pins_led_21_a>;
+	pinctrl-names = "default";
+
+	led@0 {
+		reg = <0x0>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@2 {
+		reg = <0x2>;
+		function = LED_FUNCTION_WAN_ONLINE;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@3 {
+		reg = <0x3>;
+		function = LED_FUNCTION_WAN_ONLINE;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@4 {
+		reg = <0x4>;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+		trigger-sources = <&ohci_port1>, <&ohci_port2>,
+				  <&ehci_port1>, <&ehci_port2>,
+				  <&xhci_port1>, <&xhci_port2>;
+		linux,default-trigger = "usbport";
+	};
+
+	led@a {
+		reg = <0xa>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+		linux,default-trigger = "default-on";
+	};
+
+	led@c {
+		reg = <0xc>;
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+
+	led@e {
+		reg = <0xe>;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+
+	led@f {
+		reg = <0xf>;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
+		active-low;
+	};
+
+	led@15 {
+		reg = <0x15>;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+};
+
+&enet {
+	nvmem-cells = <&base_mac_addr>;
+	nvmem-cell-names = "mac-address";
+};
+
+&usb_phy {
+	brcm,ioc = <1>;
+	brcm,ipp = <1>;
+	status = "okay";
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&xhci {
+	status = "okay";
+};
+
+&ports {
+	port@0 {
+		label = "lan1";
+	};
+
+	port@1 {
+		label = "lan2";
+	};
+
+	port@2 {
+		label = "lan3";
+	};
+
+	port@3 {
+		label = "lan4";
+	};
+
+	port@7 {
+		reg = <7>;
+		phy-mode = "internal";
+		phy-handle = <&phy12>;
+		label = "wan";
+	};
+};
+
+&nand_controller {
+	status = "okay";
+};
+
+&nandcs {
+	brcm,nand-oob-sector-size = <27>;
+	nand-ecc-strength = <8>;
+	nand-ecc-step-size = <512>;
+	nand-on-flash-bbt;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	partitions {
+		compatible = "brcm,bcm4908-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			compatible = "nvmem-cells";
+			label = "cferom";
+			reg = <0x0 0x100000>;
+			read-only;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			base_mac_addr: mac@106a0 {
+				reg = <0x106a0 0x6>;
+			};
+		};
+
+		partition@100000 {
+			compatible = "brcm,bcm4908-firmware";
+			reg = <0x100000 0x5f80000>;
+		};
+
+		partition@6080000 {
+			compatible = "brcm,bcm4908-firmware";
+			reg = <0x6080000 0x5f80000>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
index 8b924812322..613ba7ee43d 100644
--- a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
@@ -30,7 +30,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x0>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -39,7 +39,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x1>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -48,7 +48,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x2>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -57,7 +57,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x3>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -68,6 +68,16 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cfe-stub@0 {
+			reg = <0x0 0x0 0x0 0x1000>;
+		};
+	};
+
 	axi@81000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts b/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
index f43cfe66b6a..5939d342aec 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
@@ -137,7 +137,6 @@
 		spi-cpha;
 		spi-cpol;
 		pl022,interface = <0>;
-		pl022,slave-tx-disable = <0>;
 		pl022,com-mode = <0>;
 		pl022,rx-level-trig = <1>;
 		pl022,tx-level-trig = <1>;
@@ -200,7 +199,6 @@
 };
 
 &qspi {
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts b/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
index c50df1d0279..0e134a94e14 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
@@ -151,7 +151,6 @@
 		#size-cells = <1>;
 		compatible = "m25p80";
 		spi-max-frequency = <62500000>;
-		m25p,default-addr-width = <3>;
 		reg = <0x0 0x0>;
 
 		partition@0 {
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
index cfd9fd23a1c..5a4b81faff2 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
@@ -134,7 +134,6 @@
 		brcm,pcie-ob;
 		brcm,pcie-ob-oarr-size;
 		brcm,pcie-ob-axi-offset = <0x00000000>;
-		brcm,pcie-ob-window-size = <256>;
 
 		status = "disabled";
 
@@ -165,7 +164,6 @@
 		brcm,pcie-ob;
 		brcm,pcie-ob-oarr-size;
 		brcm,pcie-ob-axi-offset = <0x30000000>;
-		brcm,pcie-ob-window-size = <256>;
 
 		status = "disabled";
 
diff --git a/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts b/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
index f074df8982b..7d70a32e75b 100644
--- a/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
+++ b/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
@@ -45,17 +45,9 @@
 		};
 	};
 
-	/*
-	 * RAM: 4 GiB (eMCP):
-	 *   - 2 GiB at 0x80000000
-	 *   - 2 GiB at 0x880000000
-	 *
-	 * 0xbab00000..0xbfffffff: secure memory (85 MiB).
-	 */
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x0 0x80000000 0x3ab00000>,
-		      <0x0 0xc0000000 0x40000000>,
+		reg = <0x0 0x80000000 0x80000000>,
 		      <0x8 0x80000000 0x80000000>;
 	};
 
@@ -146,6 +138,11 @@
 		#size-cells = <1>;
 		ranges;
 
+		secure_mem: memory@bab00000 {
+			reg = <0x0 0xbab00000 0x5500000>;
+			no-map;
+		};
+
 		ramoops@f0000000 {
 			compatible = "ramoops";
 			reg = <0x0 0xf0000000 0x200000>;
diff --git a/dts/upstream/src/arm64/exynos/exynos8895.dtsi b/dts/upstream/src/arm64/exynos/exynos8895.dtsi
index 9f9ac535987..36657abfc61 100644
--- a/dts/upstream/src/arm64/exynos/exynos8895.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos8895.dtsi
@@ -38,7 +38,17 @@
 				     <&cpu3>;
 	};
 
-	/* There's no PMU model for the Mongoose cores */
+	mongoose-m2-pmu {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu4>,
+				     <&cpu5>,
+				     <&cpu6>,
+				     <&cpu7>;
+	};
 
 	cpus {
 		#address-cells = <1>;
@@ -218,6 +228,19 @@
 				      "usi1", "usi2", "usi3";
 		};
 
+		serial_0: serial@10430000 {
+			compatible = "samsung,exynos8895-uart";
+			reg = <0x10430000 0x100>;
+			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
+				 <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_bus>;
+			samsung,uart-fifosize = <256>;
+			status = "disabled";
+		};
+
 		pinctrl_peric0: pinctrl@104d0000 {
 			compatible = "samsung,exynos8895-pinctrl";
 			reg = <0x104d0000 0x1000>;
@@ -250,12 +273,69 @@
 				      "usi10", "usi11", "usi12", "usi13";
 		};
 
+		serial_1: serial@10830000 {
+			compatible = "samsung,exynos8895-uart";
+			reg = <0x10830000 0x100>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>,
+				 <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart1_bus>;
+			samsung,uart-fifosize = <256>;
+			status = "disabled";
+		};
+
 		pinctrl_peric1: pinctrl@10980000 {
 			compatible = "samsung,exynos8895-pinctrl";
 			reg = <0x10980000 0x1000>;
 			interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		hsi2c_1: i2c@10990000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x10990000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c1_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_2: i2c@109a0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109a0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c2_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_3: i2c@109b0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109b0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c3_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_4: i2c@109c0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109c0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c4_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
 		spi_0: spi@109d0000 {
 			compatible = "samsung,exynos8895-spi",
 				     "samsung,exynos850-spi";
diff --git a/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi b/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi
new file mode 100644
index 00000000000..88091bf09e4
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+	etc1: etc1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa2: gpa2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa3: gpa3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa4: gpa4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpq0: gpq0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_aud {
+	gpb0: gpb0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb1: gpb1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb2: gpb2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_chub {
+	gph0: gph0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_cmgp {
+	gpm0: gpm0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm1: gpm1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm2: gpm2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm3: gpm3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm4: gpm4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm5: gpm5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm6: gpm6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm7: gpm7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm10: gpm10-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm11: gpm11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm12: gpm12-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm13: gpm13-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm14: gpm14-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm15: gpm15-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm16: gpm16-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm17: gpm17-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm40: gpm40-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm41: gpm41-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm42: gpm42-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm43: gpm43-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pinctrl_fsys0 {
+	gpf0: gpf0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_fsys1 {
+	gpf1: gpf1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf2: gpf2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_peric0 {
+	gpg0: gpg0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp0: gpp0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp1: gpp1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp2: gpp2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp3: gpp3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_peric1 {
+	gpc0: gpc0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc1: gpc1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpd0: gpd0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg3: gpg3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp4: gpp4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp5: gpp5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp6: gpp6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_vts {
+	gpt0: gpt0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts b/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts
new file mode 100644
index 00000000000..fc0ddfee4cd
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S9 (starlte/SM-G960F) device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+/dts-v1/;
+#include "exynos9810.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Samsung Galaxy S9 (SM-G960F)";
+	compatible = "samsung,starlte", "samsung,exynos9810";
+	chassis-type = "handset";
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@cc000000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
+			width = <1440>;
+			height = <2960>;
+			stride = <(1440 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup &key_wink>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+
+		/* In stock firmware used for assistant. Map it as a camera button for now */
+		wink-key {
+			label = "Camera";
+			linux,code = <KEY_CAMERA>;
+			gpios = <&gpa0 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x3c800000>,
+		      <0x0 0xc0000000 0x20000000>,
+		      <0x0 0xe1900000 0x1e700000>,
+		      <0x8 0x80000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@cc000000 {
+			reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
+			no-map;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_wink: key-wink-pins {
+		samsung,pins = "gpa0-6";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos9810.dtsi b/dts/upstream/src/arm64/exynos/exynos9810.dtsi
new file mode 100644
index 00000000000..01eba31f7ca
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810.dtsi
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Exynos 9810 SoC device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "samsung,exynos9810";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_alive;
+		pinctrl1 = &pinctrl_aud;
+		pinctrl2 = &pinctrl_chub;
+		pinctrl3 = &pinctrl_cmgp;
+		pinctrl4 = &pinctrl_fsys0;
+		pinctrl5 = &pinctrl_fsys1;
+		pinctrl6 = &pinctrl_peric0;
+		pinctrl7 = &pinctrl_peric1;
+		pinctrl8 = &pinctrl_vts;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x3>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@100 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@101 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x101>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@102 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x102>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@103 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	oscclk: osc-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "oscclk";
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
+	};
+
+	pmu-mongoose-m3 {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu4>,
+				     <&cpu5>,
+				     <&cpu6>,
+				     <&cpu7>;
+	};
+
+	psci {
+		compatible = "arm,psci";
+		method = "smc";
+		cpu_off = <0x84000002>;
+		cpu_on = <0xc4000003>;
+		cpu_suspend = <0xc4000001>;
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0x0 0x0 0x0 0x20000000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		chipid@10000000 {
+			compatible = "samsung,exynos9810-chipid",
+				     "samsung,exynos850-chipid";
+			reg = <0x10000000 0x100>;
+		};
+
+		gic: interrupt-controller@10101000 {
+			compatible = "arm,gic-400";
+			reg = <0x10101000 0x1000>,
+			      <0x10102000 0x1000>,
+			      <0x10104000 0x2000>,
+			      <0x10106000 0x2000>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+						 IRQ_TYPE_LEVEL_HIGH)>;
+			#address-cells = <0>;
+			#size-cells = <1>;
+		};
+
+		pinctrl_peric0: pinctrl@10430000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x10430000 0x1000>;
+			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_peric1: pinctrl@10830000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x10830000 0x1000>;
+			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_fsys0: pinctrl@11050000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x11050000 0x1000>;
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_fsys1: pinctrl@11430000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x11430000 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_vts: pinctrl@13880000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x13880000 0x1000>;
+		};
+
+		pinctrl_chub: pinctrl@13a80000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x13a80000 0x1000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_alive: pinctrl@14050000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x14050000 0x1000>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos9810-wakeup-eint",
+					     "samsung,exynos850-wakeup-eint",
+					     "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pmu_system_controller: system-controller@14060000 {
+			compatible = "samsung,exynos9810-pmu",
+				     "samsung,exynos7-pmu", "syscon";
+			reg = <0x14060000 0x10000>;
+		};
+
+		pinctrl_cmgp: pinctrl@14220000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x14220000 0x1000>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos9810-wakeup-eint",
+					     "samsung,exynos850-wakeup-eint",
+					     "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pinctrl_aud: pinctrl@17c60000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x17c60000 0x1000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		/*
+		 * Non-updatable, broken stock Samsung bootloader does not
+		 * configure CNTFRQ_EL0
+		 */
+		clock-frequency = <26000000>;
+	};
+};
+
+#include "exynos9810-pinctrl.dtsi"
+#include "arm/samsung/exynos-syscon-restart.dtsi"
diff --git a/dts/upstream/src/arm64/exynos/exynos990-r8s.dts b/dts/upstream/src/arm64/exynos/exynos990-r8s.dts
new file mode 100644
index 00000000000..6bae3c0ecc1
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-r8s.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 FE (r8s/SM-G780F) device tree source
+ *
+ * Copyright (c) 2024, Denzeel Oliva <wachiturroxd150@gmail.com>
+ */
+
+/dts-v1/;
+#include "exynos990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Samsung Galaxy S20 FE";
+	compatible = "samsung,r8s", "samsung,exynos990";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@f1000000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0xf1000000 0 (1080 * 2400 * 4)>;
+			width = <1080>;
+			height = <2400>;
+			stride = <(1080 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole - last block */
+		      <0x8 0x80000000 0x0 0xc0000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cont_splash_mem: framebuffer@f1000000 {
+			reg = <0 0xf1000000 0 0x13c6800>;
+			no-map;
+		};
+
+		abox_reserved: audio@f7fb0000 {
+			reg = <0 0xf7fb0000 0 0x2a50000>;
+			no-map;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi b/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi
new file mode 100644
index 00000000000..55fa8e9e05d
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 Series device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@f1000000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0xf1000000 0 (1440 * 3200 * 4)>;
+			width = <1440>;
+			height = <3200>;
+			stride = <(1440 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cont_splash_mem: framebuffer@f1000000 {
+			reg = <0 0xf1000000 0 0x1194000>;
+			no-map;
+		};
+
+		abox_reserved: audio@f7fb0000 {
+			reg = <0 0xf7fb0000 0 0x2a50000>;
+			no-map;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1s.dts b/dts/upstream/src/arm64/exynos/exynos990-x1s.dts
new file mode 100644
index 00000000000..1ae881015e0
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1s.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990-x1s-common.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	model = "Samsung Galaxy S20 5G";
+	compatible = "samsung,x1s", "samsung,exynos990";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole */
+		      <0x8 0x80000000 0x2 0x7e800000>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts b/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts
new file mode 100644
index 00000000000..d3720996ba9
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 (x1slte/SM-G980F) device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990-x1s-common.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	model = "Samsung Galaxy S20";
+	compatible = "samsung,x1slte", "samsung,exynos990";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole */
+		      <0x8 0x80000000 0x1 0x7ec00000>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990.dtsi b/dts/upstream/src/arm64/exynos/exynos990.dtsi
index c1986f00e44..9d017dbed95 100644
--- a/dts/upstream/src/arm64/exynos/exynos990.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos990.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
  */
 
+#include <dt-bindings/clock/samsung,exynos990.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -46,7 +47,14 @@
 				     <&cpu5>;
 	};
 
-	/* There's no PMU model for cluster2, which are the Mongoose cores. */
+	mongoose-m5-pmu {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-affinity = <&cpu6>,
+				     <&cpu7>;
+	};
 
 	cpus {
 		#address-cells = <1>;
@@ -199,6 +207,23 @@
 			interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_hsi0: clock-controller@10a00000 {
+			compatible = "samsung,exynos990-cmu-hsi0";
+			reg = <0x10a00000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
+			clock-names = "oscclk",
+				      "bus",
+				      "usb31drd",
+				      "usbdp_debug",
+				      "dpgtc";
+		};
+
 		pinctrl_hsi1: pinctrl@13040000 {
 			compatible = "samsung,exynos990-pinctrl";
 			reg = <0x13040000 0x1000>;
@@ -227,10 +252,33 @@
 			};
 		};
 
+		pmu_system_controller: system-controller@15860000 {
+			compatible = "samsung,exynos990-pmu",
+				     "samsung,exynos7-pmu", "syscon";
+			reg = <0x15860000 0x10000>;
+
+			reboot: syscon-reboot {
+				compatible = "syscon-reboot";
+				regmap = <&pmu_system_controller>;
+				offset = <0x3a00>; /* SWRESET */
+				mask = <0x2>; /* SWRESET_TRIGGER */
+				value = <0x2>;
+			};
+		};
+
 		pinctrl_cmgp: pinctrl@15c30000 {
 			compatible = "samsung,exynos990-pinctrl";
 			reg = <0x15c30000 0x1000>;
 		};
+
+		cmu_top: clock-controller@1a330000 {
+			compatible = "samsung,exynos990-cmu-top";
+			reg = <0x1a330000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>;
+			clock-names = "oscclk";
+		};
 	};
 
 	timer {
diff --git a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
index c759134c909..eb446cdc4ab 100644
--- a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
@@ -183,6 +183,26 @@
 				      "noc";
 		};
 
+		watchdog_cl0: watchdog@10060000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10060000 0x100>;
+			interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <0>;
+		};
+
+		watchdog_cl1: watchdog@10070000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10070000 0x100>;
+			interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <1>;
+		};
+
 		gic: interrupt-controller@10400000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
@@ -193,6 +213,69 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		spdma0: dma-controller@10180000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10180000 0x1000>;
+			interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		spdma1: dma-controller@10190000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10190000 0x1000>;
+			interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma0: dma-controller@101a0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101a0000 0x1000>;
+			interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma1: dma-controller@101b0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101b0000 0x1000>;
+			interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma2: dma-controller@101c0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101c0000 0x1000>;
+			interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma3: dma-controller@101d0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101d0000 0x1000>;
+			interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma4: dma-controller@101e0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101e0000 0x1000>;
+			interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
 		cmu_peric0: clock-controller@10800000 {
 			compatible = "samsung,exynosautov920-cmu-peric0";
 			reg = <0x10800000 0x8000>;
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
index 387fb779bd2..e58881c61d5 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
+++ b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/usb/pd.h>
 #include "gs101-pinctrl.h"
 #include "gs101.dtsi"
 
@@ -90,6 +91,89 @@
 &hsi2c_12 {
 	status = "okay";
 	/* TODO: add the devices once drivers exist */
+
+	usb-typec@25 {
+		compatible = "maxim,max77759-tcpci", "maxim,max33359";
+		reg = <0x25>;
+		interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&typec_int>;
+		pinctrl-names = "default";
+
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			self-powered;
+			try-power-role = "sink";
+			op-sink-microwatt = <2600000>;
+			slow-charger-loop;
+			/*
+			 * max77759 operating in reverse boost mode (0xA) can
+			 * source up to 1.5A while extboost can only do ~1A.
+			 * Since extboost is the primary path, advertise 900mA.
+			 */
+			source-pdos = <PDO_FIXED(5000, 900,
+						 (PDO_FIXED_SUSPEND
+						  | PDO_FIXED_USB_COMM
+						  | PDO_FIXED_DATA_SWAP
+						  | PDO_FIXED_DUAL_ROLE))>;
+			sink-pdos = <PDO_FIXED(5000, 3000,
+					       (PDO_FIXED_DATA_SWAP
+						| PDO_FIXED_USB_COMM
+						| PDO_FIXED_HIGHER_CAP
+						| PDO_FIXED_DUAL_ROLE))
+				     PDO_FIXED(9000, 2200, 0)
+				     PDO_PPS_APDO(5000, 11000, 3000)>;
+			sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
+					     IDH_PTYPE_DFP_HOST, 2, 0x18d1)
+				     VDO_CERT(0x0)
+				     VDO_PRODUCT(0x4ee1, 0x0)
+				     VDO_UFP(UFP_VDO_VER1_2,
+					     (DEV_USB2_CAPABLE
+					      | DEV_USB3_CAPABLE),
+					     UFP_RECEPTACLE, 0,
+					     AMA_VCONN_NOT_REQ, 0,
+					     UFP_ALTMODE_NOT_SUPP,
+					     UFP_USB32_GEN1)
+				     /* padding */ 0
+				     VDO_DFP(DFP_VDO_VER1_1,
+					     (HOST_USB2_CAPABLE
+					      | HOST_USB3_CAPABLE),
+					     DFP_RECEPTACLE, 0)>;
+			sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
+						0, 0, 0x18d1)
+					VDO_CERT(0x0)
+					VDO_PRODUCT(0x4ee1, 0x0)>;
+			/*
+			 * Until bootloader is updated to set those two when
+			 * console is enabled, we disable PD here.
+			 */
+			pd-disable;
+			typec-power-opmode = "default";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdrd31_phy_orien_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&usbdrd31_dwc3_role_switch>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &pinctrl_far_alive {
@@ -106,6 +190,13 @@
 		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
 		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
 	};
+
+	typec_int: typec-int-pins {
+		samsung,pins = "gpa8-2";
+		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+		samsung,pin-pud = <GS101_PIN_PULL_UP>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
 };
 
 &pinctrl_gpio_alive {
@@ -142,9 +233,16 @@
 	role-switch-default-mode = "peripheral";
 	maximum-speed = "super-speed-plus";
 	status = "okay";
+
+	port {
+		usbdrd31_dwc3_role_switch: endpoint {
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd31_phy {
+	orientation-switch;
 	/* TODO: Update these once PMIC is implemented */
 	pll-supply = <&reg_placeholder>;
 	dvdd-usb20-supply = <&reg_placeholder>;
@@ -153,6 +251,12 @@
 	vdda-usbdp-supply = <&reg_placeholder>;
 	vddh-usbdp-supply = <&reg_placeholder>;
 	status = "okay";
+
+	port {
+		usbdrd31_phy_orien_switch: endpoint {
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &usi_uart {
diff --git a/dts/upstream/src/arm64/exynos/google/gs101.dtsi b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
index 302c5beb224..c5335dd59df 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101.dtsi
+++ b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
@@ -1267,7 +1267,7 @@
 
 		usbdrd31_phy: phy@11100000 {
 			compatible = "google,gs101-usb31drd-phy";
-			reg = <0x11100000 0x0100>,
+			reg = <0x11100000 0x0200>,
 			      <0x110f0000 0x0800>,
 			      <0x110e0000 0x2800>;
 			reg-names = "phy", "pcs", "pma";
@@ -1302,6 +1302,9 @@
 				interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
 				phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,has-lpm-erratum;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
 				status = "disabled";
 			};
 		};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phg.dts b/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
index 75bbedc6164..a134b183364 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
@@ -82,7 +82,7 @@
 	};
 
 	panel {
-		compatible = "panel-lvds";
+		compatible = "auo,g084sn05", "panel-lvds";
 		width-mm = <170>;
 		height-mm = <28>;
 		data-mapping = "jeida-18";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
index ce20de25980..3d0b1496813 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
@@ -16,10 +16,10 @@
 			"Headphone Jack", "HPOUTR",
 			"IN2L", "Line In Jack",
 			"IN2R", "Line In Jack",
-			"Headphone Jack", "MICBIAS",
-			"IN1L", "Headphone Jack";
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack";
 		simple-audio-card,widgets =
-			"Microphone", "Headphone Jack",
+			"Microphone", "Microphone Jack",
 			"Headphone", "Headphone Jack",
 			"Line", "Line In Jack";
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
index 7675583a6b6..98dec3c4206 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
@@ -4,6 +4,34 @@
  */
 
 / {
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer-panel0 {
+			compatible = "simple-framebuffer";
+			clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, /* lcdif */
+				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+				 <&clk IMX8MN_VIDEO_PLL1>,
+				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, /* pgc_dispmix */
+				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+				 <&clk IMX8MN_CLK_DISP_AXI>,
+				 <&clk IMX8MN_CLK_DISP_APB>,
+				 <&clk IMX8MN_SYS_PLL2_1000M>,
+				 <&clk IMX8MN_SYS_PLL1_800M>,
+				 <&clk IMX8MN_CLK_DSI_CORE>, /* mipi_disi */
+				 <&clk IMX8MN_CLK_DSI_PHY_REF>;
+
+			power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>,
+					<&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+			dvdd-supply = <&reg_3v3_dvdd>;
+			avdd-supply = <&reg_v3v3_avdd>;
+			status = "disabled";
+		};
+	};
+
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 700000 0>;	/* 700000 ns = 1337Hz */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts
new file mode 100644
index 00000000000..6a688510dad
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 ADLink PI SMARC carrier";
+	compatible = "abb,imx8mp-aristanetos3-adpismarc",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+};
+
+&flexcan1 {
+	status = "okay";
+};
+
+&i2c2 {
+	gpio8: pinctrl@3e {
+		compatible = "semtech,sx1509q";
+		reg = <0x3e>;
+
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio6>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso
new file mode 100644
index 00000000000..9d1f3b4ccc7
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	model = "Aristainetos3 helios carrier with LVDS";
+	compatible = "abb,imx8mp-aristanetos3-helios",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	panel_lvds: panel-lvds {
+		compatible = "lg,lb070wv8";
+		power-supply = <&reg_vcc_disp>;
+		backlight = <&lvds_backlight>;
+
+		port {
+			in_lvds0: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+
+	reg_vcc_disp: regulator-disp {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_vcc_en>;
+		compatible = "regulator-fixed";
+		regulator-name = "disp_power_en_2v8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&gpio3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+	lvdssel-hog {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "LVDSSEL";
+	};
+};
+
+&hdmi_blk_ctrl {
+	status = "disabled";
+};
+
+&hdmi_pvi {
+	status = "disabled";
+};
+
+&hdmi_tx {
+	status = "disabled";
+};
+
+&hdmi_tx_phy {
+	status = "disabled";
+};
+
+&irqsteer_hdmi {
+	status = "disabled";
+};
+
+&ldb_lvds_ch0 {
+	remote-endpoint = <&in_lvds0>;
+};
+
+&lcdif1 {
+	status = "disabled";
+};
+
+&lcdif2 {
+	status = "okay";
+};
+
+&lcdif3 {
+	status = "disabled";
+};
+
+&lvds_backlight {
+	status = "okay";
+};
+
+&lvds_bridge {
+	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
+	assigned-clock-rates = <232820000>;
+	status = "okay";
+};
+
+&media_blk_ctrl {
+	/*
+	 * currently it is not possible to let display clocks configure
+	 * automatically, so we need to set them manually
+	 */
+	assigned-clock-rates = <500000000>, <200000000>, <0>,
+		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
+		<33260000>, <0>,
+		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
+		<465640000>;
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts
new file mode 100644
index 00000000000..a4e649a8239
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 helios carrier";
+	compatible = "abb,imx8mp-aristanetos3-helios",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	led-controller {
+		compatible = "gpio-leds";
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 12 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-2 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 14 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-3 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 15 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&ethphy1 {
+	status = "disabled";
+};
+
+&fec {
+	status = "disabled";
+};
+
+&i2c1 {
+	eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+	};
+};
+
+&i2c3 {
+	pca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "DIN0_CON",
+			"DIN1_CON",
+			"DIN2_CON",
+			"DIN3_CON",
+			"DIN4_CON",
+			"DIN5_CON",
+			"DIN6_CON",
+			"DIN7_CON",
+			"PM102_RES",
+			"COMx_RES",
+			"BPL_RES",
+			"PC_RES",
+			"LED_RED",
+			"LED_YELLOW",
+			"LED_GREEN",
+			"LED_BLUE";
+	};
+
+	rtc@68 {
+		compatible = "st,m41t00";
+		reg = <0x68>;
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts
new file mode 100644
index 00000000000..2a736dbe96b
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 proton2s carrier";
+	compatible = "abb,imx8mp-aristanetos3-proton2s",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	watchdog {
+		/* MAX6371KA */
+		compatible = "linux,wdt-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_watchdog_gpio>;
+		always-running;
+		gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		hw_algo = "level";
+		/* Reset triggers in 3..9 seconds */
+		hw_margin_ms = <1500>;
+	};
+};
+
+&ethphy1 {
+	status = "disabled";
+};
+
+&eqos {
+	max-speed = <100>;
+};
+
+&ecspi1{
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+};
+
+&fec {
+	status = "disabled";
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_proton2s>;
+
+	gpio-line-names =
+		"", "", "", "", "", "", "", "POWER",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"RELAY0", "RELAY1", "RELAY2", "HEATER",
+		"FAN", "SPARE",	"CLEAR", "FAULT",
+		"", "", "", "", "", "", "", "", "";
+};
+
+&i2c2 {
+	tlc59108@40 {
+		compatible = "ti,tlc59108";
+		reg = <0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0x0>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <20>;
+		};
+
+		led@1 {
+			reg = <0x1>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <20>;
+		};
+
+		led@2 {
+			reg = <0x2>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <21>;
+		};
+
+		led@3 {
+			reg = <0x3>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <21>;
+		};
+
+		led@4 {
+			reg = <0x4>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <21>;
+		};
+
+		led@5 {
+			reg = <0x5>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <22>;
+		};
+
+		led@6 {
+			reg = <0x6>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <22>;
+		};
+
+		led@7 {
+			reg = <0x7>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <22>;
+		};
+	};
+
+	rtc1: rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart2 {
+	pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&uart3 {
+	pinctrl-0 = <&pinctrl_uart3>;
+};
+
+&uart4 {
+	linux,rs485-enabled-at-boot-time;
+	rs485-rts-active-low;
+	rs485-rts-delay = <0 0>;
+	rts-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usdhc1 {
+	status = "disabled";
+};
+
+&wdog1 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi
new file mode 100644
index 00000000000..231e480acfd
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx8mp.dtsi"
+
+/ {
+	model = "ADLINK LEC-iMX8MP-Q-N-4G-32G";
+	compatible = "abb,imx8mp-aristanetos3-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+		mmc0 = &usdhc3;	/* eMMC */
+		mmc1 = &usdhc2;	/* MicroSD */
+	};
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	connector {
+		compatible = "usb-c-connector";
+		label = "USB-C";
+
+		port {
+			usb_dr_connector: endpoint {
+				remote-endpoint = <&usb3_dwc>;
+			};
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
+			function-enumerator = <0>;
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	lvds_backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_bklt_en>;
+		pwms = <&pwm2 0 50000 0>;
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <0 100>;
+		num-interpolated-steps = <100>;
+		default-brightness-level = <80>;
+		status = "disabled";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
+		reg = <0x0 0x40000000 0 0x08000000>;
+	};
+
+	pcie0_refclk: clock-pcie-ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_can1_stby: regulator-can1-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan1_reg>;
+		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can1-stby";
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan2_reg>;
+		enable-active-high;
+		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can2-stby";
+	};
+
+	reg_dp83867_2v5: regulator-enet {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "enet_2v5";
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_usb1_host_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_vbus>;
+		enable-active-high;
+		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb1_host_vbus";
+		regulator-always-on;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+		enable-active-high;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VDD_3V3_SD";
+		off-on-delay-us = <12000>;
+		startup-delay-us = <100>;
+		vin-supply = <&buck4>;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&clk {
+	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+		 <&clk_ext3>, <&clk_ext4>;
+	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+		      "clk_ext3", "clk_ext4";
+	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+			  <&clk IMX8MP_CLK_A53_CORE>,
+			  <&clk IMX8MP_CLK_NOC>,
+			  <&clk IMX8MP_CLK_NOC_IO>,
+			  <&clk IMX8MP_CLK_GIC>,
+			  <&clk IMX8MP_CLK_AUDIO_AHB>,
+			  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
+			  <&clk IMX8MP_AUDIO_PLL1>,
+			  <&clk IMX8MP_AUDIO_PLL2>,
+			  <&clk IMX8MP_VIDEO_PLL1>;
+};
+
+&ecspi1{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* eth0 */
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos_rgmii>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	snps,force_thresh_dma_mode;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: eqos-ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,min-output-impedance;
+			ti,dp83867-rxctrl-strap-quirk;
+			interrupt-parent = <&gpio4>;
+			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <5>;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <5>;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+			snps,map-to-dma-channel = <0>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+			snps,map-to-dma-channel = <1>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+			snps,map-to-dma-channel = <2>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+			snps,map-to-dma-channel = <3>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+			snps,map-to-dma-channel = <4>;
+		};
+	};
+};
+
+/* eth1 */
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec_rgmii>;
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpio = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,min-output-impedance;
+			ti,dp83867-rxctrl-strap-quirk;
+			eee-broken-1000t;
+		};
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "disabled";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "disabled";
+};
+
+&hdmi_blk_ctrl {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		/*
+		 * i.MX 8M Plus Data Sheet for Consumer Products
+		 * 3.1.4 Operating ranges
+		 * MIMX8ML8CVNKZAB
+		 */
+		regulators {
+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
+				regulator-name = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck2: BUCK2 {	/* VDD_ARM */
+				regulator-name = "buck2";
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck4: BUCK4 {	/* VDD_3V3 */
+				regulator-name = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck5: BUCK5 {	/* VDD_1V8 */
+				regulator-name = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
+				regulator-name = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo2: LDO2 {	/* VDDA_1V8 */
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo3: LDO3 {	/* VDDA_1V8 */
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo4: LDO4 {	/* PMIC_LDO4 */
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo5: LDO5 {	/* NVCC_SD2 */
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c5 {
+	#address-cells = <1>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c5>;
+	status = "okay";
+};
+
+&i2c6 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c6>;
+	pinctrl-1 = <&pinctrl_i2c6_gpio>;
+	scl-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	/* TPM - ST33TPHF2XI2C U2301 */
+	tpm: tpm@2e {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tpm_irq>;
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+
+		label = "tpm";
+		interrupt-parent = <&gpio3>;
+		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+		status = "okay";
+	};
+
+	/* SX1509(0) U2605 */
+	gpio6: pinctrl@3f {
+		compatible = "semtech,sx1509q";
+		reg = <0x3f>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+	/* RTC U2607 */
+	rtc0: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+
+	/* SX1509(1) U2606 */
+	gpio7: pinctrl@70 {
+		compatible = "semtech,sx1509q";
+		reg = <0x70>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio4>;
+		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+
+		gpio6-cfg {
+			pins = "gpio6";
+			output-high;
+		};
+
+		gpio7-cfg {
+			pins = "gpio7";
+			output-high;
+		};
+	};
+};
+
+&irqsteer_hdmi {
+	status = "okay";
+};
+
+&lcdif1 {
+	status = "disabled";
+};
+
+&lcdif2 {
+	status = "disabled";
+};
+
+/* HDMI */
+&lcdif3 {
+	status = "okay";
+
+};
+
+&lvds_bridge {
+	status = "disabled";
+};
+
+&mipi_dsi {
+	status = "disabled";
+};
+
+&pcie{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
+	fsl,tx-deemph-gen1 = <0x1f>;
+	fsl,max-link-speed = <3>;
+	status = "okay";
+};
+
+&pcie_phy{
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	#pwm-cells = <3>;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	adp-disable;
+	hnp-disable;
+	srp-disable;
+	dr_mode = "otg";
+	usb-role-switch;
+	role-switch-default-mode = "peripheral";
+	status = "okay";
+
+	port {
+		usb3_dwc: endpoint {
+			remote-endpoint = <&usb_dr_connector>;
+		};
+	};
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+/* SD slot */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	vmmc-supply = <&buck4>;
+	vqmmc-supply = <&buck5>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi1: aristainetos3-ecspi1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40000
+		>;
+	};
+
+	pinctrl_ecspi1_cs2: aristainetos3-ecspi1-cs2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000
+		>;
+	};
+
+	pinctrl_ecspi2: aristainetos3-ecspi2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000
+		>;
+	};
+
+	pinctrl_eqos_rgmii: aristainetos3-eqos-rgmii-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19
+		>;
+	};
+
+	pinctrl_fec_rgmii: aristainetos3-fec-rgmii-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
+		>;
+	};
+
+	pinctrl_flexcan1: aristainetos3-flexcan1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
+		>;
+	};
+
+	pinctrl_flexcan1_reg: aristainetos3-flexcan1-reg-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154
+		>;
+	};
+
+	pinctrl_flexcan2: aristainetos3-flexcan2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
+		>;
+	};
+
+	pinctrl_flexcan2_reg: aristainetos3-flexcan2-reg-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154
+		>;
+	};
+
+	pinctrl_gpio3_hog: aristainetos3-gpio3-hog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23	0xd6
+		>;
+	};
+
+	pinctrl_gpio_led: aristainetos3-gpio-led-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
+		>;
+	};
+
+	pinctrl_gpio_proton2s: aristainetos3-gpio-proton2s-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x19
+		>;
+	};
+
+	pinctrl_hdmi: aristainetos3-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
+		>;
+	};
+
+	pinctrl_i2c1: aristainetos3-i2c1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c1_gpio: aristainetos3-i2c1-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1c3
+		>;
+	};
+
+	pinctrl_i2c2: aristainetos3-i2c2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: aristainetos3-i2c2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1c3
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1c3
+		>;
+	};
+
+	pinctrl_i2c3: aristainetos3-i2c3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: aristainetos3-i2c3-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1c3
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1c3
+		>;
+	};
+
+	pinctrl_i2c5: aristainetos3-i2c5-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL	0x400001c3
+			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA	0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6: aristainetos3-i2c6-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL	0x400001c3
+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6_gpio: aristainetos3-i2c6-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x1c3
+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x1c3
+		>;
+	};
+
+	pinctrl_lcd0_vcc_en: aristainetos3-lcd0-vcc-en-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0xd6
+		>;
+	};
+
+	pinctrl_lvds_bklt_en: aristainetos3-lvds-bklt-en-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0xd6
+		>;
+	};
+
+	pinctrl_pcie: aristainetos3-pcie-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x41
+		>;
+	};
+
+	pinctrl_pmic: aristainetos3-pmic-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
+		>;
+	};
+
+	pinctrl_pwm1: aristainetos3-pwm1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
+		>;
+	};
+
+	pinctrl_pwm2: aristainetos3-pwm2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
+		>;
+	};
+
+	pinctrl_tpm_irq: aristainetos3-tpm-irq-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0xd6
+		>;
+	};
+
+	pinctrl_uart1: aristainetos3-uart1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart2: aristainetos3-uart2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x140
+		>;
+	};
+
+	pinctrl_uart3: aristainetos3-uart3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX	0x140
+			MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart4: aristainetos3-uart4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX    0x140
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX    0x140
+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x140
+			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140
+		>;
+	};
+
+	pinctrl_usb1_vbus: aristainetos3-usb1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19
+		>;
+	};
+
+	pinctrl_usdhc1: aristainetos3-usdhc1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: aristainetos3-usdhc1-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: aristainetos3-usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc2: aristainetos3-usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: aristainetos3-usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: aristainetos3-usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: aristainetos3-usdhc2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40000080
+		>;
+	};
+
+	pinctrl_usdhc2_vmmc: aristainetos3-usdhc2-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc3: aristainetos3-usdhc3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: aristainetos3-usdhc3-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: aristainetos3-usdhc3-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
+		>;
+	};
+
+	pinctrl_watchdog_gpio: aristainetos3-wdog-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x19
+		>;
+	};
+
+	pinctrl_wdog: aristainetos3-wdog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
+		>;
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..44b30e9b3fd
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	lvds-hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "J2";
+		type = "a";
+
+		port {
+			lvds2hdmi_connector_in: endpoint {
+				remote-endpoint = <&it6263_out>;
+			};
+		};
+	};
+};
+
+&lcdif2 {
+	status = "okay";
+};
+
+&lvds_bridge {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 00000000000..4008d2fd36d
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+			dual-lvds-odd-pixels;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dual-lvds-even-pixels;
+
+			it6263_lvds_link2: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link2>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..6eae7477abf
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	it6263: hdmi@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "jeida-24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_en>;
+		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		ivdd-supply = <&reg_buck5>;
+		ovdd-supply = <&reg_vext_3v3>;
+		txavcc18-supply = <&reg_buck5>;
+		txavcc33-supply = <&reg_vext_3v3>;
+		pvcc1-supply = <&reg_buck5>;
+		pvcc2-supply = <&reg_buck5>;
+		avcc-supply = <&reg_vext_3v3>;
+		anvdd-supply = <&reg_buck5>;
+		apvdd-supply = <&reg_buck5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@2 {
+				reg = <2>;
+
+				it6263_out: endpoint {
+					remote-endpoint = <&lvds2hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
new file mode 100644
index 00000000000..9e11f261ad1
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 00000000000..af2e73e36a1
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+			dual-lvds-even-pixels;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dual-lvds-odd-pixels;
+
+			it6263_lvds_link2: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link2>;
+			};
+		};
+
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..8cc9d361c2a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	it6263: hdmi@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "jeida-24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_en>;
+		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		ivdd-supply = <&reg_buck5>;
+		ovdd-supply = <&reg_vext_3v3>;
+		txavcc18-supply = <&reg_buck5>;
+		txavcc33-supply = <&reg_vext_3v3>;
+		pvcc1-supply = <&reg_buck5>;
+		pvcc2-supply = <&reg_buck5>;
+		avcc-supply = <&reg_vext_3v3>;
+		anvdd-supply = <&reg_buck5>;
+		apvdd-supply = <&reg_buck5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@2 {
+				reg = <2>;
+
+				it6263_out: endpoint {
+					remote-endpoint = <&lvds2hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
new file mode 100644
index 00000000000..527a893a71b
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
index d26930f1a9e..68e12a752ed 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
@@ -938,6 +938,12 @@
 		>;
 	};
 
+	pinctrl_lvds_en: lvdsengrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x1c0
+		>;
+	};
+
 	pinctrl_pcie0: pcie0grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60 /* open drain, pull up */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
index 30962922b36..2c75da5f064 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
@@ -52,7 +52,7 @@
 
 &lvds_bridge {
 	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
-	assigned-clock-rates = <482300000>;
+	assigned-clock-rates = <490000000>;
 	status = "okay";
 
 	ports {
@@ -70,10 +70,10 @@
 	 */
 	assigned-clock-rates = <500000000>, <200000000>, <0>,
 		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
-		<68900000>,
+		<70000000>,
 		<500000000>,
-		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
-		<964600000>;
+		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */
+		<490000000>;
 };
 
 &pwm4 {
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
index 336785a9fba..3ddc5aaa7c5 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2021-2022 TQ-Systems GmbH
- * Author: Alexander Stein <alexander.stein@tq-group.com>
+ * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
  */
 
 #include "imx8mp.dtsi"
@@ -23,15 +24,6 @@
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
-
-	/* e-MMC IO, needed for HS modes */
-	reg_vcc1v8: regulator-vcc1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC1V8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
 };
 
 &A53_0 {
@@ -197,7 +189,7 @@
 	no-sd;
 	no-sdio;
 	vmmc-supply = <&reg_vcc3v3>;
-	vqmmc-supply = <&reg_vcc1v8>;
+	vqmmc-supply = <&buck5_reg>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
index da8902c5f7e..1493319aa74 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
@@ -28,10 +28,10 @@
 			"Headphone Jack", "HPOUTR",
 			"IN2L", "Line In Jack",
 			"IN2R", "Line In Jack",
-			"Headphone Jack", "MICBIAS",
-			"IN1L", "Headphone Jack";
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack";
 		simple-audio-card,widgets =
-			"Microphone", "Headphone Jack",
+			"Microphone", "Microphone Jack",
 			"Headphone", "Headphone Jack",
 			"Line", "Line In Jack";
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts b/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
index b268ba7a0e1..9d8e7231b7c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
@@ -172,7 +172,7 @@
 			"Headphones", "HP_OUT",
 			"Builtin Speaker", "Speaker Amp OUTR",
 			"Speaker Amp INR", "LINE_OUT";
-		simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,hp-det-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 
 		simple-audio-card,cpu {
 			sound-dai = <&sai2>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
index 1b39514d5c1..bb37a32ce46 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
@@ -241,7 +241,7 @@
 			"Headset Mic", "MICBIAS",
 			"IN3R", "Headset Mic",
 			"DMICDAT", "Digital Mic";
-		simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,hp-det-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
 
 		simple-audio-card,cpu {
 			sound-dai = <&sai2>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
index 0c960efd9b3..c7bbba45f36 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
@@ -517,8 +517,6 @@
 		eeprom@a4 {
 			compatible = "zii,rave-sp-eeprom";
 			reg = <0xa4 0x4000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
 			zii,eeprom-name = "main-eeprom";
 		};
 	};
diff --git a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
index 0e12dcd0d4d..8491eb53120 100644
--- a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
@@ -595,6 +595,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -932,4 +935,9 @@
 		>;
 	};
 
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts b/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
index 236a44c1782..f556b6569a6 100644
--- a/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
@@ -219,6 +219,89 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	pmic@25 {
+		compatible = "nxp,pca9452";
+		reg = <0x25>;
+		interrupt-parent = <&pcal6524>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <610000>;
+				regulator-max-microvolt = <950000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <670000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <1060000>;
+				regulator-max-microvolt = <1140000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <1980000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <1710000>;
+				regulator-max-microvolt = <1890000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <840000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
 };
 
 &lpi2c3 {
@@ -284,6 +367,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -465,4 +551,10 @@
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
index 20ec5b3c21f..75e67115d52 100644
--- a/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
@@ -221,6 +221,11 @@
 		>;
 	};
 
+	p3t1085: temperature-sensor@48 {
+		compatible = "nxp,p3t1085";
+		reg = <0x48>;
+	};
+
 	ptn5110: tcpc@50 {
 		compatible = "nxp,ptn5110", "tcpci";
 		reg = <0x50>;
@@ -454,6 +459,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -641,4 +649,10 @@
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
index 599df32976e..8e939d716aa 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
@@ -627,8 +627,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
 			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
@@ -659,8 +659,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
 			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
index 0b4b3bb866d..2e953a05c59 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
@@ -597,8 +597,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
 			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
@@ -629,8 +629,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
 			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
diff --git a/dts/upstream/src/arm64/freescale/imx93.dtsi b/dts/upstream/src/arm64/freescale/imx93.dtsi
index 688488de8cd..56766fdb0b1 100644
--- a/dts/upstream/src/arm64/freescale/imx93.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx93.dtsi
@@ -925,7 +925,7 @@
 				reg-names = "ram", "regs", "rxfifo", "txfifo";
 				interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+				clocks = <&clk IMX93_CLK_SPDIF_IPG>,
 					 <&clk IMX93_CLK_SPDIF_GATE>,
 					 <&clk IMX93_CLK_DUMMY>,
 					 <&clk IMX93_CLK_AUD_XCVR_GATE>;
diff --git a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
index 6086cb7fa5a..8bc066c3760 100644
--- a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
@@ -22,6 +22,7 @@
 	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
 
 	aliases {
+		ethernet0 = &enetc_port0;
 		gpio0 = &gpio1;
 		gpio1 = &gpio2;
 		gpio2 = &gpio3;
@@ -193,6 +194,14 @@
 	};
 };
 
+&enetc_port0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enetc0>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
 &flexspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexspi1>;
@@ -338,6 +347,25 @@
 	status = "okay";
 };
 
+&netcmix_blk_ctrl {
+	status = "okay";
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_emdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emdio>;
+	status = "okay";
+
+	ethphy0: ethernet-phy@1 {
+		reg = <1>;
+		realtek,clkout-disable;
+	};
+};
+
 &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	pinctrl-names = "default";
@@ -429,6 +457,30 @@
 };
 
 &scmi_iomuxc {
+	pinctrl_emdio: emdiogrp{
+		fsl,pins = <
+			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x57e
+			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x97e
+		>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <
+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e
+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e
+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e
+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e
+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e
+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e
+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e
+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e
+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e
+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e
+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e
+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e
+		>;
+	};
+
 	pinctrl_flexspi1: flexspi1grp {
 		fsl,pins = <
 			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B			0x3fe
diff --git a/dts/upstream/src/arm64/freescale/imx95.dtsi b/dts/upstream/src/arm64/freescale/imx95.dtsi
index e9c7a8265d7..6b8470cb346 100644
--- a/dts/upstream/src/arm64/freescale/imx95.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx95.dtsi
@@ -1697,6 +1697,99 @@
 			status = "disabled";
 		};
 
+		netc_blk_ctrl: system-controller@4cde0000 {
+			compatible = "nxp,imx95-netc-blk-ctrl";
+			reg = <0x0 0x4cde0000 0x0 0x10000>,
+			      <0x0 0x4cdf0000 0x0 0x10000>,
+			      <0x0 0x4c81000c 0x0 0x18>;
+			reg-names = "ierb", "prb", "netcmix";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			power-domains = <&scmi_devpd IMX95_PD_NETC>;
+			assigned-clocks = <&scmi_clk IMX95_CLK_ENET>,
+					  <&scmi_clk IMX95_CLK_ENETREF>;
+			assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
+						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>;
+			assigned-clock-rates = <666666666>, <250000000>;
+			clocks = <&scmi_clk IMX95_CLK_ENET>;
+			clock-names = "ipg";
+			status = "disabled";
+
+			netc_bus0: pcie@4ca00000 {
+				compatible = "pci-host-ecam-generic";
+				reg = <0x0 0x4ca00000 0x0 0x100000>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				bus-range = <0x0 0x0>;
+				msi-map = <0x0 &its 0x60 0x1>,	//ENETC0 PF
+					  <0x10 &its 0x61 0x1>, //ENETC0 VF0
+					  <0x20 &its 0x62 0x1>, //ENETC0 VF1
+					  <0x40 &its 0x63 0x1>, //ENETC1 PF
+					  <0x80 &its 0x64 0x1>, //ENETC2 PF
+					  <0x90 &its 0x65 0x1>, //ENETC2 VF0
+					  <0xa0 &its 0x66 0x1>, //ENETC2 VF1
+					  <0xc0 &its 0x67 0x1>; //NETC Timer
+					 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
+				ranges = <0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0xe0000
+					 /* Timer BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd00000  0x0 0x4cd00000  0x0 0x10000
+					 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
+					 0x82000000 0x0 0x4cd20000  0x0 0x4cd20000  0x0 0x60000
+					 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd80000  0x0 0x4cd80000  0x0 0x60000>;
+
+				enetc_port0: ethernet@0,0 {
+					compatible = "pci1131,e101";
+					reg = <0x000000 0 0 0 0>;
+					clocks = <&scmi_clk IMX95_CLK_ENETREF>;
+					clock-names = "ref";
+					status = "disabled";
+				};
+
+				enetc_port1: ethernet@8,0 {
+					compatible = "pci1131,e101";
+					reg = <0x004000 0 0 0 0>;
+					clocks = <&scmi_clk IMX95_CLK_ENETREF>;
+					clock-names = "ref";
+					status = "disabled";
+				};
+
+				enetc_port2: ethernet@10,0 {
+					compatible = "pci1131,e101";
+					reg = <0x008000 0 0 0 0>;
+					status = "disabled";
+				};
+
+				netc_timer: ethernet@18,0 {
+					reg = <0x00c000 0 0 0 0>;
+					status = "disabled";
+				};
+			};
+
+			netc_bus1: pcie@4cb00000 {
+				compatible = "pci-host-ecam-generic";
+				reg = <0x0 0x4cb00000 0x0 0x100000>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				bus-range = <0x1 0x1>;
+					 /* EMDIO BAR0 - non-prefetchable memory */
+				ranges = <0x82000000 0x0 0x4cce0000  0x0 0x4cce0000  0x0 0x20000
+					 /* EMDIO BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd10000  0x0 0x4cd10000  0x0 0x10000>;
+
+				netc_emdio: mdio@0,0 {
+					compatible = "pci1131,ee00";
+					reg = <0x010000 0 0 0 0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					status = "disabled";
+				};
+			};
+		};
+
 		ddr-pmu@4e090dc0 {
 			compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
 			reg = <0x0 0x4e090dc0 0x0 0x200>;
diff --git a/dts/upstream/src/arm64/hisilicon/hi6220.dtsi b/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
index a589954c29e..f8b56d44385 100644
--- a/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
@@ -727,8 +727,6 @@
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x0 0xf7106000 0x0 0x1000>;
 			interrupts = <0 50 4>;
-			bus-id = <0>;
-			enable-dma = <0>;
 			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
 			clock-names = "sspclk", "apb_pclk";
 			pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
index 2a5eeb21da4..1235ba5a986 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
@@ -101,10 +101,13 @@
 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
+		interrupt-parent = <&intc>;
 		reg = <0x0 0xfffc1000 0x0 0x1000>,
 		      <0x0 0xfffc2000 0x0 0x2000>,
 		      <0x0 0xfffc4000 0x0 0x2000>,
 		      <0x0 0xfffc6000 0x0 0x2000>;
+		/* VGIC maintenance interrupt */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	clocks {
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
index 1162978329c..51c6e19e40b 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
@@ -222,6 +222,26 @@
 			status = "disabled";
 		};
 
+		gpio0: gpio@ffc03200 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xffc03200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&rst GPIO0_RESET>;
+			status = "disabled";
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		gpio1: gpio@10c03300 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x10c03300 0x100>;
@@ -314,7 +334,7 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
-			dmas = <&dmac0 2>, <&dmac0 3>;
+			dmas = <&dmac0 16>, <&dmac0 17>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 
@@ -331,6 +351,8 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+			dmas = <&dmac0 20>, <&dmac0 21>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
diff --git a/dts/upstream/src/arm64/marvell/armada-7040-db.dts b/dts/upstream/src/arm64/marvell/armada-7040-db.dts
index 1e0ab35cc68..2b5e45d2c5a 100644
--- a/dts/upstream/src/arm64/marvell/armada-7040-db.dts
+++ b/dts/upstream/src/arm64/marvell/armada-7040-db.dts
@@ -214,6 +214,7 @@
 
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
index 7af949092b9..6bdc4f1e693 100644
--- a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
+++ b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
@@ -433,11 +433,13 @@
 	/* 7 + 12 SATA connector (J24) */
 	sata-port@0 {
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 
 	/* M.2-2250 B-key (J39) */
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
index 7005a32a6e1..225a54ab688 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
@@ -475,6 +475,7 @@
 
 	sata-port@1 {
 		phys = <&cp1_comphy0 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-db.dts b/dts/upstream/src/arm64/marvell/armada-8040-db.dts
index 2ec19d364e6..9d45e881a97 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-db.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-db.dts
@@ -145,9 +145,12 @@
 
 	sata-port@0 {
 		phys = <&cp0_comphy1 0>;
+		status = "okay";
 	};
+
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
@@ -304,11 +307,9 @@
 
 	sata-port@0 {
 		phys = <&cp1_comphy1 0>;
-		phy-names = "cp1-sata0-0-phy";
 	};
 	sata-port@1 {
 		phys = <&cp1_comphy3 1>;
-		phy-names = "cp1-sata0-1-phy";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi b/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
index e88ff5b179c..0d4a5fd9503 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
@@ -245,6 +245,7 @@
 	/* CPM Lane 5 - U29 */
 	sata-port@1 {
 		phys = <&cp0_comphy5 1>;
+		status = "okay";
 	};
 };
 
@@ -344,13 +345,11 @@
 	/* CPS Lane 1 - U32 */
 	sata-port@0 {
 		phys = <&cp1_comphy1 0>;
-		phy-names = "cp1-sata0-0-phy";
 	};
 
 	/* CPS Lane 3 - U31 */
 	sata-port@1 {
 		phys = <&cp1_comphy3 1>;
-		phy-names = "cp1-sata0-1-phy";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts b/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
index 3e5e0651ce6..9c25a88581e 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
@@ -408,10 +408,12 @@
 
 	sata-port@0 {
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 
 	sata-port@1 {
 		phys = <&cp0_comphy5 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi b/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
index 7e595ac8004..161beec0b6b 100644
--- a/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
@@ -347,10 +347,12 @@
 
 			sata-port@0 {
 				reg = <0>;
+				status = "disabled";
 			};
 
 			sata-port@1 {
 				reg = <1>;
+				status = "disabled";
 			};
 		};
 
diff --git a/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts b/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
index 0904cb0309a..34194745f79 100644
--- a/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
+++ b/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
@@ -28,6 +28,7 @@
 		status = "okay";
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
index b1ea7dcaed1..47234d0858d 100644
--- a/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
+++ b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
@@ -435,7 +435,7 @@
 	managed = "in-band-status";
 	phy-mode = "sgmii";
 	phy = <&cp1_phy0>;
-	phys = <&cp0_comphy3 1>;
+	phys = <&cp1_comphy3 1>;
 	status = "okay";
 };
 
@@ -444,7 +444,7 @@
 	managed = "in-band-status";
 	phy-mode = "sgmii";
 	phy = <&cp1_phy1>;
-	phys = <&cp0_comphy5 2>;
+	phys = <&cp1_comphy5 2>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9131-db.dtsi b/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
index ad7360c8304..626042fce7e 100644
--- a/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
+++ b/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
@@ -127,6 +127,7 @@
 	sata-port@1 {
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp1_comphy5 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9132-db.dtsi b/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
index e753cfdac69..f91fc69905b 100644
--- a/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
+++ b/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
@@ -175,6 +175,7 @@
 	sata-port@0 {
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp2_comphy2 0>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
index c84c47c1352..0449686bd06 100644
--- a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
@@ -115,6 +115,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default>;
 	pinctrl-1 = <&eth_sleep>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/mediatek/mt6359.dtsi b/dts/upstream/src/arm64/mediatek/mt6359.dtsi
index 8e1b8c85c6e..150ad84d5d2 100644
--- a/dts/upstream/src/arm64/mediatek/mt6359.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt6359.dtsi
@@ -8,6 +8,7 @@
 		compatible = "mediatek,mt6359";
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		#sound-dai-cells = <1>;
 
 		pmic_adc: adc {
 			compatible = "mediatek,mt6359-auxadc";
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso
new file mode 100644
index 00000000000..f7dd5298197
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+	reg_sata12v: regulator-sata12v {
+		compatible = "regulator-fixed";
+		regulator-name = "sata12v";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&pio 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_sata5v: regulator-sata5v {
+		compatible = "regulator-fixed";
+		regulator-name = "sata5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&reg_sata12v>;
+	};
+
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
new file mode 100644
index 00000000000..3e320b2f83d
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+};
+
+&{/soc/mmc@11230000} {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_emmc_51>;
+	pinctrl-1 = <&mmc0_pins_emmc_51>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	hs400-ds-delay = <0x12814>;
+	vqmmc-supply = <&reg_1p8v>;
+	vmmc-supply = <&reg_3p3v>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
new file mode 100644
index 00000000000..663c6345dd3
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+};
+
+&{/soc/mmc@11230000} {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_sdcard>;
+	pinctrl-1 = <&mmc0_pins_sdcard>;
+	cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	max-frequency = <52000000>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	no-mmc;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
index efc4ad0b08b..6623112c24c 100644
--- a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -2,10 +2,408 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
 #include "mt7988a.dtsi"
 
 / {
 	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
 	model = "Banana Pi BPI-R4";
 	chassis-type = "embedded";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_trip_hot: hot {
+			temperature = <120000>;
+			hysteresis = <2000>;
+			type = "hot";
+		};
+
+		cpu_trip_active_high: active-high {
+			temperature = <115000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_med: active-med {
+			temperature = <85000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_low: active-low {
+			temperature = <40000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_1_pins>;
+	status = "okay";
+
+	pca9545: i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			pcf8563: rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+				#clock-cells = <0>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c02";
+				reg = <0x57>;
+				size = <256>;
+			};
+
+		};
+
+		i2c_sfp1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_sfp2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+	};
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+	status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+	status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+	status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+	status = "okay";
+};
+
+&pio {
+	mdio0_pins: mdio0-pins {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio0";
+		};
+
+		conf {
+			pins = "SMI_0_MDC", "SMI_0_MDIO";
+			drive-strength = <8>;
+		};
+	};
+
+	i2c0_pins: i2c0-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c0_1";
+		};
+	};
+
+	i2c1_pins: i2c1-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	i2c1_sfp_pins: i2c1-sfp-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_sfp";
+		};
+	};
+
+	i2c2_0_pins: i2c2-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c2_0";
+		};
+	};
+
+	i2c2_1_pins: i2c2-g1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c2_1";
+		};
+	};
+
+	gbe0_led0_pins: gbe0-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe0_led0";
+		};
+	};
+
+	gbe1_led0_pins: gbe1-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe1_led0";
+		};
+	};
+
+	gbe2_led0_pins: gbe2-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe2_led0";
+		};
+	};
+
+	gbe3_led0_pins: gbe3-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe3_led0";
+		};
+	};
+
+	gbe0_led1_pins: gbe0-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe0_led1";
+		};
+	};
+
+	gbe1_led1_pins: gbe1-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe1_led1";
+		};
+	};
+
+	gbe2_led1_pins: gbe2-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe2_led1";
+		};
+	};
+
+	gbe3_led1_pins: gbe3-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe3_led1";
+		};
+	};
+
+	i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led0";
+		};
+	};
+
+	i2p5gbe_led1_pins: 2p5gbe-led1-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led1";
+		};
+	};
+
+	mmc0_pins_emmc_45: mmc0-emmc-45-pins {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+	};
+
+	mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+		mux {
+			function = "flash";
+			groups = "emmc_51";
+		};
+	};
+
+	mmc0_pins_sdcard: mmc0-sdcard-pins {
+		mux {
+			function = "flash";
+			groups = "sdcard";
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		mux {
+			function = "uart";
+			groups =  "uart0";
+		};
+	};
+
+	snfi_pins: snfi-pins {
+		mux {
+			function = "flash";
+			groups = "snfi";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0";
+		};
+	};
+
+	spi0_flash_pins: spi0-flash-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	spi1_pins: spi1-pins {
+		mux {
+			function = "spi";
+			groups = "spi1";
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2";
+		};
+	};
+
+	spi2_flash_pins: spi2-flash-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+	};
+};
+
+&pwm {
+	status = "okay";
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
index c9649b81527..88b56a24efc 100644
--- a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
@@ -3,6 +3,8 @@
 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
 
 / {
 	compatible = "mediatek,mt7988a";
@@ -14,32 +16,70 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a73";
 			reg = <0x1>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a73";
 			reg = <0x2>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a73";
 			reg = <0x3>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cluster0_opp: opp-table-0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-800000000 {
+				opp-hz = /bits/ 64 <800000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1100000000 {
+				opp-hz = /bits/ 64 <1100000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1500000000 {
+				opp-hz = /bits/ 64 <1500000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1800000000 {
+				opp-hz = /bits/ 64 <1800000000>;
+				opp-microvolt = <900000>;
+			};
 		};
 	};
 
@@ -61,6 +101,18 @@
 		method = "smc";
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
+		secmon@43000000 {
+			reg = <0 0x43000000 0 0x50000>;
+			no-map;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
@@ -84,6 +136,7 @@
 			compatible = "mediatek,mt7988-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		topckgen: clock-controller@1001b000 {
@@ -99,13 +152,66 @@
 			#reset-cells = <1>;
 		};
 
-		clock-controller@1001e000 {
+		apmixedsys: clock-controller@1001e000 {
 			compatible = "mediatek,mt7988-apmixedsys";
 			reg = <0 0x1001e000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
-		pwm@10048000 {
+		pio: pinctrl@1001f000 {
+			compatible = "mediatek,mt7988-pinctrl";
+			reg = <0 0x1001f000 0 0x1000>,
+			      <0 0x11c10000 0 0x1000>,
+			      <0 0x11d00000 0 0x1000>,
+			      <0 0x11d20000 0 0x1000>,
+			      <0 0x11e00000 0 0x1000>,
+			      <0 0x11f00000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
+			reg-names = "gpio", "iocfg_tr",
+				    "iocfg_br", "iocfg_rb",
+				    "iocfg_lb", "iocfg_tl", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 84>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+
+			pcie0_pins: pcie0-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+						 "pcie_wake_n0_0";
+				};
+			};
+
+			pcie1_pins: pcie1-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+						 "pcie_wake_n1_0";
+				};
+			};
+
+			pcie2_pins: pcie2-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+						 "pcie_wake_n2_0";
+				};
+			};
+
+			pcie3_pins: pcie3-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+						 "pcie_wake_n3_0";
+				};
+			};
+		};
+
+		pwm: pwm@10048000 {
 			compatible = "mediatek,mt7988-pwm";
 			reg = <0 0x10048000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
@@ -124,7 +230,13 @@
 			status = "disabled";
 		};
 
-		serial@11000000 {
+		mcusys: mcusys@100e0000 {
+			compatible = "mediatek,mt7988-mcusys", "syscon";
+			reg = <0 0x100e0000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		serial0: serial@11000000 {
 			compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11000000 0 0x100>;
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
@@ -157,11 +269,12 @@
 			status = "disabled";
 		};
 
-		i2c@11003000 {
+		i2c0: i2c@11003000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11003000 0 0x1000>,
 			      <0 0x10217080 0 0x80>;
 			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -170,11 +283,12 @@
 			status = "disabled";
 		};
 
-		i2c@11004000 {
+		i2c1: i2c@11004000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11004000 0 0x1000>,
 			      <0 0x10217100 0 0x80>;
 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -183,11 +297,12 @@
 			status = "disabled";
 		};
 
-		i2c@11005000 {
+		i2c2: i2c@11005000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11005000 0 0x1000>,
 			      <0 0x10217180 0 0x80>;
 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -196,6 +311,17 @@
 			status = "disabled";
 		};
 
+		lvts: lvts@1100a000 {
+			compatible = "mediatek,mt7988-lvts-ap";
+			#thermal-sensor-cells = <1>;
+			reg = <0 0x1100a000 0 0x1000>;
+			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
+			nvmem-cells = <&lvts_calibration>;
+			nvmem-cell-names = "lvts-calib-data-1";
+		};
+
 		usb@11190000 {
 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
 			reg = <0 0x11190000 0 0x2e00>,
@@ -208,9 +334,10 @@
 				 <&infracfg CLK_INFRA_133M_USB_HCK>,
 				 <&infracfg CLK_INFRA_USB_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+			status = "disabled";
 		};
 
-		usb@11200000 {
+		ssusb1: usb@11200000 {
 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
 			reg = <0 0x11200000 0 0x2e00>,
 			      <0 0x11203e00 0 0x0100>;
@@ -222,6 +349,203 @@
 				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
 				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+			phys = <&tphyu2port0 PHY_TYPE_USB2>,
+			       <&tphyu3port0 PHY_TYPE_USB3>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt7988-mmc";
+			reg = <0 0x11230000 0 0x1000>,
+			      <0 0x11D60000 0 0x1000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_MSDC400>,
+				 <&infracfg CLK_INFRA_MSDC2_HCK>,
+				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
+			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie2: pcie@11280000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11280000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <3>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x20000000 0x00
+				  0x20000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x20200000 0x00
+				  0x20200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie2_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+					<0 0 0 2 &pcie_intc2 1>,
+					<0 0 0 3 &pcie_intc2 2>,
+					<0 0 0 4 &pcie_intc2 3>;
+			pcie_intc2: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie3: pcie@11290000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11290000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <2>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x28000000 0x00
+				  0x28000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x28200000 0x00
+				  0x28200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie3_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+					<0 0 0 2 &pcie_intc3 1>,
+					<0 0 0 3 &pcie_intc3 2>,
+					<0 0 0 4 &pcie_intc3 3>;
+			pcie_intc3: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie0: pcie@11300000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11300000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <0>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x30000000 0x00
+				  0x30000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x30200000 0x00
+				  0x30200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie0_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie1: pcie@11310000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11310000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <1>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x38000000 0x00
+				  0x38000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x38200000 0x00
+				  0x38200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie1_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		tphy: t-phy@11c50000 {
+			compatible = "mediatek,mt7986-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			tphyu2port0: usb-phy@11c50000 {
+				reg = <0 0x11c50000 0 0x700>;
+				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			tphyu3port0: usb-phy@11c50700 {
+				reg = <0 0x11c50700 0 0x900>;
+				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
 		};
 
 		clock-controller@11f40000 {
@@ -236,6 +560,10 @@
 			reg = <0 0x11f50000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			lvts_calibration: calib@918 {
+				reg = <0x918 0x28>;
+			};
 		};
 
 		clock-controller@15000000 {
@@ -253,6 +581,21 @@
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&lvts 0>;
+			trips {
+				cpu_trip_crit: crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
index eee64461421..b5d4b5baf47 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
@@ -931,7 +931,7 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 
-		clock: mt6397clock {
+		clock: clocks {
 			compatible = "mediatek,mt6397-clk";
 			#clock-cells = <1>;
 		};
@@ -942,11 +942,10 @@
 			#gpio-cells = <2>;
 		};
 
-		regulator: mt6397regulator {
+		regulators {
 			compatible = "mediatek,mt6397-regulator";
 
 			mt6397_vpca15_reg: buck_vpca15 {
-				regulator-compatible = "buck_vpca15";
 				regulator-name = "vpca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -956,7 +955,6 @@
 			};
 
 			mt6397_vpca7_reg: buck_vpca7 {
-				regulator-compatible = "buck_vpca7";
 				regulator-name = "vpca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -966,7 +964,6 @@
 			};
 
 			mt6397_vsramca15_reg: buck_vsramca15 {
-				regulator-compatible = "buck_vsramca15";
 				regulator-name = "vsramca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -975,7 +972,6 @@
 			};
 
 			mt6397_vsramca7_reg: buck_vsramca7 {
-				regulator-compatible = "buck_vsramca7";
 				regulator-name = "vsramca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -984,7 +980,6 @@
 			};
 
 			mt6397_vcore_reg: buck_vcore {
-				regulator-compatible = "buck_vcore";
 				regulator-name = "vcore";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -993,7 +988,6 @@
 			};
 
 			mt6397_vgpu_reg: buck_vgpu {
-				regulator-compatible = "buck_vgpu";
 				regulator-name = "vgpu";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -1002,7 +996,6 @@
 			};
 
 			mt6397_vdrm_reg: buck_vdrm {
-				regulator-compatible = "buck_vdrm";
 				regulator-name = "vdrm";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1400000>;
@@ -1011,7 +1004,6 @@
 			};
 
 			mt6397_vio18_reg: buck_vio18 {
-				regulator-compatible = "buck_vio18";
 				regulator-name = "vio18";
 				regulator-min-microvolt = <1620000>;
 				regulator-max-microvolt = <1980000>;
@@ -1020,18 +1012,15 @@
 			};
 
 			mt6397_vtcxo_reg: ldo_vtcxo {
-				regulator-compatible = "ldo_vtcxo";
 				regulator-name = "vtcxo";
 				regulator-always-on;
 			};
 
 			mt6397_va28_reg: ldo_va28 {
-				regulator-compatible = "ldo_va28";
 				regulator-name = "va28";
 			};
 
 			mt6397_vcama_reg: ldo_vcama {
-				regulator-compatible = "ldo_vcama";
 				regulator-name = "vcama";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1039,18 +1028,15 @@
 			};
 
 			mt6397_vio28_reg: ldo_vio28 {
-				regulator-compatible = "ldo_vio28";
 				regulator-name = "vio28";
 				regulator-always-on;
 			};
 
 			mt6397_vusb_reg: ldo_vusb {
-				regulator-compatible = "ldo_vusb";
 				regulator-name = "vusb";
 			};
 
 			mt6397_vmc_reg: ldo_vmc {
-				regulator-compatible = "ldo_vmc";
 				regulator-name = "vmc";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
@@ -1058,7 +1044,6 @@
 			};
 
 			mt6397_vmch_reg: ldo_vmch {
-				regulator-compatible = "ldo_vmch";
 				regulator-name = "vmch";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -1066,7 +1051,6 @@
 			};
 
 			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
-				regulator-compatible = "ldo_vemc3v3";
 				regulator-name = "vemc_3v3";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -1074,7 +1058,6 @@
 			};
 
 			mt6397_vgp1_reg: ldo_vgp1 {
-				regulator-compatible = "ldo_vgp1";
 				regulator-name = "vcamd";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1082,7 +1065,6 @@
 			};
 
 			mt6397_vgp2_reg: ldo_vgp2 {
-				regulator-compatible = "ldo_vgp2";
 				regulator-name = "vcamio";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1090,7 +1072,6 @@
 			};
 
 			mt6397_vgp3_reg: ldo_vgp3 {
-				regulator-compatible = "ldo_vgp3";
 				regulator-name = "vcamaf";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1098,7 +1079,6 @@
 			};
 
 			mt6397_vgp4_reg: ldo_vgp4 {
-				regulator-compatible = "ldo_vgp4";
 				regulator-name = "vgp4";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -1106,7 +1086,6 @@
 			};
 
 			mt6397_vgp5_reg: ldo_vgp5 {
-				regulator-compatible = "ldo_vgp5";
 				regulator-name = "vgp5";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3000000>;
@@ -1114,7 +1093,6 @@
 			};
 
 			mt6397_vgp6_reg: ldo_vgp6 {
-				regulator-compatible = "ldo_vgp6";
 				regulator-name = "vgp6";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1123,7 +1101,6 @@
 			};
 
 			mt6397_vibr_reg: ldo_vibr {
-				regulator-compatible = "ldo_vibr";
 				regulator-name = "vibr";
 				regulator-min-microvolt = <1300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1131,7 +1108,7 @@
 			};
 		};
 
-		rtc: mt6397rtc {
+		rtc: rtc {
 			compatible = "mediatek,mt6397-rtc";
 		};
 	};
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
index bb4671c18e3..9fffed0ef4b 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
@@ -307,11 +307,10 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 
-		mt6397regulator: mt6397regulator {
+		regulators {
 			compatible = "mediatek,mt6397-regulator";
 
 			mt6397_vpca15_reg: buck_vpca15 {
-				regulator-compatible = "buck_vpca15";
 				regulator-name = "vpca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -320,7 +319,6 @@
 			};
 
 			mt6397_vpca7_reg: buck_vpca7 {
-				regulator-compatible = "buck_vpca7";
 				regulator-name = "vpca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -329,7 +327,6 @@
 			};
 
 			mt6397_vsramca15_reg: buck_vsramca15 {
-				regulator-compatible = "buck_vsramca15";
 				regulator-name = "vsramca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -338,7 +335,6 @@
 			};
 
 			mt6397_vsramca7_reg: buck_vsramca7 {
-				regulator-compatible = "buck_vsramca7";
 				regulator-name = "vsramca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -347,7 +343,6 @@
 			};
 
 			mt6397_vcore_reg: buck_vcore {
-				regulator-compatible = "buck_vcore";
 				regulator-name = "vcore";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -356,7 +351,6 @@
 			};
 
 			mt6397_vgpu_reg: buck_vgpu {
-				regulator-compatible = "buck_vgpu";
 				regulator-name = "vgpu";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -365,7 +359,6 @@
 			};
 
 			mt6397_vdrm_reg: buck_vdrm {
-				regulator-compatible = "buck_vdrm";
 				regulator-name = "vdrm";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1400000>;
@@ -374,7 +367,6 @@
 			};
 
 			mt6397_vio18_reg: buck_vio18 {
-				regulator-compatible = "buck_vio18";
 				regulator-name = "vio18";
 				regulator-min-microvolt = <1620000>;
 				regulator-max-microvolt = <1980000>;
@@ -383,19 +375,16 @@
 			};
 
 			mt6397_vtcxo_reg: ldo_vtcxo {
-				regulator-compatible = "ldo_vtcxo";
 				regulator-name = "vtcxo";
 				regulator-always-on;
 			};
 
 			mt6397_va28_reg: ldo_va28 {
-				regulator-compatible = "ldo_va28";
 				regulator-name = "va28";
 				regulator-always-on;
 			};
 
 			mt6397_vcama_reg: ldo_vcama {
-				regulator-compatible = "ldo_vcama";
 				regulator-name = "vcama";
 				regulator-min-microvolt = <1500000>;
 				regulator-max-microvolt = <2800000>;
@@ -403,18 +392,15 @@
 			};
 
 			mt6397_vio28_reg: ldo_vio28 {
-				regulator-compatible = "ldo_vio28";
 				regulator-name = "vio28";
 				regulator-always-on;
 			};
 
 			mt6397_vusb_reg: ldo_vusb {
-				regulator-compatible = "ldo_vusb";
 				regulator-name = "vusb";
 			};
 
 			mt6397_vmc_reg: ldo_vmc {
-				regulator-compatible = "ldo_vmc";
 				regulator-name = "vmc";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
@@ -422,7 +408,6 @@
 			};
 
 			mt6397_vmch_reg: ldo_vmch {
-				regulator-compatible = "ldo_vmch";
 				regulator-name = "vmch";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -430,7 +415,6 @@
 			};
 
 			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
-				regulator-compatible = "ldo_vemc3v3";
 				regulator-name = "vemc_3v3";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -438,7 +422,6 @@
 			};
 
 			mt6397_vgp1_reg: ldo_vgp1 {
-				regulator-compatible = "ldo_vgp1";
 				regulator-name = "vcamd";
 				regulator-min-microvolt = <1220000>;
 				regulator-max-microvolt = <3300000>;
@@ -446,7 +429,6 @@
 			};
 
 			mt6397_vgp2_reg: ldo_vgp2 {
-				regulator-compatible = "ldo_vgp2";
 				regulator-name = "vcamio";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <3300000>;
@@ -454,7 +436,6 @@
 			};
 
 			mt6397_vgp3_reg: ldo_vgp3 {
-				regulator-compatible = "ldo_vgp3";
 				regulator-name = "vcamaf";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -462,7 +443,6 @@
 			};
 
 			mt6397_vgp4_reg: ldo_vgp4 {
-				regulator-compatible = "ldo_vgp4";
 				regulator-name = "vgp4";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -470,7 +450,6 @@
 			};
 
 			mt6397_vgp5_reg: ldo_vgp5 {
-				regulator-compatible = "ldo_vgp5";
 				regulator-name = "vgp5";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3000000>;
@@ -478,7 +457,6 @@
 			};
 
 			mt6397_vgp6_reg: ldo_vgp6 {
-				regulator-compatible = "ldo_vgp6";
 				regulator-name = "vgp6";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -486,7 +464,6 @@
 			};
 
 			mt6397_vibr_reg: ldo_vibr {
-				regulator-compatible = "ldo_vibr";
 				regulator-name = "vibr";
 				regulator-min-microvolt = <1300000>;
 				regulator-max-microvolt = <3300000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
index 65860b33c01..3935d83a047 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
@@ -26,6 +26,10 @@
 	hid-descr-addr = <0x0001>;
 };
 
+&mt6358codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+};
+
 &qca_wifi {
 	qcom,ath10k-calibration-variant = "GO_DAMU";
 };
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
index e8241587949..561770fcf69 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -12,3 +12,18 @@
 	chassis-type = "laptop";
 	compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
 };
+
+&i2c0 {
+	touchscreen@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+
+		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+		post-power-on-delay-ms = <70>;
+		hid-descr-addr = <0x0001>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
index 76d33540166..c942e461a17 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -6,6 +6,21 @@
 /dts-v1/;
 #include "mt8183-kukui-jacuzzi.dtsi"
 
+&i2c0 {
+	touchscreen@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+
+		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+		post-power-on-delay-ms = <70>;
+		hid-descr-addr = <0x0001>;
+	};
+};
+
 &i2c2 {
 	trackpad@2c {
 		compatible = "hid-over-i2c";
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 49e053b932e..80888bd4ad8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -39,8 +39,6 @@
 	pp3300_panel: pp3300-panel {
 		compatible = "regulator-fixed";
 		regulator-name = "pp3300_panel";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pp3300_panel_pins>;
 
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
index 4b974bb781b..e1495f1900a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -269,11 +269,6 @@
 	};
 };
 
-&dpi0 {
-	/* TODO Re-enable after DP to Type-C port muxing can be described */
-	status = "disabled";
-};
-
 &gic {
 	mediatek,broken-save-restore-fw;
 };
@@ -944,13 +939,13 @@
 };
 
 &thermal_zones {
-	tboard1 {
+	tboard1-thermal {
 		polling-delay = <1000>; /* milliseconds */
 		polling-delay-passive = <0>; /* milliseconds */
 		thermal-sensors = <&tboard_thermistor1>;
 	};
 
-	tboard2 {
+	tboard2-thermal {
 		polling-delay = <1000>; /* milliseconds */
 		polling-delay-passive = <0>; /* milliseconds */
 		thermal-sensors = <&tboard_thermistor2>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
index 61a6f66914b..dbdee604eda 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -522,10 +522,6 @@
 	status = "okay";
 };
 
-&dsi0 {
-	status = "disabled";
-};
-
 &dpi0 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dpi_func_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183.dtsi b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
index 1afeeb1155f..0aa34e5bbaa 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
@@ -1024,7 +1024,8 @@
 		};
 
 		keyboard: keyboard@10010000 {
-			compatible = "mediatek,mt6779-keypad";
+			compatible = "mediatek,mt8183-keypad",
+				     "mediatek,mt6779-keypad";
 			reg = <0 0x10010000 0 0x1000>;
 			interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
 			clocks = <&clk26m>;
@@ -1834,6 +1835,7 @@
 			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 			phys = <&mipi_tx0>;
 			phy-names = "dphy";
+			status = "disabled";
 		};
 
 		dpi0: dpi@14015000 {
@@ -1845,6 +1847,7 @@
 				 <&mmsys CLK_MM_DPI_MM>,
 				 <&apmixedsys CLK_APMIXED_TVDPLL>;
 			clock-names = "pixel", "engine", "pll";
+			status = "disabled";
 
 			port {
 				dpi_out: endpoint { };
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts
new file mode 100644
index 00000000000..5d012bc4ff0
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104CM2A/CZ1204CM2A";
+	compatible = "google,chinchou-sku0", "google,chinchou-sku2",
+			"google,chinchou-sku4", "google,chinchou-sku5",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&gpio_keys {
+	status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts
new file mode 100644
index 00000000000..9d6e62af694
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A";
+	compatible = "google,chinchou-sku1", "google,chinchou-sku3",
+			"google,chinchou-sku6", "google,chinchou-sku7",
+			"google,chinchou-sku17", "google,chinchou-sku20",
+			"google,chinchou-sku22", "google,chinchou-sku23",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&gpio_keys {
+	status = "disabled";
+};
+
+&i2c1 {
+	i2c-scl-internal-delay-ns = <10000>;
+
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili2901";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&pp1800_tchscr_report_disable>;
+		vcc33-supply = <&pp3300_z2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts
new file mode 100644
index 00000000000..eb377de1fcd
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A";
+	compatible = "google,chinchou-sku16", "google,chinchou-sku18",
+			"google,chinchou-sku19", "google,chinchou-sku21",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&i2c1 {
+	i2c-scl-internal-delay-ns = <10000>;
+
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili2901";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&pp1800_tchscr_report_disable>;
+		vcc33-supply = <&pp3300_z2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi
new file mode 100644
index 00000000000..80079215702
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+
+/ {
+	/delete-node/ speaker-codec;
+
+	pp1000_edpbrdg: regulator-pp1000-edpbrdg {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1000_edpbrdg";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp1000_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 29 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_edpbrdg_dx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp1800_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&mt6366_vio18_reg>;
+	};
+
+	pp3300_edp_dx: regulator-pp3300-edp-dx {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_edp_dx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp3300_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 31 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_tchscr_report_disable";
+		pinctrl-names = "default";
+		regulator-boot-on;
+		pinctrl-0 = <&touch_pin_report>;
+		gpio = <&pio 37 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&dsi_out {
+	remote-endpoint = <&anx7625_in>;
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	anx_bridge: anx7625@58 {
+		compatible = "analogix,anx7625";
+		reg = <0x58>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&anx7625_pins>;
+		enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
+		vdd10-supply = <&pp1000_edpbrdg>;
+		vdd18-supply = <&pp1800_edpbrdg_dx>;
+		vdd33-supply = <&pp3300_edp_dx>;
+		analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
+		analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				anx7625_in: endpoint {
+					remote-endpoint = <&dsi_out>;
+					data-lanes = <0 1 2 3>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				anx7625_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+		};
+
+		aux-bus {
+			panel: panel {
+				compatible = "edp-panel";
+				power-supply = <&pp3300_disp_x>;
+				backlight = <&backlight_lcd0>;
+
+				port {
+					panel_in: endpoint {
+						remote-endpoint = <&anx7625_out>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2c2 {
+	/delete-node/ trackpad@15;
+
+	touchpad@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+		interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+		post-power-on-delay-ms = <10>;
+		hid-descr-addr = <0x0001>;
+		vdd-supply = <&pp3300_s3>;
+		wakeup-source;
+	};
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	/delete-node/ codec@1a;
+
+	rt5650: rt5650@1a {
+		compatible = "realtek,rt5650";
+		reg = <0x1a>;
+		avdd-supply = <&mt6366_vio18_reg>;
+		cpvdd-supply = <&mt6366_vio18_reg>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_codec_pins_default>;
+		cbj-sleeve-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&pio>;
+		interrupts = <17 IRQ_TYPE_EDGE_BOTH>;
+		#sound-dai-cells = <0>;
+		realtek,dmic1-data-pin = <2>;
+		realtek,jd-mode = <2>;
+	};
+};
+
+&i2c_tunnel {
+	/delete-node/ sbs-battery@b;
+
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
+
+&keyboard_controller {
+	keypad,num-columns = <15>;
+
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)        /* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)        /* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)        /* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)        /* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)        /* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)        /* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)        /* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)        /* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)        /* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)        /* T10 */
+		MATRIX_KEY(0x00, 0x01, 0)        /* T11 */
+		MATRIX_KEY(0x01, 0x05, 0)        /* T12 */
+	>;
+
+	linux,keymap = <
+		CROS_STD_MAIN_KEYMAP
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)           /* T1 */
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)        /* T2 */
+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)           /* T3 */
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)          /* T4 */
+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)          /* T5 */
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)   /* T7 */
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)           /* T8 */
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)	   /* T9 */
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)	   /* T10 */
+		MATRIX_KEY(0x00, 0x01, KEY_MICMUTE)        /* T11 */
+		MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL)   /* T12 */
+		MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG)   /* T13 */
+		MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE)	   /* T14 */
+		MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG)	   /* T15 */
+		MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)	   /* Search*/
+		MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL)	   /* Left Control*/
+		MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT)        /* Left ALT*/
+		MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL)      /* Right Control*/
+		MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH)      /* BACKSLASH*/
+	>;
+};
+
+&mmc1_pins_default {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&mmc1_pins_uhs {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&pen_insert {
+	wakeup-event-action = <EV_ACT_ANY>;
+};
+
+&pio {
+	anx7625_pins: anx7625-pins {
+		pins-int {
+			pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
+			input-enable;
+			bias-disable;
+		};
+
+		pins-reset {
+			pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
+			output-low;
+		};
+
+		pins-power-en {
+			pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
+			output-low;
+		};
+	};
+
+	en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO29__FUNC_GPIO29>;
+			output-low;
+		};
+	};
+
+	en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
+			output-low;
+		};
+	};
+
+	en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
+			output-low;
+		};
+	};
+
+	touch_pin_report: pin-report-pins {
+		pins-touch-en {
+			pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
+			output-low;
+		};
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8186-mt6366-rt5650-sound";
+	model = "mt8186_rt5650";
+	mediatek,adsp = <&adsp>;
+
+	audio-routing =
+		"Headphone", "HPOL",
+		"Headphone", "HPOR",
+		"IN1P", "Headset Mic",
+		"IN1N", "Headset Mic",
+		"Speakers", "SPOL",
+		"Speakers", "SPOR",
+		"HDMI1", "TX";
+
+	hs-playback-dai-link {
+		codec {
+			sound-dai = <&rt5650>;
+		};
+	};
+
+	hs-capture-dai-link {
+		codec {
+			sound-dai = <&rt5650>;
+		};
+	};
+
+	spk-share-dai-link {
+	};
+
+	spk-hdmi-playback-dai-link {
+		codec {
+			sound-dai = <&it6505dptx>;
+		};
+	};
+};
+
+&touchscreen_pins {
+	/delete-node/ pins-report-sw;
+};
+
+&wifi_enable_pin {
+	pins-wifi-enable {
+		pinmux = <PINMUX_GPIO51__FUNC_GPIO51>;
+	};
+};
+
+&wifi_pwrseq {
+	reset-gpios = <&pio 51 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts
new file mode 100644
index 00000000000..23e194579bf
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-starmie.dtsi"
+
+/ {
+	model = "Google Starmie sku0 board";
+	compatible = "google,starmie-sku0", "google,starmie-sku2",
+		     "google,starmie-sku3", "google,starmie",
+		     "mediatek,mt8186";
+};
+
+&panel {
+	compatible = "starry,ili9882t";
+};
+
+&i2c1 {
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili9882t";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		panel = <&panel>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&mt6366_vio18_reg>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts
new file mode 100644
index 00000000000..214b972c935
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-starmie.dtsi"
+
+/ {
+	model = "Google Starmie sku1 board";
+	compatible = "google,starmie-sku1", "google,starmie-sku4",
+		     "google,starmie", "mediatek,mt8186";
+};
+
+&panel {
+	compatible = "starry,himax83102-j02", "himax,hx83102";
+};
+
+&i2c1 {
+	touchscreen_himax: touchscreen@4f {
+		compatible = "hid-over-i2c";
+		reg = <0x4f>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		vdd-supply = <&mt6366_vio18_reg>;
+		panel = <&panel>;
+		post-power-on-delay-ms = <450>;
+		hid-descr-addr = <0x0001>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi
new file mode 100644
index 00000000000..5ea8bdc00e8
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi
@@ -0,0 +1,472 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+
+/ {
+	en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma {
+		compatible = "regulator-fixed";
+		regulator-name = "en_pp6000_mipi_disp_150ma";
+		gpio = <&pio 154 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp6000_mipi_disp_150ma_fixed_pins>;
+	};
+
+	/*
+	 * Starmie does not have 3.3V display regulator. It is replaced
+	 * with 6V module for enabling panel, re-using eDP GPIOs.
+	 */
+	/delete-node/ pp3300_disp_x;
+	en_pp6000_mipi_disp: en-regulator-pp6000-mipi-disp {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_panel_fixed_pins>;
+		gpios = <&pio 153 GPIO_ACTIVE_HIGH>;
+		regulator-name = "en_pp6000_mipi_disp";
+		enable-active-high;
+		regulator-enable-ramp-delay = <3000>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	tboard_thermistor1: thermal-sensor1 {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&auxadc 0>;
+		io-channel-names = "sensor-channel";
+		temperature-lookup-table = <    (-5000) 1492
+						0 1413
+						5000 1324
+						10000 1227
+						15000 1121
+						20000 1017
+						25000 900
+						30000 797
+						35000 698
+						40000 606
+						45000 522
+						50000 449
+						55000 383
+						60000 327
+						65000 278
+						70000 236
+						75000 201
+						80000 171
+						85000 145
+						90000 163
+						95000 124
+						100000 91
+						105000 78
+						110000 67
+						115000 58
+						120000 50
+						125000 44>;
+	};
+
+	tboard_thermistor2: thermal-sensor2 {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&auxadc 1>;
+		io-channel-names = "sensor-channel";
+		temperature-lookup-table = <    (-5000) 1492
+						0 1413
+						5000 1324
+						10000 1227
+						15000 1121
+						20000 1017
+						25000 900
+						30000 797
+						35000 698
+						40000 606
+						45000 522
+						50000 449
+						55000 383
+						60000 327
+						65000 278
+						70000 236
+						75000 201
+						80000 171
+						85000 145
+						90000 163
+						95000 124
+						100000 91
+						105000 78
+						110000 67
+						115000 58
+						120000 50
+						125000 44>;
+	};
+};
+
+/*
+ * Starmie does not have EC keyboard. Remove default keyboard controller
+ * and replace it with the driver for side switches.
+ */
+/delete-node/ &keyboard_controller;
+
+&cros_ec {
+	cbas: cbas {
+		compatible = "google,cros-cbas";
+	};
+
+	keyboard-controller {
+		compatible = "google,cros-ec-keyb-switches";
+	};
+};
+
+&dsi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	panel: panel@0 {
+		/* compatible will be set in board dts */
+		reg = <0>;
+		enable-gpios = <&pio 98 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&panel_default_pins>;
+		avdd-supply = <&en_pp6000_mipi_disp>;
+		avee-supply = <&en_pp6000_mipi_disp_150ma>;
+		pp1800-supply = <&mt6366_vio18_reg>;
+		backlight = <&backlight_lcd0>;
+		rotation = <270>;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+};
+
+&dsi_out {
+	remote-endpoint = <&panel_in>;
+};
+
+&i2c0 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&i2c4 {
+	status = "disabled";
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+};
+
+&mmc1_pins_default {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&mmc1_pins_uhs {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&pen_insert {
+	wakeup-event-action = <EV_ACT_ANY>;
+};
+
+&pio {
+	/* 185 lines */
+	gpio-line-names = "TP",
+			  "TP",
+			  "TP",
+			  "I2S0_HP_DI",
+			  "I2S3_DP_SPKR_DO",
+			  "SAR_INT_ODL",
+			  "BT_WAKE_AP_ODL",
+			  "WIFI_INT_ODL",
+			  "DPBRDG_INT_ODL",
+			  "NC",
+			  "EC_AP_HPD_OD",
+			  "NC",
+			  "TCHSCR_INT_1V8_ODL",
+			  "EC_AP_INT_ODL",
+			  "EC_IN_RW_ODL",
+			  "GSC_AP_INT_ODL",
+			  /*
+			   * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
+			   * call it AP_WP_ODL.
+			   */
+			  "AP_FLASH_WP_L",
+			  "HP_INT_ODL",
+			  "PEN_EJECT_OD",
+			  "NC",
+			  "NC",
+			  "UCAM_SEN_EN",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "I2S2_DP_SPK_MCK",
+			  "I2S2_DP_SPKR_BCK",
+			  "I2S2_DP_SPKR_LRCK",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "UART_GSC_TX_AP_RX",
+			  "UART_AP_TX_GSC_RX",
+			  "UART_DBGCON_TX_ADSP_RX",
+			  "UART_ADSP_TX_DBGCON_RX",
+			  "NC",
+			  "TCHSCR_REPORT_DISABLE",
+			  "NC",
+			  "EN_PP1800_DPBRDG",
+			  "SPI_AP_CLK_EC",
+			  "SPI_AP_CS_EC_L",
+			  "SPI_AP_DO_EC_DI",
+			  "SPI_AP_DI_EC_DO",
+			  "SPI_AP_CLK_GSC",
+			  "SPI_AP_CS_GSC_L",
+			  "SPI_AP_DO_GSC_DI",
+			  "SPI_AP_DI_GSC_DO",
+			  "UART_DBGCON_TX_SCP_RX",
+			  "UART_SCP_TX_DBGCON_RX",
+			  "EN_PP1200_CAM_X",
+			  "WLAN_MODULE_RST_L",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "I2S1_HP_DO",
+			  "I2S1_HP_BCK",
+			  "I2S1_HP_LRCK",
+			  "I2S1_HP_MCK",
+			  "TCHSCR_RST_1V8_L",
+			  "SPI_AP_CLK_ROM",
+			  "SPI_AP_CS_ROM_L",
+			  "SPI_AP_DO_ROM_DI",
+			  "SPI_AP_DI_ROM_DO",
+			  "NC",
+			  "NC",
+			  "EMMC_STRB",
+			  "EMMC_CLK",
+			  "EMMC_CMD",
+			  "EMMC_RST_L",
+			  "EMMC_DATA0",
+			  "EMMC_DATA1",
+			  "EMMC_DATA2",
+			  "EMMC_DATA3",
+			  "EMMC_DATA4",
+			  "EMMC_DATA5",
+			  "EMMC_DATA6",
+			  "EMMC_DATA7",
+			  "AP_KPCOL0",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "TP",
+			  "SDIO_CLK",
+			  "SDIO_CMD",
+			  "SDIO_DATA0",
+			  "SDIO_DATA1",
+			  "SDIO_DATA2",
+			  "SDIO_DATA3",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "MIPI_BL_PWM_1V8",
+			  "DISP_RST_1V8_L",
+			  "MIPI_DPI_CLK",
+			  "MIPI_DPI_VSYNC",
+			  "MIPI_DPI_HSYNC",
+			  "MIPI_DPI_DE",
+			  "MIPI_DPI_D0",
+			  "MIPI_DPI_D1",
+			  "MIPI_DPI_D2",
+			  "MIPI_DPI_D3",
+			  "MIPI_DPI_D4",
+			  "MIPI_DPI_D5",
+			  "MIPI_DPI_D6",
+			  "MIPI_DPI_DA7",
+			  "MIPI_DPI_D8",
+			  "MIPI_DPI_D9",
+			  "MIPI_DPI_D10",
+			  "MIPI_DPI_D11",
+			  "PCM_BT_CLK",
+			  "PCM_BT_SYNC",
+			  "PCM_BT_DI",
+			  "PCM_BT_DO",
+			  "JTAG_TMS_TP",
+			  "JTAG_TCK_TP",
+			  "JTAG_TDI_TP",
+			  "JTAG_TDO_TP",
+			  "JTAG_TRSTN_TP",
+			  "NC",
+			  "NC",
+			  "UCAM_DET_ODL",
+			  "NC",
+			  "NC",
+			  "AP_I2C_TCHSCR_SCL_1V8",
+			  "AP_I2C_TCHSCR_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "AP_I2C_DPBRDG_SCL_1V8",
+			  "AP_I2C_DPBRDG_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "AP_I2C_AUD_SCL_1V8",
+			  "AP_I2C_AUD_SDA_1V8",
+			  "AP_I2C_DISP_SCL_1V8",
+			  "AP_I2C_DISP_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "SCP_I2C_SENSOR_SCL_1V8",
+			  "SCP_I2C_SENSOR_SDA_1V8",
+			  "AP_EC_WARM_RST_REQ",
+			  "AP_XHCI_INIT_DONE",
+			  "USB3_HUB_RST_L",
+			  "EN_SPKR",
+			  "BEEP_ON",
+			  "AP_DISP_BKLTEN",
+			  "EN_PP6000_MIPI_DISP",
+			  "EN_PP6000_MIPI_DISP_150MA",
+			  "BT_KILL_1V8_L",
+			  "WIFI_KILL_1V8_L",
+			  "PWRAP_SPI0_CSN",
+			  "PWRAP_SPI0_CK",
+			  "PWRAP_SPI0_MO",
+			  "PWRAP_SPI0_MI",
+			  "SRCLKENA0",
+			  "SRCLKENA1",
+			  "SCP_VREQ_VAO",
+			  "AP_RTC_CLK32K",
+			  "AP_PMIC_WDTRST_L",
+			  "AUD_CLK_MOSI",
+			  "AUD_SYNC_MOSI",
+			  "AUD_DAT_MOSI0",
+			  "AUD_DAT_MOSI1",
+			  "AUD_CLK_MISO",
+			  "AUD_SYNC_MISO",
+			  "AUD_DAT_MISO0",
+			  "AUD_DAT_MISO1",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "DPBRDG_RST_L",
+			  "LTE_W_DISABLE_L",
+			  "LTE_SAR_DETECT_L",
+			  "EN_PP3300_LTE_X",
+			  "LTE_PWR_OFF_L",
+			  "LTE_RESET_L",
+			  "TP",
+			  "TP";
+
+	dpi_default_pins: dpi-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO103__FUNC_GPIO103>,
+				 <PINMUX_GPIO104__FUNC_GPIO104>,
+				 <PINMUX_GPIO105__FUNC_GPIO105>,
+				 <PINMUX_GPIO106__FUNC_GPIO106>,
+				 <PINMUX_GPIO107__FUNC_GPIO107>,
+				 <PINMUX_GPIO108__FUNC_GPIO108>,
+				 <PINMUX_GPIO109__FUNC_GPIO109>,
+				 <PINMUX_GPIO110__FUNC_GPIO110>,
+				 <PINMUX_GPIO111__FUNC_GPIO111>,
+				 <PINMUX_GPIO112__FUNC_GPIO112>,
+				 <PINMUX_GPIO113__FUNC_GPIO113>,
+				 <PINMUX_GPIO114__FUNC_GPIO114>,
+				 <PINMUX_GPIO101__FUNC_GPIO101>,
+				 <PINMUX_GPIO100__FUNC_GPIO100>,
+				 <PINMUX_GPIO102__FUNC_GPIO102>,
+				 <PINMUX_GPIO99__FUNC_GPIO99>;
+			drive-strength = <10>;
+			output-low;
+		};
+	};
+
+	dpi_func_pins: dpi-func-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>,
+				 <PINMUX_GPIO104__FUNC_DPI_DATA1>,
+				 <PINMUX_GPIO105__FUNC_DPI_DATA2>,
+				 <PINMUX_GPIO106__FUNC_DPI_DATA3>,
+				 <PINMUX_GPIO107__FUNC_DPI_DATA4>,
+				 <PINMUX_GPIO108__FUNC_DPI_DATA5>,
+				 <PINMUX_GPIO109__FUNC_DPI_DATA6>,
+				 <PINMUX_GPIO110__FUNC_DPI_DATA7>,
+				 <PINMUX_GPIO111__FUNC_DPI_DATA8>,
+				 <PINMUX_GPIO112__FUNC_DPI_DATA9>,
+				 <PINMUX_GPIO113__FUNC_DPI_DATA10>,
+				 <PINMUX_GPIO114__FUNC_DPI_DATA11>,
+				 <PINMUX_GPIO101__FUNC_DPI_HSYNC>,
+				 <PINMUX_GPIO100__FUNC_DPI_VSYNC>,
+				 <PINMUX_GPIO102__FUNC_DPI_DE>,
+				 <PINMUX_GPIO99__FUNC_DPI_PCLK>;
+			drive-strength = <10>;
+		};
+	};
+
+	en_pp6000_mipi_disp_150ma_fixed_pins: en_pp6000-mipi-disp-150ma-fixed-pins {
+		pins-en {
+			pinmux = <PINMUX_GPIO154__FUNC_GPIO154>;
+			output-low;
+		};
+	};
+
+	panel_default_pins: panel-default-pins {
+		pins-en {
+			pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
+			output-low;
+		};
+	};
+};
+
+&usb_c1 {
+	status = "disabled";
+};
+
+&thermal_zones {
+	tboard1-thermal {
+		polling-delay = <1000>; /* milliseconds */
+		polling-delay-passive = <0>; /* milliseconds */
+		thermal-sensors = <&tboard_thermistor1>;
+	};
+
+	tboard2-thermal {
+		polling-delay = <1000>; /* milliseconds */
+		polling-delay-passive = <0>; /* milliseconds */
+		thermal-sensors = <&tboard_thermistor2>;
+	};
+};
+
+&wifi_pwrseq {
+	reset-gpios = <&pio 51 1>;
+};
+
+/*
+ * Battery on Starmie is using a different address than default.
+ * Remove old node to reuse "battery" alias.
+ */
+/delete-node/ &battery;
+&i2c_tunnel {
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
index cfcc7909dfe..cebb134331f 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
@@ -424,6 +424,7 @@
 		ovdd-supply = <&mt6366_vsim2_reg>;
 		pwr18-supply = <&pp1800_dpbrdg_dx>;
 		reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
+		extcon = <&usbc_extcon>;
 
 		ports {
 			#address-cells = <1>;
@@ -1275,7 +1276,7 @@
 		interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>;
 		#interrupt-cells = <2>;
 
-		mt6366codec: codec {
+		mt6366codec: audio-codec {
 			compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";
 			Avdd-supply = <&mt6366_vaud28_reg>;
 			mediatek,dmic-mode = <1>; /* one-wire */
@@ -1656,6 +1657,11 @@
 				try-power-role = "source";
 			};
 		};
+
+		usbc_extcon: extcon0 {
+			compatible = "google,extcon-usbc-cros-ec";
+			google,usb-port-id = <0>;
+		};
 	};
 };
 
diff --git a/dts/upstream/src/arm64/mediatek/mt8186.dtsi b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
index d3c3c2a40ad..b91f88ffae0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
@@ -1577,6 +1577,8 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x420 2>;
 			status = "disabled";
 
 			usb_host0: usb@11200000 {
@@ -1590,8 +1592,6 @@
 					 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
 				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 				interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
-				mediatek,syscon-wakeup = <&pericfg 0x420 2>;
-				wakeup-source;
 				status = "disabled";
 			};
 		};
@@ -1643,6 +1643,8 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x424 2>;
 			status = "disabled";
 
 			usb_host1: usb@11280000 {
@@ -1656,8 +1658,6 @@
 					 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
 				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
 				interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
-				mediatek,syscon-wakeup = <&pericfg 0x424 2>;
-				wakeup-source;
 				status = "disabled";
 			};
 		};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts
new file mode 100644
index 00000000000..79d6d12394b
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku0 board";
+	compatible = "google,ciri-sku0", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_m98390_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts
new file mode 100644
index 00000000000..ef5ea9d12b1
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku1 board";
+	compatible = "google,ciri-sku1", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_m98390_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts
new file mode 100644
index 00000000000..ef56786fc2b
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku2 board";
+	compatible = "google,ciri-sku2", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_m98390_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts
new file mode 100644
index 00000000000..524f7f0064c
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku3 board";
+	compatible = "google,ciri-sku3", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_m98390_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts
new file mode 100644
index 00000000000..ea953d7e154
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku4 board (rev4)";
+	compatible = "google,ciri-sku4", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_tas2563_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts
new file mode 100644
index 00000000000..bf87201ccf2
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku5 board (rev4)";
+	compatible = "google,ciri-sku5", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_tas2563_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts
new file mode 100644
index 00000000000..17d7359dfb6
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku6 board (rev4)";
+	compatible = "google,ciri-sku6", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_tas2563_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts
new file mode 100644
index 00000000000..825015b452d
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku7 board (rev4)";
+	compatible = "google,ciri-sku7", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_tas2563_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi
new file mode 100644
index 00000000000..6815c435a57
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt.dtsi"
+
+&aud_etdm_hp_on {
+	pins-mclk {
+		pinmux = <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>;
+	};
+};
+
+&aud_etdm_hp_off {
+	pins-mclk {
+		pinmux = <PINMUX_GPIO114__FUNC_B_GPIO114>;
+		bias-pull-down;
+		input-enable;
+	};
+};
+
+&i2c0 {
+	rt5682s: audio-codec@1a {
+		compatible = "realtek,rt5682s";
+		reg = <0x1a>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_EDGE_BOTH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <1>;
+
+		AVDD-supply = <&mt6359_vio18_ldo_reg>;
+		DBVDD-supply = <&mt6359_vio18_ldo_reg>;
+		LDO1-IN-supply = <&mt6359_vio18_ldo_reg>;
+		MICVDD-supply = <&pp3300_s3>;
+		realtek,jd-src = <1>;
+	};
+
+	max98390_38: amplifier@38 {
+		compatible = "maxim,max98390";
+		reg = <0x38>;
+		sound-name-prefix = "Front Right";
+		reset-gpios = <&pio 118 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_en>;
+		#sound-dai-cells = <0>;
+	};
+
+	max98390_39: amplifier@39 {
+		compatible = "maxim,max98390";
+		reg = <0x39>;
+		sound-name-prefix = "Front Left";
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2c_tunnel {
+	/*
+	 * The virtual battery I2C addr is 0xf on Ciri, so we describe it
+	 * manually instead of including 'arm/cros-ec-sbs.dtsi'.
+	 **/
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
+
+&mipi_tx_config0 {
+	drive-strength-microamp = <5200>;
+};
+
+&mt6359_vm18_ldo_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1900000>;
+	regulator-microvolt-offset = <100000>;
+};
+
+&sound {
+	dai-link-0 {
+		link-name = "ETDM1_IN_BE";
+		dai-format = "i2s";
+		mediatek,clk-provider = "cpu";
+	};
+
+	dai-link-1 {
+		link-name = "ETDM1_OUT_BE";
+		dai-format = "i2s";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&max98390_38>,
+				    <&max98390_39>;
+		};
+	};
+
+	dai-link-2 {
+		link-name = "ETDM2_IN_BE";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&rt5682s 0>;
+		};
+	};
+
+	dai-link-3 {
+		link-name = "ETDM2_OUT_BE";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&rt5682s 0>;
+		};
+	};
+
+	dai-link-4 {
+		link-name = "DPTX_BE";
+
+		codec {
+			sound-dai = <&dp_tx>;
+		};
+	};
+};
+
+&pio {
+	gpio-line-names =
+		"GSC_AP_INT_ODL",
+		"AP_DISP_BKLTEN",
+		"",
+		"EN_PPVAR_MIPI_DISP",
+		"EN_PPVAR_MIPI_DISP_150MA",
+		"TCHSCR_RST_1V8_L",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"I2S_SPKR_DATAOUT",
+		"EN_PP3300_WLAN_X",
+		"WIFI_KILL_1V8_L",
+		"BT_KILL_1V8_L",
+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
+		"",
+		"",
+		"WCAM_PWDN_L",
+		"WCAM_RST_L",
+		"UCAM_PWDM_L",
+		"UCAM_RST_L",
+		"WCAM_24M_CLK",
+		"UCAM_24M_CLK",
+		"MT6319_INT",
+		"DISP_RST_1V8_L",
+		"DSIO_DSI_TE",
+		"",
+		"TP",
+		"MIPI_BL_PWM_1V8",
+		"",
+		"UART_AP_TX_GSC_RX",
+		"UART_GSC_TX_AP_RX",
+		"UART_SSPM_TX_DBGCON_RX",
+		"UART_DBGCON_TX_SSPM_RX",
+		"UART_ADSP_TX_DBGCON_RX",
+		"UART_DBGCON_TX_ADSP_RX",
+		"JTAG_AP_TMS",
+		"JTAG_AP_TCK",
+		"JTAG_AP_TDI",
+		"JTAG_AP_TDO",
+		"JTAG_AP_TRST",
+		"AP_KPCOL0",
+		"TP",
+		"",
+		"TP",
+		"EC_AP_HPD_OD",
+		"PCIE_WAKE_1V8_ODL",
+		"PCIE_RST_1V8_L",
+		"PCIE_CLKREQ_1V8_ODL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"AP_I2C_AUD_SCL_1V8",
+		"AP_I2C_AUD_SDA_1V8",
+		"AP_I2C_TPM_SCL_1V8",
+		"AP_I2C_TPM_SDA_1V8",
+		"AP_I2C_TCHSCR_SCL_1V8",
+		"AP_I2C_TCHSCR_SDA_1V8",
+		"AP_I2C_PMIC_SAR_SCL_1V8",
+		"AP_I2C_PMIC_SAR_SDA_1V8",
+		"AP_I2C_EC_HID_KB_SCL_1V8",
+		"AP_I2C_EC_HID_KB_SDA_1V8",
+		"AP_I2C_UCAM_SCL_1V8",
+		"AP_I2C_UCAM_SDA_1V8",
+		"AP_I2C_WCAM_SCL_1V8",
+		"AP_I2C_WCAM_SDA_1V8",
+		"SPI_AP_CS_EC_L",
+		"SPI_AP_CLK_EC",
+		"SPI_AP_DO_EC_DI",
+		"SPI_AP_DI_EC_DO",
+		"TP",
+		"TP",
+		"SPI_AP_CS_TCHSCR_L",
+		"SPI_AP_CLK_TCHSCR",
+		"SPI_AP_DO_TCHSCR_DI",
+		"SPI_AP_DI_TCHSCR_DO",
+		"TP",
+		"TP",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"PWRAP_SPI_CS_L",
+		"PWRAP_SPI_CK",
+		"PWRAP_SPI_MOSI",
+		"PWRAP_SPI_MISO",
+		"SRCLKENA0",
+		"SRCLKENA1",
+		"SCP_VREQ_VAO",
+		"AP_RTC_CLK32K",
+		"AP_PMIC_WDTRST_L",
+		"AUD_CLK_MOSI",
+		"AUD_SYNC_MOSI",
+		"AUD_DAT_MOSI0",
+		"AUD_DAT_MOSI1",
+		"AUD_DAT_MISO0",
+		"AUD_DAT_MISO1",
+		"",
+		"HP_INT_ODL",
+		"SPKR_INT_ODL",
+		"I2S_HP_DATAIN",
+		"EN_SPKR",
+		"I2S_SPKR_MCLK",
+		"I2S_SPKR_BCLK",
+		"I2S_HP_MCLK",
+		"I2S_HP_BCLK",
+		"I2S_HP_LRCK",
+		"I2S_HP_DATAOUT",
+		"RST_SPKR_L",
+		"I2S_SPKR_LRCK",
+		"I2S_SPKR_DATAIN",
+		"",
+		"",
+		"",
+		"",
+		"SPI_AP_CLK_ROM",
+		"SPI_AP_CS_ROM_L",
+		"SPI_AP_DO_ROM_DI",
+		"SPI_AP_DI_ROM_DO",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"EN_PP2800A_UCAM_X",
+		"EN_PP1200_UCAM_X",
+		"EN_PP2800A_WCAM_X",
+		"EN_PP1100_WCAM_X",
+		"TCHSCR_INT_1V8_L",
+		"",
+		"MT7921_PMU_EN_1V8",
+		"",
+		"AP_EC_WARM_RST_REQ",
+		"EC_AP_HID_INT_ODL",
+		"EC_AP_INT_ODL",
+		"AP_XHCI_INIT_DONE",
+		"EMMC_DAT7",
+		"EMMC_DAT6",
+		"EMMC_DAT5",
+		"EMMC_DAT4",
+		"EMMC_RST_L",
+		"EMMC_CMD",
+		"EMMC_CLK",
+		"EMMC_DAT3",
+		"EMMC_DAT2",
+		"EMMC_DAT1",
+		"EMMC_DAT0",
+		"EMMC_DSL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"USB3_HUB_RST_L",
+		"EC_AP_RSVD0_ODL",
+		"",
+		"",
+		"SPMI_SCL",
+		"SPMI_SDA";
+
+	audio_codec_pins: audio-codec-pins {
+		pins-hp-int-odl {
+			pinmux = <PINMUX_GPIO108__FUNC_B_GPIO108>;
+			input-enable;
+		};
+	};
+
+	speaker_en: speaker-en-pins {
+		pins-en-spkr {
+			pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi b/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi
new file mode 100644
index 00000000000..b6abecbcfa8
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "mt8188.dtsi"
+#include "mt6359.dtsi"
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		mmc0 = &mmc0;
+		serial0 = &uart0;
+	};
+
+	backlight_lcd0: backlight-lcd0 {
+		compatible = "pwm-backlight";
+		brightness-levels = <0 1023>;
+		default-brightness-level = <576>;
+		enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		num-interpolated-steps = <1023>;
+		power-supply = <&ppvar_sys>;
+		pwms = <&disp_pwm0 0 500000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		wakeup-delay-ms = <100>;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* The size will be filled in by the bootloader */
+		reg = <0 0x40000000 0 0>;
+	};
+
+	/* system wide LDO 1.8V power rail */
+	pp1800_ldo_z1: regulator-pp1800-ldo-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_ldo_z1";
+		/* controlled by PP3300_Z1 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* separately switched 3.3V power rail */
+	pp3300_s3: regulator-pp3300-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_s3";
+		/* controlled by PMIC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* system wide 3.3V power rail */
+	pp3300_z1: regulator-pp3300-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_z1";
+		/* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	pp3300_wlan: regulator-pp3300-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_wlan";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&wlan_en>;
+		pinctrl-names = "default";
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* system wide 4.2V power rail */
+	pp4200_s5: regulator-pp4200-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp4200_s5";
+		/* controlled by EC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4200000>;
+		regulator-max-microvolt = <4200000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide 5.0V power rail */
+	pp5000_z1: regulator-pp5000-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_z1";
+		/* controlled by EC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	pp5000_usb_vbus: regulator-pp5000-usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 150 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	/* system wide semi-regulated power rail from battery or USB */
+	ppvar_sys: regulator-ppvar-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_mipi_disp_avdd";
+		enable-active-high;
+		gpio = <&pio 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_disp_avdd_en>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_mipi_disp_avee";
+		regulator-enable-ramp-delay = <10000>;
+		enable-active-high;
+		gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_disp_avee_en>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		apu_mem: memory@55000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x55000000 0 0x1400000>;
+		};
+
+		adsp_mem: memory@60000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60000000 0 0xf00000>;
+			no-map;
+		};
+
+		afe_dma_mem: memory@60f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60f00000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_dma_mem: memory@61000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x61000000 0 0x100000>;
+			no-map;
+		};
+	};
+};
+
+&adsp {
+	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&adsp_uart_pins>;
+	status = "okay";
+};
+
+&afe {
+	memory-region = <&afe_dma_mem>;
+	mediatek,etdm-out1-cowork-source = <0>; /* in1 */
+	mediatek,etdm-in2-cowork-source = <3>; /* out2 */
+	status = "okay";
+};
+
+&auxadc {
+	status = "okay";
+};
+
+&cam_vcore {
+	domain-supply = <&mt6359_vproc1_buck_reg>;
+};
+
+/*
+ * Geralt is the reference design and doesn't have target TDP.
+ * Ciri is (currently) the only device following Geralt, and its
+ * TDP target is 90 degrees.
+ **/
+&cpu_little0_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little1_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little2_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little3_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_big0_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_big1_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&disp_dsi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	dsi_panel: panel@0 {
+		/* Compatible string for different panels can be found in each device dts */
+		reg = <0>;
+		enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_dsi_pins>;
+
+		backlight = <&backlight_lcd0>;
+		avdd-supply = <&ppvar_mipi_disp_avdd>;
+		avee-supply = <&ppvar_mipi_disp_avee>;
+		pp1800-supply = <&mt6359_vm18_ldo_reg>;
+		rotation = <270>;
+
+		status = "okay";
+
+		port {
+			dsi_panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+
+	port {
+		dsi_out: endpoint {
+			remote-endpoint = <&dsi_panel_in>;
+		};
+	};
+};
+
+&disp_pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&disp_pwm0_pins>;
+	status = "okay";
+};
+
+&disp_pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&disp_pwm1_pins>;
+};
+
+&dp_intf1 {
+	status = "okay";
+
+	port {
+		dp_intf1_out: endpoint {
+			remote-endpoint = <&dptx_in>;
+		};
+	};
+};
+
+&dp_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp_tx_hpd>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dptx_in: endpoint {
+				remote-endpoint = <&dp_intf1_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dptx_out: endpoint {
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&mt6359_vproc2_buck_reg>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	tpm@50 {
+		compatible = "google,cr50";
+		reg = <0x50>;
+		interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsc_int>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&mfg0 {
+	domain-supply = <&mt6359_vproc2_buck_reg>;
+};
+
+&mfg1 {
+	domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
+&mipi_tx_config0 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	hs400-ds-delay = <0x1481b>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	supports-cqe;
+	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+	status = "okay";
+};
+
+&mt6359codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+	mediatek,mic-type-0 = <2>; /* DMIC */
+	mediatek,mic-type-2 = <2>; /* DMIC */
+};
+
+&mt6359_vcore_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_sshub_buck_reg {
+	regulator-min-microvolt = <550000>;
+	regulator-max-microvolt = <550000>;
+	regulator-always-on;
+};
+
+&mt6359_vio28_ldo_reg {
+	/delete-property/ regulator-always-on;
+};
+
+&mt6359_vm18_ldo_reg {
+	/delete-property/ regulator-always-on;
+};
+
+&mt6359_vmodem_buck_reg {
+	regulator-min-microvolt = <775000>;
+	regulator-max-microvolt = <775000>;
+};
+
+&mt6359_vpa_buck_reg {
+	regulator-max-microvolt = <3100000>;
+};
+
+&mt6359_vproc2_buck_reg {
+	/*
+	 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to
+	 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements.
+	 */
+	regulator-name = "ppvar_dvdd_vgpu";
+	regulator-min-microvolt = <550000>;
+	regulator-max-microvolt = <800000>;
+	regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
+	regulator-coupled-max-spread = <6250>;
+};
+
+&mt6359_vpu_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+	regulator-min-microvolt = <800000>;
+	regulator-max-microvolt = <800000>;
+};
+
+&mt6359_vsram_others_ldo_reg {
+	regulator-name = "pp0850_dvdd_sram_gpu";
+	regulator-min-microvolt = <750000>;
+	regulator-max-microvolt = <800000>;
+	regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
+	regulator-coupled-max-spread = <6250>;
+};
+
+&mt6359_vufs_ldo_reg {
+	regulator-always-on;
+};
+
+&nor_flash {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nor_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
+};
+
+&pciephy {
+	status = "okay";
+};
+
+&pio {
+	gpio-line-names =
+		"gsc_int",
+		"AP_DISP_BKLTEN",
+		"",
+		"EN_PPVAR_MIPI_DISP",
+		"EN_PPVAR_MIPI_DISP_150MA",
+		"TCHSCR_RST_1V8_L",
+		"TCHSRC_REPORT_DISABLE",
+		"",
+		"",
+		"",
+		"",
+		"I2S_SPKR_DATAOUT",
+		"EN_PP3300_WLAN_X",
+		"WIFI_KILL_1V8_L",
+		"BT_KILL_1V8_L",
+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
+		"",
+		"EDP_HPD_1V8",
+		"WCAM_PWDN_L",
+		"WCAM_RST_L",
+		"UCAM_PWDM_L",
+		"UCAM_RST_L",
+		"WCAM_24M_CLK",
+		"UCAM_24M_CLK",
+		"MT6319_INT",
+		"DISP_RST_1V8_L",
+		"DSIO_DSI_TE",
+		"EN_PP3300_EDP_DISP_X",
+		"TP",
+		"MIPI_BL_PWM_1V8",
+		"EDP_BL_PWM_1V8",
+		"UART_AP_TX_GSC_RX",
+		"UART_GSC_TX_AP_RX",
+		"UART_SSPM_TX_DBGCON_RX",
+		"UART_DBGCON_TX_SSPM_RX",
+		"UART_ADSP_TX_DBGCON_RX",
+		"UART_DBGCON_TX_ADSP_RX",
+		"JTAG_AP_TMS",
+		"JTAG_AP_TCK",
+		"JTAG_AP_TDI",
+		"JTAG_AP_TDO",
+		"JTAG_AP_TRST",
+		"AP_KPCOL0",
+		"TP",
+		"BEEP_ON_OD",
+		"TP",
+		"EC_AP_HPD_OD",
+		"PCIE_WAKE_1V8_ODL",
+		"PCIE_RST_1V8_L",
+		"PCIE_CLKREQ_1V8_ODL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"AP_I2C_AUD_SCL_1V8",
+		"AP_I2C_AUD_SDA_1V8",
+		"AP_I2C_TPM_SCL_1V8",
+		"AP_I2C_TPM_SDA_1V8",
+		"AP_I2C_TCHSCR_SCL_1V8",
+		"AP_I2C_TCHSCR_SDA_1V8",
+		"AP_I2C_PMIC_SAR_SCL_1V8",
+		"AP_I2C_PMIC_SAR_SDA_1V8",
+		"AP_I2C_EC_HID_KB_SCL_1V8",
+		"AP_I2C_EC_HID_KB_SDA_1V8",
+		"AP_I2C_UCAM_SCL_1V8",
+		"AP_I2C_UCAM_SDA_1V8",
+		"AP_I2C_WCAM_SCL_1V8",
+		"AP_I2C_WCAM_SDA_1V8",
+		"SPI_AP_CS_EC_L",
+		"SPI_AP_CLK_EC",
+		"SPI_AP_DO_EC_DI",
+		"SPI_AP_DI_EC_DO",
+		"TP",
+		"TP",
+		"SPI_AP_CS_TCHSCR_L",
+		"SPI_AP_CLK_TCHSCR",
+		"SPI_AP_DO_TCHSCR_DI",
+		"SPI_AP_DI_TCHSCR_DO",
+		"TP",
+		"TP",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"TP",
+		"",
+		"SAR_INT_ODL",
+		"",
+		"",
+		"",
+		"PWRAP_SPI_CS_L",
+		"PWRAP_SPI_CK",
+		"PWRAP_SPI_MOSI",
+		"PWRAP_SPI_MISO",
+		"SRCLKENA0",
+		"SRCLKENA1",
+		"SCP_VREQ_VAO",
+		"AP_RTC_CLK32K",
+		"AP_PMIC_WDTRST_L",
+		"AUD_CLK_MOSI",
+		"AUD_SYNC_MOSI",
+		"AUD_DAT_MOSI0",
+		"AUD_DAT_MOSI1",
+		"AUD_DAT_MISO0",
+		"AUD_DAT_MISO1",
+		"SD_CD_ODL",
+		"HP_INT_ODL",
+		"SPKR_INT_ODL",
+		"I2S_HP_DATAIN",
+		"EN_SPKR",
+		"I2S_SPKR_MCLK",
+		"I2S_SPKR_BCLK",
+		"I2S_HP_MCLK",
+		"I2S_HP_BCLK",
+		"I2S_HP_LRCK",
+		"I2S_HP_DATAOUT",
+		"RST_SPKR_L",
+		"I2S_SPKR_LRCK",
+		"I2S_SPKR_DATAIN",
+		"",
+		"",
+		"",
+		"",
+		"SPI_AP_CLK_ROM",
+		"SPI_AP_CS_ROM_L",
+		"SPI_AP_DO_ROM_DI",
+		"SPI_AP_DI_ROM_DO",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"EN_PP2800A_UCAM_X",
+		"EN_PP1200_UCAM_X",
+		"EN_PP2800A_WCAM_X",
+		"EN_PP1100_WCAM_X",
+		"TCHSCR_INT_1V8_L",
+		"EN_PP3300_MIPI_TCHSCR_X",
+		"MT7921_PMU_EN_1V8",
+		"EN_PP3300_EDP_TCHSCR_X",
+		"AP_EC_WARM_RST_REQ",
+		"EC_AP_HID_INT_ODL",
+		"EC_AP_INT_ODL",
+		"AP_XHCI_INIT_DONE",
+		"EMMC_DAT7",
+		"EMMC_DAT6",
+		"EMMC_DAT5",
+		"EMMC_DAT4",
+		"EMMC_RST_L",
+		"EMMC_CMD",
+		"EMMC_CLK",
+		"EMMC_DAT3",
+		"EMMC_DAT2",
+		"EMMC_DAT1",
+		"EMMC_DAT0",
+		"EMMC_DSL",
+		"SD_CMD",
+		"SD_CLK",
+		"SD_DAT0",
+		"SD_DAT1",
+		"SD_DAT2",
+		"SD_DAT3",
+		"",
+		"",
+		"USB3_HUB_RST_L",
+		"EC_AP_RSVD0_ODL",
+		"",
+		"",
+		"SPMI_SCL",
+		"SPMI_SDA";
+
+	adsp_uart_pins: adsp-uart-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
+				 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
+		};
+	};
+
+	aud_etdm_hp_on: aud-etdm-hp-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>,
+				 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>,
+				 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>,
+				 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>;
+		};
+	};
+
+	aud_etdm_hp_off: aud-etdm-hp-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>,
+				 <PINMUX_GPIO115__FUNC_B_GPIO115>,
+				 <PINMUX_GPIO116__FUNC_B_GPIO116>,
+				 <PINMUX_GPIO117__FUNC_B_GPIO117>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	aud_etdm_spk_on: aud-etdm-spk-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>,
+				 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>,
+				 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>,
+				 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>;
+			drive-strength = <8>;
+		};
+	};
+
+	aud_etdm_spk_off: aud-etdm-spk-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>,
+				 <PINMUX_GPIO113__FUNC_B_GPIO113>,
+				 <PINMUX_GPIO119__FUNC_B_GPIO119>,
+				 <PINMUX_GPIO120__FUNC_B_GPIO120>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	aud_mtkaif_on: aud-mtkaif-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>,
+				 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>,
+				 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>,
+				 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>,
+				 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>,
+				 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>;
+		};
+	};
+
+	aud_mtkaif_off: aud-mtkaif-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>,
+				 <PINMUX_GPIO102__FUNC_B_GPIO102>,
+				 <PINMUX_GPIO103__FUNC_B_GPIO103>,
+				 <PINMUX_GPIO104__FUNC_B_GPIO104>,
+				 <PINMUX_GPIO105__FUNC_B_GPIO105>,
+				 <PINMUX_GPIO106__FUNC_B_GPIO106>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	cros_ec_int: cros-ec-int-pins {
+		pins-ec-ap-int-odl {
+			pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>;
+			input-enable;
+		};
+	};
+
+	disp_pwm0_pins: disp-pwm0-pins {
+		pins-disp-pwm0 {
+			pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>;
+			output-high;
+		};
+	};
+
+	disp_pwm1_pins: disp-pwm1-pins {
+		pins-disp-pwm1 {
+			pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>;
+			output-high;
+		};
+	};
+
+	dp_tx_hpd: dp-tx-hpd-pins {
+		pins-dp-tx-hpd {
+			pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
+		};
+	};
+
+	gsc_int: gsc-int-pins {
+		pins-gsc-ap-int-odl {
+			pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
+			input-enable;
+		};
+	};
+
+	i2c0_pins: i2c0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
+				 <PINMUX_GPIO55__FUNC_B1_SCL0>;
+		};
+	};
+
+	i2c1_pins: i2c1-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
+				 <PINMUX_GPIO57__FUNC_B1_SCL1>;
+		};
+	};
+
+	i2c2_pins: i2c2-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
+				 <PINMUX_GPIO59__FUNC_B1_SCL2>;
+			bias-disable;
+			drive-strength = <12>;
+		};
+	};
+
+	i2c3_pins: i2c3-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
+				 <PINMUX_GPIO61__FUNC_B1_SCL3>;
+		};
+	};
+
+	i2c4_pins: i2c4-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
+				 <PINMUX_GPIO63__FUNC_B1_SCL4>;
+		};
+	};
+
+	i2c5_pins: i2c5-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
+				 <PINMUX_GPIO65__FUNC_B1_SCL5>;
+		};
+	};
+
+	i2c6_pins: i2c6-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
+				 <PINMUX_GPIO67__FUNC_B1_SCL6>;
+		};
+	};
+
+	mipi_disp_avdd_en: mipi-disp-avdd-en-pins {
+		pins-en-ppvar-mipi-disp {
+			pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>;
+			output-low;
+		};
+	};
+
+	mipi_disp_avee_en: mipi-disp-avee-en-pins {
+		pins-en-ppvar-mipi-disp-150ma {
+			pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>;
+			output-low;
+		};
+	};
+
+	mipi_dsi_pins: mipi-dsi-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>,
+				 <PINMUX_GPIO25__FUNC_B_GPIO25>;
+			output-low;
+		};
+	};
+
+	mmc0_pins_default: mmc0-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <6>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+			drive-strength = <6>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+			drive-strength = <6>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	mmc0_pins_uhs: mmc0-uhs-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-ds {
+			pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	nor_pins: nor-default-pins {
+		pins-clk {
+			pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
+				 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
+				 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
+			bias-pull-down;
+		};
+
+		pins-cs {
+			pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>;
+			bias-pull-up;
+		};
+	};
+
+	pcie_pins: pcie-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
+				 <PINMUX_GPIO48__FUNC_O_PERSTN>,
+				 <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
+				 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
+				 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
+				 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
+			bias-disable;
+		};
+	};
+
+	spi1_pins_default: spi1-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
+				 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
+				 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
+				 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
+			bias-disable;
+		};
+	};
+
+	spi1_pins_sleep: spi1-sleep-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>,
+				 <PINMUX_GPIO76__FUNC_B_GPIO76>,
+				 <PINMUX_GPIO77__FUNC_B_GPIO77>,
+				 <PINMUX_GPIO78__FUNC_B_GPIO78>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
+				 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
+				 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
+				 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
+			bias-disable;
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
+				 <PINMUX_GPIO32__FUNC_I1_URXD0>;
+			bias-pull-up;
+		};
+	};
+
+	wlan_en: wlan-en-pins {
+		pins-en-pp3300-wlan {
+			pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
+			output-low;
+		};
+	};
+};
+
+&pmic {
+	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sound {
+	pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",
+			"aud_etdm_spk_on", "aud_etdm_spk_off",
+			"aud_mtkaif_on", "aud_mtkaif_off";
+	pinctrl-0 = <&aud_etdm_hp_on>;
+	pinctrl-1 = <&aud_etdm_hp_off>;
+	pinctrl-2 = <&aud_etdm_spk_on>;
+	pinctrl-3 = <&aud_etdm_spk_off>;
+	pinctrl-4 = <&aud_mtkaif_on>;
+	pinctrl-5 = <&aud_mtkaif_off>;
+	mediatek,adsp = <&adsp>;
+	/* The audio-routing is defined in each board dts */
+
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+
+	cros_ec: ec@0 {
+		compatible = "google,cros-ec-spi";
+		reg = <0>;
+		interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cros_ec_int>;
+		spi-max-frequency = <3000000>;
+
+		i2c_tunnel: i2c-tunnel {
+			compatible = "google,cros-ec-i2c-tunnel";
+			google,remote-bus = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		cbas {
+			compatible = "google,cros-cbas";
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&spi1_pins_default>;
+	pinctrl-1 = <&spi1_pins_sleep>;
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&u3phy0 {
+	status = "okay";
+};
+
+&u3phy1 {
+	status = "okay";
+};
+
+&u3phy2 {
+	status = "okay";
+};
+
+/* USB detachable base */
+&xhci0 {
+	/* controlled by EC */
+	vbus-supply = <&pp3300_z1>;
+	status = "okay";
+};
+
+/* USB3 hub */
+&xhci1 {
+	vusb33-supply = <&pp3300_s3>;
+	vbus-supply = <&pp5000_usb_vbus>;
+	status = "okay";
+};
+
+/* USB BT */
+&xhci2 {
+	/* no power supply since MT7921's power is controlled by PCIe */
+	/* MT7921's USB BT has issues with USB2 LPM */
+	usb2-lpm-disable;
+	status = "okay";
+};
+
+#include <arm/cros-ec-keyboard.dtsi>
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188.dtsi b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
index faccc7f1625..338120930b8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8188.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
@@ -2125,6 +2125,11 @@
 				reg = <0x1ac 0x40>;
 			};
 
+			gpu_speedbin: gpu-speedbin@581 {
+				reg = <0x581 0x1>;
+				bits = <0 3>;
+			};
+
 			socinfo-data1@7a0 {
 				reg = <0x7a0 0x4>;
 			};
@@ -2143,6 +2148,8 @@
 				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
 				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "job", "mmu", "gpu";
+			nvmem-cells = <&gpu_speedbin>;
+			nvmem-cell-names = "speed-bin";
 			operating-points-v2 = <&gpu_opp_table>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
 					<&spm MT8188_POWER_DOMAIN_MFG3>,
@@ -2488,7 +2495,7 @@
 		};
 
 		ovl0: ovl@1c000000 {
-			compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl";
+			compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";
 			reg = <0 0x1c000000 0 0x1000>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
 			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
deleted file mode 100644
index cd86ad9ba28..00000000000
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2022 Google LLC
- */
-/dts-v1/;
-#include "mt8192-asurada.dtsi"
-
-/ {
-	model = "Google Hayato rev5";
-	chassis-type = "convertible";
-	compatible = "google,hayato-rev5-sku2", "google,hayato-sku2",
-		     "google,hayato", "mediatek,mt8192";
-};
-
-&keyboard_controller {
-	function-row-physmap = <
-		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
-		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
-		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
-		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
-		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
-		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
-		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
-		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
-		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
-		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
-	>;
-	linux,keymap = <
-		MATRIX_KEY(0x00, 0x02, KEY_BACK)
-		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
-		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
-		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
-		MATRIX_KEY(0x03, 0x04, KEY_SCALE)
-		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
-		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
-		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
-		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
-		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
-		CROS_STD_MAIN_KEYMAP
-	>;
-};
-
-&rt5682 {
-	compatible = "realtek,rt5682s";
-};
-
-&sound {
-	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s";
-
-	speaker-codecs {
-		sound-dai = <&rt1015p>;
-	};
-
-	headset-codec {
-		sound-dai = <&rt5682 0>;
-	};
-};
-
-&touchscreen {
-	compatible = "hid-over-i2c";
-	post-power-on-delay-ms = <10>;
-	hid-descr-addr = <0x0001>;
-	vdd-supply = <&pp3300_u>;
-};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
deleted file mode 100644
index 5e9e598bab9..00000000000
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2022 Google LLC
- */
-/dts-v1/;
-#include "mt8192-asurada.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Google Spherion (rev4)";
-	chassis-type = "laptop";
-	compatible = "google,spherion-rev4", "google,spherion",
-		     "mediatek,mt8192";
-
-	pwmleds {
-		compatible = "pwm-leds";
-
-		led {
-			function = LED_FUNCTION_KBD_BACKLIGHT;
-			color = <LED_COLOR_ID_WHITE>;
-			pwms = <&cros_ec_pwm 0>;
-			max-brightness = <1023>;
-		};
-	};
-};
-
-&cros_ec_pwm {
-	status = "okay";
-};
-
-&keyboard_controller {
-	function-row-physmap = <
-		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
-		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
-		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
-		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
-		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
-		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
-		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
-		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
-		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
-		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
-	>;
-	linux,keymap = <
-		MATRIX_KEY(0x00, 0x02, KEY_BACK)
-		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
-		MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
-		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
-		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
-		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
-		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
-		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
-		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
-		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
-		CROS_STD_MAIN_KEYMAP
-	>;
-};
-
-&rt5682 {
-	compatible = "realtek,rt5682s";
-};
-
-&sound {
-	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s";
-
-	speaker-codecs {
-		sound-dai = <&rt1015p>;
-	};
-
-	headset-codec {
-		sound-dai = <&rt5682 0>;
-	};
-};
-
-&touchscreen {
-	compatible = "elan,ekth3500";
-};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
index 8dda8b63765..dd0d07fbe61 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
@@ -1418,7 +1418,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1428,7 +1427,6 @@
 			};
 
 			mt6315_6_vbuck3: vbuck3 {
-				regulator-compatible = "vbuck3";
 				regulator-name = "Vlcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1445,7 +1443,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <800000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
index 2c7b2223ee7..5056e07399e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
@@ -1285,7 +1285,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1303,7 +1302,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
index 31d424b8fc7..1f59b5786b8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
@@ -109,6 +109,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default_pins>;
 	pinctrl-1 = <&eth_sleep_pins>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
@@ -137,7 +138,6 @@
 			richtek,vinovp-microvolt = <14500000>;
 
 			otg_vbus_regulator: usb-otg-vbus-regulator {
-				regulator-compatible = "usb-otg-vbus";
 				regulator-name = "usb-otg-vbus";
 				regulator-min-microvolt = <4425000>;
 				regulator-max-microvolt = <5825000>;
@@ -149,7 +149,6 @@
 			LDO_VIN3-supply = <&mt6360_buck2>;
 
 			mt6360_buck1: buck1 {
-				regulator-compatible = "BUCK1";
 				regulator-name = "mt6360,buck1";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1300000>;
@@ -160,7 +159,6 @@
 			};
 
 			mt6360_buck2: buck2 {
-				regulator-compatible = "BUCK2";
 				regulator-name = "mt6360,buck2";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1300000>;
@@ -171,7 +169,6 @@
 			};
 
 			mt6360_ldo1: ldo1 {
-				regulator-compatible = "LDO1";
 				regulator-name = "mt6360,ldo1";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -180,7 +177,6 @@
 			};
 
 			mt6360_ldo2: ldo2 {
-				regulator-compatible = "LDO2";
 				regulator-name = "mt6360,ldo2";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -189,7 +185,6 @@
 			};
 
 			mt6360_ldo3: ldo3 {
-				regulator-compatible = "LDO3";
 				regulator-name = "mt6360,ldo3";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -198,7 +193,6 @@
 			};
 
 			mt6360_ldo5: ldo5 {
-				regulator-compatible = "LDO5";
 				regulator-name = "mt6360,ldo5";
 				regulator-min-microvolt = <2700000>;
 				regulator-max-microvolt = <3600000>;
@@ -207,7 +201,6 @@
 			};
 
 			mt6360_ldo6: ldo6 {
-				regulator-compatible = "LDO6";
 				regulator-name = "mt6360,ldo6";
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <2100000>;
@@ -216,7 +209,6 @@
 			};
 
 			mt6360_ldo7: ldo7 {
-				regulator-compatible = "LDO7";
 				regulator-name = "mt6360,ldo7";
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <2100000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195.dtsi b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
index ade685ed219..f013dbad9dc 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
@@ -1611,9 +1611,6 @@
 			phy-names = "pcie-phy";
 			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 
-			resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
-			reset-names = "mac";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
@@ -3138,7 +3135,7 @@
 		};
 
 		ovl0: ovl@1c000000 {
-			compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
+			compatible = "mediatek,mt8195-disp-ovl";
 			reg = <0 0x1c000000 0 0x1000>;
 			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
index 7d90112a7e2..44c61094c4d 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
@@ -21,6 +21,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		ethernet = &ethernet;
 	};
 
 	chosen {
diff --git a/dts/upstream/src/arm64/mediatek/mt8365.dtsi b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
index 9c91fe8ea0f..2bf8c9d02b6 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
@@ -449,7 +449,8 @@
 		};
 
 		keypad: keypad@10010000 {
-			compatible = "mediatek,mt6779-keypad";
+			compatible = "mediatek,mt8365-keypad",
+				     "mediatek,mt6779-keypad";
 			reg = <0 0x10010000 0 0x1000>;
 			wakeup-source;
 			interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
index 13f2e0e3fa8..04e4a2f7379 100644
--- a/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
@@ -93,6 +93,24 @@
 			compatible = "shared-dma-pool";
 			reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
 		};
+
+		adsp_mem: memory@60000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60000000 0 0xf00000>;
+			no-map;
+		};
+
+		afe_dma_mem: memory@60f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60f00000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_dma_mem: memory@61000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x61000000 0 0x100000>;
+			no-map;
+		};
 	};
 
 	common_fixed_5v: regulator-0 {
@@ -210,6 +228,16 @@
 	};
 };
 
+&adsp {
+	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+	status = "okay";
+};
+
+&afe {
+	memory-region = <&afe_dma_mem>;
+	status = "okay";
+};
+
 &gpu {
 	mali-supply = <&mt6359_vproc2_buck_reg>;
 	status = "okay";
@@ -932,6 +960,26 @@
 	status = "okay";
 };
 
+&sound {
+	compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
+	model = "mt8390-evk";
+	pinctrl-names = "default";
+	pinctrl-0 = <&audio_default_pins>;
+	audio-routing =
+		"Headphone", "Headphone L",
+		"Headphone", "Headphone R";
+	mediatek,adsp = <&adsp>;
+	status = "okay";
+
+	dai-link-0 {
+		link-name = "DL_SRC_BE";
+
+		codec {
+			sound-dai = <&pmic 0>;
+		};
+	};
+};
+
 &spi2 {
 	pinctrl-0 = <&spi2_pins>;
 	pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
index 5f16fb82058..5950194c9cc 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
@@ -835,7 +835,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
@@ -852,7 +851,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <546000>;
 				regulator-max-microvolt = <787000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
index e2e75b8ff91..4985b65925a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
@@ -271,6 +271,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default_pins>;
 	pinctrl-1 = <&eth_sleep_pins>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
index 14ec970c4e4..41dc34837b0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
@@ -812,7 +812,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
@@ -829,7 +828,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8516.dtsi b/dts/upstream/src/arm64/mediatek/mt8516.dtsi
index d0b03dc4d3f..b5e75375946 100644
--- a/dts/upstream/src/arm64/mediatek/mt8516.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8516.dtsi
@@ -144,10 +144,10 @@
 		#size-cells = <2>;
 		ranges;
 
-		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 		bl31_secmon_reserved: secmon@43000000 {
 			no-map;
-			reg = <0 0x43000000 0 0x20000>;
+			reg = <0 0x43000000 0 0x30000>;
 		};
 	};
 
@@ -206,7 +206,7 @@
 			compatible = "mediatek,mt8516-wdt",
 				     "mediatek,mt6589-wdt";
 			reg = <0 0x10007000 0 0x1000>;
-			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 			#reset-cells = <1>;
 		};
 
@@ -220,6 +220,17 @@
 			clock-names = "clk13m", "bus";
 		};
 
+		keypad: keypad@10002000 {
+			compatible = "mediatek,mt8516-keypad",
+				     "mediatek,mt6779-keypad";
+			reg = <0 0x10002000 0 0x1000>;
+			wakeup-source;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_FALLING>;
+			clocks = <&clk26m>;
+			clock-names = "kpd";
+			status = "disabled";
+		};
+
 		syscfg_pctl: syscfg-pctl@10005000 {
 			compatible = "syscon";
 			reg = <0 0x10005000 0 0x1000>;
@@ -268,7 +279,7 @@
 			interrupt-parent = <&gic>;
 			interrupt-controller;
 			reg = <0 0x10310000 0 0x1000>,
-			      <0 0x10320000 0 0x1000>,
+			      <0 0x1032f000 0 0x2000>,
 			      <0 0x10340000 0 0x2000>,
 			      <0 0x10360000 0 0x2000>;
 			interrupts = <GIC_PPI 9
@@ -344,6 +355,7 @@
 			reg = <0 0x11009000 0 0x90>,
 			      <0 0x11000180 0 0x80>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C0>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
@@ -358,6 +370,7 @@
 			reg = <0 0x1100a000 0 0x90>,
 			      <0 0x11000200 0 0x80>;
 			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C1>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
@@ -372,6 +385,7 @@
 			reg = <0 0x1100b000 0 0x90>,
 			      <0 0x11000280 0 0x80>;
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C2>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
diff --git a/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi b/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
index ec8dfb3d1c6..a356db5fcc5 100644
--- a/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
+++ b/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
@@ -47,7 +47,6 @@
 };
 
 &i2c0 {
-	clock-div = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
@@ -156,7 +155,6 @@
 };
 
 &i2c2 {
-	clock-div = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/nvidia/tegra234.dtsi b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
index 984c85eab41..2601b43b2d8 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234.dtsi
+++ b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
@@ -3815,7 +3815,7 @@
 			compatible = "nvidia,tegra234-sce-fabric";
 			reg = <0x0 0xb600000 0x0 0x40000>;
 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		rce-fabric@be00000 {
@@ -3900,7 +3900,7 @@
 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 			resets = <&bpmp TEGRA234_RESET_SPI2>;
 			reset-names = "spi";
-			dmas = <&gpcdma 19>, <&gpcdma 19>;
+			dmas = <&gpcdma 16>, <&gpcdma 16>;
 			dma-names = "rx", "tx";
 			dma-coherent;
 			status = "disabled";
@@ -3995,7 +3995,7 @@
 		};
 
 		dce-fabric@de00000 {
-			compatible = "nvidia,tegra234-sce-fabric";
+			compatible = "nvidia,tegra234-dce-fabric";
 			reg = <0x0 0xde00000 0x0 0x40000>;
 			interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
 			status = "okay";
@@ -4018,6 +4018,8 @@
 			#redistributor-regions = <1>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
+
+			#address-cells = <0>;
 		};
 
 		smmu_iso: iommu@10000000 {
diff --git a/dts/upstream/src/arm64/qcom/ipq5332.dtsi b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
index d3c3e215a15..ca3da95730b 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
@@ -180,7 +180,7 @@
 		};
 
 		rng: rng@e3000 {
-			compatible = "qcom,prng-ee";
+			compatible = "qcom,ipq5332-trng", "qcom,trng";
 			reg = <0x000e3000 0x1000>;
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 			clock-names = "core";
diff --git a/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts b/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts
new file mode 100644
index 00000000000..b6e4bb3328b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5424 RDP466 board device tree source
+ *
+ * Copyright (c) 2024 The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5424.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
+	compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	vreg_misc_3p3: regulator-usb-3p3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "usb_hs_vdda_3p3";
+	};
+
+	vreg_misc_1p8: regulator-usb-1p8 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vdda_1p8_usb";
+	};
+
+	vreg_misc_0p925: regulator-usb-0p925 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <925000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vdd_core_usb";
+	};
+};
+
+&dwc_0 {
+	dr_mode = "host";
+};
+
+&dwc_1 {
+	dr_mode = "host";
+};
+
+&qusb_phy_0 {
+	vdd-supply = <&vreg_misc_0p925>;
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+	status = "okay";
+};
+
+&qusb_phy_1 {
+	vdd-supply = <&vreg_misc_0p925>;
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&ssphy_0 {
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-supply = <&vreg_misc_0p925>;
+
+	status = "okay";
+};
+
+&tlmm {
+	spi0_default_state: spi0-default-state {
+		clk-pins {
+			pins = "gpio6";
+			function = "spi0_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		cs-pins {
+			pins = "gpio7";
+			function = "spi0_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		miso-pins {
+			pins = "gpio8";
+			function = "spi0_miso";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mosi-pins {
+			pins = "gpio9";
+			function = "spi0_mosi";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	sdc_default_state: sdc-default-state {
+		clk-pins {
+			pins = "gpio5";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cmd-pins {
+			pins = "gpio4";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio0", "gpio1", "gpio2", "gpio3";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <24000000>;
+};
+
diff --git a/dts/upstream/src/arm64/qcom/ipq5424.dtsi b/dts/upstream/src/arm64/qcom/ipq5424.dtsi
new file mode 100644
index 00000000000..7034d378b1e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq5424.dtsi
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5424 device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&intc>;
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		xo_board: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+
+				l3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x100>;
+			next-level-cache = <&l2_100>;
+
+			l2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x200>;
+			next-level-cache = <&l2_200>;
+
+			l2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x300>;
+			next-level-cache = <&l2_300>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-ipq5424", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x25100>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu-dsu {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz@8a600000 {
+			reg = <0x0 0x8a600000 0x0 0x200000>;
+			no-map;
+		};
+
+		smem@8a800000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x8a800000 0x0 0x32000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+		};
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		rng: rng@4c3000 {
+			compatible = "qcom,ipq5424-trng", "qcom,trng";
+			reg = <0 0x004c3000 0 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		system-cache-controller@800000 {
+			compatible = "qcom,ipq5424-llcc";
+			reg = <0 0x00800000 0 0x200000>;
+			reg-names = "llcc0_base";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,ipq5424-tlmm";
+			reg = <0 0x01000000 0 0x300000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 50>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart1_pins: uart1-state {
+				pins = "gpio43", "gpio44";
+				function = "uart1";
+				drive-strength = <8>;
+				bias-pull-up;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,ipq5424-gcc";
+			reg = <0 0x01800000 0 0x40000>;
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#interconnect-cells = <1>;
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0 0x01905000 0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-ipq5424", "syscon";
+			reg = <0 0x01937000 0 0x2a000>;
+		};
+
+		qupv3: geniqup@1ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x01ac0000 0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
+				 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			#address-cells = <2>;
+			#size-cells = <2>;
+
+			uart1: serial@1a84000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x01a84000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_UART1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			spi0: spi@1a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x01a90000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi1: spi@1a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x01a94000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		sdhc: mmc@7804000 {
+			compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@f200000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0xf200000 0 0x10000>, /* GICD */
+			      <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
+			#interrupt-cells = <0x3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			mbi-ranges = <672 128>;
+			msi-controller;
+		};
+
+		watchdog@f410000 {
+			compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
+			reg = <0 0x0f410000 0 0x1000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&sleep_clk>;
+		};
+
+		qusb_phy_1: phy@71000 {
+			compatible = "qcom,ipq5424-qusb2-phy";
+			reg = <0 0x00071000 0 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				<&xo_board>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+			status = "disabled";
+		};
+
+		usb2: usb2@1e00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+			reg = <0 0x01ef8800 0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB1_MASTER_CLK>,
+				 <&gcc GCC_USB1_SLEEP_CLK>,
+				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_CNOC_USB_CLK>;
+
+			clock-names = "core",
+				      "sleep",
+				      "mock_utmi",
+				      "iface",
+				      "cfg_noc";
+
+			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <24000000>;
+
+			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			resets = <&gcc GCC_USB1_BCR>;
+			qcom,select-utmi-as-pipe-clk;
+			status = "disabled";
+
+			dwc_1: usb@1e00000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x01e00000 0 0xe000>;
+				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_1>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		qusb_phy_0: phy@7b000 {
+			compatible = "qcom,ipq5424-qusb2-phy";
+			reg = <0 0x0007b000 0 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				<&xo_board>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+			status = "disabled";
+		};
+
+		ssphy_0: phy@7d000 {
+			compatible = "qcom,ipq5424-qmp-usb3-phy";
+			reg = <0 0x0007d000 0 0xa00>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_AUX_CLK>,
+				 <&xo_board>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB0_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets = <&gcc GCC_USB0_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_phy";
+
+			#clock-cells = <0>;
+			clock-output-names = "usb0_pipe_clk";
+
+			status = "disabled";
+		};
+
+		usb3: usb3@8a00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+			reg = <0 0x08af8800 0 0x400>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_CNOC_USB_CLK>;
+
+			clock-names = "core",
+				      "sleep",
+				      "mock_utmi",
+				      "iface",
+				      "cfg_noc";
+
+			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <24000000>;
+
+			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			resets = <&gcc GCC_USB_BCR>;
+			status = "disabled";
+
+			dwc_0: usb@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x08a00000 0 0xcd00>;
+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_0>, <&ssphy_0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+			};
+		};
+
+		timer@f420000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0xf420000 0 0x1000>;
+			ranges = <0 0 0 0x10000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@f421000 {
+				reg = <0xf421000 0x1000>,
+				      <0xf422000 0x1000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <0>;
+			};
+
+			frame@f423000 {
+				reg = <0xf423000 0x1000>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <1>;
+				status = "disabled";
+			};
+
+			frame@f425000 {
+				reg = <0xf425000 0x1000>,
+				      <0xf426000 0x1000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <2>;
+				status = "disabled";
+			};
+
+			frame@f427000 {
+				reg = <0xf427000 0x1000>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <3>;
+				status = "disabled";
+			};
+
+			frame@f429000 {
+				reg = <0xf429000 0x1000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <4>;
+				status = "disabled";
+			};
+
+			frame@f42b000 {
+				reg = <0xf42b000 0x1000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <5>;
+				status = "disabled";
+			};
+
+			frame@f42d000 {
+				reg = <0xf42d000 0x1000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <6>;
+				status = "disabled";
+			};
+		};
+
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
index 91e104b0f86..ae12f069f26 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
@@ -3,7 +3,7 @@
  * IPQ9574 RDP board common device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /dts-v1/;
@@ -164,6 +164,26 @@
 	status = "okay";
 };
 
+/*
+ * The bootstrap pins for the board select the XO clock frequency
+ * (48 MHZ or 96 MHZ used for different RDP type board). This setting
+ * automatically enables the right dividers, to ensure the reference
+ * clock output from WiFi to the CMN PLL is 48 MHZ.
+ */
+&ref_48mhz_clk {
+	clock-div = <1>;
+	clock-mult = <1>;
+};
+
+/*
+ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
+ * from WiFi output clock 48 MHZ divided by 2.
+ */
 &xo_board_clk {
-	clock-frequency = <24000000>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+&xo_clk {
+	clock-frequency = <48000000>;
 };
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
index 1bb8d96c9a8..165ebbb5951 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "ipq9574-rdp-common.dtsi"
 
 / {
@@ -15,6 +16,45 @@
 	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
 };
 
+&pcie1_phy {
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-0 = <&pcie1_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie2_phy {
+	status = "okay";
+};
+
+&pcie2 {
+	pinctrl-0 = <&pcie2_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie3_phy {
+	status = "okay";
+};
+
+&pcie3 {
+	pinctrl-0 = <&pcie3_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &sdhc_1 {
 	pinctrl-0 = <&sdc_default_state>;
 	pinctrl-names = "default";
@@ -28,6 +68,79 @@
 };
 
 &tlmm {
+
+	pcie1_default: pcie1-default-state {
+		clkreq-n-pins {
+			pins = "gpio25";
+			function = "pcie1_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio26";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio27";
+			function = "pcie1_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
+	pcie2_default: pcie2-default-state {
+		clkreq-n-pins {
+			pins = "gpio28";
+			function = "pcie2_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio30";
+			function = "pcie2_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
+	pcie3_default: pcie3-default-state {
+		clkreq-n-pins {
+			pins = "gpio31";
+			function = "pcie3_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio32";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio33";
+			function = "pcie3_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
 	sdc_default_state: sdc-default-state {
 		clk-pins {
 			pins = "gpio5";
diff --git a/dts/upstream/src/arm64/qcom/ipq9574.dtsi b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
index d1fd35ebc4a..94229002897 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
@@ -3,10 +3,11 @@
  * IPQ9574 SoC device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -19,12 +20,24 @@
 	#size-cells = <2>;
 
 	clocks {
+		ref_48mhz_clk: ref-48mhz-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&xo_clk>;
+			#clock-cells = <0>;
+		};
+
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
 
 		xo_board_clk: xo-board-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&ref_48mhz_clk>;
+			#clock-cells = <0>;
+		};
+
+		xo_clk: xo-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
@@ -226,8 +239,54 @@
 			reg = <0x00060000 0x6000>;
 		};
 
+		pcie0_phy: phy@84000 {
+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+			reg = <0x00084000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+				 <&gcc GCC_PCIE0_AHB_CLK>,
+				 <&gcc GCC_PCIE0_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
+				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie0_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie2_phy: phy@8c000 {
+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+			reg = <0x0008c000 0x2000>;
+
+			clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+				 <&gcc GCC_PCIE2_AHB_CLK>,
+				 <&gcc GCC_PCIE2_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE2_PHY_BCR>,
+				 <&gcc GCC_PCIE2PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie2_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		rng: rng@e3000 {
-			compatible = "qcom,prng-ee";
+			compatible = "qcom,ipq9574-trng", "qcom,trng";
 			reg = <0x000e3000 0x1000>;
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 			clock-names = "core";
@@ -243,6 +302,64 @@
 			status = "disabled";
 		};
 
+		pcie3_phy: phy@f4000 {
+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+			reg = <0x000f4000 0x2000>;
+
+			clocks = <&gcc GCC_PCIE3_AUX_CLK>,
+				 <&gcc GCC_PCIE3_AHB_CLK>,
+				 <&gcc GCC_PCIE3_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE3_PHY_BCR>,
+				 <&gcc GCC_PCIE3PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie3_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@fc000 {
+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+			reg = <0x000fc000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+				 <&gcc GCC_PCIE1_AHB_CLK>,
+				 <&gcc GCC_PCIE1_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
+				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie1_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		cmn_pll: clock-controller@9b000 {
+			compatible = "qcom,ipq9574-cmn-pll";
+			reg = <0x0009b000 0x800>;
+			clocks = <&ref_48mhz_clk>,
+				 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+				 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+			clock-names = "ref", "ahb", "sys";
+			#clock-cells = <1>;
+			assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+			assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+		};
+
 		qfprom: efuse@a4000 {
 			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
 			reg = <0x000a4000 0x5a1>;
@@ -309,10 +426,10 @@
 			clocks = <&xo_board_clk>,
 				 <&sleep_clk>,
 				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&pcie2_phy>,
+				 <&pcie3_phy>,
 				 <0>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -756,6 +873,326 @@
 				status = "disabled";
 			};
 		};
+
+		pcie1: pcie@10000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x10000000 0xf1d>,
+			       <0x10000f20 0xa8>,
+			       <0x10001000 0x1000>,
+			       <0x000f8000 0x4000>,
+			       <0x10100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
+				 <&gcc GCC_PCIE1_AXI_S_CLK>,
+				 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE1_RCHNG_CLK>,
+				 <&gcc GCC_PCIE1_AHB_CLK>,
+				 <&gcc GCC_PCIE1_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_S_ARES>,
+				 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_M_ARES>,
+				 <&gcc GCC_PCIE1_AUX_ARES>,
+				 <&gcc GCC_PCIE1_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
+					<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie3: pcie@18000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x18000000 0xf1d>,
+			       <0x18000f20 0xa8>,
+			       <0x18001000 0x1000>,
+			       <0x000f0000 0x4000>,
+			       <0x18100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <3>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3_RCHNG_CLK>,
+				 <&gcc GCC_PCIE3_AHB_CLK>,
+				 <&gcc GCC_PCIE3_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE3_PIPE_ARES>,
+				 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_S_ARES>,
+				 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_M_ARES>,
+				 <&gcc GCC_PCIE3_AUX_ARES>,
+				 <&gcc GCC_PCIE3_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie3_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
+					<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie2: pcie@20000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x20000000 0xf1d>,
+			       <0x20000f20 0xa8>,
+			       <0x20001000 0x1000>,
+			       <0x00088000 0x4000>,
+			       <0x20100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <2>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
+				 <&gcc GCC_PCIE2_AXI_S_CLK>,
+				 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE2_RCHNG_CLK>,
+				 <&gcc GCC_PCIE2_AHB_CLK>,
+				 <&gcc GCC_PCIE2_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE2_PIPE_ARES>,
+				 <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_S_ARES>,
+				 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_M_ARES>,
+				 <&gcc GCC_PCIE2_AUX_ARES>,
+				 <&gcc GCC_PCIE2_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie2_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
+					<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie0: pci@28000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x28000000 0xf1d>,
+			       <0x28000f20 0xa8>,
+			       <0x28001000 0x1000>,
+			       <0x00080000 0x4000>,
+			       <0x28100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
+				 <&gcc GCC_PCIE0_AXI_S_CLK>,
+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE0_RCHNG_CLK>,
+				 <&gcc GCC_PCIE0_AHB_CLK>,
+				 <&gcc GCC_PCIE0_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_S_ARES>,
+				 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_M_ARES>,
+				 <&gcc GCC_PCIE0_AUX_ARES>,
+				 <&gcc GCC_PCIE0_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
+					<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
 	};
 
 	thermal-zones {
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
index 5ce8f1350ab..caad1dead2e 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
@@ -321,6 +321,41 @@
 	status = "okay";
 };
 
+&gpu {
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mdss_default>;
+	pinctrl-1 = <&mdss_sleep>;
+
+	panel@0 {
+		compatible = "samsung,s6e88a0-ams427ap24";
+		reg = <0>;
+
+		vdd3-supply = <&pm8916_l17>;
+		vci-supply = <&pm8916_l6>;
+		reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+		flip-horizontal;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&panel_in>;
+};
+
 &mpss_mem {
 	reg = <0x0 0x86800000 0x0 0x5a00000>;
 };
@@ -330,6 +365,13 @@
 	linux,code = <KEY_VOLUMEDOWN>;
 };
 
+&pm8916_rpm_regulators {
+	pm8916_l17: l17 {
+		regulator-min-microvolt = <2850000>;
+		regulator-max-microvolt = <2850000>;
+	};
+};
+
 &pm8916_vib {
 	status = "okay";
 };
@@ -425,6 +467,22 @@
 		bias-disable;
 	};
 
+	mdss_default: mdss-default-state {
+		pins = "gpio25";
+		function = "gpio";
+
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	mdss_sleep: mdss-sleep-state {
+		pins = "gpio25";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	muic_i2c_default: muic-i2c-default-state {
 		pins = "gpio105", "gpio106";
 		function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916.dtsi b/dts/upstream/src/arm64/qcom/msm8916.dtsi
index 5e558bcc9d8..8f35c9af187 100644
--- a/dts/upstream/src/arm64/qcom/msm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916.dtsi
@@ -125,7 +125,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts b/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts
new file mode 100644
index 00000000000..f1d22535fed
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Barnabas Czeman
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "msm8917.dtsi"
+#include "pm8937.dtsi"
+
+/delete-node/ &qseecom_mem;
+
+/ {
+	model = "Xiaomi Redmi 5A (riva)";
+	compatible = "xiaomi,riva", "qcom,msm8917";
+	chassis-type = "handset";
+
+	qcom,msm-id = <QCOM_ID_MSM8917 0>;
+	qcom,board-id = <0x1000b 2>, <0x2000b 2>;
+
+	battery: battery {
+		compatible = "simple-battery";
+		charge-full-design-microamp-hours = <3000000>;
+		energy-full-design-microwatt-hours = <11500000>;
+		constant-charge-current-max-microamp = <1000000>;
+		constant-charge-voltage-max-microvolt = <4400000>;
+		precharge-current-microamp = <256000>;
+		charge-term-current-microamp = <60000>;
+		voltage-min-design-microvolt = <3400000>;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		stdout-path = "framebuffer0";
+
+		framebuffer0: framebuffer@90001000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
+			width = <720>;
+			height = <1280>;
+			stride = <(720 * 3)>;
+			format = "r8g8b8";
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>,
+				 <&gcc GCC_MDSS_MDP_CLK>,
+				 <&gcc GCC_MDSS_BYTE0_CLK>,
+				 <&gcc GCC_MDSS_PCLK0_CLK>,
+				 <&gcc GCC_MDSS_ESC0_CLK>;
+			power-domains = <&gcc MDSS_GDSC>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&gpio_keys_default>;
+		pinctrl-names = "default";
+
+		key-volup {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+		};
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		qseecom_mem: qseecom@84a00000 {
+			reg = <0x0 0x84a00000 0x0 0x1900000>;
+			no-map;
+		};
+
+		framebuffer_mem: memory@90001000 {
+			reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
+			no-map;
+		};
+	};
+};
+
+&blsp1_i2c3 {
+	status = "okay";
+
+	touchscreen@38 {
+		compatible = "edt,edt-ft5306";
+		reg = <0x38>;
+		interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&tsp_int_rst_default>;
+		pinctrl-names = "default";
+		vcc-supply = <&pm8937_l10>;
+		iovcc-supply = <&pm8937_l5>;
+		touchscreen-size-x = <720>;
+		touchscreen-size-y = <1280>;
+	};
+};
+
+&blsp2_i2c1 {
+	status = "okay";
+
+	bq27426@55 {
+		compatible = "ti,bq27426";
+		reg = <0x55>;
+		monitored-battery = <&battery>;
+	};
+
+	bq25601@6b{
+		compatible = "ti,bq25601";
+		reg = <0x6b>;
+		interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&bq25601_int_default>;
+		pinctrl-names = "default";
+		input-voltage-limit-microvolt = <4400000>;
+		input-current-limit-microamp = <1000000>;
+		monitored-battery = <&battery>;
+	};
+};
+
+&pm8937_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&rpm_requests {
+	regulators-0 {
+		compatible = "qcom,rpm-pm8937-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+
+		vdd_l1_l19-supply = <&pm8937_s3>;
+		vdd_l2_l23-supply = <&pm8937_s3>;
+		vdd_l3-supply = <&pm8937_s3>;
+		vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>;
+		vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
+		vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>;
+
+		pm8937_s1: s1 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1225000>;
+		};
+
+		pm8937_s3: s3 {
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1300000>;
+		};
+
+		pm8937_s4: s4 {
+			regulator-min-microvolt = <2050000>;
+			regulator-max-microvolt = <2050000>;
+		};
+
+		pm8937_l2: l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+
+		pm8937_l5: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l6: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l7: l7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l8: l8 {
+			regulator-min-microvolt = <2850000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8937_l9: l9 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l10: l10 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <3000000>;
+		};
+
+		pm8937_l11: l11 {
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+			regulator-system-load = <200000>;
+		};
+
+		pm8937_l12: l12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2950000>;
+		};
+
+		pm8937_l13: l13 {
+			regulator-min-microvolt = <3075000>;
+			regulator-max-microvolt = <3075000>;
+		};
+
+		pm8937_l14: l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l15: l15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l16: l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l17: l17 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8937_l19: l19 {
+			regulator-min-microvolt = <1225000>;
+			regulator-max-microvolt = <1350000>;
+		};
+
+		pm8937_l22: l22 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+		};
+
+		pm8937_l23: l23 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+	};
+
+};
+
+&sdhc_1 {
+	vmmc-supply = <&pm8937_l8>;
+	vqmmc-supply = <&pm8937_l5>;
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&pm8937_l11>;
+	vqmmc-supply = <&pm8937_l12>;
+	pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+	pinctrl-names = "default", "sleep";
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32768>;
+};
+
+&tlmm {
+	bq25601_int_default: bq25601-int-default-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	gpio_keys_default: gpio-keys-default-state {
+		pins = "gpio91";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	sdc2_cd_default: sdc2-cd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tsp_int_rst_default: tsp-int-rst-default-state {
+		pins = "gpio64", "gpio65";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+};
+
+&wcnss {
+	vddpx-supply = <&pm8937_l5>;
+
+	status = "okay";
+};
+
+&wcnss_iris {
+	compatible = "qcom,wcn3620";
+	vddxo-supply = <&pm8937_l7>;
+	vddrfa-supply = <&pm8937_l19>;
+	vddpa-supply = <&pm8937_l9>;
+	vdddig-supply = <&pm8937_l5>;
+};
+
+&wcnss_mem {
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <19200000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8917.dtsi b/dts/upstream/src/arm64/qcom/msm8917.dtsi
new file mode 100644
index 00000000000..7bf58dd0146
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8917.dtsi
@@ -0,0 +1,1954 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/clock/qcom,gcc-msm8917.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@100 {
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu1: cpu@101 {
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+		};
+
+		cpu2: cpu@102 {
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+		};
+
+		cpu3: cpu@103 {
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		domain-idle-states {
+			cluster_sleep_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000053>;
+				entry-latency-us = <700>;
+				exit-latency-us = <1000>;
+				min-residency-us = <6500>;
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <125>;
+				exit-latency-us = <180>;
+				min-residency-us = <595>;
+				local-timer-stop;
+			};
+		};
+
+		cpu_opp_table: opp-table-cpu {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-960000000 {
+				opp-hz = /bits/ 64 <960000000>;
+			};
+
+			opp-1094400000 {
+				opp-hz = /bits/ 64 <1094400000>;
+			};
+
+			opp-1248000000 {
+				opp-hz = /bits/ 64 <1248000000>;
+			};
+
+			opp-1401600000 {
+				opp-hz = /bits/ 64 <1401600000>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-msm8916", "qcom,scm";
+			clocks = <&gcc GCC_CRYPTO_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "core", "bus", "iface";
+			#reset-cells = <1>;
+
+			qcom,dload-mode = <&tcsr 0x6100>;
+		};
+	};
+
+	memory@80000000 {
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+		device_type = "memory";
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0>;
+		};
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+	};
+
+	rpm: remoteproc {
+		compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc";
+
+		smd-edge {
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,ipc = <&apcs 8 0>;
+			qcom,smd-edge = <15>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-msm8917", "qcom,smd-rpm";
+				qcom,smd-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc";
+					#clock-cells = <1>;
+					clocks = <&xo_board>;
+					clock-names = "xo";
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,msm8917-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp_ret: opp1 {
+							opp-level = <RPM_SMD_LEVEL_RETENTION>;
+						};
+
+						rpmpd_opp_ret_plus: opp2 {
+							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
+						};
+
+						rpmpd_opp_min_svs: opp3 {
+							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+						};
+
+						rpmpd_opp_low_svs: opp4 {
+							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+						};
+
+						rpmpd_opp_svs: opp5 {
+							opp-level = <RPM_SMD_LEVEL_SVS>;
+						};
+
+						rpmpd_opp_svs_plus: opp6 {
+							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+						};
+
+						rpmpd_opp_nom: opp7 {
+							opp-level = <RPM_SMD_LEVEL_NOM>;
+						};
+
+						rpmpd_opp_nom_plus: opp8 {
+							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+						};
+
+						rpmpd_opp_turbo: opp9 {
+							opp-level = <RPM_SMD_LEVEL_TURBO>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		qseecom_mem: qseecom@85b00000 {
+			reg = <0x0 0x85b00000 0x0 0x800000>;
+			no-map;
+		};
+
+		smem@86300000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86300000 0x0 0x100000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		};
+
+		reserved@86400000 {
+			reg = <0x0 0x86400000 0x0 0x400000>;
+			no-map;
+		};
+
+		rmtfs@92100000 {
+			compatible = "qcom,rmtfs-mem";
+			reg = <0x0 0x92100000 0x0 0x180000>;
+			no-map;
+
+			qcom,client-id = <1>;
+		};
+
+		adsp_mem: adsp {
+			size = <0x0 0x1100000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		mba_mem: mba {
+			size = <0x0 0x100000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		venus_mem: venus {
+			size = <0x0 0x400000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		wcnss_mem: wcnss {
+			size = <0x0 0x700000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcnss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <451>, <431>;
+
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 18>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <4>;
+
+		wcnss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcnss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		hexagon_smsm: hexagon@1 {
+			reg = <1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@6 {
+			reg = <6>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0xffffffff>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rpm_msg_ram: sram@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x8000>;
+		};
+
+		usb_hs_phy: phy@6c000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0006c000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&xo_board>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_QUSB2_PHY_BCR>,
+				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
+		qfprom: qfprom@a4000 {
+			compatible = "qcom,msm8917-qfprom", "qcom,qfprom";
+			reg = <0x000a4000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			tsens_base1: base1@1d8 {
+				reg = <0x1d8 1>;
+				bits = <0 8>;
+			};
+
+			tsens_s5_p1: s5-p1@1d9 {
+				reg = <0x1d9 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s5_p2: s5-p2@1d9 {
+				reg = <0x1d9 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s6_p1: s6-p1@1da {
+				reg = <0x1da 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s6_p2: s6-p2@1db {
+				reg = <0x1db 1>;
+				bits = <2 6>;
+			};
+
+			tsens_s7_p1: s7-p1@1dc {
+				reg = <0x1dc 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s7_p2: s7-p2@1dc {
+				reg = <0x1dc 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s8_p1: s8-p1@1dd {
+				reg = <0x1dd 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s8_p2: s8-p2@1de {
+				reg = <0x1de 1>;
+				bits = <2 6>;
+			};
+
+			tsens_base2: base2@1df {
+				reg = <0x1df 1>;
+				bits = <0 8>;
+			};
+
+			tsens_mode: mode@210 {
+				reg = <0x210 1>;
+				bits = <0 3>;
+			};
+
+			tsens_s0_p1: s0-p1@210 {
+				reg = <0x210 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s0_p2: s0-p2@211 {
+				reg = <0x211 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s1_p1: s1-p1@211 {
+				reg = <0x211 2>;
+				bits = <7 6>;
+			};
+
+			tsens_s1_p2: s1-p2@212 {
+				reg = <0x212 2>;
+				bits = <5 6>;
+			};
+
+			tsens_s2_p1: s2-p1@213 {
+				reg = <0x213 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s2_p2: s2-p2@214 {
+				reg = <0x214 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s3_p1: s3-p1@214 {
+				reg = <0x214 2>;
+				bits = <7 6>;
+			};
+
+			tsens_s3_p2: s3-p2@215 {
+				reg = <0x215 2>;
+				bits = <5 6>;
+			};
+
+			tsens_s4_p1: s4-p1@216 {
+				reg = <0x216 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s4_p2: s4-p2@217 {
+				reg = <0x217 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s9_p1: s9-p1@230{
+				reg = <0x230 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s9_p2: s9-p2@230 {
+				reg = <0x230 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s10_p1: s10-p1@231 {
+				reg = <0x231 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s10_p2: s10-p2@232 {
+				reg = <0x232 1>;
+				bits = <2 6>;
+			};
+		};
+
+		rng@e3000 {
+			compatible = "qcom,prng";
+			reg = <0x000e3000 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		tsens: thermal-sensor@4a9000 {
+			compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
+			reg = <0x004a9000 0x1000>,
+			      <0x004a8000 0x1000>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow";
+			nvmem-cells = <&tsens_mode>,
+				      <&tsens_base1>, <&tsens_base2>,
+				      <&tsens_s0_p1>, <&tsens_s0_p2>,
+				      <&tsens_s1_p1>, <&tsens_s1_p2>,
+				      <&tsens_s2_p1>, <&tsens_s2_p2>,
+				      <&tsens_s3_p1>, <&tsens_s3_p2>,
+				      <&tsens_s4_p1>, <&tsens_s4_p2>,
+				      <&tsens_s5_p1>, <&tsens_s5_p2>,
+				      <&tsens_s6_p1>, <&tsens_s6_p2>,
+				      <&tsens_s7_p1>, <&tsens_s7_p2>,
+				      <&tsens_s8_p1>, <&tsens_s8_p2>,
+				      <&tsens_s9_p1>, <&tsens_s9_p2>,
+				      <&tsens_s10_p1>, <&tsens_s10_p2>;
+			nvmem-cell-names = "mode",
+					   "base1", "base2",
+					   "s0_p1", "s0_p2",
+					   "s1_p1", "s1_p2",
+					   "s2_p1", "s2_p2",
+					   "s3_p1", "s3_p2",
+					   "s4_p1", "s4_p2",
+					   "s5_p1", "s5_p2",
+					   "s6_p1", "s6_p2",
+					   "s7_p1", "s7_p2",
+					   "s8_p1", "s8_p2",
+					   "s9_p1", "s9_p2",
+					   "s10_p1", "s10_p2";
+			#qcom,sensors = <11>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		restart@4ab000 {
+			compatible = "qcom,pshold";
+			reg = <0x004ab000 0x4>;
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,msm8917-pinctrl";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 134>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp1_i2c2_default: blsp1-i2c2-default-state {
+				pins = "gpio6", "gpio7";
+				function = "blsp_i2c2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_default: blsp1-i2c3-default-state {
+				pins = "gpio10", "gpio11";
+				function = "blsp_i2c3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
+				pins = "gpio10", "gpio11";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c4_default: blsp1-i2c4-default-state {
+				pins = "gpio14", "gpio15";
+				function = "blsp_i2c4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
+				pins = "gpio14", "gpio15";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c1_default: blsp2-i2c1-default-state {
+				pins = "gpio18", "gpio19";
+				function = "blsp_i2c5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_spi3_default: blsp1-spi3-default-state {
+				cs-pins {
+					pins = "gpio10";
+					function = "blsp_spi3";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio8", "gpio9", "gpio11";
+					function = "blsp_spi3";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
+
+			blsp1_spi3_sleep: blsp1-spi3-sleep-state {
+				cs-pins {
+					pins = "gpio10";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio8", "gpio9", "gpio11";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			blsp2_spi2_default: blsp2-spi2-default-state {
+				cs0-pins {
+					pins = "gpio47";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cs1-pins {
+					pins = "gpio22";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio20", "gpio21", "gpio23";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			blsp2_spi2_sleep: blsp2-spi2-sleep-state {
+				cs0-pins {
+					pins = "gpio47";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cs1-pins {
+					pins = "gpio22";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio20", "gpio21", "gpio23";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			blsp1_uart1_default: blsp1-uart1-default-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "blsp_uart1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart1_sleep: blsp1-uart1-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart2_default: blsp1-uart2-default-state {
+				pins = "gpio4", "gpio5";
+				function = "blsp_uart2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart2_sleep: blsp1-uart2-sleep-state {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			sdc1_default: sdc1-default-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_sleep: sdc1-sleep-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+
+			wcnss_pin_a: wcnss-active-state {
+				wcss-wlan-pins {
+					pins = "gpio79", "gpio80";
+					function = "wcss_wlan";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan0-pins {
+					pins = "gpio78";
+					function = "wcss_wlan0";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan1-pins {
+					pins = "gpio77";
+					function = "wcss_wlan1";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan2-pins {
+					pins = "gpio76";
+					function = "wcss_wlan2";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-msm8917";
+			reg = <0x01800000 0x80000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi0_phy 0>;
+			clock-names = "xo",
+				      "sleep_clk",
+				      "dsi0pll",
+				      "dsi0pllbyte";
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x01905000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8917", "syscon";
+			reg = <0x01937000 0x30000>;
+		};
+
+		mdss: display-subsystem@1a00000 {
+			compatible = "qcom,mdss";
+			reg = <0x01a00000 0x1000>,
+			      <0x01ab0000 0x1040>;
+			reg-names = "mdss_phys", "vbif_phys";
+			ranges;
+
+			power-domains = <&gcc MDSS_GDSC>;
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>;
+			clock-names = "iface",
+				      "bus",
+				      "vsync";
+
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			status = "disabled";
+
+			mdp: display-controller@1a01000 {
+				compatible = "qcom,msm8917-mdp5", "qcom,mdp5";
+				reg = <0x01a01000 0x89000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				power-domains = <&gcc MDSS_GDSC>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_VSYNC_CLK>;
+				clock-names = "iface",
+					      "bus",
+					      "core",
+					      "vsync";
+
+				iommus = <&apps_iommu 0x15>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdp5_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@1a94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0x01a94000 0x300>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
+						  <&gcc PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>,
+							 <&mdss_dsi0_phy 1>;
+
+				clocks = <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_BYTE0_CLK>,
+					 <&gcc GCC_MDSS_PCLK0_CLK>,
+					 <&gcc GCC_MDSS_ESC0_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core";
+				phys = <&mdss_dsi0_phy>;
+
+				operating-points-v2 = <&mdss_dsi0_opp_table>;
+				power-domains = <&rpmpd MSM8917_VDDCX>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&mdp5_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+
+				mdss_dsi0_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-125000000 {
+						opp-hz = /bits/ 64 <125000000>;
+						required-opps = <&rpmpd_opp_svs>;
+					};
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@1a94a00 {
+				compatible = "qcom,dsi-phy-28nm-8937";
+				reg = <0x01a94a00 0xd4>,
+				      <0x01a94400 0x280>,
+				      <0x01a94b80 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
+			};
+		};
+
+		apps_iommu: iommu@1e20000 {
+			compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01e20000 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_APSS_TCU_CLK>;
+			clock-names = "iface", "bus";
+
+			qcom,iommu-secure-id = <17>;
+
+			/* VFE */
+			iommu-ctx@14000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x14000 0x1000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* MDP_0 */
+			iommu-ctx@15000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x15000 0x1000>;
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* VENUS_NS */
+			iommu-ctx@16000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x16000 0x1000>;
+				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu_iommu: iommu@1f08000 {
+			compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01f08000 0x10000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_GFX_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <18>;
+
+			iommu-ctx@0 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0 0x1000>;
+				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu: gpu@1c00000 {
+			compatible = "qcom,adreno-306.32", "qcom,adreno";
+			reg = <0x01c00000 0x20000>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names = "core",
+				      "iface",
+				      "mem_iface",
+				      "alt_mem_iface",
+				      "gfx3d";
+			clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+				 <&gcc GCC_OXILI_AHB_CLK>,
+				 <&gcc GCC_BIMC_GFX_CLK>,
+				 <&gcc GCC_BIMC_GPU_CLK>,
+				 <&gcc GFX3D_CLK_SRC>;
+			power-domains = <&gcc OXILI_GX_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+			#cooling-cells = <2>;
+
+			iommus = <&gpu_iommu 0>;
+
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+				};
+
+				opp-270000000 {
+					opp-hz = /bits/ 64 <270000000>;
+				};
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+				};
+
+				opp-484800000 {
+					opp-hz = /bits/ 64 <484800000>;
+				};
+
+				opp-523200000 {
+					opp-hz = /bits/ 64 <523200000>;
+				};
+
+				opp-598000000 {
+					opp-hz = /bits/ 64 <598000000>;
+				};
+			};
+		};
+
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x800000>,
+			      <0x02c00000 0x800000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		bam_dmux_dma: dma-controller@4044000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x04044000 0x19000>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+
+			num-channels = <6>;
+			qcom,num-ees = <1>;
+			qcom,powered-remotely;
+
+			status = "disabled";
+		};
+
+		sdhc_1: mmc@7824900 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07824900 0x500>,
+			      <0x07824000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc1_default>;
+			pinctrl-1 = <&sdc1_sleep>;
+			pinctrl-names = "default", "sleep";
+			power-domains = <&rpmpd MSM8917_VDDCX>;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-ddr-1_8v;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		sdhc_2: mmc@7864900 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07864900 0x500>,
+			      <0x07864000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc2_default>;
+			pinctrl-1 = <&sdc2_sleep>;
+			pinctrl-names = "default", "sleep";
+			power-domains = <&rpmpd MSM8917_VDDCX>;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		blsp1_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1f000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			num-channels = <12>;
+			qcom,num-ees = <4>;
+			qcom,ee = <0>;
+		};
+
+		blsp2_dma: dma-controller@7ac4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07ac4000 0x1d000>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			num-channels = <10>;
+			qcom,num-ees = <4>;
+			qcom,ee = <0>;
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_uart1_default>;
+			pinctrl-1 = <&blsp1_uart1_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b0000 0x200>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			pinctrl-1 = <&blsp1_uart2_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+		};
+
+		blsp1_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b6000 0x600>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c2_default>;
+			pinctrl-1 = <&blsp1_i2c2_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c3: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c3_default>;
+			pinctrl-1 = <&blsp1_i2c3_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi3: spi@78b7000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_spi3_default>;
+			pinctrl-1 = <&blsp1_spi3_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c4: i2c@78b8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b8000 0x500>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c4_default>;
+			pinctrl-1 = <&blsp1_i2c4_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c1: i2c@7af5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07af5000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp2_i2c1_default>;
+			pinctrl-1 = <&blsp2_i2c1_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_spi2: spi@7af6000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x07af6000 0x600>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp2_spi2_default>;
+			pinctrl-1 = <&blsp2_spi2_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		usb: usb@78db000 {
+			compatible = "qcom,ci-hdrc";
+			reg = <0x078db000 0x200>,
+			      <0x078db200 0x200>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			clock-names = "iface", "core";
+			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <80000000>;
+			resets = <&gcc GCC_USB_HS_BCR>;
+			reset-names = "core";
+			phy_type = "ulpi";
+			dr_mode = "otg";
+			hnp-disable;
+			srp-disable;
+			adp-disable;
+			ahb-burst-config = <0>;
+			phy-names = "usb-phy";
+			phys = <&usb_hs_phy>;
+			status = "disabled";
+			#reset-cells = <1>;
+		};
+
+		wcnss: remoteproc@a204000 {
+			compatible = "qcom,pronto-v3-pil", "qcom,pronto";
+			reg = <0x0a204000 0x2000>,
+			      <0x0a202000 0x1000>,
+			      <0x0a21b000 0x3000>;
+			reg-names = "ccu", "dxe", "pmu";
+
+			memory-region = <&wcnss_mem>;
+
+			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+			power-domains = <&rpmpd MSM8917_VDDCX>,
+					<&rpmpd MSM8917_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			qcom,smem-states = <&wcnss_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			pinctrl-0 = <&wcnss_pin_a>;
+			pinctrl-names = "default";
+
+			status = "disabled";
+
+			wcnss_iris: iris {
+				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+				clock-names = "xo";
+			};
+
+			smd-edge {
+				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&apcs 17>;
+				qcom,smd-edge = <6>;
+				qcom,remote-pid = <4>;
+
+				label = "pronto";
+
+				wcnss_ctrl: wcnss {
+					compatible = "qcom,wcnss";
+					qcom,smd-channels = "WCNSS_CTRL";
+
+					qcom,mmio = <&wcnss>;
+
+					wcnss_bt: bluetooth {
+						compatible = "qcom,wcnss-bt";
+					};
+
+					wcnss_wifi: wifi {
+						compatible = "qcom,wcnss-wlan";
+
+						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+						interrupt-names = "tx", "rx";
+
+						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+						qcom,smem-state-names = "tx-enable",
+									"tx-rings-empty";
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			reg = <0x0b000000 0x1000>,
+			      <0x0b002000 0x1000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		apcs: mailbox@b011000 {
+			compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
+			reg = <0x0b011000 0x1000>;
+			#mbox-cells = <1>;
+			clocks = <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+			clock-names = "pll", "aux", "ref";
+			#clock-cells = <0>;
+		};
+
+		a53pll: clock@b016000 {
+			compatible = "qcom,msm8939-a53pll";
+			reg = <0x0b016000 0x40>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+			#clock-cells = <0>;
+			operating-points-v2 = <&pll_opp_table>;
+
+			pll_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-960000000 {
+					opp-hz = /bits/ 64 <960000000>;
+				};
+
+				opp-1094400000 {
+					opp-hz = /bits/ 64 <1094400000>;
+				};
+
+				opp-1248000000 {
+					opp-hz = /bits/ 64 <1248000000>;
+				};
+
+				opp-1401600000 {
+					opp-hz = /bits/ 64 <1401600000>;
+				};
+			};
+		};
+
+		watchdog@b017000 {
+			compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
+			reg = <0x0b017000 0x1000>;
+			clocks = <&sleep_clk>;
+		};
+
+		timer@b120000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@b121000 {
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@b123000 {
+				reg = <0x0b123000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				reg = <0x0b124000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				reg = <0x0b125000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				reg = <0x0b126000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				reg = <0x0b127000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				reg = <0x0b128000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	thermal_zones: thermal-zones {
+		aoss-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 0>;
+
+			trips {
+				aoss_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		camera-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 3>;
+
+			trips {
+				camera_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cpuss1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 4>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpuss1_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpuss1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpuss1_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss1_crit: cpuss1-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu0-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 5>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu0_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 6>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu1_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 7>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu2_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 8>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu3_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 9>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu_alert>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu_alert: trip-point0 {
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				gpu_crit: gpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+		};
+
+		mdm-core-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 1>;
+
+			trips {
+				mdm_core_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 2>;
+
+			trips {
+				q6_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8939.dtsi b/dts/upstream/src/arm64/qcom/msm8939.dtsi
index 7a6f1eeaa3f..7cd5660de1b 100644
--- a/dts/upstream/src/arm64/qcom/msm8939.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8939.dtsi
@@ -34,7 +34,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts b/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
index 29e79ae0849..1aca11daf83 100644
--- a/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
+++ b/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
@@ -2,12 +2,13 @@
 /*
  * Copyright (c) 2015, Huawei Inc. All rights reserved.
  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2023, Petr Vorel <petr.vorel@gmail.com>
+ * Copyright (c) 2021-2024, Petr Vorel <petr.vorel@gmail.com>
  */
 
 /dts-v1/;
 
 #include "msm8994.dtsi"
+#include "pm8994.dtsi"
 
 / {
 	model = "Huawei Nexus 6P";
@@ -46,6 +47,24 @@
 			no-map;
 		};
 	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		button-vol-up {
+			label = "volume up";
+			gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+	};
+};
+
+&pm8994_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+	status = "okay";
 };
 
 &blsp1_uart2 {
diff --git a/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
index 10cd244dea4..4c983b10dd9 100644
--- a/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
@@ -387,11 +387,6 @@
 
 		interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>;
 
-		button_num = <8>;
-		touchpad_num = <0>;
-		wheel_num = <0>;
-		slider_num = <0>;
-
 		vcc-supply = <&vreg_l18a_2p85>;
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8994.dtsi b/dts/upstream/src/arm64/qcom/msm8994.dtsi
index 1acb0f15951..b5cbdd620bb 100644
--- a/dts/upstream/src/arm64/qcom/msm8994.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8994.dtsi
@@ -34,7 +34,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 			clock-output-names = "sleep_clk";
 		};
 	};
@@ -437,6 +437,15 @@
 			#size-cells = <1>;
 			ranges;
 
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
+
 			clocks = <&gcc GCC_USB30_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 				 <&gcc GCC_USB30_SLEEP_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
index f8e9d90afab..dbad8f57f2f 100644
--- a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
+++ b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
@@ -64,7 +64,7 @@
 		};
 
 		led@1 {
-			reg = <0>;
+			reg = <1>;
 			chan-name = "button-backlight1";
 			led-cur = /bits/ 8 <0x32>;
 			max-cur = /bits/ 8 <0xc8>;
diff --git a/dts/upstream/src/arm64/qcom/msm8996.dtsi b/dts/upstream/src/arm64/qcom/msm8996.dtsi
index b379623c1b8..4719e1fc70d 100644
--- a/dts/upstream/src/arm64/qcom/msm8996.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8996.dtsi
@@ -3065,9 +3065,14 @@
 			#size-cells = <1>;
 			ranges;
 
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
 
 			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 				 <&gcc GCC_USB30_MASTER_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/pm660l.dtsi b/dts/upstream/src/arm64/qcom/pm660l.dtsi
index 0094e0ef058..3f8b9eafe16 100644
--- a/dts/upstream/src/arm64/qcom/pm660l.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm660l.dtsi
@@ -70,6 +70,12 @@
 			status = "disabled";
 		};
 
+		pm660l_flash: led-controller@d300 {
+			compatible = "qcom,pm660l-flash-led", "qcom,spmi-flash-led";
+			reg = <0xd300>;
+			status = "disabled";
+		};
+
 		pm660l_wled: leds@d800 {
 			compatible = "qcom,pm660l-wled";
 			reg = <0xd800>, <0xd900>;
diff --git a/dts/upstream/src/arm64/qcom/pm8150.dtsi b/dts/upstream/src/arm64/qcom/pm8150.dtsi
index a74a7ff660d..d2568686a09 100644
--- a/dts/upstream/src/arm64/qcom/pm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8150.dtsi
@@ -49,8 +49,6 @@
 		pon: pon@800 {
 			compatible = "qcom,pm8998-pon";
 			reg = <0x0800>;
-			mode-bootloader = <0x2>;
-			mode-recovery = <0x1>;
 
 			pon_pwrkey: pwrkey {
 				compatible = "qcom,pm8941-pwrkey";
diff --git a/dts/upstream/src/arm64/qcom/pm8937.dtsi b/dts/upstream/src/arm64/qcom/pm8937.dtsi
new file mode 100644
index 00000000000..42b3575b36f
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pm8937.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Dang Huynh <danct12@riseup.net>
+ */
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pm8937-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&pm8937_temp>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmic@0 {
+		compatible = "qcom,pm8937", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon@800 {
+			compatible = "qcom,pm8916-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pm8937_pwrkey: pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+
+			pm8937_resin: resin {
+				compatible = "qcom,pm8941-resin";
+				interrupts = <0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				status = "disabled";
+			};
+		};
+
+		pm8937_gpios: gpio@c000 {
+			compatible = "qcom,pm8937-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm8937_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8937_mpps: mpps@a000 {
+			compatible = "qcom,pm8937-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			gpio-ranges = <&pm8937_mpps 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8937_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8937_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8937_vadc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0 0x31 0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@8 {
+				reg = <VADC_DIE_TEMP>;
+			};
+
+			channel@9 {
+				reg = <VADC_REF_625MV>;
+			};
+
+			channel@a {
+				reg = <VADC_REF_1250MV>;
+			};
+
+			channel@c {
+				reg = <VADC_SPARE1>;
+			};
+
+			channel@e {
+				reg = <VADC_GND_REF>;
+			};
+
+			channel@f {
+				reg = <VADC_VDD_VADC>;
+			};
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+
+	pmic@1 {
+		compatible = "qcom,pm8937", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8937_spmi_regulators: regulators {
+			compatible = "qcom,pm8937-regulators";
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmd8028.dtsi b/dts/upstream/src/arm64/qcom/pmd8028.dtsi
new file mode 100644
index 00000000000..a00913e28a4
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pmd8028.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmd8028-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmd8028_temp_alarm>;
+
+			trips {
+				pmd8028_trip0: trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				pmd8028_trip1: trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				pmd8028_trip2: trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmd8028: pmic@4 {
+		compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmd8028_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmd8028_gpios: gpio@8800 {
+			compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmd8028_gpios 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmi8950.dtsi b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
index 4aff437263a..3d3b1cd97cc 100644
--- a/dts/upstream/src/arm64/qcom/pmi8950.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
@@ -84,6 +84,23 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		labibb {
+			compatible = "qcom,pmi8950-lab-ibb",
+				     "qcom,pmi8998-lab-ibb";
+
+			ibb: ibb {
+				interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-names = "sc-err", "ocp";
+			};
+
+			lab: lab {
+				interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-names = "sc-err", "ocp";
+			};
+		};
+
 		pmi8950_pwm: pwm {
 			compatible = "qcom,pmi8950-pwm";
 			#pwm-cells = <2>;
diff --git a/dts/upstream/src/arm64/qcom/pmih0108.dtsi b/dts/upstream/src/arm64/qcom/pmih0108.dtsi
new file mode 100644
index 00000000000..1c875995d88
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pmih0108.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmih0108-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmih0108_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmih0108: pmic@7 {
+		compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+		reg = <0x7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmih0108_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmih0108_gpios: gpio@8800 {
+			compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmih0108_gpios 0 0 18>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmih0108_eusb2_repeater: phy@fd00 {
+			compatible = "qcom,pm8550b-eusb2-repeater";
+			reg = <0xfd00>;
+			#phy-cells = <0>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmk8350.dtsi b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
index f0ed15458dd..565752af220 100644
--- a/dts/upstream/src/arm64/qcom/pmk8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
@@ -76,6 +76,14 @@
 			status = "disabled";
 		};
 
+		pmk8350_sdam_1: nvram@7000 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7000 0x100>;
+		};
+
 		pmk8350_sdam_2: nvram@7100 {
 			compatible = "qcom,spmi-sdam";
 			reg = <0x7100>;
@@ -89,6 +97,70 @@
 			};
 		};
 
+		pmk8350_sdam_5: nvram@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7400 0x100>;
+		};
+
+		pmk8350_sdam_13: nvram@7c00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7c00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7c00 0x100>;
+		};
+
+		pmk8350_sdam_14: nvram@7d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7d00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7d00 0x100>;
+		};
+
+		pmk8350_sdam_21: nvram@8400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8400 0x100>;
+		};
+
+		pmk8350_sdam_22: nvram@8500 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8500>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8500 0x100>;
+		};
+
+		pmk8350_sdam_23: nvram@8600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8600>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8600 0x100>;
+		};
+
+		pmk8350_sdam_41: nvram@9800 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x9800 0x100>;
+		};
+
+		pmk8350_sdam_46: nvram@9d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9d00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x9d00 0x100>;
+		};
+
 		pmk8350_gpios: gpio@b000 {
 			compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
 			reg = <0xb000>;
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
index fdc62f1b1c5..769c66cb5d1 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
@@ -108,6 +108,36 @@
 		};
 	};
 
+	vreg_afvdd_2p8: regulator-afvdd-2p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "AFVDD_2P8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_bob>;
+	};
+
+	vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "OIS_AVDD0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_bob>;
+	};
+
+	vreg_ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
+		compatible = "regulator-fixed";
+		regulator-name = "OIS_DVDD_1P1";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_s8b>;
+	};
+
 	reserved-memory {
 		cont_splash_mem: cont-splash@e1000000 {
 			reg = <0x0 0xe1000000 0x0 0x2300000>;
@@ -134,36 +164,6 @@
 		};
 	};
 
-	ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
-		compatible = "regulator-fixed";
-		regulator-name = "OIS_AVDD0_1P8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_bob>;
-	};
-
-	ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
-		compatible = "regulator-fixed";
-		regulator-name = "OIS_DVDD_1P1";
-		regulator-min-microvolt = <1100000>;
-		regulator-max-microvolt = <1100000>;
-		gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_s8b>;
-	};
-
-	afvdd_2p8: regulator-afvdd-2p8 {
-		compatible = "regulator-fixed";
-		regulator-name = "AFVDD_2P8";
-		regulator-min-microvolt = <2800000>;
-		regulator-max-microvolt = <2800000>;
-		gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_bob>;
-	};
-
 	thermal-zones {
 		camera-thermal {
 			polling-delay-passive = <0>;
@@ -556,6 +556,47 @@
 	};
 };
 
+&cci0 {
+	status = "okay";
+};
+
+&cci0_i2c0 {
+	/* IMX800 @ 1a */
+
+	eeprom@50 {
+		compatible = "puya,p24c256c", "atmel,24c256";
+		reg = <0x50>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
+&cci0_i2c1 {
+	/* IMX858 @ 29 */
+
+	eeprom@54 {
+		compatible = "giantec,gt24p128f", "atmel,24c128";
+		reg = <0x54>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
+&cci1 {
+	status = "okay";
+};
+
+&cci1_i2c1 {
+	/* S5KJN1SQ03 @ 10 */
+
+	eeprom@51 {
+		compatible = "giantec,gt24p128f", "atmel,24c128";
+		reg = <0x51>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
 &dispcc {
 	/* Disable for now so simple-framebuffer continues working */
 	status = "disabled";
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
index c5fb153614e..9209efcc49b 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
@@ -258,6 +258,8 @@
 			regulator-name = "vreg_l6b_1p2";
 			regulator-min-microvolt = <1140000>;
 			regulator-max-microvolt = <1260000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -265,6 +267,8 @@
 			regulator-name = "vreg_l7b_2p952";
 			regulator-min-microvolt = <2400000>;
 			regulator-max-microvolt = <3544000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -279,6 +283,8 @@
 			regulator-name = "vreg_l9b_1p2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1304000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -467,6 +473,8 @@
 			regulator-name = "vreg_l10c_0p88";
 			regulator-min-microvolt = <720000>;
 			regulator-max-microvolt = <1050000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
index 4667e47a74b..75930f95769 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
@@ -942,8 +942,6 @@
 
 	qcom,squelch-detector-bp = <(-2090)>;
 
-	orientation-switch;
-
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/qcom/qcs404.dtsi b/dts/upstream/src/arm64/qcom/qcs404.dtsi
index 215ba146207..5a9df6b1230 100644
--- a/dts/upstream/src/arm64/qcom/qcs404.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs404.dtsi
@@ -28,7 +28,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
@@ -694,6 +694,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "otg";
 			};
 		};
@@ -731,6 +733,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "peripheral";
 			};
 		};
diff --git a/dts/upstream/src/arm64/qcom/qcs615-ride.dts b/dts/upstream/src/arm64/qcom/qcs615-ride.dts
new file mode 100644
index 00000000000..2b5aa3c6686
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs615-ride.dts
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "qcs615.dtsi"
+#include "pm8150.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. QCS615 Ride";
+	compatible = "qcom,qcs615-ride", "qcom,qcs615";
+	chassis-type = "embedded";
+
+	aliases {
+		mmc0 = &sdhc_1;
+		mmc1 = &sdhc_2;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	regulator-usb2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB2_VBUS";
+		gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb2_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s3a: smps3 {
+			regulator-name = "vreg_s3a";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <650000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1829000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a: smps5 {
+			regulator-name = "vreg_s5a";
+			regulator-min-microvolt = <1896000>;
+			regulator-max-microvolt = <2040000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6a: smps6 {
+			regulator-name = "vreg_s6a";
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1404000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1a: ldo1 {
+			regulator-name = "vreg_l1a";
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <852000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2a: ldo2 {
+			regulator-name = "vreg_l2a";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a: ldo3 {
+			regulator-name = "vreg_l3a";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1248000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <875000>;
+			regulator-max-microvolt = <975000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <1150000>;
+			regulator-max-microvolt = <1350000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10a: ldo10 {
+			regulator-name = "vreg_l10a";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11a: ldo11 {
+			regulator-name = "vreg_l11a";
+			regulator-min-microvolt = <1232000>;
+			regulator-max-microvolt = <1260000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12a: ldo12 {
+			regulator-name = "vreg_l12a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1890000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13a: ldo13 {
+			regulator-name = "vreg_l13a";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3230000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15a: ldo15 {
+			regulator-name = "vreg_l15a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16a: ldo16 {
+			regulator-name = "vreg_l16a";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17a: ldo17 {
+			regulator-name = "vreg_l17a";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gcc {
+	clocks = <&rpmhcc RPMH_CXO_CLK>,
+		 <&rpmhcc RPMH_CXO_CLK_A>,
+		 <&sleep_clk>;
+};
+
+&pm8150_gpios {
+	usb2_en: usb2-en-state {
+		pins = "gpio10";
+		function = "normal";
+		output-enable;
+		power-source = <0>;
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&rpmhcc {
+	clocks = <&xo_board_clk>;
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&sdc1_state_on>;
+	pinctrl-1 = <&sdc1_state_off>;
+	pinctrl-names = "default", "sleep";
+
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	vmmc-supply = <&vreg_l17a>;
+	vqmmc-supply = <&vreg_s4a>;
+
+	non-removable;
+	no-sd;
+	no-sdio;
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	pinctrl-0 = <&sdc2_state_on>;
+	pinctrl-1 = <&sdc2_state_off>;
+	pinctrl-names = "default", "sleep";
+
+	bus-width = <4>;
+	cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+	vmmc-supply = <&vreg_l10a>;
+	vqmmc-supply = <&vreg_s4a>;
+
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_qmpphy {
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "peripheral";
+};
+
+&usb_hsphy_2 {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l17a>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&vreg_s4a>;
+	vccq2-max-microamp = <600000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+
+	status = "okay";
+};
+
+&watchdog {
+	clocks = <&sleep_clk>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs615.dtsi b/dts/upstream/src/arm64/qcom/qcs615.dtsi
new file mode 100644
index 00000000000..f4abfad474e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs615.dtsi
@@ -0,0 +1,3670 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_0>;
+			#cooling-cells = <2>;
+
+			l2_0: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_100>;
+
+			l2_100: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_200>;
+
+			l2_200: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_300>;
+
+			l2_300: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_400>;
+
+			l2_400: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_500>;
+
+			l2_500: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
+			next-level-cache = <&l2_600>;
+			#cooling-cells = <2>;
+
+			l2_600: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
+			next-level-cache = <&l2_700>;
+
+			l2_700: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+
+				core5 {
+					cpu = <&cpu5>;
+				};
+
+				core6 {
+					cpu = <&cpu6>;
+				};
+
+				core7 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+	};
+
+	dummy_eud: dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&replicator_swao_out1>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		entry-method = "psci";
+
+		little_cpu_sleep_0: cpu-sleep-0-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <549>;
+			exit-latency-us = <901>;
+			min-residency-us = <1774>;
+			local-timer-stop;
+		};
+
+		little_cpu_sleep_1: cpu-sleep-0-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <702>;
+			exit-latency-us = <915>;
+			min-residency-us = <4001>;
+			local-timer-stop;
+		};
+
+		big_cpu_sleep_0: cpu-sleep-1-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <523>;
+			exit-latency-us = <1244>;
+			min-residency-us = <2207>;
+			local-timer-stop;
+		};
+
+		big_cpu_sleep_1: cpu-sleep-1-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <526>;
+			exit-latency-us = <1854>;
+			min-residency-us = <5555>;
+			local-timer-stop;
+		};
+	};
+
+	domain-idle-states {
+		cluster_sleep_0: cluster-sleep-0 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41000044>;
+			entry-latency-us = <2752>;
+			exit-latency-us = <3048>;
+			min-residency-us = <6118>;
+		};
+
+		cluster_sleep_1: cluster-sleep-1 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41001344>;
+			entry-latency-us = <3263>;
+			exit-latency-us = <4562>;
+			min-residency-us = <8467>;
+		};
+
+		cluster_sleep_2: cluster-sleep-2 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x4100b344>;
+			entry-latency-us = <3638>;
+			exit-latency-us = <6562>;
+			min-residency-us = <9826>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-qcs615", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	camnoc_virt: interconnect-0 {
+		compatible = "qcom,qcs615-camnoc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	ipa_virt: interconnect-1 {
+		compatible = "qcom,qcs615-ipa-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-2 {
+		compatible = "qcom,qcs615-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	qup_opp_table: opp-table-qup {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+
+		opp-128000000 {
+			opp-hz = /bits/ 64 <128000000>;
+			required-opps = <&rpmhpd_opp_nom>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0
+					      &cluster_sleep_1
+					      &cluster_sleep_2>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		smem_region: smem@86000000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86000000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,qcs615-gcc";
+			reg = <0 0x00100000 0 0x1f0000>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		qfprom: efuse@780000 {
+			compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
+			reg = <0x0 0x00780000 0x0 0x7000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qusb2_hstx_trim: hstx-trim@1f8 {
+				reg = <0x1fb 0x1>;
+				bits = <1 4>;
+			};
+		};
+
+		sdhc_1: mmc@7c4000 {
+			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x007c4000 0x0 0x1000>,
+			      <0x0 0x007c5000 0x0 0x1000>,
+			      <0x0 0x007c8000 0x0 0x8000>;
+			reg-names = "hc",
+				    "cqhci",
+				    "ice";
+
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq",
+					  "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "xo",
+				      "ice";
+
+			resets = <&gcc GCC_SDCC1_BCR>;
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc1_opp_table>;
+			iommus = <&apps_smmu 0x02c0 0x0>;
+			interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr",
+					     "cpu-sdhc";
+
+			qcom,dll-config = <0x000f642c>;
+			qcom,ddr-config = <0x80040868>;
+			supports-cqe;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-384000000 {
+					opp-hz = /bits/ 64 <384000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		gpi_dma0: dma-controller@800000  {
+			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
+			reg = <0x0 0x800000 0x0 0x60000>;
+			#dma-cells = <3>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <8>;
+			dma-channel-mask = <0xf>;
+			iommus = <&apps_smmu 0xd6 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x6000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0xc3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			uart0: serial@880000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			i2c2: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi2: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart2: serial@888000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
+					    <&qup_uart2_tx>, <&qup_uart2_rx>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
+			reg = <0x0 0xa00000 0x0 0x60000>;
+			#dma-cells = <3>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <8>;
+			dma-channel-mask = <0xf>;
+			iommus = <&apps_smmu 0x376 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0xac0000 0x0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0x363 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			i2c4: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi4: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart4: serial@a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
+					    <&qup_uart4_tx>, <&qup_uart4_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			i2c6: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi6: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart6: serial@a88000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
+					    <&qup_uart6_tx>, <&qup_uart6_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi7: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart7: serial@a8c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
+					    <&qup_uart7_tx>, <&qup_uart7_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+		};
+
+		config_noc: interconnect@1500000 {
+			reg = <0x0 0x01500000 0x0 0x5080>;
+			compatible = "qcom,qcs615-config-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1620000 {
+			reg = <0x0 0x01620000 0x0 0x1f300>;
+			compatible = "qcom,qcs615-system-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@1700000 {
+			reg = <0x0 0x01700000 0x0 0x3f200>;
+			compatible = "qcom,qcs615-aggre1-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			reg = <0x0 0x01740000 0x0 0x1c100>;
+			compatible = "qcom,qcs615-mmss-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		ufs_mem_hc: ufshc@1d84000 {
+			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>,
+			      <0x0 0x01d90000 0x0 0x8000>;
+			reg-names = "std",
+				    "ice";
+
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "core_clk_ice",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk";
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			operating-points-v2 = <&ufs_opp_table>;
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			iommus = <&apps_smmu 0x300 0x0>;
+			dma-coherent;
+
+			lanes-per-direction = <1>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			#reset-cells = <1>;
+
+			status = "disabled";
+
+			ufs_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <37500000>,
+						 /bits/ 64 <75000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <75000000>,
+						 /bits/ 64 <150000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <150000000>,
+						 /bits/ 64 <300000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
+			reg = <0x0 0x01d87000 0x0 0xe00>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,qcs615-tcsr", "syscon";
+			reg = <0x0 0x01fc0000 0x0 0x30000>;
+		};
+
+		tlmm: pinctrl@3100000 {
+			compatible = "qcom,qcs615-tlmm";
+			reg = <0x0 0x03100000 0x0 0x300000>,
+			      <0x0 0x03500000 0x0 0x300000>,
+			      <0x0 0x03d00000 0x0 0x300000>;
+			reg-names = "east",
+				    "west",
+				    "south";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-ranges = <&tlmm 0 0 124>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				pins = "gpio4", "gpio5";
+				function = "qup0";
+
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				pins = "gpio18", "gpio19";
+				function = "qup0";
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				pins = "gpio20", "gpio21";
+				function = "qup1";
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				pins = "gpio14", "gpio15";
+				function = "qup1";
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				pins = "gpio6", "gpio7";
+				function = "qup1";
+			};
+
+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+				pins = "gpio10", "gpio11";
+				function = "qup1";
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup0";
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio3";
+				function = "qup0";
+			};
+
+			qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup1";
+			};
+
+			qup_spi4_cs: qup-spi4-cs-state {
+				pins = "gpio23";
+				function = "qup1";
+			};
+
+			qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
+				pins = "gpio23";
+				function = "gpio";
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				pins = "gpio6", "gpio7", "gpio8";
+				function = "qup1";
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio9";
+				function = "qup1";
+			};
+
+			qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk-state {
+				pins = "gpio10", "gpio11", "gpio12";
+				function = "qup1";
+			};
+
+			qup_spi7_cs: qup-spi7-cs-state {
+				pins = "gpio13";
+				function = "qup1";
+			};
+
+			qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
+				pins = "gpio13";
+				function = "gpio";
+			};
+
+			qup_uart0_tx: qup-uart0-tx-state {
+				pins = "gpio16";
+				function = "qup0";
+			};
+
+			qup_uart0_rx: qup-uart0-rx-state {
+				pins = "gpio17";
+				function = "qup0";
+			};
+
+			qup_uart2_cts: qup-uart2-cts-state {
+				pins = "gpio0";
+				function = "qup0";
+			};
+
+			qup_uart2_rts: qup-uart2-rts-state {
+				pins = "gpio1";
+				function = "qup0";
+			};
+
+			qup_uart2_tx: qup-uart2-tx-state {
+				pins = "gpio2";
+				function = "qup0";
+			};
+
+			qup_uart2_rx: qup-uart2-rx-state {
+				pins = "gpio3";
+				function = "qup0";
+			};
+
+			qup_uart4_cts: qup-uart4-cts-state {
+				pins = "gpio20";
+				function = "qup1";
+			};
+
+			qup_uart4_rts: qup-uart4-rts-state {
+				pins = "gpio21";
+				function = "qup1";
+			};
+
+			qup_uart4_tx: qup-uart4-tx-state {
+				pins = "gpio22";
+				function = "qup1";
+			};
+
+			qup_uart4_rx: qup-uart4-rx-state {
+				pins = "gpio23";
+				function = "qup1";
+			};
+
+			qup_uart6_cts: qup-uart6-cts-state {
+				pins = "gpio6";
+				function = "qup1";
+			};
+
+			qup_uart6_rts: qup-uart6-rts-state {
+				pins = "gpio7";
+				function = "qup1";
+			};
+
+			qup_uart6_tx: qup-uart6-tx-state {
+				pins = "gpio8";
+				function = "qup1";
+			};
+
+			qup_uart6_rx: qup-uart6-rx-state {
+				pins = "gpio9";
+				function = "qup1";
+			};
+
+			qup_uart7_cts: qup-uart7-cts-state {
+				pins = "gpio10";
+				function = "qup1";
+			};
+
+			qup_uart7_rts: qup-uart7-rts-state {
+				pins = "gpio11";
+				function = "qup1";
+			};
+
+			qup_uart7_tx: qup-uart7-tx-state {
+				pins = "gpio12";
+				function = "qup1";
+			};
+
+			qup_uart7_rx: qup-uart7-rx-state {
+				pins = "gpio13";
+				function = "qup1";
+			};
+
+			sdc1_state_on: sdc1-on-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_state_off: sdc1-off-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc2_state_on: sdc2-on-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_state_off: sdc2-off-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+		};
+
+		stm@6002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x06002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel_in0_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@6004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					tpda_qdss_in0: endpoint {
+						remote-endpoint = <&tpdm_center_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					tpda_qdss_in4: endpoint {
+						remote-endpoint = <&funnel_monaq_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					tpda_qdss_in5: endpoint {
+						remote-endpoint = <&funnel_ddr_0_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					tpda_qdss_in6: endpoint {
+						remote-endpoint = <&funnel_turing_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					tpda_qdss_in7: endpoint {
+						remote-endpoint = <&tpdm_vsense_out>;
+					};
+				};
+
+				port@8 {
+					reg = <8>;
+
+					tpda_qdss_in8: endpoint {
+						remote-endpoint = <&tpdm_dcc_out>;
+					};
+				};
+
+				port@9 {
+					reg = <9>;
+
+					tpda_qdss_in9: endpoint {
+						remote-endpoint = <&tpdm_prng_out>;
+					};
+				};
+
+				port@b {
+					reg = <11>;
+
+					tpda_qdss_in11: endpoint {
+						remote-endpoint = <&tpdm_qm_out>;
+					};
+				};
+
+				port@c {
+					reg = <12>;
+
+					tpda_qdss_in12: endpoint {
+						remote-endpoint = <&tpdm_west_out>;
+					};
+				};
+
+				port@d {
+					reg = <13>;
+
+					tpda_qdss_in13: endpoint {
+						remote-endpoint = <&tpdm_pimem_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_qdss_out: endpoint {
+						remote-endpoint = <&funnel_qatb_in>;
+					};
+				};
+			};
+		};
+
+		funnel@6005000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06005000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_qatb_in: endpoint {
+						remote-endpoint = <&tpda_qdss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qatb_out: endpoint {
+						remote-endpoint = <&funnel_in0_in6>;
+					};
+				};
+			};
+		};
+
+		cti@6010000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06010000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6011000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06011000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6012000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06012000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6013000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06013000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6014000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06014000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6015000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06015000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6016000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06016000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6017000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06017000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6018000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06018000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6019000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06019000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601c000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601d000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601e000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601f000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel_in0_in6: endpoint {
+						remote-endpoint = <&funnel_qatb_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_in0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in0_out: endpoint {
+						remote-endpoint = <&funnel_merg_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@6042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@3 {
+					reg = <3>;
+
+					funnel_in1_in3: endpoint {
+						remote-endpoint = <&replicator_swao_out0>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_in1_in4: endpoint {
+						remote-endpoint = <&tpdm_wcss_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_in1_in7: endpoint {
+						remote-endpoint = <&funnel_apss_merg_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out: endpoint {
+						remote-endpoint = <&funnel_merg_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@6045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_merg_in0: endpoint {
+						remote-endpoint = <&funnel_in0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					funnel_merg_in1: endpoint {
+						remote-endpoint = <&funnel_in1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_merg_out: endpoint {
+						remote-endpoint = <&tmc_etf_in>;
+					};
+				};
+			};
+		};
+
+		replicator@6046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x06046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator0_in: endpoint {
+						remote-endpoint= <&tmc_etf_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					replicator0_out1: endpoint {
+						remote-endpoint= <&replicator1_in>;
+					};
+				};
+			};
+		};
+
+		tmc@6047000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x06047000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in: endpoint {
+						remote-endpoint = <&funnel_merg_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_out: endpoint {
+						remote-endpoint = <&replicator0_in>;
+					};
+				};
+			};
+		};
+
+		replicator@604a000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x0604a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator1_in: endpoint {
+						remote-endpoint= <&replicator0_out1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					replicator1_out: endpoint {
+						remote-endpoint= <&funnel_swao_in6>;
+					};
+				};
+			};
+		};
+
+		cti@683b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0683b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6840000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06840000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_vsense_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@684c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0684c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_prng_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in9>;
+					};
+				};
+			};
+		};
+
+		tpdm@6850000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06850000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_pimem_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in13>;
+					};
+				};
+			};
+		};
+
+		tpdm@6860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_turing_out: endpoint {
+						remote-endpoint = <&funnel_turing_in>;
+					};
+				};
+			};
+		};
+
+		funnel@6861000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06861000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_turing_in: endpoint {
+						remote-endpoint = <&tpdm_turing_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_turing_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in6>;
+					};
+				};
+			};
+		};
+
+		cti@6867000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06867000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6870000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06870000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_dcc_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in8>;
+					};
+				};
+			};
+		};
+
+		tpdm@699c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0699c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_wcss_out: endpoint {
+						remote-endpoint = <&funnel_in1_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@69c0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x069c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_monaq_out: endpoint {
+						remote-endpoint = <&funnel_monaq_in>;
+					};
+				};
+			};
+		};
+
+		funnel@69c3000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x069c3000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_monaq_in: endpoint {
+						remote-endpoint = <&tpdm_monaq_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_monaq_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@69d0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x069d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_qm_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in11>;
+					};
+				};
+			};
+		};
+
+		tpdm@6a00000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06a00000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_ddr_out: endpoint {
+						remote-endpoint = <&funnel_ddr_0_in>;
+					};
+				};
+			};
+		};
+
+		cti@6a02000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a02000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a03000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a10000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a10000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a11000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a11000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6a05000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06a05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_ddr_0_in: endpoint {
+						remote-endpoint = <&tpdm_ddr_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_ddr_0_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in5>;
+					};
+				};
+			};
+		};
+
+		tpda@6b01000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06b01000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					tpda_swao_in0: endpoint {
+						remote-endpoint = <&tpdm_swao0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					tpda_swao_in1: endpoint {
+						remote-endpoint = <&tpdm_swao1_out>;
+					};
+
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_swao_out: endpoint {
+						remote-endpoint = <&funnel_swao_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@6b02000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b02000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_swao0_out: endpoint {
+						remote-endpoint = <&tpda_swao_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@6b03000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_swao1_out: endpoint {
+						remote-endpoint = <&tpda_swao_in1>;
+					};
+				};
+			};
+		};
+
+		cti@6b04000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b05000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b06000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b07000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b07000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6b08000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel_swao_in6: endpoint {
+						remote-endpoint= <&replicator1_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_swao_in7: endpoint {
+						remote-endpoint= <&tpda_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_swao_out: endpoint {
+						remote-endpoint = <&tmc_etf_swao_in>;
+					};
+				};
+			};
+		};
+
+		tmc@6b09000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x06b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_swao_in: endpoint {
+						remote-endpoint= <&funnel_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_swao_out: endpoint {
+						remote-endpoint= <&replicator_swao_in>;
+					};
+				};
+			};
+		};
+
+		replicator@6b0a000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x06b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_swao_in: endpoint {
+						remote-endpoint = <&tmc_etf_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					replicator_swao_out0: endpoint {
+						remote-endpoint = <&funnel_in1_in3>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					replicator_swao_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		cti@6b21000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b21000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6b48000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b48000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_west_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in12>;
+					};
+				};
+			};
+		};
+
+		cti@6c13000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6c20000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		tpdm@6c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_center_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in0>;
+					};
+				};
+			};
+		};
+
+		cti@6c29000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6c2a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c2a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@7020000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07020000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7040000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07040000 0x0 0x1000>;
+			cpu = <&cpu0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint = <&funnel_apss_in0>;
+					};
+				};
+			};
+		};
+
+		cti@7120000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07120000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7140000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07140000 0x0 0x1000>;
+			cpu = <&cpu1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint = <&funnel_apss_in1>;
+					};
+				};
+			};
+		};
+
+		cti@7220000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07220000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7240000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07240000 0x0 0x1000>;
+			cpu = <&cpu2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint = <&funnel_apss_in2>;
+					};
+				};
+			};
+		};
+
+		cti@7320000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07320000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7340000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07340000 0x0 0x1000>;
+			cpu = <&cpu3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint = <&funnel_apss_in3>;
+					};
+				};
+			};
+		};
+
+		cti@7420000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07420000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7440000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07440000 0x0 0x1000>;
+			cpu = <&cpu4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint = <&funnel_apss_in4>;
+					};
+				};
+			};
+		};
+
+		cti@7520000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07520000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7540000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07540000 0x0 0x1000>;
+			cpu = <&cpu5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint = <&funnel_apss_in5>;
+					};
+				};
+			};
+		};
+
+		cti@7620000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07620000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7640000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07640000 0x0 0x1000>;
+			cpu = <&cpu6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint = <&funnel_apss_in6>;
+					};
+				};
+			};
+		};
+
+		cti@7720000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07720000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7740000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07740000 0x0 0x1000>;
+			cpu = <&cpu7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint = <&funnel_apss_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@7800000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x07800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_apss_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					funnel_apss_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					funnel_apss_in2: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					funnel_apss_in3: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_apss_in4: endpoint {
+						remote-endpoint = <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel_apss_in5: endpoint {
+						remote-endpoint = <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel_apss_in6: endpoint {
+						remote-endpoint = <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_apss_in7: endpoint {
+						remote-endpoint = <&etm7_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@7810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x07810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_apss_merg_in0: endpoint {
+						remote-endpoint = <&funnel_apss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					funnel_apss_merg_in2: endpoint {
+						remote-endpoint = <&tpda_olc_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					funnel_apss_merg_in3: endpoint {
+						remote-endpoint = <&tpda_llm_silver_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_apss_merg_in4: endpoint {
+						remote-endpoint = <&tpda_llm_gold_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel_apss_merg_in5: endpoint {
+						remote-endpoint = <&tpda_apss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_merg_out: endpoint {
+						remote-endpoint = <&funnel_in1_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@7830000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x07830000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_olc_out: endpoint {
+						remote-endpoint = <&tpda_olc_in>;
+					};
+				};
+			};
+		};
+
+		tpda@7832000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x07832000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_olc_in: endpoint {
+						remote-endpoint = <&tpdm_olc_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_olc_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@7860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x07860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_apss_out: endpoint {
+						remote-endpoint = <&tpda_apss_in>;
+					};
+				};
+			};
+		};
+
+		tpda@7862000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x07862000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_apss_in: endpoint {
+						remote-endpoint = <&tpdm_apss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_apss_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@78a0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x078a0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_llm_silver_out: endpoint {
+						remote-endpoint = <&tpda_llm_silver_in>;
+					};
+				};
+			};
+		};
+
+		tpdm@78b0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x078b0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_llm_gold_out: endpoint {
+						remote-endpoint = <&tpda_llm_gold_in>;
+					};
+				};
+			};
+		};
+
+		tpda@78c0000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x078c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_llm_silver_in: endpoint {
+						remote-endpoint = <&tpdm_llm_silver_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_llm_silver_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in3>;
+					};
+				};
+			};
+		};
+
+		tpda@78d0000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x078d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_llm_gold_in: endpoint {
+						remote-endpoint = <&tpdm_llm_gold_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_llm_gold_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in4>;
+					};
+				};
+			};
+		};
+
+		cti@78e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x078e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@78f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x078f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@7900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		pmu@90b6300 {
+			compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x090b6300 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <12896000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <14928000>;
+				};
+			};
+		};
+
+		pmu@90cd000 {
+			compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0x0 0x090cd000 0x0 0x1000>;
+			interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <800000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1200000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <1804800>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2188800>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2726400>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <3072000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <4070400>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <5414400>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <6220800>;
+				};
+			};
+		};
+
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x08804000 0x0 0x1000>;
+			reg-names = "hc";
+
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq",
+					  "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+			iommus = <&apps_smmu 0x02a0 0x0>;
+			resets = <&gcc GCC_SDCC2_BCR>;
+			interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr",
+					     "cpu-sdhc";
+
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		dc_noc: interconnect@9160000 {
+			reg = <0x0 0x09160000 0x0 0x3200>;
+			compatible = "qcom,qcs615-dc-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		llcc: system-cache-controller@9200000 {
+			compatible = "qcom,qcs615-llcc";
+			reg = <0x0 0x09200000 0x0 0x50000>,
+			      <0x0 0x09600000 0x0 0x50000>;
+			reg-names = "llcc0_base",
+				    "llcc_broadcast_base";
+		};
+
+		gem_noc: interconnect@9680000 {
+			reg = <0x0 0x09680000 0x0 0x3e200>;
+			compatible = "qcom,qcs615-gem-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,qcs615-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		aoss_qmp: power-controller@c300000 {
+			compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&apss_shared 0>;
+
+			#clock-cells = <0>;
+			#power-domain-cells = <1>;
+		};
+
+		sram@c3f0000 {
+			compatible = "qcom,rpmh-stats";
+			reg = <0x0 0x0c3f0000 0x0 0x400>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x80000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			dma-coherent;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		spmi_bus: spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0 0x0c440000 0x0 0x1100>,
+			      <0x0 0x0c600000 0x0 0x2000000>,
+			      <0x0 0x0e600000 0x0 0x100000>,
+			      <0x0 0x0e700000 0x0 0xa0000>,
+			      <0x0 0x0c40a000 0x0 0x26000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			qcom,channel = <0>;
+			qcom,ee = <0>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
+			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		apss_shared: mailbox@17c00000 {
+			compatible = "qcom,qcs615-apss-shared",
+				     "qcom,sdm845-apss-shared";
+			reg = <0x0 0x17c00000 0x0 0x1000>;
+			#mbox-cells = <1>;
+		};
+
+		watchdog: watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0 0 0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@18200000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x18200000 0x0 0x10000>,
+			      <0x0 0x18210000 0x0 0x10000>,
+			      <0x0 0x18220000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,tcs-config = <ACTIVE_TCS    2>,
+					  <SLEEP_TCS     3>,
+					  <WAKE_TCS      3>,
+					  <CONTROL_TCS   1>;
+
+			label = "apps_rsc";
+			power-domains = <&cluster_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,qcs615-rpmh-clk";
+				clock-names = "xo";
+
+				#clock-cells = <1>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,qcs615-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-0 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs: opp-2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp-3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp-5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		usb_1_hsphy: phy@88e2000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x88e2000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+			nvmem-cells = <&qusb2_hstx_trim>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_hsphy_2: phy@88e3000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb",
+				      "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_qmpphy: phy@88e6000 {
+			compatible = "qcom,qcs615-qmp-usb3-phy";
+			reg = <0x0 0x88e6000 0x0 0x1000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+				 <&gcc GCC_AHB2PHY_WEST_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
+			reset-names = "phy", "phy_phy";
+
+			qcom,tcsr-reg = <&tcsr 0xb244>;
+
+			clock-output-names = "usb3_phy_pipe_clk_src";
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0x140 0x0>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_1_hsphy>, <&usb_qmpphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+			};
+		};
+
+		usb_2: usb@a8f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a8f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB2_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc USB20_SEC_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_SEC_BCR>;
+
+			qcom,select-utmi-as-pipe-clk;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a800000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a800000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0xe0 0x0>;
+				interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_hsphy_2>;
+				phy-names = "usb2-phy";
+
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+
+				maximum-speed = "high-speed";
+			};
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
index 27695bd5422..7a36c90ad4e 100644
--- a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
+++ b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
@@ -9,6 +9,7 @@
 #define PM7250B_SID 8
 #define PM7250B_SID1 9
 
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sc7280.dtsi"
@@ -744,6 +745,46 @@
 	};
 };
 
+&pm8350c_pwm {
+	nvmem = <&pmk8350_sdam_21>,
+		<&pmk8350_sdam_22>;
+	nvmem-names = "lpg_chan_sdam",
+		      "lut_sdam";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+
+	led@1 {
+		reg = <1>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <3>;
+		linux,default-trigger = "none";
+		default-state = "off";
+		panic-indicator;
+	};
+
+	led@2 {
+		reg = <2>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <2>;
+		linux,default-trigger = "none";
+		default-state = "off";
+	};
+
+	led@3 {
+		reg = <3>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <1>;
+		linux,default-trigger = "none";
+		default-state = "off";
+	};
+};
+
 &pmk8350_rtc {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/qcs8300-ride.dts b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts
new file mode 100644
index 00000000000..b5c9f89b343
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "qcs8300.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. QCS8300 Ride";
+	compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
+	chassis-type = "embedded";
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9a: smps9 {
+			regulator-name = "vreg_s9a";
+			regulator-min-microvolt = <1352000>;
+			regulator-max-microvolt = <1352000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a: ldo3 {
+			regulator-name = "vreg_l3a";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4a: ldo4 {
+			regulator-name = "vreg_l4a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a: ldo6 {
+			regulator-name = "vreg_l6a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a: ldo9 {
+			regulator-name = "vreg_l9a";
+			regulator-min-microvolt = <2970000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_s5c: smps5 {
+			regulator-name = "vreg_s5c";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <500000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4c: ldo4 {
+			regulator-name = "vreg_l4c";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&ethernet0 {
+	phy-mode = "2500base-x";
+	phy-handle = <&phy0>;
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: phy@8 {
+			compatible = "ethernet-phy-id31c3.1c33";
+			reg = <0x8>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 4 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+		snps,tx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/qcs8300/adsp.mbn";
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/qcs8300/cdsp0.mbn";
+	status = "okay";
+};
+
+&remoteproc_gpdsp {
+	firmware-name = "qcom/qcs8300/gpdsp0.mbn";
+	status = "okay";
+};
+
+&serdes0 {
+	phy-supply = <&vreg_l5a>;
+	status = "okay";
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio5";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio6";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l8a>;
+	vcc-max-microamp = <1100000>;
+	vccq-supply = <&vreg_l4c>;
+	vccq-max-microamp = <1200000>;
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l5a>;
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l7a>;
+	vdda18-supply = <&vreg_l7c>;
+	vdda33-supply = <&vreg_l9a>;
+
+	status = "okay";
+};
+
+&usb_qmpphy {
+	vdda-phy-supply = <&vreg_l7a>;
+	vdda-pll-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "peripheral";
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8300.dtsi b/dts/upstream/src/arm64/qcom/qcs8300.dtsi
new file mode 100644
index 00000000000..4a057f7c0d9
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8300.dtsi
@@ -0,0 +1,3548 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_1>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
+
+			l2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_2>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
+
+			l2_2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_3>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
+
+			l2_3: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu4: cpu@10000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&l2_4>;
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_4: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu5: cpu@10100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_5>;
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_5: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu6: cpu@10200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_6>;
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_6: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu7: cpu@10300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_7>;
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_7: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l3_0: l3-cache-0 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
+		l3_1: l3-cache-1 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			little_cpu_sleep_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <449>;
+				exit-latency-us = <801>;
+				min-residency-us = <1574>;
+				local-timer-stop;
+			};
+
+			little_cpu_sleep_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <602>;
+				exit-latency-us = <961>;
+				min-residency-us = <4288>;
+				local-timer-stop;
+			};
+
+			big_cpu_sleep_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <549>;
+				exit-latency-us = <901>;
+				min-residency-us = <1774>;
+				local-timer-stop;
+			};
+
+			big_cpu_sleep_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <702>;
+				exit-latency-us = <1061>;
+				min-residency-us = <4488>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			silver_cluster_sleep: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2552>;
+				exit-latency-us = <2848>;
+				min-residency-us = <5908>;
+			};
+
+			gold_cluster_sleep: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2752>;
+				exit-latency-us = <3048>;
+				min-residency-us = <6118>;
+			};
+
+			system_sleep: domain-sleep {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x42000144>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9987>;
+			};
+		};
+	};
+
+	dummy_eud: dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&swao_rep_out1>;
+				};
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-qcs8300", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,qcs8300-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,qcs8300-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cluster_pd0: power-domain-cluster0 {
+			#power-domain-cells = <0>;
+			power-domains = <&system_pd>;
+			domain-idle-states = <&gold_cluster_sleep>;
+		};
+
+		cluster_pd1: power-domain-cluster1 {
+			#power-domain-cells = <0>;
+			power-domains = <&system_pd>;
+			domain-idle-states = <&silver_cluster_sleep>;
+		};
+
+		system_pd: power-domain-system {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&system_sleep>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		aop_image_mem: aop-image-region@90800000 {
+			reg = <0x0 0x90800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db-region@90860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x90860000 0x0 0x20000>;
+			no-map;
+		};
+
+		smem_mem: smem@90900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x90900000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
+			reg = <0x0 0x93b00000 0x0 0xf00000>;
+			no-map;
+		};
+
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
+			reg = <0x0 0x94a00000 0x0 0x800000>;
+			no-map;
+		};
+
+		camera_mem: camera-region@95200000 {
+			reg = <0x0 0x95200000 0x0 0x500000>;
+			no-map;
+		};
+
+		adsp_mem: adsp-region@95c00000 {
+			no-map;
+			reg = <0x0 0x95c00000 0x0 0x1e00000>;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
+			reg = <0x0 0x97a00000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
+			reg = <0x0 0x97a80000 0x0 0x80000>;
+			no-map;
+		};
+
+		gpdsp_mem: gpdsp-region@97b00000 {
+			reg = <0x0 0x97b00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
+			reg = <0x0 0x99900000 0x0 0x80000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp-region@99980000 {
+			reg = <0x0 0x99980000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		gpu_microcode_mem: gpu-microcode-region@9b780000 {
+			reg = <0x0 0x9b780000 0x0 0x2000>;
+			no-map;
+		};
+
+		cvp_mem: cvp-region@9b782000 {
+			reg = <0x0 0x9b782000 0x0 0x700000>;
+			no-map;
+		};
+
+		video_mem: video-region@9be82000 {
+			reg = <0x0 0x9be82000 0x0 0x700000>;
+			no-map;
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <443>, <429>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <94>, <432>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		smp2p_cdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_cdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	smp2p-gpdsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_GPDSP0
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <617>, <616>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <17>;
+
+		smp2p_gpdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_gpdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x10 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,qcs8300-gcc";
+			reg = <0x0 0x00100000 0x0 0xc7018>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+		};
+
+		ipcc: mailbox@408000 {
+			compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
+			reg = <0x0 0x408000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
+		qfprom: efuse@784000 {
+			compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
+			reg = <0x0 0x00784000 0x0 0x1200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x9c0000 0x0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			uart7: serial@99c000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x0099c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				status = "disabled";
+			};
+		};
+
+		rng: rng@10d2000 {
+			compatible = "qcom,qcs8300-trng", "qcom,trng";
+			reg = <0x0 0x010d2000 0x0 0x1000>;
+		};
+
+		config_noc: interconnect@14c0000 {
+			compatible = "qcom,qcs8300-config-noc";
+			reg = <0x0 0x014c0000 0x0 0x13080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,qcs8300-system-noc";
+			reg = <0x0 0x01680000 0x0 0x15080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@16c0000 {
+			compatible = "qcom,qcs8300-aggre1-noc";
+			reg = <0x0 0x016c0000 0x0 0x17080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,qcs8300-aggre2-noc";
+			reg = <0x0 0x01700000 0x0 0x1a080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_anoc: interconnect@1760000 {
+			compatible = "qcom,qcs8300-pcie-anoc";
+			reg = <0x0 0x01760000 0x0 0xc080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gpdsp_anoc: interconnect@1780000 {
+			compatible = "qcom,qcs8300-gpdsp-anoc";
+			reg = <0x0 0x01780000 0x0 0xd080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@17a0000 {
+			compatible = "qcom,qcs8300-mmss-noc";
+			reg = <0x0 0x017a0000 0x0 0x40000>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			#reset-cells = <1>;
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			iommus = <&apps_smmu 0x100 0x0>;
+			dma-coherent;
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "rx_lane1_sync_clk";
+			freq-table-hz = <75000000 300000000>,
+					<0 0>,
+					<0 0>,
+					<75000000 300000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>,
+					<0 0>;
+			qcom,ice = <&ice>;
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
+			reg = <0x0 0x01d87000 0x0 0xe10>;
+			/*
+			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
+			 * enables the CXO clock to eDP *and* UFS PHY.
+			 */
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_EDP_REF_CLKREF_EN>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x0 0x01dc4000 0x0 0x28000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			num-channels = <20>;
+			qcom,num-ees = <4>;
+			iommus = <&apps_smmu 0x480 0x00>,
+				 <&apps_smmu 0x481 0x00>;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,qcs8300-qce", "qcom,qce";
+			reg = <0x0 0x01dfa000 0x0 0x6000>;
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x480 0x00>,
+				 <&apps_smmu 0x481 0x00>;
+			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "memory";
+		};
+
+		ice: crypto@1d88000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,qcs8300-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
+			reg = <0x0 0x3000000 0x0 0x00100>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					memory-region = <&adsp_rpc_remote_heap_mem>;
+					qcom,vmids = <QCOM_SCM_VMID_LPASS
+						      QCOM_SCM_VMID_ADSP_HEAP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x2003 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x2004 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x2005 0x0>;
+						dma-coherent;
+					};
+				};
+			};
+		};
+
+		lpass_ag_noc: interconnect@3c40000 {
+			compatible = "qcom,qcs8300-lpass-ag-noc";
+			reg = <0x0 0x03c40000 0x0 0x17200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		stm@4002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x04002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@4004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					qdss_tpda_in1: endpoint {
+						remote-endpoint = <&qdss_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_tpda_out: endpoint {
+						remote-endpoint = <&funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@400f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0400f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					qdss_tpdm1_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@4041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel0_in6: endpoint {
+						remote-endpoint = <&qdss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					funnel1_in4: endpoint {
+						remote-endpoint = <&apss_funnel1_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel1_in5: endpoint {
+						remote-endpoint = <&dlct0_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel1_in6: endpoint {
+						remote-endpoint = <&dlmm_funnel_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel1_in7: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@4045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_funnel_in0: endpoint {
+						remote-endpoint = <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_funnel_in1: endpoint {
+						remote-endpoint = <&funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@4841000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04841000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					prng_tpdm_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in19>;
+					};
+				};
+			};
+		};
+
+		tpdm@4850000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04850000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					pimem_tpdm_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in25>;
+					};
+				};
+			};
+		};
+
+		tpdm@4860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_ch_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_ch_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4864000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04864000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_ch_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_ch_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_ch_tpda_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4865000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04865000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlst_ch_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_ch_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlst_ch_funnel_in4: endpoint {
+						remote-endpoint = <&dlst_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					dlst_ch_funnel_in6: endpoint {
+						remote-endpoint = <&gdsp_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_ch_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@4980000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04980000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					turing2_tpdm_out: endpoint {
+						remote-endpoint = <&turing2_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4983000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04983000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing2_funnel_in0: endpoint {
+						remote-endpoint = <&turing2_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing2_funnel_out0: endpoint {
+						remote-endpoint = <&gdsp_tpda_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@4ac0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04ac0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlmm_tpdm0_out: endpoint {
+						remote-endpoint = <&dlmm_tpda_in27>;
+					};
+				};
+			};
+		};
+
+		tpda@4ac4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04ac4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1b {
+					reg = <27>;
+
+					dlmm_tpda_in27: endpoint {
+						remote-endpoint = <&dlmm_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlmm_tpda_out: endpoint {
+						remote-endpoint = <&dlmm_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4ac5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04ac5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlmm_funnel_in0: endpoint {
+						remote-endpoint = <&dlmm_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlmm_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4ad0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04ad0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct0_tpdm0_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in26>;
+					};
+				};
+			};
+		};
+
+		tpda@4ad3000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04ad3000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@13 {
+					reg = <19>;
+
+					dlct0_tpda_in19: endpoint {
+						remote-endpoint = <&prng_tpdm_out>;
+					};
+				};
+
+				port@19 {
+					reg = <25>;
+
+					dlct0_tpda_in25: endpoint {
+						remote-endpoint = <&pimem_tpdm_out>;
+					};
+				};
+
+				port@1a {
+					reg = <26>;
+
+					dlct0_tpda_in26: endpoint {
+						remote-endpoint = <&dlct0_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct0_tpda_out: endpoint {
+						remote-endpoint = <&dlct0_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4ad4000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04ad4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlct0_funnel_in0: endpoint {
+						remote-endpoint = <&dlct0_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlct0_funnel_in4: endpoint {
+						remote-endpoint = <&ddr_funnel5_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct0_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in5>;
+					};
+				};
+			};
+		};
+
+		funnel@4b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					aoss_funnel_in6: endpoint {
+						remote-endpoint = <&aoss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					aoss_funnel_in7: endpoint {
+						remote-endpoint = <&qdss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_funnel_out: endpoint {
+						remote-endpoint = <&etf0_in>;
+					};
+				};
+			};
+		};
+
+		tmc_etf: tmc@4b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x04b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etf0_in: endpoint {
+						remote-endpoint = <&aoss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf0_out: endpoint {
+						remote-endpoint = <&swao_rep_in>;
+					};
+				};
+			};
+		};
+
+		replicator@4b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x04b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					swao_rep_in: endpoint {
+						remote-endpoint = <&etf0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					swao_rep_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		tpda@4b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					aoss_tpda_in0: endpoint {
+						remote-endpoint = <&aoss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					aoss_tpda_in1: endpoint {
+						remote-endpoint = <&aoss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					aoss_tpda_in2: endpoint {
+						remote-endpoint = <&aoss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					aoss_tpda_in3: endpoint {
+						remote-endpoint = <&aoss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					aoss_tpda_in4: endpoint {
+						remote-endpoint = <&aoss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_tpda_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm0_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm1_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm2_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm3_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm4_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		cti@4b13000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x04b13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@4b80000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b80000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					turing0_tpdm0_out: endpoint {
+						remote-endpoint = <&turing0_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpda@4b86000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04b86000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing0_tpda_in0: endpoint {
+						remote-endpoint = <&turing0_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing0_tpda_out: endpoint {
+						remote-endpoint = <&turing0_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4b87000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04b87000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing0_funnel_in0: endpoint {
+						remote-endpoint = <&turing0_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing0_funnel_out: endpoint {
+						remote-endpoint = <&gdsp_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		cti@4b8b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x04b8b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@4c40000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04c40000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					gdsp_tpdm0_out: endpoint {
+						remote-endpoint = <&gdsp_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4c44000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04c44000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@5 {
+					reg = <5>;
+
+					gdsp_tpda_in5: endpoint {
+						remote-endpoint = <&turing2_funnel_out0>;
+					};
+				};
+
+				port@8 {
+					reg = <8>;
+
+					gdsp_tpda_in8: endpoint {
+						remote-endpoint = <&gdsp_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					gdsp_tpda_out: endpoint {
+						remote-endpoint = <&gdsp_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4c45000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04c45000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					gdsp_funnel_in0: endpoint {
+						remote-endpoint = <&gdsp_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					gdsp_funnel_in4: endpoint {
+						remote-endpoint = <&turing0_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					gdsp_funnel_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4c50000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04c50000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4c54000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04c54000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_tpda_out: endpoint {
+						remote-endpoint = <&dlst_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4c55000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04c55000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlst_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_funnel_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e00000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e00000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm3_out: endpoint {
+						remote-endpoint = <&ddr_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpda@4e03000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04e03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ddr_tpda_in0: endpoint {
+						remote-endpoint = <&ddr_funnel0_out0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					ddr_tpda_in1: endpoint {
+						remote-endpoint = <&ddr_funnel1_out0>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					ddr_tpda_in4: endpoint {
+						remote-endpoint = <&ddr_tpdm3_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_tpda_out: endpoint {
+						remote-endpoint = <&ddr_funnel5_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel5_in0: endpoint {
+						remote-endpoint = <&ddr_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel5_out: endpoint {
+						remote-endpoint = <&dlct0_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e10000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e10000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm0_out: endpoint {
+						remote-endpoint = <&ddr_funnel0_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e12000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e12000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel0_in0: endpoint {
+						remote-endpoint = <&ddr_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel0_out0: endpoint {
+						remote-endpoint = <&ddr_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e20000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm1_out: endpoint {
+						remote-endpoint = <&ddr_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e22000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e22000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel1_in0: endpoint {
+						remote-endpoint = <&ddr_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel1_out0: endpoint {
+						remote-endpoint = <&ddr_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		etm@6040000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06040000 0x0 0x1000>;
+			cpu = <&cpu0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in0>;
+					};
+				};
+			};
+		};
+
+		etm@6140000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06140000 0x0 0x1000>;
+			cpu = <&cpu1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in1>;
+					};
+				};
+			};
+		};
+
+		etm@6240000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06240000 0x0 0x1000>;
+			cpu = <&cpu2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in2>;
+					};
+				};
+			};
+		};
+
+		etm@6340000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06340000 0x0 0x1000>;
+			cpu = <&cpu3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in3>;
+					};
+				};
+			};
+		};
+
+		etm@6440000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06440000 0x0 0x1000>;
+			cpu = <&cpu4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in4>;
+					};
+				};
+			};
+		};
+
+		etm@6540000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06540000 0x0 0x1000>;
+			cpu = <&cpu5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in5>;
+					};
+				};
+			};
+		};
+
+		etm@6640000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06640000 0x0 0x1000>;
+			cpu = <&cpu6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		etm@6740000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06740000 0x0 0x1000>;
+			cpu = <&cpu7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@6800000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_funnel0_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					apss_funnel0_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					apss_funnel0_in2: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_funnel0_in3: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					apss_funnel0_in4: endpoint {
+						remote-endpoint = <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					apss_funnel0_in5: endpoint {
+						remote-endpoint = <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					apss_funnel0_in6: endpoint {
+						remote-endpoint = <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					apss_funnel0_in7: endpoint {
+						remote-endpoint = <&etm7_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel0_out: endpoint {
+						remote-endpoint = <&apss_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@6810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_funnel1_in0: endpoint {
+						remote-endpoint = <&apss_funnel0_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_funnel1_in3: endpoint {
+						remote-endpoint = <&apss_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel1_out: endpoint {
+						remote-endpoint = <&funnel1_in4>;
+					};
+				};
+			};
+		};
+
+		cti@682b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0682b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm3_out: endpoint {
+						remote-endpoint = <&apss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@6861000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06861000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm4_out: endpoint {
+						remote-endpoint = <&apss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpda@6863000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06863000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_tpda_in0: endpoint {
+						remote-endpoint = <&apss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					apss_tpda_in1: endpoint {
+						remote-endpoint = <&apss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					apss_tpda_in2: endpoint {
+						remote-endpoint = <&apss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_tpda_in3: endpoint {
+						remote-endpoint = <&apss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					apss_tpda_in4: endpoint {
+						remote-endpoint = <&apss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_tpda_out: endpoint {
+						remote-endpoint = <&apss_funnel1_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@68a0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068a0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm1_out: endpoint {
+						remote-endpoint = <&apss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@68b0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068b0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm0_out: endpoint {
+						remote-endpoint = <&apss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@68c0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm2_out: endpoint {
+						remote-endpoint = <&apss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		cti@68e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x068e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@68f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x068f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		usb_1_hsphy: phy@8904000 {
+			compatible = "qcom,qcs8300-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0x0 0x08904000 0x0 0x400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_2_hsphy: phy@8906000 {
+			compatible = "qcom,qcs8300-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0x0 0x08906000 0x0 0x400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_qmpphy: phy@8907000 {
+			compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
+			reg = <0x0 0x08907000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&gcc GCC_USB_CLKREF_EN>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "com_aux",
+				      "pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+			reset-names = "phy", "phy_phy";
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "usb3_prim_phy_pipe_clk_src";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		serdes0: phy@8909000 {
+			compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
+			reg = <0x0 0x08909000 0x0 0x00000e10>;
+			clocks = <&gcc GCC_SGMI_CLKREF_EN>;
+			clock-names = "sgmi_ref";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,qcs8300-gpucc";
+			reg = <0x0 0x03d90000 0x0 0xa000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk_src",
+				      "gcc_gpu_gpll0_div_clk_src";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		pmu@9091000 {
+			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0x0 0x9091000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2601000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <5931000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <6515000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <7984000>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <10437000>;
+				};
+
+				opp-9 {
+					opp-peak-kBps = <12195000>;
+				};
+			};
+		};
+
+		pmu@90b5400 {
+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b5400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <16265000>;
+				};
+			};
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b6400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+		};
+
+		dc_noc: interconnect@90e0000 {
+			compatible = "qcom,qcs8300-dc-noc";
+			reg = <0x0 0x090e0000 0x0 0x5080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gem_noc: interconnect@9100000 {
+			compatible = "qcom,qcs8300-gem-noc";
+			reg = <0x0 0x9100000 0x0 0xf7080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		llcc: system-cache-controller@9200000 {
+			compatible = "qcom,qcs8300-llcc";
+			reg = <0x0 0x09200000 0x0 0x80000>,
+			      <0x0 0x09300000 0x0 0x80000>,
+			      <0x0 0x09400000 0x0 0x80000>,
+			      <0x0 0x09500000 0x0 0x80000>,
+			      <0x0 0x09a00000 0x0 0x80000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc_broadcast_base";
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+			interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			wakeup-source;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xe000>;
+				interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x80 0x0>;
+				phys = <&usb_1_hsphy>, <&usb_qmpphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		usb_2: usb@a4f8800 {
+			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a4f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB20_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB20_SLEEP_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <120000000>;
+
+			interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+			interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			qcom,select-utmi-as-pipe-clk;
+			wakeup-source;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a400000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a400000 0x0 0xe000>;
+
+				interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x20 0x0>;
+
+				phys = <&usb_2_hsphy>;
+				phy-names = "usb2-phy";
+				maximum-speed = "high-speed";
+
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+			};
+		};
+
+		videocc: clock-controller@abf0000 {
+			compatible = "qcom,qcs8300-videocc";
+			reg = <0x0 0x0abf0000 0x0 0x10000>;
+			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ade0000 {
+			compatible = "qcom,qcs8300-camcc";
+			reg = <0x0 0x0ade0000 0x0 0x20000>;
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,sa8775p-dispcc0";
+			reg = <0x0 0x0af00000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,qcs8300-pdc", "qcom,pdc";
+			reg = <0x0 0xb220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			qcom,pdc-ranges = <0 480 40>,
+					  <40 140 14>,
+					  <54 263 1>,
+					  <55 306 4>,
+					  <59 312 3>,
+					  <62 374 2>,
+					  <64 434 2>,
+					  <66 438 2>,
+					  <70 520 1>,
+					  <73 523 1>,
+					  <118 568 6>,
+					  <124 609 3>,
+					  <159 638 1>,
+					  <160 720 3>,
+					  <169 728 30>,
+					  <199 416 2>,
+					  <201 449 1>,
+					  <202 89 1>,
+					  <203 451 1>,
+					  <204 462 1>,
+					  <205 264 1>,
+					  <206 579 1>,
+					  <207 653 1>,
+					  <208 656 1>,
+					  <209 659 1>,
+					  <210 122 1>,
+					  <211 699 1>,
+					  <212 705 1>,
+					  <213 450 1>,
+					  <214 643 2>,
+					  <216 646 5>,
+					  <221 390 5>,
+					  <226 700 2>,
+					  <228 440 1>,
+					  <229 663 1>,
+					  <230 524 2>,
+					  <232 612 3>,
+					  <235 723 5>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+					       IPCC_MPROC_SIGNAL_GLINK_QMP
+					       IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			#clock-cells = <0>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,qcs8300-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 134>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+
+			qup_uart7_default: qup-uart7-state {
+				/* TX, RX */
+				pins = "gpio43", "gpio44";
+				function = "qup0_se7";
+			};
+		};
+
+		sram: sram@146d8000 {
+			compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
+			reg = <0x0 0x146d8000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x146d8000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pil-reloc@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI  98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI  99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a60000 0x0 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			clocks = <&sleep_clk>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@18200000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x18200000 0x0 0x10000>,
+			      <0x0 0x18210000 0x0 0x10000>,
+			      <0x0 0x18220000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			power-domains = <&system_pd>;
+			label = "apps_rsc";
+
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS 2>,
+					  <SLEEP_TCS 3>,
+					  <WAKE_TCS 3>,
+					  <CONTROL_TCS 0>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sa8775p-rpmh-clk";
+				#clock-cells = <1>;
+				clocks = <&xo_board_clk>;
+				clock-names = "xo";
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,qcs8300-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-0 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs: opp-2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp-3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp-5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		remoteproc_gpdsp: remoteproc@20c00000 {
+			compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
+			reg = <0x0 0x20c00000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_gpdsp_in 0 0>,
+					      <&smp2p_gpdsp_in 1 0>,
+					      <&smp2p_gpdsp_in 2 0>,
+					      <&smp2p_gpdsp_in 3 0>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>;
+			power-domain-names = "cx",
+					     "mxc";
+
+			interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&gpdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_gpdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_GPDSP0
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "gpdsp";
+				qcom,remote-pid = <17>;
+			};
+		};
+
+		ethernet0: ethernet@23040000 {
+			compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
+			reg = <0x0 0x23040000 0x0 0x00010000>,
+			      <0x0 0x23056000 0x0 0x00000100>;
+			reg-names = "stmmaceth", "rgmii";
+
+			interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "sfty";
+
+			clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+				 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
+				 <&gcc GCC_EMAC0_PTP_CLK>,
+				 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
+			clock-names = "stmmaceth",
+				      "pclk",
+				      "ptp_ref",
+				      "phyaux";
+			power-domains = <&gcc GCC_EMAC0_GDSC>;
+
+			phys = <&serdes0>;
+			phy-names = "serdes";
+
+			iommus = <&apps_smmu 0x120 0xf>;
+			dma-coherent;
+
+			snps,tso;
+			snps,pbl = <32>;
+			rx-fifo-depth = <16384>;
+			tx-fifo-depth = <20480>;
+
+			status = "disabled";
+		};
+
+		nspa_noc: interconnect@260c0000 {
+			compatible = "qcom,qcs8300-nspa-noc";
+			reg = <0x0 0x260c0000 0x0 0x16080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		remoteproc_cdsp: remoteproc@26300000 {
+			compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
+			reg = <0x0 0x26300000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_NSP0>;
+
+			power-domain-names = "cx",
+					     "mxc",
+					     "nsp";
+
+			interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&cdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_cdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_CDSP
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "cdsp";
+				qcom,remote-pid = <5>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "cdsp";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+						iommus = <&apps_smmu 0x19c1 0x0440>,
+							 <&apps_smmu 0x1961 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+						iommus = <&apps_smmu 0x19c2 0x0440>,
+							 <&apps_smmu 0x1962 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x19c3 0x0440>,
+							 <&apps_smmu 0x1963 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x19c4 0x0440>,
+							 <&apps_smmu 0x1964 0x0400>;
+						dma-coherent;
+					};
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
index f6960e2d466..e6ac529e6b7 100644
--- a/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
@@ -367,7 +367,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &ufs_mem_hc {
diff --git a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
index e65305f8136..d125fc77ae1 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
@@ -22,20 +22,6 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	clocks {
-		xo_board: xo-board-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <19200000>;
-			#clock-cells = <0>;
-		};
-
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <32000>;
-			#clock-cells = <0>;
-		};
-	};
-
 	ppvar_sys: ppvar-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "ppvar_sys";
@@ -239,6 +225,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qup_i2c1_data_clk {
 	drive-strength = <2>;
 	bias-pull-up;
diff --git a/dts/upstream/src/arm64/qcom/qdu1000.dtsi b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
index 47c0dd31aaf..f973aa8f747 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000.dtsi
+++ b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
@@ -21,6 +21,20 @@
 
 	chosen: chosen { };
 
+	clocks {
+		xo_board: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <19200000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			#clock-cells = <0>;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -1009,6 +1023,8 @@
 				iommus = <&apps_smmu 0xc0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>,
 				       <&usb_1_qmpphy>;
 				phy-names = "usb2-phy",
diff --git a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
index a9540e92d3e..52db1884780 100644
--- a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
+++ b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
 #include <dt-bindings/usb/pd.h>
 #include "sm4250.dtsi"
 #include "pm6125.dtsi"
@@ -103,6 +105,55 @@
 		};
 	};
 
+	sound {
+		compatible = "qcom,qrb4210-rb2-sndcard";
+		pinctrl-0 = <&lpi_i2s2_active>;
+		pinctrl-names = "default";
+		model = "Qualcomm-RB2-WSA8815-Speakers-DMIC0";
+		audio-routing = "MM_DL1", "MultiMedia1 Playback",
+				"MM_DL2", "MultiMedia2 Playback";
+
+		mm1-dai-link {
+			link-name = "MultiMedia1";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+			};
+		};
+
+		mm2-dai-link {
+			link-name = "MultiMedia2";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+			};
+		};
+
+		mm3-dai-link {
+			link-name = "MultiMedia3";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+			};
+		};
+
+		hdmi-dai-link {
+			link-name = "HDMI Playback";
+
+			cpu {
+				sound-dai = <&q6afedai SECONDARY_MI2S_RX>;
+			};
+
+			platform {
+				sound-dai = <&q6routing>;
+			};
+
+			codec {
+				sound-dai = <&lt9611_codec 0>;
+			};
+		};
+	};
+
 	vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
 		compatible = "regulator-fixed";
 		regulator-name = "VREG_HDMI_OUT_1P2";
@@ -318,6 +369,14 @@
 	status = "okay";
 };
 
+/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */
+&q6afedai {
+	dai@20 {
+		reg = <SECONDARY_MI2S_RX>;
+		qcom,sd-lines = <0>;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -545,7 +604,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
index 52eef88e882..7afa5acac3f 100644
--- a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
+++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
@@ -964,6 +964,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/qru1000-idp.dts b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
index 1c781d9e24c..439f5c327dc 100644
--- a/dts/upstream/src/arm64/qcom/qru1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
@@ -22,20 +22,6 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	clocks {
-		xo_board: xo-board-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <19200000>;
-			#clock-cells = <0>;
-		};
-
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <32000>;
-			#clock-cells = <0>;
-		};
-	};
-
 	ppvar_sys: ppvar-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "ppvar_sys";
@@ -239,6 +225,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qup_i2c1_data_clk {
 	drive-strength = <2>;
 	bias-pull-up;
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
index 3fc62e12368..175f8b1e3b2 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
@@ -104,6 +104,30 @@
 			};
 		};
 	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		label = "eDP0";
+		type = "full-size";
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp0_out>;
+			};
+		};
+	};
+
+	dp1-connector {
+		compatible = "dp-connector";
+		label = "eDP1";
+		type = "full-size";
+
+		port {
+			dp1_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp1_out>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -498,6 +522,50 @@
 	status = "okay";
 };
 
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	pinctrl-0 = <&dp0_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+	remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss0_dp0_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&mdss0_dp1 {
+	pinctrl-0 = <&dp1_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+	remote-endpoint = <&dp1_connector_in>;
+};
+
+&mdss0_dp1_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
 &pmm8654au_0_gpios {
 	gpio-line-names = "DS_EN",
 			  "POFF_COMPLETE",
@@ -608,7 +676,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32764>;
+	clock-frequency = <32000>;
 };
 
 &spi16 {
@@ -618,6 +686,18 @@
 };
 
 &tlmm {
+	dp0_hot_plug_det: dp0-hot-plug-det-state {
+		pins = "gpio101";
+		function = "edp0_hot";
+		bias-disable;
+	};
+
+	dp1_hot_plug_det: dp1-hot-plug-det-state {
+		pins = "gpio102";
+		function = "edp1_hot";
+		bias-disable;
+	};
+
 	ethernet0_default: ethernet0-default-state {
 		ethernet0_mdc: ethernet0-mdc-pins {
 			pins = "gpio8";
diff --git a/dts/upstream/src/arm64/qcom/sa8775p.dtsi b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
index 9da62d7c4d2..3394ae2d130 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -44,6 +45,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <1024>;
@@ -66,6 +69,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -83,6 +88,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x200>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_2>;
 			capacity-dmips-mhz = <1024>;
@@ -100,6 +107,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x300>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_3>;
 			capacity-dmips-mhz = <1024>;
@@ -117,6 +126,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10000>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_4>;
 			capacity-dmips-mhz = <1024>;
@@ -140,6 +151,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10100>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_5>;
 			capacity-dmips-mhz = <1024>;
@@ -157,6 +170,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10200>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_6>;
 			capacity-dmips-mhz = <1024>;
@@ -174,6 +189,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10300>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_7>;
 			capacity-dmips-mhz = <1024>;
@@ -854,8 +871,8 @@
 			#mbox-cells = <2>;
 		};
 
-		gpi_dma2: qcom,gpi-dma@800000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma2: dma-controller@800000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00800000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
@@ -1345,8 +1362,8 @@
 
 		};
 
-		gpi_dma0: qcom,gpi-dma@900000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma0: dma-controller@900000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00900000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
@@ -1770,8 +1787,8 @@
 			};
 		};
 
-		gpi_dma1: qcom,gpi-dma@a00000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma1: dma-controller@a00000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00a00000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@@ -2225,8 +2242,8 @@
 			};
 		};
 
-		gpi_dma3: qcom,gpi-dma@b00000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma3: dma-controller@b00000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00b00000 0x0 0x58000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
@@ -3412,6 +3429,8 @@
 				iommus = <&apps_smmu 0x080 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3501,6 +3520,8 @@
 				iommus = <&apps_smmu 0x0a0 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3564,6 +3585,8 @@
 				iommus = <&apps_smmu 0x020 0x0>;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3760,6 +3783,353 @@
 			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		videocc: clock-controller@abf0000 {
+			compatible = "qcom,sa8775p-videocc";
+			reg = <0x0 0x0abf0000 0x0 0x10000>;
+			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ade0000 {
+			compatible = "qcom,sa8775p-camcc";
+			reg = <0x0 0x0ade0000 0x0 0x20000>;
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		mdss0: display-subsystem@ae00000 {
+			compatible = "qcom,sa8775p-mdss";
+			reg = <0x0 0x0ae00000 0x0 0x1000>;
+			reg-names = "mdss";
+
+			/* same path used twice */
+			interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "mdp0-mem",
+					     "mdp1-mem",
+					     "cpu-cfg";
+
+			resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+			power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+			clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+				 <&gcc GCC_DISP_HF_AXI_CLK>,
+				 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			iommus = <&apps_smmu 0x1000 0x402>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			mdss0_mdp: display-controller@ae01000 {
+				compatible = "qcom,sa8775p-dpu";
+				reg = <0x0 0x0ae01000 0x0 0x8f000>,
+				      <0x0 0x0aeb0000 0x0 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "bus",
+					      "iface",
+					      "lut",
+					      "core",
+					      "vsync";
+
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&mdss0_mdp_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&mdss0_dp0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						dpu_intf4_out: endpoint {
+							remote-endpoint = <&mdss0_dp1_in>;
+						};
+					};
+				};
+
+				mdss0_mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-375000000 {
+						opp-hz = /bits/ 64 <375000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-500000000 {
+						opp-hz = /bits/ 64 <500000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+
+					opp-575000000 {
+						opp-hz = /bits/ 64 <575000000>;
+						required-opps = <&rpmhpd_opp_turbo>;
+					};
+
+					opp-650000000 {
+						opp-hz = /bits/ 64 <650000000>;
+						required-opps = <&rpmhpd_opp_turbo_l1>;
+					};
+				};
+			};
+
+			mdss0_dp0_phy: phy@aec2a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0x0 0x0aec2a00 0x0 0x200>,
+				      <0x0 0x0aec2200 0x0 0xd0>,
+				      <0x0 0x0aec2600 0x0 0xd0>,
+				      <0x0 0x0aec2000 0x0 0x1c8>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp1_phy: phy@aec5a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0x0 0x0aec5a00 0x0 0x200>,
+				      <0x0 0x0aec5200 0x0 0xd0>,
+				      <0x0 0x0aec5600 0x0 0xd0>,
+				      <0x0 0x0aec5000 0x0 0x1c8>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp0: displayport-controller@af54000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0x0 0x0af54000 0x0 0x104>,
+				      <0x0 0x0af54200 0x0 0x0c0>,
+				      <0x0 0x0af55000 0x0 0x770>,
+				      <0x0 0x0af56000 0x0 0x09c>,
+				      <0x0 0x0af57000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <12>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+				phys = <&mdss0_dp0_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp0_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp0_out: endpoint { };
+					};
+				};
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss0_dp1: displayport-controller@af5c000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0x0 0x0af5c000 0x0 0x104>,
+				      <0x0 0x0af5c200 0x0 0x0c0>,
+				      <0x0 0x0af5d000 0x0 0x770>,
+				      <0x0 0x0af5e000 0x0 0x09c>,
+				      <0x0 0x0af5f000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <13>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+				phys = <&mdss0_dp1_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp1_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp1_in: endpoint {
+							remote-endpoint = <&dpu_intf4_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp1_out: endpoint { };
+					};
+				};
+
+				dp1_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+		};
+
+		dispcc0: clock-controller@af00000 {
+			compatible = "qcom,sa8775p-dispcc0";
+			reg = <0x0 0x0af00000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
+				 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -4382,6 +4752,22 @@
 			};
 		};
 
+		dispcc1: clock-controller@22100000 {
+			compatible = "qcom,sa8775p-dispcc1";
+			reg = <0x0 0x22100000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			status = "disabled";
+		};
+
 		ethernet1: ethernet@23000000 {
 			compatible = "qcom,sa8775p-ethqos";
 			reg = <0x0 0x23000000 0x0 0x10000>,
diff --git a/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts b/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts
new file mode 100644
index 00000000000..74778a5b19b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sar2130p.dtsi"
+#include "pm8150.dtsi"
+
+/ {
+	model = "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit";
+	compatible = "qcom,qar2130p", "qcom,sar2130p";
+	chassis-type = "embedded";
+
+	aliases {
+		serial0 = &uart11;
+		serial1 = &uart7;
+		i2c0 = &i2c8;
+		i2c1 = &i2c10;
+		mmc1 = &sdhc_1;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		regulator-always-on;
+	};
+
+	/* pm3003a on I2C0, should not be controlled */
+	vreg_ext_1p3: regulator-ext-1p3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_ext_1p3";
+		regulator-min-microvolt = <1300000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		vin-supply = <&vph_pwr>;
+	};
+
+	/* EBI rail, used as LDO input, can not be part of PMIC config */
+	vreg_s10a_0p89: regulator-s10a-0p89 {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_s10a_0p89";
+		regulator-min-microvolt = <890000>;
+		regulator-max-microvolt = <890000>;
+		regulator-always-on;
+		vin-supply = <&vph_pwr>;
+	};
+
+	thermal-zones {
+		sar2130p-thermal {
+			thermal-sensors = <&pm8150_adc_tm 1>;
+
+			trips {
+				active-config0 {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		wifi-thermal {
+			thermal-sensors = <&pm8150_adc_tm 2>;
+
+			trips {
+				active-config0 {
+					temperature = <52000>;
+					hysteresis = <4000>;
+					type = "passive";
+				};
+			};
+		};
+
+		xo-thermal {
+			thermal-sensors = <&pm8150_adc_tm 0>;
+
+			trips {
+				active-config0 {
+					temperature = <50000>;
+					hysteresis = <4000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		pinctrl-0 = <&wlan_en_state>, <&bt_en_state>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&vreg_s4a_0p95>;
+		vddio-supply = <&vreg_l15a_1p8>;
+		vddaon-supply = <&vreg_s4a_0p95>;
+		vdddig-supply = <&vreg_s4a_0p95>;
+		vddrfa1p2-supply = <&vreg_s4a_0p95>;
+		vddrfa1p8-supply = <&vreg_s5a_1p88>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-s9-supply = <&vph_pwr>;
+		vdd-s10-supply = <&vph_pwr>;
+		vdd-l1-l8-l11-supply = <&vreg_s4a_0p95>;
+		vdd-l3-l4-l5-l18-supply = <&vreg_ext_1p3>;
+		vdd-l6-l9-supply = <&vreg_s10a_0p89>;
+		vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p88>;
+
+		vreg_s4a_0p95: smps6 {
+			regulator-name = "vreg_s4a_0p95";
+			regulator-min-microvolt = <950000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a_1p88: smps5 {
+			regulator-name = "vreg_s5a_1p88";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2040000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1a_0p91: ldo1 {
+			regulator-name = "vreg_l1a_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2a_3p1: ldo2 {
+			regulator-name = "vreg_l2a_3p1";
+			regulator-min-microvolt = <3080000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a_1p2: ldo3 {
+			regulator-name = "vreg_l3a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo4 1.26 - system ? */
+
+		vreg_l5a_1p13: ldo5 {
+			regulator-name = "vreg_l5a_1p13";
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a_0p6: ldo6 {
+			regulator-name = "vreg_l6a_0p6";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <650000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a_1p8: ldo7 {
+			regulator-name = "vreg_l7a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a_0p88: ldo8 {
+			regulator-name = "vreg_l8a_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo9 - LCX */
+
+		vreg_l10a_2p95: ldo10 {
+			regulator-name = "vreg_l10a_2p95";
+			regulator-min-microvolt = <2952000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo11 - LMX */
+
+		vreg_l12a_1p8: ldo12 {
+			regulator-name = "vreg_l12a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* no ldo13 */
+
+		vreg_l14a_1p8: ldo14 {
+			regulator-name = "vreg_l14a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15a_1p8: ldo15 {
+			regulator-name = "vreg_l15a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* no ldo16 - system */
+
+		vreg_l17a_3p26: ldo17 {
+			regulator-name = "vreg_l17a_3p26";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l18a_1p2: ldo18 {
+			regulator-name = "vreg_l18a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/sar2130p/a620_zap.mbn";
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	ptn3222: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+
+		reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+		vdd3v3-supply = <&vreg_l2a_3p1>;
+		vdd1v8-supply = <&vreg_l15a_1p8>;
+
+		#phy-cells = <0>;
+	};
+};
+
+&i2c10 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&pcie0 {
+	perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcieport0 {
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l8a_0p88>;
+	vdda-pll-supply = <&vreg_l3a_1p2>;
+
+	status = "okay";
+};
+
+&pm8150_adc {
+	channel@4c {
+		reg = <ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		label = "xo_therm";
+	};
+
+	channel@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "skin_therm";
+	};
+
+	channel@4e {
+		/* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "wifi_therm";
+	};
+};
+
+&pm8150_adc_tm {
+	status = "okay";
+
+	xo-therm@0 {
+		reg = <0>;
+		io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	skin-therm@1 {
+		reg = <1>;
+		io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	wifi-therm@2 {
+		reg = <2>;
+		/* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */
+		io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
+		qcom,hw-settle-time-us = <200>;
+	};
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sar2130p/adsp.mbn";
+
+	status = "okay";
+};
+
+&sdhc_1 {
+	vmmc-supply = <&vreg_l10a_2p95>;
+	vqmmc-supply = <&vreg_l7a_1p8>;
+
+	status = "okay";
+};
+
+&tlmm {
+	bt_en_state: bt-enable-state {
+		pins = "gpio46";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	pcie0_default_state: pcie0-default-state {
+		perst-pins {
+			pins = "gpio55";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+
+		clkreq-pins {
+			pins = "gpio56";
+			function = "pcie0_clkreqn";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-pins {
+			pins = "gpio57";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie1_default_state: pcie1-default-state {
+		perst-pins {
+			pins = "gpio58";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+
+		clkreq-pins {
+			pins = "gpio59";
+			function = "pcie1_clkreqn";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-pins {
+			pins = "gpio60";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	wlan_en_state: wlan-enable-state {
+		pins = "gpio45";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+};
+
+&uart7 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&uart11 {
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l8a_0p88>;
+	vdda12-supply = <&vreg_l3a_1p2>;
+
+	phys = <&ptn3222>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3a_1p2>;
+	vdda-pll-supply = <&vreg_l1a_0p91>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sar2130p.dtsi b/dts/upstream/src/arm64/qcom/sar2130p.dtsi
new file mode 100644
index 00000000000..dd832e6816b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sar2130p.dtsi
@@ -0,0 +1,3123 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sar2130p-gcc.h>
+#include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
+#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+
+				l3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_100>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_200>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_300>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <549>;
+				exit-latency-us = <901>;
+				min-residency-us = <1774>;
+				local-timer-stop;
+			};
+
+			cpu_sleep_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <702>;
+				exit-latency-us = <915>;
+				min-residency-us = <4001>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			cluster_sleep_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2752>;
+				exit-latency-us = <3048>;
+				min-residency-us = <6118>;
+			};
+
+			cluster_sleep_1: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41002344>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <4562>;
+				min-residency-us = <8467>;
+			};
+
+			cluster_sleep_2: cluster-sleep-2 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x4100c344>;
+				entry-latency-us = <3638>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9862>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sar2130p", "qcom,scm";
+			qcom,dload-mode = <&tcsr_mutex 0x13000>;
+			interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sar2130p-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sar2130p-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cluster_pd: power-domain-cpu-cluster0 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>;
+		};
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_dt_log_mem: xbl-dt-log@80600000 {
+			reg = <0x0 0x80600000 0x0 0x40000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: xbl-ramdump@80640000 {
+			reg = <0x0 0x80640000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@80800000 {
+			reg = <0x0 0x80800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@80860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x80860000 0x0 0x20000>;
+			no-map;
+		};
+
+		aop_config_mem: aop-config@80880000 {
+			reg = <0x0 0x80880000 0x0 0x20000>;
+			no-map;
+		};
+
+		tme_crash_dump_mem: tme-crash-dump@808a0000 {
+			reg = <0x0 0x808a0000 0x0 0x40000>;
+			no-map;
+		};
+
+		tme_log_mem: tme-log@808e0000 {
+			reg = <0x0 0x808e0000 0x0 0x4000>;
+			no-map;
+		};
+
+		uefi_log_mem: uefi-log@808e4000 {
+			reg = <0x0 0x808e4000 0x0 0x10000>;
+			no-map;
+		};
+
+		secdata_apss_mem: secdata-apss@808ff000 {
+			reg = <0x0 0x808ff000 0x0 0x1000>;
+			no-map;
+		};
+
+		smem: smem@80900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x80900000 0x0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw@80b00000 {
+			reg = <0x0 0x80b00000 0x0 0x100000>;
+			no-map;
+		};
+
+		helios_ram_dump_mem: helios-ram-dump@80c00000 {
+			reg = <0x0 0x80c00000 0x0 0xe00000>;
+			no-map;
+		};
+
+		camera_mem: camera@84e00000 {
+			reg = <0x0 0x84e00000 0x0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video@86f00000 {
+			reg = <0x0 0x86f00000 0x0 0x500000>;
+			no-map;
+		};
+
+		adsp_mem: adsp@87600000 {
+			reg = <0x0 0x87600000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@89400000 {
+			reg = <0x0 0x89400000 0x0 0xf00000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@8a300000 {
+			reg = <0x0 0x8a300000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@8a3a0000 {
+			reg = <0x0 0x8a310000 0x0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code@8a31a000 {
+			reg = <0x0 0x8a31a000 0x0 0x2000>;
+			no-map;
+		};
+
+		cvp_mem: cvp@8a400000 {
+			reg = <0x0 0x8a400000 0x0 0x700000>;
+			no-map;
+		};
+
+		xbl_sc_mem: xbl-sc@a6e00000 {
+			no-map;
+			reg = <0x0 0xa6e00000 0x0 0x40000>;
+		};
+
+		global_sync_mem: global-sync@a6f00000 {
+			no-map;
+			reg = <0x0 0xa6f00000 0x0 0x100000>;
+		};
+
+		tz_stat_mem: tz-stat@e8800000 {
+			no-map;
+			reg = <0x0 0xe8800000 0x0 0x100000>;
+		};
+
+		tags_mem: tags@e8900000 {
+			no-map;
+			reg = <0x0 0xe8900000 0x0 0x500000>;
+		};
+
+		qtee_mem: qtee@e8e00000 {
+			no-map;
+			reg = <0x0 0xe8e00000 0x0 0x500000>;
+		};
+
+		trusted_apps_mem: trusted-apps@e9300000 {
+			no-map;
+			reg = <0x0 0xe9300000 0x0 0xc00000>;
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		smp2p_cdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_cdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sar2130p-gcc";
+			reg = <0x0 0x00100000 0x0 0x1f4200>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+		};
+
+		sdhc_1: mmc@7c4000 {
+			compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x007c4000 0x0 0x1000>,
+			      <0x0 0x007c5000 0x0 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			iommus = <&apps_smmu 0x160 0x0>;
+			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "sdhc-ddr","cpu-sdhc";
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc1_opp_table>;
+
+			pinctrl-0 = <&sdc1_default>;
+			pinctrl-1 = <&sdc1_sleep>;
+			pinctrl-names = "default", "sleep";
+
+			bus-width = <8>;
+			non-removable;
+			supports-cqe;
+
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-hs400-enhanced-strobe;
+
+			status = "disabled";
+
+			sdhc1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 200000>;
+					opp-avg-kBps = <104000 0>;
+				};
+
+				opp-384000000 {
+					opp-hz = /bits/ 64 <384000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <2500000 1000000>;
+					opp-avg-kBps = <400000 0>;
+				};
+			};
+		};
+
+		gpi_dma0: dma-controller@900000 {
+			compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00900000 0x0 0x60000>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <3>;
+			dma-channels = <12>;
+			dma-channel-mask = <0x7e>;
+			iommus = <&apps_smmu 0x76 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x63 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c0: i2c@980000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi0: spi@980000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c1: i2c@984000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi1: spi@984000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c2: i2c@988000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi2: spi@988000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+
+			i2c3: i2c@98c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi3: spi@98c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c4: i2c@990000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi4: spi@990000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c5: i2c@994000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi5: spi@994000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
+			#dma-cells = <3>;
+			reg = <0x0 0x00a00000 0x0 0x60000>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <12>;
+			dma-channel-mask = <0x7e>;
+			iommus = <&apps_smmu 0x16 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x3 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c6: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi6: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c7: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi7: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart7: serial@a84000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+
+				status = "disabled";
+			};
+
+			i2c8: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi8: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c9: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi9: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c10: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi10: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c11: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi11: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart11: serial@a94000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-0 = <&qup_uart11_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				status = "disabled";
+			};
+		};
+
+		config_noc: interconnect@1500000 {
+			compatible = "qcom,sar2130p-config-noc";
+			reg = <0x0 0x01500000 0x0 0x10>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sar2130p-system-noc";
+			reg = <0x0 0x01680000 0x0 0x29080>;
+			clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_noc: interconnect@16c0000 {
+			compatible = "qcom,sar2130p-pcie-anoc";
+			reg = <0x0 0x016c0000 0x0 0xa080>;
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sar2130p-mmss-noc";
+			reg = <0x0 0x01740000 0x0 0x1f100>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie0: pcie@1c00000 {
+			device_type = "pci";
+			compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
+			reg = <0x0 0x01c00000 0x0 0x3000>,
+			      <0x0 0x60000000 0x0 0xf1d>,
+			      <0x0 0x60000f20 0x0 0xa8>,
+			      <0x0 0x60001000 0x0 0x1000>,
+			      <0x0 0x60100000 0x0 0x100000>,
+			      <0x0 0x01c0c000 0x0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <0>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr";
+
+			interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+				    <0x100 &apps_smmu 0x1c01 0x1>;
+
+			resets = <&gcc GCC_PCIE_0_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+
+			pcieport0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie0_phy: phy@1c06000 {
+			compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
+			reg = <0x0 0x01c06000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_0_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie0_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		pcie1: pcie@1c08000 {
+			device_type = "pci";
+			compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
+			reg = <0x0 0x01c08000 0x0 0x3000>,
+			      <0x0 0x40000000 0x0 0xf1d>,
+			      <0x0 0x40000f20 0x0 0xa8>,
+			      <0x0 0x40001000 0x0 0x1000>,
+			      <0x0 0x40100000 0x0 0x100000>,
+			      <0x0 0x01c0b000 0x0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
+				 <&gcc GCC_QMIP_PCIE_AHB_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr",
+				      "cnoc_sf_axi",
+				      "qmip_pcie_ahb";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
+				    <0x100 &apps_smmu 0x1e01 0x1>;
+
+			resets = <&gcc GCC_PCIE_1_BCR>,
+				<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+			reset-names = "pci", "link_down";
+
+			power-domains = <&gcc PCIE_1_GDSC>;
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie1_phy: phy@1c0e000 {
+			compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
+			reg = <0x0 0x01c0e000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
+				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_1_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_1_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie1_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: clock-controller@1fc0000 {
+			compatible = "qcom,sar2130p-tcsr", "syscon";
+			reg = <0x0 0x01fc0000 0x0 0x30000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,sar2130p-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1801 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1806 0x0>;
+					};
+				};
+			};
+		};
+
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-621.0", "qcom,adreno";
+			reg = <0x0 0x03d00000 0x0 0x40000>,
+			      <0x0 0x03d9e000 0x0 0x2000>,
+			      <0x0 0x03d61000 0x0 0x800>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem",
+				    "cx_dbgc";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0 0x401>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+			#cooling-cells = <2>;
+
+			status = "disabled";
+
+			gpu_zap_shader: zap-shader {
+				memory-region = <&gpu_micro_code_mem>;
+			};
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-843000000 {
+					opp-hz = /bits/ 64 <843000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-supported-hw = <0x1>;
+				};
+
+				opp-780000000 {
+					opp-hz = /bits/ 64 <780000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-supported-hw = <0x1>;
+				};
+
+				opp-644000000 {
+					opp-hz = /bits/ 64 <644000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-570000000 {
+					opp-hz = /bits/ 64 <570000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-450000000 {
+					opp-hz = /bits/ 64 <450000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-320000000 {
+					opp-hz = /bits/ 64 <320000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-235000000 {
+					opp-hz = /bits/ 64 <235000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-supported-hw = <0x3>;
+				};
+			};
+		};
+
+		gmu: gmu@3d6a000 {
+			compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
+			reg = <0x0 0x03d6a000 0x0 0x35000>,
+			      <0x0 0x03de0000 0x0 0x10000>,
+			      <0x0 0x0b290000 0x0 0x10000>;
+			reg-names = "gmu", "rscc", "gmu_pdc";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "axi",
+				      "memnoc",
+				      "hub";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5 0x400>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-220000000 {
+					opp-hz = /bits/ 64 <220000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+
+				opp-550000000 {
+					opp-hz = /bits/ 64 <550000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+			};
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,sar2130p-gpucc";
+			reg = <0x0 0x03d90000 0x0 0xa000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x10000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>;
+			clock-names = "hlos",
+				      "bus",
+				      "iface",
+				      "ahb";
+			power-domains = <&gpucc GPU_CX_GDSC>;
+			dma-coherent;
+		};
+
+		usb_1_hsphy: phy@88e3000 {
+			compatible = "qcom,sar2130p-snps-eusb2-phy",
+				     "qcom,sm8550-snps-eusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x154>;
+			#phy-cells = <0>;
+
+			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			status = "disabled";
+		};
+
+		usb_dp_qmpphy: phy@88e8000 {
+			compatible = "qcom,sar2130p-qmp-usb3-dp-phy";
+			reg = <0x0 0x088e8000 0x0 0x3000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+			power-domains = <&gcc USB3_PHY_GDSC>;
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+
+			orientation-switch;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dp_qmpphy_out: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dp_qmpphy_usb_ss_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_dp_qmpphy_dp_in: endpoint {
+					};
+				};
+			};
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&tcsr TCSR_USB3_CLKREF_EN>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xcd00>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x20 0x0>;
+				phys = <&usb_1_hsphy>,
+				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+				phy-names = "usb2-phy", "usb3-phy";
+
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,is-utmi-l1-suspend;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,parkmode-disable-ss-quirk;
+
+				tx-fifo-resize;
+				dma-coherent;
+				usb-role-switch;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						usb_1_dwc3_hs: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						usb_1_dwc3_ss: endpoint {
+							remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+						};
+					};
+				};
+			};
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sar2130p-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 94>,
+					  <94 609 31>,
+					  <125 63 1>,
+					  <126 716 12>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupt-parent = <&ipcc>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+						     IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			#clock-cells = <0>;
+		};
+
+		tsens0: thermal-sensor@c263000 {
+			compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */
+			      <0x0 0x0c222000 0x0 0x1000>; /* SROT */
+			#qcom,sensors = <16>;
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		sram@c3f0000 {
+			compatible = "qcom,rpmh-stats";
+			reg = <0x0 0x0c3f0000 0x0 0x400>;
+		};
+
+		arbiter@c400000 {
+			compatible = "qcom,sar2130p-spmi-pmic-arb",
+				     "qcom,x1e80100-spmi-pmic-arb";
+			reg = <0x0 0x0c400000 0x0 0x3000>,
+			      <0x0 0x0c500000 0x0 0x400000>,
+			      <0x0 0x0c440000 0x0 0x80000>;
+			reg-names = "core", "chnls", "obsrvr";
+
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			spmi_bus: spmi@c42d000 {
+				reg = <0x0 0x0c42d000 0x0 0x4000>,
+				      <0x0 0x0c4c0000 0x0 0x10000>;
+				reg-names = "cnfg", "intr";
+
+				interrupt-names = "periph_irq";
+				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <4>;
+
+				#address-cells = <2>;
+				#size-cells = <0>;
+			};
+		};
+
+		ipcc: mailbox@ed18000 {
+			compatible = "qcom,sar2130p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x0ed18000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			#mbox-cells = <2>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sar2130p-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 156>;
+			wakeup-parent = <&pdc>;
+
+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio2", "gpio3";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio22", "gpio23";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio16", "gpio17";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio20", "gpio21";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio95", "gpio96";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio91", "gpio92";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio109", "gpio110";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio4", "gpio5";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio28", "gpio30";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_cs0: qup-spi0-cs0-state {
+				pins = "gpio3";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi0_cs1: qup-spi0-cs1-state {
+				pins = "gpio93";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi1_cs: qup-spi1-cs-state {
+				pins = "gpio62";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio2", "gpio3", "gpio61";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio13";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio22", "gpio23", "gpio12";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_cs0: qup-spi3-cs0-state {
+				pins = "gpio19";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_cs1: qup-spi3-cs1-state {
+				pins = "gpio41";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_cs0: qup-spi4-cs0-state {
+				pins = "gpio23";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_cs1: qup-spi4-cs1-state {
+				pins = "gpio94";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi5_cs: qup-spi5-cs-state {
+				pins = "gpio98";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio95", "gpio96", "gpio97";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio63";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio91", "gpio92", "gpio64";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi7_cs: qup-spi7-cs-state {
+				pins = "gpio27";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio24", "gpio25", "gpio26";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi8_cs: qup-spi8-cs-state {
+				pins = "gpio11";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi8_data_clk: qup-spi8-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi9_cs: qup-spi9-cs-state {
+				pins = "gpio35";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio109", "gpio110", "gpio34";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi10_cs: qup-spi10-cs-state {
+				pins = "gpio7";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi11_cs: qup-spi11-cs-state {
+				pins = "gpio15";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio28", "gpio30", "gpio14";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				cts-pins {
+					pins = "gpio24";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				rts-pins {
+					pins = "gpio25";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				rx-pins {
+					pins = "gpio27";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				tx-pins {
+					pins = "gpio26";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qup_uart11_default: qup-uart11-default-state {
+				pins = "gpio14", "gpio15";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			sdc1_default: sdc1-default-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_sleep: sdc1-sleep-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+		};
+
+		intc: interrupt-controller@17200000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			reg = <0x0 0x17200000 0x0 0x10000>,
+			      <0x0 0x17260000 0x0 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@17240000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x17240000 0x0 0x20000>;
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		apps_rsc: rsc@17a00000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a10000 0x0 0x10000>,
+			      <0x0 0x17a20000 0x0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
+					  <WAKE_TCS    2>, <CONTROL_TCS 0>;
+			power-domains = <&cluster_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sar2130p-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,sar2130p-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_d1: opp3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					};
+
+					rpmhpd_opp_low_svs: opp4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_turbo: opp8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0x0 0x17d91000 0x0 0x1000>;
+			reg-names = "freq-domain0";
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0";
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
+		gem_noc: interconnect@19100000 {
+			compatible = "qcom,sar2130p-gem-noc";
+			reg = <0x0 0x19100000 0x0 0xa2080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		/*
+		 * Bootloader expects just cache-controller node instead of
+		 * the typical system-cache-controller
+		 */
+		llcc: cache-controller@19200000 {
+			compatible = "qcom,sar2130p-llcc";
+			reg = <0x0 0x19200000 0x0 0x80000>,
+			      <0x0 0x19300000 0x0 0x80000>,
+			      <0x0 0x19a00000 0x0 0x80000>,
+			      <0x0 0x19c00000 0x0 0x80000>,
+			      <0x0 0x19af0000 0x0 0x80000>,
+			      <0x0 0x19cf0000 0x0 0x80000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc_broadcast_base",
+				    "llcc_broadcast_and_base",
+				    "llcc_scratchpad_broadcast_base",
+				    "llcc_scratchpad_broadcast_and_base";
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		qfprom: qfprom@221c8000 {
+			compatible = "qcom,sar2130p-qfprom", "qcom,qfprom";
+			reg = <0x0 0x221c8000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			read-only;
+
+			gpu_speed_bin: gpu-speed-bin@119 {
+				reg = <0x119 0x2>;
+				bits = <5 8>;
+			};
+		};
+
+		nsp_noc: interconnect@320c0000 {
+			compatible = "qcom,sar2130p-nsp-noc";
+			reg = <0x0 0x320c0000 0x0 0x10>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		lpass_ag_noc: interconnect@3c40000 {
+			compatible = "qcom,sar2130p-lpass-ag-noc";
+			reg = <0x0 0x3c40000 0x0 0x10>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	thermal-zones {
+		aoss0-thermal {
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				aoss0-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+			};
+		};
+
+		cpu0-thermal {
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu0_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu0-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu1-thermal {
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu1_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu1-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu2-thermal {
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu2_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu3-thermal {
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu3_alert1: rip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu3-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpuss0-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu0_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu0_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				trip-point2 {
+					temperature = <115000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens0 6>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu1_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu1_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				trip-point2 {
+					temperature = <115000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss0-thermal {
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss1-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss1-thermal {
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss2-thermal {
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		video-thermal {
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				video-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		ddr-thermal {
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				ddr-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera0-thermal {
+			thermal-sensors = <&tsens0 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				camera0-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera1-thermal {
+			thermal-sensors = <&tsens0 13>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				camera1-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		mdmss-thermal {
+			thermal-sensors = <&tsens0 14>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				mdmss-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index ac8d4589e3f..f7300ffbb45 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -12,11 +12,11 @@
 
 / {
 	thermal-zones {
-		5v-choke-thermal {
+		choke-5v-thermal {
 			thermal-sensors = <&pm6150_adc_tm 1>;
 
 			trips {
-				5v-choke-crit {
+				choke-5v-crit {
 					temperature = <125000>;
 					hysteresis = <1000>;
 					type = "critical";
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
index 00229b1515e..ff8996b4de4 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
@@ -78,6 +78,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_rst>;
 		avdd-supply = <&ppvar_lcd>;
+		avee-supply = <&ppvar_lcd>;
 		pp1800-supply = <&v1p8_disp>;
 		pp3300-supply = <&pp3300_dx_edp>;
 		backlight = <&backlight>;
diff --git a/dts/upstream/src/arm64/qcom/sc7180.dtsi b/dts/upstream/src/arm64/qcom/sc7180.dtsi
index 76fe314d2ad..87c432c12a2 100644
--- a/dts/upstream/src/arm64/qcom/sc7180.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180.dtsi
@@ -580,55 +580,55 @@
 		compatible = "arm,psci-1.0";
 		method = "smc";
 
-		cpu_pd0: cpu0 {
+		cpu_pd0: power-domain-cpu0 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd1: cpu1 {
+		cpu_pd1: power-domain-cpu1 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd2: cpu2 {
+		cpu_pd2: power-domain-cpu2 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd3: cpu3 {
+		cpu_pd3: power-domain-cpu3 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd4: cpu4 {
+		cpu_pd4: power-domain-cpu4 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd5: cpu5 {
+		cpu_pd5: power-domain-cpu5 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd6: cpu6 {
+		cpu_pd6: power-domain-cpu6 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
 		};
 
-		cpu_pd7: cpu7 {
+		cpu_pd7: power-domain-cpu7 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
 		};
 
-		cluster_pd: cpu-cluster0 {
+		cluster_pd: power-domain-cluster {
 			#power-domain-cells = <0>;
 			domain-idle-states = <&cluster_sleep_pc
 					      &cluster_sleep_cx_ret
@@ -3064,6 +3064,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
diff --git a/dts/upstream/src/arm64/qcom/sc7280.dtsi b/dts/upstream/src/arm64/qcom/sc7280.dtsi
index 55db1c83ef5..0f2caf36910 100644
--- a/dts/upstream/src/arm64/qcom/sc7280.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280.dtsi
@@ -83,7 +83,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -3715,6 +3715,8 @@
 				iommus = <&apps_smmu 0xa0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
@@ -4244,6 +4246,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
index 62de4774c55..21c2d25a294 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
@@ -681,10 +681,6 @@
 	status = "okay";
 };
 
-&xo_board_clk {
-	clock-frequency = <38400000>;
-};
-
 /* PINCTRL */
 
 &pmc8180c_gpios {
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
index 79b4d293ea1..7a4bd695547 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
@@ -773,10 +773,6 @@
 	status = "okay";
 };
 
-&xo_board_clk {
-	clock-frequency = <38400000>;
-};
-
 /* PINCTRL */
 
 &pmc8180c_gpios {
diff --git a/dts/upstream/src/arm64/qcom/sc8180x.dtsi b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
index 745a7d0b838..28693a3bfc7 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
@@ -2762,6 +2762,8 @@
 				iommus = <&apps_smmu 0x60 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_mp_hsphy0>,
 				       <&usb_mp_qmpphy0>,
 				       <&usb_mp_hsphy1>,
@@ -2825,6 +2827,8 @@
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2902,6 +2906,8 @@
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts
new file mode 100644
index 00000000000..09b95f89ee5
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts
@@ -0,0 +1,1318 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ *
+ * Copyright (c) 2024, Tianyu Gao <gty0622@gmail.com>
+ * Copyright (c) 2024, Xuecong Chen <chenxuecong2009@outlook.com>
+ *
+ * Copyright (c) 2024, Pengyu Luo <mitltlatltl@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "sc8280xp.dtsi"
+#include "sc8280xp-pmics.dtsi"
+
+/ {
+	chassis-type = "tablet";
+	model = "Matebook E Go";
+	compatible = "huawei,gaokun3", "qcom,sc8280xp";
+
+	aliases {
+		i2c4 = &i2c4;
+		serial1 = &uart2;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@c6200000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0xc6200000 0x0 0x02400000>;
+			width = <1600>;
+			height = <2560>;
+			stride = <(1600 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9380-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_s10b>;
+		vdd-rxtx-supply = <&vreg_s10b>;
+		vdd-io-supply = <&vreg_s10b>;
+		vdd-mic-bias-supply = <&vreg_bob>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&mode_pin_active>, <&vol_up_n>;
+		pinctrl-names = "default";
+
+		key-vol-up {
+			label = "Volume Up";
+			gpios = <&pmc8280_1_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+
+		switch-mode {
+			label = "Tablet Mode Switch";
+			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_TABLET_MODE>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&misc_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3_SSD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VPH_VCC3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		regulator-always-on;
+	};
+
+	vreg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC_WLAN_3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&hastings_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		gpu_mem: gpu-mem@8bf00000 {
+			reg = <0 0x8bf00000 0 0x2000>;
+			no-map;
+		};
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	thermal-zones {
+		skin-temp-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&pmk8280_adc_tm 5>;
+
+			trips {
+				skin_temp_alert0: trip-point0 {
+					temperature = <55000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				skin_temp_alert1: trip-point1 {
+					temperature = <58000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				skin-temp-crit {
+					temperature = <73000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&skin_temp_alert0>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&skin_temp_alert1>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_default>, <&wlan_en>;
+
+		wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
+
+		vddio-supply = <&vreg_s10b>;
+		vddaon-supply = <&vreg_s12b>;
+		vddpmu-supply = <&vreg_s12b>;
+		vddpmumx-supply = <&vreg_s12b>;
+		vddpmucx-supply = <&vreg_s12b>;
+		vddrfa0p95-supply = <&vreg_s12b>;
+		vddrfa1p3-supply = <&vreg_s11b>;
+		vddrfa1p9-supply = <&vreg_s1c>;
+		vddpcie1p3-supply = <&vreg_s11b>;
+		vddpcie1p9-supply = <&vreg_s1c>;
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-l1-l4-supply = <&vreg_s12b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_s10b: smps10 {
+			regulator-name = "vreg_s10b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_s11b: smps11 {
+			regulator-name = "vreg_s11b";
+			regulator-min-microvolt = <1272000>;
+			regulator-max-microvolt = <1272000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s12b: smps12 {
+			regulator-name = "vreg_s12b";
+			regulator-min-microvolt = <984000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b: ldo1 {
+			regulator-name = "vreg_l1b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b: ldo2 {
+			regulator-name = "vreg_l2b";
+			regulator-min-microvolt = <1904000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3b: ldo3 {
+			regulator-name = "vreg_l3b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b: ldo4 {
+			regulator-name = "vreg_l4b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b: ldo5 {
+			regulator-name = "vreg_l5b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b: ldo6 {
+			regulator-name = "vreg_l6b";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b: ldo7 {
+			regulator-name = "vreg_l7b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+
+		vreg_l9b: ldo9 {
+			regulator-name = "vreg_l9b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8350c-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-bob-supply = <&vreg_vph_pwr>;
+		vdd-l1-l12-supply = <&vreg_s1c>;
+		vdd-l2-l8-supply = <&vreg_s1c>;
+		vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+		vdd-l6-l9-l11-supply = <&vreg_bob>;
+		vdd-l10-supply = <&vreg_s11b>;
+
+		vreg_s1c: smps1 {
+			regulator-name = "vreg_s1c";
+			regulator-min-microvolt = <1880000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12c: ldo12 {
+			regulator-name = "vreg_l12c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13c: ldo13 {
+			regulator-name = "vreg_l13c";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-name = "vreg_bob";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+			regulator-always-on;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-l4-supply = <&vreg_s11b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_l2d: ldo2 {
+			regulator-name = "vreg_l2d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d: ldo3 {
+			regulator-name = "vreg_l3d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4d: ldo4 {
+			regulator-name = "vreg_l4d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6d: ldo6 {
+			regulator-name = "vreg_l6d";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7d: ldo7 {
+			regulator-name = "vreg_l7d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8d: ldo8 {
+			regulator-name = "vreg_l8d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9d: ldo9 {
+			regulator-name = "vreg_l9d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10d: ldo10 {
+			regulator-name = "vreg_l10d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&dispcc0 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn";
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	pinctrl-0 = <&i2c4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	touchscreen@4f {
+		compatible = "hid-over-i2c";
+		reg = <0x4f>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_s10b>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+
+};
+
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_0_qmpphy_dp_in>;
+};
+
+&mdss0_dp1 {
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_1_qmpphy_dp_in>;
+};
+
+&pcie2a {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie2a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie2a_phy {
+	vdda-phy-supply = <&vreg_l6d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	max-link-speed = <2>;
+
+	perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wlan>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1103";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+	};
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l6d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&pmk8280_adc_tm {
+	status = "okay";
+
+	sys-therm@0 {
+		reg = <0>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@1 {
+		reg = <1>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@2 {
+		reg = <2>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@3 {
+		reg = <3>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@4 {
+		reg = <4>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@5 {
+		reg = <5>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@6 {
+		reg = <6>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@7 {
+		reg = <7>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+};
+
+&pmk8280_pon_pwrkey {
+	status = "okay";
+};
+
+&pmk8280_pon_resin {
+	status = "okay";
+	linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pmk8280_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+
+	status = "okay";
+};
+
+&pmk8280_sdam_6 {
+	status = "okay";
+
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};
+
+&pmk8280_vadc {
+	channel@144 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm1";
+	};
+
+	channel@145 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm2";
+	};
+
+	channel@146 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm3";
+	};
+
+	channel@147 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm4";
+	};
+
+	channel@344 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm5";
+	};
+
+	channel@345 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm6";
+	};
+
+	channel@346 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm7";
+	};
+
+	channel@347 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm8";
+	};
+};
+
+&qup0 {
+	status = "okay";
+};
+
+&qup1 {
+	status = "okay";
+};
+
+&qup2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcadsp8280.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_nsp0 {
+	firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qccdsp8280.mbn";
+
+	status = "okay";
+};
+
+&rxmacro {
+	status = "okay";
+};
+
+&sound {
+	compatible = "qcom,sc8280xp-sndcard";
+	model = "SC8280XP-HUAWEI-MATEBOOKEGO";
+	audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+			"SpkrRight IN", "WSA_SPK2 OUT",
+			"IN1_HPHL", "HPHL_OUT",
+			"IN2_HPHR", "HPHR_OUT",
+			"AMIC2", "MIC BIAS2",
+			"VA DMIC0", "MIC BIAS1",
+			"VA DMIC1", "MIC BIAS1",
+			"VA DMIC2", "MIC BIAS3",
+			"VA DMIC0", "VA MIC BIAS1",
+			"VA DMIC1", "VA MIC BIAS1",
+			"VA DMIC2", "VA MIC BIAS3",
+			"TX SWR_ADC1", "ADC2_OUTPUT";
+
+	wcd-playback-dai-link {
+		link-name = "WCD Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wcd-capture-dai-link {
+		link-name = "WCD Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wsa-dai-link {
+		link-name = "WSA Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	va-dai-link {
+		link-name = "VA Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+
+		codec {
+			sound-dai = <&vamacro 0>;
+		};
+	};
+};
+
+&swr0 {
+	status = "okay";
+
+	left_spkr: wsa8830-left@0,1 {
+		compatible = "sdw10217020200";
+		reg = <0 1>;
+		pinctrl-0 = <&spkr_1_sd_n_default>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
+		#thermal-sensor-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		#sound-dai-cells = <0>;
+		vdd-supply = <&vreg_s10b>;
+	};
+
+	right_spkr: wsa8830-right@0,2 {
+		compatible = "sdw10217020200";
+		reg = <0 2>;
+		pinctrl-0 = <&spkr_2_sd_n_default>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
+		#thermal-sensor-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		#sound-dai-cells = <0>;
+		vdd-supply = <&vreg_s10b>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_rx: wcd9380-rx@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: wcd9380-tx@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
+&txmacro {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_0_hsphy {
+	vdda-pll-supply = <&vreg_l9d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l9d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp0_out>;
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l4b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l13c>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l4b>;
+	vdda-pll-supply = <&vreg_l3b>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp1_out>;
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_hsphy0 {
+	vdda-pll-supply = <&vreg_l1b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy1 {
+	vdda-pll-supply = <&vreg_l8d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy2 {
+	vdda-pll-supply = <&vreg_l10d>;
+	vdda18-supply = <&vreg_l8c>;
+	vdda33-supply = <&vreg_l2d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy3 {
+	vdda-pll-supply = <&vreg_l10d>;
+	vdda18-supply = <&vreg_l8c>;
+	vdda33-supply = <&vreg_l2d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy0 {
+	vdda-phy-supply = <&vreg_l1b>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy1 {
+	vdda-phy-supply = <&vreg_l8d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_s10b>;
+
+	qcom,dmic-sample-rate = <4800000>;
+
+	status = "okay";
+};
+
+&wsamacro {
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
+
+/* PINCTRL */
+
+&lpass_tlmm {
+	status = "okay";
+};
+
+&pmc8280_1_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+
+	vol_up_n: vol-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		input-enable;
+		bias-pull-up;
+	};
+};
+
+&pmr735a_gpios {
+	hastings_reg_en: hastings-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&tlmm {
+
+	gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 4>;
+
+	bt_default: bt-default-state {
+		hstp-bt-en-pins {
+			pins = "gpio133";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		hstp-sw-ctrl-pins {
+			pins = "gpio132";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	i2c4_default: i2c4-default-state {
+		pins = "gpio171", "gpio172";
+		function = "qup4";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	mode_pin_active: mode-pin-state {
+		pins = "gpio26";
+		function = "gpio";
+		bias-disable;
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio135";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie2a_default: pcie2a-default-state {
+		clkreq-n-pins {
+			pins = "gpio142";
+			function = "pcie2a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+		       pins = "gpio145";
+		       function = "gpio";
+		       drive-strength = <2>;
+		       bias-pull-up;
+	       };
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio140";
+			function = "pcie4_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio141";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio139";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	spkr_1_sd_n_default: spkr-1-sd-n-default-state {
+		perst-n-pins {
+			pins = "gpio178";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	spkr_2_sd_n_default: spkr-2-sd-n-default-state {
+		perst-n-pins {
+			pins = "gpio179";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio175";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		reset-n-pins {
+			pins = "gpio99";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	uart2_default: uart2-default-state {
+		cts-pins {
+			pins = "gpio121";
+			function = "qup2";
+			bias-bus-hold;
+		};
+
+		rts-pins {
+			pins = "gpio122";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		rx-pins {
+			pins = "gpio124";
+			function = "qup2";
+			bias-pull-up;
+		};
+
+		tx-pins {
+			pins = "gpio123";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	wcd_default: wcd-default-state {
+		reset-pins {
+			pins = "gpio106";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio134";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts
new file mode 100644
index 00000000000..fa9d9410505
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts
@@ -0,0 +1,1325 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ * Copyright (c) 2023, Merck Hung <merckhung@gmail.com>
+ * Copyright (c) 2023, 2024 Jens Glathe <jens.glathe@oldschoolsolutions.biz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sc8280xp.dtsi"
+#include "sc8280xp-pmics.dtsi"
+
+/ {
+	model = "Windows Dev Kit 2023";
+	compatible = "microsoft,blackrock", "qcom,sc8280xp";
+	chassis-type = "desktop";
+
+	aliases {
+		i2c4 = &i2c4;
+		i2c21 = &i2c21;
+		serial1 = &uart2;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9380-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_s10b>;
+		vdd-rxtx-supply = <&vreg_s10b>;
+		vdd-io-supply = <&vreg_s10b>;
+		vdd-mic-bias-supply = <&vreg_bob>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	dp3_connector: connector {
+		compatible = "dp-connector";
+		label = "DP-3";
+		type = "mini";
+
+		dp-pwr-supply = <&vreg_misc_3p3>;
+
+		port {
+			dp1_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp2_phy_out>;
+			};
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 49 GPIO_ACTIVE_HIGH>;
+
+		/* Left-side rear port */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "source";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_con0_hs: endpoint {
+						remote-endpoint = <&usb_0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_con0_ss: endpoint {
+						remote-endpoint = <&usb_0_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_con0_sbu: endpoint {
+						remote-endpoint = <&usb0_sbu_mux>;
+					};
+				};
+			};
+		};
+
+		/* Left-side front port */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "source";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_con1_hs: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_con1_ss: endpoint {
+						remote-endpoint = <&usb_1_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_con1_sbu: endpoint {
+						remote-endpoint = <&usb1_sbu_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&misc_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3_SSD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VPH_VCC3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		regulator-always-on;
+	};
+
+	vreg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC_WLAN_3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&hastings_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_wwan: regulator-wwan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B_WAN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wwan_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		gpu_mem: gpu-mem@8bf00000 {
+			reg = <0 0x8bf00000 0 0x2000>;
+			no-map;
+		};
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	usb0-sbu-mux {
+		compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb0_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb0_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_con0_sbu>;
+			};
+		};
+	};
+
+	usb1-sbu-mux {
+		compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb1_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb1_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_con1_sbu>;
+			};
+		};
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		pinctrl-0 = <&bt_default>, <&wlan_en>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
+
+		vddio-supply = <&vreg_s10b>;
+		vddaon-supply = <&vreg_s12b>;
+		vddpmu-supply = <&vreg_s12b>;
+		vddpmumx-supply = <&vreg_s12b>;
+		vddpmucx-supply = <&vreg_s12b>;
+		vddrfa0p95-supply = <&vreg_s12b>;
+		vddrfa1p3-supply = <&vreg_s11b>;
+		vddrfa1p9-supply = <&vreg_s1c>;
+		vddpcie1p3-supply = <&vreg_s11b>;
+		vddpcie1p9-supply = <&vreg_s1c>;
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-s10-supply = <&vreg_vph_pwr>;
+		vdd-s11-supply = <&vreg_vph_pwr>;
+		vdd-s12-supply = <&vreg_vph_pwr>;
+		vdd-l1-l4-supply = <&vreg_s12b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_s10b: smps10 {
+			regulator-name = "vreg_s10b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_s11b: smps11 {
+			regulator-name = "vreg_s11b";
+			regulator-min-microvolt = <1272000>;
+			regulator-max-microvolt = <1272000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s12b: smps12 {
+			regulator-name = "vreg_s12b";
+			regulator-min-microvolt = <984000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b: ldo1 {
+			regulator-name = "vreg_l1b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3b: ldo3 {
+			regulator-name = "vreg_l3b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+
+		vreg_l4b: ldo4 {
+			regulator-name = "vreg_l4b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b: ldo6 {
+			regulator-name = "vreg_l6b";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8350c-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-bob-supply = <&vreg_vph_pwr>;
+		vdd-l1-l12-supply = <&vreg_s1c>;
+		vdd-l2-l8-supply = <&vreg_s1c>;
+		vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+		vdd-l6-l9-l11-supply = <&vreg_bob>;
+		vdd-l10-supply = <&vreg_s11b>;
+
+		vreg_s1c: smps1 {
+			regulator-name = "vreg_s1c";
+			regulator-min-microvolt = <1880000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12c: ldo12 {
+			regulator-name = "vreg_l12c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13c: ldo13 {
+			regulator-name = "vreg_l13c";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-name = "vreg_bob";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+			regulator-always-on;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-l4-supply = <&vreg_s11b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_l2d: ldo2 {
+			regulator-name = "vreg_l2d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d: ldo3 {
+			regulator-name = "vreg_l3d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+				 RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4d: ldo4 {
+			regulator-name = "vreg_l4d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6d: ldo6 {
+			regulator-name = "vreg_l6d";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7d: ldo7 {
+			regulator-name = "vreg_l7d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8d: ldo8 {
+			regulator-name = "vreg_l8d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9d: ldo9 {
+			regulator-name = "vreg_l9d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10d: ldo10 {
+			regulator-name = "vreg_l10d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&dispcc0 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn";
+	};
+};
+
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_0_qmpphy_dp_in>;
+};
+
+&mdss0_dp1 {
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_1_qmpphy_dp_in>;
+};
+
+&mdss0_dp2 {
+	compatible = "qcom,sc8280xp-dp";
+
+	data-lanes = <0 1 2 3>;
+
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+			mdss0_dp2_phy_out: endpoint {
+				remote-endpoint = <&dp1_connector_in>;
+			};
+		};
+	};
+};
+
+&mdss0_dp2_phy {
+	compatible = "qcom,sc8280xp-dp-phy";
+
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
+
+	status = "okay";
+};
+
+&pcie2a {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie2a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie2a_phy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	max-link-speed = <2>;
+
+	perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wlan>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1103";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		qcom,ath11k-calibration-variant = "MS_Volterra";
+	};
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
+
+	status = "okay";
+};
+
+&pmc8280c_lpg {
+	status = "okay";
+};
+
+&pmk8280_adc_tm {
+	status = "okay";
+
+	sys-therm@0 {
+		reg = <0>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@1 {
+		reg = <1>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@2 {
+		reg = <2>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@3 {
+		reg = <3>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@4 {
+		reg = <4>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@5 {
+		reg = <5>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@6 {
+		reg = <6>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@7 {
+		reg = <7>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+};
+
+&pmk8280_pon_pwrkey {
+	status = "okay";
+};
+
+&pmk8280_pon_resin {
+	status = "okay";
+};
+
+&pmk8280_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+
+	status = "okay";
+};
+
+&pmk8280_sdam_6 {
+	status = "okay";
+
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};
+
+&pmk8280_vadc {
+	channel@144 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm1";
+	};
+
+	channel@145 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm2";
+	};
+
+	channel@146 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm3";
+	};
+
+	channel@147 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm4";
+	};
+
+	channel@344 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm5";
+	};
+
+	channel@345 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm6";
+	};
+
+	channel@346 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm7";
+	};
+
+	channel@347 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm8";
+	};
+};
+
+&qup0 {
+	status = "okay";
+};
+
+&qup1 {
+	status = "okay";
+};
+
+&qup2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcadsp8280.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_nsp0 {
+	firmware-name = "qcom/sc8280xp/microsoft/blackrock/qccdsp8280.mbn";
+
+	status = "okay";
+};
+
+&rxmacro {
+	status = "okay";
+};
+
+&sound {
+	compatible = "qcom,sc8280xp-sndcard";
+	model = "microsoft/blackrock";
+
+	wcd-playback-dai-link {
+		link-name = "WCD Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wcd-capture-dai-link {
+		link-name = "WCD Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wsa-dai-link {
+		link-name = "WSA Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&swr0 0>, <&wsamacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	va-dai-link {
+		link-name = "VA Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+
+		codec {
+			sound-dai = <&vamacro 0>;
+		};
+	};
+};
+
+&swr0 {
+	status = "okay";
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_rx: wcd9380-rx@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: wcd9380-tx@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
+&txmacro {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
+&usb_0_hsphy {
+	vdda-pll-supply = <&vreg_l9d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l9d>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp0_out>;
+};
+
+&usb_0_qmpphy_out {
+	remote-endpoint = <&pmic_glink_con0_ss>;
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l4b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l13c>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l4b>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp1_out>;
+};
+
+&usb_1_qmpphy_out {
+	remote-endpoint = <&pmic_glink_con1_ss>;
+};
+
+&usb_2 {
+	pinctrl-0 = <&usb2_en_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+	phy-names = "usb2-0", "usb3-0";
+};
+
+&usb_2_hsphy0 {
+	vdda-pll-supply = <&vreg_l1b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy0 {
+	vdda-phy-supply = <&vreg_l1b>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_s10b>;
+
+	qcom,dmic-sample-rate = <4800000>;
+
+	status = "okay";
+};
+
+&wsamacro {
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
+
+/* PINCTRL */
+
+&lpass_tlmm {
+	status = "okay";
+};
+
+&pmc8280_1_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+
+	edp_bl_reg_en: edp-bl-reg-en-state {
+		pins = "gpio9";
+		function = "normal";
+	};
+};
+
+&pmc8280_2_gpios {
+	wwan_sw_en: wwan-sw-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&pmc8280c_gpios {
+	edp_bl_pwm: edp-bl-pwm-state {
+		pins = "gpio8";
+		function = "func1";
+	};
+};
+
+&pmr735a_gpios {
+	hastings_reg_en: hastings-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&tlmm {
+	bt_default: bt-default-state {
+		hstp-bt-en-pins {
+			pins = "gpio133";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		hstp-sw-ctrl-pins {
+			pins = "gpio132";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio135";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie2a_default: pcie2a-default-state {
+		clkreq-n-pins {
+			pins = "gpio142";
+			function = "pcie2a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio145";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie3a_default: pcie3a-default-state {
+		clkreq-n-pins {
+			pins = "gpio150";
+			function = "pcie3a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio151";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio140";
+			function = "pcie4_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio141";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio139";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	uart2_default: uart2-default-state {
+		cts-pins {
+			pins = "gpio121";
+			function = "qup2";
+			bias-bus-hold;
+		};
+
+		rts-pins {
+			pins = "gpio122";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		rx-pins {
+			pins = "gpio124";
+			function = "qup2";
+			bias-pull-up;
+		};
+
+		tx-pins {
+			pins = "gpio123";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	usb0_sbu_default: usb0-sbu-state {
+		oe-n-pins {
+			pins = "gpio101";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+
+		sel-pins {
+			pins = "gpio164";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+		};
+	};
+
+	usb1_sbu_default: usb1-sbu-state {
+		oe-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+
+		sel-pins {
+			pins = "gpio47";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+		};
+	};
+
+	usb2_en_state: usb2-en-state {
+		/* TS3USB221A USB2.0 mux select */
+		pins = "gpio24";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	wcd_default: wcd-default-state {
+		reset-pins {
+			pins = "gpio106";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio134";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
index ef06d1ac084..01501acb179 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
@@ -2743,7 +2743,7 @@
 
 		remoteproc_adsp: remoteproc@3000000 {
 			compatible = "qcom,sc8280xp-adsp-pas";
-			reg = <0 0x03000000 0 0x100>;
+			reg = <0 0x03000000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -3536,6 +3536,8 @@
 					    "usb2-2",
 					    "usb2-3";
 				dr_mode = "host";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3593,6 +3595,8 @@
 				iommus = <&apps_smmu 0x820 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -3670,6 +3674,8 @@
 				iommus = <&apps_smmu 0x860 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -3900,26 +3906,26 @@
 				    "vfe3",
 				    "csid3";
 
-			interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csid1_lite",
 					  "vfe_lite1",
 					  "csiphy3",
@@ -5254,7 +5260,7 @@
 
 		remoteproc_nsp0: remoteproc@1b300000 {
 			compatible = "qcom,sc8280xp-nsp0-pas";
-			reg = <0 0x1b300000 0 0x100>;
+			reg = <0 0x1b300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -5385,7 +5391,7 @@
 
 		remoteproc_nsp1: remoteproc@21300000 {
 			compatible = "qcom,sc8280xp-nsp1-pas";
-			reg = <0 0x21300000 0 0x100>;
+			reg = <0 0x21300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
index c509bbfe5d3..735a21df8cc 100644
--- a/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
+++ b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
@@ -46,6 +46,18 @@
 		};
 	};
 
+	backlight: gpio-backlight {
+		compatible = "gpio-backlight";
+
+		gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+		default-on;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&backlight_enable_active>;
+		pinctrl-1 = <&backlight_enable_sleep>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		key-volume-up {
@@ -63,6 +75,49 @@
 	};
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&pm8953_s3>;
+	vddio-supply = <&pm8953_l6>;
+
+	status = "okay";
+
+	panel@0 {
+		compatible = "boe,tv101wum-ll2";
+		reg = <0>;
+
+		vsp-supply = <&lab>;
+		vsn-supply = <&ibb>;
+		reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+		backlight = <&backlight>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&panel_reset_active>;
+		pinctrl-1 = <&panel_reset_sleep>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&panel_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	vcca-supply = <&pm8953_l3>;
+
+	status = "okay";
+};
+
 &hsusb_phy {
 	vdd-supply = <&pm8953_l3>;
 	vdda-pll-supply = <&pm8953_l7>;
@@ -90,6 +145,18 @@
 	};
 };
 
+&ibb {
+	regulator-min-microvolt = <4600000>;
+	regulator-max-microvolt = <6000000>;
+	qcom,discharge-resistor-kohms = <32>;
+};
+
+&lab {
+	regulator-min-microvolt = <4600000>;
+	regulator-max-microvolt = <6000000>;
+	qcom,soft-start-us = <800>;
+};
+
 &pm8953_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 	status = "okay";
@@ -237,6 +304,36 @@
 &tlmm {
 	gpio-reserved-ranges = <0 4>, <135 4>;
 
+	backlight_enable_active: backlight-enable-active-state {
+		pins = "gpio16";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	backlight_enable_sleep: backlight-enable-sleep-state {
+		pins = "gpio16";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	panel_reset_active: panel-reset-active-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	panel_reset_sleep: panel-reset-sleep-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	ts_int_active: ts-int-active-state {
 		pins = "gpio65";
 		function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/sdm630.dtsi b/dts/upstream/src/arm64/qcom/sdm630.dtsi
index 19420cfdadf..a2c079bac1a 100644
--- a/dts/upstream/src/arm64/qcom/sdm630.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm630.dtsi
@@ -1300,6 +1300,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				phys = <&qusb2phy0>, <&usb3_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
@@ -1505,6 +1507,8 @@
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				/* This is the HS-only host */
 				maximum-speed = "high-speed";
diff --git a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
index 176b0119fe6..74b5d9c68eb 100644
--- a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
+++ b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include "sdm670.dtsi"
@@ -49,20 +50,6 @@
 		};
 	};
 
-	clocks {
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <32764>;
-		};
-
-		xo_board: xo-board {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <38400000>;
-		};
-	};
-
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -407,6 +394,15 @@
 	status = "okay";
 };
 
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sdm670/sargo/a615_zap.mbn";
+	};
+};
+
 &i2c9 {
 	clock-frequency = <100000>;
 	status = "okay";
@@ -482,6 +478,19 @@
 	status = "okay";
 };
 
+&pm660l_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <1>, <2>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <1500000>;
+		flash-max-timeout-us = <1280000>;
+	};
+};
+
 &pm660l_gpios {
 	vol_up_pin: vol-up-state {
 		pins = "gpio7";
diff --git a/dts/upstream/src/arm64/qcom/sdm670.dtsi b/dts/upstream/src/arm64/qcom/sdm670.dtsi
index c93dd06c0b7..279e62ec543 100644
--- a/dts/upstream/src/arm64/qcom/sdm670.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm670.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -28,6 +29,20 @@
 
 	chosen { };
 
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -617,6 +632,11 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			gpu_speed_bin: gpu_speed_bin@1a2 {
+				reg = <0x1a2 0x2>;
+				bits = <5 8>;
+			};
+
 			qusb2_hstx_trim: hstx-trim@1eb {
 				reg = <0x1eb 0x1>;
 				bits = <1 4>;
@@ -1299,6 +1319,180 @@
 			};
 		};
 
+		gpu: gpu@5000000 {
+			compatible = "qcom,adreno-615.0", "qcom,adreno";
+
+			reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+			/*
+			 * Look ma, no clocks! The GPU clocks and power are
+			 * controlled entirely by the GMU
+			 */
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;
+			interconnect-names = "gfx-mem";
+
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-780000000 {
+					opp-hz = /bits/ 64 <780000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x8>;
+				};
+
+				opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x8>;
+				};
+
+				opp-700000000 {
+					opp-hz = /bits/ 64 <700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x4>;
+				};
+
+				opp-650000000 {
+					opp-hz = /bits/ 64 <650000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xc>;
+				};
+
+				opp-565000000 {
+					opp-hz = /bits/ 64 <565000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xc>;
+				};
+
+				opp-504000000 {
+					opp-hz = /bits/ 64 <504000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x2>;
+				};
+
+				opp-430000000 {
+					opp-hz = /bits/ 64 <430000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-355000000 {
+					opp-hz = /bits/ 64 <355000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <6220000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-267000000 {
+					opp-hz = /bits/ 64 <267000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <4068000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-180000000 {
+					opp-hz = /bits/ 64 <180000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					opp-peak-kBps = <1804000>;
+					opp-supported-hw = <0xf>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0 0x05040000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_CFG_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
+
+			reg = <0 0x0506a000 0 0x30000>,
+			      <0 0x0b280000 0 0x10000>,
+			      <0 0x0b480000 0 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx", "gx";
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,sdm845-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk_src",
+				      "gcc_gpu_gpll0_div_clk_src";
+		};
+
 		usb_1_hsphy: phy@88e2000 {
 			compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
 			reg = <0 0x088e2000 0 0x400>;
@@ -1400,6 +1594,16 @@
 			#interrupt-cells = <4>;
 		};
 
+		camcc: clock-controller@ad00000 {
+			compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
+			reg = <0 0x0ad00000 0 0x10000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		mdss: display-subsystem@ae00000 {
 			compatible = "qcom,sdm670-mdss";
 			reg = <0 0x0ae00000 0 0x1000>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso b/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
index 0a87df806ca..59970082da4 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
+++ b/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
@@ -79,45 +79,3 @@
 		};
 	};
 };
-
-&cci_i2c1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	camera@60 {
-		compatible = "ovti,ov7251";
-
-		/* I2C address as per ov7251.txt linux documentation */
-		reg = <0x60>;
-
-		/* CAM3_RST_N */
-		enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&cam3_default>;
-
-		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
-		clock-names = "xclk";
-		clock-frequency = <24000000>;
-
-		/*
-		 * The &vreg_s4a_1p8 trace always powered on.
-		 *
-		 * The 2.8V vdda-supply regulator is enabled when the
-		 * vreg_s4a_1p8 trace is pulled high.
-		 * It too is represented by a fixed regulator.
-		 *
-		 * No 1.2V vddd-supply regulator is used.
-		 */
-		vdddo-supply = <&vreg_lvs1a_1p8>;
-		vdda-supply = <&cam3_avdd_2v8>;
-
-		status = "disabled";
-
-		port {
-			ov7251_ep: endpoint {
-				data-lanes = <0 1>;
-/*				remote-endpoint = <&csiphy3_ep>; */
-			};
-		};
-	};
-};
diff --git a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
index 486ce175e6b..ddb82ecb0a9 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
+++ b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
@@ -452,7 +452,6 @@
 		irq-gpio = <&tlmm 125 GPIO_TRANSITORY>;
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2160>;
-		focaltech,max-touch-number = <5>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/qcom/sdm845.dtsi b/dts/upstream/src/arm64/qcom/sdm845.dtsi
index 1ed794638a7..d0314cdf0b9 100644
--- a/dts/upstream/src/arm64/qcom/sdm845.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845.dtsi
@@ -4139,6 +4139,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4215,6 +4217,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -4326,16 +4330,16 @@
 				"vfe1",
 				"vfe_lite";
 
-			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csid0",
 				"csid1",
 				"csid2",
@@ -5159,7 +5163,6 @@
 				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
-			dma-coherent;
 		};
 
 		anoc_1_tbu: tbu@150c5000 {
diff --git a/dts/upstream/src/arm64/qcom/sdx75.dtsi b/dts/upstream/src/arm64/qcom/sdx75.dtsi
index 5f7e59ecf1c..b0a8a0fe5f3 100644
--- a/dts/upstream/src/arm64/qcom/sdx75.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdx75.dtsi
@@ -34,7 +34,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -893,7 +893,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sdx75-mpss-pas";
-			reg = <0 0x04080000 0 0x4040>;
+			reg = <0 0x04080000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1037,6 +1037,8 @@
 				iommus = <&apps_smmu 0x80 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>,
 				       <&usb_qmpphy>;
 				phy-names = "usb2-phy",
diff --git a/dts/upstream/src/arm64/qcom/sm4250.dtsi b/dts/upstream/src/arm64/qcom/sm4250.dtsi
index a0ed61925e1..cd8c8e59976 100644
--- a/dts/upstream/src/arm64/qcom/sm4250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4250.dtsi
@@ -36,3 +36,42 @@
 &cpu7 {
 	compatible = "qcom,kryo240";
 };
+
+&lpass_tlmm {
+	compatible = "qcom,sm4250-lpass-lpi-pinctrl";
+	gpio-ranges = <&lpass_tlmm 0 0 27>;
+
+	lpi_i2s2_active: lpi-i2s2-active-state {
+		sck-pins {
+			pins = "gpio10";
+			function = "i2s2_clk";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ws-pins {
+			pins = "gpio11";
+			function = "i2s2_ws";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		data-pins {
+			pins = "gpio12";
+			function = "i2s2_data";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ext-mclk1-pins {
+			pins = "gpio18";
+			function = "ext_mclk1_a";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sm4450.dtsi b/dts/upstream/src/arm64/qcom/sm4450.dtsi
index a0de5fe16fa..27453771aa6 100644
--- a/dts/upstream/src/arm64/qcom/sm4450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4450.dtsi
@@ -29,7 +29,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 
diff --git a/dts/upstream/src/arm64/qcom/sm6115.dtsi b/dts/upstream/src/arm64/qcom/sm6115.dtsi
index 9b23534c456..94c081bf7a8 100644
--- a/dts/upstream/src/arm64/qcom/sm6115.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6115.dtsi
@@ -14,6 +14,9 @@
 #include <dt-bindings/interconnect/qcom,sm6115.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -808,6 +811,20 @@
 			};
 		};
 
+		lpass_tlmm: pinctrl@a7c0000 {
+			compatible = "qcom,sm6115-lpass-lpi-pinctrl";
+			reg = <0x0 0x0a7c0000 0x0 0x20000>,
+			      <0x0 0x0a950000 0x0 0x10000>;
+
+			clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "audio";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 19>;
+
+		};
+
 		gcc: clock-controller@1400000 {
 			compatible = "qcom,gcc-sm6115";
 			reg = <0x0 0x01400000 0x0 0x1f0000>;
@@ -2027,7 +2044,7 @@
 
 		remoteproc_mpss: remoteproc@6080000 {
 			compatible = "qcom,sm6115-mpss-pas";
-			reg = <0x0 0x06080000 0x0 0x100>;
+			reg = <0x0 0x06080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2670,9 +2687,9 @@
 			};
 		};
 
-		remoteproc_adsp: remoteproc@ab00000 {
+		remoteproc_adsp: remoteproc@a400000 {
 			compatible = "qcom,sm6115-adsp-pas";
-			reg = <0x0 0x0ab00000 0x0 0x100>;
+			reg = <0x0 0x0a400000 0x0 0x4040>;
 
 			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
 					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2701,6 +2718,76 @@
 				qcom,remote-pid = <2>;
 				mboxes = <&apcs_glb 8>;
 
+				apr {
+					compatible = "qcom,apr-v2";
+					qcom,glink-channels = "apr_audio_svc";
+					qcom,domain = <APR_DOMAIN_ADSP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					service@3 {
+						reg = <APR_SVC_ADSP_CORE>;
+						compatible = "qcom,q6core";
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+					};
+
+					q6afe: service@4 {
+						compatible = "qcom,q6afe";
+						reg = <APR_SVC_AFE>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6afedai: dais {
+							compatible = "qcom,q6afe-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6afecc: clock-controller {
+							compatible = "qcom,q6afe-clocks";
+							#clock-cells = <2>;
+						};
+					};
+
+					q6asm: service@7 {
+						compatible = "qcom,q6asm";
+						reg = <APR_SVC_ASM>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6asmdai: dais {
+							compatible = "qcom,q6asm-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							iommus = <&apps_smmu 0x1c1 0x0>;
+
+							dai@0 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
+							};
+
+							dai@1 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
+							};
+
+							dai@2 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
+							};
+						};
+					};
+
+					q6adm: service@8 {
+						compatible = "qcom,q6adm";
+						reg = <APR_SVC_ADM>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6routing: routing {
+							compatible = "qcom,q6adm-routing";
+							#sound-dai-cells = <0>;
+						};
+					};
+				};
+
 				fastrpc {
 					compatible = "qcom,fastrpc";
 					qcom,glink-channels = "fastrpcglink-apps-dsp";
@@ -2744,7 +2831,7 @@
 
 		remoteproc_cdsp: remoteproc@b300000 {
 			compatible = "qcom,sm6115-cdsp-pas";
-			reg = <0x0 0x0b300000 0x0 0x100000>;
+			reg = <0x0 0x0b300000 0x0 0x4040>;
 
 			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
 					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm6125.dtsi b/dts/upstream/src/arm64/qcom/sm6125.dtsi
index 17d528d6393..350d807a622 100644
--- a/dts/upstream/src/arm64/qcom/sm6125.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6125.dtsi
@@ -28,7 +28,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			clock-output-names = "sleep_clk";
 		};
 	};
@@ -1209,6 +1209,8 @@
 				phy-names = "usb2-phy";
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				maximum-speed = "high-speed";
 				dr_mode = "peripheral";
 			};
diff --git a/dts/upstream/src/arm64/qcom/sm6350.dtsi b/dts/upstream/src/arm64/qcom/sm6350.dtsi
index 8d697280249..00ad1d09a19 100644
--- a/dts/upstream/src/arm64/qcom/sm6350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6350.dtsi
@@ -936,7 +936,7 @@
 				power-domains = <&rpmhpd SM6350_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
-						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
+						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
@@ -1283,7 +1283,7 @@
 
 		adsp: remoteproc@3000000 {
 			compatible = "qcom,sm6350-adsp-pas";
-			reg = <0 0x03000000 0 0x100>;
+			reg = <0x0 0x03000000 0x0 0x10000>;
 
 			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1503,7 +1503,7 @@
 
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm6350-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1924,6 +1924,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				usb-role-switch;
diff --git a/dts/upstream/src/arm64/qcom/sm6375.dtsi b/dts/upstream/src/arm64/qcom/sm6375.dtsi
index e0b1c54e98c..0faa3a40ff8 100644
--- a/dts/upstream/src/arm64/qcom/sm6375.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6375.dtsi
@@ -29,7 +29,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -1516,9 +1516,9 @@
 			#power-domain-cells = <1>;
 		};
 
-		remoteproc_mss: remoteproc@6000000 {
+		remoteproc_mss: remoteproc@6080000 {
 			compatible = "qcom,sm6375-mpss-pas";
-			reg = <0 0x06000000 0 0x4040>;
+			reg = <0x0 0x06080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1559,7 +1559,7 @@
 
 		remoteproc_adsp: remoteproc@a400000 {
 			compatible = "qcom,sm6375-adsp-pas";
-			reg = <0 0x0a400000 0 0x100>;
+			reg = <0 0x0a400000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1595,9 +1595,9 @@
 			};
 		};
 
-		remoteproc_cdsp: remoteproc@b000000 {
+		remoteproc_cdsp: remoteproc@b300000 {
 			compatible = "qcom,sm6375-cdsp-pas";
-			reg = <0x0 0x0b000000 0x0 0x100000>;
+			reg = <0x0 0x0b300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
index 2ee2561b57b..52b16a4fdc4 100644
--- a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
+++ b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
@@ -32,7 +32,7 @@
 	chassis-type = "handset";
 
 	/* required for bootloader to select correct board */
-	qcom,msm-id = <434 0x10000>, <459 0x10000>;
+	qcom,msm-id = <459 0x10000>;
 	qcom,board-id = <8 32>;
 
 	aliases {
diff --git a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
index bac08f00b30..6ea883b1edf 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
@@ -578,6 +578,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts b/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
index b039773c446..9a3d0ac6c42 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
@@ -376,8 +376,8 @@
 		pinctrl-0 = <&da7280_intr_default>;
 
 		dlg,actuator-type = "LRA";
-		dlg,dlg,const-op-mode = <1>;
-		dlg,dlg,periodic-op-mode = <1>;
+		dlg,const-op-mode = <1>;
+		dlg,periodic-op-mode = <1>;
 		dlg,nom-microvolt = <2000000>;
 		dlg,abs-max-microvolt = <2000000>;
 		dlg,imax-microamp = <129000>;
@@ -430,6 +430,11 @@
 	/* MAX34417 @ 0x1e */
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-mtp.dts b/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
index 256a1ba9494..2e1c7afe0aa 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
@@ -358,6 +358,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi b/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
index ae0ca48b89a..70fd6455518 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -601,6 +601,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150.dtsi b/dts/upstream/src/arm64/qcom/sm8150.dtsi
index cedae8d03a5..4dbda54b47a 100644
--- a/dts/upstream/src/arm64/qcom/sm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150.dtsi
@@ -3658,6 +3658,8 @@
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -3735,6 +3737,8 @@
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm64/qcom/sm8250-hdk.dts b/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
index 1bbb71e1a4f..f5c193c6c5f 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
@@ -373,6 +373,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
index 21b2ca1def8..7f592bd3024 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
@@ -627,6 +627,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
index f6870d3f288..d8289b2698f 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
@@ -591,6 +591,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
index 3596dd328c3..813b009b7bd 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -30,6 +30,10 @@
 	qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */
 	qcom,board-id = <0x10008 0>;
 
+	aliases {
+		serial0 = &uart6;
+	};
+
 	chosen {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -97,6 +101,67 @@
 		};
 	};
 
+	qca6390-pmu {
+		compatible = "qcom,qca6390-pmu";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
+
+		vddaon-supply = <&vreg_s6a_0p95>;
+		vddpmu-supply = <&vreg_s6a_0p95>;
+		vddrfa0p95-supply = <&vreg_s6a_0p95>;
+		vddrfa1p3-supply = <&vreg_s8c_1p35>;
+		vddrfa1p9-supply = <&vreg_s5a_1p9>;
+		vddpcie1p3-supply = <&vreg_s8c_1p35>;
+		vddpcie1p9-supply = <&vreg_s5a_1p9>;
+		vddio-supply = <&vreg_s4a_1p8>;
+
+		wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+
 	vph_pwr: vph-pwr-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vph_pwr";
@@ -619,6 +684,25 @@
 	status = "okay";
 };
 
+&pcieport0 {
+	wifi@0 {
+		compatible = "pci17cb,1101";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+
+		qcom,ath11k-calibration-variant = "Xiaomi_Pad_5Pro";
+	};
+};
+
 &pm8150_gpios {
 	vol_up_n: vol-up-n-state {
 		pins = "gpio6";
@@ -673,6 +757,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
@@ -701,6 +790,37 @@
 
 &tlmm {
 	gpio-reserved-ranges = <40 4>;
+
+	bt_en_state: bt-default-state {
+		pins = "gpio21";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-pull-up;
+	};
+
+	wlan_en_state: wlan-default-state {
+		pins = "gpio20";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-pull-up;
+	};
+};
+
+&uart6 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,qca6390-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+	};
 };
 
 &usb_1 {
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
index 86e1f7fd1c2..668078ea4f0 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
@@ -554,6 +554,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250.dtsi b/dts/upstream/src/arm64/qcom/sm8250.dtsi
index 48318ed1ce9..c2937b4d9f1 100644
--- a/dts/upstream/src/arm64/qcom/sm8250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250.dtsi
@@ -84,7 +84,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -4207,6 +4207,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4294,6 +4296,8 @@
 				iommus = <&apps_smmu 0x20 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -4481,20 +4485,20 @@
 				    "vfe_lite0",
 				    "vfe_lite1";
 
-			interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csiphy0",
 					  "csiphy1",
 					  "csiphy2",
diff --git a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
index 796cbb58ef6..f9de0e49fa2 100644
--- a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
@@ -925,3 +925,10 @@
 		};
 	};
 };
+
+&ipa {
+	qcom,gsi-loader = "self";
+	memory-region = <&pil_ipa_fw_mem>;
+	status = "okay";
+	firmware-name = "qcom/sm8350/ipa_fws.mbn";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8350.dtsi b/dts/upstream/src/arm64/qcom/sm8350.dtsi
index 877905dfd86..69da30f35ba 100644
--- a/dts/upstream/src/arm64/qcom/sm8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8350.dtsi
@@ -42,7 +42,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -1876,6 +1876,142 @@
 			reg = <0x0 0x1fc0000 0x0 0x30000>;
 		};
 
+		adsp: remoteproc@3000000 {
+			compatible = "qcom,sm8350-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&pil_adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				apr {
+					compatible = "qcom,apr-v2";
+					qcom,glink-channels = "apr_audio_svc";
+					qcom,domain = <APR_DOMAIN_ADSP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					service@3 {
+						reg = <APR_SVC_ADSP_CORE>;
+						compatible = "qcom,q6core";
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+					};
+
+					q6afe: service@4 {
+						compatible = "qcom,q6afe";
+						reg = <APR_SVC_AFE>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6afedai: dais {
+							compatible = "qcom,q6afe-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6afecc: clock-controller {
+							compatible = "qcom,q6afe-clocks";
+							#clock-cells = <2>;
+						};
+					};
+
+					q6asm: service@7 {
+						compatible = "qcom,q6asm";
+						reg = <APR_SVC_ASM>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6asmdai: dais {
+							compatible = "qcom,q6asm-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							iommus = <&apps_smmu 0x1801 0x0>;
+
+							dai@0 {
+								reg = <0>;
+							};
+
+							dai@1 {
+								reg = <1>;
+							};
+
+							dai@2 {
+								reg = <2>;
+							};
+						};
+					};
+
+					q6adm: service@8 {
+						compatible = "qcom,q6adm";
+						reg = <APR_SVC_ADM>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6routing: routing {
+							compatible = "qcom,q6adm-routing";
+							#sound-dai-cells = <0>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+				};
+			};
+		};
+
 		lpass_tlmm: pinctrl@33c0000 {
 			compatible = "qcom,sm8350-lpass-lpi-pinctrl";
 			reg = <0 0x033c0000 0 0x20000>,
@@ -2078,7 +2214,7 @@
 
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8350-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2360,6 +2496,115 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		cdsp: remoteproc@a300000 {
+			compatible = "qcom,sm8350-cdsp-pas";
+			reg = <0x0 0x0a300000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>;
+			power-domain-names = "cx", "mxc";
+
+			interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+			memory-region = <&pil_cdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_cdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_CDSP
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "cdsp";
+				qcom,remote-pid = <5>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "cdsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+						iommus = <&apps_smmu 0x2161 0x0400>,
+							 <&apps_smmu 0x1181 0x0420>;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+						iommus = <&apps_smmu 0x2162 0x0400>,
+							 <&apps_smmu 0x1182 0x0420>;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x2163 0x0400>,
+							 <&apps_smmu 0x1183 0x0420>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x2164 0x0400>,
+							 <&apps_smmu 0x1184 0x0420>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x2165 0x0400>,
+							 <&apps_smmu 0x1185 0x0420>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x2166 0x0400>,
+							 <&apps_smmu 0x1186 0x0420>;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x2167 0x0400>,
+							 <&apps_smmu 0x1187 0x0420>;
+					};
+
+					compute-cb@8 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <8>;
+						iommus = <&apps_smmu 0x2168 0x0400>,
+							 <&apps_smmu 0x1188 0x0420>;
+					};
+
+					/* note: secure cb9 in downstream */
+				};
+			};
+		};
+
 		usb_1: usb@a6f8800 {
 			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
@@ -2409,6 +2654,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2485,6 +2732,8 @@
 				iommus = <&apps_smmu 0x20 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -3285,142 +3534,6 @@
 			dma-coherent;
 		};
 
-		adsp: remoteproc@17300000 {
-			compatible = "qcom,sm8350-adsp-pas";
-			reg = <0 0x17300000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			memory-region = <&pil_adsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				apr {
-					compatible = "qcom,apr-v2";
-					qcom,glink-channels = "apr_audio_svc";
-					qcom,domain = <APR_DOMAIN_ADSP>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					service@3 {
-						reg = <APR_SVC_ADSP_CORE>;
-						compatible = "qcom,q6core";
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-					};
-
-					q6afe: service@4 {
-						compatible = "qcom,q6afe";
-						reg = <APR_SVC_AFE>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6afedai: dais {
-							compatible = "qcom,q6afe-dais";
-							#address-cells = <1>;
-							#size-cells = <0>;
-							#sound-dai-cells = <1>;
-						};
-
-						q6afecc: clock-controller {
-							compatible = "qcom,q6afe-clocks";
-							#clock-cells = <2>;
-						};
-					};
-
-					q6asm: service@7 {
-						compatible = "qcom,q6asm";
-						reg = <APR_SVC_ASM>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6asmdai: dais {
-							compatible = "qcom,q6asm-dais";
-							#address-cells = <1>;
-							#size-cells = <0>;
-							#sound-dai-cells = <1>;
-							iommus = <&apps_smmu 0x1801 0x0>;
-
-							dai@0 {
-								reg = <0>;
-							};
-
-							dai@1 {
-								reg = <1>;
-							};
-
-							dai@2 {
-								reg = <2>;
-							};
-						};
-					};
-
-					q6adm: service@8 {
-						compatible = "qcom,q6adm";
-						reg = <APR_SVC_ADM>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6routing: routing {
-							compatible = "qcom,q6adm-routing";
-							#sound-dai-cells = <0>;
-						};
-					};
-				};
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1803 0x0>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1804 0x0>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1805 0x0>;
-					};
-				};
-			};
-		};
-
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
@@ -3589,115 +3702,6 @@
 			#freq-domain-cells = <1>;
 			#clock-cells = <1>;
 		};
-
-		cdsp: remoteproc@98900000 {
-			compatible = "qcom,sm8350-cdsp-pas";
-			reg = <0 0x98900000 0 0x1400000>;
-
-			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_CX>,
-					<&rpmhpd RPMHPD_MXC>;
-			power-domain-names = "cx", "mxc";
-
-			interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
-
-			memory-region = <&pil_cdsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_cdsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_CDSP
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "cdsp";
-				qcom,remote-pid = <5>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "cdsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@1 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <1>;
-						iommus = <&apps_smmu 0x2161 0x0400>,
-							 <&apps_smmu 0x1181 0x0420>;
-					};
-
-					compute-cb@2 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <2>;
-						iommus = <&apps_smmu 0x2162 0x0400>,
-							 <&apps_smmu 0x1182 0x0420>;
-					};
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x2163 0x0400>,
-							 <&apps_smmu 0x1183 0x0420>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x2164 0x0400>,
-							 <&apps_smmu 0x1184 0x0420>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x2165 0x0400>,
-							 <&apps_smmu 0x1185 0x0420>;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x2166 0x0400>,
-							 <&apps_smmu 0x1186 0x0420>;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x2167 0x0400>,
-							 <&apps_smmu 0x1187 0x0420>;
-					};
-
-					compute-cb@8 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <8>;
-						iommus = <&apps_smmu 0x2168 0x0400>,
-							 <&apps_smmu 0x1188 0x0420>;
-					};
-
-					/* note: secure cb9 in downstream */
-				};
-			};
-		};
 	};
 
 	thermal_zones: thermal-zones {
diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi
index 53147aa6f7e..9c809fc5fa4 100644
--- a/dts/upstream/src/arm64/qcom/sm8450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi
@@ -43,7 +43,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 		};
 	};
 
@@ -287,6 +287,192 @@
 		};
 	};
 
+	ete-0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu0>;
+
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	ete-1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu1>;
+
+		out-ports {
+			port {
+				ete1_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete1>;
+				};
+			};
+		};
+	};
+
+	ete-2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu2>;
+
+		out-ports {
+			port {
+				ete2_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete2>;
+				};
+			};
+		};
+	};
+
+	ete-3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu3>;
+
+		out-ports {
+			port {
+				ete3_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete3>;
+				};
+			};
+		};
+	};
+
+	ete-4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu4>;
+
+		out-ports {
+			port {
+				ete4_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete4>;
+				};
+			};
+		};
+	};
+
+	ete-5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu5>;
+
+		out-ports {
+			port {
+				ete5_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete5>;
+				};
+			};
+		};
+	};
+
+	ete-6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu6>;
+
+		out-ports {
+			port {
+				ete6_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete6>;
+				};
+			};
+		};
+	};
+
+	ete-7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu7>;
+
+		out-ports {
+			port {
+				ete7_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete7>;
+				};
+			};
+		};
+	};
+
+	funnel-ete {
+		compatible = "arm,coresight-static-funnel";
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint =
+						<&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint =
+						<&ete0_out_funnel_ete>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ete_in_ete1: endpoint {
+					remote-endpoint =
+						<&ete1_out_funnel_ete>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ete_in_ete2: endpoint {
+					remote-endpoint =
+						<&ete2_out_funnel_ete>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ete_in_ete3: endpoint {
+					remote-endpoint =
+						<&ete3_out_funnel_ete>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ete_in_ete4: endpoint {
+					remote-endpoint =
+						<&ete4_out_funnel_ete>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_ete_in_ete5: endpoint {
+					remote-endpoint =
+						<&ete5_out_funnel_ete>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_ete_in_ete6: endpoint {
+					remote-endpoint =
+						<&ete6_out_funnel_ete>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_ete_in_ete7: endpoint {
+					remote-endpoint =
+						<&ete7_out_funnel_ete>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sm8450", "qcom,scm";
@@ -2496,6 +2682,112 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,sm8450-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1801 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+				};
+			};
+		};
+
 		wsa2macro: codec@31e0000 {
 			compatible = "qcom,sm8450-lpass-wsa-macro";
 			reg = <0 0x031e0000 0 0x1000>;
@@ -2692,115 +2984,9 @@
 			status = "disabled";
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8450-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			memory-region = <&adsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1801 0x0>;
-						};
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1803 0x0>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1804 0x0>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1805 0x0>;
-					};
-				};
-			};
-		};
-
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8450-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0 0x32300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2907,7 +3093,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8450-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -4144,6 +4330,546 @@
 			};
 		};
 
+		stm@10002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x10002000 0x0 0x1000>,
+				<0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out_funnel_in0: endpoint {
+						remote-endpoint =
+							<&funnel_in0_in_stm>;
+					};
+				};
+			};
+		};
+
+		funnel@10041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel_in0_in_stm: endpoint {
+						remote-endpoint =
+							<&stm_out_funnel_in0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in0_out_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_in_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+					funnel_in1_in_funnel_apss: endpoint {
+						remote-endpoint =
+							<&funnel_apss_out_funnel_in1>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+					funnel_in1_in_funnel_dl_center: endpoint {
+						remote-endpoint =
+							<&funnel_dl_center_out_funnel_in1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_in_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					funnel_qdss_in_funnel_in0: endpoint {
+						remote-endpoint =
+							<&funnel_in0_out_funnel_qdss>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					funnel_qdss_in_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_out_funnel_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qdss_out_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_in_funnel_qdss>;
+					};
+				};
+			};
+		};
+
+		replicator@10046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_qdss_in_replicator_swao: endpoint {
+						remote-endpoint =
+							<&replicator_swao_out_replicator_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					replicator_qdss_out_replicator_etr: endpoint {
+						remote-endpoint =
+							<&replicator_etr_in_replicator_qdss>;
+					};
+				};
+			};
+		};
+
+		tmc_etr: tmc@10048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10048000 0x0 0x1000>;
+
+			iommus = <&apps_smmu 0x0600 0>;
+			arm,buffer-size = <0x10000>;
+
+			arm,scatter-gather;
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etr_in_replicator_etr: endpoint {
+						remote-endpoint =
+							<&replicator_etr_out_tmc_etr>;
+					};
+				};
+			};
+		};
+
+		replicator@1004e000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x1004e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_etr_in_replicator_qdss: endpoint {
+						remote-endpoint =
+							<&replicator_qdss_out_replicator_etr>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+
+					replicator_etr_out_tmc_etr: endpoint {
+						remote-endpoint =
+							<&tmc_etr_in_replicator_etr>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+					funnel_aoss_in_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_out_funnel_aoss>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					funnel_aoss_in_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_out_funnel_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_aoss_out_tmc_etf: endpoint {
+						remote-endpoint =
+							<&tmc_etf_in_funnel_aoss>;
+					};
+				};
+			};
+		};
+
+		tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_out_tmc_etf>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_out_replicator_swao: endpoint {
+						remote-endpoint =
+							<&replicator_swao_in_tmc_etf>;
+					};
+				};
+			};
+		};
+
+		replicator@10b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10b06000 0x0 0x1000>;
+
+			qcom,replicator-loses-context;
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_swao_in_tmc_etf: endpoint {
+						remote-endpoint =
+							<&tmc_etf_out_replicator_swao>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					replicator_swao_out_replicator_qdss: endpoint {
+						remote-endpoint =
+							<&replicator_qdss_in_replicator_swao>;
+					};
+				};
+			};
+		};
+
+		tpda@10b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+
+			reg = <0x0 0x10b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					tpda_aoss_in_tpdm_swao_prio_0: endpoint {
+						remote-endpoint =
+							<&tpdm_swao_prio_0_out_tpda_aoss>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					tpda_aoss_in_tpdm_swao: endpoint {
+						remote-endpoint =
+							<&tpdm_swao_out_tpda_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					tpda_aoss_out_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_in_tpda_aoss>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b09000 0x0 0x1000>;
+
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_swao_prio_0_out_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_in_tpdm_swao_prio_0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_swao_out_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_in_tpdm_swao>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_dlct_out_tpda_dl_center_26: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_26_in_tpdm_dlct>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c29000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_ipcc_out_tpda_dl_center_27: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_27_in_tpdm_ipcc>;
+					};
+				};
+			};
+		};
+
+		cti@10c2a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x10c2a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@10c2b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x10c2b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpda@10c2e000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c2e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1a {
+					reg = <26>;
+					tpda_dl_center_26_in_tpdm_dlct: endpoint {
+						remote-endpoint =
+							<&tpdm_dlct_out_tpda_dl_center_26>;
+					};
+				};
+
+				port@1b {
+					reg = <27>;
+					tpda_dl_center_27_in_tpdm_ipcc: endpoint {
+						remote-endpoint =
+							<&tpdm_ipcc_out_tpda_dl_center_27>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					tpda_dl_center_out_funnel_dl_center: endpoint {
+						remote-endpoint =
+							<&funnel_dl_center_in_tpda_dl_center>;
+					};
+				};
+			};
+		};
+
+		funnel@10c2f000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c2f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				port {
+					funnel_dl_center_in_tpda_dl_center: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_out_funnel_dl_center>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_dl_center_out_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_in_funnel_dl_center>;
+					};
+				};
+			};
+		};
+
+		funnel@13810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x13810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				port {
+					funnel_apss_in_funnel_ete: endpoint {
+						remote-endpoint =
+							<&funnel_ete_out_funnel_apss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_in_funnel_apss>;
+					};
+				};
+			};
+		};
+
+		cti@138e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x138e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@138f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x138f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@13900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x13900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
 		sram@146aa000 {
 			compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
 			reg = <0 0x146aa000 0 0x1000>;
@@ -4672,6 +5398,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
diff --git a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
index 01c92160260..29bc1ddfc7b 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
@@ -1172,7 +1172,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
index ab447fc252f..5648ab60ba4 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
@@ -825,7 +825,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
index 6052dd922ec..3a6cb279130 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
@@ -1005,7 +1005,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
index 3c5d8d26704..e8383faac57 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
@@ -565,7 +565,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 85d487ef80a..d90dc7b37c4 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -722,7 +722,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/sm8550.dtsi b/dts/upstream/src/arm64/qcom/sm8550.dtsi
index e7774d32fb6..eac8de4005d 100644
--- a/dts/upstream/src/arm64/qcom/sm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8550.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/firmware/qcom,scm.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -1734,7 +1735,8 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -1742,7 +1744,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -1850,7 +1853,8 @@
 				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -1858,7 +1862,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -2114,6 +2119,10 @@
 			qcom,gmu = <&gmu>;
 			#cooling-cells = <2>;
 
+			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
 			status = "disabled";
 
 			zap-shader {
@@ -2127,41 +2136,49 @@
 				opp-680000000 {
 					opp-hz = /bits/ 64 <680000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <16500000>;
 				};
 
 				opp-615000000 {
 					opp-hz = /bits/ 64 <615000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-550000000 {
 					opp-hz = /bits/ 64 <550000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <10687500>;
 				};
 
 				opp-475000000 {
 					opp-hz = /bits/ 64 <475000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-401000000 {
 					opp-hz = /bits/ 64 <401000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-348000000 {
 					opp-hz = /bits/ 64 <348000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-295000000 {
 					opp-hz = /bits/ 64 <295000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-220000000 {
 					opp-hz = /bits/ 64 <220000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					opp-peak-kBps = <2136718>;
 				};
 			};
 		};
@@ -2314,7 +2331,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8550-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2354,6 +2371,137 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,sm8550-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1063 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1064 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1065 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1066 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x1007 0x80>,
+							 <&apps_smmu 0x1067 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -2872,9 +3020,8 @@
 
 			power-domains = <&dispcc MDSS_GDSC>;
 
-			interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
-					<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
-			interconnect-names = "mdp0-mem", "mdp1-mem";
+			interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
+			interconnect-names = "mdp0-mem";
 
 			iommus = <&apps_smmu 0x1c00 0x2>;
 
@@ -4576,137 +4723,6 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8550-adsp-pas";
-			reg = <0x0 0x30000000 0x0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
-
-			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1063 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1064 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1065 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1066 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x1007 0x80>,
-							 <&apps_smmu 0x1067 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		nsp_noc: interconnect@320c0000 {
 			compatible = "qcom,sm8550-nsp-noc";
 			reg = <0 0x320c0000 0 0xe080>;
@@ -4716,7 +4732,7 @@
 
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8550-cdsp-pas";
-			reg = <0x0 0x32300000 0x0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
index f00bdff4280..d0912735b54 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
@@ -1113,7 +1113,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
index 0db2cb03f25..76ef43c10f7 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
@@ -730,7 +730,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
index c5e8c3c2df9..71033fba21b 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
@@ -1041,7 +1041,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &spi4 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650.dtsi b/dts/upstream/src/arm64/qcom/sm8650.dtsi
index 25e47505adc..86684cb9a93 100644
--- a/dts/upstream/src/arm64/qcom/sm8650.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8650.dtsi
@@ -365,6 +365,40 @@
 		};
 	};
 
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+
+		cpu = <&cpu0>;
+
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	funnel-ete {
+		compatible = "arm,coresight-static-funnel";
+
+		in-ports {
+			port {
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint = <&ete0_out_funnel_ete>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sm8650", "qcom,scm";
@@ -2233,7 +2267,8 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -2241,7 +2276,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 
 			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
 				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@@ -2365,7 +2401,8 @@
 				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -2373,7 +2410,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 
 			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
 				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@@ -2636,6 +2674,10 @@
 			qcom,gmu = <&gmu>;
 			#cooling-cells = <2>;
 
+			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
 			status = "disabled";
 
 			zap-shader {
@@ -2649,56 +2691,67 @@
 				opp-231000000 {
 					opp-hz = /bits/ 64 <231000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					opp-peak-kBps = <2136718>;
 				};
 
 				opp-310000000 {
 					opp-hz = /bits/ 64 <310000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <2136718>;
 				};
 
 				opp-366000000 {
 					opp-hz = /bits/ 64 <366000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-422000000 {
 					opp-hz = /bits/ 64 <422000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-500000000 {
 					opp-hz = /bits/ 64 <500000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-578000000 {
 					opp-hz = /bits/ 64 <578000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-629000000 {
 					opp-hz = /bits/ 64 <629000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					opp-peak-kBps = <10687500>;
 				};
 
 				opp-680000000 {
 					opp-hz = /bits/ 64 <680000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-720000000 {
 					opp-hz = /bits/ 64 <720000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-770000000 {
 					opp-hz = /bits/ 64 <770000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-834000000 {
 					opp-hz = /bits/ 64 <834000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <14398437>;
 				};
 			};
 		};
@@ -2853,7 +2906,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8650-mpss-pas";
-			reg = <0 0x04080000 0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2904,6 +2957,154 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,sm8650-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				qcom,remote-pid = <2>;
+
+				label = "lpass";
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+					label = "adsp";
+
+					qcom,non-secure-domain;
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1043 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1044 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1045 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1046 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+
+						iommus = <&apps_smmu 0x1007 0x40>,
+							 <&apps_smmu 0x1067 0x0>,
+							 <&apps_smmu 0x1087 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -3455,11 +3656,8 @@
 			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
 
 			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
-					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
-					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
 					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-			interconnect-names = "mdp0-mem",
-					     "mdp1-mem";
+			interconnect-names = "mdp0-mem";
 
 			power-domains = <&dispcc MDSS_GDSC>;
 
@@ -4854,6 +5052,138 @@
 			};
 		};
 
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					funnel_in1_in_funnel_apss: endpoint {
+						remote-endpoint = <&funnel_apss_out_funnel_in1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out_funnel_qdss: endpoint {
+						remote-endpoint = <&funnel_qdss_in_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					funnel_qdss_in_funnel_in1: endpoint {
+						remote-endpoint = <&funnel_in1_out_funnel_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qdss_out_funnel_aoss: endpoint {
+						remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+
+					funnel_aoss_in_funnel_qdss: endpoint {
+						remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_aoss_out_tmc_etf: endpoint {
+						remote-endpoint = <&tmc_etf_in_funnel_aoss>;
+					};
+				};
+			};
+		};
+
+		tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in_funnel_aoss: endpoint {
+						remote-endpoint = <&funnel_aoss_out_tmc_etf>;
+					};
+				};
+			};
+		};
+
+		funnel@13810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x13810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_apss_in_funnel_ete: endpoint {
+						remote-endpoint = <&funnel_ete_out_funnel_apss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out_funnel_in1: endpoint {
+						remote-endpoint = <&funnel_in1_in_funnel_apss>;
+					};
+				};
+			};
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;
@@ -5322,154 +5652,6 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8650-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog",
-					  "fatal",
-					  "ready",
-					  "handover",
-					  "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
-					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx",
-					     "lmx";
-
-			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				qcom,remote-pid = <2>;
-
-				label = "lpass";
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-
-					label = "adsp";
-
-					qcom,non-secure-domain;
-
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1043 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1044 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1045 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1046 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-
-						iommus = <&apps_smmu 0x1007 0x40>,
-							 <&apps_smmu 0x1067 0x0>,
-							 <&apps_smmu 0x1087 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		nsp_noc: interconnect@320c0000 {
 			compatible = "qcom,sm8650-nsp-noc";
 			reg = <0 0x320c0000 0 0xf080>;
@@ -5481,7 +5663,7 @@
 
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8650-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -5622,7 +5804,7 @@
 
 					/* note: secure cb9 in downstream */
 
-					compute-cb@10 {
+					compute-cb@12 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <12>;
 
@@ -5632,7 +5814,7 @@
 						dma-coherent;
 					};
 
-					compute-cb@11 {
+					compute-cb@13 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <13>;
 
@@ -5642,7 +5824,7 @@
 						dma-coherent;
 					};
 
-					compute-cb@12 {
+					compute-cb@14 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <14>;
 
diff --git a/dts/upstream/src/arm64/qcom/sm8750-mtp.dts b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts
new file mode 100644
index 00000000000..9e3aacad7bd
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts
@@ -0,0 +1,794 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "sm8750-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SM8750 MTP";
+	compatible = "qcom,sm8750-mtp", "qcom,sm8750";
+	chassis-type = "handset";
+
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s3g_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s7i_1p2>;
+		vdd-l12-supply = <&vreg_s3g_1p8>;
+		vdd-l15-supply = <&vreg_s3g_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		qcom,pmic-id = "b";
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <4000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3100000>;
+			regulator-max-microvolt = <3148000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p0: ldo11 {
+			regulator-name = "vreg_l11b_1p0";
+			regulator-min-microvolt = <1064000>;
+			regulator-max-microvolt = <1292000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s1d_0p97>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "d";
+
+		vreg_s1d_0p97: smps1 {
+			regulator-name = "vreg_s1d_0p97";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3d_1p2: smps3 {
+			regulator-name = "vreg_s3d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4d_0p85: smps4 {
+			regulator-name = "vreg_s4d_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1036000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1d_1p2: ldo1 {
+			regulator-name = "vreg_l1d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p88: ldo2 {
+			regulator-name = "vreg_l2d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_0p88: ldo3 {
+			regulator-name = "vreg_l3d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s3g_1p8>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "f";
+
+		vreg_s5f_0p5: smps5 {
+			regulator-name = "vreg_s5f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p88: ldo1 {
+			regulator-name = "vreg_l1f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p2: ldo2 {
+			regulator-name = "vreg_l2f_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p8: ldo3 {
+			regulator-name = "vreg_l3f_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s3g_1p8>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "g";
+
+		vreg_s1g_0p5: smps1 {
+			regulator-name = "vreg_s1g_0p5";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_1p8: smps3 {
+			regulator-name = "vreg_s3g_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_0p75: smps4 {
+			regulator-name = "vreg_s4g_0p75";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_0p91: ldo1 {
+			regulator-name = "vreg_l1g_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2g_1p8: ldo2 {
+			regulator-name = "vreg_l2g_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1860000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "i";
+
+		vreg_s7i_1p2: smps7 {
+			regulator-name = "vreg_s7i_1p2";
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1340000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s8i_0p9: smps8 {
+			regulator-name = "vreg_s8i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <972000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p2: ldo1 {
+			regulator-name = "vreg_l1i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p88: ldo3 {
+			regulator-name = "vreg_l3i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "j";
+
+		vreg_s2j_1p1: smps2 {
+			regulator-name = "vreg_s2j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3j_1p1: smps3 {
+			regulator-name = "vreg_s3j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p91: ldo1 {
+			regulator-name = "vreg_l1j_0p91";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "m";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_bob2>;
+		vdd-l5-supply = <&vreg_s3g_1p8>;
+		vdd-l6-supply = <&vreg_bob1>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1m_1p1: ldo1 {
+			regulator-name = "vreg_l1m_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2m_1p056: ldo2 {
+			regulator-name = "vreg_l2m_1p056";
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3m_2p8: ldo3 {
+			regulator-name = "vreg_l3m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4m_2p8: ldo4 {
+			regulator-name = "vreg_l4m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5m_1p8: ldo5 {
+			regulator-name = "vreg_l5m_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6m_2p8: ldo6 {
+			regulator-name = "vreg_l6m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7m_2p96: ldo7 {
+			regulator-name = "vreg_l7m_2p96";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "n";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+		vdd-l5-supply = <&vreg_bob2>;
+		vdd-l6-supply = <&vreg_bob2>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1n_1p1: ldo1 {
+			regulator-name = "vreg_l1n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2n_1p1: ldo2 {
+			regulator-name = "vreg_l2n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3n_1p8: ldo3 {
+			regulator-name = "vreg_l3n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4n_1p8: ldo4 {
+			regulator-name = "vreg_l4n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5n_2p8: ldo5 {
+			regulator-name = "vreg_l5n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6n_2p8: ldo6 {
+			regulator-name = "vreg_l6n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7n_3p3: ldo7 {
+			regulator-name = "vreg_l7n_3p3";
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+	};
+};
+
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-pull-up;
+		input-enable;
+		power-source = <1>;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+	status = "okay";
+
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&tlmm {
+	/* reserved for secure world */
+	gpio-reserved-ranges = <36 4>, <74 1>;
+};
+
+&uart7 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi b/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi
new file mode 100644
index 00000000000..6eb8d78937c
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	thermal-zones {
+		pm8550ve-d-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_d_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550ve-f-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_f_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550ve-g-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_g_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550vs-j-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550vs_j_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	/* PM8550VE */
+	pm8550ve_d: pmic@3 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_d_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_d_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_d_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8550ve_f: pmic@5 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_f_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_f_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_f_gpios 0 0 6>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8550ve_g: pmic@6 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x6 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_g_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_g_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_g_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	/* PM8550VS */
+	pm8550vs_j: pmic@9 {
+		compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
+		reg = <0x9 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550vs_j_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550vs_j_gpios: gpio@8800 {
+			compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550vs_j_gpios 0 0 6>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750-qrd.dts b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts
new file mode 100644
index 00000000000..f77efab0aef
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts
@@ -0,0 +1,792 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "sm8750-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SM8750 QRD";
+	compatible = "qcom,sm8750-qrd", "qcom,sm8750";
+	chassis-type = "handset";
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s3g_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s7i_1p2>;
+		vdd-l12-supply = <&vreg_s3g_1p8>;
+		vdd-l15-supply = <&vreg_s3g_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		qcom,pmic-id = "b";
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <4000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3100000>;
+			regulator-max-microvolt = <3148000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p0: ldo11 {
+			regulator-name = "vreg_l11b_1p0";
+			regulator-min-microvolt = <1064000>;
+			regulator-max-microvolt = <1292000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s1d_0p97>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "d";
+
+		vreg_s1d_0p97: smps1 {
+			regulator-name = "vreg_s1d_0p97";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3d_1p2: smps3 {
+			regulator-name = "vreg_s3d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4d_0p85: smps4 {
+			regulator-name = "vreg_s4d_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1036000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1d_1p2: ldo1 {
+			regulator-name = "vreg_l1d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p88: ldo2 {
+			regulator-name = "vreg_l2d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_0p88: ldo3 {
+			regulator-name = "vreg_l3d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s3g_1p8>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "f";
+
+		vreg_s5f_0p5: smps5 {
+			regulator-name = "vreg_s5f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p88: ldo1 {
+			regulator-name = "vreg_l1f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p2: ldo2 {
+			regulator-name = "vreg_l2f_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p8: ldo3 {
+			regulator-name = "vreg_l3f_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s3g_1p8>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "g";
+
+		vreg_s1g_0p5: smps1 {
+			regulator-name = "vreg_s1g_0p5";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_1p8: smps3 {
+			regulator-name = "vreg_s3g_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_0p75: smps4 {
+			regulator-name = "vreg_s4g_0p75";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_0p91: ldo1 {
+			regulator-name = "vreg_l1g_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2g_1p8: ldo2 {
+			regulator-name = "vreg_l2g_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1860000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "i";
+
+		vreg_s7i_1p2: smps7 {
+			regulator-name = "vreg_s7i_1p2";
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1340000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s8i_0p9: smps8 {
+			regulator-name = "vreg_s8i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <972000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p2: ldo1 {
+			regulator-name = "vreg_l1i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p88: ldo3 {
+			regulator-name = "vreg_l3i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "j";
+
+		vreg_s2j_1p1: smps2 {
+			regulator-name = "vreg_s2j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3j_1p1: smps3 {
+			regulator-name = "vreg_s3j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+
+		vreg_l1j_0p91: ldo1 {
+			regulator-name = "vreg_l1j_0p91";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "m";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+		vdd-l5-supply = <&vreg_s3g_1p8>;
+		vdd-l6-supply = <&vreg_bob1>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1m_1p1: ldo1 {
+			regulator-name = "vreg_l1m_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2m_1p056: ldo2 {
+			regulator-name = "vreg_l2m_1p056";
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3m_2p8: ldo3 {
+			regulator-name = "vreg_l3m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4m_2p8: ldo4 {
+			regulator-name = "vreg_l4m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5m_1p8: ldo5 {
+			regulator-name = "vreg_l5m_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6m_2p8: ldo6 {
+			regulator-name = "vreg_l6m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7m_2p96: ldo7 {
+			regulator-name = "vreg_l7m_2p96";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "n";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s7i_1p2>;
+		vdd-l5-supply = <&vreg_bob2>;
+		vdd-l6-supply = <&vreg_bob2>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1n_1p1: ldo1 {
+			regulator-name = "vreg_l1n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2n_1p1: ldo2 {
+			regulator-name = "vreg_l2n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3n_1p8: ldo3 {
+			regulator-name = "vreg_l3n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4n_1p8: ldo4 {
+			regulator-name = "vreg_l4n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5n_2p8: ldo5 {
+			regulator-name = "vreg_l5n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6n_2p8: ldo6 {
+			regulator-name = "vreg_l6n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7n_3p3: ldo7 {
+			regulator-name = "vreg_l7n_3p3";
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+	};
+};
+
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-pull-up;
+		input-enable;
+		power-source = <1>;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+	status = "okay";
+
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&tlmm {
+	/* reserved for secure world */
+	gpio-reserved-ranges = <36 4>, <74 1>;
+};
+
+&uart7 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750.dtsi b/dts/upstream/src/arm64/qcom/sm8750.dtsi
new file mode 100644
index 00000000000..3bbd7d18598
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750.dtsi
@@ -0,0 +1,2907 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-gcc.h>
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+		};
+
+		cpu6: cpu@10000 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu7: cpu@10100 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+
+				core5 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cluster0_c4: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "ret";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <93>;
+				exit-latency-us = <129>;
+				min-residency-us = <560>;
+			};
+
+			cluster1_c4: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "ret";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <172>;
+				exit-latency-us = <130>;
+				min-residency-us = <686>;
+			};
+
+		};
+
+		domain-idle-states {
+			cluster_cl5: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x01000054>;
+				entry-latency-us = <2150>;
+				exit-latency-us = <1983>;
+				min-residency-us = <9144>;
+			};
+
+			domain_ss3: domain-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x0200c354>;
+				entry-latency-us = <2800>;
+				exit-latency-us = <4400>;
+				min-residency-us = <10150>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sm8750", "qcom,scm";
+			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sm8750-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sm8750-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	memory@a0000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0xa0000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster1_c4>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster1_c4>;
+		};
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_cl5>;
+			power-domains = <&system_pd>;
+		};
+
+		system_pd: power-domain-system {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&domain_ss3>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_hyp_mem: gunyah-hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0xe00000>;
+			no-map;
+		};
+
+		cpusys_vm_mem: cpusys-vm-mem@80e00000 {
+			reg = <0x0 0x80e00000 0x0 0x40000>;
+			no-map;
+		};
+
+		cpucp_mem: cpucp@81200000 {
+			reg = <0x0 0x81200000 0x0 0x200000>;
+			no-map;
+		};
+
+		xbl_dtlog_mem: xbl-dtlog@81a00000 {
+			reg = <0x0 0x81a00000 0x0 0x40000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@81c00000 {
+			reg = <0x0 0x81c00000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@81c60000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x81c60000 0x0 0x20000>;
+			no-map;
+		};
+
+		/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+		aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
+			reg = <0x0 0x81c80000 0x0 0x74000>;
+			no-map;
+		};
+
+		/* Secdata region can be reused by apps */
+
+		smem_mem: smem@81d00000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x81d00000 0x0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
+			reg = <0x0 0x81f00000 0x0 0x100000>;
+			no-map;
+		};
+
+		cpucp_scandump_mem: cpucp-scandump@82000000 {
+			reg = <0x0 0x82000000 0x0 0x380000>;
+			no-map;
+		};
+
+		adsp_mhi_mem: adsp-mhi@82380000 {
+			reg = <0x0 0x82380000 0x0 0x20000>;
+			no-map;
+		};
+
+		soccp_sdi_mem: soccp-sdi@823a0000 {
+			reg = <0x0 0x823a0000 0x0 0x40000>;
+			no-map;
+		};
+
+		pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
+			reg = <0x0 0x823e0000 0x0 0x80000>;
+			no-map;
+		};
+
+		pvmfw_mem: pvmfw@824a0000 {
+			reg = <0x0 0x824a0000 0x0 0x100000>;
+			no-map;
+		};
+
+		global_sync_mem: global-sync@82600000 {
+			reg = <0x0 0x82600000 0x0 0x100000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@82700000 {
+			reg = <0x0 0x82700000 0x0 0x100000>;
+			no-map;
+		};
+
+		qdss_mem: qdss@82800000 {
+			reg = <0x0 0x82800000 0x0 0x2000000>;
+			no-map;
+		};
+
+		dsm_partition_1_mem: dsm-partition-1@84a00000 {
+			reg = <0x0 0x84a00000 0x0 0x4900000>;
+			no-map;
+		};
+
+		dsm_partition_2_mem: dsm-partition-2@89300000 {
+			reg = <0x0 0x89300000 0x0 0xa80000>;
+			no-map;
+		};
+
+		mpss_mem: mpss@8ba00000 {
+			reg = <0x0 0x8ba00000 0x0 0xf600000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
+			reg = <0x0 0x9b000000 0x0 0x80000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@9b080000 {
+			reg = <0x0 0x9b080000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@9b090000 {
+			reg = <0x0 0x9b090000 0x0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code@9b09a000 {
+			reg = <0x0 0x9b09a000 0x0 0x2000>;
+			no-map;
+		};
+
+		spss_region_mem: spss@9b0a0000  {
+			reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
+			no-map;
+		};
+
+		/* First part of the "SPU secure shared memory" region */
+		spu_tz_shared_mem: spu-tz-shared@9b280000 {
+			reg = <0x0 0x9b280000 0x0 0x40000>;
+			no-map;
+		};
+
+		/* Second part of the "SPU secure shared memory" region */
+		spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
+			reg = <0x0 0x9b2c0000 0x0 0x40000>;
+			no-map;
+		};
+
+		camera_mem: camera@9b300000 {
+			reg = <0x0 0x9b300000 0x0 0x800000>;
+			no-map;
+		};
+
+		camera_2_mem: camera-2@9bb00000 {
+			reg = <0x0 0x9bb00000 0x0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video@9c300000 {
+			reg = <0x0 0x9c300000 0x0 0x800000>;
+			no-map;
+		};
+
+		cvp_mem: cvp@9cb00000 {
+			reg = <0x0 0x9cb00000 0x0 0x700000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@9d200000 {
+			reg = <0x0 0x9d200000 0x0 0x1900000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
+			reg = <0x0 0x9eb00000 0x0 0x80000>;
+			no-map;
+		};
+
+		soccp_mem: soccp@9ec00000 {
+			reg = <0x0 0x9ec00000 0x0 0x180000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
+			reg = <0x0 0x9ed80000 0x0 0x80000>;
+			no-map;
+		};
+
+		adspslpi_mem: adspslpi@9ee00000 {
+			reg = <0x0 0x9ee00000 0x0 0x3a80000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: xbl-ramdump@b8000000 {
+			reg = <0x0 0xb8000000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		hwfence_shbuf: hwfence-shbuf@d4e23000 {
+			no-map;
+			reg = <0x0 0xd4e23000 0x0 0x2dd000>;
+		};
+
+		/* Merged tz_reserved, xbl_sc, and qtee regions */
+		tz_merged_mem: tz-merged@d8000000 {
+			reg = <0x0 0xd8000000 0x0 0x600000>;
+			no-map;
+		};
+
+		trust_ui_vm_mem: trust-ui-vm@f3800000 {
+			reg = <0x0 0xf3800000 0x0 0x4400000>;
+			no-map;
+		};
+
+		oem_vm_mem: oem-vm@f7c00000 {
+			reg = <0x0 0xf7c00000 0x0 0x4c00000>;
+			no-map;
+		};
+
+		llcc_lpi_mem: llcc-lpi@ff800000 {
+			reg = <0x0 0xff800000 0x0 0x800000>;
+			no-map;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sm8750-gcc";
+			reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <0>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		gpi_dma2: dma-controller@800000 {
+			compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00800000 0x0 0x60000>;
+
+			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0x1e>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0x436 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_2: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			iommus = <&apps_smmu 0x423 0x0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c8: i2c@880000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi8: spi@880000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c9: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi9: spi@884000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c10: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi10: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c11: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi11: spi@88c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c12: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c12_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi12: spi@890000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c13: i2c@894000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c13_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi13: spi@894000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart14: serial@898000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00898000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects =	<&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&qup_uart14_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+
+			i2c15: i2c@89c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0089c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c15_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi15: spi@89c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0089c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		i2c_master_hub_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-i2c-master-hub";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+			clock-names = "s-ahb";
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c_hub_0: i2c@980000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_1: i2c@984000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_2: i2c@988000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_3: i2c@98c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_4: i2c@990000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_5: i2c@994000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_6: i2c@998000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00998000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_7: i2c@99c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x0099c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c7_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_8: i2c@9a0000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x009a0000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_9: i2c@9a4000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x009a4000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00a00000 0x0 0x60000>;
+
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0x1e>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0xb6 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			iommus = <&apps_smmu 0xa3 0x0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c0: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi0: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c1: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi1: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c2: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi2: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c3: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi3: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c4: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi4: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c5: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi5: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c6: i2c@a98000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a98000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi6: spi@a98000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a98000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart7: serial@a9c000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+		};
+
+		cnoc_main: interconnect@1500000 {
+			compatible = "qcom,sm8750-cnoc-main";
+			reg = <0x0 0x01500000 0x0 0x16080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		config_noc: interconnect@1600000 {
+			compatible = "qcom,sm8750-config-noc";
+			reg = <0x0 0x01600000 0x0 0x6200>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sm8750-system-noc";
+			reg = <0x0 0x01680000 0x0 0x1d080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		pcie_noc: interconnect@16c0000 {
+			compatible = "qcom,sm8750-pcie-anoc";
+			reg = <0x0 0x016c0000 0x0 0x11400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sm8750-aggre1-noc";
+			reg = <0x0 0x016e0000 0x0 0x16400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm8750-aggre2-noc";
+			reg = <0x0 0x01700000 0x0 0x1f400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+		};
+
+		mmss_noc: interconnect@1780000 {
+			compatible = "qcom,sm8750-mmss-noc";
+			reg = <0x0 0x01780000 0x0 0x5b800>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		lpass_ag_noc: interconnect@7e40000 {
+			compatible = "qcom,sm8750-lpass-ag-noc";
+			reg = <0x0 0x07e40000 0x0 0xe080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		lpass_lpiaon_noc: interconnect@7400000 {
+			compatible = "qcom,sm8750-lpass-lpiaon-noc";
+			reg = <0x0 0x07400000 0x0 0x19080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		lpass_lpicx_noc: interconnect@7420000 {
+			compatible = "qcom,sm8750-lpass-lpicx-noc";
+			reg = <0x0 0x07420000 0x0 0x44080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sm8750-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
+
+			qcom,pdc-ranges = <0 745 51>, <51 527 47>,
+					  <98 609 32>, <130 717 12>,
+					  <142 251 5>, <147 796 16>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		spmi_bus: spmi@c400000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0 0x0c400000 0x0 0x3000>,
+			      <0x0 0x0c500000 0x0 0x400000>,
+			      <0x0 0x0c440000 0x0 0x80000>,
+			      <0x0 0x0c4c0000 0x0 0x10000>,
+			      <0x0 0x0c42d000 0x0 0x4000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			qcom,bus-id = <0>;
+
+			interrupt-controller;
+			#interrupt-cells = <4>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sm8750-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x102000>;
+
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			gpio-ranges = <&tlmm 0 0 216>;
+			wakeup-parent = <&pdc>;
+
+			hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio64", "gpio65";
+				function = "i2chub0_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio66", "gpio67";
+				function = "i2chub0_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio68", "gpio69";
+				function = "i2chub0_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio70", "gpio71";
+				function = "i2chub0_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio72", "gpio73";
+				function = "i2chub0_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio74", "gpio75";
+				function = "i2chub0_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio76", "gpio77";
+				function = "i2chub0_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio82", "gpio83";
+				function = "i2chub0_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio206", "gpio207";
+				function = "i2chub0_se8";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio80", "gpio81";
+				function = "i2chub0_se9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			pcie0_default_state: pcie0-default-state {
+				perst-pins {
+					pins = "gpio102";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio103";
+					function = "pcie0_clk_req_n";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio104";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio32", "gpio33";
+				function = "qup1_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio36", "gpio37";
+				function = "qup1_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio40", "gpio41";
+				function = "qup1_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio44", "gpio45";
+				function = "qup1_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio48", "gpio49";
+				function = "qup1_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio52", "gpio53";
+				function = "qup1_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio56", "gpio57";
+				function = "qup1_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio0", "gpio1";
+				function = "qup2_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio4", "gpio5";
+				function = "qup2_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup2_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio12", "gpio13";
+				function = "qup2_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio16", "gpio17";
+				function = "qup2_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio20", "gpio21";
+				function = "qup2_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio28", "gpio29";
+				function = "qup2_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_cs: qup-spi0-cs-state {
+				pins = "gpio35";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio32", "gpio33", "gpio34";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_cs: qup-spi1-cs-state {
+				pins = "gpio39";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio36", "gpio37", "gpio38";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio43";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio40", "gpio41", "gpio42";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_cs: qup-spi3-cs-state {
+				pins = "gpio47";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio44", "gpio45", "gpio46";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_cs: qup-spi4-cs-state {
+				pins = "gpio51";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio48", "gpio49", "gpio50";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_cs: qup-spi5-cs-state {
+				pins = "gpio55";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio52", "gpio53", "gpio54";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio59";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio56", "gpio57", "gpio58";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_cs: qup-spi8-cs-state {
+				pins = "gpio3";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_data_clk: qup-spi8-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_cs: qup-spi9-cs-state {
+				pins = "gpio7";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_cs: qup-spi10-cs-state {
+				pins = "gpio11";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_cs: qup-spi11-cs-state {
+				pins = "gpio15";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio12", "gpio13", "gpio14";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_cs: qup-spi12-cs-state {
+				pins = "gpio19";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_data_clk: qup-spi12-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi13_cs: qup-spi13-cs-state {
+				pins = "gpio23";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-pull-up;
+			};
+
+			qup_spi13_data_clk: qup-spi13-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi15_cs: qup-spi15-cs-state {
+				pins = "gpio31";
+				function = "qup2_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi15_data_clk: qup-spi15-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio28", "gpio29", "gpio30";
+				function = "qup2_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				/* TX, RX */
+				pins = "gpio62", "gpio63";
+				function = "qup1_se7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_uart14_default: qup-uart14-default-state {
+				/* TX, RX */
+				pins = "gpio26", "gpio27";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+				/* CTS, RTS */
+				pins = "gpio24", "gpio25";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		tcsrcc: clock-controller@f204008 {
+			compatible = "qcom,sm8750-tcsr", "syscon";
+			reg = <0x0 0x0f204008 0x0 0x3004>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+
+			dma-coherent;
+		};
+
+		intc: interrupt-controller@16000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x16000000 0x0 0x10000>,
+			      <0x0 0x16080000 0x0 0x200000>;
+
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			#interrupt-cells = <3>;
+			interrupt-controller;
+
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x40000>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@16040000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x16040000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		apps_rsc: rsc@16500000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x16500000 0x0 0x10000>,
+			      <0x0 0x16510000 0x0 0x10000>,
+			      <0x0 0x16520000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
+					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
+
+			label = "apps_rsc";
+
+			power-domains = <&system_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm8750-rpmh-clk";
+
+				clocks = <&xo_board>;
+				clock-names = "xo";
+
+				#clock-cells = <1>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,sm8750-rpmhpd";
+
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				#power-domain-cells = <1>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-16 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-48 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_d3: opp-50 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+					};
+
+					rpmhpd_opp_low_svs_d2: opp-52 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					};
+
+					rpmhpd_opp_low_svs_d1: opp-56 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					};
+
+					rpmhpd_opp_low_svs_d0: opp-60 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					};
+
+					rpmhpd_opp_low_svs: opp-64 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_l1: opp-80 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					};
+
+					rpmhpd_opp_svs: opp-128 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l0: opp-144 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-192 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_svs_l2: opp-224 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					};
+
+					rpmhpd_opp_nom: opp-256 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-320 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-336 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-384 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-416 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+
+					rpmhpd_opp_turbo_l2: opp-432 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+					};
+
+					rpmhpd_opp_turbo_l3: opp-448 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+					};
+
+					rpmhpd_opp_turbo_l4: opp-452 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+					};
+
+					rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+						opp-level =
+							<RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+					};
+				};
+			};
+		};
+
+		timer@16800000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x16800000 0x0 0x1000>;
+
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0 0 0 0 0x20000000>;
+
+			frame@16801000 {
+				reg = <0x0 0x16801000 0x1000>,
+				      <0x0 0x16802000 0x1000>;
+
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <0>;
+			};
+
+			frame@16803000 {
+				reg = <0x0 0x16803000 0x1000>;
+
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <1>;
+
+				status = "disabled";
+			};
+
+			frame@16805000 {
+				reg = <0x0 0x16805000 0x1000>;
+
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <2>;
+
+				status = "disabled";
+			};
+
+			frame@16807000 {
+				reg = <0x0 0x16807000 0x1000>;
+
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <3>;
+
+				status = "disabled";
+			};
+
+			frame@16809000 {
+				reg = <0x0 0x16809000 0x1000>;
+
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <4>;
+
+				status = "disabled";
+			};
+
+			frame@1680b000 {
+				reg = <0x0 0x1680b000 0x1000>;
+
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <5>;
+
+				status = "disabled";
+			};
+
+			frame@1680d000 {
+				reg = <0x0 0x1680d000 0x1000>;
+
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <6>;
+
+				status = "disabled";
+			};
+		};
+
+		gem_noc: interconnect@24100000 {
+			compatible = "qcom,sm8750-gem-noc";
+			reg = <0x0 0x24100000 0x0 0x14b080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		nsp_noc: interconnect@320c0000 {
+			compatible = "qcom,sm8750-nsp-noc";
+			reg = <0x0 0x320c0000 0x0 0x13080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts
new file mode 100644
index 00000000000..5e3970b26e2
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows";
+	compatible = "qcom,x1e001de-devkit", "qcom,x1e001de", "qcom,x1e80100";
+
+	aliases {
+		serial0 = &uart21;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+		/* Back panel port closer to the RJ45 connector */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Back panel port closer to the audio jack */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "host";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Front panel port */
+		connector@2 {
+			compatible = "usb-c-connector";
+			reg = <2>;
+			power-role = "dual";
+			data-role = "host";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss2_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss2_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss2_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss2_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss2_con_sbu_out>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E001DE-DEVKIT";
+		audio-routing = "IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_NVME_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&nvme_reg_en>;
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_pwr_1p15_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_1p15: regulator-rtmr2-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_1p8: regulator-rtmr2-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_3p3: regulator-rtmr2-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wwan: regulator-wwan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDX_VPH_PWR";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wwan_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn";
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK5>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr2_1p15>;
+		vdd33-supply = <&vreg_rtmr2_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr2_3p3>;
+		vddar-supply = <&vreg_rtmr2_1p15>;
+		vddat-supply = <&vreg_rtmr2_1p15>;
+		vddio-supply = <&vreg_rtmr2_1p8>;
+
+		reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>;
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss2_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss2_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss2_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss2_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss2_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c7 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	data-lanes = <0 1>;
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie5 {
+	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wwan>;
+
+	pinctrl-0 = <&pcie5_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie5_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie6a {
+	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie6a_default>;
+
+	status = "okay";
+};
+
+&pcie6a_phy {
+	vdda-phy-supply = <&vreg_l1d_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pm8550_gpios {
+	usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+	};
+};
+
+&pmc8380_5_gpios {
+	usb0_pwr_1p15_en: usb0-pwr-1p15-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+};
+
+&pm8550ve_9_gpios {
+	usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcadsp8380.mbn",
+			"qcom/x1e80100/Thundercomm/DEVKIT/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qccdsp8380.mbn",
+			"qcom/x1e80100/Thundercomm/DEVKIT/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l6b_1p8>;
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&smb2360_0 {
+	status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1 {
+	status = "okay";
+};
+
+&smb2360_1_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2 {
+	status = "okay";
+};
+
+&smb2360_2_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l8b_3p0>;
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <44 4>; /* SPI (TPM) */
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie5_default: pcie5-default-state {
+		clkreq-n-pins {
+			pins = "gpio150";
+			function = "pcie5_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio149";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio151";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie6a_default: pcie6a-default-state {
+		clkreq-n-pins {
+			pins = "gpio153";
+			function = "pcie6a_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio152";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio154";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state {
+		pins = "gpio189";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state {
+		pins = "gpio126";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state {
+		pins = "gpio187";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	sdc2_card_det_n: sdc2-card-det-state {
+		pins = "gpio71";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	wwan_sw_en: wwan-sw-en-state {
+		pins = "gpio221";
+		function = "gpio";
+		drive-strength = <4>;
+		bias-disable;
+	};
+};
+
+&uart21 {
+	compatible = "qcom,geni-debug-uart";
+	status = "okay";
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_0_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_1_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&retimer_ss1_ss_in>;
+};
+
+&usb_1_ss2_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_2_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss2 {
+	status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss2_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+	remote-endpoint = <&retimer_ss2_ss_in>;
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
index 66513fc8e67..b2c2347f54f 100644
--- a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+++ b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
@@ -19,6 +19,32 @@
 	compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100";
 	chassis-type = "laptop";
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
@@ -153,6 +179,85 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-LENOVO-Thinkpad-T14s";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS1",
+				"VA DMIC1", "MIC BIAS1",
+				"VA DMIC0", "VA MIC BIAS1",
+				"VA DMIC1", "VA MIC BIAS1",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -185,6 +290,13 @@
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
 		vreg_l2b_3p0: ldo2 {
 			regulator-name = "vreg_l2b_3p0";
 			regulator-min-microvolt = <3072000>;
@@ -495,6 +607,54 @@
 	};
 };
 
+&i2c5 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb5_repeater: redriver@43 {
+		compatible = "nxp,ptn3222";
+		reg = <0x43>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb5_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb6_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb6_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
 &i2c8 {
 	clock-frequency = <400000>;
 
@@ -515,6 +675,24 @@
 	/* TODO: second-sourced touchscreen @ 0x41 */
 };
 
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
 &mdss {
 	status = "okay";
 };
@@ -635,22 +813,107 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
 };
 
+&swr0 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Left Speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right Speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <34 2>, /* Unused */
 			       <44 4>, /* SPI (TPM) */
 			       <72 2>, /* Secure EC I2C connection (?) */
 			       <238 1>; /* UFS Reset */
 
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb5_reset_n: eusb5-reset-n-state {
+		pins = "gpio7";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb6_reset_n: eusb6-reset-n-state {
+		pins = "gpio184";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
 	tpad_default: tpad-default-state {
 		pins = "gpio3";
 		function = "gpio";
@@ -763,7 +1026,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -795,7 +1058,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -816,3 +1079,56 @@
 &usb_1_ss1_qmpphy_out {
 	remote-endpoint = <&pmic_glink_ss1_ss_in>;
 };
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_2_hsphy {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb5_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb6_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
index 8515c254e15..53781f9b13a 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
@@ -7,7 +7,9 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
 #include "x1e80100.dtsi"
 #include "x1e80100-pmics.dtsi"
@@ -17,6 +19,20 @@
 	compatible = "asus,vivobook-s15", "qcom,x1e80100";
 	chassis-type = "laptop";
 
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
 	pmic-glink {
 		compatible = "qcom,x1e80100-pmic-glink",
 			     "qcom,sm8550-pmic-glink",
@@ -328,6 +344,14 @@
 	};
 };
 
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn";
+	};
+};
+
 &i2c0 {
 	clock-frequency = <400000>;
 	status = "okay";
@@ -399,9 +423,13 @@
 
 	aux-bus {
 		panel {
-			compatible = "edp-panel";
+			compatible = "samsung,atna56ac03", "samsung,atna33xc20";
+			enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
 			power-supply = <&vreg_edp_3p3>;
 
+			pinctrl-0 = <&edp_bl_en>;
+			pinctrl-names = "default";
+
 			port {
 				edp_panel_in: endpoint {
 					remote-endpoint = <&mdss_dp3_out>;
@@ -467,6 +495,18 @@
 	status = "okay";
 };
 
+&pmc8380_3_gpios {
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio4";
+		function = "normal";
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+		bias-pull-down;
+		input-disable;
+		output-enable;
+	};
+};
+
 &qupv3_0 {
 	status = "okay";
 };
@@ -493,11 +533,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -515,6 +563,12 @@
 		bias-disable;
 	};
 
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
 	kybd_default: kybd-default-state {
 		pins = "gpio67";
 		function = "gpio";
@@ -591,7 +645,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -623,7 +677,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
index d51a9bdcf67..ff5b3472faf 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
@@ -932,11 +932,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -1187,7 +1195,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -1219,7 +1227,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -1251,7 +1259,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
index 05624226faf..86e87f03b0e 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
@@ -89,7 +89,15 @@
 					reg = <1>;
 
 					pmic_glink_ss0_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
 					};
 				};
 			};
@@ -118,7 +126,15 @@
 					reg = <1>;
 
 					pmic_glink_ss1_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
 					};
 				};
 			};
@@ -166,6 +182,102 @@
 		regulator-boot-on;
 	};
 
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
 	vreg_vph_pwr: regulator-vph-pwr {
 		compatible = "regulator-fixed";
 
@@ -492,9 +604,60 @@
 
 &i2c3 {
 	clock-frequency = <400000>;
-	status = "disabled";
-	/* PS8830 Retimer @0x8 */
-	/* Unknown device @0x9 */
+	status = "okay";
+
+	/* Right-side USB Type-C port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
 };
 
 &i2c5 {
@@ -505,9 +668,61 @@
 
 &i2c7 {
 	clock-frequency = <400000>;
-	status = "disabled";
-	/* PS8830 Retimer @0x8 */
-	/* Unknown device @0x9 */
+	status = "okay";
+
+	/* Left-side USB Type-C port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr1_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+
+		};
+	};
 };
 
 &i2c8 {
@@ -634,6 +849,36 @@
 	status = "okay";
 };
 
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+
+	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pmc8380_5_gpios {
+	rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pm8550ve_9_gpios {
+	rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &qupv3_0 {
 	status = "okay";
 };
@@ -660,11 +905,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -762,6 +1015,34 @@
 		};
 	};
 
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_default: rtmr1-reset-n-active-state {
+		pins = "gpio176";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
 	tpad_default: tpad-default-state {
 		disable-pins {
 			pins = "gpio38";
@@ -820,7 +1101,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p9>;
 
 	status = "okay";
@@ -839,7 +1120,7 @@
 };
 
 &usb_1_ss0_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+	remote-endpoint = <&retimer_ss0_ss_in>;
 };
 
 &usb_1_ss1_hsphy {
@@ -852,7 +1133,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -871,5 +1152,5 @@
 };
 
 &usb_1_ss1_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+	remote-endpoint = <&retimer_ss1_ss_in>;
 };
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts
new file mode 100644
index 00000000000..cd860a246c4
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts
@@ -0,0 +1,1693 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+	model = "HP Omnibook X 14";
+	compatible = "hp,omnibook-x14", "qcom,x1e80100";
+	chassis-type = "laptop";
+
+	aliases {
+		serial0 = &uart21;
+		serial1 = &uart14;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pmk8550_pwm 0 5000000>;
+
+		brightness-levels = <0 2048 4096 8192 16384 65535>;
+		num-interpolated-steps = <20>;
+		default-brightness-level = <80>;
+
+		enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+		power-supply = <&vreg_edp_bl>;
+
+		pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
+		pinctrl-names = "default";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Left-side port, closer to the screen */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Left-side port, farther from the screen */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-HP-OMNIBOOK-X14";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS3",
+				"VA DMIC1", "MIC BIAS3",
+				"VA DMIC2", "MIC BIAS1",
+				"VA DMIC3", "MIC BIAS1",
+				"VA DMIC0", "VA MIC BIAS3",
+				"VA DMIC1", "VA MIC BIAS3",
+				"VA DMIC2", "VA MIC BIAS1",
+				"VA DMIC3", "VA MIC BIAS1",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	vreg_edp_3p3: regulator-edp-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_EDP_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&edp_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_edp_bl: regulator-edp-bl {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VBL9";
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+
+		gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_bl_reg_en>;
+
+		regulator-boot-on;
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_MISC_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&misc_3p3_reg_en>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_NVME_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vreg_vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wcn_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	/*
+	 * TODO: These two regulators are actually part of the removable M.2
+	 * card and not the CRD mainboard. Need to describe this differently.
+	 * Functionally it works correctly, because all we need to do is to
+	 * turn on the actual 3.3V supply above.
+	 */
+	vreg_wcn_0p95: regulator-wcn-0p95 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_0P95";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+
+		vin-supply = <&vreg_wcn_3p3>;
+	};
+
+	vreg_wcn_1p9: regulator-wcn-1p9 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_1P9";
+		regulator-min-microvolt = <1900000>;
+		regulator-max-microvolt = <1900000>;
+
+		vin-supply = <&vreg_wcn_3p3>;
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		vddaon-supply = <&vreg_wcn_0p95>;
+		vddio-supply = <&vreg_wcn_1p9>;
+		vddpcie1p3-supply = <&vreg_wcn_1p9>;
+		vddpcie1p9-supply = <&vreg_wcn_1p9>;
+		vddpmu-supply = <&vreg_wcn_0p95>;
+		vddpmumx-supply = <&vreg_wcn_0p95>;
+		vddpmucx-supply = <&vreg_wcn_0p95>;
+		vddrfa0p95-supply = <&vreg_wcn_0p95>;
+		vddrfa1p3-supply = <&vreg_wcn_1p9>;
+		vddrfa1p9-supply = <&vreg_wcn_1p9>;
+
+		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&wcn_wlan_bt_en>;
+		pinctrl-names = "default";
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vreg_vph_pwr>;
+		vdd-bob2-supply = <&vreg_vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vreg_vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+		vdd-s2-supply = <&vreg_vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vreg_vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	keyboard@3a {
+		compatible = "hid-over-i2c";
+		reg = <0x3a>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l12b_1p2>;
+
+		pinctrl-0 = <&kybd_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+
+	touchpad@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l12b_1p2>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* type-c PS8830 Retimer #2 0x8 */
+	/* is active on Windows */
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* is active on Windows */
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+
+	};
+};
+
+&i2c7 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr1_default>;
+		pinctrl-names = "default";
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+
+		};
+	};
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen@10 {
+		compatible = "hid-over-i2c";
+		reg = <0x10>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l15b_1p8>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c9 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* is active on Windows */
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp3 {
+	compatible = "qcom,x1e80100-dp";
+	/delete-property/ #sound-dai-cells;
+
+	status = "okay";
+
+	aux-bus {
+		panel {
+			compatible = "edp-panel";
+			power-supply = <&vreg_edp_3p3>;
+
+			backlight = <&backlight>;
+
+			port {
+				edp_panel_in: endpoint {
+					remote-endpoint = <&mdss_dp3_out>;
+				};
+			};
+		};
+	};
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			mdss_dp3_out: endpoint {
+				data-lanes = <0 1 2 3>;
+				link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+				remote-endpoint = <&edp_panel_in>;
+			};
+		};
+	};
+};
+
+&mdss_dp3_phy {
+	vdda-phy-supply = <&vreg_l3j_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+	};
+};
+
+&pcie6a {
+	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie6a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie6a_phy {
+	vdda-phy-supply = <&vreg_l1d_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+
+	usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&pm8550ve_8_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-disable;
+		drive-push-pull;
+		input-disable;
+		output-enable;
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+	};
+};
+
+&pm8550ve_9_gpios {
+	usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&pmc8380_3_gpios {
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio4";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		input-disable;
+		output-enable;
+	};
+
+	edp_bl_reg_en: edp-bl-reg-en-state {
+		pins = "gpio10";
+		function = "normal";
+	};
+
+};
+
+&pmk8550_gpios {
+	edp_bl_pwm: edp-bl-pwm-state {
+		pins = "gpio5";
+		function = "func3";
+	};
+};
+
+&pmk8550_pwm {
+	status = "okay";
+};
+
+&pmc8380_5_gpios {
+	usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcadsp8380.mbn",
+			"qcom/x1e80100/hp/omnibook-x14/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/hp/omnibook-x14/qccdsp8380.mbn",
+			"qcom/x1e80100/hp/omnibook-x14/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l2b_3p0>;
+
+	status = "okay";
+};
+
+&smb2360_1_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l14b_3p0>;
+
+	status = "okay";
+};
+
+&swr0 {
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WSA8845, Left Speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right Speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <34 2>, /* Unused */
+			       <44 4>, /* SPI (TPM) */
+			       <72 2>, /* Secure EC I2C connection (?) */
+			       <238 1>; /* UFS Reset */
+
+	bt_en_default: bt-en-sleep {
+		pins = "gpio116";
+		function = "gpio";
+		output-low;
+		bias-disable;
+		drive-strength = <16>;
+	};
+
+	edp_reg_en: edp-reg-en-state {
+		pins = "gpio70";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
+	kybd_default: kybd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie6a_default: pcie6a-default-state {
+		clkreq-n-pins {
+			pins = "gpio153";
+			function = "pcie6a_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio152";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio154";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	rtmr1_default: rtmr1-reset-n-active-state {
+		pins = "gpio176";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tpad_default: tpad-default-state {
+		pins = "gpio3";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio51";
+			function = "gpio";
+			bias-pull-up;
+		};
+
+		reset-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			output-high;
+			drive-strength = <16>;
+		};
+	};
+
+	usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	wcn_sw_en: wcn-sw-en-state {
+		pins = "gpio214";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+		pins = "gpio116", "gpio117";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+		max-speed = <3200000>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+	};
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_0_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_1_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&retimer_ss1_ss_in>;
+};
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_dwc3 {
+	phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>;
+	phy-names = "usb2-0", "usb3-0";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
index ca5a808f2c7..a3d53f2ba2c 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 
 #include "x1e80100.dtsi"
@@ -23,6 +24,21 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
 	pmic-glink {
 		compatible = "qcom,x1e80100-pmic-glink",
 			     "qcom,sm8550-pmic-glink",
@@ -717,11 +733,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -811,6 +835,28 @@
 		bias-disable;
 	};
 
+	hall_int_n_default: hall-int-n-state {
+		lid-n-pins {
+			pins = "gpio92";
+			function = "gpio";
+			bias-disable;
+		};
+
+		/*
+		 * Pins 71 and 92 seem to be bridged together (pin 71 and 92 show the same
+		 * events). By default, pin 71 is set as output-high, which blocks any
+		 * event on pin 92. Output-disable on pin 71 is necessary to get events on
+		 * pin 92.
+		 * The purpose of pin 71 is not yet known; lid-pull is a supposition.
+		 */
+		lid-pull-n-pins {
+			pins = "gpio71";
+			function = "gpio";
+			bias-pull-up;
+			output-disable;
+		};
+	};
+
 	kybd_default: kybd-default-state {
 		pins = "gpio67";
 		function = "gpio";
@@ -908,7 +954,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -940,7 +986,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -972,7 +1018,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
index 6835fdeef3a..5867953c735 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
@@ -22,6 +22,33 @@
 		i2c7 = &i2c7;
 	};
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+
+		vdd-buck-supply = <&vreg_l15b>;
+		vdd-rxtx-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l15b>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		#sound-dai-cells = <1>;
+	};
+
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pmk8550_pwm 0 5000000>;
@@ -97,7 +124,15 @@
 					reg = <1>;
 
 					pmic_glink_ss0_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
 					};
 				};
 			};
@@ -126,7 +161,15 @@
 					reg = <1>;
 
 					pmic_glink_ss1_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
 					};
 				};
 			};
@@ -158,6 +201,109 @@
 		regulator-boot-on;
 	};
 
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+
 	vreg_nvme: regulator-nvme {
 		compatible = "regulator-fixed";
 
@@ -184,6 +330,86 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-Romulus";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS3",
+				"VA DMIC1", "MIC BIAS3",
+				"VA DMIC0", "VA MIC BIAS3",
+				"VA DMIC1", "VA MIC BIAS3",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>,
+					    <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -558,7 +784,59 @@
 
 	status = "okay";
 
-	/* PS8830 USB retimer @8 */
+	/* Left-side rear port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+
 };
 
 &i2c4 {
@@ -592,7 +870,74 @@
 
 	status = "okay";
 
-	/* PS8830 USB retimer @8 */
+	/* Left-side front port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	qcom,dmic-sample-rate = <4800000>;
+
+	vdd-micb-supply = <&vreg_l1b>;
+
+	pinctrl-0 = <&dmic01_default>;
+	pinctrl-names = "default";
 };
 
 &mdss {
@@ -641,6 +986,25 @@
 	status = "okay";
 };
 
+&pcie3 {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie3_default>;
+	pinctrl-names = "default";
+
+	/* The RTS5261 chip on the other side only does Gen1x1 anyway */
+	max-link-speed = <1>;
+	status = "okay";
+};
+
+&pcie3_phy {
+	vdda-phy-supply = <&vreg_l3c>;
+	vdda-pll-supply = <&vreg_l3e>;
+
+	status = "okay";
+};
+
 &pcie4 {
 	status = "okay";
 };
@@ -671,6 +1035,28 @@
 	status = "okay";
 };
 
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+
+	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pm8550ve_9_gpios {
+	rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmc8380_3_gpios {
 	edp_bl_en: edp-bl-en-state {
 		pins = "gpio4";
@@ -681,6 +1067,14 @@
 	};
 };
 
+&pmc8380_5_gpios {
+	rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmk8550_pwm {
 	status = "okay";
 };
@@ -706,23 +1100,31 @@
 
 &remoteproc_adsp {
 	firmware-name = "qcom/x1e80100/microsoft/Romulus/qcadsp8380.mbn",
-			"qcom/x1e80100/microsoft/Romulus/adsp_dtb.mbn";
+			"qcom/x1e80100/microsoft/Romulus/adsp_dtbs.elf";
 
 	status = "okay";
 };
 
 &remoteproc_cdsp {
 	firmware-name = "qcom/x1e80100/microsoft/Romulus/qccdsp8380.mbn",
-			"qcom/x1e80100/microsoft/Romulus/cdsp_dtb.mbn";
+			"qcom/x1e80100/microsoft/Romulus/cdsp_dtbs.elf";
 
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d>;
 	vdd3-supply = <&vreg_l2b>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d>;
 	vdd3-supply = <&vreg_l14b>;
@@ -737,6 +1139,59 @@
 	vdd3-supply = <&vreg_l8b>;
 };
 
+&swr0 {
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WSA8845, Left speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l12b>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l12b>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
 			       <238 1>; /* UFS Reset */
@@ -767,6 +1222,29 @@
 		bias-disable;
 	};
 
+	pcie3_default: pcie3-default-state {
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		clkreq-n-pins {
+			pins = "gpio144";
+			function = "pcie3_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-n-pins {
+			pins = "gpio145";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
 	pcie6a_default: pcie6a-default-state {
 		perst-n-pins {
 			pins = "gpio152";
@@ -790,6 +1268,35 @@
 		};
 	};
 
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
 	cam_indicator_en: cam-indicator-en-state {
 		pins = "gpio225";
 		function = "gpio";
@@ -823,7 +1330,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e>;
+	vdda-phy-supply = <&vreg_l2j>;
 	vdda-pll-supply = <&vreg_l1j>;
 
 	status = "okay";
@@ -842,7 +1349,7 @@
 };
 
 &usb_1_ss0_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+	remote-endpoint = <&retimer_ss0_ss_in>;
 };
 
 &usb_1_ss1_hsphy {
@@ -855,7 +1362,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e>;
+	vdda-phy-supply = <&vreg_l2j>;
 	vdda-pll-supply = <&vreg_l2d>;
 
 	status = "okay";
@@ -874,7 +1381,7 @@
 };
 
 &usb_1_ss1_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+	remote-endpoint = <&retimer_ss1_ss_in>;
 };
 
 /* MP0 goes to the Surface Connector, MP1 goes to the USB-A port */
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
index 5b54ee79f04..d7a2a2b8fc6 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
@@ -491,6 +491,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		status = "disabled";
+
 		smb2360_0_eusb2_repeater: phy@fd00 {
 			compatible = "qcom,smb2360-eusb2-repeater";
 			reg = <0xfd00>;
@@ -504,6 +506,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		status = "disabled";
+
 		smb2360_1_eusb2_repeater: phy@fd00 {
 			compatible = "qcom,smb2360-eusb2-repeater";
 			reg = <0xfd00>;
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
index 5ef030c60ab..ec594628304 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
@@ -84,6 +84,14 @@
 						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss0_sbu_mux>;
+					};
+				};
 			};
 		};
 
@@ -112,6 +120,14 @@
 						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss1_sbu_mux>;
+					};
+				};
 			};
 		};
 
@@ -140,6 +156,14 @@
 						remote-endpoint = <&usb_1_ss2_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss2_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss2_sbu_mux>;
+					};
+				};
 			};
 		};
 	};
@@ -256,6 +280,63 @@
 
 		regulator-boot-on;
 	};
+
+	usb-1-ss0-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss0_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss0_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss0_sbu>;
+			};
+		};
+	};
+
+	usb-1-ss1-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss1_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss1_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss1_sbu>;
+			};
+		};
+	};
+
+	usb-1-ss2-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 171 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 170 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss2_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss2_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss2_sbu>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -616,6 +697,40 @@
 	};
 };
 
+&i2c5 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb6_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb6_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
 &lpass_tlmm {
 	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
 		pins = "gpio12";
@@ -630,6 +745,30 @@
 	status = "okay";
 };
 
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	data-lanes = <0 1>;
+};
+
 &mdss_dp3 {
 	compatible = "qcom,x1e80100-dp";
 	/delete-property/ #sound-dai-cells;
@@ -731,11 +870,32 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l6b_1p8>;
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -819,6 +979,22 @@
 		bias-disable;
 	};
 
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb6_reset_n: eusb6-reset-n-state {
+		pins = "gpio184";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
 	nvme_reg_en: nvme-reg-en-state {
 		pins = "gpio18";
 		function = "gpio";
@@ -872,6 +1048,86 @@
 		};
 	};
 
+	sdc2_card_det_n: sdc2-card-det-state {
+		pins = "gpio71";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	usb_1_ss0_sbu_default: usb-1-ss0-sbu-state {
+		mode-pins {
+			pins = "gpio166";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio168";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio167";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+	};
+
+	usb_1_ss1_sbu_default: usb-1-ss1-sbu-state {
+		mode-pins {
+			pins = "gpio177";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio179";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio178";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+	};
+
+	usb_1_ss2_sbu_default: usb-1-ss2-sbu-state {
+		mode-pins {
+			pins = "gpio169";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio171";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio170";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+	};
+
 	wcd_default: wcd-reset-n-active-state {
 		pins = "gpio191";
 		function = "gpio";
@@ -896,7 +1152,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -928,7 +1184,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -960,7 +1216,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -981,3 +1237,39 @@
 &usb_1_ss2_qmpphy_out {
 	remote-endpoint = <&pmic_glink_ss2_ss_in>;
 };
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb6_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100.dtsi b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
index 7e4f46ad8ed..4936fa5b98f 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
@@ -38,7 +38,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 
@@ -303,6 +303,18 @@
 		};
 	};
 
+	dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&swao_rep_out1>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-x1e80100", "qcom,scm";
@@ -677,6 +689,34 @@
 		};
 	};
 
+	qup_opp_table_100mhz: opp-table-qup100mhz {
+		compatible = "operating-points-v2";
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+	};
+
+	qup_opp_table_120mhz: opp-table-qup120mhz {
+		compatible = "operating-points-v2";
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-120000000 {
+			opp-hz = /bits/ 64 <120000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+	};
+
 	smp2p-adsp {
 		compatible = "qcom,smp2p";
 
@@ -743,7 +783,7 @@
 
 			clocks = <&bi_tcxo_div2>,
 				 <&sleep_clk>,
-				 <0>,
+				 <&pcie3_phy>,
 				 <&pcie4_phy>,
 				 <&pcie5_phy>,
 				 <&pcie6a_phy>,
@@ -831,6 +871,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -864,6 +907,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -897,6 +943,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -930,6 +979,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -963,6 +1015,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -996,6 +1051,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1029,6 +1087,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1062,6 +1123,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1095,6 +1159,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1128,6 +1195,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1161,6 +1231,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1194,6 +1267,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1224,6 +1300,9 @@
 				interconnect-names = "qup-core",
 						     "qup-config";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				pinctrl-0 = <&qup_uart21_default>;
 				pinctrl-names = "default";
 
@@ -1249,6 +1328,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1282,6 +1364,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1315,6 +1400,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1348,6 +1436,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1425,6 +1516,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1458,6 +1552,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1491,6 +1588,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1524,6 +1624,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1557,6 +1660,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1590,6 +1696,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1623,6 +1732,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1656,6 +1768,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1689,6 +1804,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1722,6 +1840,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1755,6 +1876,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1788,6 +1912,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1821,6 +1948,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1854,6 +1984,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1868,6 +2001,31 @@
 				status = "disabled";
 			};
 
+			uart14: serial@a98000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a98000 0 0x4000>;
+
+				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
+				pinctrl-0 = <&qup_uart14_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+
 			i2c15: i2c@a9c000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x00a9c000 0 0x4000>;
@@ -1887,6 +2045,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1920,6 +2081,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1996,6 +2160,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2029,6 +2196,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2062,6 +2232,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2095,6 +2268,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2128,6 +2304,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2158,6 +2337,9 @@
 				interconnect-names = "qup-core",
 						     "qup-config";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				pinctrl-0 = <&qup_uart2_default>;
 				pinctrl-names = "default";
 
@@ -2183,6 +2365,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2216,6 +2401,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2249,6 +2437,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2282,6 +2473,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2315,6 +2509,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2348,6 +2545,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2381,6 +2581,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2414,6 +2617,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2447,6 +2653,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2480,6 +2689,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2513,6 +2725,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2906,6 +3121,208 @@
 			#interconnect-cells = <2>;
 		};
 
+		pcie3: pcie@1bd0000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-x1e80100";
+			reg = <0x0 0x01bd0000 0x0 0x3000>,
+			      <0x0 0x78000000 0x0 0xf1d>,
+			      <0x0 0x78000f40 0x0 0xa8>,
+			      <0x0 0x78001000 0x0 0x1000>,
+			      <0x0 0x78100000 0x0 0x100000>,
+			      <0x0 0x01bd3000 0x0 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
+				 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <3>;
+			num-lanes = <8>;
+
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
+				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "noc_aggr",
+				      "cnoc_sf_axi";
+
+			assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			resets = <&gcc GCC_PCIE_3_BCR>,
+				 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
+			reset-names = "pci",
+				      "link_down";
+
+			power-domains = <&gcc GCC_PCIE_3_GDSC>;
+
+			phys = <&pcie3_phy>;
+			phy-names = "pciephy";
+
+			operating-points-v2 = <&pcie3_opp_table>;
+
+			status = "disabled";
+
+			pcie3_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/* GEN 1 x1 */
+				opp-2500000 {
+					opp-hz = /bits/ 64 <2500000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <250000 1>;
+				};
+
+				/* GEN 1 x2 and GEN 2 x1 */
+				opp-5000000 {
+					opp-hz = /bits/ 64 <5000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 1>;
+				};
+
+				/* GEN 1 x4 and GEN 2 x2 */
+				opp-10000000 {
+					opp-hz = /bits/ 64 <10000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <1000000 1>;
+				};
+
+				/* GEN 1 x8 and GEN 2 x4 */
+				opp-20000000 {
+					opp-hz = /bits/ 64 <20000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <2000000 1>;
+				};
+
+				/* GEN 2 x8 */
+				opp-40000000 {
+					opp-hz = /bits/ 64 <40000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <4000000 1>;
+				};
+
+				/* GEN 3 x1 */
+				opp-8000000 {
+					opp-hz = /bits/ 64 <8000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <984500 1>;
+				};
+
+				/* GEN 3 x2 and GEN 4 x1 */
+				opp-16000000 {
+					opp-hz = /bits/ 64 <16000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <1969000 1>;
+				};
+
+				/* GEN 3 x4 and GEN 4 x2 */
+				opp-32000000 {
+					opp-hz = /bits/ 64 <32000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <3938000 1>;
+				};
+
+				/* GEN 3 x8 and GEN 4 x4 */
+				opp-64000000 {
+					opp-hz = /bits/ 64 <64000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <7876000 1>;
+				};
+
+				/* GEN 4 x8 */
+				opp-128000000 {
+					opp-hz = /bits/ 64 <128000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <15753000 1>;
+				};
+			};
+		};
+
+		pcie3_phy: phy@1be0000 {
+			compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
+			reg = <0 0x01be0000 0 0x10000>;
+
+			clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
+				 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_3_PIPE_CLK>,
+				 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe",
+				      "pipediv2";
+
+			resets = <&gcc GCC_PCIE_3_PHY_BCR>,
+				 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_nocsr";
+
+			assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie3_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		pcie6a: pci@1bf8000 {
 			device_type = "pci";
 			compatible = "qcom,pcie-x1e80100";
@@ -3518,6 +3935,143 @@
 			#interconnect-cells = <2>;
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,x1e80100-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&adspslpi_mem>,
+					<&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1063 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1064 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1065 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1066 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x1007 0x80>,
+							 <&apps_smmu 0x1067 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -3892,6 +4446,112 @@
 			#interconnect-cells = <2>;
 		};
 
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08804000 0 0x1000>;
+
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0x520 0>;
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+
+			interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+			bus-width = <4>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
+		sdhc_4: mmc@8844000 {
+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08844000 0 0x1000>;
+
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC4_AHB_CLK>,
+				 <&gcc GCC_SDCC4_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0x160 0>;
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc4_opp_table>;
+
+			interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+			bus-width = <4>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc4_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
 		usb_2_hsphy: phy@88e0000 {
 			compatible = "qcom,x1e80100-snps-eusb2-phy",
 				     "qcom,sm8550-snps-eusb2-phy";
@@ -4063,6 +4723,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4118,7 +4780,7 @@
 					  <&gcc GCC_USB20_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <200000000>;
 
-			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
 			interrupt-names = "pwr_event",
@@ -4144,11 +4806,13 @@
 			usb_2_dwc3: usb@a200000 {
 				compatible = "snps,dwc3";
 				reg = <0 0x0a200000 0 0xcd00>;
-				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 				iommus = <&apps_smmu 0x14e0 0x0>;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -4245,6 +4909,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 			};
@@ -4316,6 +4982,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4414,6 +5082,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -5629,6 +6299,34 @@
 				};
 			};
 
+			qup_uart14_default: qup-uart14-default-state {
+				cts-pins {
+					pins = "gpio56";
+					function = "qup1_se6";
+					bias-bus-hold;
+				};
+
+				rts-pins {
+					pins = "gpio57";
+					function = "qup1_se6";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				tx-pins {
+					pins = "gpio58";
+					function = "qup1_se6";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				rx-pins {
+					pins = "gpio59";
+					function = "qup1_se6";
+					bias-pull-up;
+				};
+			};
+
 			qup_uart21_default: qup-uart21-default-state {
 				tx-pins {
 					pins = "gpio86";
@@ -5644,6 +6342,1487 @@
 					bias-disable;
 				};
 			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		stm@10002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x10002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@10003000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10003000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					dcc_tpdm_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpda@10004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_tpda_in0: endpoint {
+						remote-endpoint = <&dcc_tpdm_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_tpda_in1: endpoint {
+						remote-endpoint = <&qdss_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_tpda_out: endpoint {
+						remote-endpoint = <&funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@1000f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x1000f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					qdss_tpdm_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel0_in6: endpoint {
+						remote-endpoint = <&qdss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@2 {
+					reg = <2>;
+
+					funnel1_in2: endpoint {
+						remote-endpoint = <&tmess_funnel_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel1_in5: endpoint {
+						remote-endpoint = <&dlst_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel1_in6: endpoint {
+						remote-endpoint = <&dlct1_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_funnel_in0: endpoint {
+						remote-endpoint = <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_funnel_in1: endpoint {
+						remote-endpoint = <&funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@10800000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					mxa_tpdm_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in15>;
+					};
+				};
+			};
+		};
+
+		tpdm@1082c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x1082c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					gcc_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in21>;
+					};
+				};
+			};
+		};
+
+		tpdm@10841000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10841000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					prng_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in19>;
+					};
+				};
+			};
+		};
+
+		tpdm@10844000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10844000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					lpass_cx_tpdm_out: endpoint {
+						remote-endpoint = <&lpass_cx_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10846000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10846000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					lpass_cx_funnel_in0: endpoint {
+						remote-endpoint = <&lpass_cx_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					lpass_cx_funnel_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		cti@1098b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x1098b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@109d0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x109d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					qm_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in20>;
+					};
+				};
+			};
+		};
+
+		tpdm@10ac0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10ac0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					dlst_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpdm@10ac1000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10ac1000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_tpdm1_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in9>;
+					};
+				};
+			};
+		};
+
+		tpda@10ac4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10ac4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_tpdm0_out>;
+					};
+				};
+
+				port@9 {
+					reg = <9>;
+
+					dlst_tpda_in9: endpoint {
+						remote-endpoint = <&dlst_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_tpda_out: endpoint {
+						remote-endpoint = <&dlst_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10ac5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10ac5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlst_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in5>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@3 {
+					reg = <3>;
+
+					aoss_funnel_in3: endpoint {
+						remote-endpoint = <&ddr_lpi_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					aoss_funnel_in6: endpoint {
+						remote-endpoint = <&aoss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					aoss_funnel_in7: endpoint {
+						remote-endpoint = <&qdss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_funnel_out: endpoint {
+						remote-endpoint = <&etf0_in>;
+					};
+				};
+			};
+		};
+
+		etf0: tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etf0_in: endpoint {
+						remote-endpoint = <&aoss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf0_out: endpoint {
+						remote-endpoint = <&swao_rep_in>;
+					};
+				};
+			};
+		};
+
+		replicator@10b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					swao_rep_in: endpoint {
+						remote-endpoint = <&etf0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					swao_rep_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		tpda@10b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					aoss_tpda_in0: endpoint {
+						remote-endpoint = <&aoss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					aoss_tpda_in1: endpoint {
+						remote-endpoint = <&aoss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					aoss_tpda_in2: endpoint {
+						remote-endpoint = <&aoss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					aoss_tpda_in3: endpoint {
+						remote-endpoint = <&aoss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					aoss_tpda_in4: endpoint {
+						remote-endpoint = <&aoss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_tpda_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm0_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm1_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm2_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm3_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm4_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b20000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					lpicc_tpdm_out: endpoint {
+						remote-endpoint = <&ddr_lpi_tpda_in>;
+					};
+				};
+			};
+		};
+
+		tpda@10b23000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10b23000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+
+			in-ports {
+				port {
+					ddr_lpi_tpda_in: endpoint {
+						remote-endpoint = <&lpicc_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_lpi_tpda_out: endpoint {
+						remote-endpoint = <&ddr_lpi_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10b24000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10b24000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+
+			in-ports {
+				port {
+					ddr_lpi_funnel_in0: endpoint {
+						remote-endpoint = <&ddr_lpi_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_lpi_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c08000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					mm_tpdm_out: endpoint {
+						remote-endpoint = <&mm_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		funnel@10c0b000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					mm_funnel_in4: endpoint {
+						remote-endpoint = <&mm_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					mm_funnel_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct1_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in26>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c29000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ipcc_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in27>;
+					};
+				};
+			};
+		};
+
+		tpda@10c2b000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c2b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					dlct1_tpda_in4: endpoint {
+						remote-endpoint = <&lpass_cx_funnel_out>;
+					};
+				};
+
+				port@13 {
+					reg = <19>;
+
+					dlct1_tpda_in19: endpoint {
+						remote-endpoint = <&prng_tpdm_out>;
+					};
+				};
+
+				port@14 {
+					reg = <20>;
+
+					dlct1_tpda_in20: endpoint {
+						remote-endpoint = <&qm_tpdm_out>;
+					};
+				};
+
+				port@15 {
+					reg = <21>;
+
+					dlct1_tpda_in21: endpoint {
+						remote-endpoint = <&gcc_tpdm_out>;
+					};
+				};
+
+				port@1a {
+					reg = <26>;
+
+					dlct1_tpda_in26: endpoint {
+						remote-endpoint = <&dlct1_tpdm_out>;
+					};
+				};
+
+				port@1b {
+					reg = <27>;
+
+					dlct1_tpda_in27: endpoint {
+						remote-endpoint = <&ipcc_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct1_tpda_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10c2c000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c2c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlct1_funnel_in0: endpoint {
+						remote-endpoint = <&dlct1_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlct1_funnel_in4: endpoint {
+						remote-endpoint = <&dlct2_funnel_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					dlct1_funnel_in5: endpoint {
+						remote-endpoint = <&ddr_funnel0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct1_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c38000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c38000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct2_tpdm0_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in16>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c39000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c39000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct2_tpdm1_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in17>;
+					};
+				};
+			};
+		};
+
+		tpda@10c3c000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c3c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					dlct2_tpda_in4: endpoint {
+						remote-endpoint = <&mm_funnel_out>;
+					};
+				};
+
+				port@f {
+					reg = <15>;
+
+					dlct2_tpda_in15: endpoint {
+						remote-endpoint = <&mxa_tpdm_out>;
+					};
+				};
+
+				port@10 {
+					reg = <16>;
+
+					dlct2_tpda_in16: endpoint {
+						remote-endpoint = <&dlct2_tpdm0_out>;
+					};
+				};
+
+				port@11 {
+					reg = <17>;
+
+					dlct2_tpda_in17: endpoint {
+						remote-endpoint = <&dlct2_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct2_tpda_out: endpoint {
+						remote-endpoint = <&dlct2_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10c3d000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c3d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlct2_funnel_in0: endpoint {
+						remote-endpoint = <&dlct2_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct2_funnel_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10cc1000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10cc1000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tmess_tpdm1_out: endpoint {
+						remote-endpoint = <&tmess_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpda@10cc4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10cc4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@2 {
+					reg = <2>;
+
+					tmess_tpda_in2: endpoint {
+						remote-endpoint = <&tmess_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmess_tpda_out: endpoint {
+						remote-endpoint = <&tmess_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10cc5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10cc5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmess_funnel_in0: endpoint {
+						remote-endpoint = <&tmess_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmess_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in2>;
+					};
+				};
+			};
+		};
+
+		funnel@10d04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10d04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					ddr_funnel0_in6: endpoint {
+						remote-endpoint = <&ddr_funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel0_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d08000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc0_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc1_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc2_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc3_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc4_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc5_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0e000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc6_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc7_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@10d12000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10d12000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					llcc_tpda_in0: endpoint {
+						remote-endpoint = <&llcc0_tpdm_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					llcc_tpda_in1: endpoint {
+						remote-endpoint = <&llcc1_tpdm_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					llcc_tpda_in2: endpoint {
+						remote-endpoint = <&llcc2_tpdm_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					llcc_tpda_in3: endpoint {
+						remote-endpoint = <&llcc3_tpdm_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					llcc_tpda_in4: endpoint {
+						remote-endpoint = <&llcc4_tpdm_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					llcc_tpda_in5: endpoint {
+						remote-endpoint = <&llcc5_tpdm_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					llcc_tpda_in6: endpoint {
+						remote-endpoint = <&llcc6_tpdm_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					llcc_tpda_in7: endpoint {
+						remote-endpoint = <&llcc7_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					llcc_tpda_out: endpoint {
+						remote-endpoint = <&ddr_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10d13000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10d13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel1_in0: endpoint {
+						remote-endpoint = <&llcc_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel1_out: endpoint {
+						remote-endpoint = <&ddr_funnel0_in6>;
+					};
+				};
+			};
 		};
 
 		apps_smmu: iommu@15000000 {
@@ -6111,146 +8290,9 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,x1e80100-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog",
-					  "fatal",
-					  "ready",
-					  "handover",
-					  "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx",
-					     "lmx";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
-					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
-			memory-region = <&adspslpi_mem>,
-					<&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1063 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1064 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1065 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1066 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x1007 0x80>,
-							 <&apps_smmu 0x1067 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,x1e80100-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
index e11bf9ace77..2a8537e1387 100644
--- a/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
@@ -5,6 +5,121 @@
  * Copyright (C) 2021 Glider bv
  */
 
+/ {
+	aliases {
+		ethernet1 = &avb1;
+		ethernet2 = &avb2;
+		ethernet3 = &avb3;
+		ethernet4 = &avb4;
+		ethernet5 = &avb5;
+	};
+};
+
+&avb1 {
+	pinctrl-0 = <&avb1_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb1_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb1_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb2 {
+	pinctrl-0 = <&avb2_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb2_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb2_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb3 {
+	pinctrl-0 = <&avb3_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb3_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb3_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb4 {
+	pinctrl-0 = <&avb4_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb4_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb4_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb5 {
+	pinctrl-0 = <&avb5_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb5_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb5_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
 &i2c0 {
 	eeprom@53 {
 		compatible = "rohm,br24g01", "atmel,24c01";
@@ -13,3 +128,130 @@
 		pagesize = <8>;
 	};
 };
+
+&pfc {
+	avb1_pins: avb1 {
+		mux {
+			groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
+				 "avb1_txcrefclk";
+			function = "avb1";
+		};
+
+		link {
+			groups = "avb1_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb1_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb1_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb2_pins: avb2 {
+		mux {
+			groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
+				 "avb2_txcrefclk";
+			function = "avb2";
+		};
+
+		link {
+			groups = "avb2_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb2_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb2_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb3_pins: avb3 {
+		mux {
+			groups = "avb3_link", "avb3_mdio", "avb3_rgmii",
+				 "avb3_txcrefclk";
+			function = "avb3";
+		};
+
+		link {
+			groups = "avb3_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb3_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb3_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb4_pins: avb4 {
+		mux {
+			groups = "avb4_link", "avb4_mdio", "avb4_rgmii",
+				 "avb4_txcrefclk";
+			function = "avb4";
+		};
+
+		link {
+			groups = "avb4_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb4_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb4_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb5_pins: avb5 {
+		mux {
+			groups = "avb5_link", "avb5_mdio", "avb5_rgmii",
+				 "avb5_txcrefclk";
+			function = "avb5";
+		};
+
+		link {
+			groups = "avb5_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb5_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb5_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
index 7156b1a542e..fe6d97859e4 100644
--- a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
@@ -765,8 +765,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -814,8 +812,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 2>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -863,8 +859,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 3>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -912,8 +906,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -961,8 +953,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 11>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
index 61c6b8022ff..104f740d20d 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
@@ -2453,6 +2453,46 @@
 			};
 		};
 
+		fcpvx0: fcp@fedb0000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb0000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1100>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1100>;
+			iommus = <&ipmmu_vi1 24>;
+		};
+
+		fcpvx1: fcp@fedb8000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb8000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1101>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1101>;
+			iommus = <&ipmmu_vi1 25>;
+		};
+
+		vspx0: vsp@fedd0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd0000 0 0x8000>;
+			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1028>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1028>;
+
+			renesas,fcp = <&fcpvx0>;
+		};
+
+		vspx1: vsp@fedd8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd8000 0 0x8000>;
+			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1029>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1029>;
+
+			renesas,fcp = <&fcpvx1>;
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
diff --git a/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
index 0062362b0ba..48befde3893 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
@@ -7,70 +7,10 @@
 
 /dts-v1/;
 #include "r8a779g2.dtsi"
-#include "white-hawk-cpu-common.dtsi"
-#include "white-hawk-common.dtsi"
+#include "white-hawk-single.dtsi"
 
 / {
 	model = "Renesas White Hawk Single board based on r8a779g2";
 	compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
 		     "renesas,r8a779g0";
 };
-
-&hscif0 {
-	uart-has-rtscts;
-};
-
-&hscif0_pins {
-	groups = "hscif0_data", "hscif0_ctrl";
-	function = "hscif0";
-};
-
-&pfc {
-	tsn0_pins: tsn0 {
-		mux {
-			groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii",
-				 "tsn0_txcrefclk";
-			function = "tsn0";
-		};
-
-		link {
-			groups = "tsn0_link";
-			bias-disable;
-		};
-
-		mdio {
-			groups = "tsn0_mdio";
-			drive-strength = <24>;
-			bias-disable;
-		};
-
-		rgmii {
-			groups = "tsn0_rgmii";
-			drive-strength = <24>;
-			bias-disable;
-		};
-	};
-};
-
-&tsn0 {
-	pinctrl-0 = <&tsn0_pins>;
-	pinctrl-names = "default";
-	phy-mode = "rgmii";
-	phy-handle = <&phy3>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
-		reset-post-delay-us = <4000>;
-
-		phy3: ethernet-phy@0 {
-			compatible = "ethernet-phy-id002b.0980",
-				     "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>;
-		};
-	};
-};
diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts
new file mode 100644
index 00000000000..cd466d85885
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H ES3.0 White Hawk Single board
+ *
+ * Copyright (C) 2024 Glider bv
+ */
+
+/dts-v1/;
+#include "r8a779g3.dtsi"
+#include "white-hawk-single.dtsi"
+
+/ {
+	model = "Renesas White Hawk Single board based on r8a779g3";
+	compatible = "renesas,white-hawk-single", "renesas,r8a779g3",
+		     "renesas,r8a779g0";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779g3.dtsi b/dts/upstream/src/arm64/renesas/r8a779g3.dtsi
new file mode 100644
index 00000000000..0295858a026
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r8a779g3.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G3) SoC
+ *
+ * Copyright (C) 2024 Glider bv
+ */
+
+#include "r8a779g0.dtsi"
+
+/ {
+	compatible = "renesas,r8a779g3", "renesas,r8a779g0";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
index 58eabcc7e0e..18fd52f55de 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
@@ -30,6 +30,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
 
 #include "r8a779h0.dtsi"
 
@@ -59,6 +60,12 @@
 		stdout-path = "serial0:921600n8";
 	};
 
+	sn65dsi86_refclk: clk-x6 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <38400000>;
+	};
+
 	keys {
 		compatible = "gpio-keys";
 
@@ -132,22 +139,43 @@
 		#clock-cells = <0>;
 	};
 
+	mini-dp-con {
+		compatible = "dp-connector";
+		label = "CN5";
+		type = "mini";
+
+		port {
+			mini_dp_con_in: endpoint {
+				remote-endpoint = <&sn65dsi86_out0>;
+			};
+		};
+	};
+
+	reg_1p2v: regulator-1p2v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.2V";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	reg_1p8v: regulator-1p8v {
-			compatible = "regulator-fixed";
-			regulator-name = "fixed-1.8V";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-			regulator-boot-on;
-			regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	reg_3p3v: regulator-3p3v {
-			compatible = "regulator-fixed";
-			regulator-name = "fixed-3.3V";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-boot-on;
-			regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	sound_mux: sound-mux {
@@ -205,6 +233,65 @@
 	};
 };
 
+&dsi0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&sn65dsi86_in0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&du {
+	status = "okay";
+};
+
+&csi40 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			csi40_in: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&max96724_out0>;
+			};
+		};
+	};
+};
+
+&csi41 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			csi41_in: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&max96724_out1>;
+			};
+		};
+	};
+};
+
 &extal_clk {
 	clock-frequency = <16666666>;
 };
@@ -255,6 +342,20 @@
 		#interrupt-cells = <2>;
 	};
 
+	io_expander_b: gpio@21 {
+		compatible = "onnn,pca9654";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	io_expander_c: gpio@22 {
+		compatible = "onnn,pca9654";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	eeprom@50 {
 		compatible = "rohm,br24g01", "atmel,24c01";
 		label = "cpu-board";
@@ -284,6 +385,97 @@
 	};
 };
 
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	bridge@2c {
+		pinctrl-0 = <&irq0_pins>;
+		pinctrl-names = "default";
+
+		compatible = "ti,sn65dsi86";
+		reg = <0x2c>;
+
+		clocks = <&sn65dsi86_refclk>;
+		clock-names = "refclk";
+
+		interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
+
+		enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+		vccio-supply = <&reg_1p8v>;
+		vpll-supply = <&reg_1p8v>;
+		vcca-supply = <&reg_1p2v>;
+		vcc-supply = <&reg_1p2v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				sn65dsi86_in0: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				sn65dsi86_out0: endpoint {
+					remote-endpoint = <&mini_dp_con_in>;
+				};
+			};
+		};
+	};
+
+	gmsl0: gmsl-deserializer@4e {
+		compatible = "maxim,max96724";
+		reg = <0x4e>;
+		enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@4 {
+				reg = <4>;
+				max96724_out0: endpoint {
+					bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi40_in>;
+				};
+			};
+		};
+	};
+
+	gmsl1: gmsl-deserializer@4f {
+		compatible = "maxim,max96724";
+		reg = <0x4f>;
+		enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@4 {
+				reg = <4>;
+				max96724_out1: endpoint {
+					bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi41_in>;
+				};
+			};
+		};
+	};
+};
+
 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
@@ -307,6 +499,14 @@
 	};
 };
 
+&isp0 {
+	status = "okay";
+};
+
+&isp1 {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-0 = <&mmc_pins>;
 	pinctrl-1 = <&mmc_pins>;
@@ -388,11 +588,21 @@
 		function = "i2c0";
 	};
 
+	i2c1_pins: i2c1 {
+		groups = "i2c1";
+		function = "i2c1";
+	};
+
 	i2c3_pins: i2c3 {
 		groups = "i2c3";
 		function = "i2c3";
 	};
 
+	irq0_pins: irq0_pins {
+		groups = "intc_ex_irq0_a";
+		function = "intc_ex";
+	};
+
 	keys_pins: keys {
 		pins = "GP_5_0", "GP_5_1", "GP_5_2";
 		bias-pull-up;
@@ -494,3 +704,67 @@
 &scif_clk2 {
 	clock-frequency = <24000000>;
 };
+
+&vin00 {
+	status = "okay";
+};
+
+&vin01 {
+	status = "okay";
+};
+
+&vin02 {
+	status = "okay";
+};
+
+&vin03 {
+	status = "okay";
+};
+
+&vin04 {
+	status = "okay";
+};
+
+&vin05 {
+	status = "okay";
+};
+
+&vin06 {
+	status = "okay";
+};
+
+&vin07 {
+	status = "okay";
+};
+
+&vin08 {
+	status = "okay";
+};
+
+&vin09 {
+	status = "okay";
+};
+
+&vin10 {
+	status = "okay";
+};
+
+&vin11 {
+	status = "okay";
+};
+
+&vin12 {
+	status = "okay";
+};
+
+&vin13 {
+	status = "okay";
+};
+
+&vin14 {
+	status = "okay";
+};
+
+&vin15 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
index facfff4b9cd..d0c01c0fdda 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
@@ -1900,6 +1900,50 @@
 			};
 		};
 
+		fcpvd0: fcp@fea10000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea10000 0 0x200>;
+			clocks = <&cpg CPG_MOD 508>;
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 508>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x8000>;
+			interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 830>;
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 830>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a779h0";
+			reg = <0 0xfeb00000 0 0x40000>;
+			interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 411>;
+			clock-names = "du.0";
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 411>;
+			reset-names = "du.0";
+			renesas,vsps = <&vspd0 0>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_dsi0: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+			};
+		};
+
 		isp0: isp@fed00000 {
 			compatible = "renesas,r8a779h0-isp",
 				     "renesas,rcar-gen4-isp";
@@ -2068,6 +2112,35 @@
 			};
 		};
 
+		dsi0: dsi-encoder@fed80000 {
+			compatible = "renesas,r8a779h0-dsi-csi2-tx";
+			reg = <0 0xfed80000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 415>,
+				 <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>,
+				 <&cpg CPG_CORE R8A779H0_CLK_DSIREF>;
+			clock-names = "fck", "dsi", "pll";
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 415>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi0_in: endpoint {
+						remote-endpoint = <&du_out_dsi0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
diff --git a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
index be8a0a768c6..a9b98db9ef9 100644
--- a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
@@ -14,6 +14,20 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	audio_clk1: audio1-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
+	audio_clk2: audio2-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -73,6 +87,96 @@
 			status = "disabled";
 		};
 
+		scif1: serial@1004bc00 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004bc00 0 0x400>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif2: serial@1004c000 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c000 0 0x400>;
+			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif3: serial@1004c400 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c400 0 0x400>;
+			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif4: serial@1004c800 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c800 0 0x400>;
+			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif5: serial@1004e000 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004e000 0 0x400>;
+			interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
 		rtc: rtc@1004ec00 {
 			compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
 			reg = <0 0x1004ec00 0 0x400>;
@@ -87,6 +191,59 @@
 			status = "disabled";
 		};
 
+		adc: adc@10058000 {
+			compatible = "renesas,r9a08g045-adc";
+			reg = <0 0x10058000 0 0x1000>;
+			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
+				 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A08G045_ADC_PRESETN>,
+				 <&cpg R9A08G045_ADC_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			channel@0 {
+				reg = <0>;
+			};
+
+			channel@1 {
+				reg = <1>;
+			};
+
+			channel@2 {
+				reg = <2>;
+			};
+
+			channel@3 {
+				reg = <3>;
+			};
+
+			channel@4 {
+				reg = <4>;
+			};
+
+			channel@5 {
+				reg = <5>;
+			};
+
+			channel@6 {
+				reg = <6>;
+			};
+
+			channel@7 {
+				reg = <7>;
+			};
+
+			channel@8 {
+				reg = <8>;
+			};
+		};
+
 		vbattb: clock-controller@1005c000 {
 			compatible = "renesas,r9a08g045-vbattb";
 			reg = <0 0x1005c000 0 0x1000>;
@@ -187,6 +344,86 @@
 			status = "disabled";
 		};
 
+		ssi0: ssi@100a8000 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8000 0 0x400>;
+			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
+			dmas = <&dmac 0x2665>, <&dmac 0x2666>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi1: ssi@100a8400 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8400 0 0x400>;
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
+			dmas = <&dmac 0x2669>, <&dmac 0x266a>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi2: ssi@100a8800 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8800 0 0x400>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
+			dmas = <&dmac 0x266d>, <&dmac 0x266e>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi3: ssi@100a8c00 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8c00 0 0x400>;
+			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
+			dmas = <&dmac 0x2671>, <&dmac 0x2672>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a08g045-cpg";
 			reg = <0 0x11010000 0 0x10000>;
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi
new file mode 100644
index 00000000000..200e9ea8919
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g047";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_extal_clk: audio-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/*
+	 * The default cluster table is based on the assumption that the PLLCA55 clock
+	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+	 * clocked to 1.8GHz as well). The table below should be overridden in the board
+	 * DTS based on the PLLCA55 clock frequency.
+	 */
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-212500000 {
+			opp-hz = /bits/ 64 <212500000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	qextal_clk: qextal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	rtxin_clk: rtxin-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		pinctrl: pinctrl@10410000 {
+			compatible = "renesas,r9a09g047-pinctrl";
+			reg = <0 0x10410000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 232>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xa5>, <&cpg 0xa6>;
+		};
+
+		cpg: clock-controller@10420000 {
+			compatible = "renesas,r9a09g047-cpg";
+			reg = <0 0x10420000 0 0x10000>;
+			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+			clock-names = "audio_extal", "rtxin", "qextal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		scif0: serial@11c01400 {
+			compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
+			reg = <0 0x11c01400 0 0x400>;
+			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+					  "tei", "tei-dri", "rxi-edge", "txi-edge";
+			clocks = <&cpg CPG_MOD 0x8f>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x95>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@14400400 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400400 0 0x400>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x94>;
+			resets = <&cpg 0x98>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@14400800 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400800 0 0x400>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x95>;
+			resets = <&cpg 0x99>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@14400c00 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400c00 0 0x400>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x96>;
+			resets = <&cpg 0x9a>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@14401000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401000 0 0x400>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x97>;
+			resets = <&cpg 0x9b>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@14401400 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401400 0 0x400>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x98>;
+			resets = <&cpg 0x9c>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@14401800 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401800 0 0x400>;
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x99>;
+			resets = <&cpg 0x9d>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@14401c00 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401c00 0 0x400>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x9a>;
+			resets = <&cpg 0x9e>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@14402000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14402000 0 0x400>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x9b>;
+			resets = <&cpg 0x9f>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c8: i2c@11c01000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x11c01000 0 0x400>;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x93>;
+			resets = <&cpg 0xa0>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@14900000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x14900000 0 0x20000>,
+			      <0x0 0x14940000 0 0x80000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi
new file mode 100644
index 00000000000..e50d9159e83
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";
+
+	cpus {
+		/delete-node/ cpu@200;
+		/delete-node/ cpu@300;
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts b/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts
new file mode 100644
index 00000000000..c063d47e295
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SMARC EVK board
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
+#include "r9a09g047e57.dtsi"
+#include "rzg3e-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
+	compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
+		     "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
+
+&pinctrl {
+	scif_pins: scif {
+		pins = "SCIF_TXD", "SCIF_RXD";
+		renesas,output-impedance = <1>;
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif_pins>;
+	pinctrl-names = "default";
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi
new file mode 100644
index 00000000000..98a5faebd47
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
index 4703da8e9cf..0b705c987b6 100644
--- a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -7,7 +7,7 @@
 
 /dts-v1/;
 
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
 #include <dt-bindings/gpio/gpio.h>
 #include "r9a09g057.dtsi"
 
@@ -56,7 +56,7 @@
 	vqmmc_sdhi1: regulator-vccq-sdhi1 {
 		compatible = "regulator-gpio";
 		regulator-name = "SDHI1 VccQ";
-		gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
+		gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <3300000>;
 		gpios-states = <0>;
@@ -158,38 +158,38 @@
 
 &pinctrl {
 	i2c0_pins: i2c0 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
-			 <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
+			 <RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
 	};
 
 	i2c1_pins: i2c1 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
-			 <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
+			 <RZV2H_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
 	};
 
 	i2c2_pins: i2c2 {
-		pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
-			 <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
+			 <RZV2H_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
 	};
 
 	i2c3_pins: i2c3 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
-			 <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
+			 <RZV2H_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
 	};
 
 	i2c6_pins: i2c6 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
-			 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
+			 <RZV2H_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
 	};
 
 	i2c7_pins: i2c7 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
-			 <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
+			 <RZV2H_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
 	};
 
 	i2c8_pins: i2c8 {
-		pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
-			 <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
+			 <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
 	};
 
 	scif_pins: scif {
@@ -199,7 +199,7 @@
 
 	sd1-pwr-en-hog {
 		gpio-hog;
-		gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
+		gpios = <RZV2H_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
 		output-high;
 		line-name = "sd1_pwr_en";
 	};
@@ -219,7 +219,7 @@
 		};
 
 		sd1_cd {
-			pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
+			pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
 		};
 	};
 };
diff --git a/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi b/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi
new file mode 100644
index 00000000000..e378d55e6e9
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ SMARC Carrier-II Board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	model = "Renesas RZ SMARC Carrier-II Board";
+	compatible = "renesas,smarc2-evk";
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial3:115200n8";
+	};
+
+	aliases {
+		serial3 = &scif0;
+	};
+};
+
+&scif0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi
new file mode 100644
index 00000000000..6b583ae2ac5
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R9A09G047E57 SMARC SoM board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* First 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0xf8000000>;
+	};
+};
+
+&audio_extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&qextal_clk {
+	clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+	clock-frequency = <32768>;
+};
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
index 2ed01d39155..ef12c1c462a 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
@@ -43,11 +43,6 @@
 #endif
 	};
 
-	chosen {
-		bootargs = "ignore_loglevel";
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@48000000 {
 		device_type = "memory";
 		/* First 128MB is reserved for secure area. */
@@ -63,7 +58,6 @@
 		enable-active-high;
 	};
 
-#if SW_CONFIG2 == SW_ON
 	vccq_sdhi0: regulator1 {
 		compatible = "regulator-gpio";
 		regulator-name = "SDHI0 VccQ";
@@ -73,8 +67,8 @@
 		gpios-states = <1>;
 		states = <3300000 1>, <1800000 0>;
 	};
-#else
-	reg_1p8v: regulator1 {
+
+	reg_1p8v: regulator2 {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -82,9 +76,17 @@
 		regulator-boot-on;
 		regulator-always-on;
 	};
-#endif
 
-	vcc_sdhi2: regulator2 {
+	reg_3p3v: regulator3 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_sdhi2: regulator4 {
 		compatible = "regulator-fixed";
 		regulator-name = "SDHI2 Vcc";
 		regulator-min-microvolt = <3300000>;
@@ -92,6 +94,16 @@
 		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	x3_clk: x3-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+};
+
+&adc {
+	status = "okay";
 };
 
 #if SW_CONFIG3 == SW_ON
@@ -152,6 +164,30 @@
 
 &i2c1 {
 	status = "okay";
+
+	versa3: clock-generator@68 {
+		compatible = "renesas,5l35023";
+		reg = <0x68>;
+		clocks = <&x3_clk>;
+		#clock-cells = <1>;
+		assigned-clocks = <&versa3 0>,
+				  <&versa3 1>,
+				  <&versa3 2>,
+				  <&versa3 3>,
+				  <&versa3 4>,
+				  <&versa3 5>;
+		assigned-clock-rates = <24000000>,
+				       <12288000>,
+				       <11289600>,
+				       <25000000>,
+				       <100000000>,
+				       <100000000>;
+		renesas,settings = [
+		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
+		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
+		  a0 80 30 30 9c
+		];
+	};
 };
 
 #if SW_CONFIG2 == SW_ON
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
index 4509151344c..81b4ffd1417 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
@@ -12,10 +12,15 @@
 / {
 	aliases {
 		i2c0 = &i2c0;
-		serial0 = &scif0;
+		serial3 = &scif0;
 		mmc1 = &sdhi1;
 	};
 
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial3:115200n8";
+	};
+
 	keys {
 		compatible = "gpio-keys";
 
@@ -44,6 +49,23 @@
 		};
 	};
 
+	snd_rzg3s: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&cpu_dai>;
+		simple-audio-card,frame-master = <&cpu_dai>;
+		simple-audio-card,mclk-fs = <256>;
+
+		cpu_dai: simple-audio-card,cpu {
+			sound-dai = <&ssi3>;
+		};
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&da7212>;
+			clocks = <&versa3 1>;
+		};
+	};
+
 	vcc_sdhi1: regulator-vcc-sdhi1 {
 		compatible = "regulator-fixed";
 		regulator-name = "SDHI1 Vcc";
@@ -64,13 +86,56 @@
 	};
 };
 
+&audio_clk2 {
+	clock-frequency = <12288000>;
+};
+
 &i2c0 {
 	status = "okay";
 
 	clock-frequency = <1000000>;
+
+	da7212: codec@1a {
+		compatible = "dlg,da7212";
+		reg = <0x1a>;
+
+		clocks = <&versa3 1>;
+		clock-names = "mclk";
+
+		#sound-dai-cells = <0>;
+
+		dlg,micbias1-lvl = <2500>;
+		dlg,micbias2-lvl = <2500>;
+		dlg,dmic-data-sel = "lrise_rfall";
+		dlg,dmic-samplephase = "between_clkedge";
+		dlg,dmic-clkrate = <3000000>;
+
+		VDDA-supply = <&reg_1p8v>;
+		VDDSP-supply = <&reg_3p3v>;
+		VDDMIC-supply = <&reg_3p3v>;
+		VDDIO-supply = <&reg_1p8v>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+
+	power-monitor@44 {
+		compatible = "renesas,isl28022";
+		reg = <0x44>;
+		shunt-resistor-micro-ohms = <8000>;
+		renesas,average-samples = <32>;
+	};
 };
 
 &pinctrl {
+	audio_clock_pins: audio-clock {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+
 	key-1-gpio-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
@@ -128,6 +193,13 @@
 			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
 		};
 	};
+
+	ssi3_pins: ssi3 {
+		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
+			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
+			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
+			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
+	};
 };
 
 &scif0 {
@@ -148,3 +220,12 @@
 	max-frequency = <125000000>;
 	status = "okay";
 };
+
+&ssi3 {
+	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
+		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
+		 <&versa3 2>, <&audio_clk2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
index 5c211ed8304..2a157d1efb3 100644
--- a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
+++ b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
@@ -4,8 +4,24 @@
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * Sample Audio settings:
+ *
+ *	> amixer set "DVC Out" 1%
+ *	> amixer set "DVC In"  20%
+ *
+ *	// if you use xxxx-mix+split.dtsi
+ *	> amixer -D hw:1 set "pcm3168a DAC1" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC2" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC3" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC4" 50%
+ *
+ *	// else
+ *	> amixer -D hw:1 set "DAC1" 50%
+ *	> amixer -D hw:1 set "DAC2" 50%
+ *	> amixer -D hw:1 set "DAC3" 50%
+ *	> amixer -D hw:1 set "DAC4" 50%
  */
-
 / {
 	aliases {
 		serial1 = &hscif0;
diff --git a/dts/upstream/src/arm64/renesas/ulcb.dtsi b/dts/upstream/src/arm64/renesas/ulcb.dtsi
index cb11abba7be..0c58d816c37 100644
--- a/dts/upstream/src/arm64/renesas/ulcb.dtsi
+++ b/dts/upstream/src/arm64/renesas/ulcb.dtsi
@@ -4,6 +4,11 @@
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * Sample Audio settings:
+ *
+ *	> amixer set "DVC Out" 1%
+ *	> amixer set "DVC In"  20%
  */
 
 #include <dt-bindings/gpio/gpio.h>
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/dts/upstream/src/arm64/renesas/white-hawk-ard-audio-da7212.dtso
index e6cf304c77e..c27b9b3d4e5 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
+++ b/dts/upstream/src/arm64/renesas/white-hawk-ard-audio-da7212.dtso
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board
+ * Device Tree Source for White Hawk (Single) board with ARD-AUDIO-DA7212 board
  *
  * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key
  *
@@ -27,12 +27,12 @@
  * +----------------------------+
  * |Breakout board		|
  * |				|	+---------------+
- * |CN34 (I2C CN)		|	|J1		|
+ * |CN(30)34 (I2C CN)		|	|J1		|
  * |	I2C0_SCL	   pin3 |<----->| pin20 SCL	|
  * |	I2C0_SDA	   pin5 |<----->| pin18 SDA	|
  * |				|	+---------------+
  * |				|	+-----------------------+
- * |CN4 (Power)		        |	|J7			|
+ * |CN(300)4 (Power)	        |	|J7			|
  * |	3v3 (v)		   pin9 |<----->| pin4  / pin8  3.3v	|
  * |	GND (v)	    pin3 / pin4 |<----->| pin12 / pin14 GND	|
  * +----------------------------+	+-----------------------+
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
index 3006b0a64f4..9017c4475a7 100644
--- a/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
+++ b/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
@@ -21,6 +21,7 @@
 				bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
 				clock-lanes = <0>;
 				data-lanes = <1 2 3>;
+				line-orders = <0 3 0>;
 				remote-endpoint = <&max96712_out0>;
 			};
 		};
@@ -41,6 +42,7 @@
 				bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
 				clock-lanes = <0>;
 				data-lanes = <1 2 3>;
+				line-orders = <0 3 0>;
 				remote-endpoint = <&max96712_out1>;
 			};
 		};
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi
new file mode 100644
index 00000000000..20e8232f2f3
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk Single board
+ *
+ * Copyright (C) 2023-2024 Glider bv
+ */
+
+#include "white-hawk-cpu-common.dtsi"
+#include "white-hawk-common.dtsi"
+
+/ {
+	model = "Renesas White Hawk Single board";
+	compatible = "renesas,white-hawk-single";
+};
+
+&hscif0 {
+	uart-has-rtscts;
+};
+
+&hscif0_pins {
+	groups = "hscif0_data", "hscif0_ctrl";
+	function = "hscif0";
+};
+
+&pfc {
+	tsn0_pins: tsn0 {
+		mux {
+			groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii",
+				 "tsn0_txcrefclk";
+			function = "tsn0";
+		};
+
+		link {
+			groups = "tsn0_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "tsn0_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "tsn0_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+};
+
+&tsn0 {
+	pinctrl-0 = <&tsn0_pins>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii";
+	phy-handle = <&phy3>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		phy3: ethernet-phy@0 {
+			compatible = "ethernet-phy-id002b.0980",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
index e4517f47d51..1a59e8b1dc4 100644
--- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
@@ -194,6 +194,13 @@
 			  <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	uart {
+		uart5_rts_pin: uart5-rts-pin {
+			rockchip,pins =
+			  <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm0 {
@@ -222,11 +229,15 @@
 };
 
 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>;
 	status = "okay";
 };
 
 &uart5 {
-	pinctrl-0 = <&uart5_xfer>;
+	/* Add pinmux for rts-gpios (uart5_rts_pin) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5_xfer &uart5_rts_pin>;
 	rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
index ae050cc6cd0..e80412abec0 100644
--- a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
+++ b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
@@ -396,6 +396,12 @@
 	status = "okay";
 };
 
+&uart5 {
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+	pinctrl-0 = <&uart5_xfer>;
+};
+
 /* Mule UCAN */
 &usb_host0_ehci {
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
index 8dfeaf1f8eb..f7c4578865c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
@@ -110,7 +110,6 @@
 	phy-supply = <&vcc_io>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,aal;
 	snps,pbl = <0x4>;
 	tx_delay = <0x26>;
 	rx_delay = <0x11>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
index 1715d311e1f..691d17022af 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
@@ -142,7 +142,6 @@
 	phy-supply = <&vcc_io_33>;
 	pinctrl-0 = <&rgmiim1_pins>;
 	pinctrl-names = "default";
-	snps,aal;
 
 	mdio {
 		compatible = "snps,dwmac-mdio";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
index 67c246ad8b8..ec2ce894da1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -17,8 +17,7 @@
 
 &gmac2io {
 	phy-handle = <&yt8531c>;
-	tx_delay = <0x19>;
-	rx_delay = <0x05>;
+	phy-mode = "rgmii-id";
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
index 324a8e951f7..846b931e16d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
@@ -15,6 +15,7 @@
 
 &gmac2io {
 	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
 	tx_delay = <0x24>;
 	rx_delay = <0x18>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
index 82021ffb0a4..09508e324a2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
@@ -109,11 +109,9 @@
 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
 	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
 	clock_in_out = "input";
-	phy-mode = "rgmii";
 	phy-supply = <&vcc_io>;
 	pinctrl-0 = <&rgmiim1_pins>;
 	pinctrl-names = "default";
-	snps,aal;
 
 	mdio {
 		compatible = "snps,dwmac-mdio";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
index 425de197ddb..6310b58de77 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -153,9 +153,6 @@
 	phy-supply = <&vcc_io>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,aal;
-	snps,rxpbl = <0x4>;
-	snps,txpbl = <0x4>;
 	tx_delay = <0x26>;
 	rx_delay = <0x11>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
index 745d3e99641..e550b6eeeff 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
@@ -144,7 +144,6 @@
 	phy-mode = "rgmii";
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,force_thresh_dma_mode;
 	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <0 10000 50000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
index 988e6ca32fa..a9ea4b0daa0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
@@ -22,11 +22,11 @@
 	};
 
 	/* EC turns on w/ pp900_usb_en */
-	pp900_usb: pp900-ap {
+	pp900_usb: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pcie_en */
-	pp900_pcie: pp900-ap {
+	pp900_pcie: regulator-pp900-ap {
 	};
 
 	pp3000: regulator-pp3000 {
@@ -126,7 +126,7 @@
 	};
 
 	/* Always on; plain and simple */
-	pp3000_ap: pp3000_emmc: pp3000 {
+	pp3000_ap: pp3000_emmc: regulator-pp3000 {
 	};
 
 	pp1500_ap_io: regulator-pp1500-ap-io {
@@ -160,7 +160,7 @@
 	};
 
 	/* EC turns on w/ pp3300_usb_en_l */
-	pp3300_usb: pp3300 {
+	pp3300_usb: regulator-pp3300 {
 	};
 
 	/* gpio is shared with pp1800_pcie and pinctrl is set there */
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
index 19b23b43896..5e068377a0a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
@@ -92,7 +92,7 @@
 	};
 
 	/* EC turns on pp1800_s3_en */
-	pp1800_s3: pp1800 {
+	pp1800_s3: regulator-pp1800 {
 	};
 
 	/* pp3300 children, sorted by name */
@@ -109,11 +109,11 @@
 	};
 
 	/* EC turns on pp3300_s0_en */
-	pp3300_s0: pp3300 {
+	pp3300_s0: regulator-pp3300 {
 	};
 
 	/* EC turns on pp3300_s3_en */
-	pp3300_s3: pp3300 {
+	pp3300_s3: regulator-pp3300 {
 	};
 
 	/*
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
index 6d9e60b0122..7eca1da78cf 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
@@ -189,39 +189,39 @@
 	};
 
 	/* EC turns on w/ pp900_ddrpll_en */
-	pp900_ddrpll: pp900-ap {
+	pp900_ddrpll: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pll_en */
-	pp900_pll: pp900-ap {
+	pp900_pll: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pmu_en */
-	pp900_pmu: pp900-ap {
+	pp900_pmu: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp1800_s0_en_l */
-	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
+	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_avdd_en_l */
-	pp1800_avdd: pp1800 {
+	pp1800_avdd: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_lid_en_l */
-	pp1800_lid: pp1800_mic: pp1800 {
+	pp1800_lid: pp1800_mic: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ lpddr_pwr_en */
-	pp1800_lpddr: pp1800 {
+	pp1800_lpddr: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_pmu_en_l */
-	pp1800_pmu: pp1800 {
+	pp1800_pmu: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_usb_en_l */
-	pp1800_usb: pp1800 {
+	pp1800_usb: regulator-pp1800 {
 	};
 
 	pp3000_sd_slot: regulator-pp3000-sd-slot {
@@ -259,11 +259,11 @@
 	};
 
 	/* EC turns on w/ pp3300_trackpad_en_l */
-	pp3300_trackpad: pp3300-trackpad {
+	pp3300_trackpad: regulator-pp3300-trackpad {
 	};
 
 	/* EC turns on w/ usb_a_en */
-	pp5000_usb_a_vbus: pp5000 {
+	pp5000_usb_a_vbus: regulator-pp5000 {
 	};
 
 	ap_rtc_clk: ap-rtc-clk {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
index b1c9bd0e63e..8d94d9f91a5 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
@@ -115,7 +115,7 @@
 };
 
 &u2phy1_host {
-	status = "disabled";
+	phy-supply = <&vdd_5v>;
 };
 
 &uart0 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
index d12e661dfd9..995b30a7aae 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
@@ -182,7 +182,7 @@
 	snps,reset-active-low;
 	snps,reset-delays-us = <0 10000 50000>;
 	tx_delay = <0x10>;
-	rx_delay = <0x10>;
+	rx_delay = <0x23>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
index 69a9d617064..51c6aa26d82 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
@@ -227,6 +227,16 @@
 		vin-supply = <&vcc12v_dcin>;
 	};
 
+	vcca_0v9: regulator-vcca-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
 	vdd_log: regulator-vdd-log {
 		compatible = "pwm-regulator";
 		pwms = <&pwm2 0 25000 1>;
@@ -312,6 +322,8 @@
 };
 
 &hdmi {
+	avdd-0v9-supply = <&vcca_0v9>;
+	avdd-1v8-supply = <&vcc1v8_dvp>;
 	ddc-i2c-bus = <&i2c3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&hdmi_cec>;
@@ -661,6 +673,8 @@
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_perst>;
+	vpcie0v9-supply = <&vcca_0v9>;
+	vpcie1v8-supply = <&vcca_1v8>;
 	vpcie12v-supply = <&vcc12v_dcin>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts
new file mode 100644
index 00000000000..97415d099d8
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-bigtreetech-cb2.dtsi"
+
+/ {
+	model = "BigTreeTech CB2";
+	compatible = "bigtreetech,cb2-manta", "bigtreetech,cb2", "rockchip,rk3566";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi
new file mode 100644
index 00000000000..a4835147176
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi
@@ -0,0 +1,904 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3566.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	ext_cam_clk: clock-25000000-cam {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "ext_cam_clk";
+		#clock-cells = <0>;
+	};
+
+	can_mcp2515_osc: clock-8000000-mcp2515 {
+		compatible = "fixed-clock";
+		clock-frequency = <8000000>;
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 =<&blue_led>;
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_HEARTBEAT;
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 =<&heartbeat_led>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 50 100 150 200 255>;
+		pwms = <&pwm7 0 50000 0>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+
+	vbus: regulator-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_pcie: regulator-vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host3";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_otg: regulator-vcc5v0-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		regulator-name = "vcc5v0_otg3";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_usb2b: regulator-vcc5v0-usb2b {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb2b_en>;
+		regulator-name = "vcc5v0_usb2b";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_usb2t: regulator-vcc5v0-usb2t {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb2t_en>;
+		regulator-name = "vcc5v0_usb2t";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_5v: regulator-vcc-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_sd: regulator-vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc_sd";
+		vin-supply = <&vcc3v3_sys>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+			&gmac1m0_tx_bus2
+			&gmac1m0_rx_bus2
+			&gmac1m0_rgmii_clk
+			&gmac1m0_clkinout
+			&gmac1m0_rgmii_bus>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy0: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reset-delay-us = <20000>;
+		reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <100000>;
+		reg = <0x0>;
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		regulator-boot-on;
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+		fcs,suspend-voltage-selector = <1>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		#sound-dai-cells = <0>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			rockchip,mic-in-differential;
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2m1_xfer>;
+};
+
+&i2c3 {
+	status = "okay";
+
+	tft_tp: touchscreen@48 {
+		compatible = "ti,tsc2007";
+		reg = <0x48>;
+		status = "okay";
+		ti,x-plate-ohms = <660>;
+		ti,rt-thr = <3000>;
+		ti,fuzzx = <32>;
+		ti,fuzzy = <16>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+
+	can_mcp2515: can@0 {
+		compatible = "microchip,mcp2515";
+		reg = <0x00>;
+		clocks = <&can_mcp2515_osc>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcp2515_int_pin>;
+		spi-max-frequency = <10000000>;
+		vdd-supply = <&vcc3v3_sys>;
+		xceiver-supply = <&vcc3v3_sys>;
+	};
+};
+
+&spi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>;
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	bt {
+		bt_enable: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_host_wake: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake: bt-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake: wifi-host-wake-l {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb2t_en: vcc5v0-usb2t-en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb2b_en: vcc5v0-usb2b-en {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	work-led {
+		heartbeat_led: led-heartbeat {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		blue_led: led-blue {
+			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	mcp2515 {
+		mcp2515_int_pin: mcp2515-int-pin {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0m1_pins>;
+};
+
+&pwm12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm12m1_pins>;
+};
+
+&pwm13 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm13m1_pins>;
+};
+
+&pwm14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm14m1_pins>;
+};
+
+&pwm15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm15m1_pins>;
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	/* WiFi & BT combo module AMPAK AP6256 */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	rockchip,default-sample-phase = <90>;
+	status = "okay";
+
+	sdio-wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake>;
+		brcm,drive-strength = <10>;
+	};
+};
+
+&sfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	dma-names = "tx","rx";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5m1_xfer>;
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7m2_xfer>;
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb2t>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb2b>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts
new file mode 100644
index 00000000000..7cd444caa18
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-bigtreetech-cb2.dtsi"
+
+/ {
+	model = "BigTreeTech Pi 2";
+	compatible = "bigtreetech,pi2", "rockchip,rk3566";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
index 61dd71c259a..ddf84c2a19c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
@@ -512,7 +512,6 @@
 
 &sdmmc0 {
 	max-frequency = <150000000>;
-	supports-sd;
 	bus-width = <4>;
 	cap-mmc-highspeed;
 	cap-sd-highspeed;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts b/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
index c491dc4d494..b1f185a5890 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
@@ -206,12 +206,6 @@
 	};
 };
 
-&i2c2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2m0_xfer>;
-};
-
 &i2c3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c3m0_xfer>;
@@ -357,6 +351,19 @@
 	status = "okay";
 };
 
+&spi0 {
+	/* use hardware chipselect on cs0 (cs1 unconnected) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0m0_pins>, <&spi0m0_cs0>;
+	status = "okay";
+
+	fram@0 {
+		compatible = "fujitsu,mb85rs128ty";
+		reg = <0>;
+		spi-max-frequency = <33000000>;
+	};
+};
+
 &tsadc {
 	rockchip,hw-tshut-mode = <1>;
 	rockchip,hw-tshut-polarity = <0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
index e601d9271ba..7bd32d230ad 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
@@ -50,6 +50,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+			label = "hdd1:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd1_led_pin>;
@@ -59,6 +60,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+			label = "hdd2:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd2_led_pin>;
@@ -68,6 +70,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
+			label = "hdd3:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd3_led_pin>;
@@ -77,6 +80,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+			label = "hdd4:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd4_led_pin>;
@@ -483,6 +487,54 @@
 	};
 };
 
+/*
+ * The MCU can provide system temperature too, but only by polling and of
+ * course also cannot set trip points. So attach to the cpu thermal-zone
+ * instead to control the fan.
+ */
+&cpu_thermal {
+	trips {
+		case_fan0: case-fan0 {
+			hysteresis = <2000>;
+			temperature = <35000>;
+			type = "active";
+		};
+
+		case_fan1: case-fan1 {
+			hysteresis = <2000>;
+			temperature = <45000>;
+			type = "active";
+		};
+
+		case_fan2: case-fan2 {
+			hysteresis = <2000>;
+			temperature = <65000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		/*
+		 * Always provide some air movement, due to small case
+		 * full of harddrives.
+		 */
+		map1 {
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+			trip = <&case_fan0>;
+		};
+
+		map2 {
+			cooling-device = <&fan 2 3>;
+			trip = <&case_fan1>;
+		};
+
+		map3 {
+			cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
+			trip = <&case_fan2>;
+		};
+	};
+};
+
 &pcie30phy {
 	data-lanes = <1 2>;
 	status = "okay";
@@ -582,6 +634,15 @@
  */
 &uart0 {
 	status = "okay";
+
+	mcu {
+		compatible = "qnap,ts433-mcu";
+
+		fan: fan-0 {
+			#cooling-cells = <2>;
+			cooling-levels = <0 64 89 128 166 204 221 238>;
+		};
+	};
 };
 
 /*
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
index e8243c90854..bb33fabae16 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
@@ -53,7 +53,7 @@
 
 	pdm_codec: pdm-codec {
 		compatible = "dmic-codec";
-		num-channels = <1>;
+		num-channels = <2>;
 		#sound-dai-cells = <0>;
 	};
 
@@ -167,6 +167,10 @@
 	};
 };
 
+&hdmi_sound {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -414,6 +418,10 @@
 	pinctrl-0 = <&i2c4m1_xfer>;
 };
 
+&i2s0_8ch {
+	status = "okay";
+};
+
 &pdm {
 	pinctrl-0 = <&pdmm0_clk
 		     &pdmm0_sdi0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts
new file mode 100644
index 00000000000..782ca000a64
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3576.dtsi"
+
+/ {
+	model = "Rockchip RK3576 EVB V10 Board";
+	compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-back {
+			label = "back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <1235000>;
+		};
+
+		button-menu {
+			label = "menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <890000>;
+		};
+
+		button-vol-down {
+			label = "volume down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <417000>;
+		};
+
+		button-vol-up {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		work_led: led-0 {
+			gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vbus5v0_typec: regulator-vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_device>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg0_pwren>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v2_ufs_vccq_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_ufs_vccq2_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
+	vcc3v3_pcie0: regulator-vcc3v3-pcie0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_rtc_s5";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_device: regulator-vcc5v0-device {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_device";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_device>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_host_pwren>;
+	};
+
+	vcc_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_1v8_s0: regulator-vcc-1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_2v0_pldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <2000000>;
+		regulator-max-microvolt = <2000000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_3v3_s0: regulator-vcc-3v3-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_ufs_s0: regulator-vcc-ufs-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_ufs_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&combphy1_psu {
+	status = "okay";
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&rgmii_phy0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth0m0_miim
+		     &eth0m0_tx_bus2
+		     &eth0m0_rx_bus2
+		     &eth0m0_rgmii_clk
+		     &eth0m0_rgmii_bus
+		     &ethm0_clk0_25m_out>;
+	snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x21>;
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth1m0_miim
+		     &eth1m0_tx_bus2
+		     &eth1m0_rx_bus2
+		     &eth1m0_rgmii_clk
+		     &eth1m0_rgmii_bus
+		     &ethm0_clk1_25m_out>;
+	snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x20>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk806: pmic@23 {
+		compatible = "rockchip,rk806";
+		reg = <0x23>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc_sys>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs1_slp: dvs1-slp-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs1_rst: dvs1-rst-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_slp: dvs2-slp-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs2_rst: dvs2-rst-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_dvs: dvs2-dvs-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs2_gpio: dvs2-gpio-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun5";
+		};
+
+		rk806_dvs3_slp: dvs3-slp-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs3_rst: dvs3-rst-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs3_dvs: dvs3-dvs-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs3_gpio: dvs3-gpio-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun5";
+		};
+
+		regulators {
+			vdd_cpu_big_s0: dcdc-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_big_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_npu_s0: dcdc-reg2 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_npu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_gpu_s0: dcdc-reg5 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <800000>;
+				regulator-name = "vdd_logic_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo2_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdda_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v75_hdmi_s0: nldo-reg3 {
+				regulator-boot-on;
+				regulator-min-microvolt = <837500>;
+				regulator-max-microvolt = <837500>;
+				regulator-name = "vdda0v75_hdmi_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdda_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru REFCLKO25M_GMAC1_OUT>;
+	};
+};
+
+&pinctrl {
+	usb {
+		usb_host_pwren: usb-host-pwren {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb_otg0_pwren: usb-otg0-pwren {
+			rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vbus5v0_typec>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbdp_phy {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&usb_drd0_dwc3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_drd1_dwc3 {
+	dr_mode = "host";
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
index 436232ffe4d..4dde954043e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -445,6 +445,58 @@
 		#size-cells = <2>;
 		ranges;
 
+		usb_drd0_dwc3: usb@23000000 {
+			compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+			reg = <0x0 0x23000000 0x0 0x400000>;
+			clocks = <&cru CLK_REF_USB3OTG0>,
+				 <&cru CLK_SUSPEND_USB3OTG0>,
+				 <&cru ACLK_USB3OTG0>;
+			clock-names = "ref_clk", "suspend_clk", "bus_clk";
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&power RK3576_PD_USB>;
+			resets = <&cru SRST_A_USB3OTG0>;
+			dr_mode = "otg";
+			phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-hs-quirk;
+			snps,parkmode-disable-ss-quirk;
+			status = "disabled";
+		};
+
+		usb_drd1_dwc3: usb@23400000 {
+			compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+			reg = <0x0 0x23400000 0x0 0x400000>;
+			clocks = <&cru CLK_REF_USB3OTG1>,
+				 <&cru CLK_SUSPEND_USB3OTG1>,
+				 <&cru ACLK_USB3OTG1>;
+			clock-names = "ref_clk", "suspend_clk", "bus_clk";
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&power RK3576_PD_PHP>;
+			resets = <&cru SRST_A_USB3OTG1>;
+			dr_mode = "otg";
+			phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,dis_rxdet_inp3_quirk;
+			snps,parkmode-disable-hs-quirk;
+			snps,parkmode-disable-ss-quirk;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		sys_grf: syscon@2600a000 {
 			compatible = "rockchip,rk3576-sys-grf", "syscon";
 			reg = <0x0 0x2600a000 0x0 0x2000>;
@@ -515,6 +567,65 @@
 			reg = <0x0 0x2602c000 0x0 0x2000>;
 		};
 
+		usb2phy_grf: syscon@2602e000 {
+			compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
+			reg = <0x0 0x2602e000 0x0 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u2phy0: usb2-phy@0 {
+				compatible = "rockchip,rk3576-usb2phy";
+				reg = <0x0 0x10>;
+				resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
+				reset-names = "phy", "apb";
+				clocks = <&cru CLK_PHY_REF_SRC>,
+					 <&cru ACLK_MMU2>,
+					 <&cru ACLK_SLV_MMU2>;
+				clock-names = "phyclk", "aclk", "aclk_slv";
+				clock-output-names = "usb480m_phy0";
+				#clock-cells = <0>;
+				status = "disabled";
+
+				u2phy0_otg: otg-port {
+					#phy-cells = <0>;
+					interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-names = "otg-bvalid", "otg-id", "linestate";
+					status = "disabled";
+				};
+			};
+
+			u2phy1: usb2-phy@2000 {
+				compatible = "rockchip,rk3576-usb2phy";
+				reg = <0x2000 0x10>;
+				resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
+				reset-names = "phy", "apb";
+				clocks = <&cru CLK_PHY_REF_SRC>,
+					 <&cru ACLK_MMU1>,
+					 <&cru ACLK_SLV_MMU1>;
+				clock-names = "phyclk", "aclk", "aclk_slv";
+				clock-output-names = "usb480m_phy1";
+				#clock-cells = <0>;
+				status = "disabled";
+
+				u2phy1_otg: otg-port {
+					#phy-cells = <0>;
+					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-names = "otg-bvalid", "otg-id", "linestate";
+					status = "disabled";
+				};
+			};
+		};
+
+		vo1_grf: syscon@26036000 {
+			compatible = "rockchip,rk3576-vo1-grf", "syscon";
+			reg = <0x0 0x26036000 0x0 0x100>;
+			clocks = <&cru PCLK_VO1_ROOT>;
+		};
+
 		sdgmac_grf: syscon@26038000 {
 			compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
 			reg = <0x0 0x26038000 0x0 0x1000>;
@@ -1587,6 +1698,64 @@
 			status = "disabled";
 		};
 
+		combphy0_ps: phy@2b050000 {
+			compatible = "rockchip,rk3576-naneng-combphy";
+			reg = <0x0 0x2b050000 0x0 0x100>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_REF_PCIE0_PHY>,
+				 <&cru PCLK_PCIE2_COMBOPHY0>,
+				 <&cru PCLK_PCIE0>;
+			clock-names = "ref", "apb", "pipe";
+			assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
+			assigned-clock-rates = <100000000>;
+			resets = <&cru SRST_PCIE0_PIPE_PHY>,
+				 <&cru SRST_P_PCIE2_COMBOPHY0>;
+			reset-names = "phy", "apb";
+			rockchip,pipe-grf = <&php_grf>;
+			rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+			status = "disabled";
+		};
+
+		combphy1_psu: phy@2b060000 {
+			compatible = "rockchip,rk3576-naneng-combphy";
+			reg = <0x0 0x2b060000 0x0 0x100>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_REF_PCIE1_PHY>,
+				 <&cru PCLK_PCIE2_COMBOPHY1>,
+				 <&cru PCLK_PCIE1>;
+			clock-names = "ref", "apb", "pipe";
+			assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
+			assigned-clock-rates = <100000000>;
+			resets = <&cru SRST_PCIE1_PIPE_PHY>,
+				 <&cru SRST_P_PCIE2_COMBOPHY1>;
+			reset-names = "phy", "apb";
+			rockchip,pipe-grf = <&php_grf>;
+			rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+			status = "disabled";
+		};
+
+		usbdp_phy: phy@2b010000 {
+			compatible = "rockchip,rk3576-usbdp-phy";
+			reg = <0x0 0x2b010000 0x0 0x10000>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_PHY_REF_SRC >,
+				 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
+				 <&cru PCLK_USBDPPHY>,
+				 <&u2phy0>;
+			clock-names = "refclk", "immortal", "pclk", "utmi";
+			resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
+				 <&cru SRST_USBDP_COMBO_PHY_CMN>,
+				 <&cru SRST_USBDP_COMBO_PHY_LANE>,
+				 <&cru SRST_USBDP_COMBO_PHY_PCS>,
+				 <&cru SRST_P_USBDPPHY>;
+			reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+			rockchip,u2phy-grf = <&usb2phy_grf>;
+			rockchip,usb-grf = <&usb_grf>;
+			rockchip,usbdpphy-grf = <&usbdpphy_grf>;
+			rockchip,vo-grf = <&vo1_grf>;
+			status = "disabled";
+		};
+
 		sram: sram@3ff88000 {
 			compatible = "mmio-sram";
 			reg = <0x0 0x3ff88000 0x0 0x78000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts b/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts
new file mode 100644
index 00000000000..e04f21d8c83
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Radxa E52C";
+	compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <18000>;
+		poll-interval = <100>;
+
+		button-0 {
+			label = "Maskrom";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	keys-1 {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&btn_0>;
+
+		button-1 {
+			label = "User";
+			gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+			wakeup-source;
+		};
+	};
+
+	leds-0 {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_0>;
+
+		led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	leds-1 {
+		compatible = "pwm-leds";
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_LAN;
+			linux,default-trigger = "netdev";
+			pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>;
+			max-brightness = <255>;
+		};
+
+		led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_WAN;
+			linux,default-trigger = "netdev";
+			pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;
+			max-brightness = <255>;
+		};
+	};
+
+	vcc_1v1_nldo_s3: regulator-1v1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_3v3_pmu: regulator-3v3-0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pmu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_3v3_s0: regulator-3v3-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcca: regulator-4v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc5v0_usb_otg0: regulator-5v0-0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_pwren_h>;
+		regulator-name = "vcc5v0_usb_otg0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_5v0: regulator-5v0-1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_pwren_h>;
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_sysin: regulator-5v0-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sysin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+/*
+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
+ * and unused because they're marked in the efuses as defective.
+ * The disabling in the DT is performed by the boot loader.
+ */
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+		vcc-supply = <&vcc_3v3_pmu>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+	status = "okay";
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int_l>;
+		wakeup-source;
+	};
+};
+
+&pcie2x1l1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_1_perstn_m1>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+};
+
+&pinctrl {
+	keys {
+		btn_0: button-0 {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_0: led-0 {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie20x1_1_perstn_m1: pcie-1 {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie20x1_2_perstn_m0: pcie-2 {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	regulators {
+		vcc_5v0_pwren_h: regulator-5v0-1 {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int_l: rtc-0 {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usb_otg_pwren_h: regulator-5v0-0 {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm11 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm11m1_pins>;
+	status = "okay";
+};
+
+&pwm14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm14m1_pins>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	vmmc-supply = <&vcc_3v3_s0>;
+	vqmmc-supply = <&vcc_1v8_s3>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sysin>;
+		vcc2-supply = <&vcc_sysin>;
+		vcc3-supply = <&vcc_sysin>;
+		vcc4-supply = <&vcc_sysin>;
+		vcc5-supply = <&vcc_sysin>;
+		vcc6-supply = <&vcc_sysin>;
+		vcc7-supply = <&vcc_sysin>;
+		vcc8-supply = <&vcc_sysin>;
+		vcc9-supply = <&vcc_sysin>;
+		vcc10-supply = <&vcc_sysin>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sysin>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcca>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg3 {
+				regulator-name = "vdd_logic_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vcc_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg1 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg2 {
+				regulator-name = "vcca_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-name = "vdda_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-name = "vcca_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdda_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg3 {
+				regulator-name = "vdda_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-name = "vdda_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index a337f3fb837..c3abdfb04f8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -549,22 +549,21 @@
 	mmu600_pcie: iommu@fc900000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xfc900000 0x0 0x200000>;
-		interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
 		#iommu-cells = <1>;
-		status = "disabled";
 	};
 
 	mmu600_php: iommu@fcb00000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xfcb00000 0x0 0x200000>;
-		interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
 		#iommu-cells = <1>;
 		status = "disabled";
@@ -1686,6 +1685,7 @@
 		linux,pci-domain = <3>;
 		max-link-speed = <2>;
 		msi-map = <0x3000 &its0 0x3000 0x1000>;
+		iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy2_psu PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
@@ -1737,6 +1737,7 @@
 		linux,pci-domain = <4>;
 		max-link-speed = <2>;
 		msi-map = <0x4000 &its0 0x4000 0x1000>;
+		iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy0_ps PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
@@ -2667,9 +2668,9 @@
 		rockchip,hw-tshut-temp = <120000>;
 		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
-		pinctrl-0 = <&tsadc_gpio_func>;
-		pinctrl-1 = <&tsadc_shut>;
-		pinctrl-names = "gpio", "otpout";
+		pinctrl-0 = <&tsadc_shut_org>;
+		pinctrl-1 = <&tsadc_gpio_func>;
+		pinctrl-names = "default", "sleep";
 		#thermal-sensor-cells = <1>;
 		status = "disabled";
 	};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
index 92f0ed83c99..bc6b43a7715 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
@@ -113,7 +113,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_lcd";
 		enable-active-high;
-		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcdpwr_en>;
 		vin-supply = <&vcc3v3_sys>;
@@ -241,7 +241,7 @@
 &pinctrl {
 	lcd {
 		lcdpwr_en: lcdpwr-en {
-			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 
 		bl_en: bl-en {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 05ae9bdcfbb..7125790bbed 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -10,6 +10,15 @@
 		stdout-path = "serial2:1500000n8";
 	};
 
+	/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
+	pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_05>;
+	};
+
 	vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_pcie2x1l0";
@@ -19,26 +28,26 @@
 		vin-supply = <&vcc_3v3_s3>;
 	};
 
-	vcc3v3_pcie3x2: regulator-vcc3v3-pcie3x2 {
+	vcc3v3_bkey: regulator-vcc3v3-bkey {
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie3x2_vcc3v3_en>;
-		regulator-name = "vcc3v3_pcie3x2";
+		pinctrl-0 = <&pcie_4g_pwen>;
+		regulator-name = "vcc3v3_bkey";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		startup-delay-us = <5000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
 
-	vcc3v3_pcie3x4: regulator-vcc3v3-pcie3x4 {
+	vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie3x4_vcc3v3_en>;
-		regulator-name = "vcc3v3_pcie3x4";
+		pinctrl-0 = <&pcie30x4_pwren_h>;
+		regulator-name = "vcc3v3_pcie30";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		startup-delay-us = <5000>;
@@ -98,24 +107,52 @@
 };
 
 &pcie30phy {
+	data-lanes = <1 1 2 2>;
+	/* separate clock lines from the clock generator to phy and devices */
+	rockchip,rx-common-refclk-mode = <0 0 0 0>;
 	status = "okay";
 };
 
-/* B-Key and E-Key */
+/* M-Key */
 &pcie3x2 {
+	/*
+	 * The board has a "pcie_refclk" oscillator that needs enabling,
+	 * so add it to the list of clocks.
+	 */
+	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
+		 <&pcie30_port1_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe",
+		      "ref";
+	num-lanes = <2>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3x2_rst>;
-	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
-	vpcie3v3-supply = <&vcc3v3_pcie3x2>;
+	pinctrl-0 = <&pcie30x2_perstn_m1_l>;
+	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };
 
-/* M-Key */
+/* B-Key and E-Key */
 &pcie3x4 {
+	/*
+	 * The board has a "pcie_refclk" oscillator that needs enabling,
+	 * so add it to the list of clocks.
+	 */
+	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+		 <&pcie30_port0_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe",
+		      "ref";
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3x4_rst>;
-	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
-	vpcie3v3-supply = <&vcc3v3_pcie3x4>;
+	pinctrl-0 = <&pcie30x4_perstn_m1_l>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
+	vpcie3v3-supply = <&vcc3v3_bkey>;
 	status = "okay";
 };
 
@@ -127,20 +164,20 @@
 	};
 
 	pcie3 {
-		pcie3x2_rst: pcie3x2-rst {
-			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en {
-			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie_4g_pwen: pcie-4g-pwen {
+			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 
-		pcie3x4_rst: pcie3x4-rst {
-			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en {
-			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x4_pwren_h: pcie30x4-pwren-h {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
index d6e464cdc53..ba49f0bbaac 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
@@ -206,6 +206,28 @@
 		pinctrl-0 = <&vcc3v3_pcie30_en>;
 	};
 
+	vcc3v3_pciewl_vbat: regulator-vcc3v3-pciewl-vbat {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "wlan-vbat";
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
+	vcc3v3_wlan: regulator-vcc3v3-wlan {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_pwren>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "wlan-en";
+		vin-supply = <&vcc3v3_pciewl_vbat>;
+	};
+
 	vcc5v0_host: regulator-vcc5v0-host {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_host";
@@ -249,12 +271,26 @@
 		regulator-max-microvolt = <5000000>;
 		vin-supply = <&vcc5v0_usbdcin>;
 	};
+
+	vccio_wl: regulator-vccio-wl {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "wlan-vddio";
+		vin-supply = <&vcc_1v8_s0>;
+	};
 };
 
 &combphy0_ps {
 	status = "okay";
 };
 
+&combphy1_ps {
+	status = "okay";
+};
+
 &combphy2_psu {
 	status = "okay";
 };
@@ -440,6 +476,30 @@
 	};
 };
 
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_wlan>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x20 0x2f>;
+
+		wifi: wifi@0,0 {
+			compatible = "pci14e4,449d";
+			reg = <0x210000 0 0 0 0>;
+			clocks = <&hym8563>;
+			clock-names = "lpo";
+		};
+	};
+};
+
 &pcie2x1l1 {
 	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
 	pinctrl-names = "default";
@@ -494,6 +554,18 @@
 	};
 
 	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_0_wake: pcie2-0-wake {
+			rockchip,pins = <4 RK_PA4 4 &pcfg_pull_none>;
+		};
+
+		pcie2_0_clkreq: pcie2-0-clkreq {
+			rockchip,pins = <4 RK_PA3 4 &pcfg_pull_none>;
+		};
+
 		pcie2_1_rst: pcie2-1-rst {
 			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
@@ -524,6 +596,16 @@
 			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
+
+	wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		wifi_pwren: wifi-pwren {
+			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
 };
 
 &pwm2 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
index 0ce0934ec6b..840b638af1c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
@@ -162,6 +162,7 @@
 		linux,pci-domain = <0>;
 		max-link-speed = <3>;
 		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
 		num-lanes = <4>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
@@ -248,6 +249,7 @@
 		linux,pci-domain = <1>;
 		max-link-speed = <3>;
 		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
 		num-lanes = <2>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
@@ -297,6 +299,7 @@
 		linux,pci-domain = <2>;
 		max-link-speed = <2>;
 		msi-map = <0x2000 &its0 0x2000 0x1000>;
+		iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy1_ps PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi
new file mode 100644
index 00000000000..42c523b553c
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3588.dtsi"
+
+/ {
+	compatible = "firefly,core-3588j", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1m2_xfer>;
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-name = "vdd_npu_s0";
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			avcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "avcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			avdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "avdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			avdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "avdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+/* rk3588 preferred debug out */
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts
new file mode 100644
index 00000000000..2be5251d3e3
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "dt-bindings/usb/pd.h"
+
+#include "rk3588-firefly-core-3588j.dtsi"
+
+/ {
+	model = "Firefly ITX-3588J";
+	compatible = "firefly,itx-3588j", "firefly,core-3588j", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	/*
+	 * there are also a "Reset" and "Mask ROM" button, but the needed
+	 * settings are unknown at this time
+	 */
+	adc-keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		pinctrl-0 = <&hp_detect>;
+		pinctrl-names = "default";
+		simple-audio-card,aux-devs = <&amp_headphones>, <&amp_speaker>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+		simple-audio-card,mclk-fs = <384>;
+		simple-audio-card,name = "rockchip_es8323";
+		simple-audio-card,pin-switches = "Headphones", "Speaker";
+		simple-audio-card,routing =
+			"Speaker Amplifier INL", "LOUT2",
+			"Speaker Amplifier INR", "ROUT2",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR",
+			"Headphones Amplifier INL", "LOUT1",
+			"Headphones Amplifier INR", "ROUT1",
+			"Headphones", "Headphones Amplifier OUTL",
+			"Headphones", "Headphones Amplifier OUTR",
+			"LINPUT1", "Microphone Jack",
+			"RINPUT1", "Microphone Jack",
+			"LINPUT2", "Onboard Microphone",
+			"RINPUT2", "Onboard Microphone";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Microphone", "Onboard Microphone",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&es8323>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	/*
+	 * this does not seem to be a proper "amplifier" but is just
+	 * a way to control the GPIO pins to switch on or off the given
+	 * sound output device
+	 */
+	amp_headphones: headphones-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&headphone_amplifier_en>;
+		sound-name-prefix = "Headphones Amplifier";
+	};
+
+	amp_speaker: speaker-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_amplifier_en>;
+		sound-name-prefix = "Speaker Amplifier";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 120 150 180 210 240 255>;
+		fan-supply = <&vcc12v_dcin>;
+		pwms = <&pwm15 0 50000 1>;
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * There is also a Power LED control @ RK_PB3 on
+		 * GPIO1 but for some reason it doesn't seem to work right
+		 */
+
+		user_led: led-1 {
+			gpios = <&pca9555 3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "disk-activity";
+		};
+	};
+
+	pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <750000>;
+		regulator-name = "pcie30_avdd0v75";
+		vin-supply = <&avdd_0v75_s0>;
+	};
+
+	vbus5v0_typec_pwr_en: regulator-vbus5v0-typec-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 12 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vbus5v0_typec_pwr_en";
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-name = "vcc12v_dcin";
+	};
+
+	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_vcc3v3_en>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie30";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_host";
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_host3: regulator-vcc5v0-host3 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 7 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc5v0_host3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_sys";
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_usb";
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-name = "vcc_1v1_nldo_s3";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_fan_pwr_en: regulator-vcc-fan-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 11 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_fan_pwr_en";
+	};
+
+	vcc_hub_reset: regulator-vcc-hub-reset {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 4 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_hub_reset";
+	};
+
+	vcc_hub3_reset: regulator-vcc-hub3-reset {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 6 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-name = "vcc_hub3_reset";
+	};
+
+	vcc_sata_pwr_en: regulator-vcc-sata-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 10 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_sata_pwr_en";
+	};
+};
+
+&avcc_1v8_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	tx_delay = <0x45>;
+	rx_delay = <0x4a>;
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	tx_delay = <0x42>;
+	rx_delay = <0x4f>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	sram-supply = <&vdd_gpu_mem_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	/*
+	 * in the Firefly BSP source this was confusingly called an
+	 * "ES8388" - it actually seems to be an ES8323 and the drivers
+	 * for that work best
+	 */
+	es8323: audio-codec@11 {
+		compatible = "everest,es8323";
+		reg = <0x11>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m0_xfer>;
+	status = "okay";
+
+	pca9555: gpio@21 {
+		compatible = "nxp,pca9555";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec_pwr_en>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "source";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&pinctrl {
+	dp {
+		dp1_hpd: dp1-hpd {
+			 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins =
+				<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		headphone_amplifier_en: headphone-amplifier-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		speaker_amplifier_en: speaker-amplifier-en {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm15m2_pins>;
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+/* uart/232/485 */
+&uart0 {
+	pinctrl-0 = <&uart0m2_xfer>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1m1_xfer>;
+	status = "okay";
+};
+
+/* usb enable */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	usb-role-switch;
+	dr_mode = "otg";
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&vcc_1v8_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <1800000>;
+	};
+};
+
+/* for fan when deep sleep */
+&vdd_log_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <750000>;
+	};
+};
+
+/* display generator */
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts
new file mode 100644
index 00000000000..4791b77f357
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "H96 Max V58 TV Box";
+	compatible = "haochuangyi,h96-max-v58", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-function {
+			label = "Reset";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vcc_1v1_nldo_s3: regulator-1v1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	pcie_3v3: regulator-3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&pcie2_0_pow>;
+		pinctrl-names = "default";
+		regulator-name = "pcie_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	wl_en_3v3: regulator-3v3-wlen {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&wl_en>;
+		pinctrl-names = "default";
+		/*
+		 * Needs to be brought up before the PCIe driver is probed,
+		 * otherwise detecting the WLAN module requires rescanning
+		 * the bus, and even then it fails half of the time during
+		 * firmware load
+		 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "wl_en_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: regulator-5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_host_en>;
+		pinctrl-names = "default";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: regulator-5v0-otg {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		pinctrl-names = "default";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: regulator-5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		/* RTL8211F */
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x20 0x2f>;
+
+		wifi: wifi@0,0 {
+			compatible = "pci14e4,449d";
+			reg = <0x210000 0 0 0 0>;
+			clocks = <&hym8563>;
+			clock-names = "lpo";
+		};
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir-receiver {
+		ir_receiver_pin: ir-receiver-pin {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_pins: led-pins {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_0_pow: pcie2-0-pow {
+			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifibt {
+		wl_en: wl-en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		wl_wake_host: wl-wake-host {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_en: bt-en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_wake: bt-wake {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_wake_host: bt-wake-host {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&uart9 {
+	pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn &uart9m0_rtsn>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&hym8563>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&bt_en>, <&bt_wake_host>, <&bt_wake>;
+		pinctrl-names = "default";
+		shutdown-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 90f823b2c21..7f457ab7801 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -503,7 +503,6 @@
 	non-removable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
-	supports-cqe;
 	vmmc-supply = <&vcc_3v3_s3>;
 	vqmmc-supply = <&vcc_1v8_s3>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi
new file mode 100644
index 00000000000..87090cb9802
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588-orangepi-5.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi 5 Max";
+	compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
+
+	vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		/* USB_OTG_PWREN */
+		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_pwren>;
+		regulator-name = "vcc5v0_usb30_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&headphone_amp {
+	/* PHONE_CTL */
+	enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+};
+
+&analog_sound {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hp_detect>;
+	simple-audio-card,aux-devs = <&headphone_amp>;
+	simple-audio-card,hp-det-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+
+	simple-audio-card,routing =
+		"Headphones", "LOUT1",
+		"Headphones", "ROUT1",
+		"LINPUT1", "Microphone Jack",
+		"RINPUT1", "Microphone Jack",
+		"LINPUT2", "Onboard Microphone",
+		"RINPUT2", "Onboard Microphone";
+	simple-audio-card,widgets =
+		"Microphone", "Microphone Jack",
+		"Microphone", "Onboard Microphone",
+		"Headphone", "Headphones";
+};
+
+&fan {
+	/* FAN_CTL_H */
+	pwms = <&pwm9 0 50000 0>;
+};
+
+&hym8563 {
+	interrupt-parent = <&gpio0>;
+	interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rtc_int_l>;
+};
+
+&led_blue_pwm {
+	/* PWM_LED1 */
+	pwms = <&pwm4 0 25000 0>;
+	status = "okay";
+};
+
+&led_green_pwm {
+	/* PWM_LED2 */
+	pwms = <&pwm5 0 25000 0>;
+};
+
+/* phy2 */
+&pcie2x1l1 {
+	reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_eth>;
+	status = "okay";
+};
+
+&pinctrl {
+	hym8563 {
+		rtc_int_l: hym8563-int {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usb_host_pwren: usb-host-pwren {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm4m0_pins>;
+	status = "okay";
+};
+
+&pwm5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm5m1_pins>;
+	status = "okay";
+};
+
+&pwm9 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm9m2_pins>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim2_pins>;
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb30_otg>;
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb20>;
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
+
+/* pcie eth. not a real regulator. 33VAUX */
+&vcc3v3_pcie_eth {
+	/* Ethernet_power_en */
+	gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+};
+
+/*
+ * Represents the vcc5v0_usb20 and vcc5v0_usb30 in the schematic,
+ * both regulators share the same enable gpio
+ */
+&vcc5v0_usb20 {
+	/* USB_HOST_PWREN */
+	gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_host_pwren>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts
new file mode 100644
index 00000000000..ce44549babf
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588-orangepi-5-compact.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi 5 Max";
+	compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&pinctrl {
+
+	usb {
+		usb_otg_pwren: usb-otg-pwren {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
index 9f5a38b290b..255e33c5dbd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
@@ -6,86 +6,15 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/soc/rockchip,vop2.h>
 #include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
+#include "rk3588-orangepi-5.dtsi"
 
 / {
 	model = "Xunlong Orange Pi 5 Plus";
 	compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
 
-	aliases {
-		mmc0 = &sdhci;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	adc-keys-0 {
-		compatible = "adc-keys";
-		io-channels = <&saradc 0>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		button-maskrom {
-			label = "Mask Rom";
-			linux,code = <KEY_SETUP>;
-			press-threshold-microvolt = <2000>;
-		};
-	};
-
-	adc-keys-1 {
-		compatible = "adc-keys";
-		io-channels = <&saradc 1>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		button-recovery {
-			label = "Recovery";
-			linux,code = <KEY_VENDOR>;
-			press-threshold-microvolt = <2000>;
-		};
-	};
-
-	speaker_amp: speaker-audio-amplifier {
-		compatible = "simple-audio-amplifier";
-		enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
-		sound-name-prefix = "Speaker Amp";
-	};
-
-	headphone_amp: headphones-audio-amplifier {
-		compatible = "simple-audio-amplifier";
-		enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
-		sound-name-prefix = "Headphones Amp";
-	};
-
-	ir-receiver {
-		compatible = "gpio-ir-receiver";
-		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&ir_receiver_pin>;
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&blue_led_pin>;
-
-		led {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_INDICATOR;
-			function-enumerator = <1>;
-			gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
 	hdmi0-con {
 		compatible = "hdmi-connector";
 		type = "a";
@@ -97,24 +26,11 @@
 		};
 	};
 
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		cooling-levels = <0 70 75 80 100>;
-		fan-supply = <&vcc5v0_sys>;
-		pwms = <&pwm3 0 50000 0>;
-		#cooling-cells = <2>;
-	};
-
-	pwm-leds {
-		compatible = "pwm-leds";
-
-		led {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_INDICATOR;
-			function-enumerator = <2>;
-			max-brightness = <255>;
-			pwms = <&pwm2 0 25000 0>;
-		};
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
 	};
 
 	rfkill {
@@ -124,160 +40,73 @@
 		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
 	};
 
-	sound {
-		compatible = "simple-audio-card";
-		pinctrl-names = "default";
-		pinctrl-0 = <&hp_detect>;
-		simple-audio-card,name = "Analog";
-		simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,mclk-fs = <256>;
-		simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
-		simple-audio-card,bitclock-master = <&daicpu>;
-		simple-audio-card,frame-master = <&daicpu>;
-		/*TODO: SARADC_IN3 is used as MIC detection / key input */
-
-		simple-audio-card,widgets =
-			"Microphone", "Onboard Microphone",
-			"Microphone", "Microphone Jack",
-			"Speaker", "Speaker",
-			"Headphone", "Headphones";
-
-		simple-audio-card,routing =
-			"Headphones", "LOUT1",
-			"Headphones", "ROUT1",
-			"Speaker", "LOUT2",
-			"Speaker", "ROUT2",
-
-			"Headphones", "Headphones Amp OUTL",
-			"Headphones", "Headphones Amp OUTR",
-			"Headphones Amp INL", "LOUT1",
-			"Headphones Amp INR", "ROUT1",
-
-			"Speaker", "Speaker Amp OUTL",
-			"Speaker", "Speaker Amp OUTR",
-			"Speaker Amp INL", "LOUT2",
-			"Speaker Amp INR", "ROUT2",
-
-			/* single ended signal to LINPUT1 */
-			"LINPUT1", "Microphone Jack",
-			"RINPUT1", "Microphone Jack",
-			/* differential signal */
-			"LINPUT2", "Onboard Microphone",
-			"RINPUT2", "Onboard Microphone";
-
-		daicpu: simple-audio-card,cpu {
-			sound-dai = <&i2s0_8ch>;
-			system-clock-frequency = <12288000>;
-		};
-
-		daicodec: simple-audio-card,codec {
-			sound-dai = <&es8388>;
-			system-clock-frequency = <12288000>;
-		};
-	};
-
-	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
-		regulator-name = "vcc3v3_pcie30";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <5000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_pcie_eth: regulator-vcc3v3-pcie-eth {
-		compatible = "regulator-fixed";
-		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
-		regulator-name = "vcc3v3_pcie_eth";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_wf: regulator-vcc3v3-wf {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-		regulator-name = "vcc3v3_wf";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc5v0_sys: regulator-vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_usb20: regulator-vcc5v0-usb20 {
+	vbus5v0_typec: regulator-vbus-typec {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb20_en>;
-		regulator-name = "vcc5v0_usb20";
+		pinctrl-0 = <&typec5v_pwren>;
+		regulator-name = "vbus5v0_typec";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
 };
 
-&combphy0_ps {
-	status = "okay";
-};
-
-&combphy1_ps {
+&speaker_amp {
+	enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
-&combphy2_psu {
-	status = "okay";
+&headphone_amp {
+	enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
 };
 
-&cpu_b0 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&analog_sound {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hp_detect>;
+	simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
+	simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
+	simple-audio-card,widgets =
+		"Microphone", "Onboard Microphone",
+		"Microphone", "Microphone Jack",
+		"Speaker", "Speaker",
+		"Headphone", "Headphones";
+
+	simple-audio-card,routing =
+		"Headphones", "LOUT1",
+		"Headphones", "ROUT1",
+		"Speaker", "LOUT2",
+		"Speaker", "ROUT2",
+
+		"Headphones", "Headphones Amp OUTL",
+		"Headphones", "Headphones Amp OUTR",
+		"Headphones Amp INL", "LOUT1",
+		"Headphones Amp INR", "ROUT1",
+
+		"Speaker", "Speaker Amp OUTL",
+		"Speaker", "Speaker Amp OUTR",
+		"Speaker Amp INL", "LOUT2",
+		"Speaker Amp INR", "ROUT2",
+
+		/* single ended signal to LINPUT1 */
+		"LINPUT1", "Microphone Jack",
+		"RINPUT1", "Microphone Jack",
+		/* differential signal */
+		"LINPUT2", "Onboard Microphone",
+		"RINPUT2", "Onboard Microphone";
 };
 
-&cpu_l1 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&combphy0_ps {
+	status = "okay";
 };
 
-&cpu_l2 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&combphy1_ps {
+	status = "okay";
 };
 
-&cpu_l3 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu_s0>;
-	status = "okay";
+&fan {
+	pwms = <&pwm3 0 50000 0>;
 };
 
 &hdmi0 {
@@ -300,128 +129,73 @@
 	status = "okay";
 };
 
-&i2c0 {
+&hym8563 {
+	interrupt-parent = <&gpio0>;
+	interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0m2_xfer>;
-	status = "okay";
-
-	vdd_cpu_big0_s0: regulator@42 {
-		compatible = "rockchip,rk8602";
-		reg = <0x42>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big0_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vdd_cpu_big1_s0: regulator@43 {
-		compatible = "rockchip,rk8603", "rockchip,rk8602";
-		reg = <0x43>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big1_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
+	pinctrl-0 = <&hym8563_int>;
 };
 
 &i2c6 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	hym8563: rtc@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
 		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <0>;
-		clock-output-names = "hym8563";
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&hym8563_int>;
-		wakeup-source;
-	};
-};
-
-&i2c7 {
-	status = "okay";
-
-	/* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
-	es8388: audio-codec@11 {
-		compatible = "everest,es8388";
-		reg = <0x11>;
-		clocks = <&cru I2S0_8CH_MCLKOUT>;
-		AVDD-supply = <&vcc_1v8_s0>;
-		DVDD-supply = <&vcc_1v8_s0>;
-		HPVDD-supply = <&vcc_3v3_s0>;
-		PVDD-supply = <&vcc_3v3_s0>;
-		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
-		assigned-clock-rates = <12288000>;
-		#sound-dai-cells = <0>;
-	};
-};
-
-&i2s0_8ch {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2s0_lrck
-		     &i2s0_mclk
-		     &i2s0_sclk
-		     &i2s0_sdi0
-		     &i2s0_sdo0>;
-	status = "okay";
-};
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+		status = "okay";
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			power-role = "dual";
+			op-sink-microwatt = <10>;
+			source-pdos = <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 10, PDO_FIXED_USB_COMM)>;
+			try-power-role = "source";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
 
-&i2s2_2ch {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2s2m0_lrck
-		     &i2s2m0_sclk
-		     &i2s2m0_sdi
-		     &i2s2m0_sdo>;
-	status = "okay";
-};
+				port@1 {
+					reg = <1>;
 
-&package_thermal {
-	polling-delay = <1000>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
 
-	cooling-maps {
-		map0 {
-			trip = <&package_fan0>;
-			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
-		};
+				port@2 {
+					reg = <2>;
 
-		map1 {
-			trip = <&package_fan1>;
-			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
 		};
 	};
+};
 
-	trips {
-		package_fan0: package-fan0 {
-			temperature = <55000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
+&led_blue_gpio {
+	gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
 
-		package_fan1: package-fan1 {
-			temperature = <65000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
-	};
+&led_green_pwm {
+	pwms = <&pwm2 0 25000 0>;
 };
 
 /* phy1 - M.KEY socket */
@@ -445,16 +219,6 @@
 	status = "okay";
 };
 
-&pcie30phy {
-	status = "okay";
-};
-
-&pcie3x4 {
-	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie30>;
-	status = "okay";
-};
-
 &pinctrl {
 	hym8563 {
 		hym8563_int: hym8563-int {
@@ -485,6 +249,16 @@
 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm2 {
@@ -498,434 +272,68 @@
 	status = "okay";
 };
 
-&saradc {
-	vref-supply = <&vcc_1v8_s0>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	no-sdio;
-	no-sd;
-	non-removable;
-	max-frequency = <200000000>;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc_3v3_s3>;
-	vqmmc-supply = <&vccio_sd_s0>;
+&recovery_button {
 	status = "okay";
 };
 
 &sfc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&fspim1_pins>;
-	status = "okay";
+};
 
-	spi_flash: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <100000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <1>;
-	};
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_sys>;
 };
 
-&spi2 {
-	assigned-clocks = <&cru CLK_SPI2>;
-	assigned-clock-rates = <200000000>;
-	num-cs = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+&uart9 {
+	pinctrl-0 = <&uart9m0_xfer>;
 	status = "okay";
+};
 
-	pmic@0 {
-		compatible = "rockchip,rk806";
-		reg = <0x0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-		spi-max-frequency = <1000000>;
-		system-power-controller;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc5v0_sys>;
-		vcc6-supply = <&vcc5v0_sys>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc5v0_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-		vcc10-supply = <&vcc5v0_sys>;
-		vcc11-supply = <&vcc_2v0_pldo_s3>;
-		vcc12-supply = <&vcc5v0_sys>;
-		vcc13-supply = <&vdd2_ddr_s3>;
-		vcc14-supply = <&vdd2_ddr_s3>;
-		vcca-supply = <&vcc5v0_sys>;
-
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		rk806_dvs1_null: dvs1-null-pins {
-			pins = "gpio_pwrctrl1";
-			function = "pin_fun0";
-		};
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
 
-		rk806_dvs2_null: dvs2-null-pins {
-			pins = "gpio_pwrctrl2";
-			function = "pin_fun0";
-		};
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		rk806_dvs3_null: dvs3-null-pins {
-			pins = "gpio_pwrctrl3";
-			function = "pin_fun0";
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
 		};
 
-		regulators {
-			vdd_gpu_s0: dcdc-reg1 {
-				regulator-name = "vdd_gpu_s0";
-				regulator-boot-on;
-				regulator-enable-ramp-delay = <400>;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_cpu_lit_s0: dcdc-reg2 {
-				regulator-name = "vdd_cpu_lit_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_log_s0: dcdc-reg3 {
-				regulator-name = "vdd_log_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <825000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_vdenc_s0: dcdc-reg4 {
-				regulator-name = "vdd_vdenc_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <825000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_ddr_s0: dcdc-reg5 {
-				regulator-name = "vdd_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <900000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			vdd2_ddr_s3: dcdc-reg6 {
-				regulator-name = "vdd2_ddr_s3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_2v0_pldo_s3: dcdc-reg7 {
-				regulator-name = "vdd_2v0_pldo_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2000000>;
-				regulator-max-microvolt = <2000000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2000000>;
-				};
-			};
-
-			vcc_3v3_s3: dcdc-reg8 {
-				regulator-name = "vcc_3v3_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vddq_ddr_s0: dcdc-reg9 {
-				regulator-name = "vddq_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8_s3: dcdc-reg10 {
-				regulator-name = "vcc_1v8_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avcc_1v8_s0: pldo-reg1 {
-				regulator-name = "avcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			/* shorted to avcc_1v8_s0 on the board */
-			vcc_1v8_s0: pldo-reg2 {
-				regulator-name = "vcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avdd_1v2_s0: pldo-reg3 {
-				regulator-name = "avdd_1v2_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3_s0: pldo-reg4 {
-				regulator-name = "vcc_3v3_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd_s0: pldo-reg5 {
-				regulator-name = "vccio_sd_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			pldo6_s3: pldo-reg6 {
-				regulator-name = "pldo6_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd_0v75_s3: nldo-reg1 {
-				regulator-name = "vdd_0v75_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_ddr_pll_s0: nldo-reg2 {
-				regulator-name = "vdd_ddr_pll_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			avdd_0v75_s0: nldo-reg3 {
-				regulator-name = "avdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				/*
-				 * The schematic mentions that actual setting
-				 * should be 0.8375V. RK3588 datasheet specifies
-				 * maximum as 0.825V. So we set datasheet max
-				 * here.
-				 */
-				regulator-min-microvolt = <825000>;
-				regulator-max-microvolt = <825000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v85_s0: nldo-reg4 {
-				regulator-name = "vdd_0v85_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v75_s0: nldo-reg5 {
-				regulator-name = "vdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
 		};
 	};
 };
 
-&tsadc {
-	status = "okay";
-};
+&usb_host0_xhci {
+	usb-role-switch;
 
-&u2phy2 {
-	status = "okay";
-};
-
-&u2phy3 {
-	status = "okay";
-};
-
-&u2phy2_host {
-	phy-supply = <&vcc5v0_usb20>;
-	status = "okay";
-};
-
-&u2phy3_host {
-	phy-supply = <&vcc5v0_usb20>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-0 = <&uart2m0_xfer>;
-	status = "okay";
-};
-
-&uart9 {
-	pinctrl-0 = <&uart9m0_xfer>;
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
+	port {
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
 };
 
-&usb_host1_ohci {
-	status = "okay";
+&vcc3v3_pcie_eth {
+	gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
 };
 
-&vop_mmu {
+&vcc3v3_wf {
 	status = "okay";
 };
 
-&vop {
-	status = "okay";
+&vcc5v0_usb20 {
+	gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&vcc5v0_usb20_en>;
 };
 
 &vp0 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi
new file mode 100644
index 00000000000..a98e804a094
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-maskrom {
+			label = "Mask Rom";
+			linux,code = <KEY_SETUP>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	recovery_button: adc-keys-1 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		status = "disabled";
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	speaker_amp: speaker-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "Speaker Amp";
+		status = "disabled";
+	};
+
+	headphone_amp: headphones-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "Headphones Amp";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_blue_gpio: led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_INDICATOR;
+			function-enumerator = <1>;
+			status = "disabled";
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 70 75 80 100>;
+		fan-supply = <&vcc5v0_sys>;
+		#cooling-cells = <2>;
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		led_blue_pwm: led-1 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			linux,default-trigger = "heartbeat";
+			max-brightness = <255>;
+			status = "disabled";
+		};
+
+		led_green_pwm: led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			function-enumerator = <2>;
+			max-brightness = <255>;
+		};
+	};
+
+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-pcie-wlan";
+		radio-type = "wlan";
+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+	};
+
+	analog_sound: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Analog";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,bitclock-master = <&daicpu>;
+		simple-audio-card,frame-master = <&daicpu>;
+		/*TODO: SARADC_IN3 is used as MIC detection / key input */
+
+		daicpu: simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+			system-clock-frequency = <12288000>;
+		};
+
+		daicodec: simple-audio-card,codec {
+			sound-dai = <&es8388>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie_eth: regulator-vcc3v3-pcie-eth {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie_eth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc3v3_wf: regulator-vcc3v3-wf {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_wf";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc5v0_sys>;
+		status = "disabled";
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_usb20: regulator-vcc5v0-usb20 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc5v0_usb20";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	/* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
+	es8388: audio-codec@11 {
+		compatible = "everest,es8388";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		AVDD-supply = <&vcc_3v3_s0>;
+		DVDD-supply = <&vcc_1v8_s0>;
+		HPVDD-supply = <&vcc_3v3_s0>;
+		PVDD-supply = <&vcc_1v8_s0>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+};
+
+&i2s2_2ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s2m0_lrck
+		     &i2s2m0_sclk
+		     &i2s2m0_sdi
+		     &i2s2m0_sdo>;
+	status = "okay";
+};
+
+&package_thermal {
+	polling-delay = <1000>;
+
+	cooling-maps {
+		map0 {
+			trip = <&package_fan0>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map1 {
+			trip = <&package_fan1>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+	};
+
+	trips {
+		package_fan0: package-fan0 {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&sfc {
+	status = "okay";
+
+	spi_flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vdd2_ddr_s3>;
+		vcc14-supply = <&vdd2_ddr_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-enable-ramp-delay = <400>;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <825000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <825000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			/* shorted to avcc_1v8_s0 on the board */
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				/*
+				 * The schematic mentions that actual setting
+				 * should be 0.8375V. RK3588 datasheet specifies
+				 * maximum as 0.825V. So we set datasheet max
+				 * here.
+				 */
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <825000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_usb20>;
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_usb20>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
index 6d68f70284e..2a059020946 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
@@ -690,10 +690,9 @@
 
 &sdhci {
 	bus-width = <8>;
-	max-frequency = <200000000>;
+	max-frequency = <150000000>;
 	mmc-hs400-1_8v;
 	mmc-hs400-enhanced-strobe;
-	mmc-hs200-1_8v;
 	no-sdio;
 	no-sd;
 	non-removable;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
index 672d748fcc6..f229cb49da6 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
@@ -23,3 +23,7 @@
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };
+
+&mmu600_pcie {
+	status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
index 81a6a05ce13..e8fa449517c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
@@ -386,7 +386,6 @@
 	non-removable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
-	supports-cqe;
 	vmmc-supply = <&vcc_3v3_s3>;
 	vqmmc-supply = <&vcc_1v8_s3>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
index c9749cb5007..d2eddea1840 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
@@ -775,6 +775,15 @@
 	status = "okay";
 };
 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
 &u2phy2 {
 	status = "okay";
 };
@@ -797,6 +806,15 @@
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts b/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
index a251c434354..de219570bbc 100644
--- a/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
+++ b/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
@@ -61,7 +61,7 @@
 			&i2s_port4
 			&spdif_port0
 			&comp_spdif_port0>;
-		hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
 	};
 
 	spdif-out {
diff --git a/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts b/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
index 79f6db2455c..20e5fb724fa 100644
--- a/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
+++ b/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
@@ -61,7 +61,7 @@
 			&i2s_port4
 			&spdif_port0
 			&comp_spdif_port0>;
-		hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
 	};
 
 	spdif-out {
diff --git a/dts/upstream/src/arm64/sprd/sc2731.dtsi b/dts/upstream/src/arm64/sprd/sc2731.dtsi
index 12136e68dad..458685b8246 100644
--- a/dts/upstream/src/arm64/sprd/sc2731.dtsi
+++ b/dts/upstream/src/arm64/sprd/sc2731.dtsi
@@ -94,17 +94,17 @@
 			nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
 		};
 
-		fuel-gauge@a00 {
+		pmic_fgu: fuel-gauge@a00 {
 			compatible = "sprd,sc2731-fgu";
 			reg = <0xa00>;
-			bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
+			battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
 			io-channels = <&pmic_adc 3>, <&pmic_adc 6>;
 			io-channel-names = "bat-temp", "charge-vol";
-			monitored-battery = <&bat>;
 			nvmem-cell-names = "fgu_calib";
 			nvmem-cells = <&fgu_calib>;
 			interrupt-parent = <&sc2731_pmic>;
 			interrupts = <4>;
+			status = "disabled";
 		};
 
 		vibrator@ec8 {
diff --git a/dts/upstream/src/arm64/sprd/sc9863a.dtsi b/dts/upstream/src/arm64/sprd/sc9863a.dtsi
index e5a2857721e..e97000e560e 100644
--- a/dts/upstream/src/arm64/sprd/sc9863a.dtsi
+++ b/dts/upstream/src/arm64/sprd/sc9863a.dtsi
@@ -163,18 +163,18 @@
 		ap_clk: clock-controller@21500000 {
 			compatible = "sprd,sc9863a-ap-clk";
 			reg = <0 0x21500000 0 0x1000>;
-			clocks = <&ext_32k>, <&ext_26m>;
-			clock-names = "ext-32k", "ext-26m";
+			clocks = <&ext_26m>, <&ext_32k>;
+			clock-names = "ext-26m", "ext-32k";
 			#clock-cells = <1>;
 		};
 
 		aon_clk: clock-controller@402d0000 {
 			compatible = "sprd,sc9863a-aon-clk";
 			reg = <0 0x402d0000 0 0x1000>;
-			clocks = <&ext_26m>, <&rco_100m>,
-				 <&ext_32k>, <&ext_4m>;
-			clock-names = "ext-26m", "rco-100m",
-				      "ext-32k", "ext-4m";
+			clocks = <&ext_26m>, <&ext_32k>,
+				 <&ext_4m>, <&rco_100m>;
+			clock-names = "ext-26m", "ext-32k",
+				      "ext-4m", "rco-100m";
 			#clock-cells = <1>;
 		};
 
@@ -288,7 +288,7 @@
 				};
 			};
 
-			in-port {
+			in-ports {
 				port {
 					etf_little_in: endpoint {
 						remote-endpoint =
diff --git a/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts b/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
index 095b24a3131..b1fa817ece1 100644
--- a/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
+++ b/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
@@ -71,8 +71,8 @@
 		compatible = "simple-battery";
 		charge-full-design-microamp-hours = <1900000>;
 		charge-term-current-microamp = <120000>;
-		constant_charge_voltage_max_microvolt = <4350000>;
-		internal-resistance-micro-ohms = <250000>;
+		constant-charge-voltage-max-microvolt = <4350000>;
+		factory-internal-resistance-micro-ohms = <250000>;
 		ocv-capacity-celsius = <20>;
 		ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
 			<4022000 85>, <3983000 80>, <3949000 75>,
@@ -84,6 +84,11 @@
 	};
 };
 
+&pmic_fgu {
+	monitored-battery = <&bat>;
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/st/stm32mp251.dtsi b/dts/upstream/src/arm64/st/stm32mp251.dtsi
index 6fe12e3bd7d..f3c6cdfd700 100644
--- a/dts/upstream/src/arm64/st/stm32mp251.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp251.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	#address-cells = <2>;
@@ -237,6 +238,21 @@
 			#access-controller-cells = <1>;
 			ranges;
 
+			i2s2: audio-controller@400b0000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x400b0000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI2_R>;
+				dmas = <&hpdma 51 0x43 0x12>,
+				       <&hpdma 52 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 23>;
+				status = "disabled";
+			};
+
 			spi2: spi@400b0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -252,6 +268,21 @@
 				status = "disabled";
 			};
 
+			i2s3: audio-controller@400c0000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x400c0000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI3_R>;
+				dmas = <&hpdma 53 0x43 0x12>,
+				       <&hpdma 54 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 24>;
+				status = "disabled";
+			};
+
 			spi3: spi@400c0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -267,6 +298,20 @@
 				status = "disabled";
 			};
 
+			spdifrx: audio-controller@400d0000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x400d0000 0x400>;
+				clocks = <&rcc CK_KER_SPDIFRX>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&hpdma 71 0x43 0x212>,
+				       <&hpdma 72 0x43 0x212>;
+				dma-names = "rx", "rx-ctrl";
+				access-controllers = <&rifsc 30>;
+				status = "disabled";
+			};
+
 			usart2: serial@400e0000 {
 				compatible = "st,stm32h7-uart";
 				reg = <0x400e0000 0x400>;
@@ -439,6 +484,21 @@
 				status = "disabled";
 			};
 
+			i2s1: audio-controller@40230000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x40230000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI1_R>;
+				dmas = <&hpdma 49 0x43 0x12>,
+				       <&hpdma 50 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 22>;
+				status = "disabled";
+			};
+
 			spi1: spi@40230000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -484,6 +544,108 @@
 				status = "disabled";
 			};
 
+			sai1: sai@40290000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x40290000 0x4>, <0x4029a3f0 0x10>;
+				ranges = <0 0x40290000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI1>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				access-controllers = <&rifsc 49>;
+				status = "disabled";
+
+				sai1a: audio-controller@40290004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI1>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 73 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai1b: audio-controller@40290024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI1>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 74 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
+			sai2: sai@402a0000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>;
+				ranges = <0 0x402a0000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI2>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				access-controllers = <&rifsc 50>;
+				status = "disabled";
+
+				sai2a: audio-controller@402a0004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI2>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 75 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai2b: audio-controller@402a0024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI2>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 76 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
+			sai3: sai@402b0000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>;
+				ranges = <0 0x402b0000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI3>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				access-controllers = <&rifsc 51>;
+				status = "disabled";
+
+				sai3a: audio-controller@402b0004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI3>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 77 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@502b0024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI3>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 78 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
 			uart9: serial@402c0000 {
 				compatible = "st,stm32h7-uart";
 				reg = <0x402c0000 0x400>;
@@ -508,6 +670,40 @@
 				status = "disabled";
 			};
 
+			sai4: sai@40340000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x40340000 0x4>, <0x4034a3f0 0x10>;
+				ranges = <0 0x40340000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI4>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				access-controllers = <&rifsc 52>;
+				status = "disabled";
+
+				sai4a: audio-controller@40340004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI4>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 79 0x63 0x21>;
+					status = "disabled";
+				};
+
+				sai4b: audio-controller@40340024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI4>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 80 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
 			spi6: spi@40350000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -603,6 +799,44 @@
 				status = "disabled";
 			};
 
+			csi: csi@48020000 {
+				compatible = "st,stm32mp25-csi";
+				reg = <0x48020000 0x2000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CSI_R>;
+				clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>,
+					 <&rcc CK_KER_CSIPHY>;
+				clock-names = "pclk", "txesc", "csi2phy";
+				access-controllers = <&rifsc 86>;
+				status = "disabled";
+			};
+
+			dcmipp: dcmipp@48030000 {
+				compatible = "st,stm32mp25-dcmipp";
+				reg = <0x48030000 0x1000>;
+				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc DCMIPP_R>;
+				clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
+				clock-names = "kclk", "mclk";
+				access-controllers = <&rifsc 87>;
+				status = "disabled";
+			};
+
+			combophy: phy@480c0000 {
+				compatible = "st,stm32mp25-combophy";
+				reg = <0x480c0000 0x1000>;
+				#phy-cells = <1>;
+				clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
+				clock-names = "apb", "ker";
+				resets = <&rcc USB3PCIEPHY_R>;
+				reset-names = "phy";
+				access-controllers = <&rifsc 67>;
+				power-domains = <&CLUSTER_PD>;
+				wakeup-source;
+				interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+				status = "disabled";
+			};
+
 			sdmmc1: mmc@48220000 {
 				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00353180>;
diff --git a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
index 6f393b08278..1b88485a62a 100644
--- a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
+++ b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
@@ -27,6 +27,44 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	clocks {
+		clk_ext_camera: clk-ext-camera {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+
+		pad_clk: pad-clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+		};
+	};
+
+	imx335_2v9: regulator-2v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-avdd";
+		regulator-min-microvolt = <2900000>;
+		regulator-max-microvolt = <2900000>;
+		regulator-always-on;
+	};
+
+	imx335_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-ovdd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	imx335_1v2: regulator-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-dvdd";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x1 0x0>;
@@ -50,6 +88,46 @@
 	status = "okay";
 };
 
+&combophy {
+	clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>;
+	clock-names = "apb", "ker", "pad";
+	status = "okay";
+};
+
+&csi {
+	vdd-supply =  <&scmi_vddcore>;
+	vdda18-supply = <&scmi_v1v8>;
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			csi_sink: endpoint {
+				remote-endpoint = <&imx335_ep>;
+				data-lanes = <1 2>;
+				bus-type = <4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			csi_source: endpoint {
+				remote-endpoint = <&dcmipp_0>;
+			};
+		};
+	};
+};
+
+&dcmipp {
+	status = "okay";
+	port {
+		dcmipp_0: endpoint {
+			remote-endpoint = <&csi_source>;
+			bus-type = <4>;
+		};
+	};
+};
+
 &ethernet2 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth2_rgmii_pins_a>;
@@ -81,6 +159,25 @@
 	i2c-scl-falling-time-ns = <13>;
 	clock-frequency = <400000>;
 	status = "okay";
+
+	imx335: camera@1a {
+		compatible = "sony,imx335";
+		reg = <0x1a>;
+		clocks = <&clk_ext_camera>;
+		avdd-supply = <&imx335_2v9>;
+		ovdd-supply = <&imx335_1v8>;
+		dvdd-supply = <&imx335_1v2>;
+		reset-gpios = <&gpioi 7 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+		port {
+			imx335_ep: endpoint {
+				remote-endpoint = <&csi_sink>;
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+				link-frequencies = /bits/ 64 <594000000>;
+			};
+		};
+	};
 };
 
 &i2c8 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
index 7cd727d10a5..7d355aa73ea 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
@@ -23,7 +23,6 @@
 		interrupt-controller;
 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
-		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
diff --git a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
index 5952874fe42..2ef4cbaec78 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
@@ -95,6 +95,16 @@
 		regulator-boot-on;
 	};
 
+	vddshv_3v3: regulator-vddshv-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDSHV0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_3v3>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -313,6 +323,7 @@
 		compatible = "atmel,24c32";
 		pagesize = <32>;
 		reg = <0x50>;
+		vcc-supply = <&vddshv_3v3>;
 	};
 
 	i2c_som_rtc: rtc@52 {
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
index ee96f4f6deb..75c80290b12 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
@@ -610,7 +610,7 @@
 		reg = <1>;
 		reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <25>;
-		reset-deassert-us = <60000>; /* T2 */
+		reset-deassert-us = <35>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/ti/k3-am625-sk.dts b/dts/upstream/src/arm64/ti/k3-am625-sk.dts
index ae81ebb39d0..2fbfa371934 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-sk.dts
@@ -219,13 +219,6 @@
 	};
 };
 
-&mailbox0_cluster0 {
-	mbox_m4_0: mbox-m4-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
 &fss {
 	bootph-all;
 };
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
index a93e2cd7b8c..a1daba7b1fa 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
@@ -18,7 +18,6 @@
 		compatible = "arm,gic-v3";
 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
-		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
index 0b1dd5390cd..b2c8f535174 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
@@ -2,9 +2,11 @@
 /*
  * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
  *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/bus/ti-sysc.h>
+
 &cbass_wakeup {
 	wkup_conf: bus@43000000 {
 		compatible = "simple-bus";
@@ -38,14 +40,34 @@
 		};
 	};
 
-	wkup_uart0: serial@2b300000 {
-		compatible = "ti,am64-uart", "ti,am654-uart";
-		reg = <0x00 0x2b300000 0x00 0x100>;
-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+	target-module@2b300050 {
+		compatible = "ti,sysc-omap2", "ti,sysc";
+		reg = <0 0x2b300050 0 0x4>,
+		      <0 0x2b300054 0 0x4>,
+		      <0 0x2b300058 0 0x4>;
+		reg-names = "rev", "sysc", "syss";
+		ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+				 SYSC_OMAP2_SOFTRESET |
+				 SYSC_OMAP2_AUTOIDLE)>;
+		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+				<SYSC_IDLE_NO>,
+				<SYSC_IDLE_SMART>,
+				<SYSC_IDLE_SMART_WKUP>;
+		ti,syss-mask = <1>;
+		ti,no-reset-on-init;
 		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 114 0>;
-		clock-names = "fclk";
-		status = "disabled";
+		clock-names = "fck";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x2b300000 0x100000>;
+
+		wkup_uart0: serial@0 {
+			compatible = "ti,am64-uart", "ti,am654-uart";
+			reg = <0 0x100>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+	       };
 	};
 
 	wkup_i2c0: i2c@2b200000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
index 41e1c24b114..6e3beb5c2e0 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
@@ -651,6 +651,7 @@
 			interrupt-names = "host", "peripheral";
 			maximum-speed = "high-speed";
 			dr_mode = "otg";
+			bootph-all;
 			snps,usb2-gadget-lpm-disable;
 			snps,usb2-lpm-disable;
 		};
@@ -768,6 +769,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster1: mailbox@29010000 {
@@ -777,6 +779,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster2: mailbox@29020000 {
@@ -786,6 +789,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster3: mailbox@29030000 {
@@ -795,6 +799,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	ecap0: pwm@23100000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
index 7f3dc39e12b..ad71d2f27f5 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
@@ -621,6 +621,8 @@
 };
 
 &mailbox0_cluster0 {
+	status = "okay";
+
 	mbox_r5_0: mbox-r5-0 {
 		ti,mbox-rx = <0 0 0>;
 		ti,mbox-tx = <1 0 0>;
@@ -628,6 +630,8 @@
 };
 
 &mailbox0_cluster1 {
+	status = "okay";
+
 	mbox_mcu_r5_0: mbox-mcu-r5-0 {
 		ti,mbox-rx = <0 0 0>;
 		ti,mbox-tx = <1 0 0>;
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
index d364c247833..922cad14c9f 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
@@ -112,6 +112,25 @@
 		regulator-boot-on;
 	};
 
+	vcc_3v3_hdmi: regulator-vcc-3v3-hdmi {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3_HDMI";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_sw>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_1v2_hdmi: regulator-vcc-1v2-hdmi {
+		compatible = "regulator-fixed";
+		regulator-name = "HDMI_CVCC";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	vcc_3v3_mmc: regulator-vcc-3v3-mmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VCC_3V3_MMC";
@@ -367,6 +386,9 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&hdmi_int_pins_default>;
 
+		iovcc-supply = <&vcc_3v3_hdmi>;
+		cvcc12-supply = <&vcc_1v2_hdmi>;
+
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -376,6 +398,7 @@
 
 				sii9022_in: endpoint {
 					remote-endpoint = <&dpi1_out>;
+					bus-width = <16>;
 				};
 			};
 
@@ -393,6 +416,7 @@
 		compatible = "atmel,24c02";
 		pagesize = <16>;
 		reg = <0x51>;
+		vcc-supply = <&vcc_3v3_mmc>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
index 6957b3e44c8..2f129e8cd5b 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
@@ -256,7 +256,7 @@
 
 	main_usb1_pins_default: main-usb1-default-pins {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
+			AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */
 		>;
 	};
 
@@ -315,6 +315,10 @@
 	};
 };
 
+&cpsw_mac_syscon {
+	bootph-all;
+};
+
 &wkup_uart0 {
 	/* WKUP UART0 is used by DM firmware */
 	bootph-pre-ram;
diff --git a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
index c66289a4362..324eb44c258 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
@@ -1227,6 +1227,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x30000000 0x80000>;
+		clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
+			 <&k3_clks 81 3>,  /* icssg0_iep_clk */
+			 <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */
+			 <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */
+			 <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */
+			 <&k3_clks 81 19>, /* icssg0_uart_clk */
+			 <&k3_clks 81 20>; /* icssg0_iclk */
+		assigned-clocks = <&k3_clks 81 0>;
+		assigned-clock-parents = <&k3_clks 81 2>;
 
 		icssg0_mem: memories@0 {
 			reg = <0x0 0x2000>,
@@ -1252,7 +1261,7 @@
 					clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
 						 <&k3_clks 81 20>; /* icssg0_iclk */
 					assigned-clocks = <&icssg0_coreclk_mux>;
-					assigned-clock-parents = <&k3_clks 81 20>;
+					assigned-clock-parents = <&k3_clks 81 0>;
 				};
 
 				icssg0_iepclk_mux: iepclk-mux@30 {
@@ -1397,6 +1406,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x30080000 0x80000>;
+		clocks = <&k3_clks 82 0>,  /* icssg1_core_clk */
+			 <&k3_clks 82 3>,  /* icssg1_iep_clk */
+			 <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */
+			 <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */
+			 <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */
+			 <&k3_clks 82 19>, /* icssg1_uart_clk */
+			 <&k3_clks 82 20>; /* icssg1_iclk */
+		assigned-clocks = <&k3_clks 82 0>;
+		assigned-clock-parents = <&k3_clks 82 2>;
 
 		icssg1_mem: memories@0 {
 			reg = <0x0 0x2000>,
@@ -1422,7 +1440,7 @@
 					clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
 						 <&k3_clks 82 20>;  /* icssg1_iclk */
 					assigned-clocks = <&icssg1_coreclk_mux>;
-					assigned-clock-parents = <&k3_clks 82 20>;
+					assigned-clock-parents = <&k3_clks 82 0>;
 				};
 
 				icssg1_iepclk_mux: iepclk-mux@30 {
diff --git a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dts
index bd9a5caf20d..023b2a6aaa5 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dts
@@ -2,17 +2,19 @@
 /*
  * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
  *
- * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E.
+ * DTS for SolidRun AM642 HummingBoard-T,
+ * running on Cortex A53, with PCI-E.
+ *
  */
 
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/phy/phy.h>
+#include "k3-am642-hummingboard-t.dts"
 
 #include "k3-serdes.h"
 
+/ {
+	model = "SolidRun AM642 HummingBoard-T with PCI-E";
+};
+
 &pcie0_rc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie0_default_pins>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dts
index ffcc3bd3c7b..ee9bd618f37 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dts
@@ -2,16 +2,19 @@
 /*
  * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
  *
- * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1.
+ * DTS for SolidRun AM642 HummingBoard-T,
+ * running on Cortex A53, with USB-3.1 Gen 1.
+ *
  */
 
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/phy/phy.h>
+#include "k3-am642-hummingboard-t.dts"
 
 #include "k3-serdes.h"
 
+/ {
+	model = "SolidRun AM642 HummingBoard-T with USB-3.1 Gen 1";
+};
+
 &serdes0 {
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index e06a3b178b3..8f64d6272b1 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -201,8 +201,6 @@
 		reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
@@ -230,8 +228,6 @@
 		reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
@@ -242,8 +238,6 @@
 		reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
diff --git a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
index 44dfbdf8927..9be6bba28c2 100644
--- a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
+++ b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
@@ -50,11 +50,71 @@
 			no-map;
 		};
 
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
 		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
 			compatible = "shared-dma-pool";
 			reg = <0x00 0xa0100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c7x_0_memory_region: c7x-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c7x_1_memory_region: c7x-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x1c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	vsys_5v0: regulator-1 {
@@ -391,3 +451,101 @@
 	ti,fails-without-test-cd;
 	status = "okay";
 };
+
+&mailbox0_cluster0 {
+	status = "okay";
+
+	mbox_wkup_r5_0: mbox-wkup-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	status = "okay";
+
+	mbox_mcu_r5_0: mbox-mcu-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	status = "okay";
+
+	mbox_c7x_0: mbox-c7x-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "okay";
+
+	mbox_main_r5_0: mbox-main-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c7x_1: mbox-c7x-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+/* Timers are used by Remoteproc firmware */
+&main_timer0 {
+	status = "reserved";
+};
+
+&main_timer1 {
+	status = "reserved";
+};
+
+&main_timer2 {
+	status = "reserved";
+};
+
+&wkup_r5fss0 {
+	status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
+	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+			<&wkup_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0 {
+	status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0 {
+	status = "okay";
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&c7x_0 {
+	mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
+	memory-region = <&c7x_0_dma_memory_region>,
+			<&c7x_0_memory_region>;
+	status = "okay";
+};
+
+&c7x_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
+	memory-region = <&c7x_1_dma_memory_region>,
+			<&c7x_1_memory_region>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso
new file mode 100644
index 00000000000..455736e378c
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * AM68-SK board.
+ *
+ * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie1_ep: pcie-ep@2910000 {
+		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <2>;
+		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 276 41>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes0_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso b/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso
new file mode 100644
index 00000000000..9a5bcf282a9
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration
+ * on AM69-SK.
+ *
+ * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie0_ep: pcie-ep@2900000 {
+		compatible = "ti,j784s4-pcie-ep";
+		reg = <0x00 0x02900000 0x00 0x1000>,
+		      <0x00 0x02907000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x10000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 332 0>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes1_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk.dts b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
index 1e36965a140..b85227052f9 100644
--- a/dts/upstream/src/arm64/ti/k3-am69-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
@@ -484,6 +484,12 @@
 		>;
 	};
 
+	main_usbss0_pins_default: main-usbss0-default-pins {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+
 };
 
 &wkup_pmx0 {
@@ -755,6 +761,7 @@
 				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka3: buck3 {
@@ -763,6 +770,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka4: buck4 {
@@ -771,6 +779,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka5: buck5 {
@@ -779,6 +788,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa1: ldo1 {
@@ -787,6 +797,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa2: ldo2 {
@@ -795,6 +806,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa3: ldo3 {
@@ -803,6 +815,7 @@
 				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa4: ldo4 {
@@ -811,6 +824,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 		};
 	};
@@ -1299,6 +1313,14 @@
 		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
 	};
+
+	serdes0_usb_link: phy@3 {
+		reg = <3>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz0 4>;
+	};
 };
 
 &serdes_wiz1 {
@@ -1339,3 +1361,22 @@
 	phy-names = "pcie-phy";
 	num-lanes = <1>;
 };
+
+&usb_serdes_mux {
+	idle-states = <0>; /* USB0 to SERDES0 */
+};
+
+&usbss0 {
+	status = "okay";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "otg";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
index db43e7e10b7..f684ce6ad9a 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -409,6 +409,10 @@
 		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
 };
 
+&mcu_spi1 {
+	mux-controls = <&spi1_linkdis 0>;
+};
+
 &usb_serdes_mux {
 	idle-states = <1>; /* USB0 to SERDES lane 3 */
 	bootph-all;
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index 6a845386587..56ab144fea0 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -184,6 +184,13 @@
 			reg = <0x4040 0x4>;
 			#phy-cells = <1>;
 		};
+
+		spi1_linkdis: mux-controller@4060 {
+			compatible = "reg-mux";
+			reg = <0x4060 0x4>;
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x0 0x1>;
+		};
 	};
 
 	wkup_conf: bus@43000000 {
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso
new file mode 100644
index 00000000000..a8cccdcf3e3
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie1_ep: pcie-ep@2910000 {
+		compatible = "ti,j721e-pcie-ep";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <2>;
+		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 240 1>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes1_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
index a00f4a7d20d..d184e9c1a0a 100644
--- a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
@@ -359,6 +359,13 @@
 			J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
 		>;
 	};
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */
+		>;
+	};
+
 };
 
 &cpsw3g {
@@ -406,6 +413,13 @@
 
 &mcu_pmx0 {
 
+	mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */
+			J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */
+		>;
+	};
+
 	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
 		pinctrl-single,pins = <
 			J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
@@ -459,6 +473,87 @@
 	clock-frequency = <400000>;
 	status = "okay";
 	bootph-all;
+
+	tps65224: pmic@48 {
+		compatible = "ti,tps65224-q1";
+		reg = <0x48>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+		ti,primary-pmic;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		buck12-supply = <&vsys_io_3v3>;
+		buck3-supply = <&vsys_io_3v3>;
+		buck4-supply = <&vsys_io_3v3>;
+
+		ldo1-supply = <&vsys_io_3v3>;
+		ldo2-supply = <&vsys_io_3v3>;
+		ldo3-supply = <&vsys_io_3v3>;
+
+		regulators {
+
+			buck1: buck1 {
+				regulator-name = "vcc1v8_io_buck1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				bootph-all;
+			};
+
+			buck2: buck2 {
+				regulator-name = "vcc1v1_ddr_buck2";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3: buck3 {
+				regulator-name = "vcc0v85_ram_buck3";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4: buck4 {
+				regulator-name = "vcc0v75_ioret_buck4";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: ldo1 {
+				regulator-name = "vdda1v8_pll_ldo1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: ldo2 {
+				regulator-name = "dvdd3v3_ldo2";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: ldo3 {
+				regulator-name = "vdd1v85_phy_ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+	       };
+	};
 };
 
 &k3_clks {
@@ -812,3 +907,10 @@
 &mcu_gpio0 {
 	status = "okay";
 };
+
+&mcu_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_i2c0_pins_default>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
index b2e2b9f507a..2664f74a9c7 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -635,6 +635,7 @@
 				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka3: buck3 {
@@ -643,6 +644,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka4: buck4 {
@@ -651,6 +653,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka5: buck5 {
@@ -659,6 +662,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa1: ldo1 {
@@ -667,6 +671,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa2: ldo2 {
@@ -675,6 +680,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa3: ldo3 {
@@ -683,6 +689,7 @@
 				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa4: ldo4 {
@@ -691,6 +698,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 		};
 	};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
index 7721852c1f6..83bbf94b58d 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -224,7 +224,7 @@
 	};
 
 	main_pmx0: pinctrl@11c000 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x11c000 0x00 0x120>;
 		#pinctrl-cells = <1>;
@@ -234,7 +234,7 @@
 
 	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 	main_timerio_input: pinctrl@104200 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x104200 0x00 0x50>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -243,7 +243,7 @@
 
 	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 	main_timerio_output: pinctrl@104280 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x104280 0x00 0x20>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -2040,7 +2040,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 376 1>;
+		clocks = <&k3_clks 376 0>;
 		status = "disabled";
 	};
 
@@ -2051,7 +2051,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 377 1>;
+		clocks = <&k3_clks 377 0>;
 		status = "disabled";
 	};
 
@@ -2062,7 +2062,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 378 1>;
+		clocks = <&k3_clks 378 0>;
 		status = "disabled";
 	};
 
@@ -2073,7 +2073,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 379 1>;
+		clocks = <&k3_clks 379 0>;
 		status = "disabled";
 	};
 
@@ -2084,7 +2084,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 380 1>;
+		clocks = <&k3_clks 380 0>;
 		status = "disabled";
 	};
 
@@ -2095,7 +2095,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 381 1>;
+		clocks = <&k3_clks 381 0>;
 		status = "disabled";
 	};
 
@@ -2106,7 +2106,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 382 1>;
+		clocks = <&k3_clks 382 0>;
 		status = "disabled";
 	};
 
@@ -2117,7 +2117,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 383 1>;
+		clocks = <&k3_clks 383 0>;
 		status = "disabled";
 	};
 
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
index 9638130caec..52e2965a3bf 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
@@ -76,7 +76,7 @@
 	};
 
 	wkup_pmx0: pinctrl@4301c000 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c000 0x00 0x034>;
 		#pinctrl-cells = <1>;
@@ -85,7 +85,7 @@
 	};
 
 	wkup_pmx1: pinctrl@4301c038 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c038 0x00 0x02c>;
 		#pinctrl-cells = <1>;
@@ -94,7 +94,7 @@
 	};
 
 	wkup_pmx2: pinctrl@4301c068 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c068 0x00 0x120>;
 		#pinctrl-cells = <1>;
@@ -103,7 +103,7 @@
 	};
 
 	wkup_pmx3: pinctrl@4301c190 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c190 0x00 0x004>;
 		#pinctrl-cells = <1>;
@@ -125,7 +125,7 @@
 
 	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
 	mcu_timerio_input: pinctrl@40f04200 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x40f04200 0x00 0x28>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -136,7 +136,7 @@
 
 	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
 	mcu_timerio_output: pinctrl@40f04280 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x40f04280 0x00 0x28>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
diff --git a/dts/upstream/src/arm64/ti/k3-pinctrl.h b/dts/upstream/src/arm64/ti/k3-pinctrl.h
index 22b8d73cfd3..cac7cccc111 100644
--- a/dts/upstream/src/arm64/ti/k3-pinctrl.h
+++ b/dts/upstream/src/arm64/ti/k3-pinctrl.h
@@ -12,6 +12,12 @@
 #define PULLTYPESEL_SHIFT	(17)
 #define RXACTIVE_SHIFT		(18)
 #define DEBOUNCE_SHIFT		(11)
+#define FORCE_DS_EN_SHIFT	(15)
+#define DS_EN_SHIFT		(24)
+#define DS_OUT_DIS_SHIFT	(25)
+#define DS_OUT_VAL_SHIFT	(26)
+#define DS_PULLUD_EN_SHIFT	(27)
+#define DS_PULLTYPE_SEL_SHIFT	(28)
 
 #define PULL_DISABLE		(1 << PULLUDEN_SHIFT)
 #define PULL_ENABLE		(0 << PULLUDEN_SHIFT)
@@ -38,6 +44,19 @@
 #define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
 #define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
 
+#define PIN_DS_FORCE_DISABLE		(0 << FORCE_DS_EN_SHIFT)
+#define PIN_DS_FORCE_ENABLE		(1 << FORCE_DS_EN_SHIFT)
+#define PIN_DS_IO_OVERRIDE_DISABLE	(0 << DS_IO_OVERRIDE_EN_SHIFT)
+#define PIN_DS_IO_OVERRIDE_ENABLE	(1 << DS_IO_OVERRIDE_EN_SHIFT)
+#define PIN_DS_OUT_ENABLE		(0 << DS_OUT_DIS_SHIFT)
+#define PIN_DS_OUT_DISABLE		(1 << DS_OUT_DIS_SHIFT)
+#define PIN_DS_OUT_VALUE_ZERO		(0 << DS_OUT_VAL_SHIFT)
+#define PIN_DS_OUT_VALUE_ONE		(1 << DS_OUT_VAL_SHIFT)
+#define PIN_DS_PULLUD_ENABLE		(0 << DS_PULLUD_EN_SHIFT)
+#define PIN_DS_PULLUD_DISABLE		(1 << DS_PULLUD_EN_SHIFT)
+#define PIN_DS_PULL_DOWN		(0 << DS_PULLTYPE_SEL_SHIFT)
+#define PIN_DS_PULL_UP			(1 << DS_PULLTYPE_SEL_SHIFT)
+
 /* Default mux configuration for gpio-ranges to use with pinctrl */
 #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
 
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
index 467f084c646..e11d282462b 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
@@ -1306,11 +1306,14 @@
 				      "dp_vtc_pixel_clk_in";
 			power-domains = <&zynqmp_firmware PD_DP>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
-			dma-names = "vid0", "vid1", "vid2", "gfx0";
+			dma-names = "vid0", "vid1", "vid2", "gfx0",
+				    "aud0", "aud1";
 			dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
-			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
 
 			ports {
 				#address-cells = <1>;
diff --git a/dts/upstream/src/mips/mobileye/eyeq5.dtsi b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
index 5d73e8320b8..a84e6e72061 100644
--- a/dts/upstream/src/mips/mobileye/eyeq5.dtsi
+++ b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
@@ -49,6 +49,28 @@
 		mhm_reserved_0: the-mhm-reserved-0@0 {
 			reg = <0x8 0x00000000 0x0 0x0000800>;
 		};
+
+		nvram@461fe00 {
+			compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem";
+			reg = <0x0 0x0461fe00 0x0 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			no-map;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				eth0_mac: mac@7c {
+					reg = <0x7c 0x6>;
+				};
+
+				eth1_mac: mac@82 {
+					reg = <0x82 0x6>;
+				};
+			};
+		};
 	};
 
 	aliases {
diff --git a/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi b/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe..6367112e614 100644
--- a/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
+++ b/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,8 @@
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {
diff --git a/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts
new file mode 100644
index 00000000000..1d617b40a2d
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k1.dtsi"
+#include "k1-pinctrl.dtsi"
+
+/ {
+	model = "Banana Pi BPI-F3";
+	compatible = "bananapi,bpi-f3", "spacemit,k1";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_2_cfg>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 00000000000..a8eac5517f8
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+	uart0_2_cfg: uart0-2-cfg {
+		uart0-2-pins {
+			pinmux = <K1_PADCONF(68, 2)>,
+				 <K1_PADCONF(69, 2)>;
+
+			bias-pull-up = <0>;
+			drive-strength = <32>;
+		};
+	};
+};
diff --git a/dts/upstream/src/riscv/spacemit/k1.dtsi b/dts/upstream/src/riscv/spacemit/k1.dtsi
new file mode 100644
index 00000000000..c670ebf8fa1
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1.dtsi
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SpacemiT K1";
+	compatible = "spacemit,k1";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_0>;
+				};
+				core1 {
+					cpu = <&cpu_1>;
+				};
+				core2 {
+					cpu = <&cpu_2>;
+				};
+				core3 {
+					cpu = <&cpu_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_4>;
+				};
+				core1 {
+					cpu = <&cpu_5>;
+				};
+				core2 {
+					cpu = <&cpu_6>;
+				};
+				core3 {
+					cpu = <&cpu_7>;
+				};
+			};
+		};
+
+		cpu_0: cpu@0 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_1: cpu@1 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_2: cpu@2 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_3: cpu@3 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_4: cpu@4 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <4>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_5: cpu@5 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <5>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_6: cpu@6 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <6>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_7: cpu@7 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <7>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cluster0_l2_cache: l2-cache0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+
+		cluster1_l2_cache: l2-cache1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@d4017000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017000 0x0 0x100>;
+			interrupts = <42>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@d4017100 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017100 0x0 0x100>;
+			interrupts = <44>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@d4017200 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017200 0x0 0x100>;
+			interrupts = <45>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@d4017300 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017300 0x0 0x100>;
+			interrupts = <46>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@d4017400 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017400 0x0 0x100>;
+			interrupts = <47>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart6: serial@d4017500 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017500 0x0 0x100>;
+			interrupts = <48>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart7: serial@d4017600 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017600 0x0 0x100>;
+			interrupts = <49>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart8: serial@d4017700 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017700 0x0 0x100>;
+			interrupts = <50>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart9: serial@d4017800 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017800 0x0 0x100>;
+			interrupts = <51>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@d401e000 {
+			compatible = "spacemit,k1-pinctrl";
+			reg = <0x0 0xd401e000 0x0 0x400>;
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xe0000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>,
+					      <&cpu5_intc 11>, <&cpu5_intc 9>,
+					      <&cpu6_intc 11>, <&cpu6_intc 9>,
+					      <&cpu7_intc 11>, <&cpu7_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			riscv,ndev = <159>;
+		};
+
+		clint: timer@e4000000 {
+			compatible = "spacemit,k1-clint", "sifive,clint0";
+			reg = <0x0 0xe4000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+
+		sec_uart1: serial@f0612000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xf0612000 0x0 0x100>;
+			interrupts = <43>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "reserved"; /* for TEE usage */
+		};
+	};
+};
diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
index 0d248b671d4..3bd62ab7852 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
@@ -53,7 +53,23 @@
 	status = "okay";
 };
 
+&sysgpio {
+	usb0_pins: usb0-0 {
+		vbus-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &usb0 {
-	dr_mode = "peripheral";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
index fe4a490ecc6..b764d4d92fd 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
@@ -80,7 +80,23 @@
 	status = "okay";
 };
 
+&sysgpio {
+	usb0_pins: usb0-0 {
+		vbus-pins {
+			pinmux = <GPIOMUX(25,  GPOUT_SYS_USB_DRIVE_VBUS,
+					       GPOEN_ENABLE,
+					       GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &usb0 {
-	dr_mode = "peripheral";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h b/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
index 256de17f526..ae49c908e7f 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
+++ b/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
@@ -89,7 +89,7 @@
 #define GPOUT_SYS_SDIO1_DATA1			59
 #define GPOUT_SYS_SDIO1_DATA2			60
 #define GPOUT_SYS_SDIO1_DATA3			61
-#define GPOUT_SYS_SDIO1_DATA4			63
+#define GPOUT_SYS_SDIO1_DATA4			62
 #define GPOUT_SYS_SDIO1_DATA5			63
 #define GPOUT_SYS_SDIO1_DATA6			64
 #define GPOUT_SYS_SDIO1_DATA7			65
diff --git a/dts/upstream/src/riscv/thead/th1520.dtsi b/dts/upstream/src/riscv/thead/th1520.dtsi
index acfe030e803..52733641776 100644
--- a/dts/upstream/src/riscv/thead/th1520.dtsi
+++ b/dts/upstream/src/riscv/thead/th1520.dtsi
@@ -599,6 +599,22 @@
 			status = "disabled";
 		};
 
+		mbox_910t: mailbox@ffffc38000 {
+			compatible = "thead,th1520-mbox";
+			reg = <0xff 0xffc38000 0x0 0x6000>,
+			      <0xff 0xffc40000 0x0 0x6000>,
+			      <0xff 0xffc4c000 0x0 0x2000>,
+			      <0xff 0xffc54000 0x0 0x2000>;
+			reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
+			clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>,
+				 <&clk CLK_MBOX3>;
+			clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
+				      "clk-remote-icu2";
+			interrupt-parent = <&plic>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <1>;
+		};
+
 		gpio@fffff41000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff 0xfff41000 0x0 0x1000>;
diff --git a/fs/Kconfig b/fs/Kconfig
index 5e83cb27059..e0b0b901e1d 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -8,6 +8,8 @@ source "fs/btrfs/Kconfig"
 
 source "fs/cbfs/Kconfig"
 
+source "fs/exfat/Kconfig"
+
 source "fs/ext4/Kconfig"
 
 source "fs/fat/Kconfig"
diff --git a/fs/Makefile b/fs/Makefile
index 1c2ff180bda..ce5e74257a0 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -16,6 +16,7 @@ obj-y				+= fs.o
 obj-$(CONFIG_FS_BTRFS) += btrfs/
 obj-$(CONFIG_FS_CBFS) += cbfs/
 obj-$(CONFIG_CMD_CRAMFS) += cramfs/
+obj-$(CONFIG_FS_EXFAT) += exfat/
 obj-$(CONFIG_FS_EXT4) += ext4/
 obj-$(CONFIG_FS_FAT) += fat/
 obj-$(CONFIG_FS_JFFS2) += jffs2/
diff --git a/fs/exfat/Kconfig b/fs/exfat/Kconfig
new file mode 100644
index 00000000000..bce61e8fcc7
--- /dev/null
+++ b/fs/exfat/Kconfig
@@ -0,0 +1,5 @@
+config FS_EXFAT
+	bool "Enable EXFAT filesystem support"
+	imply CMD_FS_GENERIC if CMDLINE
+	help
+	  This provides read/write support for EXFAT filesystem.
diff --git a/fs/exfat/Makefile b/fs/exfat/Makefile
new file mode 100644
index 00000000000..550c0683d65
--- /dev/null
+++ b/fs/exfat/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_FS_EXFAT) += \
+	cluster.o \
+	io.o \
+	lookup.o \
+	mount.o \
+	node.o \
+	repair.o \
+	time.o \
+	utf.o \
+	utils.o
diff --git a/fs/exfat/byteorder.h b/fs/exfat/byteorder.h
new file mode 100644
index 00000000000..98b93c700c3
--- /dev/null
+++ b/fs/exfat/byteorder.h
@@ -0,0 +1,68 @@
+/*
+	byteorder.h (12.01.10)
+	Endianness stuff. exFAT uses little-endian byte order.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef BYTEORDER_H_INCLUDED
+#define BYTEORDER_H_INCLUDED
+
+#include "platform.h"
+#include <stdint.h>
+#include <stddef.h>
+
+typedef struct { uint16_t __u16; } le16_t;
+typedef struct { uint32_t __u32; } le32_t;
+typedef struct { uint64_t __u64; } le64_t;
+
+#if EXFAT_BYTE_ORDER == EXFAT_LITTLE_ENDIAN
+
+static inline uint16_t le16_to_cpu(le16_t v) { return v.__u16; }
+static inline uint32_t le32_to_cpu(le32_t v) { return v.__u32; }
+static inline uint64_t le64_to_cpu(le64_t v) { return v.__u64; }
+
+static inline le16_t cpu_to_le16(uint16_t v) { le16_t t = {v}; return t; }
+static inline le32_t cpu_to_le32(uint32_t v) { le32_t t = {v}; return t; }
+static inline le64_t cpu_to_le64(uint64_t v) { le64_t t = {v}; return t; }
+
+typedef size_t bitmap_t;
+
+#elif EXFAT_BYTE_ORDER == EXFAT_BIG_ENDIAN
+
+static inline uint16_t le16_to_cpu(le16_t v)
+	{ return exfat_bswap16(v.__u16); }
+static inline uint32_t le32_to_cpu(le32_t v)
+	{ return exfat_bswap32(v.__u32); }
+static inline uint64_t le64_to_cpu(le64_t v)
+	{ return exfat_bswap64(v.__u64); }
+
+static inline le16_t cpu_to_le16(uint16_t v)
+	{ le16_t t = {exfat_bswap16(v)}; return t; }
+static inline le32_t cpu_to_le32(uint32_t v)
+	{ le32_t t = {exfat_bswap32(v)}; return t; }
+static inline le64_t cpu_to_le64(uint64_t v)
+	{ le64_t t = {exfat_bswap64(v)}; return t; }
+
+typedef unsigned char bitmap_t;
+
+#else
+#error Wow! You have a PDP machine?!
+#endif
+
+#endif /* ifndef BYTEORDER_H_INCLUDED */
diff --git a/fs/exfat/cluster.c b/fs/exfat/cluster.c
new file mode 100644
index 00000000000..4ee6135fd84
--- /dev/null
+++ b/fs/exfat/cluster.c
@@ -0,0 +1,496 @@
+/*
+	cluster.c (03.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+#include <string.h>
+#include <inttypes.h>
+
+/*
+ * Sector to absolute offset.
+ */
+static off_t s2o(const struct exfat* ef, off_t sector)
+{
+	return sector << ef->sb->sector_bits;
+}
+
+/*
+ * Cluster to sector.
+ */
+static off_t c2s(const struct exfat* ef, cluster_t cluster)
+{
+	if (cluster < EXFAT_FIRST_DATA_CLUSTER)
+		exfat_bug("invalid cluster number %u", cluster);
+	return le32_to_cpu(ef->sb->cluster_sector_start) +
+		((off_t) (cluster - EXFAT_FIRST_DATA_CLUSTER) << ef->sb->spc_bits);
+}
+
+/*
+ * Cluster to absolute offset.
+ */
+off_t exfat_c2o(const struct exfat* ef, cluster_t cluster)
+{
+	return s2o(ef, c2s(ef, cluster));
+}
+
+/*
+ * Sector to cluster.
+ */
+static cluster_t s2c(const struct exfat* ef, off_t sector)
+{
+	return ((sector - le32_to_cpu(ef->sb->cluster_sector_start)) >>
+			ef->sb->spc_bits) + EXFAT_FIRST_DATA_CLUSTER;
+}
+
+/*
+ * Size in bytes to size in clusters (rounded upwards).
+ */
+static uint32_t bytes2clusters(const struct exfat* ef, uint64_t bytes)
+{
+	uint64_t cluster_size = CLUSTER_SIZE(*ef->sb);
+	return DIV_ROUND_UP(bytes, cluster_size);
+}
+
+cluster_t exfat_next_cluster(const struct exfat* ef,
+		const struct exfat_node* node, cluster_t cluster)
+{
+	le32_t next;
+	off_t fat_offset;
+
+	if (cluster < EXFAT_FIRST_DATA_CLUSTER)
+		exfat_bug("bad cluster 0x%x", cluster);
+
+	if (node->is_contiguous)
+		return cluster + 1;
+	fat_offset = s2o(ef, le32_to_cpu(ef->sb->fat_sector_start))
+		+ cluster * sizeof(cluster_t);
+	if (exfat_pread(ef->dev, &next, sizeof(next), fat_offset) < 0)
+		return EXFAT_CLUSTER_BAD; /* the caller should handle this and print
+		                             appropriate error message */
+	return le32_to_cpu(next);
+}
+
+cluster_t exfat_advance_cluster(const struct exfat* ef,
+		struct exfat_node* node, uint32_t count)
+{
+	uint32_t i;
+
+	if (node->fptr_index > count)
+	{
+		node->fptr_index = 0;
+		node->fptr_cluster = node->start_cluster;
+	}
+
+	for (i = node->fptr_index; i < count; i++)
+	{
+		node->fptr_cluster = exfat_next_cluster(ef, node, node->fptr_cluster);
+		if (CLUSTER_INVALID(*ef->sb, node->fptr_cluster))
+			break; /* the caller should handle this and print appropriate 
+			          error message */
+	}
+	node->fptr_index = count;
+	return node->fptr_cluster;
+}
+
+static cluster_t find_bit_and_set(bitmap_t* bitmap, size_t start, size_t end)
+{
+	const size_t start_index = start / sizeof(bitmap_t) / 8;
+	const size_t end_index = DIV_ROUND_UP(end, sizeof(bitmap_t) * 8);
+	size_t i;
+	size_t start_bitindex;
+	size_t end_bitindex;
+	size_t c;
+
+	for (i = start_index; i < end_index; i++)
+	{
+		if (bitmap[i] == (bitmap_t) ~((bitmap_t) 0))
+			continue;
+		start_bitindex = MAX(i * sizeof(bitmap_t) * 8, start);
+		end_bitindex = MIN((i + 1) * sizeof(bitmap_t) * 8, end);
+		for (c = start_bitindex; c < end_bitindex; c++)
+			if (BMAP_GET(bitmap, c) == 0)
+			{
+				BMAP_SET(bitmap, c);
+				return c + EXFAT_FIRST_DATA_CLUSTER;
+			}
+	}
+	return EXFAT_CLUSTER_END;
+}
+
+static int flush_nodes(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_node* p;
+
+	for (p = node->child; p != NULL; p = p->next)
+	{
+		int rc = flush_nodes(ef, p);
+		if (rc != 0)
+			return rc;
+	}
+	return exfat_flush_node(ef, node);
+}
+
+int exfat_flush_nodes(struct exfat* ef)
+{
+	return flush_nodes(ef, ef->root);
+}
+
+int exfat_flush(struct exfat* ef)
+{
+	if (ef->cmap.dirty)
+	{
+		if (exfat_pwrite(ef->dev, ef->cmap.chunk,
+				BMAP_SIZE(ef->cmap.chunk_size),
+				exfat_c2o(ef, ef->cmap.start_cluster)) < 0)
+		{
+			exfat_error("failed to write clusters bitmap");
+			return -EIO;
+		}
+		ef->cmap.dirty = false;
+	}
+
+	return 0;
+}
+
+static bool set_next_cluster(const struct exfat* ef, bool contiguous,
+		cluster_t current, cluster_t next)
+{
+	off_t fat_offset;
+	le32_t next_le32;
+
+	if (contiguous)
+		return true;
+	fat_offset = s2o(ef, le32_to_cpu(ef->sb->fat_sector_start))
+		+ current * sizeof(cluster_t);
+	next_le32 = cpu_to_le32(next);
+	if (exfat_pwrite(ef->dev, &next_le32, sizeof(next_le32), fat_offset) < 0)
+	{
+		exfat_error("failed to write the next cluster %#x after %#x", next,
+				current);
+		return false;
+	}
+	return true;
+}
+
+static cluster_t allocate_cluster(struct exfat* ef, cluster_t hint)
+{
+	cluster_t cluster;
+
+	hint -= EXFAT_FIRST_DATA_CLUSTER;
+	if (hint >= ef->cmap.chunk_size)
+		hint = 0;
+
+	cluster = find_bit_and_set(ef->cmap.chunk, hint, ef->cmap.chunk_size);
+	if (cluster == EXFAT_CLUSTER_END)
+		cluster = find_bit_and_set(ef->cmap.chunk, 0, hint);
+	if (cluster == EXFAT_CLUSTER_END)
+	{
+		exfat_error("no free space left");
+		return EXFAT_CLUSTER_END;
+	}
+
+	ef->cmap.dirty = true;
+	return cluster;
+}
+
+static void free_cluster(struct exfat* ef, cluster_t cluster)
+{
+	if (cluster - EXFAT_FIRST_DATA_CLUSTER >= ef->cmap.size)
+		exfat_bug("caller must check cluster validity (%#x, %#x)", cluster,
+				ef->cmap.size);
+
+	BMAP_CLR(ef->cmap.chunk, cluster - EXFAT_FIRST_DATA_CLUSTER);
+	ef->cmap.dirty = true;
+}
+
+static bool make_noncontiguous(const struct exfat* ef, cluster_t first,
+		cluster_t last)
+{
+	cluster_t c;
+
+	for (c = first; c < last; c++)
+		if (!set_next_cluster(ef, false, c, c + 1))
+			return false;
+	return true;
+}
+
+static int shrink_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference);
+
+static int grow_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference)
+{
+	cluster_t previous;
+	cluster_t next;
+	uint32_t allocated = 0;
+
+	if (difference == 0)
+		exfat_bug("zero clusters count passed");
+
+	if (node->start_cluster != EXFAT_CLUSTER_FREE)
+	{
+		/* get the last cluster of the file */
+		previous = exfat_advance_cluster(ef, node, current - 1);
+		if (CLUSTER_INVALID(*ef->sb, previous))
+		{
+			exfat_error("invalid cluster 0x%x while growing", previous);
+			return -EIO;
+		}
+	}
+	else
+	{
+		if (node->fptr_index != 0)
+			exfat_bug("non-zero pointer index (%u)", node->fptr_index);
+		/* file does not have clusters (i.e. is empty), allocate
+		   the first one for it */
+		previous = allocate_cluster(ef, 0);
+		if (CLUSTER_INVALID(*ef->sb, previous))
+			return -ENOSPC;
+		node->fptr_cluster = node->start_cluster = previous;
+		allocated = 1;
+		/* file consists of only one cluster, so it's contiguous */
+		node->is_contiguous = true;
+	}
+
+	while (allocated < difference)
+	{
+		next = allocate_cluster(ef, previous + 1);
+		if (CLUSTER_INVALID(*ef->sb, next))
+		{
+			if (allocated != 0)
+				shrink_file(ef, node, current + allocated, allocated);
+			return -ENOSPC;
+		}
+		if (next != previous + 1 && node->is_contiguous)
+		{
+			/* it's a pity, but we are not able to keep the file contiguous
+			   anymore */
+			if (!make_noncontiguous(ef, node->start_cluster, previous))
+				return -EIO;
+			node->is_contiguous = false;
+			node->is_dirty = true;
+		}
+		if (!set_next_cluster(ef, node->is_contiguous, previous, next))
+			return -EIO;
+		previous = next;
+		allocated++;
+	}
+
+	if (!set_next_cluster(ef, node->is_contiguous, previous,
+			EXFAT_CLUSTER_END))
+		return -EIO;
+	return 0;
+}
+
+static int shrink_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference)
+{
+	cluster_t previous;
+	cluster_t next;
+
+	if (difference == 0)
+		exfat_bug("zero difference passed");
+	if (node->start_cluster == EXFAT_CLUSTER_FREE)
+		exfat_bug("unable to shrink empty file (%u clusters)", current);
+	if (current < difference)
+		exfat_bug("file underflow (%u < %u)", current, difference);
+
+	/* crop the file */
+	if (current > difference)
+	{
+		cluster_t last = exfat_advance_cluster(ef, node,
+				current - difference - 1);
+		if (CLUSTER_INVALID(*ef->sb, last))
+		{
+			exfat_error("invalid cluster 0x%x while shrinking", last);
+			return -EIO;
+		}
+		previous = exfat_next_cluster(ef, node, last);
+		if (!set_next_cluster(ef, node->is_contiguous, last,
+				EXFAT_CLUSTER_END))
+			return -EIO;
+	}
+	else
+	{
+		previous = node->start_cluster;
+		node->start_cluster = EXFAT_CLUSTER_FREE;
+		node->is_dirty = true;
+	}
+	node->fptr_index = 0;
+	node->fptr_cluster = node->start_cluster;
+
+	/* free remaining clusters */
+	while (difference--)
+	{
+		if (CLUSTER_INVALID(*ef->sb, previous))
+		{
+			exfat_error("invalid cluster 0x%x while freeing after shrink",
+					previous);
+			return -EIO;
+		}
+
+		next = exfat_next_cluster(ef, node, previous);
+		if (!set_next_cluster(ef, node->is_contiguous, previous,
+				EXFAT_CLUSTER_FREE))
+			return -EIO;
+		free_cluster(ef, previous);
+		previous = next;
+	}
+	return 0;
+}
+
+static bool erase_raw(struct exfat* ef, size_t size, off_t offset)
+{
+	if (exfat_pwrite(ef->dev, ef->zero_cluster, size, offset) < 0)
+	{
+		exfat_error("failed to erase %zu bytes at %"PRId64, size, offset);
+		return false;
+	}
+	return true;
+}
+
+static int erase_range(struct exfat* ef, struct exfat_node* node,
+		uint64_t begin, uint64_t end)
+{
+	uint64_t cluster_boundary;
+	cluster_t cluster;
+
+	if (begin >= end)
+		return 0;
+
+	cluster_boundary = (begin | (CLUSTER_SIZE(*ef->sb) - 1)) + 1;
+	cluster = exfat_advance_cluster(ef, node,
+			begin / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while erasing", cluster);
+		return -EIO;
+	}
+	/* erase from the beginning to the closest cluster boundary */
+	if (!erase_raw(ef, MIN(cluster_boundary, end) - begin,
+			exfat_c2o(ef, cluster) + begin % CLUSTER_SIZE(*ef->sb)))
+		return -EIO;
+	/* erase whole clusters */
+	while (cluster_boundary < end)
+	{
+		cluster = exfat_next_cluster(ef, node, cluster);
+		/* the cluster cannot be invalid because we have just allocated it */
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+			exfat_bug("invalid cluster 0x%x after allocation", cluster);
+		if (!erase_raw(ef, CLUSTER_SIZE(*ef->sb), exfat_c2o(ef, cluster)))
+			return -EIO;
+		cluster_boundary += CLUSTER_SIZE(*ef->sb);
+	}
+	return 0;
+}
+
+int exfat_truncate(struct exfat* ef, struct exfat_node* node, uint64_t size,
+		bool erase)
+{
+	uint32_t c1 = bytes2clusters(ef, node->size);
+	uint32_t c2 = bytes2clusters(ef, size);
+	int rc = 0;
+
+	if (node->references == 0 && node->parent)
+		exfat_bug("no references, node changes can be lost");
+
+	if (node->size == size)
+		return 0;
+
+	if (c1 < c2)
+		rc = grow_file(ef, node, c1, c2 - c1);
+	else if (c1 > c2)
+		rc = shrink_file(ef, node, c1, c1 - c2);
+
+	if (rc != 0)
+		return rc;
+
+	if (erase)
+	{
+		rc = erase_range(ef, node, node->valid_size, size);
+		if (rc != 0)
+			return rc;
+		node->valid_size = size;
+	}
+	else
+	{
+		node->valid_size = MIN(node->valid_size, size);
+	}
+
+	exfat_update_mtime(node);
+	node->size = size;
+	node->is_dirty = true;
+	return 0;
+}
+
+uint32_t exfat_count_free_clusters(const struct exfat* ef)
+{
+	uint32_t free_clusters = 0;
+	uint32_t i;
+
+	for (i = 0; i < ef->cmap.size; i++)
+		if (BMAP_GET(ef->cmap.chunk, i) == 0)
+			free_clusters++;
+	return free_clusters;
+}
+
+static int find_used_clusters(const struct exfat* ef,
+		cluster_t* a, cluster_t* b)
+{
+	const cluster_t end = le32_to_cpu(ef->sb->cluster_count);
+
+	/* find first used cluster */
+	for (*a = *b + 1; *a < end; (*a)++)
+		if (BMAP_GET(ef->cmap.chunk, *a - EXFAT_FIRST_DATA_CLUSTER))
+			break;
+	if (*a >= end)
+		return 1;
+
+	/* find last contiguous used cluster */
+	for (*b = *a; *b < end; (*b)++)
+		if (BMAP_GET(ef->cmap.chunk, *b - EXFAT_FIRST_DATA_CLUSTER) == 0)
+		{
+			(*b)--;
+			break;
+		}
+
+	return 0;
+}
+
+int exfat_find_used_sectors(const struct exfat* ef, off_t* a, off_t* b)
+{
+	cluster_t ca, cb;
+
+	if (*a == 0 && *b == 0)
+		ca = cb = EXFAT_FIRST_DATA_CLUSTER - 1;
+	else
+	{
+		ca = s2c(ef, *a);
+		cb = s2c(ef, *b);
+	}
+	if (find_used_clusters(ef, &ca, &cb) != 0)
+		return 1;
+	if (*a != 0 || *b != 0)
+		*a = c2s(ef, ca);
+	*b = c2s(ef, cb) + (CLUSTER_SIZE(*ef->sb) - 1) / SECTOR_SIZE(*ef->sb);
+	return 0;
+}
diff --git a/fs/exfat/compiler.h b/fs/exfat/compiler.h
new file mode 100644
index 00000000000..48658280839
--- /dev/null
+++ b/fs/exfat/compiler.h
@@ -0,0 +1,69 @@
+/*
+	compiler.h (09.06.13)
+	Compiler-specific definitions. Note that unknown compiler is not a
+	showstopper.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef COMPILER_H_INCLUDED
+#define COMPILER_H_INCLUDED
+
+#if __STDC_VERSION__ < 199901L
+#error C99-compliant compiler is required
+#endif
+
+#if defined(__clang__)
+
+#define PRINTF __attribute__((format(printf, 1, 2)))
+#define NORETURN __attribute__((noreturn))
+#define PACKED __attribute__((packed))
+#define UNUSED __attribute__((unused))
+#if __has_extension(c_static_assert)
+#define USE_C11_STATIC_ASSERT
+#endif
+
+#elif defined(__GNUC__)
+
+#define PRINTF __attribute__((format(printf, 1, 2)))
+#define NORETURN __attribute__((noreturn))
+#define PACKED __attribute__((packed))
+#define UNUSED __attribute__((unused))
+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
+#define USE_C11_STATIC_ASSERT
+#endif
+
+#else
+
+#define PRINTF
+#define NORETURN
+#define PACKED
+#define UNUSED
+
+#endif
+
+#ifdef USE_C11_STATIC_ASSERT
+#define STATIC_ASSERT(cond) _Static_assert(cond, #cond)
+#else
+#define CONCAT2(a, b) a ## b
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define STATIC_ASSERT(cond) \
+	extern void CONCAT1(static_assert, __LINE__)(int x[(cond) ? 1 : -1])
+#endif
+
+#endif /* ifndef COMPILER_H_INCLUDED */
diff --git a/fs/exfat/exfat.h b/fs/exfat/exfat.h
new file mode 100644
index 00000000000..cce3e3021ca
--- /dev/null
+++ b/fs/exfat/exfat.h
@@ -0,0 +1,259 @@
+/*
+	exfat.h (29.08.09)
+	Definitions of structures and constants used in exFAT file system
+	implementation.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef EXFAT_H_INCLUDED
+#define EXFAT_H_INCLUDED
+
+#ifndef ANDROID
+/* Android.bp is used instead of autotools when targeting Android */
+#include "config.h"
+#endif
+#include "compiler.h"
+#include "exfatfs.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+#include <stdbool.h>
+#ifndef __UBOOT__
+#include <sys/stat.h>
+#include <sys/types.h>
+#endif
+
+#define EXFAT_NAME_MAX 255
+/* UTF-16 encodes code points up to U+FFFF as single 16-bit code units.
+   UTF-8 uses up to 3 bytes (i.e. 8-bit code units) to encode code points
+   up to U+FFFF. One additional character is for null terminator. */
+#define EXFAT_UTF8_NAME_BUFFER_MAX (EXFAT_NAME_MAX * 3 + 1)
+#define EXFAT_UTF8_ENAME_BUFFER_MAX (EXFAT_ENAME_MAX * 3 + 1)
+
+#define SECTOR_SIZE(sb) (1 << (sb).sector_bits)
+#define CLUSTER_SIZE(sb) (SECTOR_SIZE(sb) << (sb).spc_bits)
+#define CLUSTER_INVALID(sb, c) ((c) < EXFAT_FIRST_DATA_CLUSTER || \
+	(c) - EXFAT_FIRST_DATA_CLUSTER >= le32_to_cpu((sb).cluster_count))
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#ifndef __UBOOT__
+#define DIV_ROUND_UP(x, d) (((x) + (d) - 1) / (d))
+#endif
+#define ROUND_UP(x, d) (DIV_ROUND_UP(x, d) * (d))
+
+#define BMAP_SIZE(count) (ROUND_UP(count, sizeof(bitmap_t) * 8) / 8)
+#define BMAP_BLOCK(index) ((index) / sizeof(bitmap_t) / 8)
+#define BMAP_MASK(index) ((bitmap_t) 1 << ((index) % (sizeof(bitmap_t) * 8)))
+#define BMAP_GET(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] & BMAP_MASK(index))
+#define BMAP_SET(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] |= BMAP_MASK(index))
+#define BMAP_CLR(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] &= ~BMAP_MASK(index))
+
+#define EXFAT_REPAIR(hook, ef, ...) \
+	(exfat_ask_to_fix(ef) && exfat_fix_ ## hook(ef, __VA_ARGS__))
+
+/* The size of off_t type must be 64 bits. File systems larger than 2 GB will
+   be corrupted with 32-bit off_t. */
+STATIC_ASSERT(sizeof(off_t) == 8);
+
+struct exfat_node
+{
+	struct exfat_node* parent;
+	struct exfat_node* child;
+	struct exfat_node* next;
+	struct exfat_node* prev;
+
+	int references;
+	uint32_t fptr_index;
+	cluster_t fptr_cluster;
+	off_t entry_offset;
+	cluster_t start_cluster;
+	uint16_t attrib;
+	uint8_t continuations;
+	bool is_contiguous : 1;
+	bool is_cached : 1;
+	bool is_dirty : 1;
+	bool is_unlinked : 1;
+	uint64_t valid_size;
+	uint64_t size;
+	time_t mtime, atime;
+	le16_t name[EXFAT_NAME_MAX + 1];
+};
+
+enum exfat_mode
+{
+	EXFAT_MODE_RO,
+	EXFAT_MODE_RW,
+	EXFAT_MODE_ANY,
+};
+
+struct exfat_dev;
+
+struct exfat
+{
+	struct exfat_dev* dev;
+	struct exfat_super_block* sb;
+	uint16_t* upcase;
+	struct exfat_node* root;
+	struct
+	{
+		cluster_t start_cluster;
+		uint32_t size;				/* in bits */
+		bitmap_t* chunk;
+		uint32_t chunk_size;		/* in bits */
+		bool dirty;
+	}
+	cmap;
+	char label[EXFAT_UTF8_ENAME_BUFFER_MAX];
+	void* zero_cluster;
+	int dmask, fmask;
+	uid_t uid;
+	gid_t gid;
+	int ro;
+	bool noatime;
+	enum { EXFAT_REPAIR_NO, EXFAT_REPAIR_ASK, EXFAT_REPAIR_YES } repair;
+};
+
+/* in-core nodes iterator */
+struct exfat_iterator
+{
+	struct exfat_node* parent;
+	struct exfat_node* current;
+};
+
+struct exfat_human_bytes
+{
+	uint64_t value;
+	const char* unit;
+};
+
+extern int exfat_errors;
+extern int exfat_errors_fixed;
+
+#ifdef __UBOOT__
+#define exfat_bug(fmt, args...)		log_crit(fmt, ##args)
+#define exfat_error(fmt, args...)	log_err(fmt, ##args)
+#define exfat_warn(fmt, args...)	log_warning(fmt, ##args)
+#define exfat_debug(fmt, args...)	log_debug(fmt, ##args)
+#else
+void exfat_bug(const char* format, ...) PRINTF NORETURN;
+void exfat_error(const char* format, ...) PRINTF;
+void exfat_warn(const char* format, ...) PRINTF;
+void exfat_debug(const char* format, ...) PRINTF;
+#endif
+
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode);
+int exfat_close(struct exfat_dev* dev);
+int exfat_fsync(struct exfat_dev* dev);
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev);
+off_t exfat_get_size(const struct exfat_dev* dev);
+off_t exfat_seek(struct exfat_dev* dev, off_t offset, int whence);
+ssize_t exfat_read(struct exfat_dev* dev, void* buffer, size_t size);
+ssize_t exfat_write(struct exfat_dev* dev, const void* buffer, size_t size);
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset);
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset);
+ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node,
+		void* buffer, size_t size, off_t offset);
+ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node,
+		const void* buffer, size_t size, off_t offset);
+
+int exfat_opendir(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_iterator* it);
+void exfat_closedir(struct exfat* ef, struct exfat_iterator* it);
+struct exfat_node* exfat_readdir(struct exfat_iterator* it);
+int exfat_lookup(struct exfat* ef, struct exfat_node** node,
+		const char* path);
+int exfat_split(struct exfat* ef, struct exfat_node** parent,
+		struct exfat_node** node, le16_t* name, const char* path);
+
+off_t exfat_c2o(const struct exfat* ef, cluster_t cluster);
+cluster_t exfat_next_cluster(const struct exfat* ef,
+		const struct exfat_node* node, cluster_t cluster);
+cluster_t exfat_advance_cluster(const struct exfat* ef,
+		struct exfat_node* node, uint32_t count);
+int exfat_flush_nodes(struct exfat* ef);
+int exfat_flush(struct exfat* ef);
+int exfat_truncate(struct exfat* ef, struct exfat_node* node, uint64_t size,
+		bool erase);
+uint32_t exfat_count_free_clusters(const struct exfat* ef);
+int exfat_find_used_sectors(const struct exfat* ef, off_t* a, off_t* b);
+
+void exfat_stat(const struct exfat* ef, const struct exfat_node* node,
+		struct stat* stbuf);
+void exfat_get_name(const struct exfat_node* node,
+		char buffer[EXFAT_UTF8_NAME_BUFFER_MAX]);
+uint16_t exfat_start_checksum(const struct exfat_entry_meta1* entry);
+uint16_t exfat_add_checksum(const void* entry, uint16_t sum);
+le16_t exfat_calc_checksum(const struct exfat_entry* entries, int n);
+uint32_t exfat_vbr_start_checksum(const void* sector, size_t size);
+uint32_t exfat_vbr_add_checksum(const void* sector, size_t size, uint32_t sum);
+le16_t exfat_calc_name_hash(const struct exfat* ef, const le16_t* name,
+		size_t length);
+void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb);
+void exfat_print_info(const struct exfat_super_block* sb,
+		uint32_t free_clusters);
+bool exfat_match_option(const char* options, const char* option_name);
+
+int exfat_utf16_to_utf8(char* output, const le16_t* input, size_t outsize,
+		size_t insize);
+int exfat_utf8_to_utf16(le16_t* output, const char* input, size_t outsize,
+		size_t insize);
+size_t exfat_utf16_length(const le16_t* str);
+
+struct exfat_node* exfat_get_node(struct exfat_node* node);
+void exfat_put_node(struct exfat* ef, struct exfat_node* node);
+int exfat_cleanup_node(struct exfat* ef, struct exfat_node* node);
+int exfat_cache_directory(struct exfat* ef, struct exfat_node* dir);
+void exfat_reset_cache(struct exfat* ef);
+int exfat_flush_node(struct exfat* ef, struct exfat_node* node);
+int exfat_unlink(struct exfat* ef, struct exfat_node* node);
+int exfat_rmdir(struct exfat* ef, struct exfat_node* node);
+int exfat_mknod(struct exfat* ef, const char* path);
+int exfat_mkdir(struct exfat* ef, const char* path);
+int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path);
+void exfat_utimes(struct exfat_node* node, const struct timespec tv[2]);
+void exfat_update_atime(struct exfat_node* node);
+void exfat_update_mtime(struct exfat_node* node);
+const char* exfat_get_label(struct exfat* ef);
+int exfat_set_label(struct exfat* ef, const char* label);
+
+int exfat_soil_super_block(const struct exfat* ef);
+int exfat_mount(struct exfat* ef, const char* spec, const char* options);
+void exfat_unmount(struct exfat* ef);
+
+time_t exfat_exfat2unix(le16_t date, le16_t time, uint8_t centisec,
+		uint8_t tzoffset);
+void exfat_unix2exfat(time_t unix_time, le16_t* date, le16_t* time,
+		uint8_t* centisec, uint8_t* tzoffset);
+void exfat_tzset(void);
+
+bool exfat_ask_to_fix(const struct exfat* ef);
+bool exfat_fix_invalid_vbr_checksum(const struct exfat* ef, void* sector,
+		uint32_t vbr_checksum);
+bool exfat_fix_invalid_node_checksum(const struct exfat* ef,
+		struct exfat_node* node);
+bool exfat_fix_unknown_entry(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entry, off_t offset);
+
+#endif /* ifndef EXFAT_H_INCLUDED */
diff --git a/fs/exfat/exfatfs.h b/fs/exfat/exfatfs.h
new file mode 100644
index 00000000000..fa59aab47b6
--- /dev/null
+++ b/fs/exfat/exfatfs.h
@@ -0,0 +1,200 @@
+/*
+	exfatfs.h (29.08.09)
+	Definitions of structures and constants used in exFAT file system.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef EXFATFS_H_INCLUDED
+#define EXFATFS_H_INCLUDED
+
+#ifdef __UBOOT__
+#include <linux/stat.h>
+#include <linux/types.h>
+#include <log.h>
+#include <stdint.h>
+#include <vsprintf.h>
+
+struct timespec {
+	time_t	tv_sec;		/* seconds */
+	long	tv_nsec;	/* nanoseconds */
+};
+
+#define time(t)		1741234567	/* Thu Mar  6 05:16:07 CET 2025 */
+#define geteuid(n)	1000
+#define getegid(n)	1000
+#define strtol(n, e, b)	simple_strtol(n, e, b)
+#define off_t		unsigned long long
+#endif
+
+#include "byteorder.h"
+#include "compiler.h"
+
+typedef uint32_t cluster_t;		/* cluster number */
+
+#define EXFAT_FIRST_DATA_CLUSTER 2
+#define EXFAT_LAST_DATA_CLUSTER 0xfffffff6
+
+#define EXFAT_CLUSTER_FREE         0 /* free cluster */
+#define EXFAT_CLUSTER_BAD 0xfffffff7 /* cluster contains bad sector */
+#define EXFAT_CLUSTER_END 0xffffffff /* final cluster of file or directory */
+
+#define EXFAT_STATE_MOUNTED 2
+
+struct exfat_super_block
+{
+	uint8_t jump[3];				/* 0x00 jmp and nop instructions */
+	uint8_t oem_name[8];			/* 0x03 "EXFAT   " */
+	uint8_t	__unused1[53];			/* 0x0B always 0 */
+	le64_t sector_start;			/* 0x40 partition first sector */
+	le64_t sector_count;			/* 0x48 partition sectors count */
+	le32_t fat_sector_start;		/* 0x50 FAT first sector */
+	le32_t fat_sector_count;		/* 0x54 FAT sectors count */
+	le32_t cluster_sector_start;	/* 0x58 first cluster sector */
+	le32_t cluster_count;			/* 0x5C total clusters count */
+	le32_t rootdir_cluster;			/* 0x60 first cluster of the root dir */
+	le32_t volume_serial;			/* 0x64 volume serial number */
+	struct							/* 0x68 FS version */
+	{
+		uint8_t minor;
+		uint8_t major;
+	}
+	version;
+	le16_t volume_state;			/* 0x6A volume state flags */
+	uint8_t sector_bits;			/* 0x6C sector size as (1 << n) */
+	uint8_t spc_bits;				/* 0x6D sectors per cluster as (1 << n) */
+	uint8_t fat_count;				/* 0x6E always 1 */
+	uint8_t drive_no;				/* 0x6F always 0x80 */
+	uint8_t allocated_percent;		/* 0x70 percentage of allocated space */
+	uint8_t __unused2[397];			/* 0x71 always 0 */
+	le16_t boot_signature;			/* the value of 0xAA55 */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_super_block) == 512);
+
+#define EXFAT_ENTRY_VALID     0x80
+#define EXFAT_ENTRY_CONTINUED 0x40
+#define EXFAT_ENTRY_OPTIONAL  0x20
+
+#define EXFAT_ENTRY_BITMAP    (0x01 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_UPCASE    (0x02 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_LABEL     (0x03 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_FILE      (0x05 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_FILE_INFO (0x00 | EXFAT_ENTRY_VALID | EXFAT_ENTRY_CONTINUED)
+#define EXFAT_ENTRY_FILE_NAME (0x01 | EXFAT_ENTRY_VALID | EXFAT_ENTRY_CONTINUED)
+#define EXFAT_ENTRY_FILE_TAIL (0x00 | EXFAT_ENTRY_VALID \
+                                    | EXFAT_ENTRY_CONTINUED \
+                                    | EXFAT_ENTRY_OPTIONAL)
+
+struct exfat_entry					/* common container for all entries */
+{
+	uint8_t type;					/* any of EXFAT_ENTRY_xxx */
+	uint8_t data[31];
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry) == 32);
+
+#define EXFAT_ENAME_MAX 15
+
+struct exfat_entry_bitmap			/* allocated clusters bitmap */
+{
+	uint8_t type;					/* EXFAT_ENTRY_BITMAP */
+	uint8_t __unknown1[19];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_bitmap) == 32);
+
+#define EXFAT_UPCASE_CHARS 0x10000
+
+struct exfat_entry_upcase			/* upper case translation table */
+{
+	uint8_t type;					/* EXFAT_ENTRY_UPCASE */
+	uint8_t __unknown1[3];
+	le32_t checksum;
+	uint8_t __unknown2[12];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_upcase) == 32);
+
+struct exfat_entry_label			/* volume label */
+{
+	uint8_t type;					/* EXFAT_ENTRY_LABEL */
+	uint8_t length;					/* number of characters */
+	le16_t name[EXFAT_ENAME_MAX];	/* in UTF-16LE */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_label) == 32);
+
+#define EXFAT_ATTRIB_RO     0x01
+#define EXFAT_ATTRIB_HIDDEN 0x02
+#define EXFAT_ATTRIB_SYSTEM 0x04
+#define EXFAT_ATTRIB_VOLUME 0x08
+#define EXFAT_ATTRIB_DIR    0x10
+#define EXFAT_ATTRIB_ARCH   0x20
+
+struct exfat_entry_meta1			/* file or directory info (part 1) */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE */
+	uint8_t continuations;
+	le16_t checksum;
+	le16_t attrib;					/* combination of EXFAT_ATTRIB_xxx */
+	le16_t __unknown1;
+	le16_t crtime, crdate;			/* creation date and time */
+	le16_t mtime, mdate;			/* latest modification date and time */
+	le16_t atime, adate;			/* latest access date and time */
+	uint8_t crtime_cs;				/* creation time in cs (centiseconds) */
+	uint8_t mtime_cs;				/* latest modification time in cs */
+	uint8_t crtime_tzo, mtime_tzo, atime_tzo;	/* timezone offset encoded */
+	uint8_t __unknown2[7];
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_meta1) == 32);
+
+#define EXFAT_FLAG_ALWAYS1		(1u << 0)
+#define EXFAT_FLAG_CONTIGUOUS	(1u << 1)
+
+struct exfat_entry_meta2			/* file or directory info (part 2) */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE_INFO */
+	uint8_t flags;					/* combination of EXFAT_FLAG_xxx */
+	uint8_t __unknown1;
+	uint8_t name_length;
+	le16_t name_hash;
+	le16_t __unknown2;
+	le64_t valid_size;				/* in bytes, less or equal to size */
+	uint8_t __unknown3[4];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_meta2) == 32);
+
+struct exfat_entry_name				/* file or directory name */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE_NAME */
+	uint8_t __unknown;
+	le16_t name[EXFAT_ENAME_MAX];	/* in UTF-16LE */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_name) == 32);
+
+#endif /* ifndef EXFATFS_H_INCLUDED */
diff --git a/fs/exfat/io.c b/fs/exfat/io.c
new file mode 100644
index 00000000000..81e82829c72
--- /dev/null
+++ b/fs/exfat/io.c
@@ -0,0 +1,1000 @@
+/*
+	io.c (02.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <inttypes.h>
+#ifndef __UBOOT__
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#if defined(__APPLE__)
+#include <sys/disk.h>
+#elif defined(__OpenBSD__)
+#include <sys/param.h>
+#include <sys/disklabel.h>
+#include <sys/dkio.h>
+#include <sys/ioctl.h>
+#elif defined(__NetBSD__)
+#include <sys/ioctl.h>
+#elif __linux__
+#include <sys/mount.h>
+#endif
+#ifdef USE_UBLIO
+#include <sys/uio.h>
+#include <ublio.h>
+#endif
+#else
+#include <fs.h>
+#include <fs_internal.h>
+
+static struct exfat_ctxt {
+	struct disk_partition	cur_part_info;
+	struct blk_desc		*cur_dev;
+	struct exfat		ef;
+} ctxt;
+#endif
+
+struct exfat_dev
+{
+	int fd;
+	enum exfat_mode mode;
+	off_t size; /* in bytes */
+#ifdef USE_UBLIO
+	off_t pos;
+	ublio_filehandle_t ufh;
+#endif
+#ifdef __UBOOT__
+	struct exfat_ctxt *ctxt;
+#endif
+};
+
+#ifndef __UBOOT__
+static bool is_open(int fd)
+{
+	return fcntl(fd, F_GETFD) != -1;
+}
+
+static int open_ro(const char* spec)
+{
+	return open(spec, O_RDONLY);
+}
+
+static int open_rw(const char* spec)
+{
+	int fd = open(spec, O_RDWR);
+#ifdef __linux__
+	int ro = 0;
+
+	/*
+	   This ioctl is needed because after "blockdev --setro" kernel still
+	   allows to open the device in read-write mode but fails writes.
+	*/
+	if (fd != -1 && ioctl(fd, BLKROGET, &ro) == 0 && ro)
+	{
+		close(fd);
+		errno = EROFS;
+		return -1;
+	}
+#endif
+	return fd;
+}
+
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode)
+{
+	struct exfat_dev* dev;
+	struct stat stbuf;
+#ifdef USE_UBLIO
+	struct ublio_param up;
+#endif
+
+	/* The system allocates file descriptors sequentially. If we have been
+	   started with stdin (0), stdout (1) or stderr (2) closed, the system
+	   will give us descriptor 0, 1 or 2 later when we open block device,
+	   FUSE communication pipe, etc. As a result, functions using stdin,
+	   stdout or stderr will actually work with a different thing and can
+	   corrupt it. Protect descriptors 0, 1 and 2 from such misuse. */
+	while (!is_open(STDIN_FILENO)
+		|| !is_open(STDOUT_FILENO)
+		|| !is_open(STDERR_FILENO))
+	{
+		/* we don't need those descriptors, let them leak */
+		if (open("/dev/null", O_RDWR) == -1)
+		{
+			exfat_error("failed to open /dev/null");
+			return NULL;
+		}
+	}
+
+	dev = malloc(sizeof(struct exfat_dev));
+	if (dev == NULL)
+	{
+		exfat_error("failed to allocate memory for device structure");
+		return NULL;
+	}
+
+	switch (mode)
+	{
+	case EXFAT_MODE_RO:
+		dev->fd = open_ro(spec);
+		if (dev->fd == -1)
+		{
+			free(dev);
+			exfat_error("failed to open '%s' in read-only mode: %s", spec,
+					strerror(errno));
+			return NULL;
+		}
+		dev->mode = EXFAT_MODE_RO;
+		break;
+	case EXFAT_MODE_RW:
+		dev->fd = open_rw(spec);
+		if (dev->fd == -1)
+		{
+			free(dev);
+			exfat_error("failed to open '%s' in read-write mode: %s", spec,
+					strerror(errno));
+			return NULL;
+		}
+		dev->mode = EXFAT_MODE_RW;
+		break;
+	case EXFAT_MODE_ANY:
+		dev->fd = open_rw(spec);
+		if (dev->fd != -1)
+		{
+			dev->mode = EXFAT_MODE_RW;
+			break;
+		}
+		dev->fd = open_ro(spec);
+		if (dev->fd != -1)
+		{
+			dev->mode = EXFAT_MODE_RO;
+			exfat_warn("'%s' is write-protected, mounting read-only", spec);
+			break;
+		}
+		free(dev);
+		exfat_error("failed to open '%s': %s", spec, strerror(errno));
+		return NULL;
+	}
+
+	if (fstat(dev->fd, &stbuf) != 0)
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("failed to fstat '%s'", spec);
+		return NULL;
+	}
+	if (!S_ISBLK(stbuf.st_mode) &&
+		!S_ISCHR(stbuf.st_mode) &&
+		!S_ISREG(stbuf.st_mode))
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("'%s' is neither a device, nor a regular file", spec);
+		return NULL;
+	}
+
+#if defined(__APPLE__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		uint32_t block_size = 0;
+		uint64_t blocks = 0;
+
+		if (ioctl(dev->fd, DKIOCGETBLOCKSIZE, &block_size) != 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get block size");
+			return NULL;
+		}
+		if (ioctl(dev->fd, DKIOCGETBLOCKCOUNT, &blocks) != 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get blocks count");
+			return NULL;
+		}
+		dev->size = blocks * block_size;
+	}
+	else
+#elif defined(__OpenBSD__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		struct disklabel lab;
+		struct partition* pp;
+		char* partition;
+
+		if (ioctl(dev->fd, DIOCGDINFO, &lab) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get disklabel");
+			return NULL;
+		}
+
+		/* Don't need to check that partition letter is valid as we won't get
+		   this far otherwise. */
+		partition = strchr(spec, '\0') - 1;
+		pp = &(lab.d_partitions[*partition - 'a']);
+		dev->size = DL_GETPSIZE(pp) * lab.d_secsize;
+
+		if (pp->p_fstype != FS_NTFS)
+			exfat_warn("partition type is not 0x07 (NTFS/exFAT); "
+					"you can fix this with fdisk(8)");
+	}
+	else
+#elif defined(__NetBSD__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		off_t size;
+
+		if (ioctl(dev->fd, DIOCGMEDIASIZE, &size) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get media size");
+			return NULL;
+		}
+		dev->size = size;
+	}
+	else
+#endif
+	{
+		/* works for Linux, FreeBSD, Solaris */
+		dev->size = exfat_seek(dev, 0, SEEK_END);
+		if (dev->size <= 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get size of '%s'", spec);
+			return NULL;
+		}
+		if (exfat_seek(dev, 0, SEEK_SET) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to seek to the beginning of '%s'", spec);
+			return NULL;
+		}
+	}
+
+#ifdef USE_UBLIO
+	memset(&up, 0, sizeof(struct ublio_param));
+	up.up_blocksize = 256 * 1024;
+	up.up_items = 64;
+	up.up_grace = 32;
+	up.up_priv = &dev->fd;
+
+	dev->pos = 0;
+	dev->ufh = ublio_open(&up);
+	if (dev->ufh == NULL)
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("failed to initialize ublio");
+		return NULL;
+	}
+#endif
+
+	return dev;
+}
+
+int exfat_close(struct exfat_dev* dev)
+{
+	int rc = 0;
+
+#ifdef USE_UBLIO
+	if (ublio_close(dev->ufh) != 0)
+	{
+		exfat_error("failed to close ublio");
+		rc = -EIO;
+	}
+#endif
+	if (close(dev->fd) != 0)
+	{
+		exfat_error("failed to close device: %s", strerror(errno));
+		rc = -EIO;
+	}
+	free(dev);
+	return rc;
+}
+
+int exfat_fsync(struct exfat_dev* dev)
+{
+	int rc = 0;
+
+#ifdef USE_UBLIO
+	if (ublio_fsync(dev->ufh) != 0)
+	{
+		exfat_error("ublio fsync failed");
+		rc = -EIO;
+	}
+#endif
+	if (fsync(dev->fd) != 0)
+	{
+		exfat_error("fsync failed: %s", strerror(errno));
+		rc = -EIO;
+	}
+	return rc;
+}
+
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev)
+{
+	return dev->mode;
+}
+
+off_t exfat_get_size(const struct exfat_dev* dev)
+{
+	return dev->size;
+}
+
+off_t exfat_seek(struct exfat_dev* dev, off_t offset, int whence)
+{
+#ifdef USE_UBLIO
+	/* XXX SEEK_CUR will be handled incorrectly */
+	return dev->pos = lseek(dev->fd, offset, whence);
+#else
+	return lseek(dev->fd, offset, whence);
+#endif
+}
+
+ssize_t exfat_read(struct exfat_dev* dev, void* buffer, size_t size)
+{
+#ifdef USE_UBLIO
+	ssize_t result = ublio_pread(dev->ufh, buffer, size, dev->pos);
+	if (result >= 0)
+		dev->pos += size;
+	return result;
+#else
+	return read(dev->fd, buffer, size);
+#endif
+}
+
+ssize_t exfat_write(struct exfat_dev* dev, const void* buffer, size_t size)
+{
+#ifdef USE_UBLIO
+	ssize_t result = ublio_pwrite(dev->ufh, (void*) buffer, size, dev->pos);
+	if (result >= 0)
+		dev->pos += size;
+	return result;
+#else
+	return write(dev->fd, buffer, size);
+#endif
+}
+
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset)
+{
+#ifdef USE_UBLIO
+	return ublio_pread(dev->ufh, buffer, size, offset);
+#else
+	return pread(dev->fd, buffer, size, offset);
+#endif
+}
+
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset)
+{
+#ifdef USE_UBLIO
+	return ublio_pwrite(dev->ufh, (void*) buffer, size, offset);
+#else
+	return pwrite(dev->fd, buffer, size, offset);
+#endif
+}
+#else	/* U-Boot */
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode)
+{
+	struct exfat_dev* dev;
+
+	dev = malloc(sizeof(struct exfat_dev));
+	if (!dev) {
+		exfat_error("failed to allocate memory for device structure");
+		return NULL;
+	}
+	dev->mode = EXFAT_MODE_RW;
+	dev->size = ctxt.cur_part_info.size * ctxt.cur_part_info.blksz;
+	dev->ctxt = &ctxt;
+
+	return dev;
+}
+
+int exfat_close(struct exfat_dev* dev)
+{
+	free(dev);
+	return 0;
+}
+
+int exfat_fsync(struct exfat_dev* dev)
+{
+	return 0;
+}
+
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev)
+{
+	return dev->mode;
+}
+
+off_t exfat_get_size(const struct exfat_dev* dev)
+{
+	return dev->size;
+}
+
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset)
+{
+	lbaint_t sect = offset >> ctxt.cur_dev->log2blksz;
+	int off = offset & (ctxt.cur_dev->blksz - 1);
+
+	if (!ctxt.cur_dev)
+		return -EIO;
+
+	if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect,
+		       off, size, buffer))
+		return 0;
+	return -EIO;
+}
+
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset)
+{
+	lbaint_t sect = offset >> ctxt.cur_dev->log2blksz;
+	int off = offset & (ctxt.cur_dev->blksz - 1);
+
+	if (!ctxt.cur_dev)
+		return -EIO;
+
+	if (fs_devwrite(ctxt.cur_dev, &ctxt.cur_part_info, sect,
+		       off, size, buffer))
+		return 0;
+	return -EIO;
+}
+#endif
+
+ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node,
+		void* buffer, size_t size, off_t offset)
+{
+	uint64_t uoffset = offset;
+	cluster_t cluster;
+	char* bufp = buffer;
+	off_t lsize, loffset, remainder;
+
+	if (offset < 0)
+		return -EINVAL;
+	if (uoffset >= node->size)
+		return 0;
+	if (size == 0)
+		return 0;
+
+	if (uoffset + size > node->valid_size)
+	{
+		ssize_t bytes = 0;
+
+		if (uoffset < node->valid_size)
+		{
+			bytes = exfat_generic_pread(ef, node, buffer,
+					node->valid_size - uoffset, offset);
+			if (bytes < 0 || (size_t) bytes < node->valid_size - uoffset)
+				return bytes;
+		}
+		memset(buffer + bytes, 0,
+				MIN(size - bytes, node->size - node->valid_size));
+		return MIN(size, node->size - uoffset);
+	}
+
+	cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while reading", cluster);
+		return -EIO;
+	}
+
+	loffset = uoffset % CLUSTER_SIZE(*ef->sb);
+	remainder = MIN(size, node->size - uoffset);
+	while (remainder > 0)
+	{
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+		{
+			exfat_error("invalid cluster 0x%x while reading", cluster);
+			return -EIO;
+		}
+		lsize = MIN(CLUSTER_SIZE(*ef->sb) - loffset, remainder);
+		if (exfat_pread(ef->dev, bufp, lsize,
+					exfat_c2o(ef, cluster) + loffset) < 0)
+		{
+			exfat_error("failed to read cluster %#x", cluster);
+			return -EIO;
+		}
+		bufp += lsize;
+		loffset = 0;
+		remainder -= lsize;
+		cluster = exfat_next_cluster(ef, node, cluster);
+	}
+	if (!(node->attrib & EXFAT_ATTRIB_DIR) && !ef->ro && !ef->noatime)
+		exfat_update_atime(node);
+	return MIN(size, node->size - uoffset) - remainder;
+}
+
+ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node,
+		const void* buffer, size_t size, off_t offset)
+{
+	uint64_t uoffset = offset;
+	int rc;
+	cluster_t cluster;
+	const char* bufp = buffer;
+	off_t lsize, loffset, remainder;
+
+	if (offset < 0)
+		return -EINVAL;
+	if (uoffset > node->size)
+	{
+		rc = exfat_truncate(ef, node, uoffset, true);
+		if (rc != 0)
+			return rc;
+	}
+	if (uoffset + size > node->size)
+	{
+		rc = exfat_truncate(ef, node, uoffset + size, false);
+		if (rc != 0)
+			return rc;
+	}
+	if (size == 0)
+		return 0;
+
+	cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while writing", cluster);
+		return -EIO;
+	}
+
+	loffset = uoffset % CLUSTER_SIZE(*ef->sb);
+	remainder = size;
+	while (remainder > 0)
+	{
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+		{
+			exfat_error("invalid cluster 0x%x while writing", cluster);
+			return -EIO;
+		}
+		lsize = MIN(CLUSTER_SIZE(*ef->sb) - loffset, remainder);
+		if (exfat_pwrite(ef->dev, bufp, lsize,
+				exfat_c2o(ef, cluster) + loffset) < 0)
+		{
+			exfat_error("failed to write cluster %#x", cluster);
+			return -EIO;
+		}
+		bufp += lsize;
+		loffset = 0;
+		remainder -= lsize;
+		node->valid_size = MAX(node->valid_size, uoffset + size - remainder);
+		cluster = exfat_next_cluster(ef, node, cluster);
+	}
+	if (!(node->attrib & EXFAT_ATTRIB_DIR))
+		/* directory's mtime should be updated by the caller only when it
+		   creates or removes something in this directory */
+		exfat_update_mtime(node);
+	return size - remainder;
+}
+
+#ifdef __UBOOT__
+struct exfat_dir_stream {
+	struct fs_dir_stream fs_dirs;
+	struct fs_dirent dirent;
+
+	struct exfat_node* node;
+	struct exfat_iterator it;
+	/* State tracker flags for emulated . and .. dirents */
+	bool dot;
+	bool dotdot;
+};
+
+int exfat_fs_probe(struct blk_desc *fs_dev_desc,
+		struct disk_partition *fs_partition)
+{
+	int ret;
+
+	ctxt.cur_dev = fs_dev_desc;
+	ctxt.cur_part_info = *fs_partition;
+
+	ret = exfat_mount(&ctxt.ef, NULL, "");
+	if (ret)
+		goto error;
+
+	return 0;
+error:
+	ctxt.cur_dev = NULL;
+	return ret;
+}
+
+#define PATH_MAX FS_DIRENT_NAME_LEN
+
+/* Adapted from uclibc 1.0.35 */
+static char *exfat_realpath(const char *path, char got_path[])
+{
+	char copy_path[PATH_MAX];
+	char *max_path, *new_path;
+	size_t path_len;
+
+	if (path == NULL)
+		return NULL;
+
+	if (*path == '\0')
+		return NULL;
+
+	/* Make a copy of the source path since we may need to modify it. */
+	path_len = strlen(path);
+	if (path_len >= PATH_MAX - 2)
+		return NULL;
+
+	/* Copy so that path is at the end of copy_path[] */
+	strcpy(copy_path + (PATH_MAX-1) - path_len, path);
+	path = copy_path + (PATH_MAX-1) - path_len;
+	max_path = got_path + PATH_MAX - 2; /* points to last non-NUL char */
+	new_path = got_path;
+	*new_path++ = '/';
+	path++;
+
+	/* Expand each slash-separated pathname component. */
+	while (*path != '\0') {
+		/* Ignore stray "/". */
+		if (*path == '/') {
+			path++;
+			continue;
+		}
+
+		if (*path == '.') {
+			/* Ignore ".". */
+			if (path[1] == '\0' || path[1] == '/') {
+				path++;
+				continue;
+			}
+
+			if (path[1] == '.') {
+				if (path[2] == '\0' || path[2] == '/') {
+					path += 2;
+					/* Ignore ".." at root. */
+					if (new_path == got_path + 1)
+						continue;
+					/* Handle ".." by backing up. */
+					while ((--new_path)[-1] != '/')
+						;
+					continue;
+				}
+			}
+		}
+
+		/* Safely copy the next pathname component. */
+		while (*path != '\0' && *path != '/') {
+			if (new_path > max_path)
+				return NULL;
+			*new_path++ = *path++;
+		}
+
+		*new_path++ = '/';
+	}
+
+	/* Delete trailing slash but don't whomp a lone slash. */
+	if (new_path != got_path + 1 && new_path[-1] == '/')
+		new_path--;
+
+	/* Make sure it's null terminated. */
+	*new_path = '\0';
+	return got_path;
+}
+
+int exfat_lookup_realpath(struct exfat* ef, struct exfat_node** node,
+			  const char* path)
+{
+	char input_path[FS_DIRENT_NAME_LEN];
+	char real_path[FS_DIRENT_NAME_LEN];
+	char *name;
+
+	/* Input is always absolute path */
+	snprintf(input_path, FS_DIRENT_NAME_LEN, "/%s", path);
+	name = exfat_realpath(input_path, real_path);
+	if (!name)
+		return -EINVAL;
+
+	return exfat_lookup(ef, node, real_path);
+}
+
+int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+	struct exfat_dir_stream *dirs;
+	int err;
+
+	dirs = calloc(1, sizeof(*dirs));
+	if (!dirs)
+		return -ENOMEM;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &dirs->node, filename);
+	if (err)
+		goto err_out;
+
+	if (!(dirs->node->attrib & EXFAT_ATTRIB_DIR)) {
+		err = -ENOTDIR;
+		goto err_out;
+	}
+
+	err = exfat_opendir(&ctxt.ef, dirs->node, &dirs->it);
+	if (err)
+		goto err_out;
+
+	*dirsp = &dirs->fs_dirs;
+
+	return 0;
+err_out:
+	free(dirs);
+	return err;
+}
+
+int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
+	struct exfat_dir_stream *dirs =
+		container_of(fs_dirs, struct exfat_dir_stream, fs_dirs);
+	struct fs_dirent *dent = &dirs->dirent;
+	struct exfat_node* node;
+
+	/* Emulate current directory ./ */
+	if (!dirs->dot) {
+		dirs->dot = true;
+		snprintf(dent->name, FS_DIRENT_NAME_LEN, ".");
+		dent->type = FS_DT_DIR;
+		*dentp = dent;
+		return 0;
+	}
+
+	/* Emulate parent directory ../ */
+	if (!dirs->dotdot) {
+		dirs->dotdot = true;
+		snprintf(dent->name, FS_DIRENT_NAME_LEN, "..");
+		dent->type = FS_DT_DIR;
+		*dentp = dent;
+		return 0;
+	}
+
+	/* Read actual directory content */
+	node = exfat_readdir(&dirs->it);
+	if (!node) {	/* No more content, reset . and .. emulation */
+		dirs->dot = false;
+		dirs->dotdot = false;
+		return 1;
+	}
+
+	exfat_get_name(node, dent->name);
+	if (node->attrib & EXFAT_ATTRIB_DIR) {
+		dent->type = FS_DT_DIR;
+	} else {
+		dent->type = FS_DT_REG;
+		dent->size = node->size;
+	}
+
+	*dentp = dent;
+
+	return 0;
+}
+
+void exfat_fs_closedir(struct fs_dir_stream *fs_dirs)
+{
+	free(fs_dirs);
+}
+
+int exfat_fs_ls(const char *dirname)
+{
+	struct exfat_node *dnode, *node;
+	char name[FS_DIRENT_NAME_LEN];
+	int nfiles = 0, ndirs = 2;
+	struct exfat_iterator it;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &dnode, dirname);
+	if (err)
+		return err;
+
+	if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) {
+		err = -ENOTDIR;
+		goto err_out;
+	}
+
+	err = exfat_opendir(&ctxt.ef, dnode, &it);
+	if (err)
+		goto err_out;
+
+	printf("            ./\n");
+	printf("            ../\n");
+
+	/* Read actual directory content */
+	while ((node = exfat_readdir(&it))) {
+		exfat_get_name(node, name);
+		if (node->attrib & EXFAT_ATTRIB_DIR) {
+			printf("            %s/\n", name);
+			ndirs++;
+		} else {
+			printf(" %8lld   %s\n", node->size, name);
+			nfiles++;
+		}
+		exfat_put_node(&ctxt.ef, node);
+	}
+
+	printf("\n%d file(s), %d dir(s)\n\n", nfiles, ndirs);
+
+	exfat_closedir(&ctxt.ef, &it);
+
+err_out:
+	exfat_put_node(&ctxt.ef, dnode);
+	return err;
+}
+
+int exfat_fs_exists(const char *filename)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return 0;
+}
+
+int exfat_fs_size(const char *filename, loff_t *size)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	*size = node->size;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return 0;
+}
+
+int exfat_fs_read(const char *filename, void *buf, loff_t offset, loff_t len,
+	       loff_t *actread)
+{
+	struct exfat_node* node;
+	ssize_t sz;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	if (!len)
+		len = node->size;
+
+	sz = exfat_generic_pread(&ctxt.ef, node, buf, len, offset);
+	if (sz < 0) {
+		*actread = 0;
+		err = -EINVAL;
+		goto exit;
+	}
+
+	*actread = sz;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return exfat_flush_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+int exfat_fs_unlink(const char *filename)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err) {
+		printf("%s: doesn't exist (%d)\n", filename, err);
+		return err;
+	}
+
+	if (node->attrib & EXFAT_ATTRIB_DIR) {
+		err = exfat_rmdir(&ctxt.ef, node);
+		if (err == -ENOTEMPTY)
+			printf("Error: directory is not empty: %d\n", err);
+	} else {
+		err = exfat_unlink(&ctxt.ef, node);
+	}
+
+	if (err)
+		goto exit;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return exfat_cleanup_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+int exfat_fs_mkdir(const char *dirname)
+{
+	if (!strcmp(dirname, ".") || !strcmp(dirname, ".."))
+		return -EINVAL;
+
+	return exfat_mkdir(&ctxt.ef, dirname);
+}
+
+int exfat_fs_write(const char *filename, void *buf, loff_t offset,
+		   loff_t len, loff_t *actwrite)
+{
+	struct exfat_node* node;
+	ssize_t sz;
+	int err;
+
+	/*
+	 * Ignore -EEXIST error here, if the file exists,
+	 * this write should act as an append to offset.
+	 */
+	err = exfat_mknod(&ctxt.ef, filename);
+	if (err && err != -EEXIST)
+		return err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	/* Write into directories is not allowed. */
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		return -EISDIR;
+
+	/* Write past end of file is not allowed. */
+	if (offset > node->size) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	sz = exfat_generic_pwrite(&ctxt.ef, node, buf, len, offset);
+	if (sz < 0) {
+		*actwrite = 0;
+		err = -EINVAL;
+		goto exit;
+	}
+
+	err = exfat_truncate(&ctxt.ef, node, offset + sz, false);
+	if (err)
+		goto exit;
+
+	*actwrite = sz;
+
+	err = exfat_flush_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+void exfat_fs_close(void)
+{
+	exfat_unmount(&ctxt.ef);
+	ctxt.cur_dev = NULL;
+}
+#endif	/* __U_BOOT__ */
diff --git a/fs/exfat/lookup.c b/fs/exfat/lookup.c
new file mode 100644
index 00000000000..9867aab95f3
--- /dev/null
+++ b/fs/exfat/lookup.c
@@ -0,0 +1,225 @@
+/*
+	lookup.c (02.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <errno.h>
+#include <inttypes.h>
+
+int exfat_opendir(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_iterator* it)
+{
+	int rc;
+
+	exfat_get_node(dir);
+	it->parent = dir;
+	it->current = NULL;
+	rc = exfat_cache_directory(ef, dir);
+	if (rc != 0)
+		exfat_put_node(ef, dir);
+	return rc;
+}
+
+void exfat_closedir(struct exfat* ef, struct exfat_iterator* it)
+{
+	exfat_put_node(ef, it->parent);
+	it->parent = NULL;
+	it->current = NULL;
+}
+
+struct exfat_node* exfat_readdir(struct exfat_iterator* it)
+{
+	if (it->current == NULL)
+		it->current = it->parent->child;
+	else
+		it->current = it->current->next;
+
+	if (it->current != NULL)
+		return exfat_get_node(it->current);
+	else
+		return NULL;
+}
+
+static int compare_char(struct exfat* ef, uint16_t a, uint16_t b)
+{
+	return (int) ef->upcase[a] - (int) ef->upcase[b];
+}
+
+static int compare_name(struct exfat* ef, const le16_t* a, const le16_t* b)
+{
+	while (le16_to_cpu(*a) && le16_to_cpu(*b))
+	{
+		int rc = compare_char(ef, le16_to_cpu(*a), le16_to_cpu(*b));
+		if (rc != 0)
+			return rc;
+		a++;
+		b++;
+	}
+	return compare_char(ef, le16_to_cpu(*a), le16_to_cpu(*b));
+}
+
+static int lookup_name(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, const char* name, size_t n)
+{
+	struct exfat_iterator it;
+	le16_t buffer[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	*node = NULL;
+
+	rc = exfat_utf8_to_utf16(buffer, name, EXFAT_NAME_MAX + 1, n);
+	if (rc != 0)
+		return rc;
+
+	rc = exfat_opendir(ef, parent, &it);
+	if (rc != 0)
+		return rc;
+	while ((*node = exfat_readdir(&it)))
+	{
+		if (compare_name(ef, buffer, (*node)->name) == 0)
+		{
+			exfat_closedir(ef, &it);
+			return 0;
+		}
+		exfat_put_node(ef, *node);
+	}
+	exfat_closedir(ef, &it);
+	return -ENOENT;
+}
+
+static size_t get_comp(const char* path, const char** comp)
+{
+	const char* end;
+
+	*comp = path + strspn(path, "/");				/* skip leading slashes */
+	end = strchr(*comp, '/');
+	if (end == NULL)
+		return strlen(*comp);
+	else
+		return end - *comp;
+}
+
+int exfat_lookup(struct exfat* ef, struct exfat_node** node,
+		const char* path)
+{
+	struct exfat_node* parent;
+	const char* p;
+	size_t n;
+	int rc;
+
+	/* start from the root directory */
+	parent = *node = exfat_get_node(ef->root);
+	for (p = path; (n = get_comp(p, &p)); p += n)
+	{
+		if (n == 1 && *p == '.')				/* skip "." component */
+			continue;
+		rc = lookup_name(ef, parent, node, p, n);
+		if (rc != 0)
+		{
+			exfat_put_node(ef, parent);
+			return rc;
+		}
+		exfat_put_node(ef, parent);
+		parent = *node;
+	}
+	return 0;
+}
+
+static bool is_last_comp(const char* comp, size_t length)
+{
+	const char* p = comp + length;
+
+	return get_comp(p, &p) == 0;
+}
+
+static bool is_allowed(const char* comp, size_t length)
+{
+	size_t i;
+
+	for (i = 0; i < length; i++)
+		switch (comp[i])
+		{
+		case 0x01 ... 0x1f:
+		case '/':
+		case '\\':
+		case ':':
+		case '*':
+		case '?':
+		case '"':
+		case '<':
+		case '>':
+		case '|':
+			return false;
+		}
+	return true;
+}
+
+int exfat_split(struct exfat* ef, struct exfat_node** parent,
+		struct exfat_node** node, le16_t* name, const char* path)
+{
+	const char* p;
+	size_t n;
+	int rc;
+
+	memset(name, 0, (EXFAT_NAME_MAX + 1) * sizeof(le16_t));
+	*parent = *node = exfat_get_node(ef->root);
+	for (p = path; (n = get_comp(p, &p)); p += n)
+	{
+		if (n == 1 && *p == '.')
+			continue;
+		if (is_last_comp(p, n))
+		{
+			if (!is_allowed(p, n))
+			{
+				/* contains characters that are not allowed */
+				exfat_put_node(ef, *parent);
+				return -ENOENT;
+			}
+			rc = exfat_utf8_to_utf16(name, p, EXFAT_NAME_MAX + 1, n);
+			if (rc != 0)
+			{
+				exfat_put_node(ef, *parent);
+				return rc;
+			}
+
+			rc = lookup_name(ef, *parent, node, p, n);
+			if (rc != 0 && rc != -ENOENT)
+			{
+				exfat_put_node(ef, *parent);
+				return rc;
+			}
+			return 0;
+		}
+		rc = lookup_name(ef, *parent, node, p, n);
+		if (rc != 0)
+		{
+			exfat_put_node(ef, *parent);
+			return rc;
+		}
+		exfat_put_node(ef, *parent);
+		*parent = *node;
+	}
+	exfat_bug("impossible");
+#ifdef __UBOOT__
+	return 0;
+#endif
+}
diff --git a/fs/exfat/mount.c b/fs/exfat/mount.c
new file mode 100644
index 00000000000..0ff297af67b
--- /dev/null
+++ b/fs/exfat/mount.c
@@ -0,0 +1,380 @@
+/*
+	mount.c (22.10.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <inttypes.h>
+#ifndef __UBOOT__
+#include <unistd.h>
+#include <sys/types.h>
+#endif
+
+static uint64_t rootdir_size(const struct exfat* ef)
+{
+	uint32_t clusters = 0;
+	uint32_t clusters_max = le32_to_cpu(ef->sb->cluster_count);
+	cluster_t rootdir_cluster = le32_to_cpu(ef->sb->rootdir_cluster);
+
+	/* Iterate all clusters of the root directory to calculate its size.
+	   It can't be contiguous because there is no flag to indicate this. */
+	do
+	{
+		if (clusters == clusters_max) /* infinite loop detected */
+		{
+			exfat_error("root directory cannot occupy all %d clusters",
+					clusters);
+			return 0;
+		}
+		if (CLUSTER_INVALID(*ef->sb, rootdir_cluster))
+		{
+			exfat_error("bad cluster %#x while reading root directory",
+					rootdir_cluster);
+			return 0;
+		}
+		rootdir_cluster = exfat_next_cluster(ef, ef->root, rootdir_cluster);
+		clusters++;
+	}
+	while (rootdir_cluster != EXFAT_CLUSTER_END);
+
+	return (uint64_t) clusters * CLUSTER_SIZE(*ef->sb);
+}
+
+static const char* get_option(const char* options, const char* option_name)
+{
+	const char* p;
+	size_t length = strlen(option_name);
+
+	for (p = strstr(options, option_name); p; p = strstr(p + 1, option_name))
+		if ((p == options || p[-1] == ',') && p[length] == '=')
+			return p + length + 1;
+	return NULL;
+}
+
+static int get_int_option(const char* options, const char* option_name,
+		int base, int default_value)
+{
+	const char* p = get_option(options, option_name);
+
+	if (p == NULL)
+		return default_value;
+	return strtol(p, NULL, base);
+}
+
+static void parse_options(struct exfat* ef, const char* options)
+{
+	int opt_umask;
+
+	opt_umask = get_int_option(options, "umask", 8, 0);
+	ef->dmask = get_int_option(options, "dmask", 8, opt_umask);
+	ef->fmask = get_int_option(options, "fmask", 8, opt_umask);
+
+	ef->uid = get_int_option(options, "uid", 10, geteuid());
+	ef->gid = get_int_option(options, "gid", 10, getegid());
+
+	ef->noatime = exfat_match_option(options, "noatime");
+
+	switch (get_int_option(options, "repair", 10, 0))
+	{
+	case 1:
+		ef->repair = EXFAT_REPAIR_ASK;
+		break;
+	case 2:
+		ef->repair = EXFAT_REPAIR_YES;
+		break;
+	default:
+		ef->repair = EXFAT_REPAIR_NO;
+		break;
+	}
+}
+
+static bool verify_vbr_checksum(const struct exfat* ef, void* sector)
+{
+	off_t sector_size = SECTOR_SIZE(*ef->sb);
+	uint32_t vbr_checksum;
+	size_t i;
+
+	if (exfat_pread(ef->dev, sector, sector_size, 0) < 0)
+	{
+		exfat_error("failed to read boot sector");
+		return false;
+	}
+	vbr_checksum = exfat_vbr_start_checksum(sector, sector_size);
+	for (i = 1; i < 11; i++)
+	{
+		if (exfat_pread(ef->dev, sector, sector_size, i * sector_size) < 0)
+		{
+			exfat_error("failed to read VBR sector");
+			return false;
+		}
+		vbr_checksum = exfat_vbr_add_checksum(sector, sector_size,
+				vbr_checksum);
+	}
+	if (exfat_pread(ef->dev, sector, sector_size, i * sector_size) < 0)
+	{
+		exfat_error("failed to read VBR checksum sector");
+		return false;
+	}
+	for (i = 0; i < sector_size / sizeof(vbr_checksum); i++)
+		if (le32_to_cpu(((const le32_t*) sector)[i]) != vbr_checksum)
+		{
+			exfat_error("invalid VBR checksum 0x%x (expected 0x%x)",
+					le32_to_cpu(((const le32_t*) sector)[i]), vbr_checksum);
+			if (!EXFAT_REPAIR(invalid_vbr_checksum, ef, sector, vbr_checksum))
+				return false;
+		}
+	return true;
+}
+
+static int commit_super_block(const struct exfat* ef)
+{
+	if (exfat_pwrite(ef->dev, ef->sb, sizeof(struct exfat_super_block), 0) < 0)
+	{
+		exfat_error("failed to write super block");
+		return 1;
+	}
+	return exfat_fsync(ef->dev);
+}
+
+int exfat_soil_super_block(const struct exfat* ef)
+{
+	if (ef->ro)
+		return 0;
+
+	ef->sb->volume_state = cpu_to_le16(
+			le16_to_cpu(ef->sb->volume_state) | EXFAT_STATE_MOUNTED);
+	return commit_super_block(ef);
+}
+
+static void exfat_free(struct exfat* ef)
+{
+	exfat_close(ef->dev);	/* first of all, close the descriptor */
+	ef->dev = NULL;			/* struct exfat_dev is freed by exfat_close() */
+	free(ef->root);
+	ef->root = NULL;
+	free(ef->zero_cluster);
+	ef->zero_cluster = NULL;
+	free(ef->cmap.chunk);
+	ef->cmap.chunk = NULL;
+	free(ef->upcase);
+	ef->upcase = NULL;
+	free(ef->sb);
+	ef->sb = NULL;
+}
+
+int exfat_mount(struct exfat* ef, const char* spec, const char* options)
+{
+	int rc;
+	enum exfat_mode mode;
+
+	exfat_tzset();
+	memset(ef, 0, sizeof(struct exfat));
+
+	parse_options(ef, options);
+
+	if (exfat_match_option(options, "ro"))
+		mode = EXFAT_MODE_RO;
+	else if (exfat_match_option(options, "ro_fallback"))
+		mode = EXFAT_MODE_ANY;
+	else
+		mode = EXFAT_MODE_RW;
+	ef->dev = exfat_open(spec, mode);
+	if (ef->dev == NULL)
+		return -ENODEV;
+	if (exfat_get_mode(ef->dev) == EXFAT_MODE_RO)
+	{
+		if (mode == EXFAT_MODE_ANY)
+			ef->ro = -1;
+		else
+			ef->ro = 1;
+	}
+
+	ef->sb = malloc(sizeof(struct exfat_super_block));
+	if (ef->sb == NULL)
+	{
+		exfat_error("failed to allocate memory for the super block");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	memset(ef->sb, 0, sizeof(struct exfat_super_block));
+
+	if (exfat_pread(ef->dev, ef->sb, sizeof(struct exfat_super_block), 0) < 0)
+	{
+		exfat_error("failed to read boot sector");
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (memcmp(ef->sb->oem_name, "EXFAT   ", 8) != 0)
+	{
+#ifndef __UBOOT__
+		exfat_error(
+#else
+		exfat_debug(
+#endif
+		"exFAT file system is not found");
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* sector cannot be smaller than 512 bytes */
+	if (ef->sb->sector_bits < 9)
+	{
+		exfat_error("too small sector size: 2^%hhd", ef->sb->sector_bits);
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* officially exFAT supports cluster size up to 32 MB */
+	if ((int) ef->sb->sector_bits + (int) ef->sb->spc_bits > 25)
+	{
+		exfat_error("too big cluster size: 2^(%hhd+%hhd)",
+				ef->sb->sector_bits, ef->sb->spc_bits);
+		exfat_free(ef);
+		return -EIO;
+	}
+	ef->zero_cluster = malloc(CLUSTER_SIZE(*ef->sb));
+	if (ef->zero_cluster == NULL)
+	{
+		exfat_error("failed to allocate zero sector");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	/* use zero_cluster as a temporary buffer for VBR checksum verification */
+	if (!verify_vbr_checksum(ef, ef->zero_cluster))
+	{
+		exfat_free(ef);
+		return -EIO;
+	}
+	memset(ef->zero_cluster, 0, CLUSTER_SIZE(*ef->sb));
+	if (ef->sb->version.major != 1 || ef->sb->version.minor != 0)
+	{
+		exfat_error("unsupported exFAT version: %hhu.%hhu",
+				ef->sb->version.major, ef->sb->version.minor);
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (ef->sb->fat_count != 1)
+	{
+		exfat_error("unsupported FAT count: %hhu", ef->sb->fat_count);
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (le64_to_cpu(ef->sb->sector_count) * SECTOR_SIZE(*ef->sb) >
+			(uint64_t) exfat_get_size(ef->dev))
+	{
+		/* this can cause I/O errors later but we don't fail mounting to let
+		   user rescue data */
+		exfat_warn("file system in sectors is larger than device: "
+				"%"PRIu64" * %d > %"PRIu64,
+				le64_to_cpu(ef->sb->sector_count), SECTOR_SIZE(*ef->sb),
+				exfat_get_size(ef->dev));
+	}
+	if ((off_t) le32_to_cpu(ef->sb->cluster_count) * CLUSTER_SIZE(*ef->sb) >
+			exfat_get_size(ef->dev))
+	{
+		exfat_error("file system in clusters is larger than device: "
+				"%u * %d > %"PRIu64,
+				le32_to_cpu(ef->sb->cluster_count), CLUSTER_SIZE(*ef->sb),
+				exfat_get_size(ef->dev));
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (le16_to_cpu(ef->sb->volume_state) & EXFAT_STATE_MOUNTED)
+		exfat_warn("volume was not unmounted cleanly");
+
+	ef->root = malloc(sizeof(struct exfat_node));
+	if (ef->root == NULL)
+	{
+		exfat_error("failed to allocate root node");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	memset(ef->root, 0, sizeof(struct exfat_node));
+	ef->root->attrib = EXFAT_ATTRIB_DIR;
+	ef->root->start_cluster = le32_to_cpu(ef->sb->rootdir_cluster);
+	ef->root->fptr_cluster = ef->root->start_cluster;
+	ef->root->name[0] = cpu_to_le16('\0');
+	ef->root->valid_size = ef->root->size = rootdir_size(ef);
+	if (ef->root->size == 0)
+	{
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* exFAT does not have time attributes for the root directory */
+	ef->root->mtime = 0;
+	ef->root->atime = 0;
+	/* always keep at least 1 reference to the root node */
+	exfat_get_node(ef->root);
+
+	rc = exfat_cache_directory(ef, ef->root);
+	if (rc != 0)
+		goto error;
+	if (ef->upcase == NULL)
+	{
+		exfat_error("upcase table is not found");
+		goto error;
+	}
+	if (ef->cmap.chunk == NULL)
+	{
+		exfat_error("clusters bitmap is not found");
+		goto error;
+	}
+
+	return 0;
+
+error:
+	exfat_put_node(ef, ef->root);
+	exfat_reset_cache(ef);
+	exfat_free(ef);
+	return -EIO;
+}
+
+static void finalize_super_block(struct exfat* ef)
+{
+	if (ef->ro)
+		return;
+
+	ef->sb->volume_state = cpu_to_le16(
+			le16_to_cpu(ef->sb->volume_state) & ~EXFAT_STATE_MOUNTED);
+
+	/* Some implementations set the percentage of allocated space to 0xff
+	   on FS creation and never update it. In this case leave it as is. */
+	if (ef->sb->allocated_percent != 0xff)
+	{
+		uint32_t free, total;
+
+		free = exfat_count_free_clusters(ef);
+		total = le32_to_cpu(ef->sb->cluster_count);
+		ef->sb->allocated_percent = ((total - free) * 100 + total / 2) / total;
+	}
+
+	commit_super_block(ef);	/* ignore return code */
+}
+
+void exfat_unmount(struct exfat* ef)
+{
+	exfat_flush_nodes(ef);	/* ignore return code */
+	exfat_flush(ef);		/* ignore return code */
+	exfat_put_node(ef, ef->root);
+	exfat_reset_cache(ef);
+	finalize_super_block(ef);
+	exfat_free(ef);			/* will close the descriptor */
+}
diff --git a/fs/exfat/node.c b/fs/exfat/node.c
new file mode 100644
index 00000000000..88b1357189c
--- /dev/null
+++ b/fs/exfat/node.c
@@ -0,0 +1,1243 @@
+/*
+	node.c (09.10.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+#include <string.h>
+#include <inttypes.h>
+
+#define EXFAT_ENTRY_NONE (-1)
+
+struct exfat_node* exfat_get_node(struct exfat_node* node)
+{
+	/* if we switch to multi-threaded mode we will need atomic
+	   increment here and atomic decrement in exfat_put_node() */
+	node->references++;
+	return node;
+}
+
+void exfat_put_node(struct exfat* ef, struct exfat_node* node)
+{
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+
+	--node->references;
+	if (node->references < 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_bug("reference counter of '%s' is below zero", buffer);
+	}
+	else if (node->references == 0 && node != ef->root)
+	{
+		if (node->is_dirty)
+		{
+			exfat_get_name(node, buffer);
+			exfat_warn("dirty node '%s' with zero references", buffer);
+		}
+	}
+}
+
+/**
+ * This function must be called on rmdir and unlink (after the last
+ * exfat_put_node()) to free clusters.
+ */
+int exfat_cleanup_node(struct exfat* ef, struct exfat_node* node)
+{
+	int rc = 0;
+
+	if (node->references != 0)
+		exfat_bug("unable to cleanup a node with %d references",
+				node->references);
+
+	if (node->is_unlinked)
+	{
+		/* free all clusters and node structure itself */
+		rc = exfat_truncate(ef, node, 0, true);
+		/* free the node even in case of error or its memory will be lost */
+		free(node);
+	}
+	return rc;
+}
+
+static int read_entries(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_entry* entries, int n, off_t offset)
+{
+	ssize_t size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to read entries from a file");
+
+	size = exfat_generic_pread(ef, dir, entries,
+			sizeof(struct exfat_entry[n]), offset);
+	if (size == (ssize_t) sizeof(struct exfat_entry) * n)
+		return 0; /* success */
+	if (size == 0)
+		return -ENOENT;
+	if (size < 0)
+		return -EIO;
+	exfat_error("read %zd bytes instead of %zu bytes", size,
+			sizeof(struct exfat_entry[n]));
+	return -EIO;
+}
+
+static int write_entries(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entries, int n, off_t offset)
+{
+	ssize_t size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to write entries into a file");
+
+	size = exfat_generic_pwrite(ef, dir, entries,
+			sizeof(struct exfat_entry[n]), offset);
+	if (size == (ssize_t) sizeof(struct exfat_entry) * n)
+		return 0; /* success */
+	if (size < 0)
+		return -EIO;
+	exfat_error("wrote %zd bytes instead of %zu bytes", size,
+			sizeof(struct exfat_entry[n]));
+	return -EIO;
+}
+
+static struct exfat_node* allocate_node(void)
+{
+	struct exfat_node* node = malloc(sizeof(struct exfat_node));
+	if (node == NULL)
+	{
+		exfat_error("failed to allocate node");
+		return NULL;
+	}
+	memset(node, 0, sizeof(struct exfat_node));
+	return node;
+}
+
+static void init_node_meta1(struct exfat_node* node,
+		const struct exfat_entry_meta1* meta1)
+{
+	node->attrib = le16_to_cpu(meta1->attrib);
+	node->continuations = meta1->continuations;
+	node->mtime = exfat_exfat2unix(meta1->mdate, meta1->mtime,
+			meta1->mtime_cs, meta1->mtime_tzo);
+	/* there is no centiseconds field for atime */
+	node->atime = exfat_exfat2unix(meta1->adate, meta1->atime,
+			0, meta1->atime_tzo);
+}
+
+static void init_node_meta2(struct exfat_node* node,
+		const struct exfat_entry_meta2* meta2)
+{
+	node->valid_size = le64_to_cpu(meta2->valid_size);
+	node->size = le64_to_cpu(meta2->size);
+	node->start_cluster = le32_to_cpu(meta2->start_cluster);
+	node->fptr_cluster = node->start_cluster;
+	node->is_contiguous = ((meta2->flags & EXFAT_FLAG_CONTIGUOUS) != 0);
+}
+
+static void init_node_name(struct exfat_node* node,
+		const struct exfat_entry* entries, int n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		memcpy(node->name + i * EXFAT_ENAME_MAX,
+				((const struct exfat_entry_name*) &entries[i])->name,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+}
+
+static bool check_entries(const struct exfat_entry* entry, int n)
+{
+	int previous = EXFAT_ENTRY_NONE;
+	int current;
+	int i;
+
+	/* check transitions between entries types */
+	for (i = 0; i < n + 1; previous = current, i++)
+	{
+		bool valid = false;
+
+		current = (i < n) ? entry[i].type : EXFAT_ENTRY_NONE;
+		switch (previous)
+		{
+		case EXFAT_ENTRY_NONE:
+			valid = (current == EXFAT_ENTRY_FILE);
+			break;
+		case EXFAT_ENTRY_FILE:
+			valid = (current == EXFAT_ENTRY_FILE_INFO);
+			break;
+		case EXFAT_ENTRY_FILE_INFO:
+			valid = (current == EXFAT_ENTRY_FILE_NAME);
+			break;
+		case EXFAT_ENTRY_FILE_NAME:
+			valid = (current == EXFAT_ENTRY_FILE_NAME ||
+			         current == EXFAT_ENTRY_NONE ||
+			         current >= EXFAT_ENTRY_FILE_TAIL);
+			break;
+		case EXFAT_ENTRY_FILE_TAIL ... 0xff:
+			valid = (current >= EXFAT_ENTRY_FILE_TAIL ||
+			         current == EXFAT_ENTRY_NONE);
+			break;
+		}
+
+		if (!valid)
+		{
+			exfat_error("unexpected entry type %#x after %#x at %d/%d",
+					current, previous, i, n);
+			return false;
+		}
+	}
+	return true;
+}
+
+static bool check_node(const struct exfat* ef, struct exfat_node* node,
+		le16_t actual_checksum, const struct exfat_entry_meta1* meta1)
+{
+	int cluster_size = CLUSTER_SIZE(*ef->sb);
+	uint64_t clusters_heap_size =
+			(uint64_t) le32_to_cpu(ef->sb->cluster_count) * cluster_size;
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+	bool ret = true;
+
+	/*
+	   Validate checksum first. If it's invalid all other fields probably
+	   contain just garbage.
+	*/
+	if (le16_to_cpu(actual_checksum) != le16_to_cpu(meta1->checksum))
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' has invalid checksum (%#hx != %#hx)", buffer,
+				le16_to_cpu(actual_checksum), le16_to_cpu(meta1->checksum));
+		if (!EXFAT_REPAIR(invalid_node_checksum, ef, node))
+			ret = false;
+	}
+
+	/*
+	   exFAT does not support sparse files but allows files with uninitialized
+	   clusters. For such files valid_size means initialized data size and
+	   cannot be greater than file size. See SetFileValidData() function
+	   description in MSDN.
+	*/
+	if (node->valid_size > node->size)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' has valid size (%"PRIu64") greater than size "
+				"(%"PRIu64")", buffer, node->valid_size, node->size);
+		ret = false;
+	}
+
+	/*
+	   Empty file must have zero start cluster. Non-empty file must start
+	   with a valid cluster. Directories cannot be empty (i.e. must always
+	   have a valid start cluster), but we will check this later while
+	   reading that directory to give user a chance to read this directory.
+	*/
+	if (node->size == 0 && node->start_cluster != EXFAT_CLUSTER_FREE)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is empty but start cluster is %#x", buffer,
+				node->start_cluster);
+		ret = false;
+	}
+	if (node->size > 0 && CLUSTER_INVALID(*ef->sb, node->start_cluster))
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' points to invalid cluster %#x", buffer,
+				node->start_cluster);
+		ret = false;
+	}
+
+	/* File or directory cannot be larger than clusters heap. */
+	if (node->size > clusters_heap_size)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is larger than clusters heap: %"PRIu64" > %"PRIu64,
+				buffer, node->size, clusters_heap_size);
+		ret = false;
+	}
+
+	/* Empty file or directory must be marked as non-contiguous. */
+	if (node->size == 0 && node->is_contiguous)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is empty but marked as contiguous (%#hx)", buffer,
+				node->attrib);
+		ret = false;
+	}
+
+	/* Directory size must be aligned on at cluster boundary. */
+	if ((node->attrib & EXFAT_ATTRIB_DIR) && node->size % cluster_size != 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' directory size %"PRIu64" is not divisible by %d", buffer,
+				node->size, cluster_size);
+		ret = false;
+	}
+
+	return ret;
+}
+
+static int parse_file_entries(struct exfat* ef, struct exfat_node* node,
+		const struct exfat_entry* entries, int n)
+{
+	const struct exfat_entry_meta1* meta1;
+	const struct exfat_entry_meta2* meta2;
+	int mandatory_entries;
+
+	if (!check_entries(entries, n))
+		return -EIO;
+
+	meta1 = (const struct exfat_entry_meta1*) &entries[0];
+	if (meta1->continuations < 2)
+	{
+		exfat_error("too few continuations (%hhu)", meta1->continuations);
+		return -EIO;
+	}
+	meta2 = (const struct exfat_entry_meta2*) &entries[1];
+	if (meta2->flags & ~(EXFAT_FLAG_ALWAYS1 | EXFAT_FLAG_CONTIGUOUS))
+	{
+		exfat_error("unknown flags in meta2 (%#hhx)", meta2->flags);
+		return -EIO;
+	}
+	mandatory_entries = 2 + DIV_ROUND_UP(meta2->name_length, EXFAT_ENAME_MAX);
+	if (meta1->continuations < mandatory_entries - 1)
+	{
+		exfat_error("too few continuations (%hhu < %d)",
+				meta1->continuations, mandatory_entries - 1);
+		return -EIO;
+	}
+
+	init_node_meta1(node, meta1);
+	init_node_meta2(node, meta2);
+	init_node_name(node, entries + 2, mandatory_entries - 2);
+
+	if (!check_node(ef, node, exfat_calc_checksum(entries, n), meta1))
+		return -EIO;
+
+	return 0;
+}
+
+static int parse_file_entry(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, off_t* offset, int n)
+{
+	struct exfat_entry entries[n];
+	int rc;
+
+	rc = read_entries(ef, parent, entries, n, *offset);
+	if (rc != 0)
+		return rc;
+
+	/* a new node has zero references */
+	*node = allocate_node();
+	if (*node == NULL)
+		return -ENOMEM;
+	(*node)->entry_offset = *offset;
+
+	rc = parse_file_entries(ef, *node, entries, n);
+	if (rc != 0)
+	{
+		free(*node);
+		return rc;
+	}
+
+	*offset += sizeof(struct exfat_entry[n]);
+	return 0;
+}
+
+static void decompress_upcase(uint16_t* output, const le16_t* source,
+		size_t size)
+{
+	size_t si;
+	size_t oi;
+
+	for (oi = 0; oi < EXFAT_UPCASE_CHARS; oi++)
+		output[oi] = oi;
+
+	for (si = 0, oi = 0; si < size && oi < EXFAT_UPCASE_CHARS; si++)
+	{
+		uint16_t ch = le16_to_cpu(source[si]);
+
+		if (ch == 0xffff && si + 1 < size)	/* indicates a run */
+			oi += le16_to_cpu(source[++si]);
+		else
+			output[oi++] = ch;
+	}
+}
+
+/*
+ * Read one entry in a directory at offset position and build a new node
+ * structure.
+ */
+static int readdir(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, off_t* offset)
+{
+	int rc;
+	struct exfat_entry entry;
+	const struct exfat_entry_meta1* meta1;
+	const struct exfat_entry_upcase* upcase;
+	const struct exfat_entry_bitmap* bitmap;
+	const struct exfat_entry_label* label;
+	uint64_t upcase_size = 0;
+	le16_t* upcase_comp = NULL;
+	le16_t label_name[EXFAT_ENAME_MAX];
+
+	for (;;)
+	{
+		rc = read_entries(ef, parent, &entry, 1, *offset);
+		if (rc != 0)
+			return rc;
+
+		switch (entry.type)
+		{
+		case EXFAT_ENTRY_FILE:
+			meta1 = (const struct exfat_entry_meta1*) &entry;
+			return parse_file_entry(ef, parent, node, offset,
+					1 + meta1->continuations);
+
+		case EXFAT_ENTRY_UPCASE:
+			if (ef->upcase != NULL)
+				break;
+			upcase = (const struct exfat_entry_upcase*) &entry;
+			if (CLUSTER_INVALID(*ef->sb, le32_to_cpu(upcase->start_cluster)))
+			{
+				exfat_error("invalid cluster 0x%x in upcase table",
+						le32_to_cpu(upcase->start_cluster));
+				return -EIO;
+			}
+			upcase_size = le64_to_cpu(upcase->size);
+			if (upcase_size == 0 ||
+				upcase_size > EXFAT_UPCASE_CHARS * sizeof(uint16_t) ||
+				upcase_size % sizeof(uint16_t) != 0)
+			{
+				exfat_error("bad upcase table size (%"PRIu64" bytes)",
+						upcase_size);
+				return -EIO;
+			}
+			upcase_comp = malloc(upcase_size);
+			if (upcase_comp == NULL)
+			{
+				exfat_error("failed to allocate upcase table (%"PRIu64" bytes)",
+						upcase_size);
+				return -ENOMEM;
+			}
+
+			/* read compressed upcase table */
+			if (exfat_pread(ef->dev, upcase_comp, upcase_size,
+					exfat_c2o(ef, le32_to_cpu(upcase->start_cluster))) < 0)
+			{
+				free(upcase_comp);
+				exfat_error("failed to read upper case table "
+						"(%"PRIu64" bytes starting at cluster %#x)",
+						upcase_size,
+						le32_to_cpu(upcase->start_cluster));
+				return -EIO;
+			}
+
+			/* decompress upcase table */
+			ef->upcase = calloc(EXFAT_UPCASE_CHARS, sizeof(uint16_t));
+			if (ef->upcase == NULL)
+			{
+				free(upcase_comp);
+				exfat_error("failed to allocate decompressed upcase table");
+				return -ENOMEM;
+			}
+			decompress_upcase(ef->upcase, upcase_comp,
+					upcase_size / sizeof(uint16_t));
+			free(upcase_comp);
+			break;
+
+		case EXFAT_ENTRY_BITMAP:
+			bitmap = (const struct exfat_entry_bitmap*) &entry;
+			ef->cmap.start_cluster = le32_to_cpu(bitmap->start_cluster);
+			if (CLUSTER_INVALID(*ef->sb, ef->cmap.start_cluster))
+			{
+				exfat_error("invalid cluster 0x%x in clusters bitmap",
+						ef->cmap.start_cluster);
+				return -EIO;
+			}
+			ef->cmap.size = le32_to_cpu(ef->sb->cluster_count);
+			if (le64_to_cpu(bitmap->size) < DIV_ROUND_UP(ef->cmap.size, 8))
+			{
+				exfat_error("invalid clusters bitmap size: %"PRIu64
+						" (expected at least %u)",
+						le64_to_cpu(bitmap->size),
+						DIV_ROUND_UP(ef->cmap.size, 8));
+				return -EIO;
+			}
+			/* FIXME bitmap can be rather big, up to 512 MB */
+			ef->cmap.chunk_size = ef->cmap.size;
+			ef->cmap.chunk = malloc(BMAP_SIZE(ef->cmap.chunk_size));
+			if (ef->cmap.chunk == NULL)
+			{
+				exfat_error("failed to allocate clusters bitmap chunk "
+						"(%"PRIu64" bytes)", le64_to_cpu(bitmap->size));
+				return -ENOMEM;
+			}
+
+			if (exfat_pread(ef->dev, ef->cmap.chunk,
+					BMAP_SIZE(ef->cmap.chunk_size),
+					exfat_c2o(ef, ef->cmap.start_cluster)) < 0)
+			{
+				exfat_error("failed to read clusters bitmap "
+						"(%"PRIu64" bytes starting at cluster %#x)",
+						le64_to_cpu(bitmap->size), ef->cmap.start_cluster);
+				return -EIO;
+			}
+			break;
+
+		case EXFAT_ENTRY_LABEL:
+			label = (const struct exfat_entry_label*) &entry;
+			if (label->length > EXFAT_ENAME_MAX)
+			{
+				exfat_error("too long label (%hhu chars)", label->length);
+				return -EIO;
+			}
+			/* copy to a temporary buffer to avoid unaligned access to a
+			   packed member */
+			memcpy(label_name, label->name, sizeof(label_name));
+			if (exfat_utf16_to_utf8(ef->label, label_name,
+						sizeof(ef->label), EXFAT_ENAME_MAX) != 0)
+				return -EIO;
+			break;
+
+		default:
+			if (!(entry.type & EXFAT_ENTRY_VALID))
+				break; /* deleted entry, ignore it */
+
+			exfat_error("unknown entry type %#hhx", entry.type);
+			if (!EXFAT_REPAIR(unknown_entry, ef, parent, &entry, *offset))
+				return -EIO;
+		}
+		*offset += sizeof(entry);
+	}
+	/* we never reach here */
+}
+
+int exfat_cache_directory(struct exfat* ef, struct exfat_node* dir)
+{
+	off_t offset = 0;
+	int rc;
+	struct exfat_node* node;
+	struct exfat_node* current = NULL;
+
+	if (dir->is_cached)
+		return 0; /* already cached */
+
+	while ((rc = readdir(ef, dir, &node, &offset)) == 0)
+	{
+		node->parent = dir;
+		if (current != NULL)
+		{
+			current->next = node;
+			node->prev = current;
+		}
+		else
+			dir->child = node;
+
+		current = node;
+	}
+
+	if (rc != -ENOENT)
+	{
+		/* rollback */
+		for (current = dir->child; current; current = node)
+		{
+			node = current->next;
+			free(current);
+		}
+		dir->child = NULL;
+		return rc;
+	}
+
+	dir->is_cached = true;
+	return 0;
+}
+
+static void tree_attach(struct exfat_node* dir, struct exfat_node* node)
+{
+	node->parent = dir;
+	if (dir->child)
+	{
+		dir->child->prev = node;
+		node->next = dir->child;
+	}
+	dir->child = node;
+}
+
+static void tree_detach(struct exfat_node* node)
+{
+	if (node->prev)
+		node->prev->next = node->next;
+	else /* this is the first node in the list */
+		node->parent->child = node->next;
+	if (node->next)
+		node->next->prev = node->prev;
+	node->parent = NULL;
+	node->prev = NULL;
+	node->next = NULL;
+}
+
+static void reset_cache(struct exfat* ef, struct exfat_node* node)
+{
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+
+	while (node->child)
+	{
+		struct exfat_node* p = node->child;
+		reset_cache(ef, p);
+		tree_detach(p);
+		free(p);
+	}
+	node->is_cached = false;
+	if (node->references != 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_warn("non-zero reference counter (%d) for '%s'",
+				node->references, buffer);
+	}
+	if (node != ef->root && node->is_dirty)
+	{
+		exfat_get_name(node, buffer);
+		exfat_bug("node '%s' is dirty", buffer);
+	}
+	while (node->references)
+		exfat_put_node(ef, node);
+}
+
+void exfat_reset_cache(struct exfat* ef)
+{
+	reset_cache(ef, ef->root);
+}
+
+int exfat_flush_node(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_entry entries[1 + node->continuations];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int rc;
+	le16_t edate, etime;
+
+	if (!node->is_dirty)
+		return 0; /* no need to flush */
+
+	if (ef->ro)
+		exfat_bug("unable to flush node to read-only FS");
+
+	if (node->parent == NULL)
+		return 0; /* do not flush unlinked node */
+
+	rc = read_entries(ef, node->parent, entries, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+		return rc;
+	if (!check_entries(entries, 1 + node->continuations))
+		return -EIO;
+
+	meta1->attrib = cpu_to_le16(node->attrib);
+	exfat_unix2exfat(node->mtime, &edate, &etime,
+			&meta1->mtime_cs, &meta1->mtime_tzo);
+	meta1->mdate = edate;
+	meta1->mtime = etime;
+	exfat_unix2exfat(node->atime, &edate, &etime,
+			NULL, &meta1->atime_tzo);
+	meta1->adate = edate;
+	meta1->atime = etime;
+	meta2->valid_size = cpu_to_le64(node->valid_size);
+	meta2->size = cpu_to_le64(node->size);
+	meta2->start_cluster = cpu_to_le32(node->start_cluster);
+	meta2->flags = EXFAT_FLAG_ALWAYS1;
+	/* empty files must not be marked as contiguous */
+	if (node->size != 0 && node->is_contiguous)
+		meta2->flags |= EXFAT_FLAG_CONTIGUOUS;
+	/* name hash remains unchanged, no need to recalculate it */
+
+	meta1->checksum = exfat_calc_checksum(entries, 1 + node->continuations);
+	rc = write_entries(ef, node->parent, entries, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+		return rc;
+
+	node->is_dirty = false;
+	return exfat_flush(ef);
+}
+
+static int erase_entries(struct exfat* ef, struct exfat_node* dir, int n,
+		off_t offset)
+{
+	struct exfat_entry entries[n];
+	int rc;
+	int i;
+
+	rc = read_entries(ef, dir, entries, n, offset);
+	if (rc != 0)
+		return rc;
+	for (i = 0; i < n; i++)
+		entries[i].type &= ~EXFAT_ENTRY_VALID;
+	return write_entries(ef, dir, entries, n, offset);
+}
+
+static int erase_node(struct exfat* ef, struct exfat_node* node)
+{
+	int rc;
+
+	exfat_get_node(node->parent);
+	rc = erase_entries(ef, node->parent, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, node->parent);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, node->parent);
+	exfat_put_node(ef, node->parent);
+	return rc;
+}
+
+static int shrink_directory(struct exfat* ef, struct exfat_node* dir,
+		off_t deleted_offset)
+{
+	const struct exfat_node* node;
+	const struct exfat_node* last_node;
+	uint64_t entries = 0;
+	uint64_t new_size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to shrink a file");
+	if (!dir->is_cached)
+		exfat_bug("attempted to shrink uncached directory");
+
+	for (last_node = node = dir->child; node; node = node->next)
+	{
+		if (deleted_offset < node->entry_offset)
+		{
+			/* there are other entries after the removed one, no way to shrink
+			   this directory */
+			return 0;
+		}
+		if (last_node->entry_offset < node->entry_offset)
+			last_node = node;
+	}
+
+	if (last_node)
+	{
+		/* offset of the last entry */
+		entries += last_node->entry_offset / sizeof(struct exfat_entry);
+		/* two subentries with meta info */
+		entries += 2;
+		/* subentries with file name */
+		entries += DIV_ROUND_UP(exfat_utf16_length(last_node->name),
+				EXFAT_ENAME_MAX);
+	}
+
+	new_size = DIV_ROUND_UP(entries * sizeof(struct exfat_entry),
+				 CLUSTER_SIZE(*ef->sb)) * CLUSTER_SIZE(*ef->sb);
+	if (new_size == 0) /* directory always has at least 1 cluster */
+		new_size = CLUSTER_SIZE(*ef->sb);
+	if (new_size == dir->size)
+		return 0;
+	return exfat_truncate(ef, dir, new_size, true);
+}
+
+static int delete(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_node* parent = node->parent;
+	off_t deleted_offset = node->entry_offset;
+	int rc;
+
+	exfat_get_node(parent);
+	rc = erase_node(ef, node);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, parent);
+		return rc;
+	}
+	tree_detach(node);
+	rc = shrink_directory(ef, parent, deleted_offset);
+	node->is_unlinked = true;
+	if (rc != 0)
+	{
+		exfat_flush_node(ef, parent);
+		exfat_put_node(ef, parent);
+		return rc;
+	}
+	exfat_update_mtime(parent);
+	rc = exfat_flush_node(ef, parent);
+	exfat_put_node(ef, parent);
+	return rc;
+}
+
+int exfat_unlink(struct exfat* ef, struct exfat_node* node)
+{
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		return -EISDIR;
+	return delete(ef, node);
+}
+
+int exfat_rmdir(struct exfat* ef, struct exfat_node* node)
+{
+	int rc;
+
+	if (!(node->attrib & EXFAT_ATTRIB_DIR))
+		return -ENOTDIR;
+	/* check that directory is empty */
+	rc = exfat_cache_directory(ef, node);
+	if (rc != 0)
+		return rc;
+	if (node->child)
+		return -ENOTEMPTY;
+	return delete(ef, node);
+}
+
+static int check_slot(struct exfat* ef, struct exfat_node* dir, off_t offset,
+		int n)
+{
+	struct exfat_entry entries[n];
+	int rc;
+	int i;
+
+	/* Root directory contains entries, that don't have any nodes associated
+	   with them (clusters bitmap, upper case table, label). We need to be
+	   careful not to overwrite them. */
+	if (dir != ef->root)
+		return 0;
+
+	rc = read_entries(ef, dir, entries, n, offset);
+	if (rc != 0)
+		return rc;
+	for (i = 0; i < n; i++)
+		if (entries[i].type & EXFAT_ENTRY_VALID)
+			return -EINVAL;
+	return 0;
+}
+
+static int find_slot(struct exfat* ef, struct exfat_node* dir,
+		off_t* offset, int n)
+{
+	bitmap_t* dmap;
+	struct exfat_node* p;
+	size_t i;
+	int contiguous = 0;
+
+	if (!dir->is_cached)
+		exfat_bug("directory is not cached");
+
+	/* build a bitmap of valid entries in the directory */
+	dmap = calloc(BMAP_SIZE(dir->size / sizeof(struct exfat_entry)),
+			sizeof(bitmap_t));
+	if (dmap == NULL)
+	{
+		exfat_error("failed to allocate directory bitmap (%"PRIu64")",
+				dir->size / sizeof(struct exfat_entry));
+		return -ENOMEM;
+	}
+	for (p = dir->child; p != NULL; p = p->next)
+		for (i = 0; i < 1u + p->continuations; i++)
+			BMAP_SET(dmap, p->entry_offset / sizeof(struct exfat_entry) + i);
+
+	/* find a slot in the directory entries bitmap */
+	for (i = 0; i < dir->size / sizeof(struct exfat_entry); i++)
+	{
+		if (BMAP_GET(dmap, i) == 0)
+		{
+			if (contiguous++ == 0)
+				*offset = (off_t) i * sizeof(struct exfat_entry);
+			if (contiguous == n)
+			{
+				int rc;
+
+				/* suitable slot is found, check that it's not occupied */
+				rc = check_slot(ef, dir, *offset, n);
+				if (rc == -EINVAL)
+				{
+					/* slot at (i-n) is occupied, go back and check (i-n+1) */
+					i -= contiguous - 1;
+					contiguous = 0;
+				}
+				else
+				{
+					/* slot is free or an error occurred */
+					free(dmap);
+					return rc;
+				}
+			}
+		}
+		else
+			contiguous = 0;
+	}
+	free(dmap);
+
+	/* no suitable slots found, extend the directory */
+	if (contiguous == 0)
+		*offset = dir->size;
+	return exfat_truncate(ef, dir,
+			ROUND_UP(dir->size + sizeof(struct exfat_entry[n - contiguous]),
+					CLUSTER_SIZE(*ef->sb)),
+			true);
+}
+
+static int commit_entry(struct exfat* ef, struct exfat_node* dir,
+		const le16_t* name, off_t offset, uint16_t attrib)
+{
+	struct exfat_node* node;
+	const size_t name_length = exfat_utf16_length(name);
+	const int name_entries = DIV_ROUND_UP(name_length, EXFAT_ENAME_MAX);
+	struct exfat_entry entries[2 + name_entries];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int i;
+	int rc;
+	le16_t edate, etime;
+
+	memset(entries, 0, sizeof(struct exfat_entry[2]));
+
+	meta1->type = EXFAT_ENTRY_FILE;
+	meta1->continuations = 1 + name_entries;
+	meta1->attrib = cpu_to_le16(attrib);
+	exfat_unix2exfat(time(NULL), &edate, &etime,
+			&meta1->crtime_cs, &meta1->crtime_tzo);
+	meta1->adate = meta1->mdate = meta1->crdate = edate;
+	meta1->atime = meta1->mtime = meta1->crtime = etime;
+	meta1->mtime_cs = meta1->crtime_cs; /* there is no atime_cs */
+	meta1->atime_tzo = meta1->mtime_tzo = meta1->crtime_tzo;
+
+	meta2->type = EXFAT_ENTRY_FILE_INFO;
+	meta2->flags = EXFAT_FLAG_ALWAYS1;
+	meta2->name_length = name_length;
+	meta2->name_hash = exfat_calc_name_hash(ef, name, name_length);
+	meta2->start_cluster = cpu_to_le32(EXFAT_CLUSTER_FREE);
+
+	for (i = 0; i < name_entries; i++)
+	{
+		struct exfat_entry_name* name_entry;
+
+		name_entry = (struct exfat_entry_name*) &entries[2 + i];
+		name_entry->type = EXFAT_ENTRY_FILE_NAME;
+		name_entry->__unknown = 0;
+		memcpy(name_entry->name, name + i * EXFAT_ENAME_MAX,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+	}
+
+	meta1->checksum = exfat_calc_checksum(entries, 2 + name_entries);
+	rc = write_entries(ef, dir, entries, 2 + name_entries, offset);
+	if (rc != 0)
+		return rc;
+
+	node = allocate_node();
+	if (node == NULL)
+		return -ENOMEM;
+	node->entry_offset = offset;
+	memcpy(node->name, name, name_length * sizeof(le16_t));
+	init_node_meta1(node, meta1);
+	init_node_meta2(node, meta2);
+
+	tree_attach(dir, node);
+	return 0;
+}
+
+static int create(struct exfat* ef, const char* path, uint16_t attrib)
+{
+	struct exfat_node* dir;
+	struct exfat_node* existing;
+	off_t offset = -1;
+	le16_t name[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	rc = exfat_split(ef, &dir, &existing, name, path);
+	if (rc != 0)
+		return rc;
+	if (existing != NULL)
+	{
+		exfat_put_node(ef, existing);
+		exfat_put_node(ef, dir);
+		return -EEXIST;
+	}
+
+	rc = find_slot(ef, dir, &offset,
+			2 + DIV_ROUND_UP(exfat_utf16_length(name), EXFAT_ENAME_MAX));
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		return rc;
+	}
+	rc = commit_entry(ef, dir, name, offset, attrib);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		return rc;
+	}
+	exfat_update_mtime(dir);
+	rc = exfat_flush_node(ef, dir);
+	exfat_put_node(ef, dir);
+	return rc;
+}
+
+int exfat_mknod(struct exfat* ef, const char* path)
+{
+	return create(ef, path, EXFAT_ATTRIB_ARCH);
+}
+
+int exfat_mkdir(struct exfat* ef, const char* path)
+{
+	int rc;
+	struct exfat_node* node;
+
+	rc = create(ef, path, EXFAT_ATTRIB_DIR);
+	if (rc != 0)
+		return rc;
+	rc = exfat_lookup(ef, &node, path);
+	if (rc != 0)
+		return 0;
+	/* directories always have at least one cluster */
+	rc = exfat_truncate(ef, node, CLUSTER_SIZE(*ef->sb), true);
+	if (rc != 0)
+	{
+		delete(ef, node);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, node);
+	if (rc != 0)
+	{
+		delete(ef, node);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	exfat_put_node(ef, node);
+	return 0;
+}
+
+static int rename_entry(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_node* node, const le16_t* name, off_t new_offset)
+{
+	const size_t name_length = exfat_utf16_length(name);
+	const int name_entries = DIV_ROUND_UP(name_length, EXFAT_ENAME_MAX);
+	struct exfat_entry entries[2 + name_entries];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int rc;
+	int i;
+
+	rc = read_entries(ef, node->parent, entries, 2, node->entry_offset);
+	if (rc != 0)
+		return rc;
+
+	meta1->continuations = 1 + name_entries;
+	meta2->name_length = name_length;
+	meta2->name_hash = exfat_calc_name_hash(ef, name, name_length);
+
+	rc = erase_node(ef, node);
+	if (rc != 0)
+		return rc;
+
+	node->entry_offset = new_offset;
+	node->continuations = 1 + name_entries;
+
+	for (i = 0; i < name_entries; i++)
+	{
+		struct exfat_entry_name* name_entry;
+
+		name_entry = (struct exfat_entry_name*) &entries[2 + i];
+		name_entry->type = EXFAT_ENTRY_FILE_NAME;
+		name_entry->__unknown = 0;
+		memcpy(name_entry->name, name + i * EXFAT_ENAME_MAX,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+	}
+
+	meta1->checksum = exfat_calc_checksum(entries, 2 + name_entries);
+	rc = write_entries(ef, dir, entries, 2 + name_entries, new_offset);
+	if (rc != 0)
+		return rc;
+
+	memcpy(node->name, name, (EXFAT_NAME_MAX + 1) * sizeof(le16_t));
+	tree_detach(node);
+	tree_attach(dir, node);
+	return 0;
+}
+
+int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path)
+{
+	struct exfat_node* node;
+	struct exfat_node* existing;
+	struct exfat_node* dir;
+	off_t offset = -1;
+	le16_t name[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	rc = exfat_lookup(ef, &node, old_path);
+	if (rc != 0)
+		return rc;
+
+	rc = exfat_split(ef, &dir, &existing, name, new_path);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, node);
+		return rc;
+	}
+
+	/* check that target is not a subdirectory of the source */
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+	{
+		struct exfat_node* p;
+
+		for (p = dir; p; p = p->parent)
+			if (node == p)
+			{
+				if (existing != NULL)
+					exfat_put_node(ef, existing);
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return -EINVAL;
+			}
+	}
+
+	if (existing != NULL)
+	{
+		/* remove target if it's not the same node as source */
+		if (existing != node)
+		{
+			if (existing->attrib & EXFAT_ATTRIB_DIR)
+			{
+				if (node->attrib & EXFAT_ATTRIB_DIR)
+					rc = exfat_rmdir(ef, existing);
+				else
+					rc = -ENOTDIR;
+			}
+			else
+			{
+				if (!(node->attrib & EXFAT_ATTRIB_DIR))
+					rc = exfat_unlink(ef, existing);
+				else
+					rc = -EISDIR;
+			}
+			exfat_put_node(ef, existing);
+			if (rc != 0)
+			{
+				/* free clusters even if something went wrong; otherwise they
+				   will be just lost */
+				exfat_cleanup_node(ef, existing);
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return rc;
+			}
+			rc = exfat_cleanup_node(ef, existing);
+			if (rc != 0)
+			{
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return rc;
+			}
+		}
+		else
+			exfat_put_node(ef, existing);
+	}
+
+	rc = find_slot(ef, dir, &offset,
+			2 + DIV_ROUND_UP(exfat_utf16_length(name), EXFAT_ENAME_MAX));
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = rename_entry(ef, dir, node, name, offset);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, dir);
+	exfat_put_node(ef, dir);
+	exfat_put_node(ef, node);
+	/* node itself is not marked as dirty, no need to flush it */
+	return rc;
+}
+
+void exfat_utimes(struct exfat_node* node, const struct timespec tv[2])
+{
+	node->atime = tv[0].tv_sec;
+	node->mtime = tv[1].tv_sec;
+	node->is_dirty = true;
+}
+
+void exfat_update_atime(struct exfat_node* node)
+{
+	node->atime = time(NULL);
+	node->is_dirty = true;
+}
+
+void exfat_update_mtime(struct exfat_node* node)
+{
+	node->mtime = time(NULL);
+	node->is_dirty = true;
+}
+
+const char* exfat_get_label(struct exfat* ef)
+{
+	return ef->label;
+}
+
+static int find_label(struct exfat* ef, off_t* offset)
+{
+	struct exfat_entry entry;
+	int rc;
+
+	for (*offset = 0; ; *offset += sizeof(entry))
+	{
+		rc = read_entries(ef, ef->root, &entry, 1, *offset);
+		if (rc != 0)
+			return rc;
+
+		if (entry.type == EXFAT_ENTRY_LABEL)
+			return 0;
+	}
+}
+
+int exfat_set_label(struct exfat* ef, const char* label)
+{
+	le16_t label_utf16[EXFAT_ENAME_MAX + 1];
+	int rc;
+	off_t offset;
+	struct exfat_entry_label entry;
+
+	memset(label_utf16, 0, sizeof(label_utf16));
+	rc = exfat_utf8_to_utf16(label_utf16, label, EXFAT_ENAME_MAX + 1,
+			strlen(label));
+	if (rc != 0)
+		return rc;
+
+	rc = find_label(ef, &offset);
+	if (rc == -ENOENT)
+		rc = find_slot(ef, ef->root, &offset, 1);
+	if (rc != 0)
+		return rc;
+
+	entry.type = EXFAT_ENTRY_LABEL;
+	entry.length = exfat_utf16_length(label_utf16);
+	memcpy(entry.name, label_utf16, sizeof(entry.name));
+	if (entry.length == 0)
+		entry.type ^= EXFAT_ENTRY_VALID;
+
+	rc = write_entries(ef, ef->root, (struct exfat_entry*) &entry, 1, offset);
+	if (rc != 0)
+		return rc;
+
+	strcpy(ef->label, label);
+	return 0;
+}
diff --git a/fs/exfat/platform.h b/fs/exfat/platform.h
new file mode 100644
index 00000000000..668857607bf
--- /dev/null
+++ b/fs/exfat/platform.h
@@ -0,0 +1,75 @@
+/*
+	platform.h (14.05.13)
+	OS-specific code (libc-specific in fact). Note that systems with the
+	same kernel can use different libc implementations.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef PLATFORM_H_INCLUDED
+#define PLATFORM_H_INCLUDED
+
+#if defined(__linux__) || defined(__GLIBC__) || defined(__GNU__)
+
+#ifndef __UBOOT__
+#include <endian.h>
+#include <byteswap.h>
+#endif
+#define exfat_bswap16(x) bswap_16(x)
+#define exfat_bswap32(x) bswap_32(x)
+#define exfat_bswap64(x) bswap_64(x)
+#define EXFAT_BYTE_ORDER __BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN __LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN __BIG_ENDIAN
+
+#elif defined(__APPLE__)
+
+#include <machine/endian.h>
+#include <libkern/OSByteOrder.h>
+#define exfat_bswap16(x) OSSwapInt16(x)
+#define exfat_bswap32(x) OSSwapInt32(x)
+#define exfat_bswap64(x) OSSwapInt64(x)
+#define EXFAT_BYTE_ORDER BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN BIG_ENDIAN
+
+#elif defined(__FreeBSD__) || defined(__DragonFly__) || defined(__NetBSD__) || defined(__OpenBSD__)
+
+#include <sys/endian.h>
+#define exfat_bswap16(x) bswap16(x)
+#define exfat_bswap32(x) bswap32(x)
+#define exfat_bswap64(x) bswap64(x)
+#define EXFAT_BYTE_ORDER _BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN _LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN _BIG_ENDIAN
+
+#elif defined(__sun)
+
+#include <endian.h>
+#define exfat_bswap16(x) bswap_16(x)
+#define exfat_bswap32(x) bswap_32(x)
+#define exfat_bswap64(x) bswap_64(x)
+#define EXFAT_BYTE_ORDER __BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN __LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN __BIG_ENDIAN
+
+#else 
+#error Unknown platform
+#endif
+
+#endif /* ifndef PLATFORM_H_INCLUDED */
diff --git a/fs/exfat/repair.c b/fs/exfat/repair.c
new file mode 100644
index 00000000000..9c91239b899
--- /dev/null
+++ b/fs/exfat/repair.c
@@ -0,0 +1,115 @@
+/*
+	repair.c (09.03.17)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#ifndef __UBOOT__
+#include <strings.h>
+#endif
+
+int exfat_errors_fixed;
+
+bool exfat_ask_to_fix(const struct exfat* ef)
+{
+	const char* question = "Fix (Y/N)?";
+#ifndef __UBOOT__
+	char answer[8];
+	bool yeah, nope;
+#endif
+
+	switch (ef->repair)
+	{
+	case EXFAT_REPAIR_NO:
+		return false;
+	case EXFAT_REPAIR_YES:
+		printf("%s %s", question, "Y\n");
+		return true;
+	case EXFAT_REPAIR_ASK:
+#ifndef __UBOOT__
+		do
+		{
+			printf("%s ", question);
+			fflush(stdout);
+			if (fgets(answer, sizeof(answer), stdin))
+			{
+				yeah = strcasecmp(answer, "Y\n") == 0;
+				nope = strcasecmp(answer, "N\n") == 0;
+			}
+			else
+			{
+				yeah = false;
+				nope = true;
+			}
+		}
+		while (!yeah && !nope);
+		return yeah;
+#else
+	default:
+		/* Do not attempt to repair FS in U-Boot. */
+		return false;
+#endif
+	}
+	exfat_bug("invalid repair option value: %d", ef->repair);
+#ifdef __UBOOT__
+	return false;
+#endif
+}
+
+bool exfat_fix_invalid_vbr_checksum(const struct exfat* ef, void* sector,
+		uint32_t vbr_checksum)
+{
+	size_t i;
+	off_t sector_size = SECTOR_SIZE(*ef->sb);
+
+	for (i = 0; i < sector_size / sizeof(vbr_checksum); i++)
+		((le32_t*) sector)[i] = cpu_to_le32(vbr_checksum);
+	if (exfat_pwrite(ef->dev, sector, sector_size, 11 * sector_size) < 0)
+	{
+		exfat_error("failed to write correct VBR checksum");
+		return false;
+	}
+	exfat_errors_fixed++;
+	return true;
+}
+
+bool exfat_fix_invalid_node_checksum(UNUSED const struct exfat* ef,
+		struct exfat_node* node)
+{
+	/* checksum will be rewritten by exfat_flush_node() */
+	node->is_dirty = true;
+
+	exfat_errors_fixed++;
+	return true;
+}
+
+bool exfat_fix_unknown_entry(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entry, off_t offset)
+{
+	struct exfat_entry deleted = *entry;
+
+	deleted.type &= ~EXFAT_ENTRY_VALID;
+	if (exfat_generic_pwrite(ef, dir, &deleted, sizeof(struct exfat_entry),
+			offset) != sizeof(struct exfat_entry))
+		return false;
+
+	exfat_errors_fixed++;
+	return true;
+}
diff --git a/fs/exfat/time.c b/fs/exfat/time.c
new file mode 100644
index 00000000000..f2217dd7986
--- /dev/null
+++ b/fs/exfat/time.c
@@ -0,0 +1,175 @@
+/*
+	time.c (03.02.12)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+
+/* timezone offset from UTC in seconds; positive for western timezones,
+   negative for eastern ones */
+static long exfat_timezone;
+
+#define SEC_IN_MIN 60ll
+#define SEC_IN_HOUR (60 * SEC_IN_MIN)
+#define SEC_IN_DAY (24 * SEC_IN_HOUR)
+#define SEC_IN_YEAR (365 * SEC_IN_DAY) /* not leap year */
+/* Unix epoch started at 0:00:00 UTC 1 January 1970 */
+#define UNIX_EPOCH_YEAR 1970
+/* exFAT epoch started at 0:00:00 UTC 1 January 1980 */
+#define EXFAT_EPOCH_YEAR 1980
+/* number of years from Unix epoch to exFAT epoch */
+#define EPOCH_DIFF_YEAR (EXFAT_EPOCH_YEAR - UNIX_EPOCH_YEAR)
+/* number of days from Unix epoch to exFAT epoch (considering leap days) */
+#define EPOCH_DIFF_DAYS (EPOCH_DIFF_YEAR * 365 + EPOCH_DIFF_YEAR / 4)
+/* number of seconds from Unix epoch to exFAT epoch (considering leap days) */
+#define EPOCH_DIFF_SEC (EPOCH_DIFF_DAYS * SEC_IN_DAY)
+/* number of leap years passed from exFAT epoch to the specified year
+   (excluding the specified year itself) */
+#define LEAP_YEARS(year) ((EXFAT_EPOCH_YEAR + (year) - 1) / 4 \
+		- (EXFAT_EPOCH_YEAR - 1) / 4)
+/* checks whether the specified year is leap */
+#define IS_LEAP_YEAR(year) ((EXFAT_EPOCH_YEAR + (year)) % 4 == 0)
+
+static const time_t days_in_year[] =
+{
+	/* Jan  Feb  Mar  Apr  May  Jun  Jul  Aug  Sep  Oct  Nov  Dec */
+	0,   0,  31,  59,  90, 120, 151, 181, 212, 243, 273, 304, 334
+};
+
+time_t exfat_exfat2unix(le16_t date, le16_t time, uint8_t centisec,
+		uint8_t tzoffset)
+{
+	time_t unix_time = EPOCH_DIFF_SEC;
+	uint16_t ndate = le16_to_cpu(date);
+	uint16_t ntime = le16_to_cpu(time);
+
+	uint16_t day    = ndate & 0x1f;      /* 5 bits, 1-31 */
+	uint16_t month  = ndate >> 5 & 0xf;  /* 4 bits, 1-12 */
+	uint16_t year   = ndate >> 9;        /* 7 bits, 1-127 (+1980) */
+
+	uint16_t twosec = ntime & 0x1f;      /* 5 bits, 0-29 (2 sec granularity) */
+	uint16_t min    = ntime >> 5 & 0x3f; /* 6 bits, 0-59 */
+	uint16_t hour   = ntime >> 11;       /* 5 bits, 0-23 */
+
+	if (day == 0 || month == 0 || month > 12)
+	{
+		exfat_error("bad date %u-%02hu-%02hu",
+				year + EXFAT_EPOCH_YEAR, month, day);
+		return 0;
+	}
+	if (hour > 23 || min > 59 || twosec > 29)
+	{
+		exfat_error("bad time %hu:%02hu:%02u",
+				hour, min, twosec * 2);
+		return 0;
+	}
+	if (centisec > 199)
+	{
+		exfat_error("bad centiseconds count %hhu", centisec);
+		return 0;
+	}
+
+	/* every 4th year between 1904 and 2096 is leap */
+	unix_time += year * SEC_IN_YEAR + LEAP_YEARS(year) * SEC_IN_DAY;
+	unix_time += days_in_year[month] * SEC_IN_DAY;
+	/* if it's leap year and February has passed we should add 1 day */
+	if ((EXFAT_EPOCH_YEAR + year) % 4 == 0 && month > 2)
+		unix_time += SEC_IN_DAY;
+	unix_time += (day - 1) * SEC_IN_DAY;
+
+	unix_time += hour * SEC_IN_HOUR;
+	unix_time += min * SEC_IN_MIN;
+	/* exFAT represents time with 2 sec granularity */
+	unix_time += twosec * 2;
+	unix_time += centisec / 100;
+
+	/* exFAT stores timestamps in local time, so we correct it to UTC */
+	if (tzoffset & 0x80)
+		/* lower 7 bits are signed timezone offset in 15 minute increments */
+		unix_time -= (int8_t)(tzoffset << 1) * 15 * 60 / 2;
+	else
+		/* timezone offset not present, assume our local timezone */
+		unix_time += exfat_timezone;
+
+	return unix_time;
+}
+
+void exfat_unix2exfat(time_t unix_time, le16_t* date, le16_t* time,
+		uint8_t* centisec, uint8_t* tzoffset)
+{
+	time_t shift = EPOCH_DIFF_SEC + exfat_timezone;
+	uint16_t day, month, year;
+	uint16_t twosec, min, hour;
+	int days;
+	int i;
+
+	/* time before exFAT epoch cannot be represented */
+	if (unix_time < shift)
+		unix_time = shift;
+
+	unix_time -= shift;
+
+	days = unix_time / SEC_IN_DAY;
+	year = (4 * days) / (4 * 365 + 1);
+	days -= year * 365 + LEAP_YEARS(year);
+	month = 0;
+	for (i = 1; i <= 12; i++)
+	{
+		int leap_day = (IS_LEAP_YEAR(year) && i == 2);
+		int leap_sub = (IS_LEAP_YEAR(year) && i >= 3);
+
+		if (i == 12 || days - leap_sub < days_in_year[i + 1] + leap_day)
+		{
+			month = i;
+			days -= days_in_year[i] + leap_sub;
+			break;
+		}
+	}
+	day = days + 1;
+
+	hour = (unix_time % SEC_IN_DAY) / SEC_IN_HOUR;
+	min = (unix_time % SEC_IN_HOUR) / SEC_IN_MIN;
+	twosec = (unix_time % SEC_IN_MIN) / 2;
+
+	*date = cpu_to_le16(day | (month << 5) | (year << 9));
+	*time = cpu_to_le16(twosec | (min << 5) | (hour << 11));
+	if (centisec)
+		*centisec = (unix_time % 2) * 100;
+
+	/* record our local timezone offset in exFAT (15 minute increment) format */
+	*tzoffset = (uint8_t)(-exfat_timezone / 60 / 15) | 0x80;
+}
+
+void exfat_tzset(void)
+{
+#ifndef __UBOOT__
+	time_t now;
+	struct tm* utc;
+
+	tzset();
+	now = time(NULL);
+	utc = gmtime(&now);
+	/* gmtime() always sets tm_isdst to 0 because daylight savings never
+	   affect UTC. Setting tm_isdst to -1 makes mktime() to determine whether
+	   summer time is in effect. */
+	utc->tm_isdst = -1;
+	exfat_timezone = mktime(utc) - now;
+#endif
+}
diff --git a/fs/exfat/utf.c b/fs/exfat/utf.c
new file mode 100644
index 00000000000..8a28e7621ca
--- /dev/null
+++ b/fs/exfat/utf.c
@@ -0,0 +1,254 @@
+/*
+	utf.c (13.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+
+static char* wchar_to_utf8(char* output, u32 wc, size_t outsize)
+{
+	if (wc <= 0x7f)
+	{
+		if (outsize < 1)
+			return NULL;
+		*output++ = (char) wc;
+	}
+	else if (wc <= 0x7ff)
+	{
+		if (outsize < 2)
+			return NULL;
+		*output++ = 0xc0 | (wc >> 6);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0xffff)
+	{
+		if (outsize < 3)
+			return NULL;
+		*output++ = 0xe0 | (wc >> 12);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x1fffff)
+	{
+		if (outsize < 4)
+			return NULL;
+		*output++ = 0xf0 | (wc >> 18);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x3ffffff)
+	{
+		if (outsize < 5)
+			return NULL;
+		*output++ = 0xf8 | (wc >> 24);
+		*output++ = 0x80 | ((wc >> 18) & 0x3f);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x7fffffff)
+	{
+		if (outsize < 6)
+			return NULL;
+		*output++ = 0xfc | (wc >> 30);
+		*output++ = 0x80 | ((wc >> 24) & 0x3f);
+		*output++ = 0x80 | ((wc >> 18) & 0x3f);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else
+		return NULL;
+
+	return output;
+}
+
+static const le16_t* utf16_to_wchar(const le16_t* input, u32* wc,
+		size_t insize)
+{
+	if ((le16_to_cpu(input[0]) & 0xfc00) == 0xd800)
+	{
+		if (insize < 2 || (le16_to_cpu(input[1]) & 0xfc00) != 0xdc00)
+			return NULL;
+		*wc = ((u32) (le16_to_cpu(input[0]) & 0x3ff) << 10);
+		*wc |= (le16_to_cpu(input[1]) & 0x3ff);
+		*wc += 0x10000;
+		return input + 2;
+	}
+	else
+	{
+		*wc = le16_to_cpu(*input);
+		return input + 1;
+	}
+}
+
+int exfat_utf16_to_utf8(char* output, const le16_t* input, size_t outsize,
+		size_t insize)
+{
+	const le16_t* iptr = input;
+	const le16_t* iend = input + insize;
+	char* optr = output;
+	const char* oend = output + outsize;
+	u32 wc;
+
+	while (iptr < iend)
+	{
+		iptr = utf16_to_wchar(iptr, &wc, iend - iptr);
+		if (iptr == NULL)
+		{
+			exfat_error("illegal UTF-16 sequence");
+			return -EILSEQ;
+		}
+		optr = wchar_to_utf8(optr, wc, oend - optr);
+		if (optr == NULL)
+		{
+			exfat_error("name is too long");
+			return -ENAMETOOLONG;
+		}
+		if (wc == 0)
+			return 0;
+	}
+	if (optr >= oend)
+	{
+		exfat_error("name is too long");
+		return -ENAMETOOLONG;
+	}
+	*optr = '\0';
+	return 0;
+}
+
+static const char* utf8_to_wchar(const char* input, u32* wc,
+		size_t insize)
+{
+	size_t size;
+	size_t i;
+
+	if (insize == 0)
+		exfat_bug("no input for utf8_to_wchar");
+
+	if ((input[0] & 0x80) == 0)
+	{
+		*wc = (u32) input[0];
+		return input + 1;
+	}
+	else if ((input[0] & 0xe0) == 0xc0)
+	{
+		*wc = ((u32) input[0] & 0x1f) << 6;
+		size = 2;
+	}
+	else if ((input[0] & 0xf0) == 0xe0)
+	{
+		*wc = ((u32) input[0] & 0x0f) << 12;
+		size = 3;
+	}
+	else if ((input[0] & 0xf8) == 0xf0)
+	{
+		*wc = ((u32) input[0] & 0x07) << 18;
+		size = 4;
+	}
+	else if ((input[0] & 0xfc) == 0xf8)
+	{
+		*wc = ((u32) input[0] & 0x03) << 24;
+		size = 5;
+	}
+	else if ((input[0] & 0xfe) == 0xfc)
+	{
+		*wc = ((u32) input[0] & 0x01) << 30;
+		size = 6;
+	}
+	else
+		return NULL;
+
+	if (insize < size)
+		return NULL;
+
+	/* the first byte is handled above */
+	for (i = 1; i < size; i++)
+	{
+		if ((input[i] & 0xc0) != 0x80)
+			return NULL;
+		*wc |= (input[i] & 0x3f) << ((size - i - 1) * 6);
+	}
+
+	return input + size;
+}
+
+static le16_t* wchar_to_utf16(le16_t* output, u32 wc, size_t outsize)
+{
+	if (wc <= 0xffff) /* if character is from BMP */
+	{
+		if (outsize == 0)
+			return NULL;
+		output[0] = cpu_to_le16(wc);
+		return output + 1;
+	}
+	if (outsize < 2)
+		return NULL;
+	wc -= 0x10000;
+	output[0] = cpu_to_le16(0xd800 | ((wc >> 10) & 0x3ff));
+	output[1] = cpu_to_le16(0xdc00 | (wc & 0x3ff));
+	return output + 2;
+}
+
+int exfat_utf8_to_utf16(le16_t* output, const char* input, size_t outsize,
+		size_t insize)
+{
+	const char* iptr = input;
+	const char* iend = input + insize;
+	le16_t* optr = output;
+	const le16_t* oend = output + outsize;
+	u32 wc;
+
+	while (iptr < iend)
+	{
+		iptr = utf8_to_wchar(iptr, &wc, iend - iptr);
+		if (iptr == NULL)
+		{
+			exfat_error("illegal UTF-8 sequence");
+			return -EILSEQ;
+		}
+		optr = wchar_to_utf16(optr, wc, oend - optr);
+		if (optr == NULL)
+		{
+			exfat_error("name is too long");
+			return -ENAMETOOLONG;
+		}
+		if (wc == 0)
+			break;
+	}
+	if (optr >= oend)
+	{
+		exfat_error("name is too long");
+		return -ENAMETOOLONG;
+	}
+	*optr = cpu_to_le16(0);
+	return 0;
+}
+
+size_t exfat_utf16_length(const le16_t* str)
+{
+	size_t i = 0;
+
+	while (le16_to_cpu(str[i]))
+		i++;
+	return i;
+}
diff --git a/fs/exfat/utils.c b/fs/exfat/utils.c
new file mode 100644
index 00000000000..0d97b65dcab
--- /dev/null
+++ b/fs/exfat/utils.c
@@ -0,0 +1,192 @@
+/*
+	utils.c (04.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <stdio.h>
+#include <inttypes.h>
+
+void exfat_stat(const struct exfat* ef, const struct exfat_node* node,
+		struct stat* stbuf)
+{
+	memset(stbuf, 0, sizeof(struct stat));
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		stbuf->st_mode = S_IFDIR | (0777 & ~ef->dmask);
+	else
+		stbuf->st_mode = S_IFREG | (0777 & ~ef->fmask);
+	stbuf->st_nlink = 1;
+	stbuf->st_uid = ef->uid;
+	stbuf->st_gid = ef->gid;
+	stbuf->st_size = node->size;
+	stbuf->st_blocks = ROUND_UP(node->size, CLUSTER_SIZE(*ef->sb)) / 512;
+	stbuf->st_mtime = node->mtime;
+	stbuf->st_atime = node->atime;
+	/* set ctime to mtime to ensure we don't break programs that rely on ctime
+	   (e.g. rsync) */
+	stbuf->st_ctime = node->mtime;
+}
+
+void exfat_get_name(const struct exfat_node* node,
+		char buffer[EXFAT_UTF8_NAME_BUFFER_MAX])
+{
+	if (exfat_utf16_to_utf8(buffer, node->name, EXFAT_UTF8_NAME_BUFFER_MAX,
+				EXFAT_NAME_MAX) != 0)
+		exfat_bug("failed to convert name to UTF-8");
+}
+
+static uint16_t add_checksum_byte(uint16_t sum, uint8_t byte)
+{
+	return ((sum << 15) | (sum >> 1)) + byte;
+}
+
+static uint16_t add_checksum_bytes(uint16_t sum, const void* buffer, size_t n)
+{
+	size_t i;
+
+	for (i = 0; i < n; i++)
+		sum = add_checksum_byte(sum, ((const uint8_t*) buffer)[i]);
+	return sum;
+}
+
+uint16_t exfat_start_checksum(const struct exfat_entry_meta1* entry)
+{
+	uint16_t sum = 0;
+	size_t i;
+
+	for (i = 0; i < sizeof(struct exfat_entry); i++)
+		if (i != 2 && i != 3) /* skip checksum field itself */
+			sum = add_checksum_byte(sum, ((const uint8_t*) entry)[i]);
+	return sum;
+}
+
+uint16_t exfat_add_checksum(const void* entry, uint16_t sum)
+{
+	return add_checksum_bytes(sum, entry, sizeof(struct exfat_entry));
+}
+
+le16_t exfat_calc_checksum(const struct exfat_entry* entries, int n)
+{
+	uint16_t checksum;
+	int i;
+
+	checksum = exfat_start_checksum((const struct exfat_entry_meta1*) entries);
+	for (i = 1; i < n; i++)
+		checksum = exfat_add_checksum(entries + i, checksum);
+	return cpu_to_le16(checksum);
+}
+
+uint32_t exfat_vbr_start_checksum(const void* sector, size_t size)
+{
+	size_t i;
+	uint32_t sum = 0;
+
+	for (i = 0; i < size; i++)
+		/* skip volume_state and allocated_percent fields */
+		if (i != 0x6a && i != 0x6b && i != 0x70)
+			sum = ((sum << 31) | (sum >> 1)) + ((const uint8_t*) sector)[i];
+	return sum;
+}
+
+uint32_t exfat_vbr_add_checksum(const void* sector, size_t size, uint32_t sum)
+{
+	size_t i;
+
+	for (i = 0; i < size; i++)
+		sum = ((sum << 31) | (sum >> 1)) + ((const uint8_t*) sector)[i];
+	return sum;
+}
+
+le16_t exfat_calc_name_hash(const struct exfat* ef, const le16_t* name,
+		size_t length)
+{
+	size_t i;
+	uint16_t hash = 0;
+
+	for (i = 0; i < length; i++)
+	{
+		uint16_t c = le16_to_cpu(name[i]);
+
+		/* convert to upper case */
+		c = ef->upcase[c];
+
+		hash = ((hash << 15) | (hash >> 1)) + (c & 0xff);
+		hash = ((hash << 15) | (hash >> 1)) + (c >> 8);
+	}
+	return cpu_to_le16(hash);
+}
+
+void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb)
+{
+	size_t i;
+	/* 16 EB (minus 1 byte) is the largest size that can be represented by
+	   uint64_t */
+	const char* units[] = {"bytes", "KB", "MB", "GB", "TB", "PB", "EB"};
+	uint64_t divisor = 1;
+	uint64_t temp = 0;
+
+	for (i = 0; ; i++, divisor *= 1024)
+	{
+		temp = (value + divisor / 2) / divisor;
+
+		if (temp == 0)
+			break;
+		if (temp / 1024 * 1024 == temp)
+			continue;
+		if (temp < 10240)
+			break;
+	}
+	hb->value = temp;
+	hb->unit = units[i];
+}
+
+void exfat_print_info(const struct exfat_super_block* sb,
+		uint32_t free_clusters)
+{
+	struct exfat_human_bytes hb;
+	off_t total_space = le64_to_cpu(sb->sector_count) * SECTOR_SIZE(*sb);
+	off_t avail_space = (off_t) free_clusters * CLUSTER_SIZE(*sb);
+
+	printf("File system version           %hhu.%hhu\n",
+			sb->version.major, sb->version.minor);
+	exfat_humanize_bytes(SECTOR_SIZE(*sb), &hb);
+	printf("Sector size          %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(CLUSTER_SIZE(*sb), &hb);
+	printf("Cluster size         %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(total_space, &hb);
+	printf("Volume size          %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(total_space - avail_space, &hb);
+	printf("Used space           %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(avail_space, &hb);
+	printf("Available space      %10"PRIu64" %s\n", hb.value, hb.unit);
+}
+
+bool exfat_match_option(const char* options, const char* option_name)
+{
+	const char* p;
+	size_t length = strlen(option_name);
+
+	for (p = strstr(options, option_name); p; p = strstr(p + 1, option_name))
+		if ((p == options || p[-1] == ',') &&
+				(p[length] == ',' || p[length] == '\0'))
+			return true;
+	return false;
+}
diff --git a/fs/fs.c b/fs/fs.c
index 30a8e5010f2..0b62217fd59 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -32,6 +32,7 @@
 #include <efi_loader.h>
 #include <squashfs.h>
 #include <erofs.h>
+#include <exfat.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -381,6 +382,27 @@ static struct fstype_info fstypes[] = {
 		.rename = fs_rename_unsupported,
 	},
 #endif
+#if IS_ENABLED(CONFIG_FS_EXFAT)
+	{
+		.fstype = FS_TYPE_EXFAT,
+		.name = "exfat",
+		.null_dev_desc_ok = false,
+		.probe = exfat_fs_probe,
+		.opendir = exfat_fs_opendir,
+		.readdir = exfat_fs_readdir,
+		.ls = exfat_fs_ls,
+		.read = exfat_fs_read,
+		.size = exfat_fs_size,
+		.close = exfat_fs_close,
+		.closedir = exfat_fs_closedir,
+		.exists = exfat_fs_exists,
+		.uuid = fs_uuid_unsupported,
+		.write = exfat_fs_write,
+		.ln = fs_ln_unsupported,
+		.unlink = exfat_fs_unlink,
+		.mkdir = exfat_fs_mkdir,
+	},
+#endif
 	{
 		.fstype = FS_TYPE_ANY,
 		.name = "unsupported",
@@ -574,7 +596,7 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset,
 
 	lmb_dump_all();
 
-	if (lmb_alloc_addr(addr, read_len, LMB_NONE) == addr)
+	if (!lmb_alloc_addr(addr, read_len, LMB_NONE))
 		return 0;
 
 	log_err("** Reading file would overwrite reserved memory **\n");
diff --git a/fs/fs_internal.c b/fs/fs_internal.c
index 51c1719361b..ab4847ac257 100644
--- a/fs/fs_internal.c
+++ b/fs/fs_internal.c
@@ -92,3 +92,105 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition,
 	}
 	return 1;
 }
+
+int fs_devwrite(struct blk_desc *blk, struct disk_partition *partition,
+	        lbaint_t sector, int byte_offset, int byte_len, const char *buf)
+{
+	unsigned block_len;
+	int log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (blk ? blk->blksz : 0));
+	if (blk == NULL) {
+		log_err("** Invalid Block Device Descriptor (NULL)\n");
+		return 0;
+	}
+	log2blksz = blk->log2blksz;
+
+	/* Check partition boundaries */
+	if ((sector + ((byte_offset + byte_len - 1) >> log2blksz))
+	    >= partition->size) {
+		log_debug("read outside partition " LBAFU "\n", sector);
+		return 0;
+	}
+
+	/* Get the read to the beginning of a partition */
+	sector += byte_offset >> log2blksz;
+	byte_offset &= blk->blksz - 1;
+
+	log_debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
+
+	if (byte_offset != 0) {
+		int readlen;
+		/* read first part which isn't aligned with start of sector */
+		if (blk_dread(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s read error **\n", __func__);
+			return 0;
+		}
+
+		readlen = min((int)blk->blksz - byte_offset,
+			      byte_len);
+		memcpy(sec_buf + byte_offset, buf, readlen);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error **\n", __func__);
+			return 0;
+		}
+		buf += readlen;
+		byte_len -= readlen;
+		sector++;
+	}
+
+	if (byte_len == 0)
+		return 1;
+
+	/* write sector aligned part */
+	block_len = byte_len & ~(blk->blksz - 1);
+
+	if (block_len == 0) {
+		if (blk_dread(blk, partition->start + sector, 1,
+			  (void *)sec_buf) != 1) {
+			log_err(" ** %s read error **\n", __func__);
+			return 0;
+		}
+
+		memcpy(sec_buf, buf, byte_len);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error **\n", __func__);
+			return 0;
+		}
+
+		return 1;
+	}
+
+	if (blk_dwrite(blk, partition->start + sector,
+		       block_len >> log2blksz, (void *)buf) !=
+			block_len >> log2blksz) {
+		log_err(" ** %s write error - block\n", __func__);
+		return 0;
+	}
+	block_len = byte_len & ~(blk->blksz - 1);
+	buf += block_len;
+	byte_len -= block_len;
+	sector += block_len / blk->blksz;
+
+	if (byte_len != 0) {
+		/* read rest of data which are not in whole sector */
+		if (blk_dread(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err("* %s read error - last part **\n", __func__);
+			return 0;
+		}
+
+		memcpy(sec_buf, buf, byte_len);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error - last part **\n", __func__);
+			return 0;
+		}
+	}
+	return 1;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index b8b1f1338c6..8ef19adc990 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -36,7 +36,7 @@ struct acpi_ctx;
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
  */
-struct acpi_rsdp {
+struct __packed acpi_rsdp {
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 789adf2c3f9..506ee51cdb0 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -23,7 +23,7 @@
 #include <board_f.h>
 #include <event_internal.h>
 #include <fdtdec.h>
-#include <membuff.h>
+#include <membuf.h>
 #include <linux/list.h>
 #include <linux/build_bug.h>
 #include <asm-offsets.h>
@@ -316,14 +316,14 @@ struct global_data {
 	 *
 	 * This buffer is used to collect output during console recording.
 	 */
-	struct membuff console_out;
+	struct membuf console_out;
 	/**
 	 * @console_in: input buffer for console recording
 	 *
 	 * If console recording is activated, this buffer can be used to
 	 * emulate input.
 	 */
-	struct membuff console_in;
+	struct membuf console_in;
 #endif
 #if CONFIG_IS_ENABLED(VIDEO)
 	/**
diff --git a/include/blkmap.h b/include/blkmap.h
index d53095437fa..57555fda4fb 100644
--- a/include/blkmap.h
+++ b/include/blkmap.h
@@ -7,6 +7,7 @@
 #ifndef _BLKMAP_H
 #define _BLKMAP_H
 
+#include <blk.h>
 #include <dm/lists.h>
 
 /**
@@ -60,10 +61,12 @@ int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  * @blknr: Start block number of the mapping
  * @blkcnt: Number of blocks to map
  * @paddr: The target physical memory address of the mapping
+ * @preserve: Mapping intended to be preserved for subsequent stages,
+ *		like the OS (e.g. ISO installer)
  * Returns: 0 on success, negative error code on failure
  */
 int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		    phys_addr_t paddr);
+		    phys_addr_t paddr, bool preserve);
 
 /**
  * blkmap_from_label() - Find blkmap from label
@@ -102,4 +105,32 @@ int blkmap_destroy(struct udevice *dev);
 int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
 			  struct udevice **devp);
 
+/**
+ * blkmap_get_preserved_pmem_slices() - Look for memory mapped preserved slices
+ * @cb: Callback function to call for the blkmap slice
+ * @ctx: Argument to be passed to the callback function
+ *
+ * The function is used to iterate through all the blkmap slices, looking
+ * specifically for memory mapped blkmap mapping which has been
+ * created with the preserve attribute. The function looks for such slices
+ * with the relevant attributes and then calls the callback function which
+ * then does additional configuration as needed. The callback function is
+ * invoked for all the discovered slices, unless there is an error returned
+ * by the callback, in which case the function returns that error.
+ *
+ * The callback function has the following arguments
+ * @ctx:	Argument to be passed to the callback function
+ * @addr:	Start address of the memory mapped slice
+ * @size:	Size of the memory mapped slice
+ *
+ * Typically, the callback will perform some configuration needed for the
+ * information passed on to it. An example of this would be setting up the
+ * pmem node in a device-tree(passed through the ctx argument) with the
+ * parameters passed on to the callback.
+ *
+ * Return: 0 on success, negative error on failure
+ */
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+					       u64 size), void *ctx);
+
 #endif	/* _BLKMAP_H */
diff --git a/include/bootflow.h b/include/bootflow.h
index 480cf8a5af1..d408b8c85bd 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -160,6 +160,7 @@ struct bootflow_img {
  * before using it
  * @BOOTFLOWIF_ALL: Return bootflows with errors as well
  * @BOOTFLOWIF_HUNT: Hunt for new bootdevs using the bootdrv hunters
+ * @BOOTFLOWIF_ONLY_BOOTABLE: Only consider partitions marked 'bootable'
  *
  * Internal flags:
  * @BOOTFLOWIF_SINGLE_DEV: (internal) Just scan one bootdev
@@ -176,6 +177,7 @@ enum bootflow_iter_flags_t {
 	BOOTFLOWIF_SHOW			= 1 << 1,
 	BOOTFLOWIF_ALL			= 1 << 2,
 	BOOTFLOWIF_HUNT			= 1 << 3,
+	BOOTFLOWIF_ONLY_BOOTABLE	= BIT(4),
 
 	/*
 	 * flags used internally by standard boot - do not set these when
diff --git a/include/bootm.h b/include/bootm.h
index 465577a66f5..61160705215 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -44,21 +44,6 @@ struct cmd_tbl;
  * @argc: Number of arguments to the command (excluding the actual command).
  *	This is 0 if there are no arguments
  * @argv: NULL-terminated list of arguments, or NULL if there are no arguments
- *
- * For zboot:
- * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already
- *	been loaded and does not exist (as a cohesive whole) in memory
- * @bzimage_size: Size of the bzImage, or 0 to detect this
- * @initrd_addr: Address of the initial ramdisk, or 0 if none
- * @initrd_size: Size of the initial ramdisk, or 0 if none
- * @load_address: Address where the bzImage is moved before booting, either
- *	BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- *	This is set up when loading the zimage
- * @base_ptr: Pointer to the boot parameters, typically at address
- *	DEFAULT_SETUP_BASE
- *	This is set up when loading the zimage
- * @cmdline: Environment variable containing the 'override' command line, or
- *	NULL to use the one in the setup block
  */
 struct bootm_info {
 	const char *addr_img;
@@ -69,39 +54,11 @@ struct bootm_info {
 	const char *cmd_name;
 	int argc;
 	char *const *argv;
-
-	/* zboot items */
-#ifdef CONFIG_X86
-	ulong bzimage_addr;
-	ulong bzimage_size;
-	ulong initrd_addr;
-	ulong initrd_size;
-	ulong load_address;
-	struct boot_params *base_ptr;
-	const char *cmdline;
-#endif
 };
 
-/* macro to allow setting fields in generic code */
-#ifdef CONFIG_X86
-#define bootm_x86_set(_bmi, _field, _val)	(_bmi)->_field = (_val)
-#else
-#define bootm_x86_set(_bmi, _field, _val)
-#endif
-
-static inline ulong bootm_len(void)
-{
-#ifdef CONFIG_SYS_BOOTM_LEN
-	return CONFIG_SYS_BOOTM_LEN;
-#endif
-	return 0;
-}
-
 /**
  * bootm_init() - Set up a bootm_info struct with useful defaults
  *
- * @bmi: Bootm information
- *
  * Set up the struct with default values for all members:
  * @boot_progress is set to true and @images is set to the global images
  * variable. Everything else is set to NULL except @argc which is 0
@@ -117,7 +74,7 @@ void bootm_init(struct bootm_info *bmi);
  *  - disabled interrupts.
  *
  * @flag: Flags indicating what to do (BOOTM_STATE_...)
- * @bmi: Bootm information
+ * bmi: Bootm information
  * Return: 1 on error. On success the OS boots so this function does
  * not return.
  */
@@ -318,15 +275,6 @@ int bootm_process_cmdline_env(int flags);
 /**
  * zboot_run() - Run through the various steps to boot a zimage
  *
- * @bmi: Bootm information, with bzimage_size, initrd_addr, initrd_size and
- * cmdline set up. If base_ptr is 0, then bzimage_addr must be set to the start
- * of the bzImage. Otherwise base_ptr and load_address must be provided.
- */
-int zboot_run(struct bootm_info *bmi);
-
-/**
- * zboot_run_args() - Run through the various steps to boot a zimage
- *
  * Boot a zimage, given the component parts
  *
  * @addr: Address where the bzImage is moved before booting, either
@@ -341,8 +289,8 @@ int zboot_run(struct bootm_info *bmi);
  *	to use for booting
  * Return: -EFAULT on error (normally it does not return)
  */
-int zboot_run_args(ulong addr, ulong size, ulong initrd, ulong initrd_size,
-		   ulong base, char *cmdline);
+int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+	      ulong base, char *cmdline);
 
 /*
  * zimage_get_kernel_version() - Get the version string from a kernel
@@ -359,10 +307,11 @@ const char *zimage_get_kernel_version(struct boot_params *params,
  *
  * This shows all available information in a zimage that has been loaded.
  *
- * @bmi: Bootm information, with valid base_ptr
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ *	DEFAULT_SETUP_BASE
  * @show_cmdline: true to show the full command line
  */
-void zimage_dump(struct bootm_info *bmi, bool show_cmdline);
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
 
 /*
  * bootm_boot_start() - Boot an image at the given address
diff --git a/include/bootstd.h b/include/bootstd.h
index 3398e48e88b..2bc464756dd 100644
--- a/include/bootstd.h
+++ b/include/bootstd.h
@@ -22,6 +22,9 @@ struct udevice;
  * This is attached to the (only) bootstd device, so there is only one instance
  * of this struct. It provides overall information about bootdevs and bootflows.
  *
+ * TODO(sjg@chromium.org): Convert prefixes, bootdev_order and env_order to use
+ *	alist
+ *
  * @prefixes: NULL-terminated list of prefixes to use for bootflow filenames,
  *	e.g. "/", "/boot/"; NULL if none
  * @bootdev_order: Order to use for bootdevs (or NULL if none), with each item
diff --git a/include/clk.h b/include/clk.h
index 045e923a529..a6ef4e02692 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -351,6 +351,15 @@ static inline int clk_get_by_name_nodev_optional(ofnode node, const char *name,
 }
 
 /**
+ * clk_resolve_parent_clk - Determine name of clock udevice based on clock-names
+ * @dev:	The client udevice.
+ * @name:	The name of the clock to look up.
+ *
+ * Return name of the clock udevice which represents clock with clock-names name.
+ */
+const char *clk_resolve_parent_clk(struct udevice *dev, const char *name);
+
+/**
  * enum clk_defaults_stage - What stage clk_set_defaults() is called at
  * @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned
  *                    by this clock driver will be defered until after probing.
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 0a4e4b8ff85..8ac3a4feeb8 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -112,7 +112,7 @@
 #define BOOTEFI_NAME "bootarm.efi"
 #elif defined(CONFIG_X86_RUN_32BIT)
 #define BOOTEFI_NAME "bootia32.efi"
-#elif defined(CONFIG_X86_RUN_64BIT)
+#elif defined(CONFIG_X86_64)
 #define BOOTEFI_NAME "bootx64.efi"
 #elif defined(CONFIG_ARCH_RV32I)
 #define BOOTEFI_NAME "bootriscv32.efi"
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index aa31f3b05a0..266b77fbf68 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -37,20 +37,4 @@
 
 /* CPSW Ethernet */
 
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS      0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS        0x140000
-#define CFG_SYS_SPI_ARGS_SIZE        0x80000
-
-/* SPI SPL */
-
 #endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/an7581.h b/include/configs/an7581.h
new file mode 100644
index 00000000000..64f04c9d9a5
--- /dev/null
+++ b/include/configs/an7581.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for Airoha AN7581
+ */
+
+#ifndef __AN7581_H
+#define __AN7581_H
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+
+#define CFG_SYS_INIT_RAM_ADDR           CONFIG_TEXT_BASE
+#define CFG_SYS_INIT_RAM_SIZE           SZ_2M
+
+/* DRAM */
+#define CFG_SYS_SDRAM_BASE		0x80000000
+
+#endif
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 98b1e5af2c0..19d71d6066f 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -29,11 +29,6 @@
  * 0x1F00000 - 0x2000000 : SPI.factory  (1MiB)
  */
 
-/* Below values are "dummy" - only to avoid build break */
-#define CFG_SYS_SPI_KERNEL_OFFS      0x150000
-#define CFG_SYS_SPI_ARGS_OFFS        0x140000
-#define CFG_SYS_SPI_ARGS_SIZE        0x10000
-
 #define CFG_MXC_UART_BASE		UART5_BASE
 
 /* MMC Configs */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 96dcd731cb6..3c960ca2ce2 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -47,22 +47,6 @@
 
 #include <configs/ti_omap5_common.h>
 
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS	0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS	0x140000
-#define CFG_SYS_SPI_ARGS_SIZE	0x80000
-
-/* SPI SPL */
-
 /* NAND support */
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
diff --git a/include/configs/ouya.h b/include/configs/ouya.h
new file mode 100644
index 00000000000..cc86c1002e3
--- /dev/null
+++ b/include/configs/ouya.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  (C) Copyright 2010,2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING		"Ouya Game Console"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 2996b375723..cd8d0438ba6 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -11,7 +11,6 @@
 
 #include <linux/sizes.h>
 
-#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
 #define RISCV_MMODE_TIMEROFF		0xbff8
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 27e0912665b..e0064edc5c9 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -11,6 +11,5 @@
 
 #include <linux/sizes.h>
 
-#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/xea.h b/include/configs/xea.h
index 00d62748733..21454d13d21 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h
@@ -12,14 +12,6 @@
 #ifndef __CONFIGS_XEA_H__
 #define __CONFIGS_XEA_H__
 
-#include <linux/sizes.h>
-
-/* SPL */
-
-#define CFG_SYS_SPI_KERNEL_OFFS	SZ_1M
-#define CFG_SYS_SPI_ARGS_OFFS	SZ_512K
-#define CFG_SYS_SPI_ARGS_SIZE	SZ_32K
-
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 13941ba3589..ec78f2ee8ed 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -194,12 +194,6 @@
 	"dfu_bufsiz=0x1000\0"
 #endif
 
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CFG_SYS_SPI_KERNEL_OFFS	0x80000
-# define CFG_SYS_SPI_ARGS_OFFS	0xa0000
-# define CFG_SYS_SPI_ARGS_SIZE	0xa0000
-#endif
-
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
 #endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 37c77aa1611..93ae5891a07 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -191,14 +191,6 @@
 
 /* Not using MMC raw mode - just for compilation purpose */
 
-/* qspi mode is working fine */
-#ifdef CONFIG_ZYNQ_QSPI
-#define CFG_SYS_SPI_ARGS_OFFS	0x200000
-#define CFG_SYS_SPI_ARGS_SIZE	0x80000
-#define CFG_SYS_SPI_KERNEL_OFFS	(CFG_SYS_SPI_ARGS_OFFS + \
-					CFG_SYS_SPI_ARGS_SIZE)
-#endif
-
 /* SP location before relocation, must use scratch RAM */
 
 /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
diff --git a/include/dbsc5.h b/include/dbsc5.h
new file mode 100644
index 00000000000..cec937d89e7
--- /dev/null
+++ b/include/dbsc5.h
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024-2025 Renesas Electronics Corp.
+ */
+
+#ifndef __INCLUDE_DBSC5_H__
+#define __INCLUDE_DBSC5_H__
+
+/* The number of channels V4H has */
+#define DRAM_CH_CNT			4
+/* The number of slices V4H has */
+#define SLICE_CNT			2
+/* The number of chip select V4H has */
+#define CS_CNT				2
+
+struct renesas_dbsc5_board_config {
+	/* Channels in use */
+	u8 bdcfg_phyvalid;
+	/* Read vref (SoC) training range */
+	u32 bdcfg_vref_r;
+	/* Write vref (MR14, MR15) training range */
+	u16 bdcfg_vref_w;
+	/* CA vref (MR12) training range */
+	u16 bdcfg_vref_ca;
+	/* RFM required check */
+	bool bdcfg_rfm_chk;
+
+	/* Board parameter about channels */
+	struct {
+		/*
+		 * 0x00:  4Gb dual channel die /  2Gb single channel die
+		 * 0x01:  6Gb dual channel die /  3Gb single channel die
+		 * 0x02:  8Gb dual channel die /  4Gb single channel die
+		 * 0x03: 12Gb dual channel die /  6Gb single channel die
+		 * 0x04: 16Gb dual channel die /  8Gb single channel die
+		 * 0x05: 24Gb dual channel die / 12Gb single channel die
+		 * 0x06: 32Gb dual channel die / 16Gb single channel die
+		 * 0x07: 24Gb single channel die
+		 * 0x08: 32Gb single channel die
+		 * 0xFF: NO_MEMORY
+		 */
+		u8 bdcfg_ddr_density[CS_CNT];
+		/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+		u32 bdcfg_ca_swap;
+		/* SoC dqsX([1][0]) -> MEM dqsY: */
+		u8 bdcfg_dqs_swap;
+		/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
+		u32 bdcfg_dq_swap[SLICE_CNT];
+		/* SoC dm -> MEM dqY/dm:  (8 means DM) */
+		u8 bdcfg_dm_swap[SLICE_CNT];
+		/* SoC ckeX([1][0]) -> MEM csY */
+		u8 bdcfg_cs_swap;
+	} ch[4];
+};
+
+#endif	/* __INCLUDE_DBSC5_H__ */
diff --git a/include/dm/device.h b/include/dm/device.h
index add67f9ec06..678cd83c271 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -81,7 +81,10 @@ struct driver_info;
  */
 #define DM_FLAG_VITAL			(1 << 14)
 
-/* Device must be probed after it was bound */
+/* Device must be probed after it was bound. This flag is per-device and does
+ * nothing if set on a U_BOOT_DRIVER() definition. Apply it with
+ * dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND) in the devices bind function.
+ */
 #define DM_FLAG_PROBE_AFTER_BIND	(1 << 15)
 
 /*
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index cc59eeb1dd1..52657aa3deb 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,9 @@
 /* Information about a serial port */
 struct mxc_serial_plat {
 	struct mxc_uart *reg;  /* address of registers in physical memory */
+#if CONFIG_IS_ENABLED(CLK_CCF)
+	struct clk_bulk clks;
+#endif
 	bool use_dte;
 };
 
diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h
new file mode 100644
index 00000000000..74db58b27ef
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit-k1-reset.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+/* APBC */
+#define	RESET_UART1   1
+#define	RESET_UART2   2
+#define	RESET_GPIO    3
+#define	RESET_PWM0    4
+#define	RESET_PWM1    5
+#define	RESET_PWM2    6
+#define	RESET_PWM3    7
+#define	RESET_PWM4    8
+#define	RESET_PWM5    9
+#define	RESET_PWM6    10
+#define	RESET_PWM7    11
+#define	RESET_PWM8    12
+#define	RESET_PWM9    13
+#define	RESET_PWM10   14
+#define	RESET_PWM11   15
+#define	RESET_PWM12   16
+#define	RESET_PWM13   17
+#define	RESET_PWM14   18
+#define	RESET_PWM15   19
+#define	RESET_PWM16   20
+#define	RESET_PWM17   21
+#define	RESET_PWM18   22
+#define	RESET_PWM19   23
+#define	RESET_SSP3    24
+#define	RESET_UART3   25
+#define	RESET_RTC     26
+#define	RESET_TWSI0   27
+#define	RESET_TIMERS1 28
+#define	RESET_AIB     29
+#define	RESET_TIMERS2 30
+#define	RESET_ONEWIRE 31
+#define	RESET_SSPA0   32
+#define	RESET_SSPA1   33
+#define	RESET_DRO     34
+#define	RESET_IR      35
+#define	RESET_TWSI1   36
+#define	RESET_TSEN    37
+#define	RESET_TWSI2   38
+#define	RESET_TWSI4   39
+#define	RESET_TWSI5   40
+#define	RESET_TWSI6   41
+#define	RESET_TWSI7   42
+#define	RESET_TWSI8   43
+#define	RESET_IPC_AP2AUD  44
+#define	RESET_UART4   45
+#define	RESET_UART5   46
+#define	RESET_UART6   47
+#define	RESET_UART7   48
+#define	RESET_UART8   49
+#define	RESET_UART9   50
+#define	RESET_CAN0    51
+
+/* MPMU */
+#define	RESET_WDT     52
+
+/* APMU */
+#define	RESET_JPG        53
+#define	RESET_CSI        54
+#define	RESET_CCIC2_PHY  55
+#define	RESET_CCIC3_PHY  56
+#define	RESET_ISP        57
+#define	RESET_ISP_AHB    58
+#define	RESET_ISP_CI     59
+#define	RESET_ISP_CPP    60
+#define	RESET_LCD        61
+#define	RESET_DSI_ESC    62
+#define	RESET_V2D        63
+#define	RESET_MIPI       64
+#define	RESET_LCD_SPI    65
+#define	RESET_LCD_SPI_BUS  66
+#define	RESET_LCD_SPI_HBUS 67
+#define	RESET_LCD_MCLK     68
+#define	RESET_CCIC_4X      69
+#define	RESET_CCIC1_PHY    70
+#define	RESET_SDH_AXI      71
+#define	RESET_SDH0         72
+#define	RESET_SDH1         73
+#define	RESET_USB_AXI      74
+#define	RESET_USBP1_AXI    75
+#define	RESET_USB3_0       76
+#define	RESET_QSPI         77
+#define	RESET_QSPI_BUS     78
+#define	RESET_DMA          79
+#define	RESET_AES          80
+#define	RESET_VPU          81
+#define	RESET_GPU          82
+#define	RESET_SDH2         83
+#define	RESET_MC           84
+#define	RESET_EM_AXI       85
+#define	RESET_EM           86
+#define	RESET_AUDIO_SYS    87
+#define	RESET_HDMI         88
+#define	RESET_PCIE0        89
+#define	RESET_PCIE1        90
+#define	RESET_PCIE2        91
+#define	RESET_EMAC0        92
+#define	RESET_EMAC1        93
+
+/* APBC2 */
+#define	RESET_SEC_UART1    94
+#define	RESET_SEC_SSP2     95
+#define	RESET_SEC_TWSI3    96
+#define	RESET_SEC_RTC      97
+#define	RESET_SEC_TIMERS0  98
+#define	RESET_SEC_KPC      99
+#define	RESET_SEC_GPIO     100
+#define	RESET_NUMBER       101
+
+#endif
diff --git a/include/efi.h b/include/efi.h
index d005cb6181e..f9bbb175c3a 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -705,4 +705,17 @@ static inline bool efi_use_host_arch(void)
  */
 int efi_get_pxe_arch(void);
 
+/**
+ * fdt_efi_pmem_setup() - Pmem setup in DT and EFI memory map
+ * @fdt: Devicetree to add the pmem nodes to
+ *
+ * Iterate through all the blkmap devices, look for BLKMAP_MEM devices,
+ * and add pmem nodes corresponding to the blkmap slice to the
+ * devicetree along with removing the corresponding region from the
+ * EFI memory map.
+ *
+ * Returns: 0 on success, negative error on failure
+ */
+int fdt_efi_pmem_setup(void *fdt);
+
 #endif /* _LINUX_EFI_H */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index e9c10819ba2..5f769786786 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -878,6 +878,21 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
 /* Adds a range into the EFI memory map */
 efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type);
 
+/**
+ * efi_update_memory_map() - update the memory map by adding/removing pages
+ *
+ * @start:			start address, must be a multiple of
+ *				EFI_PAGE_SIZE
+ * @pages:			number of pages to add
+ * @memory_type:		type of memory added
+ * @overlap_conventional:	region may only overlap free(conventional)
+ *				memory
+ * @remove:			remove memory map
+ * Return:			status code
+ */
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+				   bool overlap_conventional, bool remove);
+
 /* Called by board init to initialize the EFI drivers */
 efi_status_t efi_driver_init(void);
 /* Called when a block device is added */
diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env
index f4e381994be..6a457d1b75b 100644
--- a/include/env/nvidia/prod_upd.env
+++ b/include/env/nvidia/prod_upd.env
@@ -3,6 +3,7 @@ boot_block_size=0x1000
 bootloader_file=u-boot-dtb-tegra.bin
 spi_size=0x400000
 boot_dev=0
+boot_interface=mmc
 
 flash_uboot=echo Preparing RAM;
 	mw ${kernel_addr_r} 0 ${boot_block_size_r};
@@ -11,9 +12,9 @@ flash_uboot=echo Preparing RAM;
 		mmc dev 0 1;
 		mmc read ${kernel_addr_r} 0 ${boot_block_size};
 		echo Reading bootloader;
-		if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
+		if load ${boot_interface} ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
 		then echo Calculating bootloader size;
-			size mmc ${boot_dev}:1 ${bootloader_file};
+			size ${boot_interface} ${boot_dev}:1 ${bootloader_file};
 			ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
 			echo Writing bootloader to eMMC;
 			mmc dev 0 1;
diff --git a/include/exfat.h b/include/exfat.h
new file mode 100644
index 00000000000..7e43beeb348
--- /dev/null
+++ b/include/exfat.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EXFAT_H_
+#define _EXFAT_H_
+
+struct disk_partition;
+
+int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp);
+int exfat_fs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+int exfat_fs_ls(const char *dirname);
+int exfat_fs_probe(struct blk_desc *fs_dev_desc,
+		struct disk_partition *fs_partition);
+int exfat_fs_read(const char *filename, void *buf, loff_t offset,
+	       loff_t len, loff_t *actread);
+int exfat_fs_size(const char *filename, loff_t *size);
+int exfat_fs_exists(const char *filename);
+void exfat_fs_close(void);
+void exfat_fs_closedir(struct fs_dir_stream *dirs);
+
+int exfat_fs_unlink(const char *filename);
+int exfat_fs_mkdir(const char *dirname);
+int exfat_fs_write(const char *filename, void *buf, loff_t offset,
+		   loff_t len, loff_t *actwrite);
+
+#endif /* _EXFAT_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index f0ad2e6b365..049190cf3d7 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -471,6 +471,20 @@ int fdt_valid(struct fdt_header **blobp);
  */
 int fdt_get_cells_len(const void *blob, char *nr_cells_name);
 
+/**
+ * fdt_fixup_pmem_region() - add a pmem node on the device tree
+ *
+ * This functions adds/updates a pmem node to the device tree.
+ * Usually used with EFI installers to preserve installer
+ * images
+ *
+ * @fdt:	device tree provided by caller
+ * @addr:	start address of the pmem node
+ * @size:	size of the memory of the pmem node
+ * Return:	0 on success or < 0 on failure
+ */
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size);
+
 #endif /* !USE_HOSTCC */
 
 #ifdef USE_HOSTCC
diff --git a/include/fs.h b/include/fs.h
index 54449faf2e5..731aaa02637 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -18,6 +18,7 @@ struct cmd_tbl;
 #define FS_TYPE_SQUASHFS 6
 #define FS_TYPE_EROFS   7
 #define FS_TYPE_SEMIHOSTING 8
+#define FS_TYPE_EXFAT   9
 
 struct blk_desc;
 
@@ -173,7 +174,7 @@ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
 #define FS_DT_REG  8         /* regular file */
 #define FS_DT_LNK  10        /* symbolic link */
 
-#define FS_DIRENT_NAME_LEN 256
+#define FS_DIRENT_NAME_LEN	CONFIG_IS_ENABLED(FS_EXFAT, (1024), (256))
 
 /**
  * struct fs_dirent - directory entry
diff --git a/include/fs_internal.h b/include/fs_internal.h
index 07f6bc5ea40..351582db61a 100644
--- a/include/fs_internal.h
+++ b/include/fs_internal.h
@@ -12,5 +12,7 @@
 
 int fs_devread(struct blk_desc *, struct disk_partition *, lbaint_t, int, int,
 	       char *);
+int fs_devwrite(struct blk_desc *, struct disk_partition *, lbaint_t, int, int,
+	        const char *);
 
 #endif /* __U_BOOT_FS_INTERNAL_H__ */
diff --git a/include/fuse.h b/include/fuse.h
index 4519821af7e..902b5f56a74 100644
--- a/include/fuse.h
+++ b/include/fuse.h
@@ -12,6 +12,7 @@
 #define _FUSE_H_
 
 #include <linux/types.h>
+#include <linux/errno.h>
 
 /*
  * Read/Sense/Program/Override interface:
@@ -25,5 +26,13 @@ int fuse_read(u32 bank, u32 word, u32 *val);
 int fuse_sense(u32 bank, u32 word, u32 *val);
 int fuse_prog(u32 bank, u32 word, u32 val);
 int fuse_override(u32 bank, u32 word, u32 val);
+#ifdef CONFIG_CMD_FUSE_WRITEBUFF
+int fuse_writebuff(ulong addr);
+#else
+static inline int fuse_writebuff(ulong addr)
+{
+	return -EPERM;
+}
+#endif	/* CONFIG_CMD_FUSE_WRITEBUFF */
 
 #endif	/* _FUSE_H_ */
diff --git a/include/image.h b/include/image.h
index 2455baa6667..c1db8383459 100644
--- a/include/image.h
+++ b/include/image.h
@@ -244,7 +244,7 @@ enum image_type_t {
  * New IDs *MUST* be appended at the end of the list and *NEVER*
  * inserted for backward compatibility.
  */
-enum image_comp_t {
+enum {
 	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
 	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
 	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
@@ -598,13 +598,10 @@ int boot_get_setup(struct bootm_headers *images, uint8_t arch, ulong *setup_star
 		   ulong *setup_len);
 
 /* Image format types, returned by _get_format() routine */
-enum image_fmt_t {
-	IMAGE_FORMAT_INVALID,
-	IMAGE_FORMAT_LEGACY,		/* legacy image_header based format */
-	IMAGE_FORMAT_FIT,		/* new, libfdt based format */
-	IMAGE_FORMAT_ANDROID,		/* Android boot image */
-	IMAGE_FORMAT_BOOTI,		/* Arm64/RISC-V boot image */
-};
+#define IMAGE_FORMAT_INVALID	0x00
+#define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
+#define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
+#define IMAGE_FORMAT_ANDROID	0x03	/* Android boot image */
 
 /**
  * genimg_get_kernel_addr_fit() - Parse FIT specifier
@@ -633,43 +630,10 @@ ulong genimg_get_kernel_addr_fit(const char *const img_addr,
 				 const char **fit_uname_kernel);
 
 ulong genimg_get_kernel_addr(char * const img_addr);
-
-/**
- * genimg_get_format - get image format type
- * @img_addr: image start address
- * Return: image format type or IMAGE_FORMAT_INVALID if no image is present
- *
- * genimg_get_format() checks whether provided address points to a valid
- * legacy or FIT image.
- *
- * New uImage format and FDT blob are based on a libfdt. FDT blob
- * may be passed directly or embedded in a FIT image. In both situations
- * genimg_get_format() must be able to dectect libfdt header.
- */
-enum image_fmt_t genimg_get_format(const void *img_addr);
-
-/**
- * genimg_get_format_comp() - Like genimg_get_format() but adds compressed booti
- *
- * If a compressed file is detected (with image_decomp_type()) and
- * CONFIG_CMD_BOOTI is enabled, then this returns IMAGE_FORMAT_BOOTI
- *
- * @img_addr: image start address
- * Return: image format type or IMAGE_FORMAT_INVALID if no image is present
- */
-enum image_fmt_t genimg_get_format_comp(const void *img_addr);
-
+int genimg_get_format(const void *img_addr);
 int genimg_has_config(struct bootm_headers *images);
 
 /**
- * booti_is_valid() - Check if an image appears to be an Arm64 image
- *
- * @img: Pointer to image
- * Return: true if the image has the Arm64 magic
- */
-bool booti_is_valid(const void *img);
-
-/**
  * boot_get_fpga() - Locate the FPGA image
  *
  * @images: Information about images being loaded
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 59f9c241b84..5ea2171492e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -105,7 +105,7 @@ struct clk_gate {
 #define CLK_GATE_HIWORD_MASK		BIT(1)
 
 extern const struct clk_ops clk_gate_ops;
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
 			      const char *parent_name, unsigned long flags,
 			      void __iomem *reg, u8 bit_idx,
 			      u8 clk_gate_flags, spinlock_t *lock);
@@ -223,7 +223,7 @@ struct clk_composite {
 
 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
 
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
 		const char * const *parent_names, int num_parents,
 		struct clk *mux_clk, const struct clk_ops *mux_ops,
 		struct clk *rate_clk, const struct clk_ops *rate_ops,
@@ -233,16 +233,16 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 int clk_register(struct clk *clk, const char *drv_name, const char *name,
 		 const char *parent_name);
 
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
 
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags);
 
-struct clk *clk_register_mux(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 5eba6334e60..b65bff7e97d 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -65,9 +65,7 @@ struct stat {
 	unsigned long	__unused5;
 };
 
-#endif	/* __PPC__ */
-
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+#elif defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
 	defined (__microblaze__) || defined (__nios2__)
 
 struct stat {
@@ -93,9 +91,7 @@ struct stat {
 	unsigned long  __unused5;
 };
 
-#endif	/* __ARM__ */
-
-#if defined (__MIPS__)
+#elif defined (__MIPS__)
 
 struct stat {
 	dev_t		st_dev;
@@ -124,9 +120,7 @@ struct stat {
 	long		st_pad4[14];
 };
 
-#endif	/* __MIPS__ */
-
-#if defined(__SH__) || defined(__XTENSA__)
+#elif defined(__SH__) || defined(__XTENSA__)
 
 struct stat {
 	unsigned long st_dev;
@@ -149,7 +143,38 @@ struct stat {
 	unsigned long  __unused5;
 };
 
-#endif /* __SH__  || __XTENSA__ */
+#else
+
+/*
+ * Everybody gets this wrong and has to stick with it for all
+ * eternity. Hopefully, this version gets used by new architectures
+ * so they don't fall into the same traps.
+ *
+ */
+struct stat {
+	unsigned long	st_dev;		/* Device.  */
+	unsigned long	st_ino;		/* File serial number.  */
+	unsigned int	st_mode;	/* File mode.  */
+	unsigned int	st_nlink;	/* Link count.  */
+	unsigned int	st_uid;		/* User ID of the file's owner.  */
+	unsigned int	st_gid;		/* Group ID of the file's group. */
+	unsigned long	st_rdev;	/* Device number, if device.  */
+	unsigned long	__pad1;
+	long		st_size;	/* Size of file, in bytes.  */
+	int		st_blksize;	/* Optimal block size for I/O.  */
+	int		__pad2;
+	long		st_blocks;	/* Number 512-byte blocks allocated. */
+	long		st_atime;	/* Time of last access.  */
+	unsigned long	st_atime_nsec;
+	long		st_mtime;	/* Time of last modification.  */
+	unsigned long	st_mtime_nsec;
+	long		st_ctime;	/* Time of last status change.  */
+	unsigned long	st_ctime_nsec;
+	unsigned int	__unused4;
+	unsigned int	__unused5;
+};
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/include/lmb.h b/include/lmb.h
index 09297a4f530..0d316c64c0a 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -135,9 +135,9 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
  * parameter. The base parameter is used to specify the base address
  * of the requested region.
  *
- * Return: Base address on success, 0 on error.
+ * Return: 0 on success -1 on error
  */
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
 
 /**
  * lmb_is_reserved_flags() - Test if address is in reserved region with flag
@@ -175,7 +175,7 @@ void lmb_pop(struct lmb *store);
 
 static inline int lmb_read_check(phys_addr_t addr, phys_size_t len)
 {
-	return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1;
+	return lmb_alloc_addr(addr, len, LMB_NONE);
 }
 
 /**
diff --git a/include/mapmem.h b/include/mapmem.h
index f496c96d16c..8ec03d59f0b 100644
--- a/include/mapmem.h
+++ b/include/mapmem.h
@@ -33,7 +33,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
  * nomap_sysmem() - pass through an address unchanged
  *
  * This is used to indicate an address which should NOT be mapped, e.g. in
- * SMBIOS tables. Using this function instead of a case shows that the sandbox
+ * SMBIOS tables. Using this function instead of a cast shows that the sandbox
  * conversion has been done
  */
 static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len)
diff --git a/include/membuff.h b/include/membuf.h
index 4eba626ce1c..46764690f53 100644
--- a/include/membuff.h
+++ b/include/membuf.h
@@ -6,11 +6,13 @@
  * Copyright (c) 1992 Simon Glass
  */
 
-#ifndef _MEMBUFF_H
-#define _MEMBUFF_H
+#ifndef _membuf_H
+#define _membuf_H
+
+#include <stdbool.h>
 
 /**
- * @struct membuff: holds the state of a membuff - it is used for input and
+ * @struct membuf: holds the state of a membuff - it is used for input and
  * output buffers. The buffer extends from @start to (@start + @size - 1).
  * Data in the buffer extends from @tail to @head: it is written in at
  * @head and read out from @tail. The membuff is empty when @head == @tail
@@ -23,13 +25,13 @@
  *
  * .............xxxxxxxxxxxxxxxx.........................
  *		^		^
- *		tail		head
+ * ^start	tail		head                     ^end
  *
  * xxxxxxxxxxxxx................xxxxxxxxxxxxxxxxxxxxxxxxx
  *		^		^
  *		head		tail
  */
-struct membuff {
+struct membuf {
 	char *start;		/** the start of the buffer */
 	char *end;		/** the end of the buffer (start + length) */
 	char *head;		/** current buffer head */
@@ -37,16 +39,16 @@ struct membuff {
 };
 
 /**
- * membuff_purge() - reset a membuff to the empty state
+ * membuf_purge() - reset a membuff to the empty state
  *
  * Initialise head and tail pointers so that the membuff becomes empty.
  *
  * @mb: membuff to purge
  */
-void membuff_purge(struct membuff *mb);
+void membuf_purge(struct membuf *mb);
 
 /**
- * membuff_putraw() - find out where bytes can be written
+ * membuf_putraw() - find out where bytes can be written
  *
  * Work out where in the membuff some data could be written. Return a pointer
  * to the address and the number of bytes which can be written there. If
@@ -64,10 +66,10 @@ void membuff_purge(struct membuff *mb);
  * @data: the address data can be written to
  * Return: number of bytes which can be written
  */
-int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
+int membuf_putraw(struct membuf *mb, int maxlen, bool update, char **data);
 
 /**
- * membuff_getraw() - find and return a pointer to available bytes
+ * membuf_getraw() - find and return a pointer to available bytes
  *
  * Returns a pointer to any valid input data in the given membuff and
  * optionally marks it as read. Note that not all input data may not be
@@ -82,37 +84,37 @@ int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
  * @data: returns address of data in input membuff
  * Return: the number of bytes available at *@data
  */
-int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data);
+int membuf_getraw(struct membuf *mb, int maxlen, bool update, char **data);
 
 /**
- * membuff_putbyte() - Writes a byte to a membuff
+ * membuf_putbyte() - Writes a byte to a membuff
  *
  * @mb: membuff to adjust
  * @ch: byte to write
  * Return: true on success, false if membuff is full
  */
-bool membuff_putbyte(struct membuff *mb, int ch);
+bool membuf_putbyte(struct membuf *mb, int ch);
 
 /**
  * @mb: membuff to adjust
- * membuff_getbyte() - Read a byte from the membuff
+ * membuf_getbyte() - Read a byte from the membuff
  * Return: the byte read, or -1 if the membuff is empty
  */
-int membuff_getbyte(struct membuff *mb);
+int membuf_getbyte(struct membuf *mb);
 
 /**
- * membuff_peekbyte() - check the next available byte
+ * membuf_peekbyte() - check the next available byte
  *
- * Return the next byte which membuff_getbyte() would return, without
+ * Return the next byte which membuf_getbyte() would return, without
  * removing it from the membuff.
  *
  * @mb: membuff to adjust
  * Return: the byte peeked, or -1 if the membuff is empty
  */
-int membuff_peekbyte(struct membuff *mb);
+int membuf_peekbyte(struct membuf *mb);
 
 /**
- * membuff_get() - get data from a membuff
+ * membuf_get() - get data from a membuff
  *
  * Copies any available data (up to @maxlen bytes) to @buff and removes it
  * from the membuff.
@@ -122,10 +124,10 @@ int membuff_peekbyte(struct membuff *mb);
  * @maxlen: maximum number of bytes to read
  * Return: the number of bytes read
  */
-int membuff_get(struct membuff *mb, char *buff, int maxlen);
+int membuf_get(struct membuf *mb, char *buff, int maxlen);
 
 /**
- * membuff_put() - write data to a membuff
+ * membuf_put() - write data to a membuff
  *
  * Writes some data to a membuff. Returns the number of bytes added. If this
  * is less than @lnehgt, then the membuff got full
@@ -135,36 +137,36 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen);
  * @length: number of bytes to write from 'data'
  * Return: the number of bytes added
  */
-int membuff_put(struct membuff *mb, const char *buff, int length);
+int membuf_put(struct membuf *mb, const char *buff, int length);
 
 /**
- * membuff_isempty() - check if a membuff is empty
+ * membuf_isempty() - check if a membuff is empty
  *
  * @mb: membuff to check
  * Return: true if empty, else false
  */
-bool membuff_isempty(struct membuff *mb);
+bool membuf_isempty(struct membuf *mb);
 
 /**
- * membuff_avail() - check available data in a membuff
+ * membuf_avail() - check available data in a membuff
  *
  * @mb: membuff to check
  * Return: number of bytes of data available
  */
-int membuff_avail(struct membuff *mb);
+int membuf_avail(struct membuf *mb);
 
 /**
- * membuff_size() - get the size of a membuff
+ * membuf_size() - get the size of a membuff
  *
  * Note that a membuff can only old data up to one byte less than its size.
  *
  * @mb: membuff to check
  * Return: total size
  */
-int membuff_size(struct membuff *mb);
+int membuf_size(struct membuf *mb);
 
 /**
- * membuff_makecontig() - adjust all membuff data to be contiguous
+ * membuf_makecontig() - adjust all membuff data to be contiguous
  *
  * This places all data in a membuff into a single contiguous lump, if
  * possible
@@ -172,18 +174,18 @@ int membuff_size(struct membuff *mb);
  * @mb: membuff to adjust
  * Return: true on success
  */
-bool membuff_makecontig(struct membuff *mb);
+bool membuf_makecontig(struct membuf *mb);
 
 /**
- * membuff_free() - find the number of bytes that can be written to a membuff
+ * membuf_free() - find the number of bytes that can be written to a membuff
  *
  * @mb: membuff to check
  * Return: returns the number of bytes free in a membuff
  */
-int membuff_free(struct membuff *mb);
+int membuf_free(struct membuf *mb);
 
 /**
- * membuff_readline() - read a line of text from a membuff
+ * membuf_readline() - read a line of text from a membuff
  *
  * Reads a line of text of up to 'maxlen' characters from a membuff and puts
  * it in @str. Any character less than @minch is assumed to be the end of
@@ -192,14 +194,16 @@ int membuff_free(struct membuff *mb);
  * @mb: membuff to adjust
  * @str: Place to put the line
  * @maxlen: Maximum line length (excluding terminator)
+ * @minch: Minimum ASCII character to permit as part of the line (e.g. ' ')
  * @must_fit: If true then str is empty if line doesn't fit
  * Return: number of bytes read (including terminator) if a line has been
  *	   read, 0 if nothing was there or line didn't fit when must_fit is set
  */
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit);
+int membuf_readline(struct membuf *mb, char *str, int maxlen, int minch,
+		    bool must_fit);
 
 /**
- * membuff_extend_by() - expand a membuff
+ * membuf_extend_by() - expand a membuff
  *
  * Extends a membuff by the given number of bytes
  *
@@ -209,38 +213,38 @@ int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool
  * Return: 0 if the expand succeeded, -ENOMEM if not enough memory, -E2BIG
  * if the the size would exceed @max
  */
-int membuff_extend_by(struct membuff *mb, int by, int max);
+int membuf_extend_by(struct membuf *mb, int by, int max);
 
 /**
- * membuff_init() - set up a new membuff using an existing membuff
+ * membuf_init() - set up a new membuff using an existing membuff
  *
  * @mb: membuff to set up
  * @buff: Address of buffer
  * @size: Size of buffer
  */
-void membuff_init(struct membuff *mb, char *buff, int size);
+void membuf_init(struct membuf *mb, char *buff, int size);
 
 /**
- * membuff_uninit() - clear a membuff so it can no longer be used
+ * membuf_uninit() - clear a membuff so it can no longer be used
  *
  * @mb: membuff to uninit
  */
-void membuff_uninit(struct membuff *mb);
+void membuf_uninit(struct membuf *mb);
 
 /**
- * membuff_new() - create a new membuff
+ * membuf_new() - create a new membuff
  *
  * @mb: membuff to init
  * @size: size of membuff to create
  * Return: 0 if OK, -ENOMEM if out of memory
  */
-int membuff_new(struct membuff *mb, int size);
+int membuf_new(struct membuf *mb, int size);
 
 /**
- * membuff_dispose() - free memory allocated to a membuff and uninit it
+ * membuf_dispose() - free memory allocated to a membuff and uninit it
  *
  * @mb: membuff to dispose
  */
-void membuff_dispose(struct membuff *mb);
+void membuf_dispose(struct membuf *mb);
 
 #endif
diff --git a/include/net-common.h b/include/net-common.h
index 6a39091a5d4..30860f5975a 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -475,36 +475,6 @@ int net_init(void);
 enum proto_t;
 int net_loop(enum proto_t protocol);
 
-/* internal function: do not use! */
-int netboot_run_(enum proto_t proto, ulong addr, const char *fname, ulong size,
-		 bool fname_explicit, bool ipv6);
-
-/**
- * netboot_run() - Run a network operation
- *
- * The following proto values are NOT supported:
- *	PING, since net_ping_ip cannot be set
- *	NETCONS, since its parameters cannot bet set
- *	RS, since first_call cannot be set, along with perhaps other things
- *	UDP, since udp_ops cannot be set
- *	DNS, since net_dns_resolve and net_dns_env_var cannot be set
- *	WGET, since DNS must be done first and that is not supported
- *	DHCP6, since the required parameters cannot be passed in
- *
- * To support one of these, either add the required arguments or perhaps a
- * separate function and a struct to hold the information.
- *
- * @proto: Operation to run: TFTPGET, FASTBOOT_UDP, FASTBOOT_TCP, BOOTP,
- *	TFTPPUT, RARP, NFS, DHCP
- * @addr: Load/save address
- * @fname: Filename
- * @size: Save size (not used for TFTPGET)
- * @ipv6: true to use IPv6, false to use IPv4
- * Return 0 on success, else -ve error code
- */
-int netboot_run(enum proto_t proto, ulong addr, const char *fname, ulong size,
-		bool ipv6);
-
 /**
  * dhcp_run() - Run DHCP on the current ethernet device
  *
@@ -549,7 +519,6 @@ int wget_do_request(ulong dst_addr, char *uri);
  * Return:	true if uri is valid, false if uri is invalid
  */
 bool wget_validate_uri(char *uri);
-//int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
 
 /**
  * enum wget_http_method - http method
diff --git a/include/phy.h b/include/phy.h
index 36785031eeb..36354aaf774 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -334,6 +334,30 @@ int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
 /**
+ * phy_set_bits - Convenience function for setting bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: bits to set
+ */
+static inline int phy_set_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+	return phy_modify(phydev, devad, regnum, 0, val);
+}
+
+/**
+ * phy_clear_bits - Convenience function for clearing bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to write to
+ * @regnum: register number to write
+ * @val: bits to clear
+ */
+static inline int phy_clear_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+	return phy_modify(phydev, devad, regnum, val, 0);
+}
+
+/**
  * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
  * @__name: name of the driver
  */
diff --git a/include/renesas/rzg2l-usbphy.h b/include/renesas/rzg2l-usbphy.h
new file mode 100644
index 00000000000..1a46b585f17
--- /dev/null
+++ b/include/renesas/rzg2l-usbphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G2L USB PHY common definitions
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#ifndef RENESAS_RZG2L_USBPHY_H
+#define RENESAS_RZG2L_USBPHY_H
+
+#include <fdtdec.h>
+
+struct rzg2l_usbphy_ctrl_priv {
+	fdt_addr_t regs;
+};
+
+#endif /* RENESAS_RZG2L_USBPHY_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index a21b3378fa7..17954461114 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -445,7 +445,9 @@ config CIRCBUF
 source "lib/dhry/Kconfig"
 
 menu "Alternative crypto libraries"
-source lib/mbedtls/Kconfig
+
+source "lib/mbedtls/Kconfig"
+
 endmenu
 
 menu "Security support"
diff --git a/lib/Makefile b/lib/Makefile
index a30ce1595d5..41de2671cc6 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -125,7 +125,7 @@ obj-y += hang.o
 obj-y += linux_compat.o
 obj-y += linux_string.o
 obj-$(CONFIG_$(PHASE_)LMB) += lmb.o
-obj-y += membuff.o
+obj-y += membuf.o
 obj-$(CONFIG_REGEX) += slre.o
 obj-y += string.o
 obj-y += tables_csum.o
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index c0ed24984af..12215f5d90a 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -66,6 +66,7 @@ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
 
 	dmar->host_address_width = info.address_width - 1;
 	dmar->flags = flags;
+	header->checksum = table_compute_checksum(dmar, header->length);
 
 	return 0;
 }
@@ -255,8 +256,8 @@ int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
 	header->creator_revision = 1;
 	fadt->minor_revision = 2;
 
-	fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
-	fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
+	fadt->x_firmware_ctrl = nomap_to_sysmem(ctx->facs);
+	fadt->x_dsdt = nomap_to_sysmem(ctx->dsdt);
 
 	if (fadt->x_firmware_ctrl < 0x100000000ULL)
 		fadt->firmware_ctrl = fadt->x_firmware_ctrl;
@@ -615,6 +616,7 @@ int acpi_iort_add_named_component(struct acpi_ctx *ctx,
 	node->length += strlen(device_name) + 1;
 
 	comp = (struct acpi_iort_named_component *)node->node_data;
+	memset(comp, '\0', sizeof(struct acpi_iort_named_component));
 
 	comp->node_flags = node_flags;
 	comp->memory_properties = memory_properties;
@@ -635,6 +637,7 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 		     const struct acpi_iort_id_mapping *map)
 {
 	struct acpi_iort_id_mapping *mapping;
+	struct acpi_iort_node *output_node;
 	struct acpi_iort_node *node;
 	struct acpi_iort_rc *rc;
 	int offset;
@@ -646,12 +649,18 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 
 	node->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
 	node->revision = 2;
+	node->mapping_count = num_mappings;
+	if (num_mappings)
+		node->mapping_offset = sizeof(struct acpi_iort_node) +
+				       sizeof(struct acpi_iort_rc);
 
 	node->length = sizeof(struct acpi_iort_node);
 	node->length += sizeof(struct acpi_iort_rc);
 	node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
 
 	rc = (struct acpi_iort_rc *)node->node_data;
+	memset(rc, '\0', sizeof(struct acpi_iort_rc));
+
 	rc->mem_access_properties = mem_access_properties;
 	rc->ats_attributes = ats_attributes;
 	rc->pci_segment_number = pci_segment_number;
@@ -659,6 +668,13 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 
 	mapping = (struct acpi_iort_id_mapping *)(rc + 1);
 	for (int i = 0; i < num_mappings; i++) {
+		/* Validate input */
+		output_node = (struct acpi_iort_node *)ctx->tab_start + map[i].output_reference;
+		/* ID mappings can use SMMUs or ITS groups as output references */
+		assert(output_node && ((output_node->type == ACPI_IORT_NODE_ITS_GROUP) ||
+				       (output_node->type == ACPI_IORT_NODE_SMMU) ||
+				       (output_node->type == ACPI_IORT_NODE_SMMU_V3)));
+
 		memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
 		mapping++;
 	}
@@ -683,6 +699,7 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 			  const struct acpi_iort_id_mapping *map)
 {
 	struct acpi_iort_node *node;
+	struct acpi_iort_node *output_node;
 	struct acpi_iort_smmu_v3 *smmu;
 	struct acpi_iort_id_mapping *mapping;
 	int offset;
@@ -695,13 +712,16 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 	node->type = ACPI_IORT_NODE_SMMU_V3;
 	node->revision = 5;
 	node->mapping_count = num_mappings;
-	node->mapping_offset = sizeof(struct acpi_iort_node) + sizeof(struct acpi_iort_smmu_v3);
+	if (num_mappings)
+		node->mapping_offset = sizeof(struct acpi_iort_node) +
+				       sizeof(struct acpi_iort_smmu_v3);
 
 	node->length = sizeof(struct acpi_iort_node);
 	node->length += sizeof(struct acpi_iort_smmu_v3);
 	node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
 
 	smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+	memset(smmu, '\0', sizeof(struct acpi_iort_smmu_v3));
 
 	smmu->base_address = base_address;
 	smmu->flags = flags;
@@ -716,6 +736,14 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 
 	mapping = (struct acpi_iort_id_mapping *)(smmu + 1);
 	for (int i = 0; i < num_mappings; i++) {
+		/* Validate input */
+		output_node = (struct acpi_iort_node *)ctx->tab_start + map[i].output_reference;
+		/*
+		 * ID mappings of an SMMUv3 node can only have ITS group nodes
+		 * as output references.
+		 */
+		assert(output_node && output_node->type == ACPI_IORT_NODE_ITS_GROUP);
+
 		memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
 		mapping++;
 	}
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c6124c590d9..f9534ef85ed 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -18,6 +18,8 @@
 #include <efi_loader.h>
 #include <efi_variable.h>
 #include <asm/unaligned.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
 
 static const struct efi_boot_services *bs;
 static const struct efi_runtime_services *rs;
@@ -348,6 +350,7 @@ static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
 					 struct efi_device_path **dp,
 					 struct udevice **blk)
 {
+	u64 pages;
 	efi_status_t ret;
 	struct udevice *ramdisk_blk;
 
@@ -362,13 +365,18 @@ static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
 	}
 
 	/*
-	 * TODO: expose the ramdisk to OS.
-	 * Need to pass the ramdisk information by the architecture-specific
-	 * methods such as 'pmem' device-tree node.
+	 * Linux supports 'pmem' which allows OS installers to find, reclaim
+	 * the mounted images and continue the installation since the contents
+	 * of the pmem region are treated as local media.
+	 *
+	 * The memory regions used for it needs to be carved out of the EFI
+	 * memory map.
 	 */
-	ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE);
+	pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+	ret = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+				    false, true);
 	if (ret != EFI_SUCCESS) {
-		log_err("Memory reservation failed\n");
+		log_err("Failed to reserve memory\n");
 		goto err;
 	}
 
@@ -490,6 +498,13 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp,
 		ret = EFI_INVALID_PARAMETER;
 		goto err;
 	}
+	/*
+	 * Depending on the kernel configuration, pmem memory areas must be
+	 * page aligned or 2MiB aligned. PowerPC is an exception here and
+	 * requires 16MiB alignment, but since we don't have EFI support for
+	 * it, limit the alignment to 2MiB.
+	 */
+	image_size = ALIGN(image_size, SZ_2M);
 
 	/*
 	 * If the file extension is ".iso" or ".img", mount it and try to load
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index c8d9a6037f7..f220daa048f 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -15,6 +15,7 @@
 #include <irq_func.h>
 #include <log.h>
 #include <malloc.h>
+#include <net-common.h>
 #include <pe.h>
 #include <time.h>
 #include <u-boot/crc.h>
@@ -2231,6 +2232,8 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
 
 	if (!efi_st_keep_devices) {
 		bootm_disable_interrupts();
+		if (IS_ENABLED(CONFIG_DM_ETH))
+			eth_halt();
 		board_quiesce_devices();
 		dm_remove_devices_active();
 	}
diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c
index f6889cb7399..452ec1b2e8b 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -181,10 +181,13 @@ static char *dp_msging(char *s, struct efi_device_path *dp)
 		switch (idp->protocol) {
 		case IPPROTO_TCP:
 			s += sprintf(s, "TCP,");
+			break;
 		case IPPROTO_UDP:
 			s += sprintf(s, "UDP,");
+			break;
 		default:
 			s += sprintf(s, "0x%x,", idp->protocol);
+			break;
 		}
 		s += sprintf(s, idp->static_ip_address ? "Static" : "DHCP");
 		s += sprintf(s, ",%pI4", &idp->local_ip_address);
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 04b2efc4a3b..8c32059edda 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -5,6 +5,7 @@
 
 #define LOG_CATEGORY LOGC_EFI
 
+#include <blkmap.h>
 #include <bootm.h>
 #include <env.h>
 #include <image.h>
@@ -454,22 +455,29 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle,
  */
 static efi_status_t copy_fdt(void **fdtp)
 {
-	unsigned long fdt_ram_start = -1L, fdt_pages;
 	efi_status_t ret = 0;
 	void *fdt, *new_fdt;
-	u64 new_fdt_addr;
-	uint fdt_size;
-	int i;
+	static u64 new_fdt_addr;
+	static efi_uintn_t fdt_pages;
+	ulong fdt_size;
 
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		u64 ram_start = gd->bd->bi_dram[i].start;
-		u64 ram_size = gd->bd->bi_dram[i].size;
+	/*
+	 * Remove the configuration table that might already be
+	 * installed, ignoring EFI_NOT_FOUND if no device-tree
+	 * is installed
+	 */
+	efi_install_configuration_table(&efi_guid_fdt, NULL);
 
-		if (!ram_size)
-			continue;
+	if (new_fdt_addr) {
+		log_debug("%s: Found allocated memory at %#llx, with %#zx pages\n",
+			  __func__, new_fdt_addr, fdt_pages);
 
-		if (ram_start < fdt_ram_start)
-			fdt_ram_start = ram_start;
+		ret = efi_free_pages(new_fdt_addr, fdt_pages);
+		if (ret != EFI_SUCCESS)
+			log_err("Unable to free up existing FDT memory region\n");
+
+		new_fdt_addr = 0;
+		fdt_pages = 0;
 	}
 
 	/*
@@ -485,15 +493,18 @@ static efi_status_t copy_fdt(void **fdtp)
 				 &new_fdt_addr);
 	if (ret != EFI_SUCCESS) {
 		log_err("Failed to reserve space for FDT\n");
-		goto done;
+		return ret;
 	}
+	log_debug("%s: Allocated memory at %#llx, with %#zx pages\n",
+		  __func__, new_fdt_addr, fdt_pages);
+
 	new_fdt = (void *)(uintptr_t)new_fdt_addr;
 	memcpy(new_fdt, fdt, fdt_totalsize(fdt));
 	fdt_set_totalsize(new_fdt, fdt_size);
 
-	*fdtp = (void *)(uintptr_t)new_fdt_addr;
-done:
-	return ret;
+	*fdtp = new_fdt;
+
+	return EFI_SUCCESS;
 }
 
 /**
@@ -546,9 +557,6 @@ efi_status_t efi_install_fdt(void *fdt)
 		const char *fdt_opt;
 		uintptr_t fdt_addr;
 
-		/* Look for device tree that is already installed */
-		if (efi_get_configuration_table(&efi_guid_fdt))
-			return EFI_SUCCESS;
 		/* Check if there is a hardware device tree */
 		fdt_opt = env_get("fdt_addr");
 		/* Use our own device tree as fallback */
@@ -680,3 +688,44 @@ out:
 
 	return ret;
 }
+
+/**
+ * pmem_node_efi_memmap_setup() - Add pmem node and tweak EFI memmap
+ * @fdt: The devicetree to which pmem node is added
+ * @addr: start address of the pmem node
+ * @size: size of the memory of the pmem node
+ *
+ * The function adds the pmem node to the device-tree along with removing
+ * the corresponding region from the EFI memory map. Used primarily to
+ * pass the information of a RAM based ISO image to the OS.
+ *
+ * Return: 0 on success, -ve value on error
+ */
+static int pmem_node_efi_memmap_setup(void *fdt, u64 addr, u64 size)
+{
+	int ret;
+	u64 pages;
+	efi_status_t status;
+
+	ret = fdt_fixup_pmem_region(fdt, addr, size);
+	if (ret) {
+		log_err("Failed to setup pmem node for addr %#llx, size %#llx, err %d\n",
+			addr, size, ret);
+		return ret;
+	}
+
+	/* Remove the pmem region from the EFI memory map */
+	pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+	status = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+				       false, true);
+	if (status != EFI_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int fdt_efi_pmem_setup(void *fdt)
+{
+	return blkmap_get_preserved_pmem_slices(pmem_node_efi_memmap_setup,
+						fdt);
+}
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 6d00b186250..0abb1f6159a 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -258,7 +258,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map,
 }
 
 /**
- * efi_add_memory_map_pg() - add pages to the memory map
+ * efi_update_memory_map() - update the memory map by adding/removing pages
  *
  * @start:			start address, must be a multiple of
  *				EFI_PAGE_SIZE
@@ -266,12 +266,11 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map,
  * @memory_type:		type of memory added
  * @overlap_conventional:	region may only overlap free(conventional)
  *				memory
+ * @remove:			remove memory map
  * Return:			status code
  */
-static
-efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
-				   int memory_type,
-				   bool overlap_conventional)
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+				   bool overlap_conventional, bool remove)
 {
 	struct efi_mem_list *lmem;
 	struct efi_mem_list *newlist;
@@ -279,9 +278,9 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 	uint64_t carved_pages = 0;
 	struct efi_event *evt;
 
-	EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
+	EFI_PRINT("%s: 0x%llx 0x%llx %d %s %s\n", __func__,
 		  start, pages, memory_type, overlap_conventional ?
-		  "yes" : "no");
+		  "yes" : "no", remove ? "remove" : "add");
 
 	if (memory_type >= EFI_MAX_MEMORY_TYPE)
 		return EFI_INVALID_PARAMETER;
@@ -364,7 +363,10 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 	}
 
 	/* Add our new map */
-        list_add_tail(&newlist->link, &efi_mem);
+	if (!remove)
+		list_add_tail(&newlist->link, &efi_mem);
+	else
+		free(newlist);
 
 	/* And make sure memory is listed in descending order */
 	efi_mem_sort();
@@ -401,7 +403,7 @@ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type)
 	pages = efi_size_in_pages(size + (start & EFI_PAGE_MASK));
 	start &= ~EFI_PAGE_MASK;
 
-	return efi_add_memory_map_pg(start, pages, memory_type, false);
+	return efi_update_memory_map(start, pages, memory_type, false, false);
 }
 
 /**
@@ -491,8 +493,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 			return EFI_NOT_FOUND;
 
 		addr = map_to_sysmem((void *)(uintptr_t)*memory);
-		addr = (u64)lmb_alloc_addr(addr, len, flags);
-		if (!addr)
+		if (lmb_alloc_addr(addr, len, flags))
 			return EFI_NOT_FOUND;
 		break;
 	default:
@@ -502,7 +503,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 
 	efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0);
 	/* Reserve that map in our memory maps */
-	ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true);
+	ret = efi_update_memory_map(efi_addr, pages, memory_type, true, false);
 	if (ret != EFI_SUCCESS) {
 		/* Map would overlap, bail out */
 		lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags);
@@ -823,8 +824,8 @@ static void add_u_boot_and_runtime(void)
 		       uboot_stack_size) & ~EFI_PAGE_MASK;
 	uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) -
 		       uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
-	efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
-			      false);
+	efi_update_memory_map(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
+			      false, false);
 #if defined(__aarch64__)
 	/*
 	 * Runtime Services must be 64KiB aligned according to the
@@ -842,8 +843,8 @@ static void add_u_boot_and_runtime(void)
 	runtime_end = (uintptr_t)__efi_runtime_stop;
 	runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
 	runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
-	efi_add_memory_map_pg(runtime_start, runtime_pages,
-			      EFI_RUNTIME_SERVICES_CODE, false);
+	efi_update_memory_map(runtime_start, runtime_pages,
+			      EFI_RUNTIME_SERVICES_CODE, false, false);
 }
 
 int efi_memory_init(void)
@@ -878,11 +879,11 @@ int efi_map_update_notify(phys_addr_t addr, phys_size_t size,
 	pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
 	efi_addr &= ~EFI_PAGE_MASK;
 
-	status = efi_add_memory_map_pg(efi_addr, pages,
+	status = efi_update_memory_map(efi_addr, pages,
 				       op == LMB_MAP_OP_RESERVE ?
 				       EFI_BOOT_SERVICES_DATA :
 				       EFI_CONVENTIONAL_MEMORY,
-				       false);
+				       false, false);
 	if (status != EFI_SUCCESS) {
 		log_err("LMB Map notify failure %lu\n",
 			status & ~EFI_ERROR_MASK);
diff --git a/lib/efi_loader/elf_efi.ldsi b/lib/efi_loader/elf_efi.ldsi
index 190a88fb69e..4fa5ca43872 100644
--- a/lib/efi_loader/elf_efi.ldsi
+++ b/lib/efi_loader/elf_efi.ldsi
@@ -21,10 +21,10 @@ SECTIONS
 		*(.gnu.linkonce.t.*)
 		*(.srodata)
 		*(.rodata*)
-		. = ALIGN(16);
-		*(.dynamic);
-		. = ALIGN(512);
 	}
+	. = ALIGN(16);
+	.dynamic : { *(.dynamic) }
+	. = ALIGN(512);
 	.rela.dyn : { *(.rela.dyn) }
 	.rela.plt : { *(.rela.plt) }
 	.rela.got : { *(.rela.got) }
diff --git a/lib/lmb.c b/lib/lmb.c
index 981ea1b2ca0..bb6f232f6bc 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -742,7 +742,7 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
 	return _lmb_alloc_base(size, align, max_addr, flags);
 }
 
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
 {
 	long rgn;
 	struct lmb_region *lmb_memory = lmb.available_mem.data;
@@ -759,11 +759,11 @@ phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
 				      base + size - 1, 1)) {
 			/* ok, reserve the memory */
 			if (!lmb_reserve(base, size, flags))
-				return base;
+				return 0;
 		}
 	}
 
-	return 0;
+	return -1;
 }
 
 /* Return number of bytes from a given address that are free */
diff --git a/lib/mbedtls/pkcs7_parser.c b/lib/mbedtls/pkcs7_parser.c
index ecfcc46edfa..bf8ee17b5b8 100644
--- a/lib/mbedtls/pkcs7_parser.c
+++ b/lib/mbedtls/pkcs7_parser.c
@@ -189,10 +189,6 @@ static int authattrs_parse(struct pkcs7_message *msg, void *aa, size_t aa_len,
 						len)) {
 			if (__test_and_set_bit(sinfo_has_smime_caps, &sinfo->aa_set))
 				return -EINVAL;
-
-			if (msg->data_type != OID_msIndirectData &&
-			    msg->data_type != OID_data)
-				return -EINVAL;
 		} else if (!MBEDTLS_OID_CMP_RAW(MBEDTLS_OID_MICROSOFT_SPOPUSINFO, inner_p,
 						len)) {
 			if (__test_and_set_bit(sinfo_has_ms_opus_info, &sinfo->aa_set))
diff --git a/lib/membuff.c b/lib/membuf.c
index b242a38ff1c..f38ff36cb0b 100644
--- a/lib/membuff.c
+++ b/lib/membuf.c
@@ -9,17 +9,17 @@
 #include <errno.h>
 #include <log.h>
 #include <malloc.h>
-#include "membuff.h"
+#include "membuf.h"
 
-void membuff_purge(struct membuff *mb)
+void membuf_purge(struct membuf *mb)
 {
 	/* set mb->head and mb->tail so the buffers look empty */
 	mb->head = mb->start;
 	mb->tail = mb->start;
 }
 
-static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update,
-			      char ***data, int *offsetp)
+static int membuf_putrawflex(struct membuf *mb, int maxlen, bool update,
+			     char ***data, int *offsetp)
 {
 	int len;
 
@@ -72,30 +72,30 @@ static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update,
 	return len;
 }
 
-int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data)
+int membuf_putraw(struct membuf *mb, int maxlen, bool update, char **data)
 {
 	char **datap;
 	int offset;
 	int size;
 
-	size = membuff_putrawflex(mb, maxlen, update, &datap, &offset);
+	size = membuf_putrawflex(mb, maxlen, update, &datap, &offset);
 	*data = *datap + offset;
 
 	return size;
 }
 
-bool membuff_putbyte(struct membuff *mb, int ch)
+bool membuf_putbyte(struct membuf *mb, int ch)
 {
 	char *data;
 
-	if (membuff_putraw(mb, 1, true, &data) != 1)
+	if (membuf_putraw(mb, 1, true, &data) != 1)
 		return false;
 	*data = ch;
 
 	return true;
 }
 
-int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data)
+int membuf_getraw(struct membuf *mb, int maxlen, bool update, char **data)
 {
 	int len;
 
@@ -146,21 +146,21 @@ int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data)
 	return len;
 }
 
-int membuff_getbyte(struct membuff *mb)
+int membuf_getbyte(struct membuf *mb)
 {
 	char *data = 0;
 
-	return membuff_getraw(mb, 1, true, &data) != 1 ? -1 : *(uint8_t *)data;
+	return membuf_getraw(mb, 1, true, &data) != 1 ? -1 : *(uint8_t *)data;
 }
 
-int membuff_peekbyte(struct membuff *mb)
+int membuf_peekbyte(struct membuf *mb)
 {
 	char *data = 0;
 
-	return membuff_getraw(mb, 1, false, &data) != 1 ? -1 : *(uint8_t *)data;
+	return membuf_getraw(mb, 1, false, &data) != 1 ? -1 : *(uint8_t *)data;
 }
 
-int membuff_get(struct membuff *mb, char *buff, int maxlen)
+int membuf_get(struct membuf *mb, char *buff, int maxlen)
 {
 	char *data = 0, *buffptr = buff;
 	int len = 1, i;
@@ -171,7 +171,7 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen)
 	 */
 	for (i = 0; len && i < 2; i++) {
 		/* get a pointer to the data available */
-		len = membuff_getraw(mb, maxlen, true, &data);
+		len = membuf_getraw(mb, maxlen, true, &data);
 
 		/* copy it into the buffer */
 		memcpy(buffptr, data, len);
@@ -183,14 +183,14 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen)
 	return buffptr - buff;
 }
 
-int membuff_put(struct membuff *mb, const char *buff, int length)
+int membuf_put(struct membuf *mb, const char *buff, int length)
 {
 	char *data;
 	int towrite, i, written;
 
 	for (i = written = 0; i < 2; i++) {
 		/* ask where some data can be written */
-		towrite = membuff_putraw(mb, length, true, &data);
+		towrite = membuf_putraw(mb, length, true, &data);
 
 		/* and write it, updating the bytes length */
 		memcpy(data, buff, towrite);
@@ -203,14 +203,14 @@ int membuff_put(struct membuff *mb, const char *buff, int length)
 	return written;
 }
 
-bool membuff_isempty(struct membuff *mb)
+bool membuf_isempty(struct membuf *mb)
 {
 	return mb->head == mb->tail;
 }
 
-int membuff_avail(struct membuff *mb)
+int membuf_avail(struct membuf *mb)
 {
-	struct membuff copy;
+	struct membuf copy;
 	int i, avail;
 	char *data = 0;
 
@@ -219,18 +219,18 @@ int membuff_avail(struct membuff *mb)
 
 	/* now read everything out of the copied buffer */
 	for (i = avail = 0; i < 2; i++)
-		avail += membuff_getraw(&copy, -1, true, &data);
+		avail += membuf_getraw(&copy, -1, true, &data);
 
 	/* and return how much we read */
 	return avail;
 }
 
-int membuff_size(struct membuff *mb)
+int membuf_size(struct membuf *mb)
 {
 	return mb->end - mb->start;
 }
 
-bool membuff_makecontig(struct membuff *mb)
+bool membuf_makecontig(struct membuf *mb)
 {
 	int topsize, botsize;
 
@@ -281,13 +281,14 @@ bool membuff_makecontig(struct membuff *mb)
 	return true;
 }
 
-int membuff_free(struct membuff *mb)
+int membuf_free(struct membuf *mb)
 {
 	return mb->end == mb->start ? 0 :
-			(mb->end - mb->start) - 1 - membuff_avail(mb);
+			(mb->end - mb->start) - 1 - membuf_avail(mb);
 }
 
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit)
+int membuf_readline(struct membuf *mb, char *str, int maxlen, int minch,
+		    bool must_fit)
 {
 	int len;  /* number of bytes read (!= string length) */
 	char *s, *end;
@@ -322,7 +323,7 @@ int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool
 	return len;
 }
 
-int membuff_extend_by(struct membuff *mb, int by, int max)
+int membuf_extend_by(struct membuf *mb, int by, int max)
 {
 	int oldhead, oldtail;
 	int size, orig;
@@ -358,32 +359,32 @@ int membuff_extend_by(struct membuff *mb, int by, int max)
 	return 0;
 }
 
-void membuff_init(struct membuff *mb, char *buff, int size)
+void membuf_init(struct membuf *mb, char *buff, int size)
 {
 	mb->start = buff;
 	mb->end = mb->start + size;
-	membuff_purge(mb);
+	membuf_purge(mb);
 }
 
-int membuff_new(struct membuff *mb, int size)
+int membuf_new(struct membuf *mb, int size)
 {
 	mb->start = malloc(size);
 	if (!mb->start)
 		return -ENOMEM;
 
-	membuff_init(mb, mb->start, size);
+	membuf_init(mb, mb->start, size);
 	return 0;
 }
 
-void membuff_uninit(struct membuff *mb)
+void membuf_uninit(struct membuf *mb)
 {
 	mb->end = NULL;
 	mb->start = NULL;
-	membuff_purge(mb);
+	membuf_purge(mb);
 }
 
-void membuff_dispose(struct membuff *mb)
+void membuf_dispose(struct membuf *mb)
 {
-	free(&mb->start);
-	membuff_uninit(mb);
+	free(mb->start);
+	membuf_uninit(mb);
 }
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index c00a7fe97cd..6b7b696dbf0 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -57,7 +57,7 @@ static err_t net_lwip_tx(struct netif *netif, struct pbuf *p)
 	err = eth_get_ops(udev)->send(udev, pp ? pp : p->payload, p->len);
 	free(pp);
 	if (err) {
-		log_err("send error %d\n", err);
+		debug("send error %d\n", err);
 		return ERR_ABRT;
 	}
 
diff --git a/net/lwip/ping.c b/net/lwip/ping.c
index 200a702bbb5..c586a96806d 100644
--- a/net/lwip/ping.c
+++ b/net/lwip/ping.c
@@ -121,7 +121,7 @@ static int ping_loop(struct udevice *udev, const ip_addr_t *addr)
 
 	netif = net_lwip_new_netif(udev);
 	if (!netif)
-		return CMD_RET_FAILURE;
+		return -ENODEV;
 
 	printf("Using %s device\n", udev->name);
 
diff --git a/net/net.c b/net/net.c
index ef97377cdec..1828f1cca36 100644
--- a/net/net.c
+++ b/net/net.c
@@ -775,50 +775,6 @@ done:
 	return ret;
 }
 
-int netboot_run_(enum proto_t proto, ulong addr, const char *fname, ulong size,
-		 bool fname_explicit, bool ipv6)
-{
-	int ret;
-
-	bootstage_mark(BOOTSTAGE_ID_NET_START);
-
-	/*
-	 * For now we use the global variables as that is the only way to
-	 * control the network stack. At some point, perhaps, the state could be
-	 * in a struct
-	 */
-	if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT)
-		image_save_addr = addr;
-	else
-		image_load_addr = addr;
-
-	net_boot_file_name_explicit = fname_explicit;
-	copy_filename(net_boot_file_name, fname, sizeof(net_boot_file_name));
-	if (IS_ENABLED(CONFIG_IPV6))
-		use_ip6 = ipv6;
-	if (IS_ENABLED(CONFIG_CMD_TFTPPUT) && proto == TFTPPUT) {
-		image_save_addr = addr;
-		image_save_size = size;
-	} else {
-		image_load_addr = addr;
-	}
-
-	ret = net_loop(proto);
-	if (ret < 0) {
-		bootstage_error(BOOTSTAGE_ID_NET_NETLOOP_OK);
-		return ret;
-	}
-	bootstage_mark(BOOTSTAGE_ID_NET_NETLOOP_OK);
-
-	return 0;
-}
-
-int netboot_run(enum proto_t proto, ulong addr, const char *fname, ulong size,
-		bool ipv6)
-{
-	return netboot_run_(proto, addr, fname, size, true, ipv6);
-}
-
 /**********************************************************************/
 
 static void start_again_timeout_handler(void)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 18993435eae..275c308154b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -513,8 +513,8 @@ $(obj)/%_efi.S: $(obj)/%.efi
 	$(call cmd,S_efi)
 
 quiet_cmd_efi_objcopy = OBJCOPY $@
-cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \
-		.dynamic -j .dynsym  -j .rel* -j .rela* -j .reloc \
+cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data \
+		-j .dynamic -j .dynstr  -j .dynsym -j .rel* -j .reloc \
 		$(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
 
 $(obj)/%.efi: $(obj)/%_efi.so
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index f9f8891c0c4..414019c5b89 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2692,6 +2692,12 @@ sub u_boot_line {
 		ERROR("PRE_SCHEMA",
 		      "Driver model schema uses 'bootph-...' tags now\n" . $herecurr);
 	}
+
+	# Do not allow CONFIG_xPL_BUILD in device trees
+	if ($realfile =~ /\.dtsi?$/ && $line =~ /^\+.*CONFIG_(X|S|T|V)PL_BUILD.*/) {
+		ERROR("CONFIG_xPL_BUILD",
+		      "Do not use CONFIG_xPL_BUILD in device trees\n" . $herecurr);
+	}
 }
 
 sub exclude_global_initialisers {
diff --git a/scripts/event_dump.py b/scripts/event_dump.py
index 24dfe2bda91..61bb3a8eb92 100755
--- a/scripts/event_dump.py
+++ b/scripts/event_dump.py
@@ -107,7 +107,7 @@ def main(argv):
     Args:
         argv (list of str): List of program arguments, excluding arvg[0]
     """
-    epilog = 'Show a list of even spies in a U-Boot EFL file'
+    epilog = 'Show a list of event spies in a U-Boot ELF file'
     parser = ArgumentParser(epilog=epilog)
     parser.add_argument('elf', type=str, help='ELF file to decode')
     parser.add_argument('-e', '--endian', type=str, default='auto',
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 5f07430714e..d5499918249 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -509,6 +509,7 @@ static int bootdev_test_bootable(struct unit_test_state *uts)
 	iter.part = 0;
 	ut_assertok(uclass_get_device_by_name(UCLASS_BLK, "mmc1.blk", &blk));
 	iter.dev = blk;
+	iter.flags = BOOTFLOWIF_ONLY_BOOTABLE;
 	ut_assertok(device_find_next_child(&iter.dev));
 	uclass_first_device(UCLASS_BOOTMETH, &bflow.method);
 
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index eb7f00af39a..5f9c037ff53 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -297,8 +297,9 @@ static int bootflow_iter(struct unit_test_state *uts)
 
 	/* The first device is mmc2.bootdev which has no media */
 	ut_asserteq(-EPROTONOSUPPORT,
-		    bootflow_scan_first(NULL, NULL, &iter,
-					BOOTFLOWIF_ALL | BOOTFLOWIF_SKIP_GLOBAL, &bflow));
+		    bootflow_scan_first(NULL, NULL, &iter, BOOTFLOWIF_ALL |
+					BOOTFLOWIF_SKIP_GLOBAL |
+					BOOTFLOWIF_ONLY_BOOTABLE, &bflow));
 	ut_asserteq(2, iter.num_methods);
 	ut_asserteq(0, iter.cur_method);
 	ut_asserteq(0, iter.part);
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 39a26bbb492..db012b6d2f1 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -309,6 +309,8 @@ static int dm_test_acpi_write_tables(struct unit_test_state *uts)
 	}
 	ut_asserteq(0, ctx.rsdt->entry[3]);
 	ut_asserteq(0, ctx.xsdt->entry[3]);
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -386,6 +388,8 @@ static int dm_test_acpi_ctx_and_base_tables(struct unit_test_state *uts)
 
 	ut_asserteq(nomap_to_sysmem(rsdt), rsdp->rsdt_address);
 	ut_asserteq(nomap_to_sysmem(xsdt), rsdp->xsdt_address);
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -428,11 +432,59 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts)
 	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0",
 			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
 DM_TEST(dm_test_acpi_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
 
+/* Test 'acpi list -c' command */
+static int dm_test_acpi_cmd_list_chksum(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+	ulong addr;
+	void *buf;
+
+	buf = memalign(16, BUF_SIZE);
+	ut_assertnonnull(buf);
+	addr = map_to_sysmem(buf);
+	ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr));
+
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	run_command("acpi list -c", 0);
+	ut_assert_nextline("Name              Base   Size  Detail");
+	ut_assert_nextline("----  ----------------  -----  ----------------------------");
+	ut_assert_nextline("RSDP  %16lx  %5zx  v02 U-BOOT  OK  OK", addr,
+			   sizeof(struct acpi_rsdp));
+	addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16);
+	ut_assert_nextline("RSDT  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_table_header) +
+			   3 * sizeof(u32), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16);
+	ut_assert_nextline("XSDT  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_table_header) +
+			   3 * sizeof(u64), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	ut_assert_console_end();
+	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_cmd_list_chksum,
+	UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
+
 /* Test 'acpi dump' command */
 static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
 {
@@ -458,6 +510,8 @@ static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
 	ut_assert_nextline("DMAR @ %16lx", addr);
 	ut_assert_nextlines_are_dump(0x30);
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -642,6 +696,8 @@ static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
 	ut_assert_nextlines_are_dump(2);
 	ut_assert_nextline("%s", "");
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -679,6 +735,8 @@ static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
 	ut_asserteq(addr, gd_acpi_start());
 
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -774,6 +832,7 @@ static int dm_test_acpi_find_table(struct unit_test_state *uts)
 
 	/* Restore previous ACPI tables */
 	gd_set_acpi_start(acpi_start);
+	unmap_sysmem(buf);
 	free(buf);
 
 	return 0;
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 23c16bd9866..ee9517f9c29 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1742,3 +1742,118 @@ static int dm_test_acpi_write_tsd_package(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_write_tsd_package, 0);
+
+static int dm_test_acpi_iort_smmu_v3(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	int smmu_offset;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ctx->tab_start = ctx->current;
+	acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+	ptr = acpigen_get_current(ctx);
+
+	smmu_offset = acpi_iort_add_smmu_v3(ctx,
+					    0xaabbccddeeffULL, // Base address
+					    1, // Flags
+					    0xffeeddccaabbULL,  // VATOS address
+					    0,  // SMMUv3 Model
+					    3, // Event
+					    4, // Pri
+					    5, // Gerror
+					    6, // Sync
+					    7,  // Proximity domain
+					    8,  // DevIDMappingIndex
+					    0,
+					    NULL);
+	ut_assert(smmu_offset);
+
+	ut_asserteq(ACPI_IORT_NODE_SMMU_V3, ptr[0]);
+	ut_asserteq(68, get_unaligned((u16 *)(ptr + 1)));
+	ut_asserteq(0, get_unaligned((u16 *)(ptr + 4)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 8)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 12)));
+
+	ut_asserteq_64(0xaabbccddeeffULL, get_unaligned((u64 *)(ptr + 16)));
+	ut_asserteq(1, get_unaligned((u32 *)(ptr + 24)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 28)));
+	ut_asserteq_64(0xffeeddccaabbULL, get_unaligned((u64 *)(ptr + 32)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 40)));
+	ut_asserteq(3, get_unaligned((u32 *)(ptr + 44)));
+	ut_asserteq(4, get_unaligned((u32 *)(ptr + 48)));
+	ut_asserteq(5, get_unaligned((u32 *)(ptr + 52)));
+	ut_asserteq(6, get_unaligned((u32 *)(ptr + 56)));
+	ut_asserteq(7, get_unaligned((u32 *)(ptr + 60)));
+	ut_asserteq(8, get_unaligned((u32 *)(ptr + 64)));
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_iort_smmu_v3, 0);
+
+static int dm_test_acpi_iort_rc(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	int its_group_offset, offset;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ctx->tab_start = ctx->current;
+	acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+	u32 identifiers[] = { 0 };
+
+	its_group_offset = acpi_iort_add_its_group(ctx, ARRAY_SIZE(identifiers),
+						   identifiers);
+
+	ptr = acpigen_get_current(ctx);
+
+	struct acpi_iort_id_mapping map_rc[] = {
+		{0, 0xfff, 0, its_group_offset, 0},
+		{0x1000, 0xffff, 0x1000, its_group_offset, 0}
+	};
+
+	offset = acpi_iort_add_rc(ctx,
+				  0xaabbccddeeffULL, // Mem Access Properties
+				  2, // ATS attributes
+				  3, // PCI segment
+				  4, // Memory address size limit
+				  ARRAY_SIZE(map_rc),
+				  map_rc);
+
+	ut_assert(offset);
+	ut_asserteq(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, ptr[0]);
+	ut_asserteq(36 + ARRAY_SIZE(map_rc) * sizeof(struct acpi_iort_id_mapping),
+		    get_unaligned((u16 *)(ptr + 1)));
+	ut_asserteq(0, get_unaligned((u16 *)(ptr + 4)));
+	ut_asserteq(2, get_unaligned((u32 *)(ptr + 8)));
+	ut_asserteq(36, get_unaligned((u32 *)(ptr + 12)));
+
+	ut_asserteq_64(0xaabbccddeeffULL, get_unaligned((u64 *)(ptr + 16)));
+	ut_asserteq(2, get_unaligned((u32 *)(ptr + 24)));
+	ut_asserteq(3, get_unaligned((u32 *)(ptr + 28)));
+	ut_asserteq(4, ptr[32]);
+	ut_asserteq(0, ptr[33]);
+	ut_asserteq(0, ptr[34]);
+	ut_asserteq(0, ptr[35]);
+
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 36)));
+	ut_asserteq(0xfff, get_unaligned((u32 *)(ptr + 40)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 44)));
+	ut_asserteq(its_group_offset, get_unaligned((u32 *)(ptr + 48)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 52)));
+
+	ut_asserteq(0x1000, get_unaligned((u32 *)(ptr + 56)));
+	ut_asserteq(0xffff, get_unaligned((u32 *)(ptr + 60)));
+	ut_asserteq(0x1000, get_unaligned((u32 *)(ptr + 64)));
+	ut_asserteq(its_group_offset, get_unaligned((u32 *)(ptr + 68)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 72)));
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_iort_rc, 0);
\ No newline at end of file
diff --git a/test/lib/Makefile b/test/lib/Makefile
index 0e4cb8e3dfd..aa89923f786 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -14,6 +14,7 @@ obj-y += hexdump.o
 obj-$(CONFIG_SANDBOX) += kconfig.o
 obj-y += lmb.o
 obj-$(CONFIG_HAVE_SETJMP) += longjmp.o
+obj-$(CONFIG_SANDBOX) += membuf.o
 obj-$(CONFIG_CONSOLE_RECORD) += test_print.o
 obj-$(CONFIG_SSCANF) += sscanf.o
 obj-$(CONFIG_$(PHASE_)STRTO) += str.o
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 24416e83491..3bf558f7f4f 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -566,21 +566,21 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 
 	/* Try to allocate a page twice */
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
-	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
 	ut_asserteq(b, 0);
+	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(b, -1);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
+	ut_asserteq(b, 0);
 	b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
+	ut_asserteq(b, 0);
 	ret = lmb_free(alloc_addr_a, 0x2000);
 	ut_asserteq(ret, 0);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, alloc_addr_a);
-	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
 	ut_asserteq(b, 0);
+	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+	ut_asserteq(b, -1);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, 0);
+	ut_asserteq(b, -1);
 	ret = lmb_free(alloc_addr_a, 0x1000);
 	ut_asserteq(ret, 0);
 
@@ -591,21 +591,21 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	 * region 2. Should fail.
 	 */
 	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(a, alloc_addr_a);
+	ut_asserteq(a, 0);
 
 	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, alloc_addr_a + 0x4000);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, a, 0x1000,
-		   b, 0x1000, 0, 0);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
 
 	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
-	ut_asserteq(c, 0);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, a, 0x1000,
-		   b, 0x1000, 0, 0);
+	ut_asserteq(c, -1);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
 
-	ret = lmb_free(a, 0x1000);
+	ret = lmb_free(alloc_addr_a, 0x1000);
 	ut_asserteq(ret, 0);
-	ret = lmb_free(b, 0x1000);
+	ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
 	ut_asserteq(ret, 0);
 
 	/*
@@ -616,19 +616,19 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	 * single region.
 	 */
 	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(a, alloc_addr_a);
+	ut_asserteq(a, 0);
 
 	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a + 0x4000);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, a, 0x1000,
-		   b, 0x1000, 0, 0);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
 
 	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
-	ut_asserteq(c, alloc_addr_a + 0x1000);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, 0x6000,
+	ut_asserteq(c, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_addr_a, 0x6000,
 		   0, 0, 0, 0);
 
-	ret = lmb_free(a, 0x6000);
+	ret = lmb_free(alloc_addr_a, 0x6000);
 	ut_asserteq(ret, 0);
 
 	/*
@@ -638,21 +638,21 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	 * region 2. Should fail.
 	 */
 	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(a, alloc_addr_a);
+	ut_asserteq(a, 0);
 
 	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, alloc_addr_a + 0x4000);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, a, 0x1000,
-		   b, 0x1000, 0, 0);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
 
 	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NOOVERWRITE);
-	ut_asserteq(c, 0);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, a, 0x1000,
-		   b, 0x1000, 0, 0);
+	ut_asserteq(c, -1);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
 
-	ret = lmb_free(a, 0x1000);
+	ret = lmb_free(alloc_addr_a, 0x1000);
 	ut_asserteq(ret, 0);
-	ret = lmb_free(b, 0x1000);
+	ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
 	ut_asserteq(ret, 0);
 
 	/*  reserve 3 blocks */
@@ -667,22 +667,22 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 
 	/* allocate blocks */
 	a = lmb_alloc_addr(ram, alloc_addr_a - ram, LMB_NONE);
-	ut_asserteq(a, ram);
+	ut_asserteq(a, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000,
 		   alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
 	b = lmb_alloc_addr(alloc_addr_a + 0x10000,
 			   alloc_addr_b - alloc_addr_a - 0x10000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a + 0x10000);
+	ut_asserteq(b, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000,
 		   alloc_addr_c, 0x10000, 0, 0);
 	c = lmb_alloc_addr(alloc_addr_b + 0x10000,
 			   alloc_addr_c - alloc_addr_b - 0x10000, LMB_NONE);
-	ut_asserteq(c, alloc_addr_b + 0x10000);
+	ut_asserteq(c, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 	d = lmb_alloc_addr(alloc_addr_c + 0x10000,
 			   ram_end - alloc_addr_c - 0x10000, LMB_NONE);
-	ut_asserteq(d, alloc_addr_c + 0x10000);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
 		   0, 0, 0, 0);
 
@@ -692,57 +692,58 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
 		   0, 0, 0, 0);
 
-	ret = lmb_free(d, ram_end - alloc_addr_c - 0x10000);
+	/* free thge allocation from d */
+	ret = lmb_free(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000);
 	ut_asserteq(ret, 0);
 
 	/* allocate at 3 points in free range */
 
 	d = lmb_alloc_addr(ram_end - 4, 4, LMB_NONE);
-	ut_asserteq(d, ram_end - 4);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
-		   d, 4, 0, 0);
-	ret = lmb_free(d, 4);
+		   ram_end - 4, 4, 0, 0);
+	ret = lmb_free(ram_end - 4, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
 	d = lmb_alloc_addr(ram_end - 128, 4, LMB_NONE);
-	ut_asserteq(d, ram_end - 128);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
-		   d, 4, 0, 0);
-	ret = lmb_free(d, 4);
+		   ram_end - 128, 4, 0, 0);
+	ret = lmb_free(ram_end - 128, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
 	d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4, LMB_NONE);
-	ut_asserteq(d, alloc_addr_c + 0x10000);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004,
 		   0, 0, 0, 0);
-	ret = lmb_free(d, 4);
+	ret = lmb_free(alloc_addr_c + 0x10000, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
-	/* allocate at the bottom */
-	ret = lmb_free(a, alloc_addr_a - ram);
+	/* allocate at the bottom a was assigned to ram at the top */
+	ret = lmb_free(ram, alloc_addr_a - ram);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000,
 		   0x10010000, 0, 0, 0, 0);
 
 	d = lmb_alloc_addr(ram, 4, LMB_NONE);
-	ut_asserteq(d, ram);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4,
+	ut_asserteq(d, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 4,
 		   ram + 0x8000000, 0x10010000, 0, 0);
 
 	/* check that allocating outside memory fails */
 	if (ram_end != 0) {
 		ret = lmb_alloc_addr(ram_end, 1, LMB_NONE);
-		ut_asserteq(ret, 0);
+		ut_asserteq(ret, -1);
 	}
 	if (ram != 0) {
 		ret = lmb_alloc_addr(ram - 1, 1, LMB_NONE);
-		ut_asserteq(ret, 0);
+		ut_asserteq(ret, -1);
 	}
 
 	lmb_pop(&store);
diff --git a/test/lib/membuf.c b/test/lib/membuf.c
new file mode 100644
index 00000000000..3f268a422d5
--- /dev/null
+++ b/test/lib/membuf.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <membuf.h>
+#include <os.h>
+#include <rand.h>
+#include <string.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define TEST_SIZE	16
+#define TEST_COUNT	10000
+
+static void membuf_zero(struct membuf *mb)
+{
+	memset(mb->start, '\0', mb->end - mb->start);
+}
+
+static int membuf_check(struct unit_test_state *uts, struct membuf *mb,
+			int value)
+{
+	/* head is out of range */
+	ut_assert(!(mb->head < mb->start || mb->head >= mb->end));
+
+	/* tail is out of range */
+	ut_assert(!(mb->tail < mb->start || mb->tail >= mb->end));
+
+	return 0;
+}
+
+/* write from 1 to test_size bytes, and check they come back OK */
+static int lib_test_membuf_one(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2], out[TEST_SIZE * 2];
+	struct membuf mb;
+	int size, ret, test_size, i;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	/* setup in test */
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE;
+
+	for (i = 1; i < TEST_COUNT; i++) {
+		membuf_zero(&mb);
+		size = rand() % test_size;
+
+		// now write patterns and check they come back OK
+		ret = membuf_put(&mb, in, 0);
+		ret = membuf_put(&mb, in, size);
+		ut_asserteq(size, ret);
+
+		ret = membuf_put(&mb, in, 0);
+		ut_assertok(membuf_check(uts, &mb, i));
+
+		ret = membuf_get(&mb, out, 0);
+		ret = membuf_get(&mb, out, size);
+		ut_asserteq(size, ret);
+
+		ret = membuf_get(&mb, out, 0);
+		ut_assertok(membuf_check(uts, &mb, i));
+
+		ut_asserteq_mem(in, out, size);
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_one, 0);
+
+/* write random number of bytes, and check they come back OK */
+static int lib_test_membuf_random(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2];
+	char buf[TEST_SIZE * 2];
+	struct membuf mb;
+	int size, ret, test_size, i;
+	char *inptr, *outptr;
+	int max_avail, min_free;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE;
+
+	inptr = in;
+	outptr = in;
+	min_free = TEST_COUNT;
+	max_avail = 0;
+	membuf_zero(&mb);
+	for (i = 0; i < TEST_COUNT; i++) {
+		size = rand() % test_size;
+
+		if (membuf_free(&mb) < min_free)
+			min_free = membuf_free(&mb);
+
+		ret = membuf_put(&mb, inptr, size);
+		ut_assertok(membuf_check(uts, &mb, i));
+		inptr += ret;
+		if (inptr >= in + TEST_SIZE)
+			inptr -= TEST_SIZE;
+
+		size = rand() % (test_size - 1);
+
+		if (membuf_avail(&mb) > max_avail)
+			max_avail = membuf_avail(&mb);
+
+		ret = membuf_get(&mb, buf, size);
+		ut_assertok(membuf_check(uts, &mb, i));
+		ut_asserteq_mem(buf, outptr, ret);
+
+		outptr += ret;
+		if (outptr >= in + TEST_SIZE)
+			outptr -= TEST_SIZE;
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_random, 0);
+
+/* test membuf_extend() with split segments */
+static int lib_test_membuf_extend(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2];
+	char buf[TEST_SIZE * 2];
+	struct membuf mb;
+	int ret, test_size, i, cur;
+	char *data;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE - 1;
+
+	for (cur = 0; cur <= test_size; cur++) {
+		ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+		membuf_zero(&mb);
+
+		/*
+		 * add some bytes, then remove them - this will force the membuf
+		 * to have data split into two segments when we fill it
+		 */
+		ret = membuf_putraw(&mb, TEST_SIZE / 2, true, &data);
+		membuf_getraw(&mb, ret, true, &data);
+		ut_asserteq(TEST_SIZE / 2, ret);
+
+		/* fill it */
+		ret = membuf_put(&mb, in, cur);
+		ut_assertok(membuf_check(uts, &mb, cur));
+		ut_asserteq(cur, ret);
+
+		/* extend the buffer */
+		ut_assertok(membuf_extend_by(&mb, TEST_SIZE, -1));
+		ut_assertok(membuf_check(uts, &mb, cur));
+
+		/* check our data is still there */
+		ret = membuf_get(&mb, buf, TEST_SIZE * 2);
+		ut_assertok(membuf_check(uts, &mb, cur));
+		ut_asserteq(cur, ret);
+		ut_asserteq_mem(in, buf, cur);
+		membuf_uninit(&mb);
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_extend, 0);
+
+/* test membuf_readline() with generated data */
+static int lib_test_membuf_readline(struct unit_test_state *uts)
+{
+	char *buf;
+	int size, cur, i, ret, readptr, cmpptr;
+	struct membuf mb;
+	char *data;
+	char str[256];
+	char *s;
+
+	ut_assertok(membuf_new(&mb, 1024));
+	membuf_zero(&mb);
+
+	/* Use the README as test data */
+	ut_assertok(os_read_file("README", (void **)&buf, &size));
+
+	cur = 0;
+	readptr = 0;
+	cmpptr = 0;
+	for (i = 0; i < 100000; i++, cur += 1) {
+		/* fill the buffer with up to 'cur' bytes */
+		ret = membuf_putraw(&mb, cur, false, &data);
+
+		if (ret > 0) {
+			int can_read = min(ret, size - readptr);
+
+			memcpy(data, &buf[readptr], can_read);
+			readptr += can_read;
+
+			membuf_putraw(&mb, can_read, true, &data);
+			ut_assertok(membuf_check(uts, &mb, i));
+		}
+
+		/* read a line and compare */
+		ret = membuf_readline(&mb, str, 256, 0, true);
+		ut_assertok(membuf_check(uts, &mb, i));
+		if (ret) {
+			char *ptr;
+
+			s = &buf[cmpptr];
+			ptr = strchr(s, '\n');
+			*ptr = '\0';
+
+			ut_asserteq_str(s, str);
+			cmpptr += strlen(s) + 1;
+			*ptr = '\n';
+		} else {
+			ut_assert(membuf_free(&mb));
+		}
+	}
+	membuf_dispose(&mb);
+	os_free(buf);
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_readline, 0);
diff --git a/test/py/conftest.py b/test/py/conftest.py
index e59897c1f78..5aea85647af 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -334,6 +334,7 @@ def pytest_configure(config):
     ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb'
     ubconfig.connection_ok = True
     ubconfig.timing = config.getoption('timing')
+    ubconfig.role = config.getoption('role')
 
     env_vars = (
         'board_type',
@@ -760,6 +761,26 @@ def setup_singlethread(item):
         if worker_id and worker_id != 'master':
             pytest.skip('must run single-threaded')
 
+def setup_role(item):
+    """Process any 'role' marker for a test.
+
+    Skip this test if the role does not match.
+
+    Args:
+        item (pytest.Item): The pytest test item
+    """
+    required_roles = []
+    for roles in item.iter_markers('role'):
+        role = roles.args[0]
+        if role.startswith('!'):
+            if ubconfig.role == role[1:]:
+                pytest.skip(f'role "{ubconfig.role}" not supported')
+                return
+        else:
+            required_roles.append(role)
+    if required_roles and ubconfig.role not in required_roles:
+        pytest.skip(f'board "{ubconfig.role}" not supported')
+
 def start_test_section(item):
     anchors[item.name] = log.start_section(item.name)
 
@@ -781,6 +802,7 @@ def pytest_runtest_setup(item):
     setup_buildconfigspec(item)
     setup_requiredtool(item)
     setup_singlethread(item)
+    setup_role(item)
 
 def pytest_runtest_protocol(item, nextitem):
     """pytest hook: Called to execute a test.
diff --git a/test/py/console_base.py b/test/py/console_base.py
index 260df773bac..88d444b44b8 100644
--- a/test/py/console_base.py
+++ b/test/py/console_base.py
@@ -370,21 +370,30 @@ class ConsoleBase(object):
             output.append(self.run_command(cmd))
         return output
 
-    def ctrlc(self):
-        """Send a CTRL-C character to U-Boot.
+    def send(self, msg):
+        """Send characters without waiting for echo, etc."""
+        self.run_command(msg, wait_for_prompt=False, wait_for_echo=False,
+                         send_nl=False)
+
+    def ctrl(self, char):
+        """Send a CTRL- character to U-Boot.
 
         This is useful in order to stop execution of long-running synchronous
         commands such as "ums".
 
         Args:
-            None.
-
-        Returns:
-            Nothing.
+            char (str): Character to send, e.g. 'C' to send Ctrl-C
         """
+        self.log.action(f'Sending Ctrl-{char}')
+        self.send(chr(ord(char) - ord('@')))
 
-        self.log.action('Sending Ctrl-C')
-        self.run_command(chr(3), wait_for_echo=False, send_nl=False)
+    def ctrlc(self):
+        """Send a CTRL-C character to U-Boot.
+
+        This is useful in order to stop execution of long-running synchronous
+        commands such as "ums".
+        """
+        self.ctrl('C')
 
     def wait_for(self, text):
         """Wait for a pattern to be emitted by U-Boot.
diff --git a/test/py/pytest.ini b/test/py/pytest.ini
index 26d83f83e00..361be0178ee 100644
--- a/test/py/pytest.ini
+++ b/test/py/pytest.ini
@@ -12,3 +12,4 @@ markers =
     requiredtool: U-Boot: Required host tools for a test.
     slow: U-Boot: Specific test will run slowly.
     singlethread: Cannot run in parallel
+    role: U-Boot: Indicates the lab 'role' which can execute this test
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index acfe17dce9f..804a427b351 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -2,3 +2,4 @@ filelock==3.0.12
 pycryptodomex==3.21.0
 pytest==6.2.5
 pytest-xdist==2.5.0
+FATtools==1.0.42
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index 2faab21509f..b8a22b22806 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -35,7 +35,9 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
     else:
         mkfs_opt = ''
 
-    if re.match('fat', fs_type):
+    if fs_type == 'exfat':
+        fs_lnxtype = 'exfat'
+    elif re.match('fat', fs_type) or fs_type == 'fs_generic':
         fs_lnxtype = 'vfat'
     else:
         fs_lnxtype = fs_type
@@ -43,7 +45,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
     if src_dir:
         if fs_lnxtype == 'ext4':
             mkfs_opt = mkfs_opt + ' -d ' + src_dir
-        elif fs_lnxtype != 'vfat':
+        elif fs_lnxtype != 'vfat' and fs_lnxtype != 'exfat':
             raise ValueError(f'src_dir not implemented for fs {fs_lnxtype}')
 
     count = (size + size_gran - 1) // size_gran
@@ -54,7 +56,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
 
     try:
         check_call(f'rm -f {fs_img}', shell=True)
-        check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}',
+        check_call(f'truncate -s $(( {size_gran} * {count} )) {fs_img}',
                    shell=True)
         check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
         if fs_type == 'ext4':
@@ -64,6 +66,8 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
                 check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True)
         elif fs_lnxtype == 'vfat' and src_dir:
             check_call(f'mcopy -i {fs_img} -vsmpQ {src_dir}/* ::/', shell=True)
+        elif fs_lnxtype == 'exfat' and src_dir:
+            check_call(f'fattools cp {src_dir}/* {fs_img}', shell=True)
         return fs_img
     except CalledProcessError:
         call(f'rm -f {fs_img}', shell=True)
diff --git a/test/py/tests/test_distro.py b/test/py/tests/test_distro.py
new file mode 100644
index 00000000000..bdf4ab657d1
--- /dev/null
+++ b/test/py/tests/test_distro.py
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2025 Canonical Ltd.
+# Written by Simon Glass <simon.glass@canonical.com>
+
+import pytest
+
+# Enable early console so that the test can see if something goes wrong
+CONSOLE = 'earlycon=uart8250,io,0x3f8 console=uart8250,io,0x3f8'
+
+@pytest.mark.boardspec('qemu-x86_64')
+@pytest.mark.role('qemu-x86_64')
+def test_distro(ubman):
+    """Test that of-platdata can be generated and used in sandbox"""
+    with ubman.log.section('boot'):
+        ubman.run_command('boot', wait_for_prompt=False)
+
+    with ubman.log.section('Grub'):
+        # Wait for grub to come up and offset a menu
+        ubman.p.expect(['Try or Install Ubuntu'])
+
+        # Press 'e' to edit the command line
+        ubman.log.info("Pressing 'e'")
+        ubman.run_command('e', wait_for_prompt=False, send_nl=False)
+
+        # Wait until we see the editor appear
+        ubman.p.expect(['/casper/initrd'])
+
+        # Go down to the 'linux' line. Avoid using down-arrow as that includes
+        # an Escape character, which may be parsed by Grub as such, causing it
+        # to return to the top menu
+        ubman.log.info("Going DOWN")
+        ubman.ctrl('N')
+        ubman.ctrl('N')
+        ubman.ctrl('N')
+
+        # Go to end of line
+        ubman.log.info("Going to EOL")
+        ubman.ctrl('E')
+
+        # Backspace to remove 'quiet splash'
+        ubman.log.info("Erasing quiet and splash")
+        ubman.send('\b' * len('quiet splash'))
+
+        # Send our noisy console
+        ubman.log.info("Noisy console")
+        ubman.send(CONSOLE)
+
+        # Tell grub to boot
+        ubman.log.info("boot")
+        ubman.ctrl('X')
+        ubman.p.expect(['Booting a command list'])
+
+    with ubman.log.section('Linux'):
+        # Linux should start immediately
+        ubman.p.expect(['Linux version'])
+
+    with ubman.log.section('Ubuntu'):
+        # Shortly later, we should see this banner
+        ubman.p.expect(['Welcome to .*Ubuntu 24.04.1 LTS.*!'])
+
+    ubman.restart_uboot()
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 47a584ffe7c..c73fb4abbcb 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -11,11 +11,11 @@ from fstest_defs import *
 # pylint: disable=E0611
 from tests import fs_helper
 
-supported_fs_basic = ['fat16', 'fat32', 'ext4']
-supported_fs_ext = ['fat12', 'fat16', 'fat32']
+supported_fs_basic = ['fat16', 'fat32', 'exfat', 'ext4', 'fs_generic']
+supported_fs_ext = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
 supported_fs_fat = ['fat12', 'fat16']
-supported_fs_mkdir = ['fat12', 'fat16', 'fat32']
-supported_fs_unlink = ['fat12', 'fat16', 'fat32']
+supported_fs_mkdir = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
+supported_fs_unlink = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
 supported_fs_symlink = ['ext4']
 supported_fs_rename = ['fat12', 'fat16', 'fat32']
 
@@ -108,6 +108,22 @@ def pytest_generate_tests(metafunc):
 #
 # Helper functions
 #
+def fstype_to_prefix(fs_type):
+    """Convert a file system type to an U-Boot command prefix
+
+    Args:
+        fs_type: File system type.
+
+    Return:
+        A corresponding command prefix for file system type.
+    """
+    if fs_type == 'fs_generic' or fs_type == 'exfat':
+        return ''
+    elif re.match('fat', fs_type):
+        return 'fat'
+    else:
+        return fs_type
+
 def fstype_to_ubname(fs_type):
     """Convert a file system type to an U-Boot specific string
 
@@ -139,8 +155,12 @@ def check_ubconfig(config, fs_type):
     Return:
         Nothing.
     """
-    if not config.buildconfig.get('config_cmd_%s' % fs_type, None):
+    if fs_type == 'exfat' and not config.buildconfig.get('config_fs_%s' % fs_type, None):
+        pytest.skip('.config feature "FS_%s" not enabled' % fs_type.upper())
+    if fs_type != 'exfat' and not config.buildconfig.get('config_cmd_%s' % fs_type, None):
         pytest.skip('.config feature "CMD_%s" not enabled' % fs_type.upper())
+    if fs_type == 'fs_generic' or fs_type == 'exfat':
+        return
     if not config.buildconfig.get('config_%s_write' % fs_type, None):
         pytest.skip('.config feature "%s_WRITE" not enabled'
         % fs_type.upper())
@@ -178,6 +198,8 @@ def fs_obj_basic(request, u_boot_config):
         volume file name and  a list of MD5 hashes.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
+    fs_cmd_write = 'save' if fs_type == 'fs_generic' or fs_type == 'exfat' else 'write'
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -267,7 +289,7 @@ def fs_obj_basic(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type + '. {}'.format(err))
         return
     else:
-        yield [fs_ubtype, fs_img, md5val]
+        yield [fs_ubtype, fs_cmd_prefix, fs_cmd_write, fs_img, md5val]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
@@ -288,6 +310,8 @@ def fs_obj_ext(request, u_boot_config):
         volume file name and  a list of MD5 hashes.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
+    fs_cmd_write = 'save' if fs_type == 'fs_generic' or fs_type == 'exfat' else 'write'
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -357,7 +381,7 @@ def fs_obj_ext(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img, md5val]
+        yield [fs_ubtype, fs_cmd_prefix, fs_cmd_write, fs_img, md5val]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
@@ -378,6 +402,7 @@ def fs_obj_mkdir(request, u_boot_config):
         volume file name.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -390,7 +415,7 @@ def fs_obj_mkdir(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img]
+        yield [fs_ubtype, fs_cmd_prefix, fs_img]
     call('rm -f %s' % fs_img, shell=True)
 
 #
@@ -409,6 +434,7 @@ def fs_obj_unlink(request, u_boot_config):
         volume file name.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -456,7 +482,7 @@ def fs_obj_unlink(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img]
+        yield [fs_ubtype, fs_cmd_prefix, fs_img]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
diff --git a/test/py/tests/test_fs/fstest_helpers.py b/test/py/tests/test_fs/fstest_helpers.py
index c1447b4d43e..d25326ee993 100644
--- a/test/py/tests/test_fs/fstest_helpers.py
+++ b/test/py/tests/test_fs/fstest_helpers.py
@@ -9,6 +9,8 @@ def assert_fs_integrity(fs_type, fs_img):
     try:
         if fs_type == 'ext4':
             check_call('fsck.ext4 -n -f %s' % fs_img, shell=True)
+        elif fs_type == 'exfat':
+            check_call('fsck.exfat -n %s' % fs_img, shell=True)
         elif fs_type in ['fat12', 'fat16', 'fat32']:
             check_call('fsck.fat -n %s' % fs_img, shell=True)
     except CalledProcessError:
diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py
index 5a02348bb94..64a3b50f52a 100644
--- a/test/py/tests/test_fs/test_basic.py
+++ b/test/py/tests/test_fs/test_basic.py
@@ -20,32 +20,32 @@ class TestFsBasic(object):
         """
         Test Case 1 - ls command, listing a root directory and invalid directory
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 1a - ls'):
             # Test Case 1 - ls
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sls host 0:0' % fs_type])
+                '%sls host 0:0' % fs_cmd_prefix])
             assert(re.search('2621440000 *%s' % BIG_FILE, ''.join(output)))
             assert(re.search('1048576 *%s' % SMALL_FILE, ''.join(output)))
 
         with ubman.log.section('Test Case 1b - ls (invalid dir)'):
             # In addition, test with a nonexistent directory to see if we crash.
             output = ubman.run_command(
-                '%sls host 0:0 invalid_d' % fs_type)
+                '%sls host 0:0 invalid_d' % fs_cmd_prefix)
             assert('' == output)
 
     def test_fs2(self, ubman, fs_obj_basic):
         """
         Test Case 2 - size command for a small file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 2a - size (small)'):
             # 1MB is 0x0010 0000
             # Test Case 2a - size of small file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%ssize host 0:0 /%s' % (fs_type, SMALL_FILE),
+                '%ssize host 0:0 /%s' % (fs_cmd_prefix, SMALL_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=100000' in ''.join(output))
@@ -53,7 +53,7 @@ class TestFsBasic(object):
         with ubman.log.section('Test Case 2b - size (/../<file>)'):
             # Test Case 2b - size of small file via a path using '..'
             output = ubman.run_command_list([
-                '%ssize host 0:0 /SUBDIR/../%s' % (fs_type, SMALL_FILE),
+                '%ssize host 0:0 /SUBDIR/../%s' % (fs_cmd_prefix, SMALL_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=100000' in ''.join(output))
@@ -62,13 +62,13 @@ class TestFsBasic(object):
         """
         Test Case 3 - size command for a large file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 3 - size (large)'):
             # 2.5GB (1024*1024*2500) is 0x9C40 0000
             # Test Case 3 - size of big file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%ssize host 0:0 /%s' % (fs_type, BIG_FILE),
+                '%ssize host 0:0 /%s' % (fs_cmd_prefix, BIG_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=9c400000' in ''.join(output))
@@ -77,12 +77,12 @@ class TestFsBasic(object):
         """
         Test Case 4 - load a small file, 1MB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 4 - load (small)'):
             # Test Case 4a - Read full 1MB of small file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -96,12 +96,12 @@ class TestFsBasic(object):
         """
         Test Case 5 - load, reading first 1MB of 3GB file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 5 - load (first 1MB)'):
             # Test Case 5a - First 1MB of big file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s %x 0x0' % (fs_type, ADDR, BIG_FILE, LENGTH),
+                '%sload host 0:0 %x /%s %x 0x0' % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -115,14 +115,14 @@ class TestFsBasic(object):
         """
         Test Case 6 - load, reading last 1MB of 3GB file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 6 - load (last 1MB)'):
             # fails for ext as no offset support
             # Test Case 6a - Last 1MB of big file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x9c300000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -136,14 +136,14 @@ class TestFsBasic(object):
         """
         Test Case 7 - load, 1MB from the last 1MB in 2GB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 7 - load (last 1MB in 2GB)'):
             # fails for ext as no offset support
             # Test Case 7a - One from the last 1MB chunk of 2GB
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x7ff00000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -157,14 +157,14 @@ class TestFsBasic(object):
         """
         Test Case 8 - load, reading first 1MB in 2GB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 8 - load (first 1MB in 2GB)'):
             # fails for ext as no offset support
             # Test Case 8a - One from the start 1MB chunk from 2GB
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x80000000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -178,14 +178,14 @@ class TestFsBasic(object):
         """
         Test Case 9 - load, 1MB crossing 2GB boundary
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 9 - load (crossing 2GB boundary)'):
             # fails for ext as no offset support
             # Test Case 9a - One 1MB chunk crossing the 2GB boundary
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x7ff80000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
@@ -199,14 +199,14 @@ class TestFsBasic(object):
         """
         Test Case 10 - load, reading beyond file end'):
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 10 - load (beyond file end)'):
             # Generic failure case
             # Test Case 10 - 2MB chunk from the last 1MB of big file
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s 0x00200000 0x9c300000'
-                    % (fs_type, ADDR, BIG_FILE),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE),
                 'printenv filesize',
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
@@ -216,22 +216,22 @@ class TestFsBasic(object):
         """
         Test Case 11 - write'
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 11 - write'):
             # Read 1MB from small file
             # Write it back to test the writes
             # Test Case 11a - Check that the write succeeded
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
-                '%swrite host 0:0 %x /%s.w $filesize'
-                    % (fs_type, ADDR, SMALL_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
+                '%s%s host 0:0 %x /%s.w $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, SMALL_FILE)])
             assert('1048576 bytes written' in ''.join(output))
 
             # Test Case 11b - Check md5 of written to is same
             # as the one read from
             output = ubman.run_command_list([
-                '%sload host 0:0 %x /%s.w' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /%s.w' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
@@ -241,7 +241,7 @@ class TestFsBasic(object):
         """
         Test Case 12 - write to "." directory
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 12 - write (".")'):
             # Next test case checks writing a file whose dirent
             # is the first in the block, which is always true for "."
@@ -249,7 +249,8 @@ class TestFsBasic(object):
             # Test Case 12 - Check directory traversal
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%swrite host 0:0 %x /. 0x10' % (fs_type, ADDR)])
+                '%s%s host 0:0 %x /. 0x10'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR)])
             assert('Unable to write' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -257,23 +258,23 @@ class TestFsBasic(object):
         """
         Test Case 13 - write to a file with "/./<filename>"
         """
-        fs_type,fs_img,md5val = fs_obj_basic
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
         with ubman.log.section('Test Case 13 - write  ("./<file>")'):
             # Read 1MB from small file
             # Write it via "same directory", i.e. "." dirent
             # Test Case 13a - Check directory traversal
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
-                '%swrite host 0:0 %x /./%s2 $filesize'
-                    % (fs_type, ADDR, SMALL_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
+                '%s%s host 0:0 %x /./%s2 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, SMALL_FILE)])
             assert('1048576 bytes written' in ''.join(output))
 
             # Test Case 13b - Check md5 of written to is same
             # as the one read from
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /./%s2' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /./%s2' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
@@ -282,7 +283,7 @@ class TestFsBasic(object):
             # as the one read from
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /%s2' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /%s2' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
diff --git a/test/py/tests/test_fs/test_ext.py b/test/py/tests/test_fs/test_ext.py
index 9c213f2da55..41f126e7876 100644
--- a/test/py/tests/test_fs/test_ext.py
+++ b/test/py/tests/test_fs/test_ext.py
@@ -33,20 +33,20 @@ class TestFsExt(object):
         """
         Test Case 1 - write a file with absolute path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 1 - write with abs path'):
             # Test Case 1a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w1 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w1 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('20480 bytes written' in ''.join(output))
 
             # Test Case 1b - Check md5 of file content
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w1' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w1' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
@@ -56,20 +56,20 @@ class TestFsExt(object):
         """
         Test Case 2 - write to a file with relative path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 2 - write with rel path'):
             # Test Case 2a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x dir1/%s.w2 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x dir1/%s.w2 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('20480 bytes written' in ''.join(output))
 
             # Test Case 2b - Check md5 of file content
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x dir1/%s.w2' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x dir1/%s.w2' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
@@ -79,14 +79,14 @@ class TestFsExt(object):
         """
         Test Case 3 - write to a file with invalid path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 3 - write with invalid path'):
             # Test Case 3 - Check if command expectedly failed
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/none/%s.w3 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/none/%s.w3 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('Unable to write file /dir1/none/' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -94,22 +94,22 @@ class TestFsExt(object):
         """
         Test Case 4 - write at non-zero offset, enlarging file size
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
             # Test Case 4a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w4 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w4 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             output = ubman.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%s%s host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('20480 bytes written' in output)
 
             # Test Case 4b - Check size of written file
             output = ubman.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w4' % (fs_type, MIN_FILE),
+                '%ssize host 0:0 /dir1/%s.w4' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=6400' in ''.join(output))
@@ -117,7 +117,7 @@ class TestFsExt(object):
             # Test Case 4c - Check md5 of file content
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w4' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w4' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[1] in ''.join(output))
@@ -127,22 +127,22 @@ class TestFsExt(object):
         """
         Test Case 5 - write at non-zero offset, shrinking file size
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
             # Test Case 5a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w5 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w5 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             output = ubman.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%s%s host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('5120 bytes written' in output)
 
             # Test Case 5b - Check size of written file
             output = ubman.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w5' % (fs_type, MIN_FILE),
+                '%ssize host 0:0 /dir1/%s.w5' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=2800' in ''.join(output))
@@ -150,7 +150,7 @@ class TestFsExt(object):
             # Test Case 5c - Check md5 of file content
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w5' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w5' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[2] in ''.join(output))
@@ -160,22 +160,22 @@ class TestFsExt(object):
         """
         Test Case 6 - write nothing at the start, truncating to zero
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
             # Test Case 6a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w6 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w6 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             output = ubman.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w6 0 0'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%s%s host 0:0 %x /dir1/%s.w6 0 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('0 bytes written' in output)
 
             # Test Case 6b - Check size of written file
             output = ubman.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w6' % (fs_type, MIN_FILE),
+                '%ssize host 0:0 /dir1/%s.w6' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=0' in ''.join(output))
@@ -185,22 +185,22 @@ class TestFsExt(object):
         """
         Test Case 7 - write at the end (append)
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 7 - write at the end (append)'):
             # Test Case 7a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w7 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w7 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             output = ubman.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w7 $filesize $filesize'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%s%s host 0:0 %x /dir1/%s.w7 $filesize $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('20480 bytes written' in output)
 
             # Test Case 7b - Check size of written file
             output = ubman.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w7' % (fs_type, MIN_FILE),
+                '%ssize host 0:0 /dir1/%s.w7' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=a000' in ''.join(output))
@@ -208,7 +208,7 @@ class TestFsExt(object):
             # Test Case 7c - Check md5 of file content
             output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w7' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w7' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[3] in ''.join(output))
@@ -218,17 +218,17 @@ class TestFsExt(object):
         """
         Test Case 8 - write at offset beyond the end of file
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 8 - write beyond the end'):
             # Test Case 8a - Check if command expectedly failed
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w8 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w8 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             output = ubman.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w8 0x1400 %x'
-                    % (fs_type, ADDR, MIN_FILE, 0x100000 + 0x1400))
+                '%s%s host 0:0 %x /dir1/%s.w8 0x1400 %x'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE, 0x100000 + 0x1400))
             assert('Unable to write file /dir1' in output)
             assert_fs_integrity(fs_type, fs_img)
 
@@ -236,14 +236,14 @@ class TestFsExt(object):
         """
         Test Case 9 - write to a non-existing file at non-zero offset
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
             # Test Case 9a - Check if command expectedly failed
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('Unable to write file /dir1' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -252,7 +252,7 @@ class TestFsExt(object):
         'Test Case 10 - create/delete as many directories under root directory
         as amount of directory entries goes beyond one cluster size)'
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 10 - create/delete (many)'):
             # Test Case 10a - Create many files
             #   Please note that the size of directory entry is 32 bytes.
@@ -262,9 +262,9 @@ class TestFsExt(object):
 
             for i in range(0, 66):
                 output = ubman.run_command(
-                    '%swrite host 0:0 %x /FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = ubman.run_command('%sls host 0:0 /' % fs_type)
+                    '%s%s host 0:0 %x /FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert('FILE0123456789_00' in output)
             assert('FILE0123456789_41' in output)
 
@@ -272,8 +272,8 @@ class TestFsExt(object):
             for i in range(0, 66):
                 output = ubman.run_command(
                     '%srm host 0:0 /FILE0123456789_%02x'
-                    % (fs_type, i))
-            output = ubman.run_command('%sls host 0:0 /' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert(not 'FILE0123456789_00' in output)
             assert(not 'FILE0123456789_41' in output)
 
@@ -281,9 +281,9 @@ class TestFsExt(object):
             # Please note no.64 and 65 are intentionally re-created
             for i in range(64, 128):
                 output = ubman.run_command(
-                    '%swrite host 0:0 %x /FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = ubman.run_command('%sls host 0:0 /' % fs_type)
+                    '%s%s host 0:0 %x /FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert('FILE0123456789_40' in output)
             assert('FILE0123456789_79' in output)
 
@@ -294,7 +294,7 @@ class TestFsExt(object):
         'Test Case 11 - create/delete as many directories under non-root
         directory as amount of directory entries goes beyond one cluster size)'
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 11 - create/delete (many)'):
             # Test Case 11a - Create many files
             #   Please note that the size of directory entry is 32 bytes.
@@ -304,9 +304,9 @@ class TestFsExt(object):
 
             for i in range(0, 66):
                 output = ubman.run_command(
-                    '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
+                    '%s%s host 0:0 %x /dir1/FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert('FILE0123456789_00' in output)
             assert('FILE0123456789_41' in output)
 
@@ -314,8 +314,8 @@ class TestFsExt(object):
             for i in range(0, 66):
                 output = ubman.run_command(
                     '%srm host 0:0 /dir1/FILE0123456789_%02x'
-                    % (fs_type, i))
-            output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert(not 'FILE0123456789_00' in output)
             assert(not 'FILE0123456789_41' in output)
 
@@ -323,9 +323,9 @@ class TestFsExt(object):
             # Please note no.64 and 65 are intentionally re-created
             for i in range(64, 128):
                 output = ubman.run_command(
-                    '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = ubman.run_command('%sls host 0:0 /dir1' % fs_type)
+                    '%s%s host 0:0 %x /dir1/FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert('FILE0123456789_40' in output)
             assert('FILE0123456789_79' in output)
 
@@ -335,21 +335,29 @@ class TestFsExt(object):
         """
         Test Case 12 - write plain and mangle file
         """
-        fs_type,fs_img,md5val = fs_obj_ext
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
         with ubman.log.section('Test Case 12 - write plain and mangle file'):
             # Test Case 12a - Check if command successfully returned
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%swrite host 0:0 %x /%s 0'
-                    % (fs_type, ADDR, PLAIN_FILE),
-                '%swrite host 0:0 %x /%s 0'
-                    % (fs_type, ADDR, MANGLE_FILE)])
+                '%s%s host 0:0 %x /%s 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, PLAIN_FILE),
+                '%s%s host 0:0 %x /%s 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MANGLE_FILE)])
             assert('0 bytes written' in ''.join(output))
-            # Test Case 12b - Read file system content
-            output = check_output('mdir -i %s' % fs_img, shell=True).decode()
-            # Test Case 12c - Check if short filename is not mangled
-            assert(str2fat(PLAIN_FILE) in ''.join(output))
-            # Test Case 12d - Check if long filename is mangled
-            assert(str2fat(MANGLE_FILE) in ''.join(output))
+            if fs_type == 'exfat':
+                # Test Case 12b - Read file system content
+                output = check_output('fattools ls %s' % fs_img, shell=True).decode()
+                # Test Case 12c - Check if short filename is not mangled
+                assert(PLAIN_FILE in ''.join(output))
+                # Test Case 12d - Check if long filename is mangled
+                assert(MANGLE_FILE in ''.join(output))
+            else:
+                # Test Case 12b - Read file system content
+                output = check_output('mdir -i %s' % fs_img, shell=True).decode()
+                # Test Case 12c - Check if short filename is not mangled
+                assert(str2fat(PLAIN_FILE) in ''.join(output))
+                # Test Case 12d - Check if long filename is mangled
+                assert(str2fat(MANGLE_FILE) in ''.join(output))
 
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_mkdir.py b/test/py/tests/test_fs/test_mkdir.py
index df680a87d57..1578c3cba3a 100644
--- a/test/py/tests/test_fs/test_mkdir.py
+++ b/test/py/tests/test_fs/test_mkdir.py
@@ -18,16 +18,16 @@ class TestMkdir(object):
         """
         Test Case 1 - create a directory under a root
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 1 - mkdir'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir1' % fs_type,
-                '%sls host 0:0 /' % fs_type])
+                '%smkdir host 0:0 dir1' % fs_cmd_prefix,
+                '%sls host 0:0 /' % fs_cmd_prefix])
             assert('dir1/' in ''.join(output))
 
             output = ubman.run_command(
-                '%sls host 0:0 dir1' % fs_type)
+                '%sls host 0:0 dir1' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
             assert_fs_integrity(fs_type, fs_img)
@@ -37,16 +37,16 @@ class TestMkdir(object):
         """
         Test Case 2 - create a directory under a sub-directory
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 2 - mkdir (sub-sub directory)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir1/dir2' % fs_type,
-                '%sls host 0:0 dir1' % fs_type])
+                '%smkdir host 0:0 dir1/dir2' % fs_cmd_prefix,
+                '%sls host 0:0 dir1' % fs_cmd_prefix])
             assert('dir2/' in ''.join(output))
 
             output = ubman.run_command(
-                '%sls host 0:0 dir1/dir2' % fs_type)
+                '%sls host 0:0 dir1/dir2' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
             assert_fs_integrity(fs_type, fs_img)
@@ -56,11 +56,11 @@ class TestMkdir(object):
         Test Case 3 - trying to create a directory with a non-existing
         path should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 3 - mkdir (non-existing path)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 none/dir3' % fs_type])
+                '%smkdir host 0:0 none/dir3' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -68,11 +68,11 @@ class TestMkdir(object):
         """
         Test Case 4 - trying to create "." should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 4 - mkdir (".")'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 .' % fs_type])
+                '%smkdir host 0:0 .' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -80,11 +80,11 @@ class TestMkdir(object):
         """
         Test Case 5 - trying to create ".." should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 5 - mkdir ("..")'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 ..' % fs_type])
+                '%smkdir host 0:0 ..' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -93,29 +93,29 @@ class TestMkdir(object):
         'Test Case 6 - create as many directories as amount of directory
         entries goes beyond a cluster size)'
         """
-        fs_type,fs_img = fs_obj_mkdir
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
         with ubman.log.section('Test Case 6 - mkdir (create many)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir6' % fs_type,
-                '%sls host 0:0 /' % fs_type])
+                '%smkdir host 0:0 dir6' % fs_cmd_prefix,
+                '%sls host 0:0 /' % fs_cmd_prefix])
             assert('dir6/' in ''.join(output))
 
             for i in range(0, 20):
                 output = ubman.run_command(
                     '%smkdir host 0:0 dir6/0123456789abcdef%02x'
-                    % (fs_type, i))
-            output = ubman.run_command('%sls host 0:0 dir6' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 dir6' % fs_cmd_prefix)
             assert('0123456789abcdef00/'  in output)
             assert('0123456789abcdef13/'  in output)
 
             output = ubman.run_command(
-                '%sls host 0:0 dir6/0123456789abcdef13/.' % fs_type)
+                '%sls host 0:0 dir6/0123456789abcdef13/.' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
 
             output = ubman.run_command(
-                '%sls host 0:0 dir6/0123456789abcdef13/..' % fs_type)
+                '%sls host 0:0 dir6/0123456789abcdef13/..' % fs_cmd_prefix)
             assert('0123456789abcdef00/'  in output)
             assert('0123456789abcdef13/'  in output)
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_unlink.py b/test/py/tests/test_fs/test_unlink.py
index 7e911f02413..1e2df3dbfd8 100644
--- a/test/py/tests/test_fs/test_unlink.py
+++ b/test/py/tests/test_fs/test_unlink.py
@@ -19,16 +19,16 @@ class TestUnlink(object):
         """
         Test Case 1 - delete a file
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 1 - unlink (file)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir1/file1' % fs_type,
-                '%sls host 0:0 dir1/file1' % fs_type])
+                '%srm host 0:0 dir1/file1' % fs_cmd_prefix,
+                '%sls host 0:0 dir1/file1' % fs_cmd_prefix])
             assert('' == ''.join(output))
 
             output = ubman.run_command(
-                '%sls host 0:0 dir1/' % fs_type)
+                '%sls host 0:0 dir1/' % fs_cmd_prefix)
             assert(not 'file1' in output)
             assert('file2' in output)
             assert_fs_integrity(fs_type, fs_img)
@@ -37,18 +37,18 @@ class TestUnlink(object):
         """
         Test Case 2 - delete many files
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 2 - unlink (many)'):
             output = ubman.run_command('host bind 0 %s' % fs_img)
 
             for i in range(0, 20):
                 output = ubman.run_command_list([
-                    '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
-                    '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
+                    '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_cmd_prefix, i),
+                    '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_cmd_prefix, i)])
                 assert('' == ''.join(output))
 
             output = ubman.run_command(
-                '%sls host 0:0 dir2' % fs_type)
+                '%sls host 0:0 dir2' % fs_cmd_prefix)
             assert('0 file(s), 2 dir(s)' in output)
             assert_fs_integrity(fs_type, fs_img)
 
@@ -56,11 +56,11 @@ class TestUnlink(object):
         """
         Test Case 3 - trying to delete a non-existing file should fail
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 3 - unlink (non-existing)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir1/nofile' % fs_type])
+                '%srm host 0:0 dir1/nofile' % fs_cmd_prefix])
             assert('nofile: doesn\'t exist' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -68,15 +68,15 @@ class TestUnlink(object):
         """
         Test Case 4 - delete an empty directory
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 4 - unlink (directory)'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir4' % fs_type])
+                '%srm host 0:0 dir4' % fs_cmd_prefix])
             assert('' == ''.join(output))
 
             output = ubman.run_command(
-                '%sls host 0:0 /' % fs_type)
+                '%sls host 0:0 /' % fs_cmd_prefix)
             assert(not 'dir4' in output)
             assert_fs_integrity(fs_type, fs_img)
 
@@ -85,11 +85,11 @@ class TestUnlink(object):
         Test Case 5 - trying to deleting a non-empty directory ".."
         should fail
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 5 - unlink ("non-empty directory")'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5' % fs_type])
+                '%srm host 0:0 dir5' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -97,11 +97,11 @@ class TestUnlink(object):
         """
         Test Case 6 - trying to deleting a "." should fail
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 6 - unlink (".")'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5/.' % fs_type])
+                '%srm host 0:0 dir5/.' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
@@ -109,10 +109,10 @@ class TestUnlink(object):
         """
         Test Case 7 - trying to deleting a ".." should fail
         """
-        fs_type,fs_img = fs_obj_unlink
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
         with ubman.log.section('Test Case 7 - unlink ("..")'):
             output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5/..' % fs_type])
+                '%srm host 0:0 dir5/..' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 3a3f12d0898..cdf54adc600 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -27,6 +27,17 @@ def mkdir_cond(dirname):
     if not os.path.exists(dirname):
         os.mkdir(dirname)
 
+def copy_partition(ubman, fsfile, outname):
+    """Copy a partition into a disk iamge
+
+    Args:
+        ubman (ConsoleBase): U-Boot fixture
+        fsfile (str): Name of partition file
+        outname (str): Name of full-disk file to update
+    """
+    utils.run_and_log(ubman,
+                      f'dd if={fsfile} of={outname} bs=1M seek=1 conv=notrunc')
+
 def setup_bootmenu_image(ubman):
     """Create a 20MB disk image with a single ext4 partition
 
@@ -142,7 +153,7 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
     fsfile = 'ext18M.img'
     utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
     utils.run_and_log(ubman, f'mkfs.ext4 {fsfile} -d {mnt}')
-    utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+    copy_partition(ubman, fsfile, fname)
     utils.run_and_log(ubman, f'rm -rf {mnt}')
     utils.run_and_log(ubman, f'rm -f {fsfile}')
 
@@ -194,7 +205,7 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
     utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
     utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
     utils.run_and_log(ubman, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
-    utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+    copy_partition(ubman, fsfile, fname)
     utils.run_and_log(ubman, f'rm -rf {mnt}')
     utils.run_and_log(ubman, f'rm -f {fsfile}')
 
@@ -532,7 +543,7 @@ def setup_efi_image(ubman):
     utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
     utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
     utils.run_and_log(ubman, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
-    utils.run_and_log(ubman, f'dd if={fsfile} of={fname} bs=1M seek=1')
+    copy_partition(ubman, fsfile, fname)
     utils.run_and_log(ubman, f'rm -rf {mnt}')
     utils.run_and_log(ubman, f'rm -f {fsfile}')
 
diff --git a/tools/binman/control.py b/tools/binman/control.py
index e73c598298c..81f61e3e152 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -522,9 +522,13 @@ def _ProcessTemplates(parent):
 def _RemoveTemplates(parent):
     """Remove any templates in the binman description
     """
+    del_nodes = []
     for node in parent.subnodes:
         if node.name.startswith('template'):
-            node.Delete()
+            del_nodes.append(node)
+
+    for node in del_nodes:
+        node.Delete()
 
 def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded, indir):
     """Prepare the images to be processed and select the device tree
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 1a92a99b511..948fcc02259 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -7990,5 +7990,12 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         """Test an image with an FIT with multiple FDT images using NAME"""
         self.CheckFitFdt('345_fit_fdt_name.dts', use_seq_num=False)
 
+    def testRemoveTemplate(self):
+        """Test whether template is removed"""
+        TestFunctional._MakeInputFile('my-blob.bin', b'blob')
+        TestFunctional._MakeInputFile('my-blob2.bin', b'other')
+        self._DoTestFile('346_remove_template.dts',
+                         force_missing_bintools='openssl',)
+
 if __name__ == "__main__":
     unittest.main()
diff --git a/tools/binman/test/346_remove_template.dts b/tools/binman/test/346_remove_template.dts
new file mode 100644
index 00000000000..e05229f3ebc
--- /dev/null
+++ b/tools/binman/test/346_remove_template.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/ {
+    binman: binman {
+		multiple-images;
+
+		template_1: template-1 {
+			section {
+				phandle1: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+		template_2: template-2 {
+			section {
+				ti-secure {
+					content = <&phandle2>;
+					keyfile = "key.pem";
+				};
+				phandle2: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+		template_3: template-3 {
+			section {
+				phandle3: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+
+		file1 {
+			insert-template = <&template_1>;
+		};
+
+		file2 {
+			insert-template = <&template_2>;
+		};
+
+		file3 {
+			insert-template = <&template_3>;
+		};
+	};
+};
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index d779040c74e..b45eb95a1e6 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -288,11 +288,11 @@ class TestFunctional(unittest.TestCase):
         """Test gitutils.Setup(), from outside the module itself"""
         command.TEST_RESULT = command.CommandResult(return_code=1)
         gitutil.setup()
-        self.assertEqual(gitutil.use_no_decorate, False)
+        self.assertEqual(gitutil.USE_NO_DECORATE, False)
 
         command.TEST_RESULT = command.CommandResult(return_code=0)
         gitutil.setup()
-        self.assertEqual(gitutil.use_no_decorate, True)
+        self.assertEqual(gitutil.USE_NO_DECORATE, True)
 
     def _HandleCommandGitLog(self, args):
         if args[-1] == '--':
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index f28fbf97cac..e14d1640f9c 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -74,6 +74,7 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \
 	e2fsprogs \
 	efitools \
 	erofs-utils \
+	exfatprogs \
 	expect \
 	fakeroot \
 	flex \
diff --git a/tools/qconfig.py b/tools/qconfig.py
index 259adbe1bc9..c96a305a48f 100755
--- a/tools/qconfig.py
+++ b/tools/qconfig.py
@@ -1453,7 +1453,7 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options used as Proper in Makefiles but without a non-xPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= {not_found.keys()}
+    proper_not_found |= not_found.keys()
 
     # Scan the source code
     all_uses, _ = scan_src_files(src_list)
@@ -1471,7 +1471,7 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options used as Proper in source but without a non-xPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= {not_found.keys()}
+    proper_not_found |= not_found.keys()
 
     print('\nCONFIG options used as SPL but without an xPL_ variant:')
     for item in sorted(spl_not_found):
diff --git a/tools/sfspl.c b/tools/sfspl.c
index c76420ce21b..516e96e8dd9 100644
--- a/tools/sfspl.c
+++ b/tools/sfspl.c
@@ -70,11 +70,14 @@ static int sfspl_verify_header(unsigned char *buf, int size,
 		printf("Truncated file\n");
 		return EXIT_FAILURE;
 	}
+	if ((size_t)size > hdr_size + file_size)
+		printf("File too long, expected %u bytes\n",
+		       hdr_size + file_size);
 	if (hdr->version != DEFAULT_VERSION) {
 		printf("Unknown file format version\n");
 		return EXIT_FAILURE;
 	}
-	crc_check = crc32(0, &buf[hdr_size], size - hdr_size);
+	crc_check = crc32(0, &buf[hdr_size], file_size);
 	if (crc_check != crc) {
 		printf("Incorrect CRC32\n");
 		return EXIT_FAILURE;
diff --git a/tools/u_boot_pylib/gitutil.py b/tools/u_boot_pylib/gitutil.py
index 6d6a7eedecc..5e3e98ac9a6 100644
--- a/tools/u_boot_pylib/gitutil.py
+++ b/tools/u_boot_pylib/gitutil.py
@@ -10,7 +10,7 @@ from u_boot_pylib import command
 from u_boot_pylib import terminal
 
 # True to use --no-decorate - we check this in setup()
-use_no_decorate = True
+USE_NO_DECORATE = True
 
 
 def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
@@ -18,11 +18,11 @@ def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
     """Create a command to perform a 'git log'
 
     Args:
-        commit_range: Range expression to use for log, None for none
-        git_dir: Path to git repository (None to use default)
-        oneline: True to use --oneline, else False
-        reverse: True to reverse the log (--reverse)
-        count: Number of commits to list, or None for no limit
+        commit_range (str): Range expression to use for log, None for none
+        git_dir (str): Path to git repository (None to use default)
+        oneline (bool): True to use --oneline, else False
+        reverse (bool): True to reverse the log (--reverse)
+        count (int or None): Number of commits to list, or None for no limit
     Return:
         List containing command and arguments to run
     """
@@ -32,12 +32,12 @@ def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
     cmd += ['--no-pager', 'log', '--no-color']
     if oneline:
         cmd.append('--oneline')
-    if use_no_decorate:
+    if USE_NO_DECORATE:
         cmd.append('--no-decorate')
     if reverse:
         cmd.append('--reverse')
     if count is not None:
-        cmd.append('-n%d' % count)
+        cmd.append(f'-n{count}')
     if commit_range:
         cmd.append(commit_range)
 
@@ -55,22 +55,22 @@ def count_commits_to_branch(branch):
     since then.
 
     Args:
-        branch: Branch to count from (None for current branch)
+        branch (str or None): Branch to count from (None for current branch)
 
     Return:
         Number of patches that exist on top of the branch
     """
     if branch:
-        us, msg = get_upstream('.git', branch)
-        rev_range = '%s..%s' % (us, branch)
+        us, _ = get_upstream('.git', branch)
+        rev_range = f'{us}..{branch}'
     else:
         rev_range = '@{upstream}..'
     cmd = log_cmd(rev_range, oneline=True)
     result = command.run_one(*cmd, capture=True, capture_stderr=True,
                              oneline=True, raise_on_error=False)
     if result.return_code:
-        raise ValueError('Failed to determine upstream: %s' %
-                         result.stderr.strip())
+        raise ValueError(
+            f'Failed to determine upstream: {result.stderr.strip()}')
     patch_count = len(result.stdout.splitlines())
     return patch_count
 
@@ -79,7 +79,7 @@ def name_revision(commit_hash):
     """Gets the revision name for a commit
 
     Args:
-        commit_hash: Commit hash to look up
+        commit_hash (str): Commit hash to look up
 
     Return:
         Name of revision, if any, else None
@@ -99,8 +99,8 @@ def guess_upstream(git_dir, branch):
     'git name-rev' returns a plain branch name, with no ! or ^ modifiers.
 
     Args:
-        git_dir: Git directory containing repo
-        branch: Name of branch
+        git_dir (str): Git directory containing repo
+        branch (str): Name of branch
 
     Returns:
         Tuple:
@@ -111,23 +111,23 @@ def guess_upstream(git_dir, branch):
     result = command.run_one(*cmd, capture=True, capture_stderr=True,
                              raise_on_error=False)
     if result.return_code:
-        return None, "Branch '%s' not found" % branch
+        return None, f"Branch '{branch}' not found"
     for line in result.stdout.splitlines()[1:]:
         commit_hash = line.split(' ')[0]
         name = name_revision(commit_hash)
         if '~' not in name and '^' not in name:
             if name.startswith('remotes/'):
                 name = name[8:]
-            return name, "Guessing upstream as '%s'" % name
-    return None, "Cannot find a suitable upstream for branch '%s'" % branch
+            return name, f"Guessing upstream as '{name}'"
+    return None, f"Cannot find a suitable upstream for branch '{branch}'"
 
 
 def get_upstream(git_dir, branch):
     """Returns the name of the upstream for a branch
 
     Args:
-        git_dir: Git directory containing repo
-        branch: Name of branch
+        git_dir (str): Git directory containing repo
+        branch (str): Name of branch
 
     Returns:
         Tuple:
@@ -136,31 +136,30 @@ def get_upstream(git_dir, branch):
     """
     try:
         remote = command.output_one_line('git', '--git-dir', git_dir, 'config',
-                                         'branch.%s.remote' % branch)
+                                         f'branch.{branch}.remote')
         merge = command.output_one_line('git', '--git-dir', git_dir, 'config',
-                                        'branch.%s.merge' % branch)
+                                        f'branch.{branch}.merge')
     except command.CommandExc:
         upstream, msg = guess_upstream(git_dir, branch)
         return upstream, msg
 
     if remote == '.':
         return merge, None
-    elif remote and merge:
+    if remote and merge:
         # Drop the initial refs/heads from merge
         leaf = merge.split('/', maxsplit=2)[2:]
-        return '%s/%s' % (remote, '/'.join(leaf)), None
-    else:
-        raise ValueError("Cannot determine upstream branch for branch "
-                         "'%s' remote='%s', merge='%s'"
-                         % (branch, remote, merge))
+        return f'{remote}/{"/".join(leaf)}', None
+    raise ValueError("Cannot determine upstream branch for branch "
+                     f"'{branch}' remote='{remote}', merge='{merge}'")
 
 
 def get_range_in_branch(git_dir, branch, include_upstream=False):
     """Returns an expression for the commits in the given branch.
 
     Args:
-        git_dir: Directory containing git repo
-        branch: Name of branch
+        git_dir (str): Directory containing git repo
+        branch (str): Name of branch
+        include_upstream (bool): Include the upstream commit as well
     Return:
         Expression in the form 'upstream..branch' which can be used to
         access the commits. If the branch does not exist, returns None.
@@ -168,7 +167,7 @@ def get_range_in_branch(git_dir, branch, include_upstream=False):
     upstream, msg = get_upstream(git_dir, branch)
     if not upstream:
         return None, msg
-    rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
+    rstr = f"{upstream}{'~' if include_upstream else ''}..{branch}"
     return rstr, msg
 
 
@@ -176,8 +175,8 @@ def count_commits_in_range(git_dir, range_expr):
     """Returns the number of commits in the given range.
 
     Args:
-        git_dir: Directory containing git repo
-        range_expr: Range to check
+        git_dir (str): Directory containing git repo
+        range_expr (str): Range to check
     Return:
         Number of patches that exist in the supplied range or None if none
         were found
@@ -186,7 +185,7 @@ def count_commits_in_range(git_dir, range_expr):
     result = command.run_one(*cmd, capture=True, capture_stderr=True,
                              raise_on_error=False)
     if result.return_code:
-        return None, "Range '%s' not found or is invalid" % range_expr
+        return None, f"Range '{range_expr}' not found or is invalid"
     patch_count = len(result.stdout.splitlines())
     return patch_count, None
 
@@ -195,8 +194,9 @@ def count_commits_in_branch(git_dir, branch, include_upstream=False):
     """Returns the number of commits in the given branch.
 
     Args:
-        git_dir: Directory containing git repo
-        branch: Name of branch
+        git_dir (str): Directory containing git repo
+        branch (str): Name of branch
+        include_upstream (bool): Include the upstream commit as well
     Return:
         Number of patches that exist on top of the branch, or None if the
         branch does not exist.
@@ -211,7 +211,7 @@ def count_commits(commit_range):
     """Returns the number of commits in the given range.
 
     Args:
-        commit_range: Range of commits to count (e.g. 'HEAD..base')
+        commit_range (str): Range of commits to count (e.g. 'HEAD..base')
     Return:
         Number of patches that exist on top of the branch
     """
@@ -226,7 +226,10 @@ def checkout(commit_hash, git_dir=None, work_tree=None, force=False):
     """Checkout the selected commit for this build
 
     Args:
-        commit_hash: Commit hash to check out
+        commit_hash (str): Commit hash to check out
+        git_dir (str): Directory containing git repo, or None for current dir
+        work_tree (str): Git worktree to use, or None if none
+        force (bool): True to force the checkout (git checkout -f)
     """
     pipe = ['git']
     if git_dir:
@@ -240,26 +243,28 @@ def checkout(commit_hash, git_dir=None, work_tree=None, force=False):
     result = command.run_pipe([pipe], capture=True, raise_on_error=False,
                               capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git checkout (%s): %s' % (pipe, result.stderr))
+        raise OSError(f'git checkout ({pipe}): {result.stderr}')
 
 
-def clone(git_dir, output_dir):
-    """Checkout the selected commit for this build
+def clone(repo, output_dir):
+    """Clone a repo
 
     Args:
-        commit_hash: Commit hash to check out
+        repo (str): Repo to clone (e.g. web address)
+        output_dir (str): Directory to close into
     """
-    result = command.run_one('git', 'clone', git_dir, '.', capture=True,
+    result = command.run_one('git', 'clone', repo, '.', capture=True,
                              cwd=output_dir, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git clone: %s' % result.stderr)
+        raise OSError(f'git clone: {result.stderr}')
 
 
 def fetch(git_dir=None, work_tree=None):
     """Fetch from the origin repo
 
     Args:
-        commit_hash: Commit hash to check out
+        git_dir (str): Directory containing git repo, or None for current dir
+        work_tree (str or None): Git worktree to use, or None if none
     """
     cmd = ['git']
     if git_dir:
@@ -269,14 +274,14 @@ def fetch(git_dir=None, work_tree=None):
     cmd.append('fetch')
     result = command.run_one(*cmd, capture=True, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git fetch: %s' % result.stderr)
+        raise OSError(f'git fetch: {result.stderr}')
 
 
 def check_worktree_is_available(git_dir):
     """Check if git-worktree functionality is available
 
     Args:
-        git_dir: The repository to test in
+        git_dir (str): The repository to test in
 
     Returns:
         True if git-worktree commands will work, False otherwise.
@@ -291,9 +296,9 @@ def add_worktree(git_dir, output_dir, commit_hash=None):
     """Create and checkout a new git worktree for this build
 
     Args:
-        git_dir: The repository to checkout the worktree from
-        output_dir: Path for the new worktree
-        commit_hash: Commit hash to checkout
+        git_dir (str): The repository to checkout the worktree from
+        output_dir (str): Path for the new worktree
+        commit_hash (str): Commit hash to checkout
     """
     # We need to pass --detach to avoid creating a new branch
     cmd = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
@@ -302,19 +307,19 @@ def add_worktree(git_dir, output_dir, commit_hash=None):
     result = command.run_one(*cmd, capture=True, cwd=output_dir,
                              capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git worktree add: %s' % result.stderr)
+        raise OSError(f'git worktree add: {result.stderr}')
 
 
 def prune_worktrees(git_dir):
     """Remove administrative files for deleted worktrees
 
     Args:
-        git_dir: The repository whose deleted worktrees should be pruned
+        git_dir (str): The repository whose deleted worktrees should be pruned
     """
     result = command.run_one('git', '--git-dir', git_dir, 'worktree', 'prune',
                              capture=True, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git worktree prune: %s' % result.stderr)
+        raise OSError(f'git worktree prune: {result.stderr}')
 
 
 def create_patches(branch, start, count, ignore_binary, series, signoff=True):
@@ -324,11 +329,12 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
     git format-patch.
 
     Args:
-        branch: Branch to create patches from (None for current branch)
-        start: Commit to start from: 0=HEAD, 1=next one, etc.
-        count: number of commits to include
-        ignore_binary: Don't generate patches for binary files
-        series: Series object for this series (set of patches)
+        branch (str): Branch to create patches from (None for current branch)
+        start (int): Commit to start from: 0=HEAD, 1=next one, etc.
+        count (int): number of commits to include
+        ignore_binary (bool): Don't generate patches for binary files
+        series (Series): Series object for this series (set of patches)
+        signoff (bool): True to add signoff lines automatically
     Return:
         Filename of cover letter (None if none)
         List of filenames of patch files
@@ -342,9 +348,9 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
         cmd.append('--cover-letter')
     prefix = series.GetPatchPrefix()
     if prefix:
-        cmd += ['--subject-prefix=%s' % prefix]
+        cmd += [f'--subject-prefix={prefix}']
     brname = branch or 'HEAD'
-    cmd += ['%s~%d..%s~%d' % (brname, start + count, brname, start)]
+    cmd += [f'{brname}~{start + count}..{brname}~{start}']
 
     stdout = command.run_list(cmd)
     files = stdout.splitlines()
@@ -352,8 +358,7 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
     # We have an extra file if there is a cover letter
     if series.get('cover'):
         return files[0], files[1:]
-    else:
-        return None, files
+    return None, files
 
 
 def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
@@ -367,11 +372,13 @@ def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
     command line parameter) then the email address is quoted.
 
     Args:
-        in_list:        List of aliases/email addresses
-        tag:            Text to put before each address
-        alias:          Alias dictionary
-        warn_on_error: True to raise an error when an alias fails to match,
-                False to just print a message.
+        in_list (list of str): List of aliases/email addresses
+        tag (str): Text to put before each address
+        alias (dict): Alias dictionary:
+            key: alias
+            value: list of aliases or email addresses
+        warn_on_error (bool): True to raise an error when an alias fails to
+            match, False to just print a message.
 
     Returns:
         List of email addresses
@@ -399,7 +406,7 @@ def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
         if item not in result:
             result.append(item)
     if tag:
-        return ['%s %s%s%s' % (tag, quote, email, quote) for email in result]
+        return [f'{tag} {quote}{email}{quote}' for email in result]
     return result
 
 
@@ -407,24 +414,23 @@ def check_suppress_cc_config():
     """Check if sendemail.suppresscc is configured correctly.
 
     Returns:
-        True if the option is configured correctly, False otherwise.
+        bool: True if the option is configured correctly, False otherwise.
     """
     suppresscc = command.output_one_line(
         'git', 'config', 'sendemail.suppresscc', raise_on_error=False)
 
     # Other settings should be fine.
-    if suppresscc == 'all' or suppresscc == 'cccmd':
+    if suppresscc in ('all', 'cccmd'):
         col = terminal.Color()
 
-        print((col.build(col.RED, "error") +
-               ": git config sendemail.suppresscc set to %s\n"
-               % (suppresscc)) +
-              "  patman needs --cc-cmd to be run to set the cc list.\n" +
-              "  Please run:\n" +
-              "    git config --unset sendemail.suppresscc\n" +
-              "  Or read the man page:\n" +
-              "    git send-email --help\n" +
-              "  and set an option that runs --cc-cmd\n")
+        print(col.build(col.RED, 'error') +
+              f': git config sendemail.suppresscc set to {suppresscc}\n' +
+              '  patman needs --cc-cmd to be run to set the cc list.\n' +
+              '  Please run:\n' +
+              '    git config --unset sendemail.suppresscc\n' +
+              '  Or read the man page:\n' +
+              '    git send-email --help\n' +
+              '  and set an option that runs --cc-cmd\n')
         return False
 
     return True
@@ -432,24 +438,26 @@ def check_suppress_cc_config():
 
 def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname,
                   self_only=False, alias=None, in_reply_to=None, thread=False,
-                  smtp_server=None, get_maintainer_script=None):
+                  smtp_server=None):
     """Email a patch series.
 
     Args:
-        series: Series object containing destination info
-        cover_fname: filename of cover letter
-        args: list of filenames of patch files
-        dry_run: Just return the command that would be run
-        warn_on_error: True to print a warning when an alias fails to match,
-                False to ignore it.
-        cc_fname: Filename of Cc file for per-commit Cc
-        self_only: True to just email to yourself as a test
-        in_reply_to: If set we'll pass this to git as --in-reply-to.
-            Should be a message ID that this is in reply to.
-        thread: True to add --thread to git send-email (make
+        series (Series): Series object containing destination info
+        cover_fname (str or None): filename of cover letter
+        args (list of str): list of filenames of patch files
+        dry_run (bool): Just return the command that would be run
+        warn_on_error (bool): True to print a warning when an alias fails to
+            match, False to ignore it.
+        cc_fname (str): Filename of Cc file for per-commit Cc
+        self_only (bool): True to just email to yourself as a test
+        alias (dict or None): Alias dictionary: (None to use settings default)
+            key: alias
+            value: list of aliases or email addresses
+        in_reply_to (str or None): If set we'll pass this to git as
+            --in-reply-to - should be a message ID that this is in reply to.
+        thread (bool): True to add --thread to git send-email (make
             all patches reply to cover-letter or first patch in series)
-        smtp_server: SMTP server to use to send patches
-        get_maintainer_script: File name of script to get maintainers emails
+        smtp_server (str or None): SMTP server to use to send patches
 
     Returns:
         Git command that was/would be run
@@ -500,7 +508,7 @@ send --cc-cmd cc-fname" cover p1 p2'
                   "Series-to: Fred Bloggs <f.blogs@napier.co.nz>\n"
                   "Or do something like this\n"
                   "git config sendemail.to u-boot@lists.denx.de")
-            return
+            return None
     cc = build_email_list(list(set(series.get('cc')) - set(series.get('to'))),
                           '--cc', alias, warn_on_error)
     if self_only:
@@ -509,15 +517,15 @@ send --cc-cmd cc-fname" cover p1 p2'
         cc = []
     cmd = ['git', 'send-email', '--annotate']
     if smtp_server:
-        cmd.append('--smtp-server=%s' % smtp_server)
+        cmd.append(f'--smtp-server={smtp_server}')
     if in_reply_to:
-        cmd.append('--in-reply-to="%s"' % in_reply_to)
+        cmd.append(f'--in-reply-to="{in_reply_to}"')
     if thread:
         cmd.append('--thread')
 
     cmd += to
     cmd += cc
-    cmd += ['--cc-cmd', '"%s send --cc-cmd %s"' % (sys.argv[0], cc_fname)]
+    cmd += ['--cc-cmd', f'"{sys.argv[0]} send --cc-cmd {cc_fname}"']
     if cover_fname:
         cmd.append(cover_fname)
     cmd += args
@@ -533,10 +541,13 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0):
     TODO: Why not just use git's own alias feature?
 
     Args:
-        lookup_name: Alias or email address to look up
-        alias: Dictionary containing aliases (None to use settings default)
-        warn_on_error: True to print a warning when an alias fails to match,
-                False to ignore it.
+        lookup_name (str): Alias or email address to look up
+        alias (dict or None): Alias dictionary: (None to use settings default)
+            key: alias
+            value: list of aliases or email addresses
+        warn_on_error (bool): True to print a warning when an alias fails to
+            match, False to ignore it.
+        level (int): Depth of alias stack, used to detect recusion/loops
 
     Returns:
         tuple:
@@ -589,16 +600,15 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0):
 
     out_list = []
     if level > 10:
-        msg = "Recursive email alias at '%s'" % lookup_name
+        msg = f"Recursive email alias at '{lookup_name}'"
         if warn_on_error:
             raise OSError(msg)
-        else:
-            print(col.build(col.RED, msg))
-            return out_list
+        print(col.build(col.RED, msg))
+        return out_list
 
     if lookup_name:
         if lookup_name not in alias:
-            msg = "Alias '%s' not found" % lookup_name
+            msg = f"Alias '{lookup_name}' not found"
             if warn_on_error:
                 print(col.build(col.RED, msg))
             return out_list
@@ -615,7 +625,7 @@ def get_top_level():
     """Return name of top-level directory for this git repo.
 
     Returns:
-        Full path to git top-level directory
+        str: Full path to git top-level directory
 
     This test makes sure that we are running tests in the right subdir
 
@@ -630,7 +640,7 @@ def get_alias_file():
     """Gets the name of the git alias file.
 
     Returns:
-        Filename of git alias file, or None if none
+        str: Filename of git alias file, or None if none
     """
     fname = command.output_one_line('git', 'config', 'sendemail.aliasesfile',
                                     raise_on_error=False)
@@ -650,7 +660,8 @@ def get_default_user_name():
     Returns:
         User name found in .gitconfig file, or None if none
     """
-    uname = command.output_one_line('git', 'config', '--global', '--includes', 'user.name')
+    uname = command.output_one_line('git', 'config', '--global', '--includes',
+                                    'user.name')
     return uname
 
 
@@ -660,7 +671,8 @@ def get_default_user_email():
     Returns:
         User's email found in .gitconfig file, or None if none
     """
-    uemail = command.output_one_line('git', 'config', '--global', '--includes', 'user.email')
+    uemail = command.output_one_line('git', 'config', '--global', '--includes',
+                                     'user.email')
     return uemail
 
 
@@ -677,15 +689,15 @@ def get_default_subject_prefix():
 
 
 def setup():
-    """Set up git utils, by reading the alias files."""
+    """setup() - Set up git utils, by reading the alias files."""
     # Check for a git alias file also
-    global use_no_decorate
+    global USE_NO_DECORATE
 
     alias_fname = get_alias_file()
     if alias_fname:
         settings.ReadGitAliases(alias_fname)
     cmd = log_cmd(None, count=0)
-    use_no_decorate = (command.run_one(*cmd, raise_on_error=False)
+    USE_NO_DECORATE = (command.run_one(*cmd, raise_on_error=False)
                        .return_code == 0)