diff options
170 files changed, 7380 insertions, 1271 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b7780de776b..bd5887bf750 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -125,6 +125,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ rk3328-nanopi-r2c.dtb \ rk3328-nanopi-r2s.dtb \ + rk3328-orangepi-r1-plus.dtb \ + rk3328-orangepi-r1-plus-lts.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb @@ -159,6 +161,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-4c-plus.dtb \ + rk3399-rock-4se.dtb \ rk3399-rock-pi-4a.dtb \ rk3399-rock-pi-4c.dtb \ rk3399-rock960.dtb \ @@ -169,10 +172,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-anbernic-rgxx3.dtb \ rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb \ + rk3568-nanopi-r5c.dtb \ + rk3568-nanopi-r5s.dtb \ + rk3568-odroid-m1.dtb \ rk3568-rock-3a.dtb dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ + rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ rk3588-rock-5b.dtb diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 4a42f1b2e31..2488e3a537f 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -54,6 +54,12 @@ reg = <0x4044 0x8>; #phy-cells = <1>; }; + + epwm_tbclk: clock@4130 { + compatible = "ti,am62-epwm-tbclk", "syscon"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; dmss: bus@48000000 { @@ -144,8 +150,8 @@ compatible = "ti,k2g-sci"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; reg-names = "debug_messages"; reg = <0x00 0x44043000 0x00 0xfe0>; @@ -178,6 +184,21 @@ dma-names = "tx", "rx1", "rx2"; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -186,6 +207,108 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -193,6 +316,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -202,6 +326,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -211,6 +336,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -220,6 +346,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -229,6 +356,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -238,6 +366,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -247,6 +376,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -258,6 +388,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -269,6 +400,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -280,6 +412,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -291,6 +424,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -300,7 +434,8 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 172 0>; + clocks = <&k3_clks 141 0>; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -310,7 +445,8 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 173 0>; + clocks = <&k3_clks 142 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -320,7 +456,8 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 174 0>; + clocks = <&k3_clks 143 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { @@ -345,7 +482,7 @@ <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <87>; + ti,ngpio = <92>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; @@ -362,7 +499,7 @@ <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <88>; + ti,ngpio = <52>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; @@ -385,8 +522,11 @@ ti,clkbuf-sel = <0x7>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x9>; - ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-mmc-hs = <0x1>; + status = "disabled"; }; sdhci1: mmc@fa00000 { @@ -397,19 +537,20 @@ clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x4>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; bus-width = <4>; + status = "disabled"; }; sdhci2: mmc@fa20000 { @@ -420,18 +561,65 @@ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; ti,trm-icp = <0x2>; - ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-legacy = <0x8>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x6>; - ti,otap-del-sel-ddr50 = <0x9>; - ti,itap-del-sel-legacy = <0x0>; - ti,itap-del-sel-sd-hs = <0x0>; - ti,itap-del-sel-sdr12 = <0x0>; - ti,itap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x8>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0xa>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; ti,clkbuf-sel = <0x7>; + status = "disabled"; + }; + + usbss0: dwc3-usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31000000 0x00 0x50000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg =<0x00 0x31100000 0x00 0x50000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; }; fss: bus@fc00000 { @@ -456,6 +644,7 @@ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -514,12 +703,13 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { compatible = "ti,j721e-cpts"; reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 13 1>; + clocks = <&k3_clks 13 3>; clock-names = "cpts"; interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; @@ -551,6 +741,7 @@ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -560,6 +751,7 @@ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -569,6 +761,7 @@ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; }; main_mcan0: can@20701000 { @@ -583,5 +776,141 @@ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; + }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23000000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23010000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x23020000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; }; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi index f56c803560f..19fc38157d9 100644 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -14,6 +14,57 @@ pinctrl-single,function-mask = <0xffffffff>; }; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + }; + + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -21,6 +72,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -32,6 +84,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -42,6 +95,7 @@ #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -52,6 +106,7 @@ #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { @@ -81,4 +136,15 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; }; diff --git a/arch/arm/dts/k3-am62-thermal.dtsi b/arch/arm/dts/k3-am62-thermal.dtsi new file mode 100644 index 00000000000..a358757e26f --- /dev/null +++ b/arch/arm/dts/k3-am62-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/thermal/thermal.h> + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi index 4090134676c..eae05288718 100644 --- a/arch/arm/dts/k3-am62-wakeup.dtsi +++ b/arch/arm/dts/k3-am62-wakeup.dtsi @@ -26,16 +26,47 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "fclk"; + status = "disabled"; }; wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 4>; clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; }; }; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index 37fcbe7a3c3..5e72c445f37 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -8,9 +8,10 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM625 SoC"; compatible = "ti,am625"; @@ -80,6 +81,7 @@ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; @@ -90,14 +92,17 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; - cbass_wakeup: bus@2b000000 { + cbass_wakeup: bus@b00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; }; }; + + #include "k3-am62-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 3ec5bad7350..bf219226b97 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -9,7 +9,6 @@ #include "k3-am62-ddr.dtsi" #include "k3-am625-sk-u-boot.dtsi" -#include "k3-am625-sk-binman.dtsi" / { aliases { @@ -19,31 +18,6 @@ serial3 = &main_uart1; }; - chosen { - stdout-path = "serial2:115200n8"; - tick-timer = &timer1; - }; - - memory@80000000 { - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - - bootph-pre-ram; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - }; - a53_0: a53@0 { compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; @@ -81,80 +55,44 @@ ti,secure-host; }; -&cbass_mcu { - mcu_esm: esm@4100000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x4100000 0x0 0x1000>; - ti,esm-pins = <0>, <1>, <2>, <85>; - bootph-pre-ram; - }; +&mcu_esm { + bootph-pre-ram; }; -&cbass_main { - sa3_secproxy: secproxy@44880000 { - bootph-pre-ram; - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "rt", "scfg", "target_data"; - reg = <0x00 0x44880000 0x00 0x20000>, - <0x0 0x44860000 0x0 0x20000>, - <0x0 0x43600000 0x0 0x10000>; - }; +&secure_proxy_sa3 { + bootph-pre-ram; + /* We require this for boot handshake */ + status = "okay"; +}; + +&main_esm { + bootph-pre-ram; +}; +&cbass_main { sysctrler: sysctrler { compatible = "ti,am654-system-controller"; - mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; }; - - main_esm: esm@420000 { - compatible = "ti,j721e-esm"; - reg = <0x0 0x420000 0x0 0x1000>; - ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; - bootph-pre-ram; - }; }; -&mcu_pmx0 { +&wkup_uart0_pins_default { bootph-pre-ram; - wkup_uart0_pins_default: wkup-uart0-pins-default { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ - AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ - AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ - AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ - >; - bootph-pre-ram; - }; }; -&main_pmx0 { +&main_uart1_pins_default { bootph-pre-ram; - main_uart1_pins_default: main-uart1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ - AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ - AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ - AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ - >; - bootph-pre-ram; - }; }; /* WKUP UART0 is used for DM firmware logs */ &wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; - status = "okay"; bootph-pre-ram; }; /* Main UART1 is used for TIFS firmware logs */ &main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart1_pins_default>; - status = "okay"; bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index a60c37f1dbf..c1685bc9ca3 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -9,7 +9,7 @@ / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &timer1; + tick-timer = &main_timer0; }; aliases { @@ -21,16 +21,13 @@ }; }; -&cbass_main{ +&cbass_main { bootph-pre-ram; +}; - timer1: timer@2400000 { - compatible = "ti,omap5430-timer"; - reg = <0x00 0x2400000 0x00 0x80>; - ti,timer-alwon; - clock-frequency = <25000000>; - bootph-pre-ram; - }; +&main_timer0 { + clock-frequency = <25000000>; + bootph-pre-ram; }; &dmss { @@ -77,10 +74,6 @@ bootph-pre-ram; }; -&main_uart1 { - bootph-pre-ram; -}; - &cbass_mcu { bootph-pre-ram; }; @@ -93,10 +86,6 @@ bootph-pre-ram; }; -&wkup_uart0 { - bootph-pre-ram; -}; - &sdhci1 { bootph-pre-ram; }; @@ -130,17 +119,7 @@ }; &cpsw3g { - reg = <0x0 0x8000000 0x0 0x200000>, - <0x0 0x43000200 0x0 0x8>; - reg-names = "cpsw_nuss", "mac_efuse"; - /delete-property/ ranges; bootph-pre-ram; - - cpsw-phy-sel@04044 { - compatible = "ti,am64-phy-gmii-sel"; - reg = <0x0 0x00104044 0x0 0x8>; - bootph-pre-ram; - }; }; &cpsw_port1 { diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index af5617ff44d..3f9ef4053aa 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -7,28 +7,19 @@ /dts-v1/; -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "k3-am625.dtsi" +#include "k3-am62x-sk-common.dtsi" / { - compatible = "ti,am625-sk", "ti,am625"; + compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; - aliases { - serial2 = &main_uart0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - spi0 = &ospi0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; }; memory@80000000 { @@ -38,39 +29,6 @@ }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@9ca00000 { - compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x00>; - pmsg-size = <0x8000>; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; - vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; @@ -130,108 +88,20 @@ <3300000 0x1>; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pins_default>; - - led-0 { - label = "am62-sk:green:heartbeat"; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; }; }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ - AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ - AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_mmc0_pins_default: main-mmc0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ - AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ - >; - }; - - usr_led_pins_default: usr-led-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ - >; - }; - - main_mdio1_pins_default: main-mdio1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ - >; - }; - - main_rgmii1_pins_default: main-rgmii1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; - }; - - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -248,7 +118,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -264,77 +134,20 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; }; -&wkup_uart0 { - /* WKUP UART0 is used by DM firmware */ - status = "reserved"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - /* Main UART1 is used by TIFS firmware */ - status = "reserved"; -}; - -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; - -&wkup_i2c0 { - status = "disabled"; -}; - -&main_i2c0 { - status = "disabled"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; -}; - &main_i2c1 { - status = "disabled"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - exp1: gpio@22 { compatible = "ti,tca6424"; reg = <0x22>; @@ -348,7 +161,7 @@ "UART1_FET_BUF_EN", "WL_LT_EN", "GPIO_HDMI_RSTn", "CSI_GPIO1", "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "TEST_GPIO2", + "HDMI_INTn", "PD_I2C_IRQ", "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "TSINT#", "IO_EXP_TEST_LED"; @@ -363,41 +176,14 @@ }; }; -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - &sdhci1 { - /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; }; &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default - &main_rgmii1_pins_default - &main_rgmii2_pins_default>; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; &cpsw_port2 { @@ -406,13 +192,6 @@ }; &cpsw3g_mdio { - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,min-output-impedance; - }; - cpsw3g_phy1: ethernet-phy@1 { reg = <1>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; @@ -429,6 +208,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -487,18 +267,6 @@ }; }; -&ecap0 { - status = "disabled"; -}; - -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; +&tlv320aic3106 { + DVDD-supply = <&vcc_1v8>; }; diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi index 887f31c23fe..4193c2b3eed 100644 --- a/arch/arm/dts/k3-am625.dtsi +++ b/arch/arm/dts/k3-am625.dtsi @@ -48,6 +48,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,13 +96,59 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi new file mode 100644 index 00000000000..34c8ffc553e --- /dev/null +++ b/arch/arm/dts/k3-am62x-sk-common.dtsi @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for AM62x SK and derivatives + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "k3-am625.dtsi" + +/ { + aliases { + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; +}; + +&main_pmx0 { + /* First pad number is ALW package and second is AMC package */ + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ + >; + }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ + >; + }; + + main_mcasp1_pins_default: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + >; + }; +}; + +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + usb-role-switch; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index 7bfa4eebb90..3ecb461b011 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) Siemens AG, 2020-2022 + * Copyright (c) Siemens AG, 2020-2023 * * Authors: * Jan Kiszka <jan.kiszka@siemens.com> @@ -10,23 +10,23 @@ #include <config.h> / { - binman { - filename = "flash.bin"; + binman: binman { + multiple-images; + }; +}; + +&binman { + common_part: template { pad-byte = <0xff>; size = <0x8c0000>; allow-repack; - blob-ext@0x000000 { + blob-ext@0 { offset = <0x000000>; -#ifdef CONFIG_TARGET_IOT2050_A53_PG1 - filename = "seboot_pg1.bin"; -#else - filename = "seboot_pg2.bin"; -#endif missing-msg = "iot2050-seboot"; }; - fit@0x180000 { + fit@180000 { offset = <0x180000>; filename = "tispl.bin"; pad-byte = <0xff>; @@ -104,9 +104,8 @@ }; }; - fit@0x380000 { + fit@380000 { description = "U-Boot for IOT2050"; - fit,fdt-list = "of-list"; offset = <0x380000>; images { u-boot { @@ -134,36 +133,6 @@ }; }; -#ifdef CONFIG_TARGET_IOT2050_A53_PG2 - bkey-usb3-overlay { - description = "M.2-bkey-usb3-overlay"; - type = "blob"; - load = <0x82100000>; - arch = "arm64"; - compression = "none"; - blob-ext { - filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo"; - }; - hash { - algo = "sha256"; - }; - }; - - bkey-ekey-pcie-overlay { - description = "M.2-bkey-ekey-pcie-overlay"; - type = "blob"; - load = <0x82110000>; - arch = "arm64"; - compression = "none"; - blob-ext { - filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo"; - }; - hash { - algo = "sha256"; - }; - }; -#endif - #ifdef CONFIG_WDT_K3_RTI_FW_FILE k3-rti-wdt-firmware { type = "firmware"; @@ -182,20 +151,10 @@ }; configurations { - default = "@config-DEFAULT-SEQ"; @config-SEQ { description = "NAME"; firmware = "u-boot"; fdt = "fdt-SEQ"; - loadables = -#ifdef CONFIG_TARGET_IOT2050_A53_PG2 - "bkey-usb3-overlay", - "bkey-ekey-pcie-overlay", -#endif -#ifdef CONFIG_WDT_K3_RTI_FW_FILE - "k3-rti-wdt-firmware", -#endif - <>; signature { sign-images = "firmware", "fdt", "loadables"; }; @@ -207,32 +166,112 @@ }; /* primary env */ - fill@0x680000 { + fill@680000 { offset = <0x680000>; size = <0x020000>; fill-byte = [00]; }; /* secondary env */ - fill@0x6a0000 { + fill@6a0000 { offset = <0x6a0000>; size = <0x020000>; fill-byte = [00]; }; - /* OTP update command block */ -#if CONFIG_IOT2050_EMBED_OTPCMD - blob-ext@0x6c0000 { +/* OTP update command block */ +#ifdef CONFIG_IOT2050_EMBED_OTPCMD + blob-ext@6c0000 { offset = <0x6c0000>; + size = <0x010000>; filename = "otpcmd.bin"; missing-msg = "iot2050-otpcmd"; }; #else - fill@0x6c0000 { + fill@6c0000 { offset = <0x6c0000>; size = <0x010000>; fill-byte = [ff]; }; #endif }; + + flash-pg1 { + filename = "flash-pg1.bin"; + insert-template = <&common_part>; + + blob-ext@0 { + filename = "seboot_pg1.bin"; + }; + + fit@380000 { + fit,fdt-list-val = "k3-am6528-iot2050-basic", "k3-am6548-iot2050-advanced"; + + configurations { + default = "k3-am6528-iot2050-basic"; + @config-SEQ { + loadables = +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + "k3-rti-wdt-firmware", +#endif + <>; + }; + }; + }; + }; + + flash-pg2 { + filename = "flash-pg2.bin"; + insert-template = <&common_part>; + + blob-ext@0 { + filename = "seboot_pg2.bin"; + }; + + fit@380000 { + fit,fdt-list-val = "k3-am6528-iot2050-basic-pg2", "k3-am6548-iot2050-advanced-pg2", "k3-am6548-iot2050-advanced-m2"; + + images { + bkey-usb3-overlay { + description = "M.2-bkey-usb3-overlay"; + type = "blob"; + load = <0x82100000>; + arch = "arm64"; + compression = "none"; + blob-ext { + filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo"; + }; + hash { + algo = "sha256"; + }; + }; + + bkey-ekey-pcie-overlay { + description = "M.2-bkey-ekey-pcie-overlay"; + type = "blob"; + load = <0x82110000>; + arch = "arm64"; + compression = "none"; + blob-ext { + filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo"; + }; + hash { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "k3-am6528-iot2050-basic-pg2"; + @config-SEQ { + loadables = +#ifdef CONFIG_WDT_K3_RTI_FW_FILE + "k3-rti-wdt-firmware", +#endif + "bkey-usb3-overlay", + "bkey-ekey-pcie-overlay"; + }; + }; + }; + }; }; diff --git a/arch/arm/dts/k3-pinctrl.h b/arch/arm/dts/k3-pinctrl.h new file mode 100644 index 00000000000..c97548a3f42 --- /dev/null +++ b/arch/arm/dts/k3-pinctrl.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef DTS_ARM64_TI_K3_PINCTRL_H +#define DTS_ARM64_TI_K3_PINCTRL_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 19206988845..c4c5a2d225c 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "rockchip-u-boot.dtsi" -#include "rockchip-optee.dtsi" / { aliases { diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi new file mode 100644 index 00000000000..ebe33e48cb9 --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-lpddr3-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + bootph-pre-ram; +}; + +&gmac2io { + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +}; + +&spi0 { + spi_flash: spiflash@0 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts new file mode 100644 index 00000000000..5d7d567283e --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Xunlong Software. Co., Ltd. + * (http://www.orangepi.org) + * + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include "rk3328-orangepi-r1-plus.dts" + +/ { + model = "Xunlong Orange Pi R1 Plus LTS"; + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; +}; + +&gmac2io { + phy-handle = <&yt8531c>; + tx_delay = <0x19>; + rx_delay = <0x05>; + + mdio { + /delete-node/ ethernet-phy@1; + + yt8531c: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <15000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi new file mode 100644 index 00000000000..637c70adf19 --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + bootph-pre-ram; +}; + +&pinctrl { + bootph-pre-ram; +}; + +&sdmmc0m1_pin { + bootph-pre-ram; +}; + +&pcfg_pull_up_4ma { + bootph-pre-ram; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + bootph-pre-ram; +}; + +&gmac2io { + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +}; + +&spi0 { + spi_flash: spiflash@0 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts new file mode 100644 index 00000000000..dc83d74045a --- /dev/null +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Based on rk3328-nanopi-r2s.dts, which is: + * Copyright (c) 2020 David Bauer <mail@david-bauer.net> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "rk3328.dtsi" + +/ { + model = "Xunlong Orange Pi R1 Plus"; + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; + + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_5v_lan: vdd-5v-lan-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lan_vdd_pin>; + pinctrl-names = "default"; + regulator-name = "vdd_5v_lan"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + snps,aal; + rx_delay = <0x18>; + tx_delay = <0x24>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + gmac2io { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lan { + lan_vdd_pin: lan-vdd-pin { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd3 { + dr_mode = "host"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /* Second port is for USB 3.0 */ + rtl8153: device@2 { + compatible = "usbbda,8153"; + reg = <2>; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts index 028eb508ae3..8bfd5f88d1e 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -548,9 +548,8 @@ &sdhci { max-frequency = <150000000>; bus-width = <8>; - mmc-hs400-1_8v; + mmc-hs200-1_8v; non-removable; - mmc-hs400-enhanced-strobe; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi new file mode 100644 index 00000000000..85ee5770add --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "rk3399-rock-pi-4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rock-4se.dts b/arch/arm/dts/rk3399-rock-4se.dts new file mode 100644 index 00000000000..7cfc198bbae --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4se.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com> + * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com> + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" +#include "rk3399-t-opp.dtsi" + +/ { + model = "Radxa ROCK 4SE"; + compatible = "radxa,rock-4se", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; +}; + +&pinctrl { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&vcc5v0_host { + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index 907071d4fe8..b1b7f4ffb1d 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -9,7 +9,6 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" -#include "rk3399-opp.dtsi" / { aliases { @@ -645,9 +644,9 @@ }; &sdhci { + max-frequency = <150000000>; bus-width = <8>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; non-removable; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts b/arch/arm/dts/rk3399-rock-pi-4a.dts index 89f2af5e111..931334aa3d6 100644 --- a/arch/arm/dts/rk3399-rock-pi-4a.dts +++ b/arch/arm/dts/rk3399-rock-pi-4a.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4A"; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index 4053ba72618..d32efab74e9 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4C"; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index a18e5d1cf75..f986e1941e7 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -46,7 +46,17 @@ <&pmucru CLK_RTC32K_FRAC>; }; +&dsi_dphy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + &i2c2 { + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi new file mode 100644 index 00000000000..fe5bc6af476 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk3568-nanopi-r5s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568-nanopi-r5c.dts b/arch/arm/dts/rk3568-nanopi-r5c.dts new file mode 100644 index 00000000000..f70ca9f0470 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5c.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = <KEY_RESTART>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; + + led-lan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-wlan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led_pin: wlan-led-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_reset_pin: pcie20-reset-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi new file mode 100644 index 00000000000..0ecca85b206 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; + }; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&uart2 { + clock-frequency = <24000000>; + bootph-all; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dts b/arch/arm/dts/rk3568-nanopi-r5s.dts new file mode 100644 index 00000000000..b6ad8328c7e --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pcie2x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + lan1_led_pin: lan1-led-pin { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi new file mode 100644 index 00000000000..58ba328ea78 --- /dev/null +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vdd_usbc: vdd-usbc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi new file mode 100644 index 00000000000..0fc360b06df --- /dev/null +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&fspi_dual_io_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts new file mode 100644 index 00000000000..59ecf868dbd --- /dev/null +++ b/arch/arm/dts/rk3568-odroid-m1.dts @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Hardkernel ODROID-M1"; + compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + i2c0 = &i2c3; + i2c3 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + serial0 = &uart1; + serial1 = &uart0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + + leds { + compatible = "gpio-leds"; + + led_power: led-0 { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + default-state = "keep"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&led_power_pin>; + }; + led_work: led-1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_pin>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_pin>; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&combphy1 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + /* external pullup to VCC3V3_SYS */ + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_work_pin: led-work-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk809 { + hp_det_pin: hp-det-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sfc { + /* Dual I/O mode as the D2 pin conflicts with the eMMC */ + pinctrl-0 = <&fspi_dual_io_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0xe0000>; + }; + partition@e0000 { + label = "U-Boot Env"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { + label = "U-Boot"; + reg = <0x100000 0x200000>; + }; + partition@300000 { + label = "splash"; + reg = <0x300000 0x100000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index bbf54f888fa..9ee7b494ee2 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -36,8 +36,22 @@ bootph-all; }; +&pcie2x1 { + pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>; +}; + +&pcie3x2 { + pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>; +}; + &pinctrl { bootph-all; + + pcie { + pcie3x2_reset_h: pcie3x2-reset-h { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pcfg_pull_none { diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi index ba67b58f05b..f1be76a54ce 100644 --- a/arch/arm/dts/rk3568.dtsi +++ b/arch/arm/dts/rk3568.dtsi @@ -94,9 +94,10 @@ power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0400000 0x0 0x00400000>, <0x0 0xfe270000 0x0 0x00010000>, - <0x3 0x7f000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; + <0x0 0xf2000000 0x0 0x00100000>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -146,9 +147,10 @@ power-domains = <&power RK3568_PD_PIPE>; reg = <0x3 0xc0800000 0x0 0x00400000>, <0x0 0xfe280000 0x0 0x00010000>, - <0x3 0xbf000000 0x0 0x01000000>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, - <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; + <0x0 0xf0000000 0x0 0x00100000>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index 6492ace0de6..e0591c194be 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -951,7 +951,7 @@ compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0000000 0x0 0x00400000>, <0x0 0xfe260000 0x0 0x00010000>, - <0x3 0x3f000000 0x0 0x01000000>; + <0x0 0xf4000000 0x0 0x00100000>; reg-names = "dbi", "apb", "config"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, @@ -980,8 +980,9 @@ phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 - 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, + <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi new file mode 100644 index 00000000000..cd7626b24b6 --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rk3588j-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = &sdmmc; + }; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts new file mode 100644 index 00000000000..e9d5a8bab58 --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588j.dtsi" +#include "rk3588-edgeble-neu6b.dtsi" + +/ { + model = "Edgeble Neu6B IO Board"; + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi new file mode 100644 index 00000000000..1c5bcf1280b --- /dev/null +++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1cd8a57a6fa..5a329269964 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/usb/pd.h> / { aliases { @@ -18,6 +19,25 @@ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -29,6 +49,28 @@ pinctrl-0 = <&vcc5v0_host_en>; vin-supply = <&vcc5v0_sys>; }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; }; &combphy0_ps { @@ -85,6 +127,16 @@ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pcfg_pull_none { @@ -168,6 +220,15 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + &u2phy2 { resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; reset-names = "phy", "apb"; @@ -209,3 +270,139 @@ status = "okay"; }; +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 95805cb0adf..3e4aee8f70c 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -2,6 +2,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "rk3588.dtsi" / { @@ -17,6 +18,31 @@ stdout-path = "serial2:1500000n8"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + sound { + compatible = "audio-graph-card"; + label = "Analog"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -27,6 +53,132 @@ }; }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 4c8ac804d61..68b419f3abd 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -5,3 +5,96 @@ #include "rockchip-u-boot.dtsi" #include "rk3588s-u-boot.dtsi" + +/ { + usbdrd3_1: usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + }; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index d085e57fbc4..8be75556af8 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" / { + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/arch/arm/dts/rk3588j-u-boot.dtsi b/arch/arm/dts/rk3588j-u-boot.dtsi new file mode 100644 index 00000000000..f5c9e329a50 --- /dev/null +++ b/arch/arm/dts/rk3588j-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rk3588-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588j.dtsi b/arch/arm/dts/rk3588j.dtsi new file mode 100644 index 00000000000..38b9dbf38a2 --- /dev/null +++ b/arch/arm/dts/rk3588j.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c703e41802b..acb1cfe2006 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -13,6 +13,37 @@ status = "okay"; }; + usbdrd3_0: usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + quirk-skip-phy-init; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -64,6 +95,33 @@ reg = <0x0 0xfd5bc000 0x0 0x100>; }; + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -87,6 +145,17 @@ }; }; + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + usb2phy3_grf: syscon@fd5dc000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -110,6 +179,11 @@ }; }; + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + pcie2x1l2: pcie@fe190000 { compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; #address-cells = <3>; @@ -174,24 +248,43 @@ status = "disabled"; }; - otp: nvmem@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - cpu_id: id@7 { - reg = <0x07 0x10>; - }; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; status = "disabled"; }; + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index fca8503aed8..7dbac9ae2e1 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -60,6 +60,8 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -136,6 +138,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -174,6 +178,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -222,6 +228,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -230,6 +238,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -238,6 +248,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -246,6 +258,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -254,6 +268,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -262,6 +278,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -270,6 +288,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -278,6 +298,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>; + cache-level = <2>; + cache-unified; next-level-cache = <&l3_cache>; }; @@ -286,6 +308,8 @@ cache-size = <3145728>; cache-line-size = <64>; cache-sets = <4096>; + cache-level = <3>; + cache-unified; }; }; @@ -304,10 +328,6 @@ scmi_clk: protocol@14 { reg = <0x14>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, - <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <1200000000>, - <1200000000>; #clock-cells = <1>; }; @@ -414,7 +434,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, @@ -1132,6 +1152,103 @@ status = "disabled"; }; + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ @@ -1141,7 +1258,24 @@ mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; + ranges; + #address-cells = <2>; #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; ppi-partitions { ppi_partition0: interrupt-partition-0 { @@ -1241,6 +1375,22 @@ status = "disabled"; }; + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; + }; + spi0: spi@feb00000 { compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; reg = <0x0 0xfeb00000 0x0 0x1000>; @@ -1572,6 +1722,26 @@ status = "disabled"; }; + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1627,6 +1797,60 @@ status = "disabled"; }; + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>; diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi deleted file mode 100644 index d84c10cf436..00000000000 --- a/arch/arm/dts/rockchip-optee.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Google LLC - */ - -#include <config.h> - -#if defined(CONFIG_HAS_ROM) && defined(CONFIG_FIT) -&binman { - itb { - filename = "u-boot.itb"; - fit { - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; - description = "FIT image with OP-TEE support"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot"; - type = "standalone"; - os = "U-Boot"; - arch = "arm"; - compression = "none"; - load = <CONFIG_TEXT_BASE>; - - u-boot-nodtb { - }; - }; - optee { - description = "OP-TEE"; - type = "firmware"; - arch = "arm"; - os = "tee"; - compression = "none"; - load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - - blob-ext { - filename = "tee.bin"; - }; - }; - fdt { - description = CONFIG_SYS_BOARD; - type = "flat_dt"; - compression = "none"; - - u-boot-dtb { - }; - }; - }; - - configurations { - default = "conf"; - conf { - description = CONFIG_SYS_BOARD; - firmware = "optee"; - loadables = "uboot"; - fdt = "fdt"; - }; - }; - }; - }; -}; -#endif diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index 2878b80926c..be2658e8ef1 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -33,9 +33,13 @@ }; }; -#if defined(CONFIG_SPL_FIT) && defined(CONFIG_ARM64) +#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) fit: fit { +#ifdef CONFIG_ARM64 description = "FIT image for U-Boot with bl31 (TF-A)"; +#else + description = "FIT image with OP-TEE"; +#endif #address-cells = <1>; fit,fdt-list = "of-list"; filename = "u-boot.itb"; @@ -44,10 +48,14 @@ offset = <CONFIG_SPL_PAD_TO>; images { u-boot { - description = "U-Boot (64-bit)"; + description = "U-Boot"; type = "standalone"; os = "U-Boot"; +#ifdef CONFIG_ARM64 arch = "arm64"; +#else + arch = "arm"; +#endif compression = "none"; load = <CONFIG_TEXT_BASE>; entry = <CONFIG_TEXT_BASE>; @@ -60,6 +68,7 @@ #endif }; +#ifdef CONFIG_ARM64 @atf-SEQ { fit,operation = "split-elf"; description = "ARM Trusted Firmware"; @@ -99,6 +108,25 @@ }; #endif }; +#else + op-tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm"; + os = "tee"; + compression = "none"; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + + tee-os { + }; +#ifdef CONFIG_SPL_FIT_SIGNATURE + hash { + algo = "sha256"; + }; +#endif + }; +#endif @fdt-SEQ { description = "fdt-NAME"; @@ -117,7 +145,11 @@ @config-SEQ { description = "NAME.dtb"; fdt = "fdt-SEQ"; +#ifdef CONFIG_ARM64 fit,firmware = "atf-1", "u-boot"; +#else + fit,firmware = "op-tee", "u-boot"; +#endif fit,loadables; }; }; @@ -150,7 +182,7 @@ }; }; -#ifdef CONFIG_ARM64 +#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE) fit { type = "blob"; filename = "u-boot.itb"; diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c index 1a6f9e2ca03..59c95df2a88 100644 --- a/arch/arm/mach-k3/am62x/dev-data.c +++ b/arch/arm/mach-k3/am62x/dev-data.c @@ -58,6 +58,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(161, &soc_lpsc_list[8]), PSC_DEV(162, &soc_lpsc_list[9]), PSC_DEV(75, &soc_lpsc_list[10]), + PSC_DEV(36, &soc_lpsc_list[11]), PSC_DEV(102, &soc_lpsc_list[11]), PSC_DEV(146, &soc_lpsc_list[11]), PSC_DEV(13, &soc_lpsc_list[12]), diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 9478f605441..645c4de42f7 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -7,6 +7,7 @@ #include <dm.h> #include <fdt_support.h> #include <linux/soc/ti/ti_sci_protocol.h> +#include "common_fdt.h" static int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name) { diff --git a/arch/arm/mach-k3/common_fdt.h b/arch/arm/mach-k3/common_fdt.h index 46c3dc5e119..4d23ae638ca 100644 --- a/arch/arm/mach-k3/common_fdt.h +++ b/arch/arm/mach-k3/common_fdt.h @@ -7,5 +7,6 @@ #define _COMMON_FDT_H int fdt_fixup_msmc_ram_k3(void *blob); +int fdt_del_node_path(void *blob, const char *path); #endif /* _COMMON_FDT_H */ diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 6038c9665ec..89659f479ee 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -67,14 +67,6 @@ void ti_secure_image_check_binary(void **p_image, size_t *p_size) return; } - - if (get_device_type() != K3_DEVICE_TYPE_HS_SE && - !ti_secure_cert_detected(*p_image)) { - printf("Warning: Did not detect image signing certificate. " - "Skipping authentication to prevent boot failure. " - "This will fail on Security Enforcing(HS-SE) devices\n"); - return; - } } void ti_secure_image_post_process(void **p_image, size_t *p_size) @@ -91,11 +83,17 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) return; } - if (get_device_type() == K3_DEVICE_TYPE_GP && - (get_device_type() != K3_DEVICE_TYPE_HS_SE && - !ti_secure_cert_detected(*p_image))) + if (get_device_type() == K3_DEVICE_TYPE_GP) return; + if (get_device_type() != K3_DEVICE_TYPE_HS_SE && + !ti_secure_cert_detected(*p_image)) { + printf("Warning: Did not detect image signing certificate. " + "Skipping authentication to prevent boot failure. " + "This will fail on Security Enforcing(HS-SE) devices\n"); + return; + } + /* Clean out image so it can be seen by system firmware */ image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9d6d20bf8ed..07b5595dac8 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -106,6 +106,7 @@ config ROCKCHIP_RK322X imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT @@ -250,7 +251,6 @@ config ROCKCHIP_RK3399 imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON - imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL imply TPL_LIBCOMMON_SUPPORT diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 94e04b79e7d..f46be3d081f 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -17,6 +17,11 @@ config TARGET_ANBERNIC_RGXX3_RK3566 and RG503. The correct device tree name will automatically be selected by the bootloader. +config TARGET_ODROID_M1_RK3568 + bool "ODROID-M1" + help + Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC. + endchoice config ROCKCHIP_BOOT_MODE_REG @@ -29,9 +34,10 @@ config SYS_SOC default "rk3568" config SYS_MALLOC_F_LEN - default 0x2000 + default 0x20000 source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" +source "board/hardkernel/odroid_m1/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index b7d5f13bebb..d72ef92f2ef 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -10,15 +10,25 @@ config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT help - Neu6: - Neural Compute Module 6A(Neu6a) is a 96boards SoM-CB compute module + Neu6A: + Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module based on Rockchip RK3588 from Edgeble AI. - Neu6-IO: - Neural Compute Module 6(Neu6) IO board is an industrial form factor + Neu6A-IO: + Neural Compute Module 6A(Neu6A) IO board is an industrial form factor IO board and Neu6a needs to mount on top of this IO board in order to - create complete Edgeble Neural Compute Module 6(Neu6) IO platform. + create complete Edgeble Neural Compute Module 6A(Neu6A) IO platform. + Neu6B: + Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module + based on Rockchip RK3588J from Edgeble AI. + + Neu6A-IO: + Neural Compute Module 6B(Neu6B) IO board is an industrial form factor + IO board and Neu6a needs to mount on top of this IO board in order to + create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. + +config TARGET_ROCK5B_RK3588 config TARGET_ROCK5B_RK3588 bool "Radxa ROCK5B RK3588 board" select BOARD_LATE_INIT diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c index decc46db78e..3f1a42d1844 100644 --- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c +++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c @@ -6,25 +6,37 @@ #include <abuf.h> #include <adc.h> #include <asm/io.h> +#include <display.h> #include <dm.h> +#include <dm/lists.h> +#include <env.h> +#include <fdt_support.h> #include <linux/delay.h> +#include <mipi_dsi.h> +#include <mmc.h> +#include <panel.h> #include <pwm.h> #include <rng.h> #include <stdlib.h> -#include <mmc.h> -#include <env.h> +#include <video_bridge.h> #define GPIO0_BASE 0xfdd60000 +#define GPIO4_BASE 0xfe770000 +#define GPIO_SWPORT_DR_L 0x0000 #define GPIO_SWPORT_DR_H 0x0004 +#define GPIO_SWPORT_DDR_L 0x0008 #define GPIO_SWPORT_DDR_H 0x000c -#define GPIO_A5 BIT(5) -#define GPIO_A6 BIT(6) +#define GPIO_A0 BIT(0) +#define GPIO_C5 BIT(5) +#define GPIO_C6 BIT(6) +#define GPIO_C7 BIT(7) #define GPIO_WRITEMASK(bits) ((bits) << 16) #define DTB_DIR "rockchip/" struct rg3xx_model { + const u16 adc_value; const char *board; const char *board_name; const char *fdtfile; @@ -34,49 +46,74 @@ enum rgxx3_device_id { RG353M, RG353P, RG353V, - RG353VS, RG503, + /* Devices with duplicate ADC value */ + RG353PS, + RG353VS, }; static const struct rg3xx_model rg3xx_model_details[] = { [RG353M] = { + 517, /* Observed average from device */ "rk3566-anbernic-rg353m", "RG353M", - DTB_DIR "rk3566-anbernic-rg353m.dtb", + DTB_DIR "rk3566-anbernic-rg353p.dtb", /* Identical devices */ }, [RG353P] = { + 860, /* Documented value of 860 */ "rk3566-anbernic-rg353p", "RG353P", DTB_DIR "rk3566-anbernic-rg353p.dtb", }, [RG353V] = { + 695, /* Observed average from device */ "rk3566-anbernic-rg353v", "RG353V", DTB_DIR "rk3566-anbernic-rg353v.dtb", }, - [RG353VS] = { - "rk3566-anbernic-rg353vs", - "RG353VS", - DTB_DIR "rk3566-anbernic-rg353vs.dtb", - }, [RG503] = { + 1023, /* Observed average from device */ "rk3566-anbernic-rg503", "RG503", DTB_DIR "rk3566-anbernic-rg503.dtb", }, + /* Devices with duplicate ADC value */ + [RG353PS] = { + 860, /* Observed average from device */ + "rk3566-anbernic-rg353ps", + "RG353PS", + DTB_DIR "rk3566-anbernic-rg353ps.dtb", + }, + [RG353VS] = { + 695, /* Gathered from second hand information */ + "rk3566-anbernic-rg353vs", + "RG353VS", + DTB_DIR "rk3566-anbernic-rg353vs.dtb", + }, +}; + +struct rg353_panel { + const u16 id; + const char *panel_compat; +}; + +static const struct rg353_panel rg353_panel_details[] = { + { .id = 0x3052, .panel_compat = "newvision,nv3051d"}, + { .id = 0x3821, .panel_compat = "anbernic,rg353v-panel-v2"}, }; /* * Start LED very early so user knows device is on. Set color - * to amber. + * to red. */ void spl_board_init(void) { - /* Set GPIO0_A5 and GPIO0_A6 to output. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | (GPIO_A6 | GPIO_A5), + /* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \ + (GPIO_C7 | GPIO_C6 | GPIO_C5), (GPIO0_BASE + GPIO_SWPORT_DDR_H)); - /* Set GPIO0_A5 to 0 and GPIO0_A6 to 1. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A6, + /* Set GPIO0_C5 and GPIO_C6 to 0 and GPIO0_C7 to 1. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C7, (GPIO0_BASE + GPIO_SWPORT_DR_H)); } @@ -126,15 +163,159 @@ void __maybe_unused startup_buzz(void) pwm_set_enable(dev, 0, 0); } +/* + * Provide the bare minimum to identify the panel for the RG353 + * series. Since we don't have a working framebuffer device, no + * need to init the panel; just identify it and provide the + * clocks so we know what to set the different clock values to. + */ + +static const struct display_timing rg353_default_timing = { + .pixelclock.typ = 24150000, + .hactive.typ = 640, + .hfront_porch.typ = 40, + .hback_porch.typ = 80, + .hsync_len.typ = 2, + .vactive.typ = 480, + .vfront_porch.typ = 18, + .vback_porch.typ = 28, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_HIGH | + DISPLAY_FLAGS_VSYNC_HIGH, +}; + +static int anbernic_rg353_panel_get_timing(struct udevice *dev, + struct display_timing *timings) +{ + memcpy(timings, &rg353_default_timing, sizeof(*timings)); + + return 0; +} + +static int anbernic_rg353_panel_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + plat->lanes = 4; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_MODE_LPM; + + return 0; +} + +static const struct panel_ops anbernic_rg353_panel_ops = { + .get_display_timing = anbernic_rg353_panel_get_timing, +}; + +U_BOOT_DRIVER(anbernic_rg353_panel) = { + .name = "anbernic_rg353_panel", + .id = UCLASS_PANEL, + .ops = &anbernic_rg353_panel_ops, + .probe = anbernic_rg353_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), +}; + +int rgxx3_detect_display(void) +{ + struct udevice *dev; + struct mipi_dsi_device *dsi; + struct mipi_dsi_panel_plat *mplat; + const struct rg353_panel *panel; + int ret = 0; + int i; + u8 panel_id[2]; + + /* + * Take panel out of reset status. + * Set GPIO4_A0 to output. + */ + writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0, + (GPIO4_BASE + GPIO_SWPORT_DDR_L)); + /* Set GPIO4_A0 to 1. */ + writel(GPIO_WRITEMASK(GPIO_A0) | GPIO_A0, + (GPIO4_BASE + GPIO_SWPORT_DR_L)); + + /* Probe the DSI controller. */ + ret = uclass_get_device_by_name(UCLASS_VIDEO_BRIDGE, + "dsi@fe060000", &dev); + if (ret) { + printf("DSI host not probed: %d\n", ret); + return ret; + } + + /* Probe the DSI panel. */ + ret = device_bind_driver_to_node(dev, "anbernic_rg353_panel", + "anbernic_rg353_panel", + dev_ofnode(dev), NULL); + if (ret) { + printf("Failed to probe RG353 panel: %d\n", ret); + return ret; + } + + /* + * Attach the DSI controller which will also probe and attach + * the DSIDPHY. + */ + ret = video_bridge_attach(dev); + if (ret) { + printf("Failed to attach DSI controller: %d\n", ret); + return ret; + } + + /* + * Get the panel which should have already been probed by the + * video_bridge_attach() function. + */ + ret = uclass_first_device_err(UCLASS_PANEL, &dev); + if (ret) { + printf("Panel device error: %d\n", ret); + return ret; + } + + /* Now call the panel via DSI commands to get the panel ID. */ + mplat = dev_get_plat(dev); + dsi = mplat->device; + mipi_dsi_set_maximum_return_packet_size(dsi, sizeof(panel_id)); + ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, &panel_id, + sizeof(panel_id)); + if (ret < 0) { + printf("Unable to read panel ID: %d\n", ret); + return ret; + } + + /* Get the correct panel compatible from the table. */ + for (i = 0; i < ARRAY_SIZE(rg353_panel_details); i++) { + if (rg353_panel_details[i].id == ((panel_id[0] << 8) | + panel_id[1])) { + panel = &rg353_panel_details[i]; + break; + } + } + + if (!panel) { + printf("Unable to identify panel_id %x\n", + (panel_id[0] << 8) | panel_id[1]); + env_set("panel", "unknown"); + return -EINVAL; + } + + env_set("panel", panel->panel_compat); + + return 0; +} + /* Detect which Anbernic RGXX3 device we are using so as to load the * correct devicetree for Linux. Set an environment variable once * found. The detection depends on the value of ADC channel 1, the - * presence of an eMMC on mmc0, and querying the DSI panel (TODO). + * presence of an eMMC on mmc0, and querying the DSI panel. */ int rgxx3_detect_device(void) { u32 adc_info; - int ret; + int ret, i; int board_id = -ENXIO; struct mmc *mmc; @@ -144,30 +325,37 @@ int rgxx3_detect_device(void) return ret; } - /* Observed value 517. */ - if (adc_info > 505 && adc_info < 530) - board_id = RG353M; - /* Observed value 695. */ - if (adc_info > 680 && adc_info < 710) - board_id = RG353V; - /* Documented value 860. */ - if (adc_info > 850 && adc_info < 870) - board_id = RG353P; - /* Observed value 1023. */ - if (adc_info > 1010) - board_id = RG503; + /* + * Get the correct device from the table. The ADC value is + * determined by a resistor on ADC channel 0. The hardware + * design calls for no more than a 1% variance on the + * resistor, so assume a +- value of 15 should be enough. + */ + for (i = 0; i < ARRAY_SIZE(rg3xx_model_details); i++) { + u32 adc_min = rg3xx_model_details[i].adc_value - 15; + u32 adc_max = rg3xx_model_details[i].adc_value + 15; + + if (adc_min < adc_info && adc_max > adc_info) { + board_id = i; + break; + } + } /* - * Try to access the eMMC on an RG353V. If it's missing, it's - * an RG353VS. Note we could also check for a touchscreen at - * 0x1a on i2c2. + * Try to access the eMMC on an RG353V or RG353P. If it's + * missing, it's an RG353VS or RG353PS. Note we could also + * check for a touchscreen at 0x1a on i2c2. */ - if (board_id == RG353V) { + if (board_id == RG353V || board_id == RG353P) { mmc = find_mmc_device(0); if (mmc) { ret = mmc_init(mmc); - if (ret) - board_id = RG353VS; + if (ret) { + if (board_id == RG353V) + board_id = RG353VS; + else + board_id = RG353PS; + } } } @@ -179,6 +367,14 @@ int rgxx3_detect_device(void) rg3xx_model_details[board_id].board_name); env_set("fdtfile", rg3xx_model_details[board_id].fdtfile); + /* Detect the panel type for any device that isn't a 503. */ + if (board_id == RG503) + return 0; + + ret = rgxx3_detect_display(); + if (ret) + return ret; + return 0; } @@ -186,18 +382,64 @@ int rk_board_late_init(void) { int ret; - /* Turn off orange LED and turn on green LED. */ - writel(GPIO_WRITEMASK(GPIO_A6 | GPIO_A5) | GPIO_A5, - (GPIO0_BASE + GPIO_SWPORT_DR_H)); - ret = rgxx3_detect_device(); if (ret) { printf("Unable to detect device type: %d\n", ret); return ret; } + /* Turn off red LED and turn on orange LED. */ + writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | GPIO_C6, + (GPIO0_BASE + GPIO_SWPORT_DR_H)); + if (IS_ENABLED(CONFIG_DM_PWM)) startup_buzz(); return 0; } + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int node, ret; + char *env; + + /* No fixups necessary for the RG503 */ + env = env_get("board_name"); + if (env && (!strcmp(env, rg3xx_model_details[RG503].board_name))) + return 0; + + /* Change the model name of the RG353M */ + if (env && (!strcmp(env, rg3xx_model_details[RG353M].board_name))) + fdt_setprop(blob, 0, "model", + rg3xx_model_details[RG353M].board_name, + sizeof(rg3xx_model_details[RG353M].board_name)); + + /* + * Check if the environment variable doesn't equal the panel. + * If it doesn't, update the devicetree to the correct panel. + */ + node = fdt_path_offset(blob, "/dsi@fe060000/panel@0"); + if (!(node > 0)) { + printf("Can't find the DSI node\n"); + return -ENODEV; + } + + env = env_get("panel"); + if (!env) { + printf("Can't get panel env\n"); + return -ENODEV; + } + + ret = fdt_node_check_compatible(blob, node, env); + if (ret < 0) + return -ENODEV; + + /* Panels match, return 0. */ + if (!ret) + return 0; + + do_fixup_by_path_string(blob, "/dsi@fe060000/panel@0", + "compatible", env); + + return 0; +} diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index 249df957f1d..bc7f9b0e680 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig +F: configs/neu6b-io-rk3588_defconfig diff --git a/board/hardkernel/odroid_go2/go2.c b/board/hardkernel/odroid_go2/go2.c index 29464ae63ec..a0338ead3b5 100644 --- a/board/hardkernel/odroid_go2/go2.c +++ b/board/hardkernel/odroid_go2/go2.c @@ -2,3 +2,106 @@ /* * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ + +#include <linux/stddef.h> +#include <adc.h> +#include <asm/io.h> +#include <dm.h> +#include <env.h> +#include <stdlib.h> + +#define DTB_DIR "rockchip/" + +struct oga_model { + const u16 adc_value; + const char *board; + const char *board_name; + const char *fdtfile; +}; + +enum oga_device_id { + OGA, + OGA_V11, + OGS, +}; + +/* + * All ADC values from schematic of Odroid Go Advance Black Edition. + * Value for OGS is inferred based on schematic and observed values. + */ +static const struct oga_model oga_model_details[] = { + [OGA] = { + 856, + "rk3326-odroid-go2", + "ODROID-GO Advance", + DTB_DIR "rk3326-odroid-go2.dtb", + }, + [OGA_V11] = { + 677, + "rk3326-odroid-go2-v11", + "ODROID-GO Advance Black Edition", + DTB_DIR "rk3326-odroid-go2-v11.dtb", + }, + [OGS] = { + 85, + "rk3326-odroid-go3", + "ODROID-GO Super", + DTB_DIR "rk3326-odroid-go3.dtb", + }, +}; + +/* Detect which Odroid Go Advance device we are using so as to load the + * correct devicetree for Linux. Set an environment variable once + * found. The detection depends on the value of ADC channel 0. + */ +int oga_detect_device(void) +{ + u32 adc_info; + int ret, i; + int board_id = -ENXIO; + + ret = adc_channel_single_shot("saradc@ff288000", 0, &adc_info); + if (ret) { + printf("Read SARADC failed with error %d\n", ret); + return ret; + } + + /* + * Get the correct device from the table. The ADC value is + * determined by a resistor on ADC channel 0. The manufacturer + * accounted for this with a 5% tolerance, so assume a +- value + * of 50 should be enough. + */ + for (i = 0; i < ARRAY_SIZE(oga_model_details); i++) { + u32 adc_min = oga_model_details[i].adc_value - 50; + u32 adc_max = oga_model_details[i].adc_value + 50; + + if (adc_min < adc_info && adc_max > adc_info) { + board_id = i; + break; + } + } + + if (board_id < 0) + return board_id; + + env_set("board", oga_model_details[board_id].board); + env_set("board_name", + oga_model_details[board_id].board_name); + env_set("fdtfile", oga_model_details[board_id].fdtfile); + + return 0; +} + +int rk_board_late_init(void) +{ + int ret; + + ret = oga_detect_device(); + if (ret) { + printf("Unable to detect device type: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/board/hardkernel/odroid_m1/Kconfig b/board/hardkernel/odroid_m1/Kconfig new file mode 100644 index 00000000000..999c4944a83 --- /dev/null +++ b/board/hardkernel/odroid_m1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ODROID_M1_RK3568 + +config SYS_BOARD + default "odroid_m1" + +config SYS_VENDOR + default "hardkernel" + +config SYS_CONFIG_NAME + default "odroid_m1" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS new file mode 100644 index 00000000000..165d2d96741 --- /dev/null +++ b/board/hardkernel/odroid_m1/MAINTAINERS @@ -0,0 +1,8 @@ +ODROID-M1 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/hardkernel/odroid_m1/ +F: include/configs/odroid_m1.h +F: configs/odroid-m1-rk3568_defconfig +F: arch/arm/dts/rk3568-odroid-m1.dts +F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi diff --git a/board/hardkernel/odroid_m1/Makefile b/board/hardkernel/odroid_m1/Makefile new file mode 100644 index 00000000000..ae8ea3d9781 --- /dev/null +++ b/board/hardkernel/odroid_m1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += odroid_m1.o diff --git a/board/hardkernel/odroid_m1/odroid_m1.c b/board/hardkernel/odroid_m1/odroid_m1.c new file mode 100644 index 00000000000..4c027f2a7af --- /dev/null +++ b/board/hardkernel/odroid_m1/odroid_m1.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README index 9068225e272..a8dcc40f09b 100644 --- a/board/rockchip/evb_rk3229/README +++ b/board/rockchip/evb_rk3229/README @@ -13,25 +13,23 @@ Compile the OP-TEE > cd optee_os > make clean - > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x - Get tee.bin in this step, copy it to U-Boot root dir: - > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + > make CROSS_COMPILE=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee-raw.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-raw.bin ../u-boot/tee.bin Compile the U-Boot ================== > cd ../u-boot - > export CROSS_COMPILE=arm-linux-gnueabihf- > make evb-rk3229_defconfig - > make - > make u-boot.itb + > TEE=tee.bin CROSS_COMPILE=arm-linux-gnueabihf- make - Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + Get u-boot-rockchip.bin in this step. Compile the rkdeveloptool ======================= Follow instructions in latest README - > cd ../rkflashtool + > cd ../rkdeveloptool > autoreconf -i > ./configure > make @@ -42,30 +40,56 @@ Compile the rkdeveloptool Both origin binaries and Tool are ready now, choose either option 1 or option 2 to deploy U-Boot. -Package the image -================= - - > cd ../u-boot - > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img - > cat spl/u-boot-spl.bin >> idbloader.img - - Get idbloader.img in this step. - Flash the image to eMMC ======================= Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: > cd .. - > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin - > rkdeveloptool wl 64 u-boot/idbloader.img - > rkdeveloptool wl 0x4000 u-boot/u-boot.itb - > rkdeveloptool rd + > rkdeveloptool/rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool/rkdeveloptool wl 64 u-boot/u-boot-rockchip.bin + > rkdeveloptool/rkdeveloptool rd Flash the image to SD card ========================== - > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 - > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + > dd if=u-boot/u-boot-rockchip.bin of=/dev/sdb seek=64 + +You should be able to get U-Boot log message with OP-TEE boot info: + +U-Boot TPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51) +Trying to boot from BOOTROM +Returning to boot ROM... + +U-Boot SPL 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) +Trying to boot from MMC1 +I/TC: +I/TC: Non-secure external DT found +I/TC: Switching console to device: /serial@11030000 +I/TC: OP-TEE version: 3.22.0-27-g893a762d1 (gcc version 10.3.1 20210621 (release) (15:10.3-2021.07-4)) #1 Sat Jul 15 12:14:36 UTC 2023 arm +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +M/TC: Not protecting region 1: 0x68400000-0x68600000 +I/TC: Primary CPU switching to normal world boot + + +U-Boot 2023.07-00524-gf5346eba55-dirty (Jul 15 2023 - 14:22:51 +0200) + +Model: Rockchip RK3229 Evaluation board +DRAM: 1 GiB (effective 992 MiB) +Core: 113 devices, 16 uclasses, devicetree: separate +MMC: mmc@30000000: 1, mmc@30020000: 0 +Loading Environment from MMC... Card did not respond to voltage select! : -110 +*** Warning - No block device, using default environment + +In: serial@11030000 +Out: serial@11030000 +Err: serial@11030000 +Model: Rockchip RK3229 Evaluation board +Net: +Warning: ethernet@30200000 (eth0) using random MAC address - 72:65:2b:f1:c5:0a +eth0: ethernet@30200000 +Hit any key to stop autoboot: 0 +=> -You should be able to get U-Boot log message with OP-TEE boot info. For more detail, please reference to: http://opensource.rock-chips.com/wiki_Boot_option diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 3c46613ab58..8a19eb373d0 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -18,6 +18,18 @@ F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi F: arch/arm/dts/rk3328-nanopi-r2s.dts +ORANGEPI-R1-PLUS-RK3328 +M: Tianling Shen <cnsztl@gmail.com> +S: Maintained +F: configs/orangepi-r1-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi + +ORANGEPI-R1-PLUS-LTS-RK3328 +M: Tianling Shen <cnsztl@gmail.com> +S: Maintained +F: configs/orangepi-r1-plus-lts-rk3328_defconfig +F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi + ROC-RK3328-CC M: Loic Devulder <ldevulder@suse.com> M: Chen-Yu Tsai <wens@csie.org> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index de1dc64a962..cb44bc9fda4 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -86,6 +86,12 @@ S: Maintained F: configs/rock-4c-plus-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4c-plus.dts +ROCK-4SE +M: Christopher Obbard <chris.obbard@collabora.com> +S: Maintained +F: configs/rock-4se-rk3399_defconfig +F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi + ROCK-PI-4 M: Akash Gajjar <akash@openedev.com> M: Jagan Teki <jagan@amarulasolutions.com> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 6b2e7c7575d..a8ed2508a16 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -7,6 +7,21 @@ F: configs/evb-rk3568_defconfig F: arch/arm/dts/rk3568-evb-boot.dtsi F: arch/arm/dts/rk3568-evb.dts +NANOPI-R5C +M: Tianling Shen <cnsztl@gmail.com> +S: Maintained +F: configs/nanopi-r5c-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5c.dts +F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi + +NANOPI-R5S +M: Tianling Shen <cnsztl@gmail.com> +S: Maintained +F: configs/nanopi-r5s-rk3568_defconfig +F: arch/arm/dts/rk3568-nanopi-r5s.dts +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi + RADXA-CM3 M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig index e66b2427d95..a6170aae807 100644 --- a/board/siemens/iot2050/Kconfig +++ b/board/siemens/iot2050/Kconfig @@ -1,40 +1,22 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (c) Siemens AG, 2018-2022 +# Copyright (c) Siemens AG, 2018-2023 # # Authors: # Le Jin <le.jin@siemens.com> # Jan Kiszka <jan.kiszka@siemens.com> -choice - prompt "Siemens SIMATIC IOT2050 boards" - optional - -config TARGET_IOT2050_A53_PG1 - bool "IOT2050 PG1 running on A53" - select IOT2050_A53_COMMON - help - This builds U-Boot for the Product Generation 1 (PG1) of the IOT2050 - devices. - -config TARGET_IOT2050_A53_PG2 - bool "IOT2050 PG2 running on A53" - select IOT2050_A53_COMMON - help - This builds U-Boot for the Product Generation 2 (PG2) of the IOT2050 - devices. - -endchoice - -config IOT2050_A53_COMMON - bool +config TARGET_IOT2050_A53 + bool "IOT2050 running on A53" select ARM64 select SOC_K3_AM654 select BOARD_LATE_INIT select SYS_DISABLE_DCACHE_OPS select BINMAN + help + This builds U-Boot for the IOT2050 devices. -if IOT2050_A53_COMMON +if TARGET_IOT2050_A53 config SYS_BOARD default "iot2050" diff --git a/board/siemens/iot2050/MAINTAINERS b/board/siemens/iot2050/MAINTAINERS index aa21de2099f..1b525356c2d 100644 --- a/board/siemens/iot2050/MAINTAINERS +++ b/board/siemens/iot2050/MAINTAINERS @@ -4,7 +4,6 @@ M: Jan Kiszka <jan.kiszka@siemens.com> S: Maintained F: board/siemens/iot2050/ F: include/configs/iot2050.h -F: configs/iot2050_pg1_defconfig -F: configs/iot2050_pg2_defconfig +F: configs/iot2050_defconfig F: arch/arm/dts/iot2050-* F: doc/board/siemens/iot2050.rst diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 2653e107450..15f5310c7bf 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Board specific initialization for IOT2050 - * Copyright (c) Siemens AG, 2018-2022 + * Copyright (c) Siemens AG, 2018-2023 * * Authors: * Le Jin <le.jin@siemens.com> @@ -147,21 +147,28 @@ static void set_pinvalue(const char *gpio_name, const char *label, int value) dm_gpio_set_value(&gpio, value); } -static bool board_is_m2(void) +static bool board_is_advanced(void) { struct iot2050_info *info = IOT2050_INFO_DATA; - return IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG2) && - info->magic == IOT2050_INFO_MAGIC && - strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0; + return info->magic == IOT2050_INFO_MAGIC && + strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; } -static bool board_is_advanced(void) +static bool board_is_sr1(void) { struct iot2050_info *info = IOT2050_INFO_DATA; return info->magic == IOT2050_INFO_MAGIC && - strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; + strstr((char *)info->name, "-PG2") != NULL; +} + +static bool board_is_m2(void) +{ + struct iot2050_info *info = IOT2050_INFO_DATA; + + return !board_is_sr1() && info->magic == IOT2050_INFO_MAGIC && + strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0; } static void remove_mmc1_target(void) @@ -210,14 +217,14 @@ void set_board_info_env(void) } if (board_is_advanced()) { - if (IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG1)) + if (board_is_sr1()) fdtfile = "ti/k3-am6548-iot2050-advanced.dtb"; else if(board_is_m2()) fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb"; else fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb"; } else { - if (IS_ENABLED(CONFIG_TARGET_IOT2050_A53_PG1)) + if (board_is_sr1()) fdtfile = "ti/k3-am6528-iot2050-basic.dtb"; else fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb"; diff --git a/board/siemens/iot2050/iot2050.env b/board/siemens/iot2050/iot2050.env index 02958798b49..7fd836e6285 100644 --- a/board/siemens/iot2050/iot2050.env +++ b/board/siemens/iot2050/iot2050.env @@ -6,6 +6,8 @@ * Jan Kiszka <jan.kiszka@siemens.com> */ +#include <environment/ti/ti_armv7_common.env> + usb_pgood_delay=900 watchdog_timeout_ms=CONFIG_WATCHDOG_TIMEOUT_MSECS diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index 0901a8536da..bb37d21de61 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -16,20 +16,6 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- -init_mmc=run args_all args_mmc -get_overlay_mmc= - fdt address ${fdtaddr}; - fdt resize 0x100000; - for overlay in $name_overlays; - do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && - fdt apply ${dtboaddr}; - done; -get_kern_mmc=load mmc ${bootpart} ${loadaddr} - ${bootdir}/${name_kern} -get_fit_mmc=load mmc ${bootpart} ${addr_fit} - ${bootdir}/${name_fit} -partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} splashfile=ti.gz splashimage=0x80200000 diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 015f63a66c7..ecb07366fc8 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -20,20 +20,6 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- -init_mmc=run args_all args_mmc -get_overlay_mmc= - fdt address ${fdtaddr}; - fdt resize 0x100000; - for overlay in $name_overlays; - do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && - fdt apply ${dtboaddr}; - done; -get_kern_mmc=load mmc ${bootpart} ${loadaddr} - ${bootdir}/${name_kern} -get_fit_mmc=load mmc ${bootpart} ${addr_fit} - ${bootdir}/${name_fit} -partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} args_usb=run finduuid;setenv bootargs console=${console} ${optargs} diff --git a/board/ti/am65x/am65x.env b/board/ti/am65x/am65x.env index d7130cc3f7d..036f4752835 100644 --- a/board/ti/am65x/am65x.env +++ b/board/ti/am65x/am65x.env @@ -19,20 +19,6 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- -init_mmc=run args_all args_mmc -get_overlay_mmc= - fdt address ${fdtaddr}; - fdt resize 0x100000; - for overlay in $name_overlays; - do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && - fdt apply ${dtboaddr}; - done; -get_kern_mmc=load mmc ${bootpart} ${loadaddr} - ${bootdir}/${name_kern} -get_fit_mmc=load mmc ${bootpart} ${addr_fit} - ${bootdir}/${name_fit} -partitions=name=root,start=0,size=-,uuid=${uuid_gpt_rootfs} init_ubi= run args_all args_ubi; diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 23ce7e1af74..f7a4880bf83 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -36,21 +36,6 @@ mmcdev=1 bootpart=1:2 bootdir=/boot rd_spec=- -init_mmc=run args_all args_mmc -get_overlay_mmc= - fdt address ${fdtaddr}; - fdt resize 0x100000; - for overlay in $name_overlays; - do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && - fdt apply ${dtboaddr}; - done; -partitions=uuid_disk=${uuid_gpt_disk}; - name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} -get_kern_mmc=load mmc ${bootpart} ${loadaddr} - ${bootdir}/${name_kern} -get_fit_mmc=load mmc ${bootpart} ${addr_fit} - ${bootdir}/${name_fit} #if CONFIG_TARGET_J7200_A72_EVM do_main_cpsw0_qsgmii_phyinit=1 diff --git a/board/ti/j721s2/j721s2.env b/board/ti/j721s2/j721s2.env index 9464fe49903..2ec652dbdd3 100644 --- a/board/ti/j721s2/j721s2.env +++ b/board/ti/j721s2/j721s2.env @@ -30,23 +30,6 @@ addr_mcur5f0_0load=0x89000000 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw #endif rd_spec=- -init_mmc=run args_all args_mmc -get_overlay_mmc= - fdt address ${fdtaddr}; - fdt resize 0x100000; - for overlay in $name_overlays; - do; - load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && - fdt apply ${dtboaddr}; - done; -partitions=uuid_disk=${uuid_gpt_disk}; - name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} -get_kern_mmc=load mmc ${bootpart} ${loadaddr} - ${bootdir}/${name_kern} -get_fit_mmc=load mmc ${bootpart} ${addr_fit} - ${bootdir}/${name_fit} -partitions=uuid_disk=${uuid_gpt_disk}; - name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} rproc_fw_binaries= 2 /lib/firmware/j721s2-main-r5f0_0-fw 3 /lib/firmware/j721s2-main-r5f0_1-fw 4 /lib/firmware/j721s2-main-r5f1_0-fw 5 /lib/firmware/j721s2-main-r5f1_1-fw 6 /lib/firmware/j721s2-c71_0-fw 7 /lib/firmware/j721s2-c71_1-fw diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 9477f5336b8..8b3a43a5aa8 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -9,6 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "k2e_evm" +config ENV_SOURCE_FILE + default "k2e_evm" + endif if TARGET_K2HK_EVM @@ -22,6 +25,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "k2hk_evm" +config ENV_SOURCE_FILE + default "k2hk_evm" + endif if TARGET_K2L_EVM @@ -35,6 +41,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "k2l_evm" +config ENV_SOURCE_FILE + default "k2l_evm" + endif if TARGET_K2G_EVM @@ -48,6 +57,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "k2g_evm" +config ENV_SOURCE_FILE + default "k2g_evm" + endif source "board/ti/common/Kconfig" diff --git a/board/ti/ks2_evm/k2e_evm.env b/board/ti/ks2_evm/k2e_evm.env new file mode 100644 index 00000000000..746e4065a2c --- /dev/null +++ b/board/ti/ks2_evm/k2e_evm.env @@ -0,0 +1,12 @@ +#include <environment/ti/ti_armv7_common.env> +#include <environment/ti/ti_armv7_keystone2.env> + +findfdt=setenv fdtfile ${name_fdt} +boot=ubi +args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048 + +name_fdt=keystone-k2e-evm.dtb +name_mon=skern-k2e.bin +name_ubi=k2e-evm-ubifs.ubi +name_uboot=u-boot-spi-k2e-evm.gph +name_fs=arago-console-image-k2e-evm.cpio.gz diff --git a/board/ti/ks2_evm/k2g_evm.env b/board/ti/ks2_evm/k2g_evm.env new file mode 100644 index 00000000000..72807ac87a6 --- /dev/null +++ b/board/ti/ks2_evm/k2g_evm.env @@ -0,0 +1,45 @@ +#include <environment/ti/ti_armv7_common.env> +#include <environment/ti/ti_armv7_keystone2.env> +#include <environment/ti/mmc.env> + +set_name_pmmc=setenv name_pmmc ti-sci-firmware-k2g.bin +dev_pmmc=0 +get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc} +get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc} +get_pmmc_ramfs=run get_pmmc_net +get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} ${bootdir}/${name_pmmc} +get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc} +run_pmmc=rproc init; + rproc list; + rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; + rproc start ${dev_pmmc} + +boot=mmc +console=ttyS0,115200n8 +bootpart=0:2 +bootdir=/boot +rd_spec=- +args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048 + +findfdt= + if test $board_name = 66AK2GGP; then + setenv name_fdt keystone-k2g-evm.dtb; fi; + if test $board_name = 66AK2GG1; then + setenv name_fdt keystone-k2g-evm.dtb; fi; + if test $board_name = 66AK2GIC; then + setenv name_fdt keystone-k2g-ice.dtb; fi; + if test $board_name = 66AK2GI1; then + setenv name_fdt keystone-k2g-ice.dtb; fi; + if test $name_fdt = undefined; then + echo WARNING: Could not determine device tree to use; fi; + setenv fdtfile ${name_fdt} + +name_mon=skern-k2g.bin +name_ubi=k2g-evm-ubifs.ubi +name_uboot=u-boot-spi-k2g-evm.gph +init_mmc=run args_all args_mmc +init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} ${bootdir}/${name_fw_rd}; run set_rd_spec +get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt} +get_kern_mmc=load mmc ${bootpart} ${loadaddr} ${bootdir}/${name_kern} +get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon} +name_fs=arago-base-tisdk-image-k2g-evm.cpio diff --git a/board/ti/ks2_evm/k2hk_evm.env b/board/ti/ks2_evm/k2hk_evm.env new file mode 100644 index 00000000000..f1cdc706036 --- /dev/null +++ b/board/ti/ks2_evm/k2hk_evm.env @@ -0,0 +1,12 @@ +#include <environment/ti/ti_armv7_common.env> +#include <environment/ti/ti_armv7_keystone2.env> + +findfdt=setenv fdtfile ${name_fdt} +boot=ubi +args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048 + +name_fdt=keystone-k2hk-evm.dtb +name_mon=skern-k2hk.bin +name_ubi=k2hk-evm-ubifs.ubi +name_uboot=u-boot-spi-k2hk-evm.gph +name_fs=arago-console-image-k2hk-evm.cpio.gz diff --git a/board/ti/ks2_evm/k2l_evm.env b/board/ti/ks2_evm/k2l_evm.env new file mode 100644 index 00000000000..ddb5cd4aadc --- /dev/null +++ b/board/ti/ks2_evm/k2l_evm.env @@ -0,0 +1,12 @@ +#include <environment/ti/ti_armv7_common.env> +#include <environment/ti/ti_armv7_keystone2.env> + +findfdt=setenv fdtfile ${name_fdt} +boot=ubi +args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096 + +name_fdt=keystone-k2l-evm.dtb +name_mon=skern-k2l.bin +name_ubi=k2l-evm-ubifs.ubi +name_uboot=u-boot-spi-k2l-evm.gph +name_fs=arago-console-image-k2l-evm.cpio.gz\0" diff --git a/cmd/ini.c b/cmd/ini.c index 81dfc4c4e83..35de2373e60 100644 --- a/cmd/ini.c +++ b/cmd/ini.c @@ -89,7 +89,7 @@ static char *memgets(char *str, int num, char **mem, size_t *memsize) end = *mem + *memsize; newline = 0; } - len = min((end - *mem) + newline, num); + len = min((int)(end - *mem) + newline, num); memcpy(str, *mem, len); if (len < num) str[len] = '\0'; diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index de90663383e..d55caabe22c 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;" +CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 diff --git a/configs/anbernic-rgxx3_defconfig b/configs/anbernic-rgxx3_defconfig index b17e9179148..ed6643d9d4f 100644 --- a/configs/anbernic-rgxx3_defconfig +++ b/configs/anbernic-rgxx3_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x600000 @@ -24,9 +25,13 @@ CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb" +# CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_RNG_SEED=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -41,6 +46,7 @@ CONFIG_CMD_PWM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_CLS is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y @@ -60,6 +66,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y @@ -69,10 +76,18 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_RNG_SMCCC_TRNG is not set CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_VIDEO=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y +CONFIG_VIDEO_BRIDGE=y CONFIG_REGEX=y CONFIG_ERRNO_STR=y # CONFIG_EFI_LOADER is not set diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index d4302353c5d..253ef99f993 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -81,6 +81,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index dd6d4069a60..1807e838223 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -43,6 +43,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 1a54986d089..3172f04a264 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -84,6 +84,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 3d2642f0d07..638beee2c6d 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -44,6 +44,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 73ab2f62af5..25a56f45fe6 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -83,6 +83,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 06437aae18d..ff2a12b25c3 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -82,6 +82,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MTD=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index b4112a14712..77edbdbf959 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index cf73afeded8..73015f098c2 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000 CONFIG_SPL_OPTEE_IMAGE=y CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_GPT=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index f594f15b3f8..5740ffc38f6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 94b8f88a965..90b07d847cc 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 0ece93b71d6..b4660a051df 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/iot2050_pg1_defconfig b/configs/iot2050_defconfig index cc1b9673d79..bcbaa92ee89 100644 --- a/configs/iot2050_pg1_defconfig +++ b/configs/iot2050_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM654=y -CONFIG_TARGET_IOT2050_A53_PG1=y +CONFIG_TARGET_IOT2050_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80100000 CONFIG_ENV_SIZE=0x20000 @@ -29,12 +29,17 @@ CONFIG_SPL_SPI=y CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_SPL_SHOW_BOOT_PROGRESS=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_FLUSH_STDIN=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE to stop autoboot in %d seconds...\n" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -73,7 +78,6 @@ CONFIG_CMD_TIME=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-am6528-iot2050-basic k3-am6548-iot2050-advanced" CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y diff --git a/configs/iot2050_pg2_defconfig b/configs/iot2050_pg2_defconfig deleted file mode 100644 index c5741a4dae4..00000000000 --- a/configs/iot2050_pg2_defconfig +++ /dev/null @@ -1,150 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_K3=y -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SOC_K3_AM654=y -CONFIG_TARGET_IOT2050_A53_PG2=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80100000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0x680000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am6528-iot2050-basic-pg2" -CONFIG_SPL_TEXT_BASE=0x80080000 -CONFIG_SYS_PROMPT="IOT2050> " -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_ENV_OFFSET_REDUND=0x6a0000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_PCI=y -# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL_LOAD_FIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTSTAGE=y -CONFIG_SHOW_BOOT_PROGRESS=y -CONFIG_SPL_SHOW_BOOT_PROGRESS=y -CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" -CONFIG_CONSOLE_MUX=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x58000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x80a00000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_STACK_R=y -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_POWER_DOMAIN=y -# CONFIG_SPL_SPI_FLASH_TINY is not set -CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x380000 -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=1050 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y -CONFIG_CMD_WDT=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TIME=y -# CONFIG_ISO_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="k3-am6528-iot2050-basic-pg2 k3-am6548-iot2050-advanced-pg2 k3-am6548-iot2050-advanced-m2" -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="k3-am65-iot2050-spl" -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_REGMAP=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_CLK_TI_SCI=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_DFU_SF=y -CONFIG_DMA_CHANNELS=y -CONFIG_TI_K3_NAVSS_UDMA=y -CONFIG_TI_SCI_PROTOCOL=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_LED=y -CONFIG_SPL_LED=y -CONFIG_LED_GPIO=y -CONFIG_SPL_LED_GPIO=y -CONFIG_DM_MAILBOX=y -CONFIG_K3_SEC_PROXY=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ADMA=y -CONFIG_MMC_SDHCI_AM654=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PCI_KEYSTONE=y -CONFIG_PHY=y -CONFIG_AM654_PHY=y -CONFIG_OMAP_USB2_PHY=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_GENERIC is not set -CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINCTRL_GENERIC is not set -CONFIG_PINCTRL_SINGLE=y -CONFIG_POWER_DOMAIN=y -CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_REMOTEPROC_TI_K3_R5F=y -CONFIG_RESET_TI_SCI=y -CONFIG_DM_SERIAL=y -CONFIG_SOC_DEVICE=y -CONFIG_SOC_DEVICE_TI_K3=y -CONFIG_SOC_TI=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_TI_SCI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_KEYBOARD=y -# CONFIG_WATCHDOG is not set -# CONFIG_WATCHDOG_AUTOSTART is not set -CONFIG_WATCHDOG_TIMEOUT_MSECS=0 -CONFIG_WDT=y -CONFIG_WDT_K3_RTI=y -CONFIG_WDT_K3_RTI_LOAD_FW=y -CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 6d9d82594e1..44bed00ec97 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index c782bf11830..55c0182f874 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 756e7502a19..45c7fade320 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -56,7 +56,6 @@ CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index f0de3232e9d..54a980cab54 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 74ef0668d86..a2651780484 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 5bd8c28f546..8c0472dcc2b 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 378a71f94e1..55ddd3cce96 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -58,7 +58,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 31ec3029d76..ce7aa3a39ef 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_NAND=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 0651b982f59..2800c47361d 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 85e18aaa1a2..33b2afd869d 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 7fe559b49ea..f7a6445b3c1 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1048 CONFIG_CMD_BOOTZ=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index c1184596889..fa936609e9b 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 75589bb519a..82e86ca0702 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 04ce5438f4f..dd715517d5a 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 6745934d988..3da93db06da 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 1a9839b4d15..701dde15f3e 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index ad0627fe655..3f9d0340c81 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index a41e774b0c4..4f4363cb0f9 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig new file mode 100644 index 00000000000..b913ad4494c --- /dev/null +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig new file mode 100644 index 00000000000..0a298c65a76 --- /dev/null +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_WARN=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_ERRNO_STR=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig new file mode 100644 index 00000000000..c7bc3b1965f --- /dev/null +++ b/configs/neu6b-io-rk3588_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_RK3588_NEU6=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 459ae3d59c6..bdc2288af66 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3326-odroid-go2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_PAD_TO=0x7f8000 diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig new file mode 100644 index 00000000000..3dda5c1f917 --- /dev/null +++ b/configs/odroid-m1-rk3568_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_ODROID_M1_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_INI=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_CRAMFS=y +CONFIG_MTDPARTS_DEFAULT="nor0:0x100000(reserved),0x200000(uboot),0x100000(splash),0xc00000(Firmware)" +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_FS_CRAMFS=y +CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig new file mode 100644 index 00000000000..59a28e5209c --- /dev/null +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig new file mode 100644 index 00000000000..3f62f0588d7 --- /dev/null +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK=0x400000 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2000000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 0f814b1b289..ba6d91e877d 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 58a8b91aa60..5d493c910ee 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index e4a8beeb1ab..f97a4003bba 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 9321292ca52..0d113c764f6 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 824b4041c20..7e5db741951 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig index 753d03914d9..8e3fe0a25e1 100644 --- a/configs/rock-3a-rk3568_defconfig +++ b/configs/rock-3a-rk3568_defconfig @@ -22,7 +22,9 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -46,6 +48,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PMIC=y @@ -56,6 +59,8 @@ CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -70,6 +75,8 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_SPL_PINCTRL=y @@ -78,6 +85,8 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 3c79d2ac3d3..3028a86705c 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig new file mode 100644 index 00000000000..9abe8bf8535 --- /dev/null +++ b/configs/rock-4se-rk3399_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 466868d80b0..84e0dcf0282 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 1c7648c1f0c..5c9fb14787d 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 8eb17d8feca..1978fd525b8 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 17205a56cd9..3976a6c0f05 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a00000 @@ -34,6 +35,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -47,9 +49,11 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -59,6 +63,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -71,10 +76,12 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_XTX=y CONFIG_ETH_DESIGNWARE=y +CONFIG_RTL8169=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y @@ -85,10 +92,16 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y @@ -97,4 +110,8 @@ CONFIG_USB_ETHER_LAN78XX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_PRODUCT_NUM=0x350b +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3d6aeaa5efc..4e048b6ba18 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PBSIZE=1052 CONFIG_CMD_BOOTZ=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index dc4392c7451..62daad27a6f 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst index afa7538282f..7d1beb423ce 100644 --- a/doc/board/anbernic/rgxx3.rst +++ b/doc/board/anbernic/rgxx3.rst @@ -7,27 +7,36 @@ This allows U-Boot to boot the following Anbernic devices: - Anbernic RG353M - Anbernic RG353P + - Anbernic RG353PS - Anbernic RG353V - Anbernic RG353VS - Anbernic RG503 The correct device is detected automatically by comparing ADC values -from ADC channel 1. In the event of an RG353V, an attempt is then made -to probe for an eMMC and if it fails the device is assumed to be an -RG353VS. Based on the detected device, the environment variables -"board", "board_name", and "fdtfile" are set to the correct values -corresponding to the board which can be read by a boot script to boot -with the correct device tree. - -Please note that there are some versions of the RG353 devices with -different panels. Panel auto-detection is planned for a later date. +from ADC channel 1. In the event of an RG353V or RG353P, an attempt +is then made to probe for an eMMC and if it fails the device is assumed +to be an RG353VS or RG353PS. Based on the detected device, the +environment variables "board", "board_name", and "fdtfile" are set to +the correct values corresponding to the board which can be read by a +boot script to boot with the correct device tree. If the board detected +is not of type RG503 (which currently has only 1 panel revision) a +panel detect is then performed by probing a "dummy" display on the DSI +bus and then querying the display ID. The display ID is then compared +to a table to get the known compatible string for use in Linux, and +this string is saved as an environment variable of "panel". + +FDT fixups are performed in the event of an RG353M to change the device +name, or in the event the panel detected does not match the devicetree. +This allows Linux to load the correct panel driver without having to +know exactly which panel is used (as there is no user distingushable +way to tell). Building U-Boot --------------- .. code-block:: bash - $ export CROSS_COMPILE=aarch64-none-elf- + $ export CROSS_COMPILE=aarch64-linux-gnu- $ export BL31=../rkbin/bin/rk35/rk3568_bl31_v1.34.elf $ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3568_ddr_1056MHz_v1.13.bin $ make anbernic-rgxx3_defconfig @@ -40,7 +49,7 @@ Image installation ------------------ Write the ``u-boot-rockchip.bin`` to an SD card offset 32kb from the -start. +start. Please note that eMMC booting has not been tested at this time. .. code-block:: bash diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 4c555e1c9c1..dfbc27a86d6 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -84,7 +84,7 @@ List of mainline supported Rockchip boards: - Orange Pi RK3399 (orangepi-rk3399) - Pine64 RockPro64 (rockpro64-rk3399) - Radxa ROCK 4C+ (rock-4c-plus-rk3399) - - Radxa ROCK 4SE (rock-pi-4-rk3399) + - Radxa ROCK 4SE (rock-4se-rk3399) - Radxa ROCK Pi 4A/B/A+/B+ (rock-pi-4-rk3399) - Radxa ROCK Pi 4C (rock-pi-4c-rk3399) - Rockchip Evb-RK3399 (evb_rk3399) @@ -95,10 +95,12 @@ List of mainline supported Rockchip boards: * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) + - Hardkernel ODROID-M1 (odroid-m1-rk3568) * rk3588 - Rockchip EVB (evb-rk3588) - - Edgeble Neural Compute Module 6 SoM - Neu6a (neu6a-io-rk3588) + - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) + - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) - Radxa ROCK 5B (rock5b-rk3588) * rv1108 diff --git a/doc/board/siemens/iot2050.rst b/doc/board/siemens/iot2050.rst index 074d6aa15af..ee3c5c95846 100644 --- a/doc/board/siemens/iot2050.rst +++ b/doc/board/siemens/iot2050.rst @@ -66,17 +66,16 @@ U-Boot: .. code-block:: text - $ export ATF=/path/to/bl31.bin - $ export TEE=/path/to/tee-pager_v2.bin - - # configure for PG1 - $ make iot2050_pg1_defconfig - - # or configure for PG2 or the M.2 variant - $ make iot2050_pg2_defconfig + $ export BL31=/path/to/bl31.bin + $ export TEE=/path/to/tee-raw.bin + $ make iot2050_defconfig $ make +This will generate two different flash images: flash-p1.bin that targets the +first generation of IOT2050 devices and flash-pg2.bin that runs on PG2 +including M.2 devices. + Flashing -------- @@ -85,20 +84,20 @@ Via U-Boot: .. code-block:: text IOT2050> sf probe - IOT2050> load mmc 0:1 $loadaddr /path/to/flash.bin + IOT2050> load mmc 0:1 $loadaddr /path/to/flash-pgX.bin IOT2050> sf update $loadaddr 0x0 $filesize Via external programmer Dediprog SF100 or SF600: .. code-block:: text - $ dpcmd --vcc 2 -v -u flash.bin + $ dpcmd --vcc 2 -v -u flash-pgX.bin Signing (optional) ------------------ To enable verified boot for the firmware artifacts after the Siemens-managed -first-stage loader (seboot_pg*.bin), the following steps need to be taken +first-stage loader (seboot_pgX.bin), the following steps need to be taken before and after the build: Generate dtsi holding the public key @@ -131,8 +130,8 @@ Build U-Boot See related section above. -Sign flash.bin -^^^^^^^^^^^^^^ +Sign flash-pgX.bin +^^^^^^^^^^^^^^^^^^ In the build folder still containing artifacts from step 3, invoke: @@ -140,10 +139,10 @@ In the build folder still containing artifacts from step 3, invoke: tools/iot2050-sign-fw.sh /path/to/key.pem -Flash signed flash.bin -^^^^^^^^^^^^^^^^^^^^^^ +Flash signed flash-pgX.bin +^^^^^^^^^^^^^^^^^^^^^^^^^^ -The signing has happen in-place in flash.bin, thus the flashing procedure +The signing has happen in-place in flash-pgX.bin, thus the flashing procedure described above. M.2 slot configuration diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index 826fea71cc5..1dc91e7fce7 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -13,7 +13,9 @@ #include <ahci.h> #include <scsi.h> #include <sata.h> +#ifdef CONFIG_ARCH_OMAP2PLUS #include <asm/arch/sata.h> +#endif #include <asm/io.h> #include <generic-phy.h> @@ -72,12 +74,14 @@ static int dwc_ahci_probe(struct udevice *dev) return ret; } +#ifdef CONFIG_ARCH_OMAP2PLUS if (priv->wrapper_base) { u32 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; /* Enable SATA module, No Idle, No Standby */ writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG); } +#endif return ahci_probe_scsi(dev, (ulong)priv->base); } diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 6bdd96f35b5..0df82f59715 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -427,6 +427,7 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) break; case CLK_PCIEPHY0_REF: case CLK_PCIEPHY1_REF: + case CLK_PCIEPHY2_REF: return 0; default: return -ENOENT; diff --git a/drivers/core/read.c b/drivers/core/read.c index 5749473a6ca..49066b59cda 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -150,6 +150,17 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, return devfdt_get_addr_size_index(dev, index, size); } +void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size) +{ + fdt_addr_t addr = dev_read_addr_size_index(dev, index, size); + + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_sysmem(addr, 0); +} + void *dev_remap_addr_index(const struct udevice *dev, int index) { fdt_addr_t addr = dev_read_addr_index(dev, index); diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 5fcf6a6bfc3..274489ecbc6 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -525,7 +525,7 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, int pages_per_blk = mtd->erasesize / mtd->writesize; int ret = 0, i, boot_rom_mode = 0; dma_addr_t dma_data, dma_oob; - u32 reg; + u32 tmp; u8 *oob; nand_prog_page_begin_op(chip, page, 0, NULL, 0); @@ -552,6 +552,13 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, * * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... * + * The code here just swaps the first 4 bytes with the last + * 4 bytes without losing any data. + * + * The chip->oob_poi data layout: + * + * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 + * * Configure the ECC algorithm supported by the boot ROM. */ if (page < (pages_per_blk * rknand->boot_blks)) { @@ -561,21 +568,17 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, } for (i = 0; i < ecc->steps; i++) { - if (!i) { - reg = 0xFFFFFFFF; - } else { + if (!i) + oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; - reg = oob[0] | oob[1] << 8 | oob[2] << 16 | - oob[3] << 24; - } - if (!i && boot_rom_mode) - reg = (page & (pages_per_blk - 1)) * 4; + tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24; if (nfc->cfg->type == NFC_V9) - nfc->oob_buf[i] = reg; + nfc->oob_buf[i] = tmp; else - nfc->oob_buf[i * (oob_step / 4)] = reg; + nfc->oob_buf[i * (oob_step / 4)] = tmp; } dma_data = dma_map_single((void *)nfc->page_buf, @@ -720,12 +723,17 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, goto timeout_err; } - for (i = 1; i < ecc->steps; i++) { - oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + for (i = 0; i < ecc->steps; i++) { + if (!i) + oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + if (nfc->cfg->type == NFC_V9) tmp = nfc->oob_buf[i]; else tmp = nfc->oob_buf[i * (oob_step / 4)]; + *oob++ = (u8)tmp; *oob++ = (u8)(tmp >> 8); *oob++ = (u8)(tmp >> 16); diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c index 6b59b5fcd26..43baa699619 100644 --- a/drivers/net/ksz9477.c +++ b/drivers/net/ksz9477.c @@ -16,6 +16,10 @@ #include <asm-generic/gpio.h> +/* Used with variable features to indicate capabilities. */ +#define NEW_XMII BIT(1) +#define IS_9893 BIT(2) + /* Global registers */ /* Chip ID */ @@ -41,6 +45,13 @@ #define PORT_RMII_SEL 0x1 #define PORT_GMII_SEL 0x2 #define PORT_MII_SEL 0x3 +/* S1 */ +#define PORT_MII_1000MBIT_S1 BIT(6) +/* S1 */ +#define PORT_MII_SEL_S1 0x0 +#define PORT_RMII_SEL_S1 0x1 +#define PORT_GMII_SEL_S1 0x2 +#define PORT_RGMII_SEL_S1 0x3 /* Port MSTP State Register */ #define REG_PORT_MSTP_STATE 0x0b04 @@ -62,6 +73,8 @@ struct ksz_dsa_priv { struct udevice *dev; + + u32 features; /* chip specific features */ }; static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val) @@ -284,6 +297,60 @@ U_BOOT_DRIVER(ksz_mdio) = { .plat_auto = sizeof(struct mdio_perdev_priv), }; +static void ksz9477_set_gbit(struct ksz_dsa_priv *priv, bool gbit, u8 *data) +{ + if (priv->features & NEW_XMII) { + if (gbit) + *data &= ~PORT_MII_NOT_1GBIT; + else + *data |= PORT_MII_NOT_1GBIT; + } else { + if (gbit) + *data |= PORT_MII_1000MBIT_S1; + else + *data &= ~PORT_MII_1000MBIT_S1; + } +} + +static void ksz9477_set_xmii(struct ksz_dsa_priv *priv, int mode, u8 *data) +{ + u8 xmii; + + if (priv->features & NEW_XMII) { + switch (mode) { + case 0: + xmii = PORT_MII_SEL; + break; + case 1: + xmii = PORT_RMII_SEL; + break; + case 2: + xmii = PORT_GMII_SEL; + break; + default: + xmii = PORT_RGMII_SEL; + break; + } + } else { + switch (mode) { + case 0: + xmii = PORT_MII_SEL_S1; + break; + case 1: + xmii = PORT_RMII_SEL_S1; + break; + case 2: + xmii = PORT_GMII_SEL_S1; + break; + default: + xmii = PORT_RGMII_SEL_S1; + break; + } + } + *data &= ~PORT_MII_SEL_M; + *data |= xmii; +} + static int ksz_port_setup(struct udevice *dev, int port, phy_interface_t interface) { @@ -293,9 +360,11 @@ static int ksz_port_setup(struct udevice *dev, int port, dev_dbg(dev, "%s P%d %s\n", __func__, port + 1, (port == pdata->cpu_port) ? "cpu" : ""); + struct ksz_dsa_priv *priv = dev_get_priv(dev); if (port != pdata->cpu_port) { - /* phy port: config errata and leds */ - ksz_phy_errata_setup(dev, port); + if (priv->features & NEW_XMII) + /* phy port: config errata and leds */ + ksz_phy_errata_setup(dev, port); } else { /* cpu port: configure MAC interface mode */ ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); @@ -303,24 +372,20 @@ static int ksz_port_setup(struct udevice *dev, int port, phy_string_for_interface(interface)); switch (interface) { case PHY_INTERFACE_MODE_MII: - data8 &= ~PORT_MII_SEL_M; - data8 |= PORT_MII_SEL; - data8 |= PORT_MII_NOT_1GBIT; + ksz9477_set_xmii(priv, 0, &data8); + ksz9477_set_gbit(priv, false, &data8); break; case PHY_INTERFACE_MODE_RMII: - data8 &= ~PORT_MII_SEL_M; - data8 |= PORT_RMII_SEL; - data8 |= PORT_MII_NOT_1GBIT; + ksz9477_set_xmii(priv, 1, &data8); + ksz9477_set_gbit(priv, false, &data8); break; case PHY_INTERFACE_MODE_GMII: - data8 &= ~PORT_MII_SEL_M; - data8 |= PORT_GMII_SEL; - data8 &= ~PORT_MII_NOT_1GBIT; + ksz9477_set_xmii(priv, 2, &data8); + ksz9477_set_gbit(priv, true, &data8); break; default: - data8 &= ~PORT_MII_SEL_M; - data8 |= PORT_RGMII_SEL; - data8 &= ~PORT_MII_NOT_1GBIT; + ksz9477_set_xmii(priv, 3, &data8); + ksz9477_set_gbit(priv, true, &data8); data8 &= ~PORT_RGMII_ID_IG_ENABLE; data8 &= ~PORT_RGMII_ID_EG_ENABLE; if (interface == PHY_INTERFACE_MODE_RGMII_ID || @@ -329,6 +394,8 @@ static int ksz_port_setup(struct udevice *dev, int port, if (interface == PHY_INTERFACE_MODE_RGMII_ID || interface == PHY_INTERFACE_MODE_RGMII_TXID) data8 |= PORT_RGMII_ID_EG_ENABLE; + if (priv->features & IS_9893) + data8 &= ~PORT_MII_MAC_MODE; break; } ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8); @@ -479,10 +546,17 @@ static int ksz_i2c_probe(struct udevice *dev) case 0x00989700: puts("KSZ9897S: "); break; + case 0x00989300: + puts("KSZ9893R: "); + break; default: dev_err(dev, "invalid chip id: 0x%08x\n", id); return -EINVAL; } + if ((id & 0xf00) == 0x300) + priv->features |= IS_9893; + else + priv->features |= NEW_XMII; /* probe mdio bus */ ret = ksz_probe_mdio(dev); @@ -503,6 +577,7 @@ static const struct udevice_id ksz_i2c_ids[] = { { .compatible = "microchip,ksz9897" }, { .compatible = "microchip,ksz9477" }, { .compatible = "microchip,ksz9567" }, + { .compatible = "microchip,ksz9893" }, { } }; diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index fb9f1e4c70d..0970449d0f9 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -155,6 +155,18 @@ static int adin_ext_write(struct phy_device *phydev, const u32 regnum, const u16 return phy_write(phydev, MDIO_DEVAD_NONE, ADIN1300_EXT_REG_DATA, val); } +static int adin_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return adin_ext_read(phydev, regnum); +} + +static int adin_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return adin_ext_write(phydev, regnum, val); +} + static int adin_config_clk_out(struct phy_device *phydev) { ofnode node = phy_get_ofnode(phydev); @@ -260,4 +272,6 @@ U_BOOT_PHY_DRIVER(ADIN1300) = { .config = adin1300_config, .startup = genphy_startup, .shutdown = genphy_shutdown, + .readext = adin_extread, + .writeext = adin_extwrite, }; diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index e13dbc94018..02660e4fbb4 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -41,8 +41,10 @@ endchoice config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 + imply DM_MDIO imply MISC_INIT_R imply MISC + imply SYSCON select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 523a4c9f919..51a8167d14a 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -15,13 +15,16 @@ #include <dm.h> #include <dm/device_compat.h> #include <dm/lists.h> +#include <dm/pinctrl.h> #include <dma-uclass.h> #include <dm/of_access.h> #include <miiphy.h> #include <net.h> #include <phy.h> #include <power-domain.h> +#include <regmap.h> #include <soc.h> +#include <syscon.h> #include <linux/bitops.h> #include <linux/soc/ti/ti-udma.h> @@ -100,8 +103,6 @@ struct am65_cpsw_common { fdt_addr_t cpsw_base; fdt_addr_t mdio_base; fdt_addr_t ale_base; - fdt_addr_t gmii_sel; - fdt_addr_t mac_efuse; struct clk fclk; struct power_domain pwrdmn; @@ -231,18 +232,37 @@ out: #define AM65_GMII_SEL_RGMII_IDMODE BIT(4) -static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, - phy_interface_t phy_mode, int slave) +static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, + phy_interface_t phy_mode) { - struct am65_cpsw_common *common = priv->cpsw_common; - fdt_addr_t gmii_sel = common->gmii_sel + AM65_GMII_SEL_PORT_OFFS(slave); - u32 reg; - u32 mode = 0; + struct udevice *dev = priv->dev; + u32 offset, reg, phandle; bool rgmii_id = false; + fdt_addr_t gmii_sel; + u32 mode = 0; + ofnode node; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle); + if (ret) + return ret; + + ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset); + if (ret) + return ret; + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) + return -ENODEV; + + gmii_sel = ofnode_get_addr(node); + if (gmii_sel == FDT_ADDR_T_NONE) + return -ENODEV; + gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset); reg = readl(gmii_sel); - dev_dbg(common->dev, "old gmii_sel: %08x\n", reg); + dev_dbg(dev, "old gmii_sel: %08x\n", reg); switch (phy_mode) { case PHY_INTERFACE_MODE_RMII: @@ -261,7 +281,7 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, break; default: - dev_warn(common->dev, + dev_warn(dev, "Unsupported PHY mode: %u. Defaulting to MII.\n", phy_mode); /* fallthrough */ @@ -274,15 +294,19 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, mode |= AM65_GMII_SEL_RGMII_IDMODE; reg = mode; - dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", + dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", phy_mode, reg); writel(reg, gmii_sel); reg = readl(gmii_sel); - if (reg != mode) - dev_err(common->dev, + if (reg != mode) { + dev_err(dev, "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n", mode, reg); + return 0; + } + + return 0; } static int am65_cpsw_start(struct udevice *dev) @@ -516,24 +540,45 @@ static void am65_cpsw_stop(struct udevice *dev) common->started = false; } +static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev, + int slave, u8 *mac_addr) +{ + u32 mac_lo, mac_hi, offset; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse"); + if (IS_ERR(syscon)) { + if (PTR_ERR(syscon) == -ENODEV) + return 0; + return PTR_ERR(syscon); + } + + ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset); + if (ret) + return ret; + + regmap_read(syscon, offset, &mac_lo); + regmap_read(syscon, offset + 4, &mac_hi); + + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; + + return 0; +} + static int am65_cpsw_read_rom_hwaddr(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); - struct am65_cpsw_common *common = priv->cpsw_common; struct eth_pdata *pdata = dev_get_plat(dev); - u32 mac_hi, mac_lo; - - if (common->mac_efuse == FDT_ADDR_T_NONE) - return -1; - mac_lo = readl(common->mac_efuse); - mac_hi = readl(common->mac_efuse + 4); - pdata->enetaddr[0] = (mac_hi >> 8) & 0xff; - pdata->enetaddr[1] = mac_hi & 0xff; - pdata->enetaddr[2] = (mac_lo >> 24) & 0xff; - pdata->enetaddr[3] = (mac_lo >> 16) & 0xff; - pdata->enetaddr[4] = (mac_lo >> 8) & 0xff; - pdata->enetaddr[5] = mac_lo & 0xff; + am65_cpsw_am654_get_efuse_macid(dev, + priv->port_id, + pdata->enetaddr); return 0; } @@ -561,14 +606,62 @@ static const struct soc_attr k3_mdio_soc_data[] = { { /* sentinel */ }, }; +static ofnode am65_cpsw_find_mdio(ofnode parent) +{ + ofnode node; + + ofnode_for_each_subnode(node, parent) + if (ofnode_device_is_compatible(node, "ti,cpsw-mdio")) + return node; + + return ofnode_null(); +} + +static int am65_cpsw_mdio_setup(struct udevice *dev) +{ + struct am65_cpsw_priv *priv = dev_get_priv(dev); + struct am65_cpsw_common *cpsw_common = priv->cpsw_common; + struct udevice *mdio_dev; + ofnode mdio; + int ret; + + mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev)); + if (!ofnode_valid(mdio)) + return 0; + + /* + * The MDIO controller is represented in the DT binding by a + * subnode of the MAC controller. + * + * We don't have a DM driver for the MDIO device yet, and thus any + * pinctrl setting on its node will be ignored. + * + * However, we do need to make sure the pins states tied to the + * MDIO node are configured properly. Fortunately, the core DM + * does that for use when we get a device, so we can work around + * that whole issue by just requesting a dummy MDIO driver to + * probe, and our pins will get muxed. + */ + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev); + if (ret) + return ret; + + return 0; +} + static int am65_cpsw_mdio_init(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct am65_cpsw_common *cpsw_common = priv->cpsw_common; + int ret; if (!priv->has_phy || cpsw_common->bus) return 0; + ret = am65_cpsw_mdio_setup(dev); + if (ret) + return ret; + cpsw_common->bus = cpsw_mdio_init(dev->name, cpsw_common->mdio_base, cpsw_common->bus_freq, @@ -686,7 +779,9 @@ static int am65_cpsw_port_probe(struct udevice *dev) if (ret) goto out; - am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface); + if (ret) + goto out; ret = am65_cpsw_mdio_init(dev); if (ret) @@ -710,8 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE) return -EINVAL; - cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse"); - /* no err check - optional */ ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0); if (ret) { @@ -783,19 +876,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev) AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET; } - node = dev_read_subnode(dev, "cpsw-phy-sel"); - if (!ofnode_valid(node)) { - dev_err(dev, "can't find cpsw-phy-sel\n"); - ret = -ENOENT; - goto out; - } - - cpsw_common->gmii_sel = ofnode_get_addr(node); - if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) { - dev_err(dev, "failed to get gmii_sel base\n"); - goto out; - } - cpsw_common->bus_freq = dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF); @@ -837,3 +917,14 @@ U_BOOT_DRIVER(am65_cpsw_nuss_port) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE, }; + +static const struct udevice_id am65_cpsw_mdio_ids[] = { + { .compatible = "ti,cpsw-mdio" }, + { } +}; + +U_BOOT_DRIVER(am65_cpsw_mdio) = { + .name = "am65_cpsw_mdio", + .id = UCLASS_MDIO, + .of_match = am65_cpsw_mdio_ids, +}; diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 9f8b016d114..74fb6df412c 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie, /* * Not accessing root port configuration space? - * Region #0 is used for Outbound CFG space access. + * Region #1 is used for Outbound CFG space access. * Direction = Outbound - * Region Index = 0 + * Region Index = 1 */ d = PCI_MASK_BUS(d); d = PCI_ADD_BUS(bus, d); @@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci) pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */ pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */ } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { - pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); - pci->cfg_size = pci->io.size; + if (!pci->cfg_base) { + pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); + pci->cfg_size = pci->io.size; + } } else { dev_err(pci->dev, "invalid flags type!\n"); } diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6da618055cb..1a35fae5c3a 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -61,8 +61,7 @@ struct rk_pcie { #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 #define PCIE_CLIENT_DBF_EN 0xffff0003 -/* Parameters for the waiting for #perst signal */ -#define MACRO_US 1000 +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { @@ -161,6 +160,12 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) { dw_pcie_dbi_write_enable(&pci->dw, true); + /* Disable BAR 0 and BAR 1 */ + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + + PCI_BASE_ADDRESS_0); + writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + + PCI_BASE_ADDRESS_1); + clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, TARGET_LINK_SPEED_MASK, cap_speed); @@ -242,43 +247,46 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) /* DW pre link configurations */ rk_pcie_configure(priv, cap_speed); - /* Rest the device */ - if (dm_gpio_is_valid(&priv->rst_gpio)) { - dm_gpio_set_value(&priv->rst_gpio, 0); - /* - * Minimal is 100ms from spec but we see - * some wired devices need much more, such as 600ms. - * Add a enough delay to cover all cases. - */ - udelay(MACRO_US * 1000); - dm_gpio_set_value(&priv->rst_gpio, 1); - } - rk_pcie_disable_ltssm(priv); rk_pcie_link_status_clear(priv); rk_pcie_enable_debug(priv); + /* Reset the device */ + if (dm_gpio_is_valid(&priv->rst_gpio)) + dm_gpio_set_value(&priv->rst_gpio, 0); + /* Enable LTSSM */ rk_pcie_enable_ltssm(priv); - for (retries = 0; retries < 5; retries++) { - if (is_link_up(priv)) { - dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n", - rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); - rk_pcie_debug_dump(priv); - return 0; - } - - dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n", - rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); - rk_pcie_debug_dump(priv); - udelay(MACRO_US * 1000); + /* + * PCIe requires the refclk to be stable for 100ms prior to releasing + * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI + * Express Card Electromechanical Specification, 1.1. However, we don't + * know if the refclk is coming from RC's PHY or external OSC. If it's + * from RC, so enabling LTSSM is the just right place to release #PERST. + */ + mdelay(100); + if (dm_gpio_is_valid(&priv->rst_gpio)) + dm_gpio_set_value(&priv->rst_gpio, 1); + + /* Check if the link is up or not */ + for (retries = 0; retries < 10; retries++) { + if (is_link_up(priv)) + break; + + mdelay(100); + } + + if (retries >= 10) { + dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", + dev_seq(priv->dw.dev)); + return -EIO; } - dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev)); - /* Link maybe in Gen switch recovery but we need to wait more 1s */ - udelay(MACRO_US * 1000); - return -EIO; + dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n", + rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); + rk_pcie_debug_dump(priv); + return 0; } static int rockchip_pcie_init_port(struct udevice *dev) @@ -287,22 +295,23 @@ static int rockchip_pcie_init_port(struct udevice *dev) u32 val; struct rk_pcie *priv = dev_get_priv(dev); - /* Set power and maybe external ref clk input */ - if (priv->vpcie3v3) { - ret = regulator_set_value(priv->vpcie3v3, 3300000); - if (ret) { - dev_err(priv->dw.dev, "failed to enable vpcie3v3 (ret=%d)\n", - ret); - return ret; - } + ret = reset_assert_bulk(&priv->rsts); + if (ret) { + dev_err(dev, "failed to assert resets (ret=%d)\n", ret); + return ret; } - udelay(MACRO_US * 1000); + /* Set power and maybe external ref clk input */ + ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret); + return ret; + } ret = generic_phy_init(&priv->phy); if (ret) { dev_err(dev, "failed to init phy (ret=%d)\n", ret); - return ret; + goto err_disable_regulator; } ret = generic_phy_power_on(&priv->phy); @@ -345,6 +354,8 @@ err_power_off_phy: generic_phy_power_off(&priv->phy); err_exit_phy: generic_phy_exit(&priv->phy); +err_disable_regulator: + regulator_set_enable_if_allowed(priv->vpcie3v3, false); return ret; } @@ -366,6 +377,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); + priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2, + &priv->dw.cfg_size); + if (!priv->dw.cfg_base) + return -EINVAL; + + dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base); + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->rst_gpio, GPIOD_IS_OUT); if (ret) { diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index f87ca8c3106..0247d93ab40 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3 It could support PCIe Gen3 single root complex, and could also be able splited into multiple combinations of lanes. +config PHY_ROCKCHIP_USBDP + tristate "Rockchip USBDP COMBO PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip USB3.0/DP + combo PHY with Samsung IP block. config PHY_ROCKCHIP_TYPEC bool "Rockchip TYPEC PHY Driver" diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 25a803a8a86..7fdbd107976 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o +obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c new file mode 100644 index 00000000000..baf92529348 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dm/of.h> +#include <dm/of_access.h> +#include <generic-phy.h> +#include <linux/bitfield.h> +#include <linux/usb/ch9.h> +#include <linux/usb/otg.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> + +#include <linux/usb/phy-rockchip-usbdp.h> + +#define BIT_WRITEABLE_SHIFT 16 + +enum { + UDPHY_MODE_NONE = 0, + UDPHY_MODE_USB = BIT(0), + UDPHY_MODE_DP = BIT(1), + UDPHY_MODE_DP_USB = BIT(1) | BIT(0), +}; + +struct udphy_grf_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +/** + * struct reg_sequence - An individual write from a sequence of writes. + * + * @reg: Register address. + * @def: Register value. + * @delay_us: Delay to be applied after the register write in microseconds + * + * Register/value pairs for sequences of writes with an optional delay in + * microseconds to be applied after each write. + */ +struct reg_sequence { + unsigned int reg; + unsigned int def; + unsigned int delay_us; +}; + +struct udphy_grf_cfg { + /* u2phy-grf */ + struct udphy_grf_reg bvalid_phy_con; + struct udphy_grf_reg bvalid_grf_con; + + /* usb-grf */ + struct udphy_grf_reg usb3otg0_cfg; + struct udphy_grf_reg usb3otg1_cfg; + + /* usbdpphy-grf */ + struct udphy_grf_reg low_pwrn; + struct udphy_grf_reg rx_lfps; +}; + +struct rockchip_udphy; + +struct rockchip_udphy_cfg { + /* resets to be requested */ + const char * const *rst_list; + int num_rsts; + + struct udphy_grf_cfg grfcfg; + int (*combophy_init)(struct rockchip_udphy *udphy); +}; + +struct rockchip_udphy { + struct udevice *dev; + struct regmap *pma_regmap; + struct regmap *u2phygrf; + struct regmap *udphygrf; + struct regmap *usbgrf; + struct regmap *vogrf; + + /* clocks and rests */ + struct reset_ctl *rsts; + + /* PHY status management */ + bool flip; + bool mode_change; + u8 mode; + u8 status; + + /* utilized for USB */ + bool hs; /* flag for high-speed */ + + /* utilized for DP */ + struct gpio_desc *sbu1_dc_gpio; + struct gpio_desc *sbu2_dc_gpio; + u32 lane_mux_sel[4]; + u32 dp_lane_sel[4]; + u32 dp_aux_dout_sel; + u32 dp_aux_din_sel; + int id; + + /* PHY const config */ + const struct rockchip_udphy_cfg *cfgs; +}; + +static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { + {0x0090, 0x68}, {0x0094, 0x68}, + {0x0128, 0x24}, {0x012c, 0x44}, + {0x0130, 0x3f}, {0x0134, 0x44}, + {0x015c, 0xa9}, {0x0160, 0x71}, + {0x0164, 0x71}, {0x0168, 0xa9}, + {0x0174, 0xa9}, {0x0178, 0x71}, + {0x017c, 0x71}, {0x0180, 0xa9}, + {0x018c, 0x41}, {0x0190, 0x00}, + {0x0194, 0x05}, {0x01ac, 0x2a}, + {0x01b0, 0x17}, {0x01b4, 0x17}, + {0x01b8, 0x2a}, {0x01c8, 0x04}, + {0x01cc, 0x08}, {0x01d0, 0x08}, + {0x01d4, 0x04}, {0x01d8, 0x20}, + {0x01dc, 0x01}, {0x01e0, 0x09}, + {0x01e4, 0x03}, {0x01f0, 0x29}, + {0x01f4, 0x02}, {0x01f8, 0x02}, + {0x01fc, 0x29}, {0x0208, 0x2a}, + {0x020c, 0x17}, {0x0210, 0x17}, + {0x0214, 0x2a}, {0x0224, 0x20}, + {0x03f0, 0x0d}, {0x03f4, 0x09}, + {0x03f8, 0x09}, {0x03fc, 0x0d}, + {0x0404, 0x0e}, {0x0408, 0x14}, + {0x040c, 0x14}, {0x0410, 0x3b}, + {0x0ce0, 0x68}, {0x0ce8, 0xd0}, + {0x0cf0, 0x87}, {0x0cf8, 0x70}, + {0x0d00, 0x70}, {0x0d08, 0xa9}, + {0x1ce0, 0x68}, {0x1ce8, 0xd0}, + {0x1cf0, 0x87}, {0x1cf8, 0x70}, + {0x1d00, 0x70}, {0x1d08, 0xa9}, + {0x0a3c, 0xd0}, {0x0a44, 0xd0}, + {0x0a48, 0x01}, {0x0a4c, 0x0d}, + {0x0a54, 0xe0}, {0x0a5c, 0xe0}, + {0x0a64, 0xa8}, {0x1a3c, 0xd0}, + {0x1a44, 0xd0}, {0x1a48, 0x01}, + {0x1a4c, 0x0d}, {0x1a54, 0xe0}, + {0x1a5c, 0xe0}, {0x1a64, 0xa8} +}; + +static const struct reg_sequence rk3588_udphy_init_sequence[] = { + {0x0104, 0x44}, {0x0234, 0xE8}, + {0x0248, 0x44}, {0x028C, 0x18}, + {0x081C, 0xE5}, {0x0878, 0x00}, + {0x0994, 0x1C}, {0x0AF0, 0x00}, + {0x181C, 0xE5}, {0x1878, 0x00}, + {0x1994, 0x1C}, {0x1AF0, 0x00}, + {0x0428, 0x60}, {0x0D58, 0x33}, + {0x1D58, 0x33}, {0x0990, 0x74}, + {0x0D64, 0x17}, {0x08C8, 0x13}, + {0x1990, 0x74}, {0x1D64, 0x17}, + {0x18C8, 0x13}, {0x0D90, 0x40}, + {0x0DA8, 0x40}, {0x0DC0, 0x40}, + {0x0DD8, 0x40}, {0x1D90, 0x40}, + {0x1DA8, 0x40}, {0x1DC0, 0x40}, + {0x1DD8, 0x40}, {0x03C0, 0x30}, + {0x03C4, 0x06}, {0x0E10, 0x00}, + {0x1E10, 0x00}, {0x043C, 0x0F}, + {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, + {0x0D34, 0x0F}, {0x1D34, 0x0F}, + {0x08FC, 0x2A}, {0x0914, 0x28}, + {0x0A30, 0x03}, {0x0E38, 0x05}, + {0x0ECC, 0x27}, {0x0ED0, 0x22}, + {0x0ED4, 0x26}, {0x18FC, 0x2A}, + {0x1914, 0x28}, {0x1A30, 0x03}, + {0x1E38, 0x05}, {0x1ECC, 0x27}, + {0x1ED0, 0x22}, {0x1ED4, 0x26}, + {0x0048, 0x0F}, {0x0060, 0x3C}, + {0x0064, 0xF7}, {0x006C, 0x20}, + {0x0070, 0x7D}, {0x0074, 0x68}, + {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, + {0x0440, 0x3F}, {0x10D4, 0x08}, + {0x20D4, 0x08}, {0x00D4, 0x30}, + {0x0024, 0x6e}, +}; + +static inline int grfreg_write(struct regmap *base, + const struct udphy_grf_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static int __regmap_multi_reg_write(struct regmap *map, + const struct reg_sequence *regs, + int num_regs) +{ + int i, ret = 0; + + for (i = 0; i < num_regs; i++) { + ret = regmap_write(map, regs[i].reg, regs[i].def); + + if (regs[i].delay_us) + udelay(regs[i].delay_us); + } + + return ret; +} + +static int udphy_clk_init(struct rockchip_udphy *udphy, struct udevice *dev) +{ + return 0; +} + +static int udphy_reset_init(struct rockchip_udphy *udphy, struct udevice *dev) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + int ret; + + udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, + sizeof(*udphy->rsts), GFP_KERNEL); + if (!udphy->rsts) + return -ENOMEM; + + for (idx = 0; idx < cfg->num_rsts; idx++) { + const char *name = cfg->rst_list[idx]; + + ret = reset_get_by_name(dev, name, &udphy->rsts[idx]); + if (ret) { + dev_err(dev, "failed to get %s reset\n", name); + goto err; + } + + reset_assert(&udphy->rsts[idx]); + } + + return 0; + +err: + devm_kfree(dev, udphy->rsts); + return ret; +} + +static int udphy_get_rst_idx(const char * const *list, int num, char *name) +{ + int idx; + + for (idx = 0; idx < num; idx++) { + if (!strcmp(list[idx], name)) + return idx; + } + + return -EINVAL; +} + +static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); + if (idx < 0) + return idx; + + return reset_assert(&udphy->rsts[idx]); +} + +static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int idx; + + idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); + if (idx < 0) + return idx; + + return reset_deassert(&udphy->rsts[idx]); +} + +static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + const struct udphy_grf_reg *preg; + + preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; + grfreg_write(udphy->usbgrf, preg, disable); +} + +__maybe_unused +static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); +} + +/* + * In usb/dp combo phy driver, here are 2 ways to mapping lanes. + * + * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) + * --------------------------------------------------------------------------- + * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 + * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * C/E(Normal) dpln3 dpln2 dpln0 dpln1 + * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 + * D/F(Normal) usbrx usbtx dpln0 dpln1 + * D/F(Flip ) dpln0 dpln1 usbrx usbtx + * A(Normal ) dpln3 dpln1 dpln2 dpln0 + * A(Flip ) dpln2 dpln0 dpln3 dpln1 + * B(Normal ) usbrx usbtx dpln1 dpln0 + * B(Flip ) dpln1 dpln0 usbrx usbtx + * --------------------------------------------------------------------------- + * + * 2 Mapping the lanes in dtsi + * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 + * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 + * --------------------------------------------------------------------------- + * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1> dpln0 dpln1 usbrx usbtx + * <2 3> usbrx usbtx dpln0 dpln1 + * --------------------------------------------------------------------------- + */ + +__maybe_unused +static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) +{ + if (udphy->flip) { + udphy->dp_lane_sel[0] = 0; + udphy->dp_lane_sel[1] = 1; + udphy->dp_lane_sel[2] = 3; + udphy->dp_lane_sel[3] = 2; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; + } else { + udphy->dp_lane_sel[0] = 2; + udphy->dp_lane_sel[1] = 3; + udphy->dp_lane_sel[2] = 1; + udphy->dp_lane_sel[3] = 0; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; + } + + udphy->mode = UDPHY_MODE_DP_USB; + + return 0; +} + +static int udphy_setup(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret = 0; + + if (cfg->combophy_init) { + ret = cfg->combophy_init(udphy); + if (ret) + dev_err(udphy->dev, "failed to init usbdp combophy\n"); + } + + return ret; +} + +static int udphy_disable(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int i; + + for (i = 0; i < cfg->num_rsts; i++) + reset_assert(&udphy->rsts[i]); + + return 0; +} + +static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, + const struct device_node *np) +{ + struct property *prop; + int ret, i, len, num_lanes; + + prop = of_find_property(np, "rockchip,dp-lane-mux", &len); + if (!prop) { + dev_dbg(udphy->dev, + "failed to find dp lane mux, following dp alt mode\n"); + udphy->mode = UDPHY_MODE_USB; + return 0; + } + + num_lanes = len / sizeof(u32); + + if (num_lanes != 2 && num_lanes != 4) { + dev_err(udphy->dev, "invalid number of lane mux\n"); + return -EINVAL; + } + + ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, + num_lanes); + if (ret) { + dev_err(udphy->dev, "get dp lane mux failed\n"); + return -EINVAL; + } + + for (i = 0; i < num_lanes; i++) { + int j; + + if (udphy->dp_lane_sel[i] > 3) { + dev_err(udphy->dev, + "lane mux between 0 and 3, exceeding the range\n"); + return -EINVAL; + } + + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; + + for (j = i + 1; j < num_lanes; j++) { + if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { + dev_err(udphy->dev, + "set repeat lane mux value\n"); + return -EINVAL; + } + } + } + + udphy->mode = UDPHY_MODE_DP; + if (num_lanes == 2) + udphy->mode |= UDPHY_MODE_USB; + + return 0; +} + +static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) +{ + const struct device_node *np = ofnode_to_np(dev_ofnode(dev)); + enum usb_device_speed maximum_speed; + int ret; + + udphy->u2phygrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,u2phy-grf"); + if (IS_ERR(udphy->u2phygrf)) { + if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { + dev_warn(dev, "missing u2phy-grf dt node\n"); + udphy->u2phygrf = NULL; + } else { + return PTR_ERR(udphy->u2phygrf); + } + } + + udphy->udphygrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,usbdpphy-grf"); + if (IS_ERR(udphy->udphygrf)) { + if (PTR_ERR(udphy->udphygrf) == -ENODEV) { + dev_warn(dev, "missing usbdpphy-grf dt node\n"); + udphy->udphygrf = NULL; + } else { + return PTR_ERR(udphy->udphygrf); + } + } + + udphy->usbgrf = syscon_regmap_lookup_by_phandle(dev, + "rockchip,usb-grf"); + if (IS_ERR(udphy->usbgrf)) { + if (PTR_ERR(udphy->usbgrf) == -ENODEV) { + dev_warn(dev, "missing usb-grf dt node\n"); + udphy->usbgrf = NULL; + } else { + return PTR_ERR(udphy->usbgrf); + } + } + + udphy->vogrf = syscon_regmap_lookup_by_phandle(dev, "rockchip,vo-grf"); + if (IS_ERR(udphy->vogrf)) { + if (PTR_ERR(udphy->vogrf) == -ENODEV) { + dev_warn(dev, "missing vo-grf dt node\n"); + udphy->vogrf = NULL; + } else { + return PTR_ERR(udphy->vogrf); + } + } + + ret = udphy_parse_lane_mux_data(udphy, np); + if (ret) + return ret; + + if (dev_read_prop(dev, "maximum-speed", NULL)) { + maximum_speed = usb_get_maximum_speed(dev_ofnode(dev)); + udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; + } + + ret = udphy_clk_init(udphy, dev); + if (ret) + return ret; + + ret = udphy_reset_init(udphy, dev); + if (ret) + return ret; + + return 0; +} + +static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + return 0; + } + + if (udphy->status == UDPHY_MODE_NONE) { + udphy->mode_change = false; + ret = udphy_setup(udphy); + if (ret) + return ret; + + if (udphy->mode & UDPHY_MODE_USB) + udphy_u3_port_disable(udphy, false); + } else if (udphy->mode_change) { + udphy->mode_change = false; + udphy->status = UDPHY_MODE_NONE; + if (udphy->mode == UDPHY_MODE_DP) + udphy_u3_port_disable(udphy, true); + + ret = udphy_disable(udphy); + if (ret) + return ret; + ret = udphy_setup(udphy); + if (ret) + return ret; + } + + udphy->status |= mode; + + return 0; +} + +static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); + return 0; + } + + if (!udphy->status) + return 0; + + udphy->status &= ~mode; + + if (udphy->status == UDPHY_MODE_NONE) { + ret = udphy_disable(udphy); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_u3phy_init(struct phy *phy) +{ + struct udevice *parent = phy->dev->parent; + struct rockchip_udphy *udphy = dev_get_priv(parent); + + /* DP only or high-speed, disable U3 port */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + udphy_u3_port_disable(udphy, true); + return 0; + } + + return udphy_power_on(udphy, UDPHY_MODE_USB); +} + +static int rockchip_u3phy_exit(struct phy *phy) +{ + struct udevice *parent = phy->dev->parent; + struct rockchip_udphy *udphy = dev_get_priv(parent); + + /* DP only or high-speed */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + return 0; + + return udphy_power_off(udphy, UDPHY_MODE_USB); +} + +static const struct phy_ops rockchip_u3phy_ops = { + .init = rockchip_u3phy_init, + .exit = rockchip_u3phy_exit, +}; + +int rockchip_u3phy_uboot_init(void) +{ + struct udevice *udev; + struct rockchip_udphy *udphy; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PHY, + DM_DRIVER_GET(rockchip_udphy_u3_port), + &udev); + if (ret) { + pr_err("%s: get u3-port failed: %d\n", __func__, ret); + return ret; + } + + /* DP only or high-speed, disable U3 port */ + udphy = dev_get_priv(udev->parent); + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + udphy_u3_port_disable(udphy, true); + return 0; + } + + return udphy_power_on(udphy, UDPHY_MODE_USB); +} + +static int rockchip_udphy_probe(struct udevice *dev) +{ + const struct device_node *np = ofnode_to_np(dev_ofnode(dev)); + struct rockchip_udphy *udphy = dev_get_priv(dev); + const struct rockchip_udphy_cfg *phy_cfgs; + int id, ret; + + udphy->dev = dev; + + id = of_alias_get_id(np, "usbdp"); + if (id < 0) + id = 0; + udphy->id = id; + + phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev); + if (!phy_cfgs) { + dev_err(dev, "unable to get phy_cfgs\n"); + return -EINVAL; + } + udphy->cfgs = phy_cfgs; + + ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap); + if (ret) + return ret; + udphy->pma_regmap->ranges[0].start += UDPHY_PMA; + + ret = udphy_parse_dt(udphy, dev); + if (ret) + return ret; + + return 0; +} + +static int rockchip_udphy_bind(struct udevice *parent) +{ + struct udevice *child; + ofnode subnode; + const char *node_name; + int ret; + + dev_for_each_subnode(subnode, parent) { + if (!ofnode_valid(subnode)) { + printf("%s: no subnode for %s", __func__, parent->name); + return -ENXIO; + } + + node_name = ofnode_get_name(subnode); + debug("%s: subnode %s\n", __func__, node_name); + + /* if there is no match, continue */ + if (strcasecmp(node_name, "usb3-port")) + continue; + + /* node name is usb3-port */ + ret = device_bind_driver_to_node(parent, + "rockchip_udphy_u3_port", + node_name, subnode, &child); + if (ret) { + printf("%s: '%s' cannot bind its driver\n", + __func__, node_name); + return ret; + } + } + + return 0; +} + +static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) +{ + /* configure phy reference clock */ + return __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_24m_refclk_cfg, + ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); +} + +static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) +{ + unsigned int val; + int ret; + + if (!(udphy->mode & UDPHY_MODE_USB)) + return 0; + + /* LCPLL check */ + ret = regmap_read_poll_timeout(udphy->pma_regmap, + CMN_ANA_LCPLL_DONE_OFFSET, + val, (val & CMN_ANA_LCPLL_AFC_DONE) && + (val & CMN_ANA_LCPLL_LOCK_DONE), + 200, 100); + if (ret) { + dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); + return ret; + } + + if (!udphy->flip) { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN0_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); + } else { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN2_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); + } + + return 0; +} + +static int rk3588_udphy_init(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret; + + /* enable rx lfps for usb */ + if (udphy->mode & UDPHY_MODE_USB) + grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); + + /* Step 1: power on pma and deassert apb rstn */ + grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); + + udphy_reset_deassert(udphy, "pma_apb"); + udphy_reset_deassert(udphy, "pcs_apb"); + + /* Step 2: set init sequence and phy refclk */ + ret = __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_init_sequence, + ARRAY_SIZE(rk3588_udphy_init_sequence)); + if (ret) { + dev_err(udphy->dev, "init sequence set error %d\n", ret); + goto assert_apb; + } + + ret = rk3588_udphy_refclk_set(udphy); + if (ret) { + dev_err(udphy->dev, "refclk set error %d\n", ret); + goto assert_apb; + } + + /* Step 3: configure lane mux */ + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, + CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_MUX_N(3), + udphy->lane_mux_sel[3]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(2), + udphy->lane_mux_sel[2]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(1), + udphy->lane_mux_sel[1]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(0), + udphy->lane_mux_sel[0]) | + FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); + + /* Step 4: deassert init rstn and wait for 200ns from datasheet */ + if (udphy->mode & UDPHY_MODE_USB) + udphy_reset_deassert(udphy, "init"); + + if (udphy->mode & UDPHY_MODE_DP) { + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_INIT_RSTN, + FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); + } + + udelay(1); + + /* Step 5: deassert cmn/lane rstn */ + if (udphy->mode & UDPHY_MODE_USB) { + udphy_reset_deassert(udphy, "cmn"); + udphy_reset_deassert(udphy, "lane"); + } + + /* Step 6: wait for lock done of pll */ + ret = rk3588_udphy_status_check(udphy); + if (ret) + goto assert_phy; + + return 0; + +assert_phy: + udphy_reset_assert(udphy, "init"); + udphy_reset_assert(udphy, "cmn"); + udphy_reset_assert(udphy, "lane"); + +assert_apb: + udphy_reset_assert(udphy, "pma_apb"); + udphy_reset_assert(udphy, "pcs_apb"); + + return ret; +} + +static const char * const rk3588_udphy_rst_l[] = { + "init", "cmn", "lane", "pcs_apb", "pma_apb" +}; + +static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), + .rst_list = rk3588_udphy_rst_l, + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, + .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .combophy_init = rk3588_udphy_init, +}; + +static const struct udevice_id rockchip_udphy_dt_match[] = { + { + .compatible = "rockchip,rk3588-usbdp-phy", + .data = (ulong)&rk3588_udphy_cfgs + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(rockchip_udphy_u3_port) = { + .name = "rockchip_udphy_u3_port", + .id = UCLASS_PHY, + .ops = &rockchip_u3phy_ops, +}; + +U_BOOT_DRIVER(rockchip_udphy) = { + .name = "rockchip_udphy", + .id = UCLASS_PHY, + .of_match = rockchip_udphy_dt_match, + .probe = rockchip_udphy_probe, + .bind = rockchip_udphy_bind, + .priv_auto = sizeof(struct rockchip_udphy), +}; diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index ad3b4b98d66..f7ddba8b45e 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -25,6 +25,7 @@ static int fixed_regulator_of_to_plat(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; struct regulator_common_plat *plat; + bool gpios; plat = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); @@ -33,7 +34,8 @@ static int fixed_regulator_of_to_plat(struct udevice *dev) uc_pdata->type = REGULATOR_TYPE_FIXED; - return regulator_common_of_to_plat(dev, plat, "gpio"); + gpios = dev_read_bool(dev, "gpios"); + return regulator_common_of_to_plat(dev, plat, gpios ? "gpios" : "gpio"); } static int fixed_regulator_get_value(struct udevice *dev) diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index aa2e4360c1b..9b6d97dae67 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -114,6 +114,7 @@ static const struct udevice_id omap_timer_ids[] = { { .compatible = "ti,am335x-timer" }, { .compatible = "ti,am4372-timer" }, { .compatible = "ti,omap5430-timer" }, + { .compatible = "ti,am654-timer" }, {} }; diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c index 117c3db21ac..0852b53ebed 100644 --- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c +++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c @@ -134,6 +134,32 @@ #define HS_RX_CONTROL_OF_LANE_2 0x84 #define HS_RX_CONTROL_OF_LANE_3 0x94 +#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) +#define DW_MIPI_NEEDS_GRF_CLK BIT(1) + +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_DSI0_LCDC_SEL BIT(0) +#define RK3399_DSI1_LCDC_SEL BIT(4) + +#define RK3399_GRF_SOC_CON22 0x6258 +#define RK3399_DSI0_TURNREQUEST (0xf << 12) +#define RK3399_DSI0_TURNDISABLE (0xf << 8) +#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) +#define RK3399_DSI0_FORCERXMODE (0xf << 0) + +#define RK3399_GRF_SOC_CON23 0x625c +#define RK3399_DSI1_TURNDISABLE (0xf << 12) +#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) +#define RK3399_DSI1_FORCERXMODE (0xf << 4) +#define RK3399_DSI1_ENABLE (0xf << 0) + +#define RK3399_GRF_SOC_CON24 0x6260 +#define RK3399_TXRX_MASTERSLAVEZ BIT(7) +#define RK3399_TXRX_ENABLECLK BIT(6) +#define RK3399_TXRX_BASEDIR BIT(5) +#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) +#define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) + #define RK3568_GRF_VO_CON2 0x0368 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) @@ -209,6 +235,8 @@ struct dw_rockchip_dsi_priv { struct clk *pclk; struct clk *ref; + struct clk *grf_clk; + struct clk *phy_cfg_clk; struct reset_ctl *rst; unsigned int lane_mbps; /* per lane */ u16 input_div; @@ -844,6 +872,28 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev) } } + if (cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { + priv->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(priv->phy_cfg_clk)) { + ret = PTR_ERR(priv->phy_cfg_clk); + dev_err(dev, "phy_cfg_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->phy_cfg_clk); + } + + if (cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { + priv->grf_clk = devm_clk_get(dev, "grf"); + if (IS_ERR(priv->grf_clk)) { + ret = PTR_ERR(priv->grf_clk); + dev_err(dev, "grf_clk clock get error %d\n", ret); + return ret; + } + + clk_enable(priv->grf_clk); + } + priv->rst = devm_reset_control_get_by_index(device->dev, 0); if (IS_ERR(priv->rst)) { ret = PTR_ERR(priv->rst); @@ -864,6 +914,52 @@ struct video_bridge_ops dw_mipi_dsi_rockchip_ops = { .set_backlight = dw_mipi_dsi_rockchip_set_bl, }; +static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { + { + .reg = 0xff960000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, + RK3399_DSI0_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | + RK3399_DSI0_TURNDISABLE | + RK3399_DSI0_FORCETXSTOPMODE | + RK3399_DSI0_FORCERXMODE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { + .reg = 0xff968000, + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, + RK3399_DSI1_LCDC_SEL), + + .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, + .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | + RK3399_DSI1_FORCETXSTOPMODE | + RK3399_DSI1_FORCERXMODE | + RK3399_DSI1_ENABLE), + + .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, + .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK, + RK3399_TXRX_MASTERSLAVEZ | + RK3399_TXRX_ENABLECLK | + RK3399_TXRX_BASEDIR), + + .enable_grf_reg = RK3399_GRF_SOC_CON23, + .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), + + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -887,6 +983,9 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { }; static const struct udevice_id dw_mipi_dsi_rockchip_dt_ids[] = { + { .compatible = "rockchip,rk3399-mipi-dsi", + .data = (long)&rk3399_chip_data, + }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = (long)&rk3568_chip_data, }, diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 2177e0dfe38..4968722d18f 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -15,6 +15,17 @@ #include <configs/ti_armv7_common.h> +/* + * This defines all MMC devices, even if the basic variant has no mmc1. + * The non-supported device will be removed from the boot targets during + * runtime, when that board was detected. + */ +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + BOOT_TARGET_USB(func) + #ifdef CONFIG_ENV_WRITEABLE_LIST #define CFG_ENV_FLAGS_LIST_STATIC \ "board_uuid:sw,board_name:sw,board_serial:sw,board_a5e:sw," \ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 630dfdc5b7f..5cdd87c0a17 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -9,26 +9,8 @@ #ifndef __CONFIG_K2E_EVM_H #define __CONFIG_K2E_EVM_H -#include <environment/ti/spi.h> - -/* U-Boot general configuration */ -#define ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=keystone-k2e-evm.dtb\0" \ - "name_mon=skern-k2e.bin\0" \ - "name_ubi=k2e-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2e-evm.gph\0" \ - "name_fs=arago-console-image-k2e-evm.cpio.gz\0" - #include <configs/ti_armv7_keystone2.h> -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - /* Network */ #define CFG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index d0634a99f49..2f25d393a37 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -9,53 +9,10 @@ #ifndef __CONFIG_K2G_EVM_H #define __CONFIG_K2G_EVM_H -#include <environment/ti/mmc.h> -#include <environment/ti/spi.h> - -/* U-Boot general configuration */ -#define ENV_KS2_BOARD_SETTINGS \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_PMMC_BOOT_ENV \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "boot=mmc\0" \ - "console=ttyS0,115200n8\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "rd_spec=-\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "findfdt="\ - "if test $board_name = 66AK2GGP; then " \ - "setenv name_fdt keystone-k2g-evm.dtb; " \ - "else if test $board_name = 66AK2GG1; then " \ - "setenv name_fdt keystone-k2g-evm.dtb; " \ - "else if test $board_name = 66AK2GIC; then " \ - "setenv name_fdt keystone-k2g-ice.dtb; " \ - "else if test $board_name = 66AK2GI1; then " \ - "setenv name_fdt keystone-k2g-ice.dtb; " \ - "else if test $name_fdt = undefined; then " \ - "echo WARNING: Could not determine device tree to use;"\ - "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ - "name_mon=skern-k2g.bin\0" \ - "name_ubi=k2g-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2g-evm.gph\0" \ - "init_mmc=run args_all args_mmc\0" \ - "init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} " \ - "${bootdir}/${name_fw_rd}; run set_rd_spec\0" \ - "soc_variant=k2g\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\ - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" \ - "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ - "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" - /* Network */ #define CFG_KSNET_CPSW_NUM_PORTS 2 #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ -#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS - #include <configs/ti_armv7_keystone2.h> #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index ed54be839ff..5e52bbb98f8 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -9,26 +9,8 @@ #ifndef __CONFIG_K2HK_EVM_H #define __CONFIG_K2HK_EVM_H -#include <environment/ti/spi.h> - -/* U-Boot general configuration */ -#define ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=keystone-k2hk-evm.dtb\0" \ - "name_mon=skern-k2hk.bin\0" \ - "name_ubi=k2hk-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ - "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" - #include <configs/ti_armv7_keystone2.h> -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - /* Network */ #define CFG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 69d42eaf9f1..199959fbd42 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -9,26 +9,8 @@ #ifndef __CONFIG_K2L_EVM_H #define __CONFIG_K2L_EVM_H -#include <environment/ti/spi.h> - -/* U-Boot general configuration */ -#define ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ - "name_fdt=keystone-k2l-evm.dtb\0" \ - "name_mon=skern-k2l.bin\0" \ - "name_ubi=k2l-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2l-evm.gph\0" \ - "name_fs=arago-console-image-k2l-evm.cpio.gz\0" - #include <configs/ti_armv7_keystone2.h> -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - /* Network */ #define CFG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/odroid_m1.h b/include/configs/odroid_m1.h new file mode 100644 index 00000000000..0d2e9fd94bf --- /dev/null +++ b/include/configs/odroid_m1.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ODROID_M1_H +#define __ODROID_M1_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "cramfsaddr=0x0c000000\0" + +#include <configs/rk3568_common.h> + +#endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 6fbd2679f09..13ed9011764 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -21,8 +21,9 @@ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ "kernel_addr_r=0x00280000\0" \ - "kernel_addr_c=0x03e80000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x03e80000\0" \ + "kernel_comp_size=0x2000000\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index a47f0902a26..72c04d8a994 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -63,111 +63,12 @@ #define CFG_SYS_NAND_LARGEPAGE #define CFG_SYS_NAND_BASE_LIST { 0x30000000, } -#define DFU_ALT_INFO_MMC \ - "dfu_alt_info_mmc=" \ - "MLO fat 0 1;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1\0" -/* DFU settings */ -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ /* U-Boot general configuration */ /* EDMA3 */ -#define KERNEL_MTD_PARTS \ - "mtdparts=" \ - SPI_MTD_PARTS - -#define DEFAULT_FW_INITRAMFS_BOOT_ENV \ - "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ - "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ - "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - "init_fw_rd_ramfs=setenv rd_spec -\0" \ - "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - -#define DEFAULT_PMMC_BOOT_ENV \ - "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ - "dev_pmmc=0\0" \ - "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ - "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \ - "get_pmmc_ramfs=run get_pmmc_net\0" \ - "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_pmmc}\0" \ - "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \ - "run_pmmc=rproc init; rproc list; " \ - "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ - "rproc start ${dev_pmmc}\0" \ - -#define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - ENV_KS2_BOARD_SETTINGS \ - DFUARGS \ - "bootdir=/boot\0" \ - "tftp_root=/\0" \ - "nfs_root=/export\0" \ - "mem_lpae=1\0" \ - "uinitrd_fixup=1\0" \ - "addr_ubi=0x82000000\0" \ - "addr_secdb_key=0xc000000\0" \ - "name_kern=zImage\0" \ - "addr_mon=0x87000000\0" \ - "addr_non_sec_mon=0x0c097fc0\0" \ - "addr_load_sec_bm=0x0c09c000\0" \ - "run_mon=mon_install ${addr_mon}\0" \ - "run_mon_hs=mon_install ${addr_non_sec_mon} " \ - "${addr_load_sec_bm}\0" \ - "run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ - "init_net=run args_all args_net\0" \ - "init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \ - "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount ubi:rootfs;\0" \ - "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ - "get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \ - "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ - "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ - "get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \ - "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ - "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \ - "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \ - "get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ - "get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0" \ - "get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0" \ - "get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \ - "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ - "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ - "sf write ${loadaddr} 0 ${filesize}\0" \ - "burn_uboot_nand=nand erase 0 0x100000; " \ - "nand write ${loadaddr} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait " \ - KERNEL_MTD_PARTS \ - "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ - "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ - "${nfs_options} ip=dhcp\0" \ - "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ - "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ - "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ - "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ - "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ - "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ - "get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \ - "burn_ubi=nand erase.part ubifs; " \ - "nand write ${addr_ubi} ubifs ${filesize}\0" \ - "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ - "args_ramfs=setenv bootargs ${bootargs} " \ - "rdinit=/sbin/init rw root=/dev/ram0 " \ - "initrd=0x808080000,80M\0" \ - "no_post=1\0" /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/dm/read.h b/include/dm/read.h index 137f2a52a29..c2615f72f40 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -247,6 +247,20 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size); /** + * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device + * as a pointer + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of <addr, size> pairs + * and @index is used to select which one is required + * @size: place to put size value (on success) + * + * Return: pointer or NULL if not found + */ +void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size); + +/** * dev_remap_addr_index() - Get the indexed reg property of a device * as a memory-mapped I/O pointer * @@ -952,6 +966,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, return devfdt_get_addr_size_index(dev, index, size); } +static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev, + int index, + fdt_size_t *size) +{ + return devfdt_get_addr_size_index_ptr(dev, index, size); +} + static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) { diff --git a/include/environment/ti/mmc.env b/include/environment/ti/mmc.env index a052d288535..6fb47fb2667 100644 --- a/include/environment/ti/mmc.env +++ b/include/environment/ti/mmc.env @@ -60,3 +60,17 @@ mmcboot=mmc dev ${mmcdev}; fi; fi; +init_mmc=run args_all args_mmc +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} && + fdt apply ${dtboaddr}; + done; +get_kern_mmc=load mmc ${bootpart} ${loadaddr} + ${bootdir}/${name_kern} +get_fit_mmc=load mmc ${bootpart} ${addr_fit} + ${bootdir}/${name_fit} +partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs} diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h deleted file mode 100644 index 1681dc8635e..00000000000 --- a/include/environment/ti/spi.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com - * - * Environment variable definitions for SPI on TI boards. - */ - -#ifndef __TI_SPI_H -#define __TI_SPI_H - -#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0" -#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0" - -#endif diff --git a/include/environment/ti/ti_armv7_keystone2.env b/include/environment/ti/ti_armv7_keystone2.env new file mode 100644 index 00000000000..e0395d302cb --- /dev/null +++ b/include/environment/ti/ti_armv7_keystone2.env @@ -0,0 +1,61 @@ +name_fw_rd=k2-fw-initrd.cpio.gz +set_rd_spec=setenv rd_spec ${rdaddr}:${filesize} +init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; run set_rd_spec +init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; run set_rd_spec +init_fw_rd_ramfs=setenv rd_spec - +init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; run set_rd_spec + +dfu_bufsiz=0x10000 +dfu_alt_info_mmc= + MLO fat 0 1; + u-boot.img fat 0 1; + uEnv.txt fat 0 1 + +bootdir=/boot +tftp_root=/ +nfs_root=/export +mem_lpae=1 +uinitrd_fixup=1 +addr_ubi=0x82000000 +addr_secdb_key=0xc000000 +name_kern=zImage +addr_mon=0x87000000 +addr_non_sec_mon=0x0c097fc0 +addr_load_sec_bm=0x0c09c000 +run_mon=mon_install ${addr_mon} +run_mon_hs=mon_install ${addr_non_sec_mon} ${addr_load_sec_bm} +run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr} +init_net=run args_all args_net +init_nfs=setenv autoload no; dhcp; run args_all args_net +init_ubi=run args_all args_ubi; ubi part ubifs; ubifsmount ubi:rootfs; +get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt} +get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt} +get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt} +get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern} +get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern} +get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern} +get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon} +get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon} +get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon} +get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit} +get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit} +get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit} +get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit} +get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot} +get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot} +burn_uboot_spi=sf probe; sf erase 0 0x100000; sf write ${loadaddr} 0 ${filesize} +burn_uboot_nand=nand erase 0 0x100000; nand write ${loadaddr} 0 ${filesize} +args_all=setenv bootargs console=ttyS0,115200n8 rootwait +args_net=setenv bootargs ${bootargs} rootfstype=nfs root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},${nfs_options} ip=dhcp +nfs_options=v3,tcp,rsize=4096,wsize=4096 +get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt} +get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern} +get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon} +get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit} +get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs} +get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi} +get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi} +burn_ubi=nand erase.part ubifs; nand write ${addr_ubi} ubifs ${filesize} +init_ramfs=run args_all args_ramfs get_fs_ramfs +args_ramfs=setenv bootargs ${bootargs} rdinit=/sbin/init rw root=/dev/ram0 initrd=0x808080000,80M +no_post=1 diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h new file mode 100644 index 00000000000..8acfa6ddf5a --- /dev/null +++ b/include/linux/usb/phy-rockchip-usbdp.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __PHY_ROCKCHIP_USBDP_H_ +#define __PHY_ROCKCHIP_USBDP_H_ + +#include <linux/bitops.h> + +/* RK3588 USBDP PHY Register Definitions */ + +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ +#define RK3588_GRF_VO0_CON0 0x0000 +#define RK3588_GRF_VO0_CON2 0x0008 +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) +#define PHY_AUX_DP_DATA_POL_NORMAL 0 +#define PHY_AUX_DP_DATA_POL_INVERT 1 + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) +#define PHY_LANE_MUX_USB 0 +#define PHY_LANE_MUX_DP 1 + +#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ +#define CMN_ROPLL_SSC_EN BIT(1) +#define CMN_LCPLL_SSC_EN BIT(0) + +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) +#define CMN_ANA_LCPLL_AFC_DONE BIT(6) + +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) +#define CMN_ANA_ROPLL_AFC_DONE BIT(0) + +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ +#define CMN_DP_INIT_RSTN BIT(3) +#define CMN_DP_CMN_RSTN BIT(2) +#define CMN_CDR_WTCHDG_EN BIT(1) +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) + +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ +#define LN_ANA_TX_SER_TXCLK_INV BIT(1) + +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) + +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + +#endif diff --git a/include/net6.h b/include/net6.h index beafc053386..1e766aa7209 100644 --- a/include/net6.h +++ b/include/net6.h @@ -204,7 +204,7 @@ struct icmp6_ra_prefix_info { * be initialized to zero by the sender and ignored by the receiver. */ struct in6_addr prefix; -}; +} __packed; extern struct in6_addr const net_null_addr_ip6; /* NULL IPv6 address */ extern struct in6_addr net_gateway6; /* Our gateways IPv6 address */ diff --git a/net/ndisc.c b/net/ndisc.c index 0b27779ce5a..d1cec0601c8 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -382,6 +382,8 @@ int process_ra(struct ip6_hdr *ip6, int len) unsigned char type = 0; struct icmp6_ra_prefix_info *prefix = NULL; + if (len > ETH_MAX_MTU) + return -EMSGSIZE; /* Ignore the packet if router lifetime is 0. */ if (!icmp->icmp6_rt_lifetime) return -EOPNOTSUPP; diff --git a/tools/iot2050-sign-fw.sh b/tools/iot2050-sign-fw.sh index 4d1d79498c2..6b426c854c2 100755 --- a/tools/iot2050-sign-fw.sh +++ b/tools/iot2050-sign-fw.sh @@ -39,13 +39,10 @@ CERT_X509=$(mktemp XXXXXXXX.crt) openssl req -new -x509 -key $1 -nodes -outform DER -out $CERT_X509 -config $TEMP_X509 -sha512 cat $CERT_X509 tispl.bin > tispl.bin_signed -# currently broken in upstream -#source/tools/binman/binman replace -i flash.bin -f tispl.bin_signed blob@0x180000 -dd if=tispl.bin_signed of=flash.bin bs=$((0x1000)) seek=$((0x180000/0x1000)) conv=notrunc +source/tools/binman/binman replace -i flash-pg1.bin -f tispl.bin_signed fit@180000 +source/tools/binman/binman replace -i flash-pg2.bin -f tispl.bin_signed fit@180000 rm $TEMP_X509 $CERT_X509 -tools/mkimage -G $1 -r -o sha256,rsa4096 -F fit@0x380000.fit -# currently broken in upstream -#source/tools/binman/binman replace -i flash.bin -f fit@0x380000.fit fit@0x380000 -dd if=fit@0x380000.fit of=flash.bin bs=$((0x1000)) seek=$((0x380000/0x1000)) conv=notrunc +source/tools/binman/binman sign -i flash-pg1.bin -k $1 -a sha256,rsa4096 fit@380000 +source/tools/binman/binman sign -i flash-pg2.bin -k $1 -a sha256,rsa4096 fit@380000 |