diff options
585 files changed, 16040 insertions, 2320 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index b3fd4ceef13..8209d2b329c 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2022 ubuntu_vm: ubuntu-24.04 macos_vm: macOS-14 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -251,7 +251,7 @@ stages: # the below corresponds to .gitlab-ci.yml "before_script" cd \${WORK_DIR} git config --global --add safe.directory \${WORK_DIR} - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks + git clone --depth=1 https://github.com/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled. # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na @@ -531,10 +531,11 @@ stages: TEST_PY_BD: "r2dplus" TEST_PY_ID: "--id tulip_qemu" TEST_PY_TEST_SPEC: "not sleep" - sifive_unleashed_sdcard: - TEST_PY_BD: "sifive_unleashed" - TEST_PY_ID: "--id sdcard_qemu" - TEST_PY_TEST_SPEC: "not sleep" +# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945 +# sifive_unleashed_sdcard: +# TEST_PY_BD: "sifive_unleashed" +# TEST_PY_ID: "--id sdcard_qemu" +# TEST_PY_TEST_SPEC: "not sleep" sifive_unleashed_spi-nor: TEST_PY_BD: "sifive_unleashed" TEST_PY_ID: "--id spi-nor_qemu" diff --git a/.gitignore b/.gitignore index bb03833b5f2..6d85b3aa238 100644 --- a/.gitignore +++ b/.gitignore @@ -56,11 +56,12 @@ fit-dtb.blob* /*.log # -# git files that we don't want to ignore even it they are dot-files +# We don't want to ignore the following even if they are dot-files # +!.get_maintainer.* +!.gitattributes !.gitignore !.mailmap -!.get_maintainer.* # # Generated files diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2dfeda9985d..85401d3e09b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ workflow: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025 # We run some tests in different order, to catch some failures quicker. stages: @@ -519,12 +519,13 @@ r2dplus_tulip test.py: TEST_PY_ID: "--id tulip_qemu" <<: *buildman_and_testpy_dfn -sifive_unleashed_sdcard test.py: - variables: - TEST_PY_BD: "sifive_unleashed" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id sdcard_qemu" - <<: *buildman_and_testpy_dfn +# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945 +#sifive_unleashed_sdcard test.py: +# variables: +# TEST_PY_BD: "sifive_unleashed" +# TEST_PY_TEST_SPEC: "not sleep" +# TEST_PY_ID: "--id sdcard_qemu" +# <<: *buildman_and_testpy_dfn sifive_unleashed_spi-nor test.py: variables: diff --git a/MAINTAINERS b/MAINTAINERS index ce7f7e03505..c4eaba58a90 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -602,6 +602,7 @@ ARM SAMSUNG EXYNOS850 SOC M: Sam Protsenko <semen.protsenko@linaro.org> S: Maintained F: drivers/clk/exynos/clk-exynos850.c +F: drivers/phy/phy-exynos-usbdrd.c F: drivers/pinctrl/exynos/pinctrl-exynos850.c ARM SAMSUNG SOC DRIVERS @@ -653,7 +654,7 @@ F: include/dt-bindings/pinctrl/adi-adsp.h F: include/env/adi/ ARM SNAPDRAGON -M: Caleb Connolly <caleb.connolly@linaro.org> +M: Casey Connolly <casey.connolly@linaro.org> M: Neil Armstrong <neil.armstrong@linaro.org> R: Sumit Garg <sumit.garg@kernel.org> L: u-boot-qcom@groups.io @@ -1093,7 +1094,7 @@ F: drivers/core/ F: include/dm/ F: test/dm/ -EFI APP +EFI CLIENT M: Simon Glass <sjg@chromium.org> M: Heinrich Schuchardt <xypron.glpk@gmx.de> S: Maintained @@ -1103,11 +1104,11 @@ F: configs/efi-x86_app* F: doc/develop/uefi/u-boot_on_efi.rst F: drivers/block/efi-media-uclass.c F: drivers/block/sb_efi_media.c -F: lib/efi/efi_app.c +F: lib/efi_client/ F: scripts/build-efi.sh F: test/dm/efi_media.c -EFI PAYLOAD +EFI LOADER M: Heinrich Schuchardt <xypron.glpk@gmx.de> M: Ilias Apalodimas <ilias.apalodimas@linaro.org> S: Maintained @@ -1793,7 +1794,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ UFETCH -M: Caleb Connolly <caleb.connolly@linaro.org> +M: Casey Connolly <casey.connolly@linaro.org> S: Maintained F: cmd/ufetch.c @@ -1865,7 +1866,7 @@ F: common/spl_reloc.c F: include/vbe.h VIDEO -M: Anatolij Gustschin <agust@denx.de> +M: Anatolij Gustschin <ag.dev.uboot@gmail.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-video.git F: drivers/video/ @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ VERSION = 2025 -PATCHLEVEL = 07 +PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* @@ -1891,7 +1891,7 @@ u-boot-payload.lds: $(LDSCRIPT_EFI) FORCE quiet_cmd_u-boot_payload ?= LD $@ cmd_u-boot_payload ?= $(LD) $(LDFLAGS_EFI_PAYLOAD) -o $@ \ -T u-boot-payload.lds arch/x86/cpu/call32.o \ - lib/efi/efi.o lib/efi/efi_stub.o u-boot.bin.o \ + lib/efi_client/efi.o lib/efi_client/efi_stub.o u-boot.bin.o \ $(addprefix arch/$(ARCH)/lib/,$(EFISTUB)) u-boot-payload: u-boot.bin.o u-boot-payload.lds FORCE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5872455a0fe..4e7593616d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -835,6 +835,9 @@ config ARCH_K3 select FIT_SIGNATURE if ARM64 select LTO imply TI_SECURE_DEVICE + imply DM_RNG if ARM64 + imply TEE if ARM64 + imply OPTEE if ARM64 config ARCH_OMAP2PLUS bool "TI OMAP2+" diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 6a7ec9a7ec1..ccddfaaf04c 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -41,10 +41,11 @@ ENTRY(return_to_fel) str w2, [x1] ldr w0, =0xfa50392f // CPU hotplug magic -#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) +#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \ + defined(CONFIG_MACH_SUN55I_A523) ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0) str w0, [x2], #0x4 -#elif CONFIG_MACH_SUN50I_H6 +#elif defined(CONFIG_MACH_SUN50I_H6) ldr w2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG str w0, [x2], #0x4 #else diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 17795f8f746..0dc7e190eb9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -760,7 +760,6 @@ dtb-y += \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ - imx6dl-sielaff.dtb \ imx6dl-wandboard-revd1.dtb endif @@ -918,6 +917,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ + imx93-11x11-frdm.dtb \ imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index cb8ce8b6b6f..a048951fa18 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -794,7 +794,7 @@ uart11: serial@1e790500 { compatible = "ns16550a"; - reg = <0x1e790400 0x20>; + reg = <0x1e790500 0x20>; reg-shift = <2>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; diff --git a/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..343f10cdf9a --- /dev/null +++ b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7d65_curiosity-u-boot.dtsi - Device Tree Include file for + * SAMA7D65 CURIOSITY. + * + * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + */ + +/{ + aliases { + serial0 = &uart6; + }; + + chosen { + bootph-all; + }; + + clocks { + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + cpu@0 { + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 26>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + soc { + bootph-all; + }; +}; + +&clk32k { + clocks = <&slow_rc_osc>, <&slow_xtal>; +}; + +&main_xtal { + bootph-all; +}; + +&pioa { + bootph-all; +}; + +&pinctrl_uart6_default { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc1 { + assigned-clock-parents = <&pmc PMC_TYPE_CORE 27>; /* MCK1 div */ + microchip,sdcal-inverted; + no-1-8-v; +}; + +&slow_rc_osc { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&uart6 { + bootph-all; +}; diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts deleted file mode 100644 index 7de8d5f2651..00000000000 --- a/arch/arm/dts/imx6dl-sielaff.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2022 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include <dt-bindings/clock/imx6qdl-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Sielaff i.MX6 Solo"; - compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; - - chosen { - stdout-path = &uart2; - }; - - backlight: pwm-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm3 0 50000 0>; - brightness-levels = <0 0 64 88 112 136 184 232 255>; - default-brightness-level = <4>; - enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - power-supply = <®_backlight>; - }; - - cec { - compatible = "cec-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - hdmi-phandle = <&hdmi>; - }; - - enet_ref: clock-enet-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet-ref"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-0 { - gpios = <&gpio2 16 0>; - debounce-interval = <10>; - linux,code = <1>; - }; - - key-1 { - gpios = <&gpio3 27 0>; - debounce-interval = <10>; - linux,code = <2>; - }; - - key-2 { - gpios = <&gpio5 4 0>; - debounce-interval = <10>; - linux,code = <3>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-debug { - label = "debug-led"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; - - osc_eth_phy: clock-osc-eth-phy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc-eth-phy"; - }; - - panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_backlight>; - enable-active-high; - gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - regulator-name = "backlight"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - /* - * Set PTP clock to external instead of internal reference, as the - * REF_CLK from the PHY is fed back into the i.MX6 and the GPR - * register needs to be set accordingly (see mach-imx6q.c). - */ - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&enet_ref>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rmii"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - clocks = <&osc_eth_phy>; - clock-names = "rmii-ref"; - micrel,led-mode = <1>; - reset-assert-us = <500>; - reset-deassert-us = <100>; - reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "key-out", "key-in", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "lan9500a-rst", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c4>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1633"; - reg = <0x55>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio5>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <100000>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds_out: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - disable-over-current; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - usb1@1 { - compatible = "usb4b4,6570"; - reg = <1>; - clocks = <&clks IMX6QDL_CLK_CKO>; - - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, - <&clks IMX6QDL_CLK_OSC>; - assigned-clock-rates = <12000000 0>; - }; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "host"; - over-current-active-low; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_backlight: regbacklightgrp { - fsl,pins = < - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 - >; - }; - - pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi new file mode 100644 index 00000000000..41111b1a95a --- /dev/null +++ b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&A55_0 { + clocks = <&clk IMX93_CLK_A55_SEL>; +}; + +&A55_1 { + clocks = <&clk IMX93_CLK_A55_SEL>; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; +}; + +&lpi2c2 { + bootph-pre-ram; +}; + +&lpi2c3 { + bootph-pre-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; +}; + +&fec { + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts new file mode 100644 index 00000000000..993567e767d --- /dev/null +++ b/arch/arm/dts/imx93-11x11-frdm.dts @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; + model = "NXP i.MX93 11X11 FRDM board"; + + aliases { + mmc0 = &usdhc1; /* EMMC */ + mmc1 = &usdhc2; /* uSD */ + rtc0 = &pcf2131; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; +}; diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 6deebdadf09..a9bd5a2be84 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -69,7 +69,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -105,7 +105,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 6822a5dac89..f743c4353b4 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index bfbba28269c..65fef6e4790 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index fd340101532..9bcdf74ffe4 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -30,7 +30,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -110,7 +110,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 877a513a241..0685bdd7e0c 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -27,7 +27,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -71,7 +71,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -107,7 +107,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index d65e5c4d4e1..feb59edcd83 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; @@ -72,7 +72,7 @@ content-sysfw-data = <&combined_tifs_cfg_hs>; content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; content-dm-data = <&combined_dm_cfg_hs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi index 13fac18d7aa..b1591faaf0a 100644 --- a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_hs>; content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; content-dm-data = <&combined_dm_cfg_hs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index f49d6f262f2..b3d64485249 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -208,7 +208,7 @@ fit,fdt-list-val = "ti/k3-am6528-iot2050-basic", "ti/k3-am6548-iot2050-advanced"; configurations { - default = "ti/k3-am6528-iot2050-basic"; + default = "config-1"; @config-SEQ { loadables = #ifdef CONFIG_WDT_K3_RTI_FW_FILE @@ -265,7 +265,7 @@ }; configurations { - default = "ti/k3-am6528-iot2050-basic-pg2"; + default = "config-1"; @config-SEQ { loadables = #ifdef CONFIG_WDT_K3_RTI_FW_FILE diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi index 2a0023fb7c3..0e810e7f492 100644 --- a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi +++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi @@ -75,7 +75,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; @@ -125,7 +125,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index b74bd1657f9..b4e0ce8bfcf 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -24,7 +24,7 @@ content-sysfw-data = <&combined_tifs_cfg_sr1>; content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; content-dm-data = <&combined_dm_cfg_sr1>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -112,7 +112,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; content-dm-data = <&combined_dm_cfg_fs_sr1>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -155,7 +155,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -192,7 +192,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 4f524e58ceb..f79b3e543ae 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x41c80000>; @@ -66,7 +66,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x41c80000>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index 57e966ea666..278b7bfac7f 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; @@ -73,7 +73,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index a7ce1ee2b03..34b2cc1e681 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -27,7 +27,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x66800>; load-dm-data = <0x41c80000>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x66800>; load-dm-data = <0x41c80000>; @@ -114,7 +114,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts index ec8e7dee271..1068f1a288a 100644 --- a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts +++ b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts @@ -51,6 +51,26 @@ &i2c0 { status = "okay"; + + pca9547@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ivm@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "MAIN_CTRL"; + }; + }; + }; }; &dspi1 { diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts index 03ce3ab4e47..3e8c54d83c9 100644 --- a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts +++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts @@ -44,6 +44,26 @@ &i2c0 { status = "okay"; + + pca9547@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ivm@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "MAIN_CTRL"; + }; + }; + }; }; &ifc { diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index a70123feead..469b94bbde6 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -20,7 +20,6 @@ binman: binman { multiple-images; -#ifdef CONFIG_SPL fit-dtb.blob { filename = "fit-dtb.blob"; pad-byte = <0>; @@ -109,6 +108,7 @@ }; }; +#ifdef CONFIG_SPL /* Generation in a static way */ itb { filename = U_BOOT_ITB_FILENAME; diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 0dd2d62b9ef..a8e3f7354c7 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -118,6 +118,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate); void ddrphy_init_read_msg_block(enum fw_type type); void get_trained_CDD(unsigned int fsp); +u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr); ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 575dff68804..45fa4ab6e57 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -13,6 +13,7 @@ #include <linux/bitops.h> #endif +/* Main CCU register offsets */ #define CCU_H6_PLL1_CFG 0x000 #define CCU_H6_PLL5_CFG 0x010 #define CCU_H6_PLL6_CFG 0x020 @@ -31,29 +32,39 @@ #define CCU_H6_UART_GATE_RESET 0x90c #define CCU_H6_I2C_GATE_RESET 0x91c -/* pll1 bit field */ -#define CCM_PLL1_CTRL_EN BIT(31) -#define CCM_PLL1_LDO_EN BIT(30) -#define CCM_PLL1_LOCK_EN BIT(29) -#define CCM_PLL1_LOCK BIT(28) -#define CCM_PLL1_OUT_EN BIT(27) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) +/* A523 CPU PLL offsets */ +#define CPC_CPUA_PLL_CTRL 0x04 +#define CPC_DSU_PLL_CTRL 0x08 +#define CPC_CPUB_PLL_CTRL 0x0c +#define CPC_CPUA_CLK_REG 0x60 +#define CPC_CPUB_CLK_REG 0x64 +#define CPC_DSU_CLK_REG 0x6c + +/* PLL bit fields */ +#define CCM_PLL_CTRL_EN BIT(31) +#define CCM_PLL_LDO_EN BIT(30) +#define CCM_PLL_LOCK_EN BIT(29) +#define CCM_PLL_LOCK BIT(28) +#define CCM_PLL_OUT_EN BIT(27) +#define CCM_PLL1_UPDATE BIT(26) #define CCM_PLL1_CTRL_P(p) ((p) << 16) +#define CCM_PLL1_CTRL_N_MASK GENMASK(15, 8) #define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) +/* A523 CPU clock fields */ +#define CPU_CLK_SRC_HOSC (0 << 24) +#define CPU_CLK_SRC_CPUPLL (3 << 24) +#define CPU_CLK_CTRL_P(p) ((p) << 16) +#define CPU_CLK_APB_DIV(n) (((n) - 1) << 8) +#define CPU_CLK_PERI_DIV(m1) (((m1) - 1) << 2) +#define CPU_CLK_AXI_DIV(m) (((m) - 1) << 0) + /* pll5 bit field */ -#define CCM_PLL5_CTRL_EN BIT(31) -#define CCM_PLL5_LOCK_EN BIT(29) -#define CCM_PLL5_LOCK BIT(28) -#define CCM_PLL5_OUT_EN BIT(27) #define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) /* pll6 bit field */ -#define CCM_PLL6_CTRL_EN BIT(31) -#define CCM_PLL6_LOCK_EN BIT(29) -#define CCM_PLL6_LOCK BIT(28) #define CCM_PLL6_CTRL_P0_SHIFT 16 #define CCM_PLL6_CTRL_P0_MASK (0x7 << CCM_PLL6_CTRL_P0_SHIFT) #define CCM_PLL6_CTRL_N_SHIFT 8 @@ -97,6 +108,13 @@ #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 #define CCM_AHB3_DEFAULT 0x03000002 #define CCM_APB1_DEFAULT 0x03000102 + +#elif CONFIG_MACH_SUN55I_A523 /* A523 */ + +#define CCM_PLL6_DEFAULT 0xe8216310 /* 1200 MHz */ +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 /* 200 MHz */ +#define CCM_APB1_DEFAULT 0x03000005 /* APB0 really */ +#define CCM_APB2_DEFAULT 0x03000005 /* APB1 really */ #endif /* apb2 bit field */ @@ -116,6 +134,7 @@ /* MBUS clock bit field */ #define MBUS_ENABLE BIT(31) #define MBUS_RESET BIT(30) +#define MBUS_UPDATE BIT(27) #define MBUS_CLK_SRC_MASK GENMASK(25, 24) #define MBUS_CLK_SRC_OSCM24 (0 << 24) #define MBUS_CLK_SRC_PLL6X2 (1 << 24) @@ -128,10 +147,12 @@ #define GATE_SHIFT (0) /* DRAM clock bit field */ +#define DRAM_CLK_ENABLE BIT(31) #define DRAM_MOD_RESET BIT(30) #define DRAM_CLK_UPDATE BIT(27) #define DRAM_CLK_SRC_MASK GENMASK(25, 24) #define DRAM_CLK_SRC_PLL5 (0 << 24) +#define DRAM_CLK_M_MASK (0x1f) #define DRAM_CLK_M(m) (((m)-1) << 0) /* MMC clock bit field */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h index 908a582ae0f..bcfdc0a41c5 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -21,14 +21,34 @@ #define SUNXI_SID_BASE 0x03006200 #define SUNXI_GIC400_BASE 0x03020000 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_DRAM_COM_BASE 0x03120000 +#define SUNXI_DRAM_CTL0_BASE 0x03130000 +#define SUNXI_DRAM_PHY0_BASE 0x03140000 +#endif + #define SUNXI_MMC0_BASE 0x04020000 #define SUNXI_MMC1_BASE 0x04021000 #define SUNXI_MMC2_BASE 0x04022000 +#ifndef CONFIG_MACH_SUN55I_A523 #define SUNXI_R_CPUCFG_BASE 0x07000400 +#endif #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_R_CPUCFG_BASE 0x07050000 +#endif +#define SUNXI_R_TWI_BASE 0x07081400 +#define SUNXI_RTC_BASE 0x07090000 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_CPUCFG_BASE 0x08815000 +#else #define SUNXI_CPUCFG_BASE 0x09010000 +#endif + +#define SUNXI_CPU_PLL_CFG_BASE 0x08817000 #ifndef __ASSEMBLY__ void sunxi_board_init(void); diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 0708ae3ee3b..0eccb1e6c28 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -35,6 +35,8 @@ #include <asm/arch/dram_sun50i_a133.h> #elif defined(CONFIG_MACH_SUNIV) #include <asm/arch/dram_suniv.h> +#elif defined(CONFIG_MACH_SUN55I_A523) +#include <asm/arch/dram_sun55i_a523.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h new file mode 100644 index 00000000000..08bfe462856 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * t527 dram controller register and constant defines + * + * (C) Copyright 2024 Jernej Skrabec <jernej.skrabec@gmail.com> + */ + +#ifndef _SUNXI_DRAM_SUN55I_A523_H +#define _SUNXI_DRAM_SUN55I_A523_H + +#include <linux/bitops.h> + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_DDR4, + SUNXI_DRAM_TYPE_LPDDR3 = 7, + SUNXI_DRAM_TYPE_LPDDR4 +}; + +#define MCTL_COM_UNK_008 0x008 +#define MCTL_COM_MAER0 0x020 + +/* + * Controller registers seems to be the same or at least very similar + * to those in H6. + */ +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x000 */ + u32 statr; /* 0x004 unused */ + u32 mstr1; /* 0x008 unused */ + u32 clken; /* 0x00c */ + u32 mrctrl0; /* 0x010 unused */ + u32 mrctrl1; /* 0x014 unused */ + u32 mrstatr; /* 0x018 unused */ + u32 mrctrl2; /* 0x01c unused */ + u32 derateen; /* 0x020 unused */ + u32 derateint; /* 0x024 unused */ + u8 reserved_0x028[8]; /* 0x028 */ + u32 pwrctl; /* 0x030 */ + u32 pwrtmg; /* 0x034 unused */ + u32 hwlpctl; /* 0x038 */ + u8 reserved_0x03c[20]; /* 0x03c */ + u32 rfshctl0; /* 0x050 unused */ + u32 rfshctl1; /* 0x054 unused */ + u8 reserved_0x058[8]; /* 0x058 */ + u32 rfshctl3; /* 0x060 */ + u32 rfshtmg; /* 0x064 */ + u8 reserved_0x068[104]; /* 0x068 */ + u32 init[8]; /* 0x0d0 */ + u32 dimmctl; /* 0x0f0 unused */ + u32 rankctl; /* 0x0f4 */ + u8 reserved_0x0f8[8]; /* 0x0f8 */ + u32 dramtmg[17]; /* 0x100 */ + u8 reserved_0x144[60]; /* 0x144 */ + u32 zqctl[3]; /* 0x180 */ + u32 zqstat; /* 0x18c unused */ + u32 dfitmg0; /* 0x190 */ + u32 dfitmg1; /* 0x194 */ + u32 dfilpcfg[2]; /* 0x198 unused */ + u32 dfiupd[3]; /* 0x1a0 */ + u32 reserved_0x1ac; /* 0x1ac */ + u32 dfimisc; /* 0x1b0 */ + u32 dfitmg2; /* 0x1b4 unused */ + u32 dfitmg3; /* 0x1b8 unused */ + u32 dfistat; /* 0x1bc */ + u32 dbictl; /* 0x1c0 */ + u8 reserved_0x1c4[60]; /* 0x1c4 */ + u32 addrmap[12]; /* 0x200 */ + u8 reserved_0x230[16]; /* 0x230 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 reserved_0x248[8]; /* 0x248 */ + u32 sched[2]; /* 0x250 */ + u8 reserved_0x258[12]; /* 0x258 */ + u32 unk_0x264; /* 0x264 */ + u8 reserved_0x268[8]; /* 0x268 */ + u32 unk_0x270; /* 0x270 */ + u8 reserved_0x274[152]; /* 0x274 */ + u32 dbgcmd; /* 0x30c unused */ + u32 dbgstat; /* 0x310 unused */ + u8 reserved_0x314[12]; /* 0x314 */ + u32 swctl; /* 0x320 */ + u32 swstat; /* 0x324 */ + u8 reserved_0x328[7768];/* 0x328 */ + u32 unk_0x2180; /* 0x2180 */ + u8 reserved_0x2184[188];/* 0x2184 */ + u32 unk_0x2240; /* 0x2240 */ + u8 reserved_0x2244[3900];/* 0x2244 */ + u32 unk_0x3180; /* 0x3180 */ + u8 reserved_0x3184[188];/* 0x3184 */ + u32 unk_0x3240; /* 0x3240 */ + u8 reserved_0x3244[3900];/* 0x3244 */ + u32 unk_0x4180; /* 0x4180 */ + u8 reserved_0x4184[188];/* 0x4184 */ + u32 unk_0x4240; /* 0x4240 */ +}; +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); +check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); + +#define MSTR_DEVICETYPE_DDR3 BIT(0) +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) +#define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_LPDDR4 BIT(5) +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) +#define MSTR_2TMODE BIT(10) +#define MSTR_BUSWIDTH_FULL (0 << 12) +#define MSTR_BUSWIDTH_HALF (1 << 12) +#define MSTR_ACTIVE_RANKS(x) ((((x) == 2) ? 3 : 1) << 24) +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) + +#define TPR10_CA_BIT_DELAY 0xffff0000 +#define TPR10_DX_BIT_DELAY0 BIT(17) +#define TPR10_DX_BIT_DELAY1 BIT(18) +#define TPR10_WRITE_LEVELING BIT(20) +#define TPR10_READ_CALIBRATION BIT(21) +#define TPR10_READ_TRAINING BIT(22) +#define TPR10_WRITE_TRAINING BIT(23) + +struct dram_para { + enum sunxi_dram_type type; + u32 dx_odt; + u32 dx_dri; + u32 ca_dri; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr6; + u32 tpr10; +}; + +struct dram_config { + u8 cols; + u8 rows; + u8 ranks; + u8 bus_full_width; + u32 clk; + u32 odt_en; + u32 tpr11; + u32 tpr12; + u32 tpr14; +}; + +static inline int ns_to_t(int nanoseconds, u32 clk) +{ + const unsigned int ctrl_freq = clk / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(u32 clk); + +#endif /* _SUNXI_DRAM_SUN55I_T527_H */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h index 38e2ef2aca3..14a6e89ccfa 100644 --- a/arch/arm/include/asm/arch-sunxi/watchdog.h +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -12,6 +12,8 @@ #define WDT_CTRL_RESTART (0x1 << 0) #define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_SRST_REG 0x08 + #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN5I) || \ defined(CONFIG_MACH_SUN7I) || \ diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d21534ce883..7d00f1650b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -52,6 +52,11 @@ config SAMA7G5 select CPU_V7A select AT91RESET_EXTRST +config SAMA7D65 + bool + select CPU_V7A + select AT91RESET_EXTRST + config SAMA5D2 bool select CPU_V7A @@ -299,6 +304,13 @@ config TARGET_SAMA7G54_CURIOSITY 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors, 1 x SD-Card connector, 1 x M.2 slot, 3 x USB +config TARGET_SAMA7D65_CURIOSITY + bool "SAMA7D65 CURIOSITY board" + select SAMA7D65 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply OF_UPSTREAM + config TARGET_TAURUS bool "Support taurus" select AT91SAM9G20 @@ -365,6 +377,7 @@ source "board/atmel/sam9x60_curiosity/Kconfig" source "board/atmel/sam9x75_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama7g54_curiosity/Kconfig" +source "board/atmel/sama7d65_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 6da1cdffef6..4303a60e0e3 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o clock.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o +obj-$(CONFIG_SAMA7D65) += sama7d65_devices.o obj-y += cpu.o ifneq ($(CONFIG_ATMEL_TCB_TIMER),y) ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) diff --git a/arch/arm/mach-at91/armv7/sama7d65_devices.c b/arch/arm/mach-at91/armv7/sama7d65_devices.c new file mode 100644 index 00000000000..6c6ae751b1a --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama7d65_devices.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. + */ + +#include <asm/arch/sama7d65.h> + +char *get_cpu_name(void) +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama7d65()) + switch (extension_id) { + case ARCH_EXID_SAMA7D65: + return "SAMA7D65"; + case ARCH_EXID_SAMA7D65_DD2: + return "SAMA7D65 DDR2"; + case ARCH_EXID_SAMA7D65_D1G: + return "SAMA7D65 1Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D2G: + return "SAMA7D65 2Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D4G: + return "SAMA7D65 4Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_TA: + return "SAMA7D65 TA1000 SiP"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type10"; +} diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index de89714b097..0b2ddbab3be 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -27,6 +27,8 @@ # include <asm/arch/sam9x7.h> #elif defined(CONFIG_SAMA7G5) # include <asm/arch/sama7g5.h> +#elif defined(CONFIG_SAMA7D65) +# include <asm/arch/sama7d65.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sama7d65.h b/arch/arm/mach-at91/include/mach/sama7d65.h new file mode 100644 index 00000000000..8adc5c9a733 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7d65.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + */ + +#ifndef __SAMA7D65_H__ +#define __SAMA7D65_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FLEXCOM0 34 +#define ATMEL_ID_FLEXCOM1 35 +#define ATMEL_ID_FLEXCOM2 36 +#define ATMEL_ID_FLEXCOM3 37 +#define ATMEL_ID_FLEXCOM4 38 +#define ATMEL_ID_FLEXCOM5 39 +#define ATMEL_ID_FLEXCOM6 40 +#define ATMEL_ID_FLEXCOM7 41 +#define ATMEL_ID_FLEXCOM8 42 + +#define ATMEL_ID_SDMMC0 75 +#define ATMEL_ID_SDMMC1 76 +#define ATMEL_ID_SDMMC2 77 + +#define ATMEL_ID_PIT64B0 66 +#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 + +#define ATMEL_CHIPID_CIDR 0xe0020000 +#define ATMEL_CHIPID_EXID 0xe0020004 +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_PIOA 0xe0014000 +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) +#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) + +#define ATMEL_PIO_PORTS 5 + +#define CPU_HAS_PCR + +#define ATMEL_BASE_PMC 0xe0018000 + +#define ATMEL_BASE_WDT 0xe001c000 +#define ATMEL_BASE_RSTC 0xe001d100 +#define ATMEL_BASE_WDTS 0xe001d180 +#define ATMEL_BASE_SCKCR 0xe001d500 + +#define ATMEL_BASE_SDMMC0 0xe1204000 +#define ATMEL_BASE_SDMMC1 0xe1208000 + +#define ATMEL_BASE_PIT64B0 0xe1800000 + +#define ATMEL_BASE_FLEXCOM0 0xe1820000 +#define ATMEL_BASE_FLEXCOM1 0xe1824000 +#define ATMEL_BASE_FLEXCOM2 0xe1828000 +#define ATMEL_BASE_FLEXCOM3 0xe182c000 +#define ATMEL_BASE_FLEXCOM4 0xe2018000 +#define ATMEL_BASE_FLEXCOM5 0xe201C000 +#define ATMEL_BASE_FLEXCOM6 0xe2020000 +#define ATMEL_BASE_FLEXCOM7 0xe2024000 +#define ATMEL_BASE_FLEXCOM8 0xe281C000 + +#define ATMEL_BASE_TZC400 0xe3000000 + +#define ATMEL_BASE_UMCTL2 0xe3800000 +#define ATMEL_BASE_UMCTL2_MP 0xe38003f8 +#define ATMEL_BASE_PUBL 0xe3804000 + +#define ATMEL_NUM_FLEXCOM 11 +#define ATMEL_PIO_PORTS 5 + +#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 + +#define ARCH_ID_SAMA7D65 0x80262100 +#define ARCH_EXID_SAMA7D65 0x00000080 +#define ARCH_EXID_SAMA7D65_DD2 0x00000010 +#define ARCH_EXID_SAMA7D65_D1G 0x00000018 +#define ARCH_EXID_SAMA7D65_D2G 0x00000020 +#define ARCH_EXID_SAMA7D65_D4G 0x00000028 +#define ARCH_EXID_SAMA7D65_TA 0x00000040 + +#define cpu_is_sama7d65() (get_chip_id() == ARCH_ID_SAMA7D65) +#define cpu_is_sama7d65_S() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65)) +#define cpu_is_sama7d65_DD2() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_DD2)) +#define cpu_is_sama7d65_D1G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D1G)) +#define cpu_is_sama7d65_D2G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D2G)) +#define cpu_is_sama7d65_D4G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D4G)) +#define cpu_is_sama7d65_TA() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_TA)) + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +char *get_cpu_name(void); +#endif + +#endif /* #ifndef __SAMA7D65_H__ */ diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 95bd1823531..4e0e194690b 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -66,6 +66,14 @@ config TARGET_IMX93_11X11_EVK imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND +config TARGET_IMX93_FRDM + bool "imx93_frdm" + select OF_BOARD_FIXUP + select IMX93 + select IMX9_LPDDR4X + imply BOOTSTD_FULL + imply BOOTSTD_BOOTCOMMAND + config TARGET_IMX93_VAR_SOM bool "imx93_var_som" select IMX93 @@ -90,6 +98,7 @@ endchoice source "board/freescale/imx91_evk/Kconfig" source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 0f11511bda0..53f152ccd9c 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -17,6 +17,7 @@ #include <dm/pinctrl.h> #include <mmc.h> #include <remoteproc.h> +#include <k3_bist.h> #include "../sysfw-loader.h" #include "../common.h" @@ -122,6 +123,48 @@ static void setup_navss_nb(void) writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); } +/* Execute and check results of BIST executed on MCU1_x and MCU4_O */ +static void run_bist_j784s4(struct udevice *dev) +{ + struct bist_ops *ops; + struct ti_sci_handle *handle; + int ret; + + ops = (struct bist_ops *)device_get_ops(dev); + handle = get_ti_sci_handle(); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_pbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger PBIST tests on MCU4_0 */ + ret = prepare_pbist(handle); + ret |= ops->run_pbist_neg(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist_rom(); + ret |= deprepare_pbist(handle); + + if (ret) + panic("PBIST on MCU4_0 failed: %d\n", ret); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_lbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger LBIST tests on MCU1_x */ + ret = prepare_lbist(handle); + ret |= ops->run_lbist(); + ret |= deprepare_lbist(handle); + if (ret) + panic("LBIST on MCU4_0 failed: %d\n", ret); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -266,6 +309,15 @@ void board_init_f(ulong dummy) printf("AVS init failed: %d\n", ret); } + if (!IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_BIST)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(k3_bist), + &dev); + if (ret) + panic("Failed to get BIST device: %d\n", ret); + run_bist_j784s4(dev); + } + if (IS_ENABLED(CONFIG_CPU_V7R)) setup_navss_nb(); diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 6ac2973bd67..6269b33f66b 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -27,7 +27,7 @@ enum { IMAGE_ID_DM_FW, IMAGE_ID_TIFSSTUB_HS, IMAGE_ID_TIFSSTUB_FS, - IMAGE_ID_T, + IMAGE_ID_TIFSSTUB_GP, IMAGE_AMT, }; diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index ec51ebbbe7f..fc921a4be26 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -3,7 +3,7 @@ * Common initialisation for Qualcomm Snapdragon boards. * * Copyright (c) 2024 Linaro Ltd. - * Author: Caleb Connolly <caleb.connolly@linaro.org> + * Author: Casey Connolly <casey.connolly@linaro.org> */ #define LOG_CATEGORY LOGC_BOARD diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c index 4dced4961b6..3699d91852d 100644 --- a/arch/arm/mach-snapdragon/capsule_update.c +++ b/arch/arm/mach-snapdragon/capsule_update.c @@ -3,7 +3,7 @@ * Capsule update support for Qualcomm boards. * * Copyright (c) 2024 Linaro Ltd. - * Author: Caleb Connolly <caleb.connolly@linaro.org> + * Author: Casey Connolly <casey.connolly@linaro.org> */ #define pr_fmt(fmt) "QCOM-FMP: " fmt diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 328c7812f30..eec2c0c757e 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -13,7 +13,7 @@ * boot Linux with the original FDT. * * Copyright (c) 2024 Linaro Ltd. - * Author: Caleb Connolly <caleb.connolly@linaro.org> + * Author: Casey Connolly <casey.connolly@linaro.org> */ #define pr_fmt(fmt) "of_fixup: " fmt diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0a7c029b15a..6a511c4fd39 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -57,7 +57,12 @@ config DRAM_SUN50I_A133 Select this dram controller driver for some sun50i platforms, like A133. -if DRAM_SUN50I_H616 || DRAM_SUN50I_A133 +config DRAM_SUN55I_A523 + bool + help + Select this DRAM controller driver for A523/T527 SoCs. + +if DRAM_SUN50I_H616 || DRAM_SUN50I_A133 || DRAM_SUN55I_A523 config DRAM_SUNXI_DX_ODT hex "DRAM DX ODT parameter" help @@ -170,8 +175,8 @@ config DRAM_SUNXI_TPR13 config DRAM_SUNXI_TPR14 hex "DRAM TPR14 parameter" - depends on DRAM_SUN50I_A133 - default 0x0 + depends on DRAM_SUN50I_A133 || MACH_SUN55I_A523 + default 0x48484848 help TPR14 value from vendor DRAM settings. @@ -209,6 +214,7 @@ config AXP_PMIC_BUS config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 + default 0x44000 if MACH_SUN55I_A523 default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x0 ---help--- @@ -221,6 +227,7 @@ config SUNXI_RVBAR_ADDRESS hex depends on ARM64 default 0x08100040 if MACH_SUN50I_A133 + default 0x08000040 if MACH_SUN55I_A523 default 0x09010040 if SUN50I_GEN_H6 default 0x017000a0 ---help--- @@ -249,6 +256,7 @@ config SUNXI_BL31_BASE default 0x00044000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x40000000 if MACH_SUN50I_H616 default 0x00104000 if SUN50I_GEN_H6 + default 0x00054000 if MACH_SUN55I_A523 default 0x0 help Address where BL31 (TF-A) is loaded, or zero if BL31 is not used. @@ -330,7 +338,7 @@ config MACH_SUNXI_H3_H5 # TODO: try out A80's 8GiB DRAM space config SUNXI_DRAM_MAX_SIZE hex - default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133 + default 0x100000000 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 default 0x80000000 @@ -532,6 +540,16 @@ config MACH_SUN50I_A133 select SUN50I_GEN_H6 imply OF_UPSTREAM +config MACH_SUN55I_A523 + bool "sun55i (Allwinner A523/A527/T527/H728)" + select ARM64 + select SUNXI_GEN_NCAT2 + select SUNXI_NEW_PINCTRL + select DRAM_SUN55I_A523 + select FIT + select SPL_LOAD_FIT if SPL + imply OF_UPSTREAM + endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" @@ -569,7 +587,7 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed. -if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 || DRAM_SUN50I_A133 +if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 || DRAM_SUN50I_A133 || DRAM_SUN55I_A523 config SUNXI_DRAM_DDR3 bool @@ -587,6 +605,7 @@ config SUNXI_DRAM_DDR4 choice prompt "DRAM Type and Timing" + default SUNXI_DRAM_A523_LPDDR4 if MACH_SUN55I_A523 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S @@ -670,6 +689,21 @@ config SUNXI_DRAM_DDR2_V3S This option is only for the DDR2 memory chip which is co-packaged in Allwinner V3s SoC. +config SUNXI_DRAM_A523_DDR3 + bool "DDR3 DRAM chips on the A523/T527 DRAM controller" + select SUNXI_DRAM_DDR3 + depends on DRAM_SUN55I_A523 + help + This option is the DDR3 timing used by the stock boot0 by + Allwinner. + +config SUNXI_DRAM_A523_LPDDR4 + bool "LPDDR4 DRAM chips on the A523/T527 DRAM controller" + select SUNXI_DRAM_LPDDR4 + depends on DRAM_SUN55I_A523 + help + This option is the LPDDR4 timing used by the stock boot0 by + Allwinner. endchoice endif @@ -690,6 +724,7 @@ config DRAM_CLK default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 + default 1200 if MACH_SUN55I_A523 ---help--- Set the dram clock speed, valid range 240 - 480 (prior to sun9i), must be a multiple of 24. For the sun9i (A80), the tested values @@ -706,7 +741,9 @@ endif config DRAM_ZQ int "sunxi dram zq value" - depends on !MACH_SUN50I_H616 && !MACH_SUN50I_A133 + depends on !MACH_SUN50I_H616 + depends on !MACH_SUN50I_A133 + depends on !MACH_SUN55I_A523 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T default 127 if MACH_SUN7I @@ -720,6 +757,7 @@ config DRAM_ZQ config DRAM_ODT_EN bool "sunxi dram odt enable" depends on !MACH_SUN50I_H616 + depends on !MACH_SUN55I_A523 default y if MACH_SUN8I_A23 default y if MACH_SUNXI_H3_H5 default y if MACH_SUN8I_R40 @@ -809,6 +847,7 @@ endif config SYS_CLK_FREQ default 408000000 if MACH_SUNIV + default 792000000 if MACH_SUN55I_A523 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5 default 888000000 if MACH_SUN50I_H6 default 912000000 if MACH_SUN7I @@ -827,6 +866,7 @@ config SYS_CONFIG_NAME default "sun50i" if MACH_SUN50I_H6 default "sun50i" if MACH_SUN50I_H616 default "sun50i" if MACH_SUN50I_A133 + default "sun55i" if MACH_SUN55I_A523 config SYS_BOARD default "sunxi" @@ -893,7 +933,7 @@ config I2C1_ENABLE ---help--- See I2C0_ENABLE help text. -if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 +if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 config R_I2C_ENABLE bool "Enable the PRCM I2C/TWI controller" # This is used for the pmic on H3 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 8eff20b77bf..579530f27e3 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -47,4 +47,6 @@ obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ obj-$(CONFIG_DRAM_SUN50I_A133) += dram_sun50i_a133.o obj-$(CONFIG_DRAM_SUN50I_A133) += dram_timings/ +obj-$(CONFIG_MACH_SUN55I_A523) += dram_sun55i_a523.o +obj-$(CONFIG_DRAM_SUN55I_A523) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 08d55b3a0e3..fb4837c2082 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -141,6 +141,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN55I_A523) + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), 2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(10), 2); + sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); @@ -197,6 +201,7 @@ static int gpio_init(void) if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) { val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + /* TODO: A523: keep only the lower two bits? */ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); } if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) { @@ -502,6 +507,12 @@ void reset_cpu(void) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } +#elif defined(CONFIG_MACH_SUN55I_A523) + static const void *wdog = (void *)SUNXI_TIMER_BASE; + + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdog + WDT_SRST_REG); + while (1) + ; #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) #if defined(CONFIG_MACH_SUN50I_H6) /* WDOG is broken for some H6 rev. use the R_WDOG instead */ diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 3f375a51965..80004f13a1e 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -1,7 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <asm/arch/prcm.h> +#include <linux/delay.h> + +#ifndef SUNXI_CPU_PLL_CFG_BASE +#define SUNXI_CPU_PLL_CFG_BASE 0 +#endif #ifdef CONFIG_XPL_BUILD void clock_init_safe(void) @@ -9,15 +16,22 @@ void clock_init_safe(void) void *const ccm = (void *)SUNXI_CCM_BASE; void *const prcm = (void *)SUNXI_PRCM_BASE; - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { - /* this seems to enable PLLs on H616 */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10); + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x200); + udelay(1); + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2); - } + udelay(1); if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || - IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + IS_ENABLED(CONFIG_MACH_SUN50I_H6) || + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); + udelay(1); setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); } @@ -31,12 +45,13 @@ void clock_init_safe(void) clock_set_pll1(408000000); writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG); - while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK)) + while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL_LOCK)) ; - clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, - CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, - CCM_CPU_AXI_DEFAULT_FACTORS); + if (!IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, + CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, + CCM_CPU_AXI_DEFAULT_FACTORS); writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG); #ifdef CCM_AHB3_DEFAULT @@ -48,7 +63,15 @@ void clock_init_safe(void) * The mux and factor are set, but the clock will be enabled in * DRAM initialization code. */ - writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG); + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { + writel(MBUS_RESET, ccm + CCU_H6_MBUS_CFG); + udelay(1); + writel(MBUS_UPDATE | MBUS_CLK_SRC_OSCM24 | MBUS_CLK_M(4), + ccm + CCU_H6_MBUS_CFG); + } else { + writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), + ccm + CCU_H6_MBUS_CFG); + } } void clock_init_uart(void) @@ -70,38 +93,118 @@ void clock_init_uart(void) 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } -void clock_set_pll1(unsigned int clk) +static bool has_pll_output_gate(void) { - void *const ccm = (void *)SUNXI_CCM_BASE; + return (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || + IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN50I_A133)); +} + +/* A shared routine to program the CPU PLLs for H6, H616, T113, A523 */ +static void clock_set_pll(u32 *reg, unsigned int n) +{ + u32 val = readl(reg); + + /* clear the lock enable bit */ + val &= ~CCM_PLL_LOCK_EN; + writel(val, reg); + + /* gate the output on the newer SoCs */ + if (has_pll_output_gate()) { + val &= ~CCM_PLL_OUT_EN; + writel(val, reg); + } + + val &= ~(CCM_PLL1_CTRL_N_MASK | GENMASK(3, 0) | GENMASK(21, 16)); + val |= CCM_PLL1_CTRL_N(n); + writel(val, reg); /* program parameter */ + + val |= CCM_PLL_CTRL_EN; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + val |= CCM_PLL_LDO_EN; + writel(val, reg); /* enable PLL */ + + val |= CCM_PLL_LOCK_EN; + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + val |= CCM_PLL1_UPDATE; + writel(val, reg); /* start locking process */ + + while (!(readl(reg) & CCM_PLL_LOCK)) { /* wait for lock bit */ + } + udelay(20); /* wait as per manual */ + + /* un-gate the output on the newer SoCs */ + if (has_pll_output_gate()) { + val |= CCM_PLL_OUT_EN; + writel(val, reg); + } +} + +/* Program the PLLs for both clusters plus the DSU. */ +static void clock_a523_set_cpu_plls(unsigned int n_factor) +{ + void *const cpc = (void *)SUNXI_CPU_PLL_CFG_BASE; u32 val; - /* Do not support clocks < 288MHz as they need factor P */ - if (clk < 288000000) clk = 288000000; + val = CPU_CLK_SRC_HOSC | CPU_CLK_CTRL_P(0) | + CPU_CLK_APB_DIV(4) | CPU_CLK_PERI_DIV(2) | + CPU_CLK_AXI_DIV(2); + + /* Switch CPU clock source to 24MHz HOSC while changing the PLL */ + writel(val, cpc + CPC_CPUA_CLK_REG); + writel(val, cpc + CPC_CPUB_CLK_REG); + udelay(20); + writel(CPU_CLK_SRC_HOSC | CPU_CLK_CTRL_P(0), + cpc + CPC_DSU_CLK_REG); + udelay(20); - /* Switch to 24MHz clock while changing PLL1 */ + clock_set_pll(cpc + CPC_CPUA_PLL_CTRL, n_factor); + clock_set_pll(cpc + CPC_CPUB_PLL_CTRL, n_factor); + clock_set_pll(cpc + CPC_DSU_PLL_CTRL, n_factor); + + /* Switch CPU clock source to the CPU PLL */ + clrsetbits_le32(cpc + CPC_CPUA_CLK_REG, CPU_CLK_SRC_HOSC, + CPU_CLK_SRC_CPUPLL); + clrsetbits_le32(cpc + CPC_CPUB_CLK_REG, CPU_CLK_SRC_HOSC, + CPU_CLK_SRC_CPUPLL); + clrsetbits_le32(cpc + CPC_DSU_CLK_REG, CPU_CLK_SRC_HOSC, + CPU_CLK_SRC_CPUPLL); +} + +static void clock_h6_set_cpu_pll(unsigned int n_factor) +{ + void *const ccm = (void *)SUNXI_CCM_BASE; + u32 val; + + /* Switch CPU clock source to 24MHz HOSC while changing the PLL */ val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_OSC24M; writel(val, ccm + CCU_H6_CPU_AXI_CFG); - /* clk = 24*n/p, p is ignored if clock is >288MHz */ - val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; - val |= CCM_PLL1_CTRL_N(clk / 24000000); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || - IS_ENABLED(CONFIG_MACH_SUN50I_A133)) - val |= CCM_PLL1_OUT_EN; - if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) - val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; - writel(val, ccm + CCU_H6_PLL1_CFG); - while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {} + clock_set_pll(ccm + CCU_H6_PLL1_CFG, n_factor); - /* Switch CPU to PLL1 */ + /* Switch CPU clock source to the CPU PLL */ val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_PLL_CPUX; writel(val, ccm + CCU_H6_CPU_AXI_CFG); } +void clock_set_pll1(unsigned int clk) +{ + /* Do not support clocks < 288MHz as they need factor P */ + if (clk < 288000000) + clk = 288000000; + + clk /= 24000000; + + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + clock_a523_set_cpu_plls(clk); + else + clock_h6_set_cpu_pll(clk); +} + int clock_twi_onoff(int port, int state) { void *const ccm = (void *)SUNXI_CCM_BASE; diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 3f4735d4717..c3a51d9956e 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -106,6 +106,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner H616 (SUN50I)\n"); #elif defined CONFIG_MACH_SUN50I_A133 puts("CPU: Allwinner A133 (SUN50I)\n"); +#elif defined CONFIG_MACH_SUN55I_A523 + puts("CPU: Allwinner A523 (SUN55I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index a0fca3738f4..3a231141168 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -78,19 +78,19 @@ static void mctl_clk_init(u32 clk) clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); - clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN); clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set up PLL5 clock, used for DRAM */ clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0xff03, - CCM_PLL5_CTRL_N((clk * 2) / 24) | CCM_PLL5_CTRL_EN); + CCM_PLL5_CTRL_N((clk * 2) / 24) | CCM_PLL_CTRL_EN); setbits_le32(ccm + CCU_H6_PLL5_CFG, BIT(24)); clrsetbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3, - CCM_PLL5_LOCK_EN | CCM_PLL5_CTRL_EN | BIT(30)); - clrbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3 | BIT(30)); + CCM_PLL_LOCK_EN | CCM_PLL_CTRL_EN | CCM_PLL_LDO_EN); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, 0x3 | CCM_PLL_LDO_EN); mctl_await_completion(ccm + CCU_H6_PLL5_CFG, - CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL_LOCK, CCM_PLL_LOCK); /* Enable DRAM clock and gate*/ clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, BIT(24) | BIT(25)); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 84fd64a2bfc..ea26e6dd327 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -167,16 +167,16 @@ static void mctl_sys_init(u32 clk_rate) clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0)); udelay(5); writel(0, ccm + CCU_H6_DRAM_GATE_RESET); - clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN); clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ - writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | + writel(CCM_PLL_CTRL_EN | CCM_PLL_LOCK_EN | CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); mctl_await_completion(ccm + CCU_H6_PLL5_CFG, - CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL_LOCK, CCM_PLL_LOCK); /* Configure DRAM mod clock */ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 5a59f82d1ef..877181016f3 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -106,16 +106,16 @@ static void mctl_sys_init(u32 clk_rate) clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); udelay(5); clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); - clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN); clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ - writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN | + writel(CCM_PLL_CTRL_EN | CCM_PLL_LOCK_EN | CCM_PLL_OUT_EN | CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); mctl_await_completion(ccm + CCU_H6_PLL5_CFG, - CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL_LOCK, CCM_PLL_LOCK); /* Configure DRAM mod clock */ writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); diff --git a/arch/arm/mach-sunxi/dram_sun55i_a523.c b/arch/arm/mach-sunxi/dram_sun55i_a523.c new file mode 100644 index 00000000000..30bbeb40d0b --- /dev/null +++ b/arch/arm/mach-sunxi/dram_sun55i_a523.c @@ -0,0 +1,1590 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sun55i A523/A527/T527/H728 platform DRAM controller driver + * + * This driver supports DDR3 and LPDDR4 memory. + * + * (C) Copyright 2024 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ +#include <init.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> +#include <asm/arch/prcm.h> +#include <linux/bitops.h> +#include <linux/delay.h> + +static void mctl_sys_init(u32 clk_rate) +{ + void * const ccm = (void *)SUNXI_CCM_BASE; + + /* Put all DRAM-related blocks to reset state */ + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_UPDATE); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); + udelay(5); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL_CTRL_EN); + clrsetbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, + DRAM_CLK_ENABLE, DRAM_CLK_UPDATE); + + udelay(5); + + /* Set PLL5 rate to doubled DRAM clock rate */ + writel(CCM_PLL_CTRL_EN | CCM_PLL_LDO_EN | CCM_PLL_LOCK_EN | + CCM_PLL_OUT_EN | CCM_PLL5_CTRL_N(clk_rate * 2 / 24), + ccm + CCU_H6_PLL5_CFG); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL_LOCK, CCM_PLL_LOCK); + + /* Configure DRAM mod clock */ + writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); + writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET); + udelay(5); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); + + /* Configure MBUS and enable DRAM clock */ + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET | MBUS_UPDATE); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE | MBUS_UPDATE); + + clrsetbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_M_MASK, + DRAM_CLK_ENABLE | DRAM_CLK_UPDATE | DRAM_CLK_M(4)); + udelay(5); +} + +static void mctl_set_addrmap(const struct dram_config *config) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u8 cols = config->cols; + u8 rows = config->rows; + u8 ranks = config->ranks; + + if (!config->bus_full_width) + cols -= 1; + + /* Ranks */ + if (ranks == 2) + mctl_ctl->addrmap[0] = 0x1F00 | (rows + cols - 3); + else + mctl_ctl->addrmap[0] = 0x1F1F; + + /* Banks, hardcoded to 8 banks now */ + mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16; + + /* Columns */ + mctl_ctl->addrmap[2] = 0; + switch (cols) { + case 7: + mctl_ctl->addrmap[3] = 0x1F1F1F00; + mctl_ctl->addrmap[4] = 0x1F1F; + break; + case 8: + mctl_ctl->addrmap[3] = 0x1F1F0000; + mctl_ctl->addrmap[4] = 0x1F1F; + break; + case 9: + mctl_ctl->addrmap[3] = 0x1F000000; + mctl_ctl->addrmap[4] = 0x1F1F; + break; + case 10: + mctl_ctl->addrmap[3] = 0; + mctl_ctl->addrmap[4] = 0x1F1F; + break; + case 11: + mctl_ctl->addrmap[3] = 0; + mctl_ctl->addrmap[4] = 0x1F00; + break; + case 12: + mctl_ctl->addrmap[3] = 0; + mctl_ctl->addrmap[4] = 0; + break; + default: + panic("Unsupported DRAM configuration: column number invalid\n"); + } + + /* Rows */ + mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | + ((cols - 3) << 16) | ((cols - 3) << 24); + switch (rows) { + case 13: + mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00; + mctl_ctl->addrmap[7] = 0x0F0F; + break; + case 14: + mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | + 0x0F0F0000; + mctl_ctl->addrmap[7] = 0x0F0F; + break; + case 15: + mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | + ((cols - 3) << 16) | 0x0F000000; + mctl_ctl->addrmap[7] = 0x0F0F; + break; + case 16: + mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | + ((cols - 3) << 16) | ((cols - 3) << 24); + mctl_ctl->addrmap[7] = 0x0F0F; + break; + case 17: + mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | + ((cols - 3) << 16) | ((cols - 3) << 24); + mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00; + break; + case 18: + mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | + ((cols - 3) << 16) | ((cols - 3) << 24); + mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8); + break; + default: + panic("Unsupported DRAM configuration: row number invalid\n"); + } + + /* Bank groups, DDR4 only */ + mctl_ctl->addrmap[8] = 0x3F3F; +} + +#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f) +static void mctl_phy_configure_odt(const struct dram_para *para) +{ + u32 val_lo, val_hi; + + val_hi = para->dx_dri; + val_lo = (para->type != SUNXI_DRAM_TYPE_LPDDR4) ? para->dx_dri : + (para->tpr1 & 0x1f1f1f1f) ? para->tpr1 : 0x04040404; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x304, 0x1f1f0000, + (MASK_BYTE(val_hi, 0) << 24) | + (MASK_BYTE(val_lo, 0) << 16)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x484, 0x1f1f0000, + (MASK_BYTE(val_hi, 1) << 24) | + (MASK_BYTE(val_lo, 1) << 16)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x604, 0x1f1f0000, + (MASK_BYTE(val_hi, 2) << 24) | + (MASK_BYTE(val_lo, 2) << 16)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x784, 0x1f1f0000, + (MASK_BYTE(val_hi, 3) << 24) | + (MASK_BYTE(val_lo, 3) << 16)); + + val_lo = para->ca_dri; + val_hi = para->ca_dri; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xf4, 0x1f1f1f1f, + (MASK_BYTE(val_hi, 0) << 24) | + (MASK_BYTE(val_lo, 0) << 16) | + (MASK_BYTE(val_hi, 1) << 8) | + (MASK_BYTE(val_lo, 1))); + + val_hi = para->dx_odt; + val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x304, 0x00001f1f, + (MASK_BYTE(val_hi, 0) << 8) | MASK_BYTE(val_lo, 0)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x484, 0x00001f1f, + (MASK_BYTE(val_hi, 1) << 8) | MASK_BYTE(val_lo, 1)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x604, 0x00001f1f, + (MASK_BYTE(val_hi, 2) << 8) | MASK_BYTE(val_lo, 2)); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x784, 0x00001f1f, + (MASK_BYTE(val_hi, 3) << 8) | MASK_BYTE(val_lo, 3)); +} + +static bool mctl_phy_write_leveling(const struct dram_para *para, + const struct dram_config *config) +{ + u32 mr2, low, high, val = 0; + bool result = true; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0xf00, 0xe00); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + if (config->clk <= 936) + mr2 = 0x1b; + else if (config->clk <= 1200) + mr2 = 0x2d; + else + mr2 = 0x36; + writeb(mr2, SUNXI_DRAM_PHY0_BASE + 3); + } + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) | 4; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + if (config->bus_full_width) + val = 0xf; + else + val = 3; + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x62), val, val); + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) & 0xfffb; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + val = readl(SUNXI_DRAM_PHY0_BASE + 0x96); + if (val == 0 || val == 0x3f) + result = false; + val = readl(SUNXI_DRAM_PHY0_BASE + 0x97); //TODO: ??? + if (val == 0 || val == 0x3f) + result = false; + val = readl(SUNXI_DRAM_PHY0_BASE + 0xc6); + if (val == 0 || val == 0x3f) + result = false; + val = readl(SUNXI_DRAM_PHY0_BASE + 0xc7); //TODO: ??? + if (val == 0 || val == 0x3f) + result = false; + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) & 0xff3f; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + if (config->ranks == 2) { + low = (readw(SUNXI_DRAM_PHY0_BASE + 2) & 0xff3f) | 0x40; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) | 4; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + if (config->bus_full_width) + val = 0xf; + else + val = 3; + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x62), val, val); + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) & 0xfffb; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + } + + low = readw(SUNXI_DRAM_PHY0_BASE + 2) & 0xff3f; + high = readw(SUNXI_DRAM_PHY0_BASE + 4); + writew(low, SUNXI_DRAM_PHY0_BASE + 2); + writew(high, SUNXI_DRAM_PHY0_BASE + 4); + + return result; +} + +static bool mctl_phy_read_calibration(const struct dram_para *para, + const struct dram_config *config) +{ + bool result = true; + u32 val; + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x44, 0x20000000); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x3c, 0x38); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 1); + + if (config->bus_full_width) + val = 0xf; + else + val = 3; + + while ((readl(SUNXI_DRAM_PHY0_BASE + 0x20c) & val) != val) { + if (readl(SUNXI_DRAM_PHY0_BASE + 0x20c) & 0x20) { + result = false; + break; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x3c); + + if (config->ranks == 2) { + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x3c, 0x34); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 1); + + while ((readl(SUNXI_DRAM_PHY0_BASE + 0x20c) & val) != val) { + if (readl(SUNXI_DRAM_PHY0_BASE + 0x20c) & 0x20) { + result = false; + break; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x3c); + } + + return result; +} + +static bool mctl_phy_read_training(const struct dram_para *para, + const struct dram_config *config) +{ + u32 val1, val2, *ptr1, *ptr2; + bool result = true; + int i; + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + writel(0, SUNXI_DRAM_PHY0_BASE + 0x200); + writeb(0, SUNXI_DRAM_PHY0_BASE + 0x207); + writeb(0, SUNXI_DRAM_PHY0_BASE + 0x208); + writeb(0, SUNXI_DRAM_PHY0_BASE + 0x209); + writeb(0, SUNXI_DRAM_PHY0_BASE + 0x20a); + } + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x804, 0x3f, 0xf); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x808, 0x3f, 0xf); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa04, 0x3f, 0xf); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa08, 0x3f, 0xf); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1); + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc); + if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3) + result = false; + + if (config->bus_full_width) { + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc); + if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3) + result = false; + } + + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x850); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x874); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + + if (config->bus_full_width) { + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa74); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 3); + + if (config->ranks == 2) { + /* maybe last parameter should be 1? */ + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1); + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc); + if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3) + result = false; + + if (config->bus_full_width) { + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc); + if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3) + result = false; + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 3); + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3); + + return result; +} + +static bool mctl_phy_write_training(const struct dram_config *config) +{ + u32 val1, val2, *ptr1, *ptr2; + bool result = true; + int i; + + writel(0, SUNXI_DRAM_PHY0_BASE + 0x134); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x138); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x19c); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x1a0); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc, 8); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20); + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3); + if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc) + result = false; + + if (config->bus_full_width) { + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3); + if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc) + result = false; + } + + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x938); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8f0); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x95c); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x914); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + + if (config->bus_full_width) { + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb38); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xaf0); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb5c); + ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb14); + for (i = 0; i < 9; i++) { + val1 = readl(&ptr1[i]); + val2 = readl(&ptr2[i]); + if (val1 - val2 <= 6) + result = false; + } + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x60); + + if (config->ranks == 2) { + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc, 4); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20); + + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3); + if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc) + result = false; + + if (config->bus_full_width) { + mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3); + if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc) + result = false; + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x60); + } + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 0xc); + + return result; +} + +static void mctl_phy_bit_delay_compensation(const struct dram_para *para, + const struct dram_config *config) +{ + u8 array0[32], array1[32]; + u32 tmp; + int i; + + for (i = 0; i < 32; i++) { + array0[i] = (config->tpr11 >> (i & 0xf8)) & 0xff; + array1[i] = (config->tpr12 >> (i & 0xf8)) & 0x7f; + } + + if (para->tpr10 & TPR10_DX_BIT_DELAY1) { + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa0, 3); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x80); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x44, BIT(28)); + + writel(array0[0], SUNXI_DRAM_PHY0_BASE + 0x320); + writel((array0[0] << 24) | (array0[1] << 16) | + (array0[2] << 8) | + array0[3], SUNXI_DRAM_PHY0_BASE + 0x324); + writel((array0[4] << 24) | (array0[5] << 16) | + (array0[6] << 8) | + array0[7], SUNXI_DRAM_PHY0_BASE + 0x328); + + writel(array0[0], SUNXI_DRAM_PHY0_BASE + 0x340); + writel((array0[0] << 24) | (array0[1] << 16) | + (array0[2] << 8) | + array0[3], SUNXI_DRAM_PHY0_BASE + 0x344); + writel((array0[4] << 24) | (array0[5] << 16) | + (array0[6] << 8) | + array0[7], SUNXI_DRAM_PHY0_BASE + 0x348); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x40c, 0xff00, + array0[0] << 8); + writel((array0[0] << 24) | (array0[1] << 16) | + (array0[2] << 8) | array0[3], + SUNXI_DRAM_PHY0_BASE + 0x400); + writel((array0[4] << 24) | (array0[5] << 16) | + (array0[6] << 8) | array0[7], + SUNXI_DRAM_PHY0_BASE + 0x404); + + writel(array0[0], SUNXI_DRAM_PHY0_BASE + 0x41c); + writel((array0[0] << 24) | (array0[1] << 16) | + (array0[2] << 8) | array0[3], + SUNXI_DRAM_PHY0_BASE + 0x420); + writel((array0[4] << 24) | (array0[5] << 16) | + (array0[6] << 8) | array0[7], + SUNXI_DRAM_PHY0_BASE + 0x424); + + tmp = config->odt_en & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x32c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x34c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x408); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x428); + + writel(array0[8], SUNXI_DRAM_PHY0_BASE + 0x4a0); + writel((array0[8] << 24) | (array0[9] << 16) | + (array0[10] << 8) | array0[11], + SUNXI_DRAM_PHY0_BASE + 0x4a4); + writel((array0[12] << 24) | (array0[13] << 16) | + (array0[14] << 8) | array0[15], + SUNXI_DRAM_PHY0_BASE + 0x4a8); + + writel(array0[8], SUNXI_DRAM_PHY0_BASE + 0x4c0); + writel((array0[8] << 24) | (array0[9] << 16) | + (array0[10] << 8) | array0[11], + SUNXI_DRAM_PHY0_BASE + 0x4c4); + writel((array0[12] << 24) | (array0[13] << 16) | + (array0[14] << 8) | array0[15], + SUNXI_DRAM_PHY0_BASE + 0x4c8); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x58c, 0xff00, + array0[8] << 8); + writel((array0[8] << 24) | (array0[9] << 16) | + (array0[10] << 8) | array0[11], + SUNXI_DRAM_PHY0_BASE + 0x580); + writel((array0[12] << 24) | (array0[13] << 16) | + (array0[14] << 8) | array0[15], + SUNXI_DRAM_PHY0_BASE + 0x584); + + writel(array0[8], SUNXI_DRAM_PHY0_BASE + 0x59c); + writel((array0[8] << 24) | (array0[9] << 16) | + (array0[10] << 8) | array0[11], + SUNXI_DRAM_PHY0_BASE + 0x5a0); + writel((array0[12] << 24) | (array0[13] << 16) | + (array0[14] << 8) | array0[15], + SUNXI_DRAM_PHY0_BASE + 0x5a4); + + tmp = (config->odt_en >> 8) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x4ac); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x4cc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x588); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x5a8); + + writel(array0[16], SUNXI_DRAM_PHY0_BASE + 0x620); + writel((array0[16] << 24) | (array0[17] << 16) | + (array0[18] << 8) | array0[19], + SUNXI_DRAM_PHY0_BASE + 0x624); + writel((array0[20] << 24) | (array0[21] << 16) | + (array0[22] << 8) | array0[23], + SUNXI_DRAM_PHY0_BASE + 0x628); + + writel(array0[16], SUNXI_DRAM_PHY0_BASE + 0x640); + writel((array0[16] << 24) | (array0[17] << 16) | + (array0[18] << 8) | array0[19], + SUNXI_DRAM_PHY0_BASE + 0x644); + writel((array0[20] << 24) | (array0[21] << 16) | + (array0[22] << 8) | array0[23], + SUNXI_DRAM_PHY0_BASE + 0x648); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x70c, + 0xff00, array0[16] << 8); + writel((array0[16] << 24) | (array0[17] << 16) | + (array0[18] << 8) | array0[19], + SUNXI_DRAM_PHY0_BASE + 0x700); + writel((array0[20] << 24) | (array0[21] << 16) | + (array0[22] << 8) | array0[23], + SUNXI_DRAM_PHY0_BASE + 0x704); + + writel(array0[16], SUNXI_DRAM_PHY0_BASE + 0x71c); + writel((array0[16] << 24) | (array0[17] << 16) | + (array0[18] << 8) | array0[19], + SUNXI_DRAM_PHY0_BASE + 0x720); + writel((array0[20] << 24) | (array0[21] << 16) | + (array0[22] << 8) | array0[23], SUNXI_DRAM_PHY0_BASE + 0x724); + + tmp = (config->odt_en >> 16) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x62c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x64c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x708); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x728); + + writel(array0[24], SUNXI_DRAM_PHY0_BASE + 0x7a0); + writel((array0[24] << 24) | (array0[25] << 16) | + (array0[26] << 8) | array0[27], + SUNXI_DRAM_PHY0_BASE + 0x7a4); + writel((array0[28] << 24) | (array0[29] << 16) | + (array0[30] << 8) | array0[31], + SUNXI_DRAM_PHY0_BASE + 0x7a8); + + writel(array0[24], SUNXI_DRAM_PHY0_BASE + 0x7c0); + writel((array0[24] << 24) | (array0[25] << 16) | + (array0[26] << 8) | array0[27], + SUNXI_DRAM_PHY0_BASE + 0x7c4); + writel((array0[28] << 24) | (array0[29] << 16) | + (array0[30] << 8) | array0[31], + SUNXI_DRAM_PHY0_BASE + 0x7c8); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x88c, 0xff00, + array0[24] << 8); + writel((array0[24] << 24) | (array0[25] << 16) | + (array0[26] << 8) | array0[27], + SUNXI_DRAM_PHY0_BASE + 0x880); + writel((array0[28] << 24) | (array0[29] << 16) | + (array0[30] << 8) | array0[31], + SUNXI_DRAM_PHY0_BASE + 0x884); + + writel(array0[24], SUNXI_DRAM_PHY0_BASE + 0x89c); + writel((array0[24] << 24) | (array0[25] << 16) | + (array0[26] << 8) | array0[27], + SUNXI_DRAM_PHY0_BASE + 0x8a0); + writel((array0[28] << 24) | (array0[29] << 16) | + (array0[30] << 8) | array0[31], + SUNXI_DRAM_PHY0_BASE + 0x8a4); + + tmp = (config->odt_en >> 24) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x7ac); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x7cc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x888); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x8a8); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x44, BIT(28)); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x44, BIT(28)); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + } + + if (para->tpr10 & TPR10_DX_BIT_DELAY0) { + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + + writel(array1[0] << 8, SUNXI_DRAM_PHY0_BASE + 0x330); + writel((array1[0] << 24) | (array1[1] << 16) | + (array1[2] << 8) | array1[3], + SUNXI_DRAM_PHY0_BASE + 0x334); + writel((array1[4] << 24) | (array1[5] << 16) | + (array1[6] << 8) | array1[7], + SUNXI_DRAM_PHY0_BASE + 0x338); + + writel(array1[0] << 8, SUNXI_DRAM_PHY0_BASE + 0x350); + writel((array1[0] << 24) | (array1[1] << 16) | + (array1[2] << 8) | array1[3], + SUNXI_DRAM_PHY0_BASE + 0x354); + writel((array1[4] << 24) | (array1[5] << 16) | + (array1[6] << 8) | array1[7], + SUNXI_DRAM_PHY0_BASE + 0x358); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x40c, 0xff, array1[0]); + writel((array1[0] << 24) | (array1[1] << 16) | + (array1[2] << 8) | array1[3], + SUNXI_DRAM_PHY0_BASE + 0x410); + writel((array1[4] << 24) | (array1[5] << 16) | + (array1[6] << 8) | array1[7], + SUNXI_DRAM_PHY0_BASE + 0x414); + + writel(array1[0] << 8, SUNXI_DRAM_PHY0_BASE + 0x42c); + writel((array1[0] << 24) | (array1[1] << 16) | + (array1[2] << 8) | array1[3], + SUNXI_DRAM_PHY0_BASE + 0x430); + writel((array1[4] << 24) | (array1[5] << 16) | + (array1[6] << 8) | array1[7], + SUNXI_DRAM_PHY0_BASE + 0x434); + + tmp = config->tpr14 & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x33c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x35c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x418); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x438); + + writel(array1[8] << 8, SUNXI_DRAM_PHY0_BASE + 0x4b0); + writel((array1[8] << 24) | (array1[9] << 16) | + (array1[10] << 8) | array1[11], + SUNXI_DRAM_PHY0_BASE + 0x4b4); + writel((array1[12] << 24) | (array1[13] << 16) | + (array1[14] << 8) | array1[15], + SUNXI_DRAM_PHY0_BASE + 0x4b8); + + writel(array1[8] << 8, SUNXI_DRAM_PHY0_BASE + 0x4d0); + writel((array1[8] << 24) | (array1[9] << 16) | + (array1[10] << 8) | array1[11], + SUNXI_DRAM_PHY0_BASE + 0x4d4); + writel((array1[12] << 24) | (array1[13] << 16) | + (array1[14] << 8) | array1[15], + SUNXI_DRAM_PHY0_BASE + 0x4d8); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x58c, 0xff, array1[8]); + writel((array1[8] << 24) | (array1[9] << 16) | + (array1[10] << 8) | array1[11], + SUNXI_DRAM_PHY0_BASE + 0x590); + writel((array1[12] << 24) | (array1[13] << 16) | + (array1[14] << 8) | array1[15], + SUNXI_DRAM_PHY0_BASE + 0x594); + + writel(array1[8] << 8, SUNXI_DRAM_PHY0_BASE + 0x5ac); + writel((array1[8] << 24) | (array1[9] << 16) | + (array1[10] << 8) | array1[11], + SUNXI_DRAM_PHY0_BASE + 0x5b0); + writel((array1[12] << 24) | (array1[13] << 16) | + (array1[14] << 8) | array1[15], + SUNXI_DRAM_PHY0_BASE + 0x5b4); + + tmp = (config->tpr14 >> 8) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x4bc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x4dc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x598); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x5b8); + + writel(array1[16] << 8, SUNXI_DRAM_PHY0_BASE + 0x630); + writel((array1[16] << 24) | (array1[17] << 16) | + (array1[18] << 8) | array1[19], + SUNXI_DRAM_PHY0_BASE + 0x634); + writel((array1[20] << 24) | (array1[21] << 16) | + (array1[22] << 8) | array1[23], + SUNXI_DRAM_PHY0_BASE + 0x638); + + writel(array1[16] << 8, SUNXI_DRAM_PHY0_BASE + 0x650); + writel((array1[16] << 24) | (array1[17] << 16) | + (array1[18] << 8) | array1[19], + SUNXI_DRAM_PHY0_BASE + 0x654); + writel((array1[20] << 24) | (array1[21] << 16) | + (array1[22] << 8) | array1[23], + SUNXI_DRAM_PHY0_BASE + 0x658); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x70c, 0xff, array1[16]); + writel((array1[16] << 24) | (array1[17] << 16) | + (array1[18] << 8) | array1[19], + SUNXI_DRAM_PHY0_BASE + 0x710); + writel((array1[20] << 24) | (array1[21] << 16) | + (array1[22] << 8) | array1[23], + SUNXI_DRAM_PHY0_BASE + 0x714); + + writel(array1[16] << 8, SUNXI_DRAM_PHY0_BASE + 0x72c); + writel((array1[16] << 24) | (array1[17] << 16) | + (array1[18] << 8) | array1[19], + SUNXI_DRAM_PHY0_BASE + 0x730); + writel((array1[20] << 24) | (array1[21] << 16) | + (array1[22] << 8) | array1[23], + SUNXI_DRAM_PHY0_BASE + 0x734); + + tmp = (config->tpr14 >> 16) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x63c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x65c); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x718); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x738); + + writel(array1[24] << 8, SUNXI_DRAM_PHY0_BASE + 0x7b0); + writel((array1[24] << 24) | (array1[25] << 16) | + (array1[26] << 8) | array1[27], + SUNXI_DRAM_PHY0_BASE + 0x7b4); + writel((array1[28] << 24) | (array1[29] << 16) | + (array1[30] << 8) | array1[31], + SUNXI_DRAM_PHY0_BASE + 0x7b8); + + writel(array1[24] << 8, SUNXI_DRAM_PHY0_BASE + 0x7d0); + writel((array1[24] << 24) | (array1[25] << 16) | + (array1[26] << 8) | array1[27], + SUNXI_DRAM_PHY0_BASE + 0x7d4); + writel((array1[28] << 24) | (array1[29] << 16) | + (array1[30] << 8) | array1[31], + SUNXI_DRAM_PHY0_BASE + 0x7d8); + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x88c, 0xff, array1[24]); + writel((array1[24] << 24) | (array1[25] << 16) | + (array1[26] << 8) | array1[27], + SUNXI_DRAM_PHY0_BASE + 0x890); + writel((array1[28] << 24) | (array1[29] << 16) | + (array1[30] << 8) | array1[31], + SUNXI_DRAM_PHY0_BASE + 0x894); + + writel(array1[24] << 8, SUNXI_DRAM_PHY0_BASE + 0x8ac); + writel((array1[24] << 24) | (array1[25] << 16) | + (array1[26] << 8) | array1[27], + SUNXI_DRAM_PHY0_BASE + 0x8b0); + writel((array1[28] << 24) | (array1[29] << 16) | + (array1[30] << 8) | array1[31], + SUNXI_DRAM_PHY0_BASE + 0x8b4); + + tmp = (config->tpr14 >> 24) & 0xff; + tmp = (tmp << 24) | (tmp << 8); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x7bc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x7dc); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x898); + writel(tmp, SUNXI_DRAM_PHY0_BASE + 0x8b8); + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x94, 4); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x94, 4); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + } +} + +static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para, + const struct dram_config *config) +{ + u32 val, low, high; + + if (para->tpr10 & BIT(31)) { + val = para->tpr0; + } else { + val = ((para->tpr10 & 0xf0) << 5) | ((para->tpr10 & 0xf) << 1); + if (para->tpr10 >> 29) + val <<= 1; + } + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0xac, 0x1000); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x48, 0xc0000000); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + case SUNXI_DRAM_TYPE_DDR4: + case SUNXI_DRAM_TYPE_LPDDR3: + low = val & 0xff; + high = (val >> 8) & 0xff; + + val = (high << 24) | (high << 16) | (high << 8) | high; + writel(val, SUNXI_DRAM_PHY0_BASE + 0x104); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x108); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x10c); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x114); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x118); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x11c); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x120); + + val = (low << 24) | (low << 16) | (high << 8) | high; + writel(val, SUNXI_DRAM_PHY0_BASE + 0x11c); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + low = val & 0xff; + high = (val >> 8) & 0xff; + + val = (high << 24) | (high << 16) | (high << 8) | high; + writel(val, SUNXI_DRAM_PHY0_BASE + 0x104); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x108); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x10c); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x114); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x118); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x11c); + writel(val, SUNXI_DRAM_PHY0_BASE + 0x120); + + val = (high << 24) | (high << 16) | (low << 8) | low; + writel(val, SUNXI_DRAM_PHY0_BASE + 0x110); + + val = (low << 24) | (high << 16) | (low << 8) | high; + writel(val, SUNXI_DRAM_PHY0_BASE + 0x11c); + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x38, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x38, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); +} + +static bool mctl_phy_init(const struct dram_para *para, + const struct dram_config *config) +{ + void * const mctl_com = (void *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; + u32 val, val2, mr1, mr2; + int i; + + clrbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 1); + udelay(1); + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x40000); + + if (config->bus_full_width) + val = 0xf00; + else + val = 0x300; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x00, 0xf00, val); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 9; + val2 = 13; + break; + case SUNXI_DRAM_TYPE_DDR4: + if (config->clk <= 936) { + val = 10; + val2 = 14; + } else if (config->clk <= 1200) { + val = 12; + val2 = 16; + } else { + val = 14; + val2 = 18; + } + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = 8; + val2 = 14; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + if (config->clk <= 936) { + val = 10; + val2 = 20; + } else if (config->clk <= 1200) { + val = 14; + val2 = 28; + } else { + val = 16; + val2 = 32; + } + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + writel((val << 24) | (val << 16) | (val << 8) | val, SUNXI_DRAM_PHY0_BASE + 0x10); + writel((val2 << 24) | (val2 << 16) | (val2 << 8) | val2, SUNXI_DRAM_PHY0_BASE + 0x0c); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x08); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + writel(0x150a0310, SUNXI_DRAM_PHY0_BASE + 0x54); + writel(0x13140816, SUNXI_DRAM_PHY0_BASE + 0x58); + writel(0x001c0d1b, SUNXI_DRAM_PHY0_BASE + 0x5c); + writel(0x050c1d1a, SUNXI_DRAM_PHY0_BASE + 0x60); + writel(0x0411060b, SUNXI_DRAM_PHY0_BASE + 0x64); + writel(0x09071217, SUNXI_DRAM_PHY0_BASE + 0x68); + writel(0x18190e01, SUNXI_DRAM_PHY0_BASE + 0x6c); + writel(0x020f1e00, SUNXI_DRAM_PHY0_BASE + 0x70); + break; + case SUNXI_DRAM_TYPE_DDR4: + writel(0x090c1c14, SUNXI_DRAM_PHY0_BASE + 0x54); + writel(0x1300060f, SUNXI_DRAM_PHY0_BASE + 0x58); + writel(0x12030807, SUNXI_DRAM_PHY0_BASE + 0x5c); + writel(0x0b100a02, SUNXI_DRAM_PHY0_BASE + 0x60); + writel(0x1a110e05, SUNXI_DRAM_PHY0_BASE + 0x64); + writel(0x0d041617, SUNXI_DRAM_PHY0_BASE + 0x68); + writel(0x1819011b, SUNXI_DRAM_PHY0_BASE + 0x6c); + writel(0x151d1e00, SUNXI_DRAM_PHY0_BASE + 0x70); + break; + case SUNXI_DRAM_TYPE_LPDDR3: + writel(0x010a1a0f, SUNXI_DRAM_PHY0_BASE + 0x54); + writel(0x10081b07, SUNXI_DRAM_PHY0_BASE + 0x58); + writel(0x11061c12, SUNXI_DRAM_PHY0_BASE + 0x5c); + writel(0x00131409, SUNXI_DRAM_PHY0_BASE + 0x60); + writel(0x15030e16, SUNXI_DRAM_PHY0_BASE + 0x64); + writel(0x0b0c0d17, SUNXI_DRAM_PHY0_BASE + 0x68); + writel(0x18190204, SUNXI_DRAM_PHY0_BASE + 0x6c); + writel(0x051d1e00, SUNXI_DRAM_PHY0_BASE + 0x70); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + writel(0x00010203, SUNXI_DRAM_PHY0_BASE + 0x54); + writel(0x04050607, SUNXI_DRAM_PHY0_BASE + 0x58); + writel(0x08090a0b, SUNXI_DRAM_PHY0_BASE + 0x5c); + writel(0x0c0d0e0f, SUNXI_DRAM_PHY0_BASE + 0x60); + writel(0x10111213, SUNXI_DRAM_PHY0_BASE + 0x64); + writel(0x14151617, SUNXI_DRAM_PHY0_BASE + 0x68); + writel(0x18191a1b, SUNXI_DRAM_PHY0_BASE + 0x6c); + writel(0x1c1d1e00, SUNXI_DRAM_PHY0_BASE + 0x70); + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + mctl_phy_configure_odt(para); + + if (para->tpr10 & TPR10_CA_BIT_DELAY) + mctl_phy_ca_bit_delay_compensation(para, config); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 0x2bbd4900; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = 0x3841b800; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = 0x19016300; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = 0x18fd6300; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xa8, 0xffffff00, val); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x00, 0x70); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = 0x20; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = 0x40; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = 0x30; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = 0x50; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x00, val); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x00, 0x80); + + // TODO: fix intervals + if (config->clk - 251 < 250) { + val = 0x18000000; + val2 = 0x18181818; + } else if (config->clk - 126 < 125) { + val = 0x28000000; + val2 = 0x28282828; + } else if (config->clk < 126) { + val = 0x38000000; + val2 = 0x38383838; + } else { + val = 0x18000000; + val2 = 0; + } + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xc0, 0x78000000, val); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0xd0, 0x78787878, val2); + + clrbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(9)); + udelay(10); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + val = para->tpr6 & 0xff; + break; + case SUNXI_DRAM_TYPE_DDR4: + val = para->tpr6 >> 8 & 0xff; + break; + case SUNXI_DRAM_TYPE_LPDDR3: + val = para->tpr6 >> 16 & 0xff; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + val = para->tpr6 >> 24; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + val <<= 24; + + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x300, 0xff800060, val | 0x40); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x600, 0xff800060, val | 0x40); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x480, 0xff800060, val | 0x40); + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x780, 0xff800060, val | 0x40); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x8000000); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x94, 0x80); + udelay(10); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x94, 0x80); + udelay(10); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x84, 0x8000000); + + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x308, 0x200); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x488, 0x200); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x608, 0x200); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x788, 0x200); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x908, 0x200); + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x308, 0x200); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x488, 0x200); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x608, 0x200); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x788, 0x200); + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x908, 0x200); + } + + if (config->clk < 936) + val = 0x1b000000; + else + val = 0xc000000; + clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14, 0x1f000000, val); + + setbits_le32(mctl_com + MCTL_COM_MAER0, BIT(8)); + + /* start DFI init */ + writel(0, &mctl_ctl->swctl); + setbits_le32(&mctl_ctl->dfimisc, 1); + setbits_le32(&mctl_ctl->dfimisc, 0x20); + writel(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, 1, 1); + mctl_await_completion(&mctl_ctl->dfistat, 1, 1); + + udelay(500); + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 1); + udelay(1); + + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->dfimisc, 0x20); + writel(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, 1, 1); + + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->pwrctl, 0x20); + writel(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, 1, 1); + mctl_await_completion(&mctl_ctl->statr, 3, 1); + + udelay(500); + + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->dfimisc, 1); + writel(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, 1, 1); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + writel(0x1f14, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(4, &mctl_ctl->mrctrl1); + writel(0x800010f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x20, &mctl_ctl->mrctrl1); + writel(0x800020f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0, &mctl_ctl->mrctrl1); + writel(0x800030f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + break; + case SUNXI_DRAM_TYPE_LPDDR4: + if (config->clk <= 936) { + mr1 = 0x34; + mr2 = 0x1b; + } else if (config->clk <= 1200) { + mr1 = 0x54; + mr2 = 0x2d; + } else { + mr1 = 0x64; + mr2 = 0x36; + } + + writel(0x0, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x100 | mr1, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x200 | mr2, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x333, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x403, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0xb04, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0xc72, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0xd00, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0xe08, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + + writel(0x1626, &mctl_ctl->mrctrl1); + writel(0x800000f0, &mctl_ctl->mrctrl0); + mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->rfshctl3, 1); + writel(1, &mctl_ctl->swctl); + + if (para->tpr10 & TPR10_WRITE_LEVELING) { + for (i = 0; i < 5; i++) + if (mctl_phy_write_leveling(para, config)) + break; + if (i == 5) { + debug("write leveling failed!\n"); + return false; + } + } + + if (para->tpr10 & TPR10_READ_CALIBRATION) { + for (i = 0; i < 5; i++) + if (mctl_phy_read_calibration(para, config)) + break; + if (i == 5) { + debug("read calibration failed!\n"); + return false; + } + } + + if (para->tpr10 & TPR10_READ_TRAINING) { + for (i = 0; i < 5; i++) + if (mctl_phy_read_training(para, config)) + break; + if (i == 5) { + debug("read training failed!\n"); + return false; + } + } + + if (para->tpr10 & TPR10_WRITE_TRAINING) { + for (i = 0; i < 5; i++) + if (mctl_phy_write_training(config)) + break; + if (i == 5) { + debug("write training failed!\n"); + return false; + } + } + + mctl_phy_bit_delay_compensation(para, config); + + return true; +} + +static bool mctl_ctrl_init(const struct dram_para *para, + const struct dram_config *config) +{ + void * const mctl_com = (void *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u32 reg_val; + + clrsetbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24), BIT(25) | BIT(9)); + setbits_le32(mctl_com + MCTL_COM_MAER0, BIT(15) | BIT(9)); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + setbits_le32(0x02023ea8, 1); // NSI + setbits_le32(0x02071008, 1); // NSI_CPU + } + + clrsetbits_le32(&mctl_ctl->sched[0], 0xff08, 0x3000); + clrsetbits_le32(&mctl_ctl->sched[1], 0x77000000, 0x33000000); + clrsetbits_le32(&mctl_ctl->unk_0x270, 0xffff, 0x808); + clrsetbits_le32(&mctl_ctl->unk_0x264, 0xff00ffff, 0x1f000030); + + writel(0, &mctl_ctl->hwlpctl); + + reg_val = MSTR_ACTIVE_RANKS(config->ranks); + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + reg_val |= MSTR_BURST_LENGTH(16) | MSTR_DEVICETYPE_LPDDR4; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + if (config->bus_full_width) + reg_val |= MSTR_BUSWIDTH_FULL; + else + reg_val |= MSTR_BUSWIDTH_HALF; + writel(BIT(31) | BIT(30) | reg_val, &mctl_ctl->mstr); + + if (config->ranks == 2) + writel(0x0303, &mctl_ctl->odtmap); + else + writel(0x0201, &mctl_ctl->odtmap); + + switch (para->type) { + case SUNXI_DRAM_TYPE_DDR3: + reg_val = 0x06000400; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + reg_val = 0x04000400; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + writel(reg_val, &mctl_ctl->odtcfg); + writel(reg_val, &mctl_ctl->unk_0x2240); + writel(reg_val, &mctl_ctl->unk_0x3240); + writel(reg_val, &mctl_ctl->unk_0x4240); + + mctl_set_addrmap(config); + + mctl_set_timing_params(config->clk); + + writel(0, &mctl_ctl->pwrctl); + + setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x2180, BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30)); + setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30)); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) + setbits_le32(&mctl_ctl->dbictl, 0x1); + + setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); + clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); + + writel(0x20, &mctl_ctl->pwrctl); + setbits_le32(&mctl_ctl->clken, BIT(8)); + + clrsetbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24), BIT(9)); + udelay(1); + /* this write seems to enable PHY MMIO region */ + setbits_le32(mctl_com + MCTL_COM_UNK_008, BIT(24)); + + if (!mctl_phy_init(para, config)) + return false; + + writel(0, &mctl_ctl->swctl); + clrbits_le32(&mctl_ctl->rfshctl3, BIT(0)); + writel(1, &mctl_ctl->swctl); + mctl_await_completion(&mctl_ctl->swstat, 1, 1); + + return true; +} + +static bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) +{ + mctl_sys_init(config->clk); + + return mctl_ctrl_init(para, config); +} + +static void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config) +{ + /* this is minimum size that it's supported */ + config->cols = 8; + config->rows = 13; + + /* + * Strategy here is to test most demanding combination first and least + * demanding last, otherwise HW might not be fully utilized. For + * example, half bus width and rank = 1 combination would also work + * on HW with full bus width and rank = 2, but only 1/4 RAM would be + * visible. + */ + + debug("testing 32-bit width, rank = 2\n"); + config->bus_full_width = 1; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 32-bit width, rank = 1\n"); + config->bus_full_width = 1; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 2\n"); + config->bus_full_width = 0; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 1\n"); + config->bus_full_width = 0; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + panic("This DRAM setup is currently not supported.\n"); +} + +static void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) +{ + /* detect row address bits */ + config->cols = 8; + config->rows = 16; + mctl_core_init(para, config); + + for (config->rows = 13; config->rows < 16; config->rows++) { + /* 8 banks, 8 bit per byte and 16/32 bit width */ + if (mctl_mem_matches((1 << (config->rows + config->cols + + 4 + config->bus_full_width)))) + break; + } + + /* detect column address bits */ + config->cols = 11; + mctl_core_init(para, config); + + for (config->cols = 8; config->cols < 11; config->cols++) { + /* 8 bits per byte and 16/32 bit width */ + if (mctl_mem_matches(1 << (config->cols + 1 + + config->bus_full_width))) + break; + } +} + +static unsigned long long mctl_calc_size(const struct dram_config *config) +{ + u8 width = config->bus_full_width ? 4 : 2; + + /* 8 banks */ + return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; +} + +static const struct dram_para para = { +#ifdef CONFIG_SUNXI_DRAM_A523_DDR3 + .type = SUNXI_DRAM_TYPE_DDR3, +#elif defined(CONFIG_SUNXI_DRAM_A523_LPDDR4) + .type = SUNXI_DRAM_TYPE_LPDDR4, +#endif + .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT, + .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI, + .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI, + .tpr0 = CONFIG_DRAM_SUNXI_TPR0, + .tpr1 = CONFIG_DRAM_SUNXI_TPR1, + .tpr2 = CONFIG_DRAM_SUNXI_TPR2, + .tpr6 = CONFIG_DRAM_SUNXI_TPR6, + .tpr10 = CONFIG_DRAM_SUNXI_TPR10, +}; + +static void sunxi_nsi_init(void) +{ + /* IOMMU prio 3 */ + writel(0x1, 0x02021418); + writel(0xf, 0x02021414); + /* DE prio 2 */ + writel(0x1, 0x02021a18); + writel(0xa, 0x02021a14); + /* VE R prio 2 */ + writel(0x1, 0x02021618); + writel(0xa, 0x02021614); + /* VE RW prio 2 */ + writel(0x1, 0x02021818); + writel(0xa, 0x02021814); + /* ISP prio 2 */ + writel(0x1, 0x02020c18); + writel(0xa, 0x02020c14); + /* CSI prio 2 */ + writel(0x1, 0x02021c18); + writel(0xa, 0x02021c14); + /* NPU prio 2 */ + writel(0x1, 0x02020a18); + writel(0xa, 0x02020a14); + + /* close ra0 autogating */ + writel(0x0, 0x02023c00); + /* close ta autogating */ + writel(0x0, 0x02023e00); + /* close pcie autogating */ + writel(0x0, 0x02020600); +} + +static void init_something(void) + +{ + u32 *ptr = (u32 *)0x02000804; + + do { + *ptr++ = 0xffffffff; + } while (ptr != (u32 *)0x20008e4); + + writel(0, 0x07002400); + writel(0, 0x07002404); + writel(0, 0x07002408); + + writel(0xffffffff, 0x07002004); + writel(0xffffffff, 0x07002014); + writel(0xffffffff, 0x07002024); + setbits_le32(0x07010290, 7); + + writel(7, 0x02001f00); + writel(0xffff, 0x03002020); + writel(3, 0x020008e0); + writel(7, 0x07102008); +} + +unsigned long sunxi_dram_init(void) +{ + struct dram_config config; + unsigned long size; + + config.clk = 360; + switch (para.type) { + case SUNXI_DRAM_TYPE_DDR3: + config.odt_en = 0x90909090; + config.tpr11 = 0x8f919190; + config.tpr12 = 0x22222723; + config.tpr14 = 0x48484848; + break; + case SUNXI_DRAM_TYPE_LPDDR4: + config.odt_en = 0x84848484; + config.tpr11 = 0x9a9a9a9a; + config.tpr12 = 0x0e0f070a; + config.tpr14 = 0x48484848; + break; + default: + panic("This DRAM setup is currently not supported.\n"); + }; + + setbits_le32(0x03000160, BIT(8)); + clrbits_le32(0x03000168, 0x3f); + + mctl_auto_detect_rank_width(¶, &config); + mctl_auto_detect_dram_size(¶, &config); + + config.clk = CONFIG_DRAM_CLK; + config.odt_en = CONFIG_DRAM_SUNXI_ODT_EN; + config.tpr11 = CONFIG_DRAM_SUNXI_TPR11; + config.tpr12 = CONFIG_DRAM_SUNXI_TPR12; + config.tpr14 = CONFIG_DRAM_SUNXI_TPR14; + + mctl_core_init(¶, &config); + + size = mctl_calc_size(&config); + + sunxi_nsi_init(); + init_something(); + + return size; +}; diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 4dc1f29fc08..5de9fd5aab4 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -8,3 +8,5 @@ obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3) += h616_lpddr3.o obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4) += h616_lpddr4_2133.o obj-$(CONFIG_SUNXI_DRAM_A133_DDR4) += a133_ddr4.o obj-$(CONFIG_SUNXI_DRAM_A133_LPDDR4) += a133_lpddr4.o +obj-$(CONFIG_SUNXI_DRAM_A523_DDR3) += a523_ddr3.o +obj-$(CONFIG_SUNXI_DRAM_A523_LPDDR4) += a523_lpddr4.o diff --git a/arch/arm/mach-sunxi/dram_timings/a523_ddr3.c b/arch/arm/mach-sunxi/dram_timings/a523_ddr3.c new file mode 100644 index 00000000000..6e140bb1454 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/a523_ddr3.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sun55i A523 DDR3 timings, as programmed by Allwinner's boot0 on + * the X96QPro+ TV box. As usual very conservative timings, but probably + * the most compatible and reliable. + * + * (C) Copyright 2024 Mikhail Kalashnikov <iuncuim@gmail.com> + * Based on H616 DDR3 timings: + * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> + */ + +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> + +void mctl_set_timing_params(u32 clk) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + /* + * formulas and constraints as of + * JEDEC DDR3 specification, for + * DDR3-1600, per JESD79-3F + */ + u8 tccd = 2; /* 4nCK */ + u8 tfaw = ns_to_t(50, clk); + u8 trrd = max(ns_to_t(6, clk), 4); /* max(6 ns, 4nCK) */ + u8 twtr = max(ns_to_t(8, clk), 4); /* max(7.5 ns, 4nCK) */ + u8 trcd = ns_to_t(15, clk); /* 13.5 ns */ + u8 trc = ns_to_t(53, clk); + u8 txp = max(ns_to_t(8, clk), 2); /* max(6 ns, 3nCK) */ + u8 trtp = max(ns_to_t(8, clk), 4); /* max(7.5 ns, 4nCK) */ + u8 trp = ns_to_t(15, clk); /* >= 13.75 ns */ + u8 tras = ns_to_t(38, clk); + u16 trefi = ns_to_t(11350, clk) / 32; + u16 trfc = ns_to_t(360, clk); /* 160 ns for 2Gb */ + u16 txsr = 4; + + u8 tmrw = 0; + u8 tmrd = 4; /* 4nCK */ + + u8 tmod = max(ns_to_t(15, clk), 12); /* max(15 ns, 12nCK) */ + u8 tcke = max(ns_to_t(6, clk), 4); /* max(5.625 ns, 3nCK)*/ + u8 tcksrx = max(ns_to_t(10, clk), 4); /* max(10 ns, 5nCK) */ + u8 tcksre = max(ns_to_t(10, clk), 4); /* max(10 ns, 5nCK) */ + u8 trasmax = (clk / 2) / 15; /* tREFI * 9 */ + + /* + * TODO: support multiple DDR3 speed grades, these values below match + * the worst case for DDR3-2133, so should be good for all frequencies, + * but use the most conversative timings. + * DDR3-1866 (DRAM_CLK=912) should also work, or tcl=6 and tcwl=4 with + * DRAM_CLK=792. Maybe even the combination of both, depending on the + * particular device. + */ + u8 tcl = 7; /* CAS latency: 14 */ + u8 tcwl = 5; /* CAS write latency: 10 */ + u8 t_rdata_en = 9; + u8 tphy_wrlat = 5; + u8 twr = 7; + + u8 tckesr = tcke + 1; /* tCKE(min) + 1nCK */ + + u8 twtp = twr + 2 + tcwl; + u8 twr2rd = twtr + 2 + tcwl; /* (WL + BL / 2 + tWTR) / 2 */ + u8 trd2wr = tcl + 3 - tcwl; + u8 txs = ns_to_t(360, clk) / 32; /* max(5nCK,tRFC+10ns)*/ + u8 txsdll = 512 / 32; /* 512 nCK */ + u8 txsabort = 4; + u8 txsfast = 4; + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(0x00020208, &mctl_ctl->dramtmg[9]); + writel(0xe0c05, &mctl_ctl->dramtmg[10]); + writel(0x440c021c, &mctl_ctl->dramtmg[11]); + writel(8, &mctl_ctl->dramtmg[12]); + writel(0xa100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], 0xc0000fff, 0x156); + writel(0x01f20000, &mctl_ctl->init[1]); + writel(0x00001700, &mctl_ctl->init[2]); + writel(0, &mctl_ctl->dfimisc); + writel(0x1f140004, &mctl_ctl->init[3]); + writel(0x00200000, &mctl_ctl->init[4]); + writel(0, &mctl_ctl->init[6]); /* ? */ + writel(0, &mctl_ctl->init[7]); /* ? */ + + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* Configure DFI timing */ + writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + + /* set refresh timing */ + trfc = 0; /* as written so by boot0 */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} diff --git a/arch/arm/mach-sunxi/dram_timings/a523_lpddr4.c b/arch/arm/mach-sunxi/dram_timings/a523_lpddr4.c new file mode 100644 index 00000000000..940a4d04d57 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/a523_lpddr4.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * sun55i A523 LPDDR4-2133 timings, as programmed by Allwinner's boot0 + * + * (C) Copyright 2024 Jernej Skrabec <jernej.skrabec@gmail.com> + * (C) Copyright 2023 Mikhail Kalashnikov <iuncuim@gmail.com> + * + */ + +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h> + +void mctl_set_timing_params(u32 clk) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u8 tcl, tcwl, t_rdata_en, trtp, twr, tphy_wrlat; + unsigned int mr1, mr2; + + u8 tccd = 4; + u8 tfaw = ns_to_t(40, clk); + u8 trrd = max(ns_to_t(10, clk), 2); + u8 twtr = max(ns_to_t(10, clk), 4); + u8 trcd = max(ns_to_t(18, clk), 2); + u8 trc = ns_to_t(65, clk); + u8 txp = max(ns_to_t(8, clk), 2); + u8 trp = ns_to_t(21, clk); + u8 tras = ns_to_t(42, clk); + u16 trefi = ns_to_t(3904, clk) / 32; + u16 trfc = ns_to_t(280, clk); + u16 txsr = ns_to_t(290, clk); + + u8 tmrw = max(ns_to_t(14, clk), 5); + u8 tmod = 12; + u8 tcke = max(ns_to_t(15, clk), 2); + u8 tcksrx = max(ns_to_t(2, clk), 2); + u8 tcksre = max(ns_to_t(5, clk), 2); + u8 trasmax = (trefi * 9) / 32; + + if (clk <= 936) { + mr1 = 0x34; + mr2 = 0x1b; + tcl = 10; + tcwl = 5; + t_rdata_en = 17; + trtp = 4; + tphy_wrlat = 5; + twr = 10; + } else if (clk <= 1200) { + mr1 = 0x54; + mr2 = 0x2d; + tcl = 14; + tcwl = 7; + t_rdata_en = 25; + trtp = 6; + tphy_wrlat = 9; + twr = 15; + } else { + mr1 = 0x64; + mr2 = 0x36; + tcl = 16; + tcwl = 8; + t_rdata_en = 29; + trtp = 7; + tphy_wrlat = 11; + twr = 17; + } + + u8 tmrd = tmrw; + u8 tckesr = tcke; + u8 twtp = twr + 9 + tcwl; + u8 twr2rd = twtr + 9 + tcwl; + u8 trd2wr = ns_to_t(4, clk) + 7 - ns_to_t(1, clk) + tcl; + u8 txs = 4; + u8 txsdll = 16; + u8 txsabort = 4; + u8 txsfast = 4; + + /* set DRAM timing */ + writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, + &mctl_ctl->dramtmg[0]); + writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); + writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, + &mctl_ctl->dramtmg[2]); + writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); + writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, + &mctl_ctl->dramtmg[4]); + writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, + &mctl_ctl->dramtmg[5]); + /* Value suggested by ZynqMP manual and used by libdram */ + writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); + writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, + &mctl_ctl->dramtmg[8]); + writel(0x00020208, &mctl_ctl->dramtmg[9]); + writel(0xE0C05, &mctl_ctl->dramtmg[10]); + writel(0x440C021C, &mctl_ctl->dramtmg[11]); + writel(8, &mctl_ctl->dramtmg[12]); + writel(0xA100002, &mctl_ctl->dramtmg[13]); + writel(txsr, &mctl_ctl->dramtmg[14]); + + clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x558); + writel(0x01f20000, &mctl_ctl->init[1]); + writel(0x00001705, &mctl_ctl->init[2]); + writel(0, &mctl_ctl->dfimisc); + writel((mr1 << 16) | mr2, &mctl_ctl->init[3]); + writel(0x00330000, &mctl_ctl->init[4]); + writel(0x00040072, &mctl_ctl->init[6]); + writel(0x00260008, &mctl_ctl->init[7]); + + clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); + + /* Configure DFI timing */ + writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000, + &mctl_ctl->dfitmg0); + writel(0x100202, &mctl_ctl->dfitmg1); + + /* set refresh timing */ + writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); +} diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6ca0605466f..5aa134b6bcb 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -368,7 +368,7 @@ config USE_HOB config HAVE_FSP bool "Add an Firmware Support Package binary" - depends on !EFI + depends on !EFI_CLIENT select USE_HOB select HAS_ROM help @@ -517,7 +517,7 @@ config FSP_BROKEN_HOB config ENABLE_MRC_CACHE bool "Enable MRC cache" - depends on !EFI && !SYS_COREBOOT + depends on !EFI_CLIENT && !SYS_COREBOOT help Enable this feature to cause MRC data to be cached in NV storage to be used for speeding up boot time on future reboots and/or @@ -756,7 +756,7 @@ config HAVE_P2SB devices. menu "System tables" - depends on !EFI && !SYS_COREBOOT + depends on !EFI_CLIENT && !SYS_COREBOOT config GENERATE_PIRQ_TABLE bool "Generate a PIRQ table" diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index cc55c8fa39c..5150edb833f 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_SYS_SLIMBOOTLOADER) += slimbootloader/ -obj-$(CONFIG_EFI) += efi/ +obj-$(CONFIG_EFI_CLIENT) += efi/ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ diff --git a/arch/x86/cpu/efi/Kconfig b/arch/x86/cpu/efi/Kconfig index e0975d34d36..f5288013a8a 100644 --- a/arch/x86/cpu/efi/Kconfig +++ b/arch/x86/cpu/efi/Kconfig @@ -1,4 +1,4 @@ -if EFI +if EFI_CLIENT config SYS_CAR_ADDR hex diff --git a/arch/x86/cpu/x86_64/Makefile b/arch/x86/cpu/x86_64/Makefile index e929563b2c1..cb23c071aa3 100644 --- a/arch/x86/cpu/x86_64/Makefile +++ b/arch/x86/cpu/x86_64/Makefile @@ -5,6 +5,6 @@ obj-y += cpu.o interrupts.o setjmp.o -ifndef CONFIG_EFI +ifndef CONFIG_EFI_CLIENT obj-y += misc.o endif diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 01ba53cf68d..1bea5a60513 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -93,11 +93,6 @@ int board_early_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c index f9412071737..fc0057746e0 100644 --- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c +++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c @@ -13,8 +13,3 @@ int mmc_get_env_dev(void) return 1; return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 3ad77f51949..16d0e679c3e 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -77,11 +77,6 @@ static struct mm_region corstone1000_mem_map[] = { struct mm_region *mem_map = corstone1000_mem_map; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE; diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 75bc6b0631f..12bb6defab2 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -70,11 +70,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/atmel/sama7d65_curiosity/Kconfig b/board/atmel/sama7d65_curiosity/Kconfig new file mode 100644 index 00000000000..21ff432f2c1 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7D65_CURIOSITY + +config SYS_BOARD + default "sama7d65_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7d65_curiosity" + +endif diff --git a/board/atmel/sama7d65_curiosity/MAINTAINERS b/board/atmel/sama7d65_curiosity/MAINTAINERS new file mode 100644 index 00000000000..054af3c6541 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA7D65 CURIOSITY BOARD +M: Ryan Wanner <ryan.wanner@microchip.com> +S: Maintained +F: board/atmel/sama7d65_curiosity.c +F: include/configs/sama7d65_curiosity.h +F: configs/sama7d65_curiosity_mmc1_defconfig diff --git a/board/atmel/sama7d65_curiosity/Makefile b/board/atmel/sama7d65_curiosity/Makefile new file mode 100644 index 00000000000..56d011d1d81 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Author: Ryan Wanner <ryan.wanner@microchip.com> + +obj-y += sama7d65_curiosity.o diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c new file mode 100644 index 00000000000..713b1b9d959 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#include <debug_uart.h> +#include <init.h> +#include <fdtdec.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7d65.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 21, 0); /* LED BLUE */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 15, 1); /* LED GREEN */ +} + +int board_late_init(void) +{ + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_uart0_hw_init(void) +{ + /* FLEXCOM6 IO0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 18, 0); + /* FLEXCOM6 IO1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 19, 0); + + at91_periph_clk_enable(ATMEL_ID_FLEXCOM6); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + board_leds_init(); + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ b/board/beacon/imx8mm/imx8mm_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mn/imx8mn_beacon.c +++ b/board/beacon/imx8mn/imx8mn_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 99eb8972cf3..500fcc58ed8 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -45,11 +45,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 78635810585..9bc9ca30e95 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c index 9786f628f6d..26fa54e27bb 100644 --- a/board/beagle/beagley-ai/beagley-ai.c +++ b/board/beagle/beagley-ai/beagley-ai.c @@ -21,11 +21,6 @@ void set_dfu_alt_info(char *interface, char *devstr) } #endif -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index a6ced92565f..1ab6224011c 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -5,11 +5,6 @@ #include <fdtdec.h> -int board_init(void) -{ - return 0; -} - int dram_init(void) { if (fdtdec_setup_mem_size_base() != 0) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 45cc62936ce..47a01227a35 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -31,11 +31,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index e655f610c84..e7313d8c431 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -32,11 +32,6 @@ union reg_value_union { const phys_addr_t *address; }; -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c index c9989687399..c4a85c4aa44 100644 --- a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c +++ b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c @@ -6,11 +6,6 @@ #include <asm/arch/sys_proto.h> #include <env.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (is_usb_boot()) { diff --git a/board/canaan/k230_canmv/board.c b/board/canaan/k230_canmv/board.c index a705ee8f67b..7d012df214f 100644 --- a/board/canaan/k230_canmv/board.c +++ b/board/canaan/k230_canmv/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2025, Junhui Liu <junhui.liu@pigmoral.tech> */ -int board_init(void) -{ - return 0; -} diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index b1a805c1360..4c477ad551c 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -72,11 +72,6 @@ static struct mm_region thunderx_mem_map[] = { struct mm_region *mem_map = thunderx_mem_map; -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 339702e8392..e271d060efa 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index 138acd36ad2..d6f0a917023 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -46,11 +46,6 @@ enum env_location env_get_location(enum env_operation op, int prio) return prio ? ENVL_UNKNOWN : ENVL_MMC; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 4275436b128..3a890c5920c 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -153,11 +153,6 @@ void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip) } } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 }; diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c index 219efdddcb5..04b3bc8caf5 100644 --- a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c +++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c @@ -4,7 +4,3 @@ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 31f5a775137..38f0ec5f2fb 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -102,11 +102,6 @@ static struct mm_region qemu_arm64_mem_map[] = { struct mm_region *mem_map = qemu_arm64_mem_map; #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 40d295dbf06..58de4a05296 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -170,9 +170,9 @@ int misc_init_r(void) * Detect the presence of the platform bus node, and * create a virtual memory mapping for it. */ - for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); + for (uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); dev; - ret = uclass_find_next_device(&dev)) { + uclass_find_next_device(&dev)) { if (device_is_compatible(dev, "qemu,platform")) { struct simple_bus_plat *plat = dev_get_uclass_plat(dev); diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 70190ebe8fc..97c8211c100 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -28,11 +28,6 @@ int is_flash_available(void) } #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* start usb so that usb keyboard can be used as input device */ diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.c b/board/emulation/qemu-sbsa/qemu-sbsa.c index cf1d5acf5cb..30b3a41a9e9 100644 --- a/board/emulation/qemu-sbsa/qemu-sbsa.c +++ b/board/emulation/qemu-sbsa/qemu-sbsa.c @@ -93,11 +93,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - /** * dtb_dt_qemu - Return the address of the QEMU provided FDT. * diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c index 0ca83341c25..2e2a5a26d94 100644 --- a/board/emulation/qemu-xtensa/qemu-xtensa.c +++ b/board/emulation/qemu-xtensa/qemu-xtensa.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - unsigned long get_board_sys_clk(void) { return gd->cpu_clk ? gd->cpu_clk : 40000000; diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 56557d56429..82278a48ae8 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -34,12 +34,6 @@ int checkboard(void) return 0; } -/* board dependent setup after realloc */ -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 2a9ba7df2bb..732c0fa561d 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -28,12 +28,6 @@ struct efi_capsule_update_info update_info = { }; #endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c index 83bfca2f22d..cbd0a72bf4b 100644 --- a/board/freescale/imx91_evk/imx91_evk.c +++ b/board/freescale/imx91_evk/imx91_evk.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS index 34ba278fcdf..eb6e669bd17 100644 --- a/board/freescale/imx93_evk/MAINTAINERS +++ b/board/freescale/imx93_evk/MAINTAINERS @@ -1,4 +1,4 @@ -i.MX93 MEK BOARD +i.MX93 EVK BOARD M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/imx93_evk/ diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index d84d56be5e1..d62f94dc418 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -13,11 +13,8 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-imx9/imx93_pins.h> #include <asm/arch/clock.h> -#include <power/pmic.h> #include <dm/device.h> #include <dm/uclass.h> -#include <usb.h> -#include <dwc3-uboot.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/imx93_frdm/Kconfig b/board/freescale/imx93_frdm/Kconfig new file mode 100644 index 00000000000..5f5ac7f8f04 --- /dev/null +++ b/board/freescale/imx93_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX93_FRDM + +config SYS_BOARD + default "imx93_frdm" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_frdm" + +endif diff --git a/board/freescale/imx93_frdm/MAINTAINERS b/board/freescale/imx93_frdm/MAINTAINERS new file mode 100644 index 00000000000..59595bb2118 --- /dev/null +++ b/board/freescale/imx93_frdm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX93 FRDM BOARD +M: Fabio Estevam <festevam@gmail.com> +S: Maintained +F: board/freescale/imx93_frdm/ +F: include/configs/imx93_frdm.h +F: configs/imx93_frdm_defconfig diff --git a/board/freescale/imx93_frdm/Makefile b/board/freescale/imx93_frdm/Makefile new file mode 100644 index 00000000000..9612b1fa55b --- /dev/null +++ b/board/freescale/imx93_frdm/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_frdm.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +endif diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c new file mode 100644 index 00000000000..c74fd85712f --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <env.h> +#include <efi_loader.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <dm/device.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-FRDM-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "11X11_FRDM"); + env_set("board_rev", "iMX93"); + } + + return 0; +} diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env new file mode 100644 index 00000000000..528a953c8df --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.env @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=1 +mmcpart=1 +mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +boot_os=booti ${loadaddr} - ${fdt_addr_r} + +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + run mmcargs; + run loadimage; + run loadfdt; + run boot_os; + +scriptaddr=0x83500000 diff --git a/board/freescale/imx93_frdm/lpddr4_timing.h b/board/freescale/imx93_frdm/lpddr4_timing.h new file mode 100644 index 00000000000..192bc9e1519 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut <marex@denx.de> + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dram_timing_1GB; +extern struct dram_timing_info dram_timing_2GB; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c new file mode 100644 index 00000000000..17549206ee4 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A380E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 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{0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c new file mode 100644 index 00000000000..cd129e12959 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24AB321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2EE233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C760000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x015B015B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x015B2213}, + {0x4e300308, 0x0A3C0E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/spl.c b/board/freescale/imx93_frdm/spl.c new file mode 100644 index 00000000000..006c752d071 --- /dev/null +++ b/board/freescale/imx93_frdm/spl.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "lpddr4_timing.h" + +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> +#include <linux/delay.h> +#include <power/pca9450.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SRC_DDRC_SW_CTRL (0x44461020) +#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) + +static struct _drams { + u8 mr8; + struct dram_timing_info *pdram_timing; + char *name; +} frdm_drams[2] = { + {0x10, &dram_timing_1GB, "1GB DRAM" }, + {0x18, &dram_timing_2GB, "2GB DRAM" }, +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { + struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ret = ddr_init(ptiming); + if (ret == 0) { + if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { + printf("found DRAM %s matched\n", frdm_drams[i].name); + break; + } + + /* Power down and Power up DDR Mixer */ + + /* Clear PwrOkIn via DDRMIX register */ + setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + /* Power off the DDRMIX */ + setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + + udelay(50); + + /* Power up the DDRMIX */ + clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + } + } +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c index 388d99106db..503a8667245 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.c +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx95_evk/imx95_evk.c b/board/freescale/imx95_evk/imx95_evk.c index d5f5e310b6b..fe0111be508 100644 --- a/board/freescale/imx95_evk/imx95_evk.c +++ b/board/freescale/imx95_evk/imx95_evk.c @@ -15,11 +15,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 17095c34e92..a58ab93f27d 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: mx6memcal\n"); diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 29165266630..5e60ab9d7b7 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -372,11 +372,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MMC static int init_dwmmc(void) diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 41458813858..b68c10f85e4 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -29,14 +29,6 @@ config KM_PHRAM help Start address of the physical RAM, which is the mounted /var folder. -config KM_RESERVED_PRAM - hex "Reserved RAM" - default 0x0 if MPC83xx - default 0x1000 if MPC85xx || ARCH_LS1021A - depends on !ARCH_SOCFPGA - help - Reserved physical RAM area at the end of memory for special purposes. - config KM_CRAMFS_ADDR hex "CRAMFS Address" default 0x83000000 if ARCH_LS1021A diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 25897af2d8a..4bdaf90deff 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -53,7 +53,7 @@ int set_km_env(void) char *p; pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; + CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -61,12 +61,10 @@ int set_km_env(void) p = env_get("rootfssize"); if (p) strict_strtoul(p, 16, &rootfssize); - pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM) / 0x400; + pram = (rootfssize + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram); - varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); env_set("varaddr", envval); diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index c8299483299..f8f8d5edede 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -18,6 +18,11 @@ #define DIRECT_OFF 0x18 #define GPRT_OFF 0x1c +// used to keep track of the user settings for the input/output +static u32 gprt_user[2] = { 0x0, 0x0 }; +// convert the bank offset to the correct static user gprt +#define QRIO_USER_GRPT_BANK(bank) gprt_user[(bank - 0x40) / 0x20] + void show_qrio(void) { void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; @@ -72,12 +77,13 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) mask = 1U << gpio_nr; - gprt = in_be32(qrio_base + port_off + GPRT_OFF); + gprt = QRIO_USER_GRPT_BANK(port_off); if (value) gprt |= mask; else gprt &= ~mask; + QRIO_USER_GRPT_BANK(port_off) = gprt; out_be32(qrio_base + port_off + GPRT_OFF, gprt); } diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index ed5baf269a7..7d80cfbf64f 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -1,6 +1,6 @@ Hitachi Power Grids LS102XA BOARD -M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> -M: Rainer Boschung <rainer.boschung@hitachienergy.com> +M: Holger Brunck <holger.brunck@hitachienergy.com> +M: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com> S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: board/keymile/common/ diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env index 1054dbf9f54..c1c73b7da49 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=EXPU1 +netdev=eth2 diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 409a55ebda6..7db75f4df3e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -38,7 +38,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) { show_qrio(); - + i2c_deblock_gpio_cfg(); return 0; } @@ -96,8 +96,6 @@ int board_early_init_f(void) qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false); - i2c_deblock_gpio_cfg(); - /* enable the Unit LED (red) & Boot LED (on) */ qrio_set_leds(); diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env index 1232fe9da8b..bbfa8194a7e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=SELI8 +netdev=eth2 diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 8dcc2ea54f6..2e387038395 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -116,11 +116,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size); } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") || diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 0baf5c63f18..8a9502037fb 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -51,11 +51,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_eth_init(struct bd_info *bis) { return pci_eth_init(bis); diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 9d24c8cd412..405f393aade 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -10,8 +10,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7981/mt7981_rfb.c b/board/mediatek/mt7981/mt7981_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7981/mt7981_rfb.c +++ b/board/mediatek/mt7981/mt7981_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7986/mt7986_rfb.c b/board/mediatek/mt7986/mt7986_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c index fcb844deed8..c5cb33f06f7 100644 --- a/board/mediatek/mt7987/mt7987_rfb.c +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7988/mt7988_rfb.c b/board/mediatek/mt7988/mt7988_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c index 723a50fec00..41a6febf03d 100644 --- a/board/mediatek/mt8365_evk/mt8365_evk.c +++ b/board/mediatek/mt8365_evk/mt8365_evk.c @@ -6,11 +6,6 @@ #include <asm/armv8/mmu.h> -int board_init(void) -{ - return 0; -} - static struct mm_region mt8365_evk_mem_map[] = { { /* DDR */ diff --git a/board/mediatek/mt8516/mt8516_pumpkin.c b/board/mediatek/mt8516/mt8516_pumpkin.c index 930bfec3483..c383d194357 100644 --- a/board/mediatek/mt8516/mt8516_pumpkin.c +++ b/board/mediatek/mt8516/mt8516_pumpkin.c @@ -6,11 +6,6 @@ #include <dm.h> #include <net.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 699e5ca54a7..16dbaa96e8c 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -22,11 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_size_t get_effective_memsize(void) { /* Use bank0 only */ diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 2faa34954eb..0a3c052a019 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -14,11 +14,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c index 4c957e88992..62007f2f81d 100644 --- a/board/openpiton/riscv64/openpiton-riscv64.c +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -25,8 +25,3 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[i] = boot_devices[i]; } #endif - -int board_init(void) -{ - return 0; -} diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c index 14b8959c07a..3e1c4102cc1 100644 --- a/board/phytec/phycore_am62ax/phycore-am62ax.c +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -11,11 +11,6 @@ #include "../common/am6_som_detection.h" -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index b199fdaa59b..51da864aa80 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am62_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index f14c87f5c72..33c39376ceb 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am64_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index 402d967ab7d..b3f09154328 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -1,65 +1,15 @@ -#include <env/phytec/rauc.env> - -bootcmd= - mmc dev ${mmcdev}; - if mmc rescan; then - if test ${doraucboot} = 1; then - run raucinit; - fi; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; -console=ttymxc2,115200 +console=ttymxc2,CONFIG_BAUDRATE emmc_dev=2 -fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 ip_dyn=yes -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcargs= - setenv bootargs console=${console} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw -mmcautodetect=yes -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if run loadfdt; then - if test ${dofitboot} = 1; then - booti ${loadaddr} - ${fdt_addr_r} - else - echo WARN: Cannot load the DT; - fi; - fi; -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=2 -netargs= - setenv bootargs console=${console} root=/dev/nfs ip=dhcp - nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - run netargs; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; nfsroot=/srv/nfs -update_bootimg= - mmc dev ${mmcdev}; - if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then - setexpr fw_sz ${filesize} / 0x200; - mmc write ${loadaddr} ${update_offset} ${fw_sz}; - fi; -update_filename=flash.bin -update_offset=0x42 diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index a55795e0603..8d2caf8bbef 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -6,10 +6,7 @@ * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ -#include <asm/arch-imx9/ccm_regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch-imx9/imx93_pins.h> -#include <asm/arch/clock.h> #include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index a4d2aaac320..7b5d38d438f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -14,9 +14,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> #include <asm/sections.h> -#include <hang.h> #include <init.h> -#include <log.h> #include <power/pmic.h> #include <power/pca9450.h> #include <spl.h> @@ -25,11 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * Will be part of drivers/power/regulator/pca9450.c - * when pca9451a support is added. - */ -#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) #define EEPROM_ADDR 0x50 /* diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 01e210fcdd1..9fc63febdac 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -37,11 +37,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index fbbf6789b50..6824454cdf4 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -50,11 +50,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 0ea335e7486..3984ddc4594 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -32,11 +32,6 @@ int dram_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c index 78b8cb4ac34..6ea903f2d62 100644 --- a/board/renesas/r2dplus/r2dplus.c +++ b/board/renesas/r2dplus/r2dplus.c @@ -17,11 +17,6 @@ int checkboard(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 0f6d6e7f514..509c5dbb156 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -51,8 +51,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index 3bbd95201b5..a6c264d1248 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -4,9 +4,57 @@ * Author: Sam Protsenko <semen.protsenko@linaro.org> */ +#include <efi_loader.h> +#include <env.h> #include <init.h> +#include <mapmem.h> +#include <asm/io.h> #include "fw.h" +/* OTP Controller base address and register offsets */ +#define EXYNOS850_OTP_BASE 0x10000000 +#define OTP_CHIPID0 0x4 +#define OTP_CHIPID1 0x8 + +struct efi_fw_image fw_images[] = { + { + .image_type_id = E850_96_FWBL1_IMAGE_GUID, + .fw_name = u"E850-96-FWBL1", + .image_index = 1, + }, + { + .image_type_id = E850_96_EPBL_IMAGE_GUID, + .fw_name = u"E850-96-EPBL", + .image_index = 2, + }, + { + .image_type_id = E850_96_BL2_IMAGE_GUID, + .fw_name = u"E850-96-BL2", + .image_index = 3, + }, + { + .image_type_id = E850_96_BOOTLOADER_IMAGE_GUID, + .fw_name = u"E850-96-BOOTLOADER", + .image_index = 4, + }, + { + .image_type_id = E850_96_EL3_MON_IMAGE_GUID, + .fw_name = u"E850-96-EL3-MON", + .image_index = 5, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=" + "fwbl1.img raw 0x0 0x18 mmcpart 1;" + "epbl.img raw 0x18 0x98 mmcpart 1;" + "bl2.img raw 0xb0 0x200 mmcpart 1;" + "bootloader.img raw 0x438 0x1000 mmcpart 1;" + "el3_mon.img raw 0x1438 0x200 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -17,15 +65,39 @@ int dram_init_banksize(void) return fdtdec_setup_memory_banksize(); } -int board_init(void) +/* Read the unique SoC ID from OTP registers */ +static u64 get_chip_id(void) { - return 0; + void __iomem *otp_base; + u64 val; + + otp_base = map_sysmem(EXYNOS850_OTP_BASE, 12); + val = readl(otp_base + OTP_CHIPID0); + val |= (u64)readl(otp_base + OTP_CHIPID1) << 32UL; + unmap_sysmem(otp_base); + + return val; +} + +static void setup_serial(void) +{ + char serial_str[17] = { 0 }; + u64 serial_num; + + if (env_get("serial#")) + return; + + serial_num = get_chip_id(); + snprintf(serial_str, sizeof(serial_str), "%016llx", serial_num); + env_set("serial#", serial_str); } int board_late_init(void) { int err; + setup_serial(); + /* * Do this in board_late_init() to make sure MMC is not probed before * efi_init_early(). diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index 5ac76bcef02..aed7a71046d 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -7,5 +7,49 @@ pxefile_addr_r=0x8c200000 ramdisk_addr_r=0x8c300000 fdtfile=CONFIG_DEFAULT_FDT_FILE +dfu_alt_info= + rawemmc raw 0 0x747c000 mmcpart 1; + esp part 0 1; + rootfs part 0 2; + fwbl1 raw 0x0 0x18 mmcpart 1; + epbl raw 0x18 0x98 mmcpart 1; + bl2 raw 0xb0 0x200 mmcpart 1; + dram_train raw 0x2b0 0x20 mmcpart 1; + ect_test raw 0x2d0 0x64 mmcpart 1; + acpm_test raw 0x334 0x104 mmcpart 1; + bootloader raw 0x438 0x1000 mmcpart 1; + el3_mon raw 0x1438 0x200 mmcpart 1 + partitions=name=esp,start=512K,size=128M,bootable,type=system; partitions+=name=rootfs,size=-,bootable,type=linux + +partitions_android=name=esp,start=512K,size=128M,bootable,type=system; +partitions_android+=name=efs,size=20M,uuid=${uuid_gpt_efs}; +partitions_android+=name=env,size=16K,uuid=${uuid_gpt_env}; +partitions_android+=name=kernel,size=30M,uuid=${uuid_gpt_kernel}; +partitions_android+=name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk}; +partitions_android+=name=dtbo_a,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=dtbo_b,size=1M,uuid=${uuid_gpt_dtbo}; +partitions_android+=name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw}; +partitions_android+=name=keystorage,size=8K,uuid=${uuid_gpt_keystorage}; +partitions_android+=name=tzsw,size=1M,uuid=${uuid_gpt_tzsw}; +partitions_android+=name=harx,size=2M,uuid=${uuid_gpt_harx}; +partitions_android+=name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp}; +partitions_android+=name=logo,size=40M,uuid=${uuid_gpt_logo}; +partitions_android+=name=super,size=3600M,uuid=${uuid_gpt_super}; +partitions_android+=name=cache,size=300M,uuid=${uuid_gpt_cache}; +partitions_android+=name=modem,size=100M,uuid=${uuid_gpt_modem}; +partitions_android+=name=boot_a,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=boot_b,size=100M,uuid=${uuid_gpt_boot}; +partitions_android+=name=persist,size=30M,uuid=${uuid_gpt_persist}; +partitions_android+=name=recovery_a,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=recovery_b,size=40M,uuid=${uuid_gpt_recovery}; +partitions_android+=name=misc,size=40M,uuid=${uuid_gpt_misc}; +partitions_android+=name=mnv,size=20M,uuid=${uuid_gpt_mnv}; +partitions_android+=name=frp,size=512K,uuid=${uuid_gpt_frp}; +partitions_android+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta}; +partitions_android+=name=metadata,size=16M,uuid=${uuid_gpt_metadata}; +partitions_android+=name=dtb_a,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=dtb_b,size=1M,uuid=${uuid_gpt_dtb}; +partitions_android+=name=userdata,size=-,uuid=${uuid_gpt_userdata} diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 43f4edc39e9..0dc23a27dfc 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -104,11 +104,6 @@ int dram_init(void) return 0; } -int board_init(void) -{ - return 0; -} - int ft_board_setup(void *fdt, struct bd_info *bd) { /* Create an arbitrary reservation to allow testing OF_BOARD_SETUP.*/ diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index 3b4bd64dd00..9c8c7a6ecdc 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,6 +1,5 @@ CAPRICORN BOARD M: Alexander Sverdlin <alexander.sverdlin@siemens.com> -M: Anatolij Gustschin <agust@denx.de> M: Heiko Schocher <hs@denx.de> M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 161210c60a9..c75f4a0d084 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -367,11 +367,6 @@ static void m2_connector_setup(void) m2_overlay_prepare(); } -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct udevice *sysinfo; diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index 08077a1f9e1..f76e1ae75a1 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -43,8 +43,3 @@ int board_early_init_f(void) { return sram_init(); } - -int board_init(void) -{ - return 0; -} diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c index eaa47be1739..e6099d35dbf 100644 --- a/board/sophgo/licheerv_nano/board.c +++ b/board/sophgo/licheerv_nano/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c index 2631cdd49e0..ea416621544 100644 --- a/board/spacemit/bananapi-f3/board.c +++ b/board/spacemit/bananapi-f3/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index 8ad593cccdd..f5174720434 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -32,11 +32,6 @@ void enable_caches(void) } #endif -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_USB_DWC3 int g_dnl_board_usb_cable_connected(void) { diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 22d751b44d3..4b0defda1ec 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -45,11 +45,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index db59ebb838e..88c825334a8 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 134d207d95d..7aab7f71d0c 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c index be0884bdeb4..645685a64f1 100644 --- a/board/st/stm32h747-disco/stm32h747-disco.c +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -35,8 +35,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 75aa4d139fb..31c85c6816e 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -44,8 +44,3 @@ int board_late_init(void) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1b4b7d87163..e00b54f4535 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -137,6 +137,11 @@ M: Chris Morgan <macromorgan@hotmail.com> S: Maintained F: configs/anbernic_rg35xx_h700_defconfig +AVAOTA A1 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/avaota-a1_defconfig + BANANAPI M1 PLUS M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained @@ -531,6 +536,11 @@ M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained F: configs/parrot_r16_defconfig +RADXA CUBIE A5E BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/radxa-cubie-a5e_defconfig + SINLINX SINA31s BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -591,6 +601,11 @@ M: Andre Przywara <andre.przywara@arm.com> S: Maintained F: configs/x96_mate_defconfig +X96Q PRO+ TV BOX +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/x96q_pro_plus_defconfig + YONES TOPTECH BD1078 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 943b6221b8a..2929bc17f08 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -118,6 +118,10 @@ void i2c_init_board(void) clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI); +#elif CONFIG_MACH_SUN55I_A523 + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI); #else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); @@ -435,7 +439,8 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } -#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) +#elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \ + defined(CONFIG_MACH_SUN55I_A523) /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) { if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5)) diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS index 1e726e93603..6e7eee9c3e3 100644 --- a/board/terasic/de1-soc/MAINTAINERS +++ b/board/terasic/de1-soc/MAINTAINERS @@ -1,5 +1,5 @@ DE1-SoC BOARD -M: Anatolij Gustschin <agust@denx.de> +M: Anatolij Gustschin <ag.dev.uboot@gmail.com> S: Maintained F: board/terasic/de1-soc/ F: include/configs/socfpga_de1_soc.h diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 3351544c5b3..a445f983255 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -16,11 +16,6 @@ #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 379d1a5b316..2e85363cf5f 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 3051a0a27a1..d7b07a0d34d 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -74,11 +74,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 35fd30dbceb..8e89b3b15df 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -54,11 +54,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 6658794a137..5c45a33eac9 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -45,11 +45,6 @@ enum { DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index b1ed29af001..1527eaf1e16 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -66,11 +66,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 8c8f8e2a265..5d3b84607d8 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -28,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index f085ecfd37e..d2b94913c12 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -15,11 +15,6 @@ #include <asm/arch/k3-ddr.h> #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index c8d01bf0ca8..6335676081a 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index a89c5bf2c19..869656eee7a 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -183,6 +183,7 @@ const struct toradex_som toradex_modules[] = { { AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, { AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, { AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX8MMQ_WB_IT_64G, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index db612811c5c..d002b969bdf 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -141,6 +141,7 @@ enum { AQUILA_AM69O_16GB_IT, AQUILA_AM69O_8GB_WB_IT, AQUILA_AM69O_8GB_IT, /* 215 */ + VERDIN_IMX8MMQ_WB_IT_64G, }; enum { diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index bbe371516cc..915b413b15e 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -10,11 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index eca2cc8bc7f..069aa6c7909 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -22,11 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); @@ -95,7 +90,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 43d1c9312fe..7c631f380ff 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -55,11 +55,6 @@ static void read_hw_cfg(void) printf("0x%02x\n", hw_cfg); } -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); @@ -124,7 +119,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 066e8db678f..b4402415845 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -85,7 +85,8 @@ static void select_dt_from_module_version(void) is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G); } switch (get_pcb_revision()) { @@ -100,7 +101,7 @@ static void select_dt_from_module_version(void) break; } - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e57ec3b6896..34ce25512e8 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -90,7 +90,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 80c84e64241..14aa93c527b 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -44,11 +44,6 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -int board_init(void) -{ - return 0; -} - int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 216a022aa15..174752f6b07 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -33,11 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define GUEST_VIRTIO_MMIO_BASE 0x2000000 #define GUEST_VIRTIO_MMIO_SIZE 0x100000 -int board_init(void) -{ - return 0; -} - /* * Use fdt provided by Xen: according to * https://www.kernel.org/doc/Documentation/arm64/booting.txt diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index c478f7e04a0..ed3fe16af7b 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -7,11 +7,6 @@ #include <spl.h> -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_SPL u32 spl_boot_device(void) { diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c index 0c62b0013c4..c34a7c5ecae 100644 --- a/board/xilinx/zynqmp_r5/board.c +++ b/board/xilinx/zynqmp_r5/board.c @@ -7,11 +7,6 @@ #include <init.h> #include <linux/errno.h> -int board_init(void) -{ - return 0; -} - int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 3791ebfcb42..3f8dc2c3c4e 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -213,10 +213,12 @@ void bootdev_list(bool probe) device_active(dev) ? '+' : ' ', ret ? simple_itoa(-ret) : "OK", dev_get_uclass_name(dev_get_parent(dev)), dev->name); - if (probe) + if (probe) { ret = uclass_next_device_check(&dev); - else - ret = uclass_find_next_device(&dev); + } else { + uclass_find_next_device(&dev); + ret = 0; + } } printf("--- ------ ------ -------- ------------------\n"); printf("(%d bootdev%s)\n", i, i != 1 ? "s" : ""); diff --git a/boot/bootmeth_rauc.c b/boot/bootmeth_rauc.c index fc60e6e355d..cc6180221ed 100644 --- a/boot/bootmeth_rauc.c +++ b/boot/bootmeth_rauc.c @@ -79,18 +79,17 @@ static int distro_rauc_check(struct udevice *dev, struct bootflow_iter *iter) return 0; } -static int distro_rauc_scan_boot_part(struct bootflow *bflow) +static int distro_rauc_scan_parts(struct bootflow *bflow) { struct blk_desc *desc; struct distro_rauc_priv *priv; char *boot_order; const char **boot_order_list; - bool exists; int ret; int i; - int j; - desc = dev_get_uclass_plat(bflow->blk); + if (bflow->blk) + desc = dev_get_uclass_plat(bflow->blk); priv = bflow->bootmeth_priv; if (!priv || !priv->slots) @@ -99,20 +98,21 @@ static int distro_rauc_scan_boot_part(struct bootflow *bflow) boot_order = env_get("BOOT_ORDER"); boot_order_list = str_to_list(boot_order); for (i = 0; boot_order_list[i]; i++) { - exists = false; - for (j = 0; script_names[j]; j++) { - const struct distro_rauc_slot *slot; + const struct distro_rauc_slot *slot; - slot = get_slot(priv, boot_order_list[i]); - if (!slot) - return log_msg_ret("env", -ENOENT); + slot = get_slot(priv, boot_order_list[i]); + if (!slot) + return log_msg_ret("slot", -EINVAL); + if (desc) { ret = fs_set_blk_dev_with_part(desc, slot->boot_part); if (ret) - return log_msg_ret("blk", ret); - exists |= fs_exists(script_names[j]); + return log_msg_ret("part", ret); + fs_close(); + ret = fs_set_blk_dev_with_part(desc, slot->root_part); + if (ret) + return log_msg_ret("part", ret); + fs_close(); } - if (!exists) - return log_msg_ret("fs", -ENOENT); } str_free_list(boot_order_list); @@ -168,20 +168,24 @@ static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow (slot = strsep(&boot_order_copy, " ")); i++) { struct distro_rauc_slot *s; + struct distro_rauc_slot **new_slots; s = calloc(1, sizeof(struct distro_rauc_slot)); s->name = strdup(slot); s->boot_part = simple_strtoul(strsep(&parts, ","), NULL, 10); s->root_part = simple_strtoul(strsep(&parts, ","), NULL, 10); - priv->slots = realloc(priv->slots, (i + 1) * - sizeof(struct distro_rauc_slot)); + new_slots = realloc(priv->slots, (i + 1) * + sizeof(struct distro_rauc_slot)); + if (!new_slots) + return log_msg_ret("buf", -ENOMEM); + priv->slots = new_slots; priv->slots[i - 1] = s; - priv->slots[i]->name = NULL; + priv->slots[i] = NULL; } bflow->bootmeth_priv = priv; - ret = distro_rauc_scan_boot_part(bflow); + ret = distro_rauc_scan_parts(bflow); if (ret < 0) { for (i = 0; priv->slots[i]->name; i++) { free(priv->slots[i]->name); diff --git a/cmd/Makefile b/cmd/Makefile index e4ecf2e0493..12e948fd1b9 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -67,7 +67,7 @@ obj-$(CONFIG_CMD_EXTENSION) += extension_board.o obj-$(CONFIG_CMD_ECHO) += echo.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o obj-$(CONFIG_CMD_EEPROM) += eeprom.o -obj-$(CONFIG_EFI) += efi.o efi_common.o +obj-$(CONFIG_EFI_CLIENT) += efi.o efi_common.o obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o efi_common.o obj-$(CONFIG_CMD_EFICONFIG) += eficonfig.o ifdef CONFIG_CMD_EFICONFIG diff --git a/cmd/elf.c b/cmd/elf.c index 5e0ee30a7c8..53ec193aaa6 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -21,6 +21,8 @@ #include <linux/linkage.h> #endif +#define BOOTLINE_BUF_LEN 128 + /* Interpreter command to boot an arbitrary ELF image from memory */ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -114,7 +116,7 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) unsigned long bootaddr = 0; /* Address to put the bootline */ char *bootline; /* Text of the bootline */ char *tmp; /* Temporary char pointer */ - char build_buf[128]; /* Buffer for building the bootline */ + char build_buf[BOOTLINE_BUF_LEN]; /* Buffer for building the bootline */ int ptr = 0; #ifdef CONFIG_X86 ulong base; @@ -226,7 +228,7 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (!bootline) { tmp = env_get("bootdev"); if (tmp) { - strcpy(build_buf, tmp); + strlcpy(build_buf, tmp, BOOTLINE_BUF_LEN); ptr = strlen(tmp); } else { printf("## VxWorks boot device not specified\n"); diff --git a/cmd/fpga.c b/cmd/fpga.c index 9dc7b63db5d..d51c380d7b3 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -28,7 +28,7 @@ static long do_fpga_get_device(char *arg) if (dev == FPGA_INVALID_DEVICE && arg) dev = simple_strtol(arg, NULL, 16); - debug("%s: device = %ld\n", __func__, dev); + log_debug("device = %ld\n", dev); return dev; } @@ -40,26 +40,26 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, size_t local_data_size; long local_fpga_data; - debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs); + log_debug("%d, %d\n", argc, cmdtp->maxargs); if (argc != cmdtp->maxargs) { - debug("fpga: incorrect parameters passed\n"); - return CMD_RET_USAGE; + log_err("Incorrect number of parameters passed\n"); + return CMD_RET_FAILURE; } *dev = do_fpga_get_device(argv[0]); local_fpga_data = simple_strtol(argv[1], NULL, 16); if (!local_fpga_data) { - debug("fpga: zero fpga_data address\n"); - return CMD_RET_USAGE; + log_err("Zero fpga_data address\n"); + return CMD_RET_FAILURE; } *fpga_data = local_fpga_data; local_data_size = hextoul(argv[2], NULL); if (!local_data_size) { - debug("fpga: zero size\n"); - return CMD_RET_USAGE; + log_err("Zero size\n"); + return CMD_RET_FAILURE; } *data_size = local_data_size; @@ -70,51 +70,52 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + struct fpga_secure_info fpga_sec_info; + const int pos_userkey = 5; size_t data_size = 0; long fpga_data, dev; int ret; - struct fpga_secure_info fpga_sec_info; memset(&fpga_sec_info, 0, sizeof(fpga_sec_info)); - if (argc < 5) { - debug("fpga: incorrect parameters passed\n"); - return CMD_RET_USAGE; + if (argc < pos_userkey) { + log_err("Too few parameters passed\n"); + return CMD_RET_FAILURE; } - if (argc == 6) + if (argc == pos_userkey + 1) fpga_sec_info.userkey_addr = (u8 *)(uintptr_t) - simple_strtoull(argv[5], + simple_strtoull(argv[pos_userkey], NULL, 16); else /* * If 6th parameter is not passed then do_fpga_check_params * will get 5 instead of expected 6 which means that function - * return CMD_RET_USAGE. Increase number of params +1 to pass + * return CMD_RET_FAILURE. Increase number of params +1 to pass * this. */ argc++; + ret = do_fpga_check_params(&dev, &fpga_data, &data_size, + cmdtp, argc, argv); + if (ret) + return ret; + fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL); fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL); if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH && fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) { - debug("fpga: Use <fpga load> for NonSecure bitstream\n"); - return CMD_RET_USAGE; + log_err("Use <fpga load> for NonSecure bitstream\n"); + return CMD_RET_FAILURE; } if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY && !fpga_sec_info.userkey_addr) { - debug("fpga: User key not provided\n"); - return CMD_RET_USAGE; + log_err("User key not provided\n"); + return CMD_RET_FAILURE; } - ret = do_fpga_check_params(&dev, &fpga_data, &data_size, - cmdtp, argc, argv); - if (ret) - return ret; - return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info); } #endif @@ -245,23 +246,23 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, ulong dev = do_fpga_get_device(argv[0]); char *datastr = env_get("fpgadata"); - debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr); + log_debug("argc %x, dev %lx, datastr %s\n", argc, dev, datastr); if (dev == FPGA_INVALID_DEVICE) { - debug("fpga: Invalid fpga device\n"); - return CMD_RET_USAGE; + log_err("Invalid fpga device\n"); + return CMD_RET_FAILURE; } if (argc == 0 && !datastr) { - debug("fpga: No datastr passed\n"); - return CMD_RET_USAGE; + log_err("No datastr passed\n"); + return CMD_RET_FAILURE; } if (argc == 2) { datastr = argv[1]; - debug("fpga: Full command with two args\n"); + log_debug("Full command with two args\n"); } else if (argc == 1 && !datastr) { - debug("fpga: Dev is setup - fpgadata passed\n"); + log_debug("Dev is setup - fpgadata passed\n"); datastr = argv[0]; } @@ -269,20 +270,20 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, if (fit_parse_subimage(datastr, (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug("* fpga: subimage '%s' from FIT image ", - fit_uname); - debug("at 0x%08lx\n", fit_addr); + log_debug("* fpga: subimage '%s' from FIT image ", + fit_uname); + log_debug("at 0x%08lx\n", fit_addr); } else #endif { fpga_data = (void *)hextoul(datastr, NULL); - debug("* fpga: cmdline image address = 0x%08lx\n", - (ulong)fpga_data); + log_debug("* fpga: cmdline image address = 0x%08lx\n", + (ulong)fpga_data); } - debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); + log_debug("fpga_data = 0x%lx\n", (ulong)fpga_data); if (!fpga_data) { - puts("Zero fpga_data address\n"); - return CMD_RET_USAGE; + log_err("Zero fpga_data address\n"); + return CMD_RET_FAILURE; } switch (genimg_get_format(fpga_data)) { @@ -301,15 +302,15 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, data = image_get_load(hdr); - if (gunzip((void *)data, ~0UL, (void *)image_buf, + if (gunzip((void *)data, ~0U, (void *)image_buf, &image_size) != 0) { - puts("GUNZIP: error\n"); + log_err("Gunzip error\n"); return CMD_RET_FAILURE; } data_size = image_size; #else - puts("Gunzip image is not supported\n"); - return 1; + log_err("Gunzip image is not supported\n"); + return CMD_RET_FAILURE; #endif } else { data = (ulong)image_get_data(hdr); @@ -327,12 +328,12 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, const void *fit_data; if (!fit_uname) { - puts("No FIT subimage unit name\n"); + log_err("No FIT subimage unit name\n"); return CMD_RET_FAILURE; } if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - puts("Bad FIT image format\n"); + log_err("Bad FIT image format\n"); return CMD_RET_FAILURE; } @@ -348,7 +349,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, } #endif default: - puts("** Unknown image type\n"); + log_err("Unknown image type\n"); return CMD_RET_FAILURE; } } @@ -390,16 +391,16 @@ static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, fpga_cmd = find_cmd_tbl(argv[1], fpga_commands, ARRAY_SIZE(fpga_commands)); if (!fpga_cmd) { - debug("fpga: non existing command\n"); - return CMD_RET_USAGE; + log_err("Non existing command\n"); + return CMD_RET_FAILURE; } argc -= 2; argv += 2; if (argc > fpga_cmd->maxargs) { - debug("fpga: more parameters passed\n"); - return CMD_RET_USAGE; + log_err("Too many parameters passed\n"); + return CMD_RET_FAILURE; } ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv); diff --git a/cmd/gpt.c b/cmd/gpt.c index 27aea2df197..e18e5036a06 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -911,8 +911,9 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm, goto out; if (!strcmp(subcomm, "swap")) { - if ((strlen(name1) > PART_NAME_LEN) || (strlen(name2) > PART_NAME_LEN)) { - printf("Names longer than %d characters are truncated.\n", PART_NAME_LEN); + if ((strlen(name1) >= PART_NAME_LEN) || (strlen(name2) >= PART_NAME_LEN)) { + printf("Names longer than %d characters are truncated.\n", + PART_NAME_LEN - 1); ret = -EINVAL; goto out; } @@ -967,8 +968,9 @@ static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm, *first = *second; *second = tmp_part; } else { /* rename */ - if (strlen(name2) > PART_NAME_LEN) { - printf("Names longer than %d characters are truncated.\n", PART_NAME_LEN); + if (strlen(name2) >= PART_NAME_LEN) { + printf("Names longer than %d characters are truncated.\n", + PART_NAME_LEN - 1); ret = -EINVAL; goto out; } diff --git a/cmd/i2c.c b/cmd/i2c.c index 7246c4fa3e7..f0aae93073f 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -917,9 +917,9 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, #endif /* NOPROBES */ int ret; #if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *bus, *dev; + struct udevice *cur_bus, *dev; - if (i2c_get_cur_bus(&bus)) + if (i2c_get_cur_bus(&cur_bus)) return CMD_RET_FAILURE; #endif @@ -943,7 +943,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, continue; #endif #if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_probe(bus, j, 0, &dev); + ret = dm_i2c_probe(cur_bus, j, 0, &dev); #else ret = i2c_probe(j); #endif diff --git a/cmd/regulator.c b/cmd/regulator.c index da298090bb7..8d743c8d269 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -96,11 +96,11 @@ static int do_list(struct cmd_tbl *cmdtp, int flag, int argc, LIMIT_OFNAME, LIMIT_OFNAME, "regulator-name", "Parent"); - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret) - continue; + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) + return ret; + for (; dev; uclass_find_next_device(&dev)) { uc_pdata = dev_get_uclass_plat(dev); printf("| %-*.*s| %-*.*s| %s\n", LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name, diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c index d7c229e5441..3127660dd9e 100644 --- a/cmd/tlv_eeprom.c +++ b/cmd/tlv_eeprom.c @@ -41,7 +41,7 @@ static int set_date(char *buf, const char *string); static int set_bytes(char *buf, const char *string, int *converted_accum); static void show_tlv_devices(int current_dev); -/* The EERPOM contents after being read into memory */ +/* The EEPROM contents after being read into memory */ static u8 eeprom[TLV_INFO_MAX_LEN]; static struct udevice *tlv_devices[MAX_TLV_DEVICES]; @@ -430,7 +430,7 @@ int do_tlv_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) static int has_been_read; int ret; - // If no arguments, read the EERPOM and display its contents + // If no arguments, read the EEPROM and display its contents if (argc == 1) { if (!has_been_read) { ret = read_eeprom(current_dev, eeprom); @@ -560,7 +560,7 @@ U_BOOT_CMD(tlv_eeprom, 4, 1, do_tlv_eeprom, /** * tlvinfo_find_tlv * - * This function finds the TLV with the supplied code in the EERPOM. + * This function finds the TLV with the supplied code in the EEPROM. * An offset from the beginning of the EEPROM is returned in the * eeprom_index parameter if the TLV is found. */ @@ -631,7 +631,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval) char data[MAX_TLV_VALUE_LEN]; int eeprom_index; - // Encode each TLV type into the format to be stored in the EERPOM + // Encode each TLV type into the format to be stored in the EEPROM switch (tcode) { case TLV_CODE_PRODUCT_NAME: case TLV_CODE_PART_NUMBER: @@ -691,7 +691,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval) // Is there room for this TLV? if ((be16_to_cpu(eeprom_hdr->totallen) + ENT_SIZE + new_tlv_len) > TLV_TOTAL_LEN_MAX) { - printf("ERROR: There is not enough room in the EERPOM to save data.\n"); + printf("ERROR: There is not enough room in the EEPROM to save data.\n"); return false; } @@ -1033,10 +1033,8 @@ int mac_read_from_eeprom(void) struct tlvinfo_header *eeprom_hdr = to_header(eeprom); int devnum = 0; // TODO: support multiple EEPROMs - puts("EEPROM: "); - if (read_eeprom(devnum, eeprom)) { - printf("Read failed.\n"); + log_err("EEPROM: read failed\n"); return -1; } @@ -1082,8 +1080,8 @@ int mac_read_from_eeprom(void) } } - printf("%s v%u len=%u\n", eeprom_hdr->signature, eeprom_hdr->version, - be16_to_cpu(eeprom_hdr->totallen)); + log_debug("EEPROM: %s v%u len=%u\n", eeprom_hdr->signature, eeprom_hdr->version, + be16_to_cpu(eeprom_hdr->totallen)); return 0; } diff --git a/common/button_cmd.c b/common/button_cmd.c index 72dac1f9ef6..a6c437d7a34 100644 --- a/common/button_cmd.c +++ b/common/button_cmd.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2023 Linaro Ltd. - * Author: Caleb Connolly <caleb.connolly@linaro.org> + * Author: Casey Connolly <casey.connolly@linaro.org> */ #include <button.h> diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ac25fcea21d..ab05536bd02 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -80,7 +80,7 @@ config SPL_MAX_SIZE default 0x1b000 if AM33XX && !TI_SECURE_DEVICE default 0xec00 if OMAP34XX default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB - default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133 + default 0xbfa0 if MACH_SUN50I_H616 || MACH_SUN50I_A133 || MACH_SUN55I_A523 default 0x7000 if RCAR_GEN3 default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0 default 0x7fa0 if ARCH_SUNXI @@ -278,6 +278,7 @@ config SPL_TEXT_BASE default 0x00912000 if ARCH_MX7 default 0x40301350 if OMAP54XX default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I + default 0x44060 if MACH_SUN55I_A523 default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x00060 if ARCH_SUNXI default 0xfffc0000 if ARCH_ZYNQMP @@ -432,6 +433,7 @@ config SPL_STACK default 0x118000 if MACH_SUN50I_H6 default 0x52a00 if MACH_SUN50I_H616 default 0x40000 if MACH_SUN8I_R528 || MACH_SUN50I_A133 + default 0x44000 if MACH_SUN55I_A523 default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5 default 0x18000 if MACH_SUN9I default 0x8000 if ARCH_SUNXI diff --git a/common/spl/spl.c b/common/spl/spl.c index d8e26605d20..ed443c645a7 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -634,7 +634,7 @@ static int boot_from_devices(struct spl_image_info *spl_image, if (CONFIG_IS_ENABLED(SHOW_ERRORS)) ret = -ENXIO; for (loader = drv; loader != drv + n_ents; loader++) { - if (bootdev != loader->boot_device) + if (loader && bootdev != loader->boot_device) continue; if (!CONFIG_IS_ENABLED(SILENT_CONSOLE)) { if (loader) diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index b3565efb225..79d021f81dc 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -31,7 +31,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, ulong container_offset) { struct boot_img_t *images; - ulong offset, overhead, size; + ulong offset, size; void *buf, *trampoline; if (image_index > container->num_images) { @@ -54,7 +54,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, debug("%s: container: %p offset: %lu size: %lu\n", __func__, container, offset, size); - buf = map_sysmem(images[image_index].dst - overhead, images[image_index].size); + buf = map_sysmem(images[image_index].dst, images[image_index].size); if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) && arch_check_dst_in_secure(buf, size)) { trampoline = arch_get_container_trampoline(); diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 14860ab9bc4..3716973592e 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -27,10 +27,10 @@ CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_BOOTP_NTPSERVER=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 732a0c4e645..ae74b3ec092 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -27,10 +27,10 @@ CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_BOOTP_NTPSERVER=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y # CONFIG_CMD_LED is not set CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index e1dac88a46f..2b68902edef 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -20,7 +20,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 5fd3e96abb1..f81149e9435 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -22,7 +22,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 4f8fd5b740c..808fda1e50b 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -28,7 +28,6 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index b224f8635a4..6673038cb4c 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -18,7 +18,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0xb0b0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index fd8aa3dbfa8..00fe12f8f67 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -21,7 +21,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd" CONFIG_LOGLEVEL=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MAX_SIZE=0x9ab0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 52df6e0ca3f..64886986c42 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 21a381e8113..c9592d7b6c4 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 373b1d0ed64..04f360668b6 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -1,3 +1,4 @@ +# CONFIG_BOARD_INIT is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 099a4828a7f..ce503000e4c 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index ba6396c9dfc..18ffc991b25 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index fd2b28a1c6e..ae261f2fa01 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index fdf5d7803bb..491e0dd102e 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 438ec8a1c56..bf44c19befe 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTSTD_BOOTCOMMAND=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 7d3eb6f8c93..6733dcfdd85 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 63ba94ff90e..37b5c6a43e7 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 diff --git a/configs/am67a_beagley_ai_a53_defconfig b/configs/am67a_beagley_ai_a53_defconfig index 013529d26da..4693f3bc9b3 100644 --- a/configs/am67a_beagley_ai_a53_defconfig +++ b/configs/am67a_beagley_ai_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb; run set_led_state_fail_load" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig index b0a95da1086..00c6ba6e2b5 100644 --- a/configs/am67a_beagley_ai_r5_defconfig +++ b/configs/am67a_beagley_ai_r5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x6ce00 diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index da0d51a844b..b8754f912a4 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -32,7 +32,6 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_CMD_CPU=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 34c4e9a3f74..8572ad204d8 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -25,6 +25,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 diff --git a/configs/avaota-a1_defconfig b/configs/avaota-a1_defconfig new file mode 100644 index 00000000000..55457edd3b3 --- /dev/null +++ b/configs/avaota-a1_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun55i-t527-avaota-a1" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 +CONFIG_DRAM_SUNXI_DX_DRI=0x0d0d0d0d +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0x84848484 +CONFIG_DRAM_SUNXI_TPR0=0x80808080 +CONFIG_DRAM_SUNXI_TPR1=0x06060606 +CONFIG_DRAM_SUNXI_TPR6=0x38000000 +CONFIG_DRAM_SUNXI_TPR10=0x802f3333 +CONFIG_DRAM_SUNXI_TPR11=0xc7c5c4c2 +CONFIG_DRAM_SUNXI_TPR12=0x3533302f +CONFIG_MACH_SUN55I_A523=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_REGULATOR_AXP=y +CONFIG_AXP717_POWER=y +CONFIG_AXP_I2C_ADDRESS=0x35 +CONFIG_AXP_DCDC2_VOLT=920 +CONFIG_AXP_DCDC3_VOLT=1160 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig index a8b4cc675ab..a726ce84775 100644 --- a/configs/bananapi-f3_defconfig +++ b/configs/bananapi-f3_defconfig @@ -14,6 +14,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_ENV_OVERWRITE=y CONFIG_PINCTRL=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 040ef695fec..ca09351384d 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 1eafadf2535..185d6e24bd4 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index 566f9f2920f..1481e03f980 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM47622" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm94908_defconfig b/configs/bcm94908_defconfig index a19b112f86a..90eaacd8878 100644 --- a/configs/bcm94908_defconfig +++ b/configs/bcm94908_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM4908" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig index 46bbfb67980..859bb78c248 100644 --- a/configs/bcm94912_defconfig +++ b/configs/bcm94912_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM4912" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963138_defconfig b/configs/bcm963138_defconfig index aa582b79bc8..f59e4e245ea 100644 --- a/configs/bcm963138_defconfig +++ b/configs/bcm963138_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63138" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig index 239a8a10fa5..5deea27ee34 100644 --- a/configs/bcm963146_defconfig +++ b/configs/bcm963146_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63146" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963148_defconfig b/configs/bcm963148_defconfig index 48bc620e181..8b8a46c321c 100644 --- a/configs/bcm963148_defconfig +++ b/configs/bcm963148_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63148" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig index a6cfea6cd79..df78621c1e7 100644 --- a/configs/bcm963158_defconfig +++ b/configs/bcm963158_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63158" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig index 95c9c8e396e..2015b71f36e 100644 --- a/configs/bcm963178_defconfig +++ b/configs/bcm963178_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63178" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig index bfd309c25f5..0bd4ccb377a 100644 --- a/configs/bcm96756_defconfig +++ b/configs/bcm96756_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6756" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig index 7f165231648..a3909c67474 100644 --- a/configs/bcm96813_defconfig +++ b/configs/bcm96813_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6813" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig index 8bc6ac18be9..d26e4db2a96 100644 --- a/configs/bcm96846_defconfig +++ b/configs/bcm96846_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6846" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NAND=y diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig index 342be0a0e17..de113ef4746 100644 --- a/configs/bcm96855_defconfig +++ b/configs/bcm96855_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6855" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig index 5f22186966f..710440f9c79 100644 --- a/configs/bcm96856_defconfig +++ b/configs/bcm96856_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6856" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig index 682cb14e898..62e767fc830 100644 --- a/configs/bcm96858_defconfig +++ b/configs/bcm96858_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6858" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig index ad65187c30c..9689c6a9a15 100644 --- a/configs/bcm96878_defconfig +++ b/configs/bcm96878_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6878" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig index c53c6fffbc4..21e7c684a47 100644 --- a/configs/bcmns_defconfig +++ b/configs/bcmns_defconfig @@ -20,6 +20,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl" CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="northstar> " CONFIG_CMD_BOOTZ=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index d504f43462e..ee92019ac36 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -29,9 +29,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 855159430e1..03aa226f79a 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -30,9 +30,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 4b78d03fc86..edf7415da21 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -30,9 +30,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index 14eecb8fa5e..7c1be03a0c0 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -31,9 +31,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 0a79526ca10..0c63d3261ad 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -30,9 +30,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index aed2eff788c..369dfa7fefa 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -31,9 +31,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index 6b3e91d6d10..bfbf3c94e34 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -30,9 +30,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 8a7ebd6ef5a..28ae1978b00 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -31,9 +31,9 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_PCI=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_DOS_PARTITION is not set diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 58da63d11dd..1e1949b6fe6 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -37,7 +37,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index ebc885464a7..761de142935 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -37,7 +37,6 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_TYPES=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 2af491b065d..084e11a8ff0 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -33,7 +33,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 1677b671c6b..931e2eba902 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -21,7 +21,6 @@ CONFIG_BOOTDELAY=1 CONFIG_BOOTCOMMAND="run mmcboot; run nandboot; run netboot" CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 6880caf9208..d90bce3ebb6 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -33,7 +33,6 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Colibri iMX8X # " CONFIG_CMD_CPU=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 9a8fc7a4007..1364fe45291 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -28,7 +28,6 @@ CONFIG_SYS_PBSIZE=1056 CONFIG_LOGLEVEL=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_SYS_LONGHELP is not set diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 80163580f85..527a679b785 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_LOGLEVEL=7 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="corstone1000# " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index 31026c8dbbd..6bab5d3bc35 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -51,8 +51,8 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/durian_defconfig b/configs/durian_defconfig index 336c7a5269e..448332d4667 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="durian#" # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index f0e9ff7c447..b4066d87460 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_EXYNOS=y CONFIG_TEXT_BASE=0xf8800000 -CONFIG_SYS_MALLOC_LEN=0x81f000 +CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ARCH_EXYNOS9=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -15,15 +15,19 @@ CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_ENV_OFFSET_REDUND=0x10000 # CONFIG_PSCI_RESET is not set CONFIG_EFI_SET_TIME=y -CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ABOOTIMG=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_EFIDEBUG=y @@ -39,8 +43,18 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_NO_NET=y CONFIG_CLK_EXYNOS850=y +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x8a000000 +CONFIG_FASTBOOT_BUF_SIZE=0x30000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y +CONFIG_PHY=y +CONFIG_PHY_EXYNOS_USBDRD=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_SOC_SAMSUNG=y @@ -48,3 +62,11 @@ CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_USI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_SYSCON=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Samsung" +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0002 diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index 71d1bbd956e..a06f1ccfe2a 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -7,7 +7,7 @@ CONFIG_DEBUG_UART_CLOCK=0 CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_APP32=y CONFIG_DEBUG_UART=y -CONFIG_EFI=y +CONFIG_EFI_CLIENT=y CONFIG_FIT=y # CONFIG_BOOTSTD is not set CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index 9f7b53d0106..9bcf5162b50 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -8,7 +8,7 @@ CONFIG_X86_RUN_64BIT=y CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_APP64=y CONFIG_DEBUG_UART=y -CONFIG_EFI=y +CONFIG_EFI_CLIENT=y CONFIG_EFI_APP_64BIT=y CONFIG_FIT=y # CONFIG_BOOTSTD is not set diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index e9c5ddf12ad..ce9b7ff939d 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -5,7 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="efi-x86_payload" CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_PAYLOAD=y -CONFIG_EFI=y +CONFIG_EFI_CLIENT=y CONFIG_EFI_STUB=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index b82e10dc3a1..6ce00189886 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -5,7 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="efi-x86_payload" CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_PAYLOAD=y -CONFIG_EFI=y +CONFIG_EFI_CLIENT=y CONFIG_EFI_STUB=y CONFIG_EFI_STUB_64BIT=y CONFIG_FIT=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index b8cca3c74df..edf2aa7061c 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -54,11 +54,11 @@ CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 59c2101110e..476bfc3af10 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 65aca43e8b9..60a61086bb5 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -2,48 +2,41 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/raidsonic/ib62x0/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_IB62X0=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ib62x0" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" +CONFIG_LTO=y +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000" CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=1051 # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y CONFIG_CMD_IDE=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -58,6 +51,5 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_BZIP2=y diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig index 6673e1e6915..a4271ea071a 100644 --- a/configs/imx6dl_sielaff_defconfig +++ b/configs/imx6dl_sielaff_defconfig @@ -14,7 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6S=y CONFIG_TARGET_MX6S_SIELAFF=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-sielaff" CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SF_DEFAULT_BUS=1 @@ -61,6 +61,7 @@ CONFIG_CMD_UBI=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y @@ -114,5 +115,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x17ffffc0 CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 07390037c46..4634a0972f0 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -11,6 +11,7 @@ CONFIG_ARCH_IMX8M=y CONFIG_ARCH_MISC_INIT=y CONFIG_ARM=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index eb8e90a1251..13e7d1fca0a 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -44,7 +44,6 @@ CONFIG_SYS_PBSIZE=2081 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 7c8a2060b1a..7369c0a05ac 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -9,7 +9,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l" -CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y @@ -20,16 +19,15 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x47602000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" -CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_DEFAULT_FDT_FILE="imx8mm-phygate-tauri-l" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y @@ -44,7 +42,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -60,15 +57,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 06cc4bb7dde..7c520f6e4b5 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 5e60c9d3a08..0cefcadff6a 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index b71cdbb2e4e..c757a2180c0 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -40,6 +40,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index bb483653db2..ddaea0c68bd 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -40,6 +40,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index f163871bfaa..4a49355195a 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index c83f6a99a7e..dafef23650a 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -31,7 +31,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 58550c6c332..ee12de0deea 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -32,7 +32,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index f871bf1653d..a80ceab56f5 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -31,7 +31,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 127903045e5..47a30946818 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -37,7 +37,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 875ddcaaaa4..b9f3b9b8999 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -36,7 +36,7 @@ CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 CONFIG_BOARD_TYPES=y -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config index 226c58c0277..406529346c5 100644 --- a/configs/imx8mp_dhsom.config +++ b/configs/imx8mp_dhsom.config @@ -3,6 +3,7 @@ CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y # CONFIG_INPUT is not set CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset" CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 46039fd0c03..0ad1acb94b6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig index 552665d27ca..216831b0ede 100644 --- a/configs/imx8mp_navqp_defconfig +++ b/configs/imx8mp_navqp_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mp-navqp.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index b7a0b0533ba..9b10abfa488 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -46,7 +46,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 1e2fad98b7d..e230cb85d8b 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -46,7 +46,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mp-rsb3720-a1.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig index b92754074a0..809885c0873 100644 --- a/configs/imx91_11x11_evk_defconfig +++ b/configs/imx91_11x11_evk_defconfig @@ -35,7 +35,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig index 8a5222b6540..e7fa6b2f730 100644 --- a/configs/imx91_11x11_evk_inline_ecc_defconfig +++ b/configs/imx91_11x11_evk_inline_ecc_defconfig @@ -35,7 +35,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 99c349a9295..be250abb0b1 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig index 0966f166ec6..3cb9ee3daf3 100644 --- a/configs/imx93_9x9_qsb_inline_ecc_defconfig +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig new file mode 100644 index 00000000000..4f837ca9282 --- /dev/null +++ b/configs/imx93_frdm_defconfig @@ -0,0 +1,124 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-frdm" +CONFIG_TARGET_IMX93_FRDM=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_CPU=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SPAWN=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_ADC_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_DFU_MMC=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SHA384=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_UTHREAD=y diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index 814570ee2ae..73818a82627 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -38,8 +38,8 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index a88e697d9fa..077992b5fab 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -46,6 +46,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 3987bab5679..36274804881 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -39,6 +39,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index dca757fe057..d97d331fdbd 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 00ed3d91242..e7f708a60c5 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -37,6 +37,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index 99e96c90ef9..50a9d95d7bf 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 02e3ac343d9..42e1dd21d0b 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -36,6 +36,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 3a54a4c97d1..ceb2e273b54 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index ac584f50b94..8ea9decf15b 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -36,6 +36,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index f4c0862d0a8..aaf8fd32879 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 19f4a3b0e92..83ac99c922a 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index f4562bd0d68..8e2741c8d42 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x6ce00 diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 6b1306cf7af..67aa18a16da 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 9e4170028f4..cc340a2fe76 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 diff --git a/configs/k230_canmv_defconfig b/configs/k230_canmv_defconfig index 47fa1add2a9..a43412f0290 100644 --- a/configs/k230_canmv_defconfig +++ b/configs/k230_canmv_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k230-canmv" CONFIG_SYS_LOAD_ADDR=0xc000000 CONFIG_TARGET_K230_CANMV=y CONFIG_ARCH_RV64I=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="K230# " CONFIG_CMD_USB=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index e8635054e8c..c87a0cf3241 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 0557dd5a5b3..56447e9d065 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -18,7 +18,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm" CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 02a948c251f..bcec8191acf 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_mon_${boot} run_mon; run set_name_pmmc get_pmmc_${boot} run_pmmc; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index ca58125aa3f..fe66bfeb6c5 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm" CONFIG_SF_DEFAULT_BUS=1 CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index b3756c60efc..1855593832f 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 0025412b10f..e132bc750fb 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -18,7 +18,6 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm" CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index e90297cd2e9..ba10ab1d256 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run init_${boot}; run get_mon_${boot} run_mon; run get_kern_${boot}; run init_fw_rd_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 8864b60e845..0fc1c4c9fc9 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -17,7 +17,6 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm" CONFIG_TIMESTAMP=y -CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run run_mon_hs; run init_${boot}; run get_fit_${boot}; bootm ${addr_fit}#${name_fdt}" CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index cdf8e406483..4f08f2c572c 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -41,6 +41,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=276 CONFIG_BOARD_TYPES=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 6ddd21bd295..e97534ecc0a 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -47,6 +47,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTARGS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y # CONFIG_HWCONFIG is not set CONFIG_PCI_INIT_R=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 8fbe4c45fd6..f37c25a43b8 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -36,7 +36,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_SYS_DEVICE_NULLDEV is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index c497cdd92a2..9ccd35ac223 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -13,6 +13,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 @@ -45,7 +46,6 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index ff7ebbc8d9c..643814577ca 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_FSL_QIXIS=y @@ -54,7 +55,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index abc1f5ab726..bb9cf573cc2 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -14,6 +14,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 @@ -48,7 +49,6 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index e086f36d6ea..9353979a2e7 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -24,7 +24,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index ea5bb34cfbe..6b32150e408 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -38,7 +38,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 16968e1d3d8..4bea39a636f 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 5b3e65c310e..f897e41e444 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index e4adb8eeb1e..1d90a27c0ac 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -50,7 +50,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 651e59a0b5a..8fa9bb60238 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 48bfa53a167..881fe3dabae 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 9f26abb123a..5b28997dbaa 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -34,7 +34,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_HUSH_PARSER=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 10b69284d01..c1d5ee340e9 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -49,7 +49,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 30d6c54e4ce..9b96676bb69 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -48,7 +48,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index bc499a51630..e36d336d84b 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -28,7 +28,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_CMD_GREPENV=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 6bb5c1628d7..3a927c858b3 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -42,7 +42,6 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SPL_MAX_SIZE=0x1a000 diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 0cd6b7c7809..ffaecb5c90c 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 4e894badbc9..f666f477727 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index ddda1a1d896..f8c6d82887b 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -36,7 +36,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 3f0d277703d..8c7126b53f5 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -50,7 +50,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 897f9b6408d..6f249d7fb1f 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -51,7 +51,6 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_SILENT_CONSOLE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_ID_EEPROM=y CONFIG_SYS_EEPROM_BUS_NUM=1 diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index f3642594ff0..3d38f584150 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y @@ -68,7 +69,6 @@ CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 1537f8aab91..e3fcdd37a40 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -43,7 +43,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 1b41fe608da..2dcb99e9e20 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_OF_BOARD_FIXUP=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y @@ -55,7 +56,6 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index ca100bd4bca..0fb8061bf33 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -34,7 +34,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index ce501dd1404..6efe356e842 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -14,6 +14,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y @@ -49,7 +50,6 @@ CONFIG_SATA_CEVA=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x52 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index b32adab0bad..1282cb355d3 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -30,7 +30,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index b657248f918..941224b5ac2 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y @@ -68,7 +69,6 @@ CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_EARLY_INIT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 7b4d4ff92c7..191ab45aec0 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -43,7 +43,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)" # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 6b4e834ad4a..8a8a4e1c8d6 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -18,6 +18,7 @@ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y CONFIG_PCI=y CONFIG_AHCI=y CONFIG_NXP_ESBC=y +CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y @@ -55,7 +56,6 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -CONFIG_SYS_FSL_SEC_MON_BE=y CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index d0d612bd395..62c4a6a66ea 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -34,7 +34,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_MISC_INIT_R=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_DM=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 08a88e1f33d..7213c878830 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7622> " CONFIG_SYS_MAXARGS=8 CONFIG_CMD_BOOTMENU=y diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index dac7d341131..4f96cc50b40 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 80f7a7ff924..3b950a0db84 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index 47203ff4e64..0f56ca8a37c 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 696741d4264..9d7554c5da7 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7986> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index ef6a4822c18..153c1934bd0 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="BPI-R3> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index 3d971f5c313..ad9711da614 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="BPI-R3> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig index 022ca32169b..26be8ea4491 100644 --- a/configs/mt7987_emmc_rfb_defconfig +++ b/configs/mt7987_emmc_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index c6a88e7e9d3..ea43483d7ed 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig index ca7714b1242..70eb5afb999 100644 --- a/configs/mt7987_sd_rfb_defconfig +++ b/configs/mt7987_sd_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig index eebf7fb43ba..f492ad8da58 100644 --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7988> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig index 99469985c5c..a07362c84fc 100644 --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7988> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig index 6ec3aa834b1..9d8ea72370e 100644 --- a/configs/mt8365_evk_defconfig +++ b/configs/mt8365_evk_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_MT8365=y CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_IDENT_STRING=" mt8365-evk" CONFIG_DEFAULT_FDT_FILE="mt8365-evk" +# CONFIG_BOARD_INIT is not set CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_BAUDRATE=921600 diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 756d974278a..72ff8c79153 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -23,6 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index c467a7fbe1e..1da18f31344 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -18,7 +18,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loaduimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index f303322856f..8937afc9800 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -20,7 +20,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else echo ERR: Fail to boot from MMC; fi; fi; else exit; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 76dde53f2a5..e2fd47f45d5 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -21,7 +21,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 4011b8ef7ff..53e9804b0dd 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_PBSIZE=528 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 0422edeb53d..36c342bcfe2 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 36d1f96f25d..28961f5a13f 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig index caa2d316765..6378db863dd 100644 --- a/configs/n2350_defconfig +++ b/configs/n2350_defconfig @@ -52,8 +52,8 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig index ab9316340d8..284a74d08d8 100644 --- a/configs/nsa325_defconfig +++ b/configs/nsa325_defconfig @@ -39,8 +39,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y # CONFIG_CMD_BLOCK_CACHE is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig index 76adbf201e3..06fe9f78591 100644 --- a/configs/octeon_nic23_defconfig +++ b/configs/octeon_nic23_defconfig @@ -25,7 +25,6 @@ CONFIG_SYS_PBSIZE=276 CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_SYS_DEVICE_NULLDEV is not set CONFIG_CYCLIC=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 92592ad2195..1d29fe8ebc1 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -37,6 +37,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_CMD_MD5SUM=y @@ -60,12 +61,12 @@ CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_PXE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index f77d515706b..ef21eef74a3 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -37,6 +37,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_CMD_MD5SUM=y @@ -61,12 +62,12 @@ CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_PXE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index 19a52bc7eb5..011d51e6b00 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -61,12 +61,12 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_PXE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 498a8b994e1..69469265443 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -59,12 +59,12 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_PXE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index 97c44b1115b..f2c8b1d237c 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -23,6 +23,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig index 1e693c621eb..31b0dd58c17 100644 --- a/configs/openpiton_riscv64_defconfig +++ b/configs/openpiton_riscv64_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="openpiton$ " # CONFIG_CMD_CPU is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 13d956aea32..92f4c16ff76 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -29,6 +29,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index e9184549601..933e2e9df07 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -57,11 +57,11 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DHCP=y CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 9d54f7b2d32..0932c95642d 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -16,7 +16,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig index 020a2d49e60..9cc0710aaf5 100644 --- a/configs/pe2201_defconfig +++ b/configs/pe2201_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="pe2201#" CONFIG_CMD_BOOTMETH=y # CONFIG_CMD_LZMADEC is not set diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 2443af4c4d7..2f9faa888a2 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -23,7 +23,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index ebde47bba80..487131d5a7a 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -23,7 +23,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 96eacec1d23..4d6bce26f07 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" -CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000 +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 @@ -23,7 +23,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x47602000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 @@ -31,8 +31,9 @@ CONFIG_PCI=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_DEFAULT_FDT_FILE="imx8mm-phyboard-polis-rdk" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y @@ -48,7 +49,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -66,15 +66,9 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 975d061e7ba..6bd8bcf15da 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -41,7 +41,6 @@ CONFIG_FDT_FIXUP_PARTITIONS=y CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index bdd7e288aa4..05849d05be4 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -42,6 +42,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index 8ee6ed73adc..01d100842de 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 92a159e7466..fdbe79d3e32 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -1,5 +1,4 @@ CONFIG_ARM=y -CONFIG_ARM_SMCCC=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y @@ -46,6 +45,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 73517e04d0a..0368d4ef474 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 9f98b3522dc..62c9eec971d 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -41,6 +41,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 189d0706ce5..d1ac992dc7a 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 03b4fd9b2fc..1c0e0de8d4f 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y # CONFIG_CMD_BLOCK_CACHE is not set CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 365f6434f83..a87e918117c 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 CONFIG_CMD_FUSE=y diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig index f7070543260..87e8e2271ff 100644 --- a/configs/pomelo_defconfig +++ b/configs/pomelo_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="pomelo#" CONFIG_OF_CONTROL=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 05adbcbb9f3..45d9813950c 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index b9ba7a677d9..86d7de89e77 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -140,7 +140,6 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y -CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_UFS=y CONFIG_QCOM_UFS=y CONFIG_VIDEO=y diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig index 3819670defe..76e07cac7b6 100644 --- a/configs/qemu-arm-sbsa_defconfig +++ b/configs/qemu-arm-sbsa_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_QEMU_ARM_SBSA=y CONFIG_EFI_VARIABLE_NO_STORE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="bootflow scan" +# CONFIG_BOARD_INIT is not set CONFIG_EFI_PARTITION=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_EFI_MEDIA=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index cdffda26281..bf39a1da723 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 3d065b6a9fb..2a876aefecd 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 15f1a5d973d..36f8b457586 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index bf9a0b07400..a9ff831be91 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 6cc42817970..8384fe78a31 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -15,6 +15,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 1c7cef056c4..34e14b8f8df 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 39afb837e41..358bb1aeeb9 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -25,6 +25,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_BLOBLIST=y CONFIG_CMD_SMBIOS=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 92ba48f6af9..d5890bf87fb 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -27,6 +27,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig new file mode 100644 index 00000000000..88019acf576 --- /dev/null +++ b/configs/radxa-cubie-a5e_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun55i-a527-cubie-a5e" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 +CONFIG_DRAM_SUNXI_DX_DRI=0x0d0d0d0d +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0x84848484 +CONFIG_DRAM_SUNXI_TPR0=0x80808080 +CONFIG_DRAM_SUNXI_TPR1=0x06060606 +CONFIG_DRAM_SUNXI_TPR6=0x38000000 +CONFIG_DRAM_SUNXI_TPR10=0x802f3333 +CONFIG_DRAM_SUNXI_TPR11=0xc7c5c4c2 +CONFIG_DRAM_SUNXI_TPR12=0x3533302f +CONFIG_MACH_SUN55I_A523=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_REGULATOR_AXP=y +CONFIG_AXP717_POWER=y +CONFIG_AXP_DCDC2_VOLT=920 +CONFIG_AXP_DCDC3_VOLT=1100 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index e7c0a7e1eae..c2bdc521018 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -19,6 +19,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CLK=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 6084336fc21..9e15fa00768 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -35,7 +35,6 @@ CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig index 1cd530260cd..65a9c25b4aa 100644 --- a/configs/rzn1_snarc_defconfig +++ b/configs/rzn1_snarc_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x8fffffff # CONFIG_EFI_LOADER is not set -# CONFIG_ARCH_MISC_INIT is not set # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/sama7d65_curiosity_mmc1_defconfig b/configs/sama7d65_curiosity_mmc1_defconfig new file mode 100644 index 00000000000..e819e51b458 --- /dev/null +++ b/configs/sama7d65_curiosity_mmc1_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x66f00000 +CONFIG_SYS_MALLOC_F_LEN=0x11000 +CONFIG_TARGET_SAMA7D65_CURIOSITY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60014ef0 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x70000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="microchip/at91-sama7d65_curiosity" +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xe2020200 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x62000000 +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7d65_curiosity.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_CMD_IMI=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_WGET=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DNS=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_DM_MTD=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=n +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=133000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPI_FLASH_SOFT_RESET=n +CONFIG_SPI_FLASH_MACRONIX=n +CONFIG_SPI_FLASH_MX66LM1G45G=n +CONFIG_SPI_FLASH_SST=n +CONFIG_SPI_FLASH_MTD=n +CONFIG_DM_ETH=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH_PHY=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_RESET=y +CONFIG_RESET_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=n +# CONFIG_ATMEL_SPI is not set +CONFIG_TIMER=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_RESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 374dcb1d5ba..169d0a2adef 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -27,6 +27,7 @@ CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000 CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_ANDROID_AB=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y @@ -72,11 +73,11 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_ETHSW=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 2eba02e1f07..6d2aec3a43e 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -49,6 +49,7 @@ CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=6 CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_STACKPROTECTOR=y CONFIG_ANDROID_AB=y CONFIG_CMD_CPU=y @@ -77,6 +78,11 @@ CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO_READ=y CONFIG_CMD_PWM=y @@ -110,11 +116,11 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_ETHSW=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_2048=y CONFIG_CMD_BMP=y CONFIG_CMD_BOOTCOUNT=y @@ -197,6 +203,20 @@ CONFIG_SANDBOX_DMA=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_STRATIX_II=y +CONFIG_FPGA_STRATIX_V=y +CONFIG_FPGA_ACEX1K=y +CONFIG_FPGA_CYCLON2=y +CONFIG_FPGA_LATTICE=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN2=y +CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_VIRTEX2=y +CONFIG_SYS_FPGA_CHECK_BUSY=y +CONFIG_SYS_FPGA_CHECK_CTRLC=y +CONFIG_DM_FPGA=y +CONFIG_SANDBOX_FPGA=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_QCOM_PMIC_GPIO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index e81941fb14f..c8ff95f6159 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -26,6 +26,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y @@ -61,10 +62,10 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_IPV6_ROUTER_DISCOVERY=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index a0702d6f6e1..253faaf0ba4 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y @@ -97,9 +98,9 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index f1c48c84b62..3d2fa732f41 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -28,6 +28,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y @@ -75,9 +76,9 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 9d75bb5f933..e248966b954 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BLOBLIST_SIZE=0x5000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y @@ -88,9 +89,9 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y CONFIG_CMD_RARP=y CONFIG_CMD_CDP=y -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig index 14fefa968c6..fc7f82e878a 100644 --- a/configs/sipeed_licheerv_nano_defconfig +++ b/configs/sipeed_licheerv_nano_defconfig @@ -18,6 +18,7 @@ CONFIG_SD_BOOT=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="licheerv_nano# " # CONFIG_CMD_BOOTDEV is not set CONFIG_CMD_MBR=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index b2e21c7d7ae..9fcdfb4a8fe 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index d838b252d53..11d78688780 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -17,6 +17,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index d17b86b344d..4333913d61e 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -56,10 +56,10 @@ CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_SNTP=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_MTDPARTS=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index c0992f397f6..8282271d0ed 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m" CONFIG_SYS_PBSIZE=1058 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="stih410-b2260 => " CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index bca3d871f5c..492d5554c0e 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -26,9 +26,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 137c91e6a8e..432d35d0d5a 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -43,9 +43,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 36e57edbb4d..45dc8bb0cee 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglev CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index a2ce8c80e20..02fc2dc521a 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 7a1fe576cc3..f0aab073bae 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CYCLIC_MAX_CPU_TIME_US=50000 +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 00245dcb750..1e39569c055 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -26,9 +26,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index b849d8f3266..699ae9d08fc 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -43,9 +43,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index af0a7dacbe2..8cda9e3dff8 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -27,9 +27,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 61bbca3ec10..74210fe8252 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -44,9 +44,9 @@ CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_SNTP=y CONFIG_CMD_LINK_LOCAL=y CONFIG_CMD_DNS=y +CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 38312e9a5f1..5818e68ff7e 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index fcbf7177690..3ee8d082da8 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h747-disco_defconfig b/configs/stm32h747-disco_defconfig index 5bb87eee510..bea1fa5a809 100644 --- a/configs/stm32h747-disco_defconfig +++ b/configs/stm32h747-disco_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h747i-disco" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index 8a7c45f74a4..971d5c00d88 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index cfbe5a4ae91..2e86abac801 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index f6ca1700a5f..b800b4c4073 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 16524245ce1..870e17e451a 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 3348b3f0546..88ee89aa13a 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 7dd75bfe365..7fe0d87a3e2 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="ThunderX_88XX> " diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index c90dfe517d6..42ec5957510 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_BOOTI=n CONFIG_CMD_ELF=n CONFIG_CMD_EXTENSION=n CONFIG_CMD_DATE=n +CONFIG_BOARD_INIT=n CONFIG_OF_CONTROL=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 0489f444115..f8a984f1e6b 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -46,7 +46,7 @@ CONFIG_SYS_PBSIZE=2081 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index cce58d31994..74dcc455f7a 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BLOBLIST=y CONFIG_BLOBLIST_PASSAGE_MANDATORY=y CONFIG_SYS_PROMPT="TOTAL_COMPUTE# " diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index e36b55faec1..2c0573cd54e 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -41,6 +41,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}- CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y @@ -170,7 +171,6 @@ CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y -CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -178,8 +178,6 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -CONFIG_TEE=y -CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 5cc7d050c33..efba857ad70 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig index 7e6132cde53..c46b883a9c6 100644 --- a/configs/verdin-am62p_a53_defconfig +++ b/configs/verdin-am62p_a53_defconfig @@ -42,6 +42,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am62p5-verdin-${variant} CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x80000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y @@ -169,7 +170,6 @@ CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_RESET_TI_SCI=y -CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -177,8 +177,6 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y -CONFIG_TEE=y -CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y diff --git a/configs/verdin-am62p_r5_defconfig b/configs/verdin-am62p_r5_defconfig index 42361523ab3..a8b0e942b61 100644 --- a/configs/verdin-am62p_r5_defconfig +++ b/configs/verdin-am62p_r5_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index ea085acd28f..d33fd8614b5 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -39,7 +39,6 @@ CONFIG_SYS_PBSIZE=2081 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 065520071d1..e50bd5865ca 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -48,7 +48,6 @@ CONFIG_SYS_PBSIZE=2081 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 diff --git a/configs/x96q_pro_plus_defconfig b/configs/x96q_pro_plus_defconfig new file mode 100644 index 00000000000..07d3b078bef --- /dev/null +++ b/configs/x96q_pro_plus_defconfig @@ -0,0 +1,32 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun55i-h728-x96qpro+" +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x07070707 +CONFIG_DRAM_SUNXI_DX_DRI=0x0c0c0c0c +CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e +CONFIG_DRAM_SUNXI_ODT_EN=0x90909090 +CONFIG_DRAM_SUNXI_TPR0=0x80808080 +CONFIG_DRAM_SUNXI_TPR1=0x06060606 +CONFIG_DRAM_SUNXI_TPR6=0x3380807e +CONFIG_DRAM_SUNXI_TPR10=0x802f7788 +CONFIG_DRAM_SUNXI_TPR11=0x8f919190 +CONFIG_DRAM_SUNXI_TPR12=0x22222723 +CONFIG_MACH_SUN55I_A523=y +CONFIG_SUNXI_DRAM_A523_DDR3=y +CONFIG_DRAM_CLK=792 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_REGULATOR_AXP=y +CONFIG_AXP717_POWER=y +CONFIG_AXP_DCDC2_VOLT=920 +CONFIG_AXP_DCDC3_VOLT=1360 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index e9a5219a7c4..161fa1a6eff 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -12,6 +12,7 @@ CONFIG_IDENT_STRING=" xenguest" CONFIG_BOOTDELAY=10 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1051 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="xenguest# " # CONFIG_CMD_BDI is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xenguest_arm64_virtio_defconfig b/configs/xenguest_arm64_virtio_defconfig index acf131fc837..ebd2c9b483a 100644 --- a/configs/xenguest_arm64_virtio_defconfig +++ b/configs/xenguest_arm64_virtio_defconfig @@ -14,6 +14,7 @@ CONFIG_PCI=y CONFIG_BOOTDELAY=10 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1051 +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_SYS_PROMPT="xenguest# " # CONFIG_CMD_BDI is not set diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 7dde2fc0a8f..92f7aa04ec0 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index b96b02c6125..b61ec90d096 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index 77fcf4d6865..c4d458370b6 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index e53c0771baf..2d7227c9e33 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index f164580c501..41444271f0d 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 8a8a9b0b463..369d480fd1f 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 3fc4f2f9b86..2b415b8f727 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index cfcb4321b1f..c7271899bdf 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 9af0b717ba9..bb9cd882340 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index d4ec2b59b71..81ea0e175ff 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTSTAGE=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="ZynqMP r5> " CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_SETEXPR is not set diff --git a/doc/README.pxe b/doc/README.pxe deleted file mode 100644 index ba189080e8c..00000000000 --- a/doc/README.pxe +++ /dev/null @@ -1,292 +0,0 @@ -SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Calxeda, Inc. - */ - -The 'pxe' commands provide a near subset of the functionality provided by -the PXELINUX boot loader. This allows U-Boot based systems to be controlled -remotely using the same PXE based techniques that many non U-Boot based servers -use. - -Commands -======== - -pxe get -------- - syntax: pxe get - - follows PXELINUX's rules for retrieving configuration files from a tftp - server, and supports a subset of PXELINUX's config file syntax. - - Environment - ----------- - 'pxe get' requires two environment variables to be set: - - pxefile_addr_r - should be set to a location in RAM large enough to hold - pxe files while they're being processed. Up to 16 config files may be - held in memory at once. The exact number and size of the files varies with - how the system is being used. A typical config file is a few hundred bytes - long. - - bootfile,serverip - these two are typically set in the DHCP response - handler, and correspond to fields in the DHCP response. - - 'pxe get' optionally supports these two environment variables being set: - - ethaddr - this is the standard MAC address for the ethernet adapter in use. - 'pxe get' uses it to look for a configuration file specific to a system's - MAC address. - - pxeuuid - this is a UUID in standard form using lower case hexadecimal - digits, for example, 550e8400-e29b-41d4-a716-446655440000. 'pxe get' uses - it to look for a configuration file based on the system's UUID. - - File Paths - ---------- - 'pxe get' repeatedly tries to download config files until it either - successfully downloads one or runs out of paths to try. The order and - contents of paths it tries mirrors exactly that of PXELINUX - you can - read in more detail about it at: - - http://syslinux.zytor.com/wiki/index.php/Doc/pxelinux - -pxe boot --------- - syntax: pxe boot [pxefile_addr_r] - - Interprets a pxe file stored in memory. - - pxefile_addr_r is an optional argument giving the location of the pxe file. - The file must be terminated with a NUL byte. - - Environment - ----------- - There are some environment variables that may need to be set, depending - on conditions. - - pxefile_addr_r - if the optional argument pxefile_addr_r is not supplied, - an environment variable named pxefile_addr_r must be supplied. This is - typically the same value as is used for the 'pxe get' command. - - bootfile - typically set in the DHCP response handler based on the - same field in the DHCP respone, this path is used to generate the base - directory that all other paths to files retrieved by 'pxe boot' will use. - If no bootfile is specified, paths used in pxe files will be used as is. - - serverip - typically set in the DHCP response handler, this is the IP - address of the tftp server from which other files will be retrieved. - - kernel_addr_r, initrd_addr_r - locations in RAM at which 'pxe boot' will - store the kernel(or FIT image) and initrd it retrieves from tftp. These - locations will be passed to the bootm command to boot the kernel. These - environment variables are required to be set. - - fdt_addr_r - location in RAM at which 'pxe boot' will store the fdt blob it - retrieves from tftp. The retrieval is possible if 'fdt' label is defined in - pxe file and 'fdt_addr_r' is set. If retrieval is possible, 'fdt_addr_r' - will be passed to bootm command to boot the kernel. - - fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm - command if it is set and 'fdt_addr_r' is not passed to bootm command. - - fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store - fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'. - - pxe_label_override - override label to be used, if exists, instead of the - default label. This will allow consumers to choose a pxe label at - runtime instead of having to prompt the user. If "pxe_label_override" is set - but does not exist in the pxe menu, pxe would fallback to the default label if - given, and no failure is returned but rather a warning message. - -pxe file format -=============== -The pxe file format is nearly a subset of the PXELINUX file format; see -http://syslinux.zytor.com/wiki/index.php/PXELINUX. It's composed of one line -commands - global commands, and commands specific to labels. Lines begining -with # are treated as comments. White space between and at the beginning of -lines is ignored. - -The size of pxe files and the number of labels is only limited by the amount -of RAM available to U-Boot. Memory for labels is dynamically allocated as -they're parsed, and memory for pxe files is statically allocated, and its -location is given by the pxefile_addr_r environment variable. The pxe code is -not aware of the size of the pxefile memory and will outgrow it if pxe files -are too large. - -Supported global commands -------------------------- -Unrecognized commands are ignored. - -default <label> - the label named here is treated as the default and is - the first label 'pxe boot' attempts to boot. - -fallback <label> - the label named here is treated as a fallback option that - may be attempted should it be detected that booting of - the default has failed to complete, for example via - U-Boot's boot count limit functionality. - -menu title <string> - sets a title for the menu of labels being displayed. - -menu include <path> - use tftp to retrieve the pxe file at <path>, which - is then immediately parsed as if the start of its - contents were the next line in the current file. nesting - of include up to 16 files deep is supported. - -prompt <flag> - if 1, always prompt the user to enter a label to boot - from. if 0, only prompt the user if timeout expires. - -timeout <num> - wait for user input for <num>/10 seconds before - auto-booting a node. - -label <name> - begin a label definition. labels continue until - a command not recognized as a label command is seen, - or EOF is reached. - -Supported label commands ------------------------- -labels end when a command not recognized as a label command is reached, or EOF. - -menu default - set this label as the default label to boot; this is - the same behavior as the global default command but - specified in a different way - -kernel <path> - if this label is chosen, use tftp to retrieve the kernel - (or FIT image) at <path>. it will be stored at the address - indicated in the kernel_addr_r environment variable, and - that address will be passed to bootm to boot this kernel. - For FIT image, The configuration specification can be - appended to the file name, with the format: - <path>#<conf>[#<extra-conf[#...]] - It will passed to bootm with that address. - (see: doc/uImage.FIT/command_syntax_extensions.txt) - It useful for overlay selection in pxe file - (see: doc/usage/fit/overlay-fdt-boot.rst). - -fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT - overlay(s) at <path>. it will be temporarily stored at the - address indicated in the fdtoverlay_addr_r environment variable, - and then applied in the load order to the fdt blob stored at the - address indicated in the fdt_addr_r environment variable. - -devicetree-overlay <path> [...] - if this label is chosen, use tftp to retrieve the DT - overlay(s) at <path>. it will be temporarily stored at the - address indicated in the fdtoverlay_addr_r environment variable, - and then applied in the load order to the fdt blob stored at the - address indicated in the fdt_addr_r environment variable. - Alias for fdtoverlays. - -kaslrseed - set this label to request random number from hwrng as kaslr seed. - -append <string> - use <string> as the kernel command line when booting this - label. Environment variable references like ${var} are - substituted before boot. - -initrd <path> - if this label is chosen, use tftp to retrieve the initrd - at <path>. it will be stored at the address indicated in - the initrd_addr_r environment variable, and that address - will be passed to bootm. - For FIT image, the initrd can be provided with the same value than - kernel, including configuration: - <path>#<conf>[#<extra-conf[#...]] - In this case, kernel_addr_r is passed to bootm. - -fdt <path> - if this label is chosen, use tftp to retrieve the fdt blob - at <path>. it will be stored at the address indicated in - the fdt_addr_r environment variable, and that address will - be passed to bootm. - For FIT image, the device tree can be provided with the same value - than kernel, including configuration: - <path>#<conf>[#<extra-conf[#...]] - In this case, kernel_addr_r is passed to bootm. - -devicetree <path> - if this label is chosen, use tftp to retrieve the fdt blob - at <path>. it will be stored at the address indicated in - the fdt_addr_r environment variable, and that address will - be passed to bootm. Alias for fdt. - -fdtdir <path> - if this label is chosen, use tftp to retrieve a fdt blob - relative to <path>. If the fdtfile environment variable - is set, <path>/<fdtfile> is retrieved. Otherwise, the - filename is generated from the soc and board environment - variables, i.e. <path>/<soc>-<board>.dtb is retrieved. - If the fdt command is specified, fdtdir is ignored. - -localboot <flag> - Run the command defined by "localcmd" in the environment. - <flag> is ignored and is only here to match the syntax of - PXELINUX config files. - -Example -------- -Here's a couple of example files to show how this works. - -------------/tftpboot/pxelinux.cfg/menus/base.menu----------- -menu title Linux selections - -# This is the default label -label install - menu label Default Install Image - kernel kernels/install.bin - append console=ttyAMA0,38400 debug earlyprintk - initrd initrds/uzInitrdDebInstall - -# Just another label -label linux-2.6.38 - kernel kernels/linux-2.6.38.bin - append root=/dev/sdb1 - -# The locally installed kernel -label local - menu label Locally installed kernel - append root=/dev/sdb1 - localboot 1 -------------------------------------------------------------- - -------------/tftpboot/pxelinux.cfg/default------------------- -menu include pxelinux.cfg/menus/base.menu -timeout 500 - -default linux-2.6.38 -------------------------------------------------------------- - -When a pxe client retrieves and boots the default pxe file, -'pxe boot' will wait for user input for 5 seconds before booting -the linux-2.6.38 label, which will cause /tftpboot/kernels/linux-2.6.38.bin -to be downloaded, and boot with the command line "root=/dev/sdb1" - -Differences with PXELINUX -========================= -The biggest difference between U-Boot's pxe and PXELINUX is that since -U-Boot's pxe support is written entirely in C, it can run on any platform -with network support in U-Boot. Here are some other differences between -PXELINUX and U-Boot's pxe support. - -- U-Boot's pxe does not support the PXELINUX DHCP option codes specified - in RFC 5071, but could be extended to do so. - -- when U-Boot's pxe fails to boot, it will return control to U-Boot, - allowing another command to run, other U-Boot command, instead of resetting - the machine like PXELINUX. - -- U-Boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it - only uses U-Boot. - -- U-Boot's pxe doesn't provide the full menu implementation that PXELINUX - does, only a simple text based menu using the commands described in - this README. With PXELINUX, it's possible to have a graphical boot - menu, submenus, passwords, etc. U-Boot's pxe could be extended to support - a more robust menuing system like that of PXELINUX's. - -- U-Boot's pxe expects U-Boot uimg's as kernels. Anything that would work - with the 'bootm' command in U-Boot could work with the 'pxe boot' command. - -- U-Boot's pxe only recognizes a single file on the initrd command line. It - could be extended to support multiple. - -- in U-Boot's pxe, the localboot command doesn't necessarily cause a local - disk boot - it will do whatever is defined in the 'localcmd' env - variable. And since it doesn't support a full UNDI/PXE stack, the - type field is ignored. - -- the interactive prompt in U-Boot's pxe only allows you to choose a label - from the menu. If you want to boot something not listed, you can ctrl+c - out of 'pxe boot' and use existing U-Boot commands to accomplish it. diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 6f92cd28eb1..19e2ee9d407 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -32,7 +32,7 @@ The following OEM commands are supported (if enabled): - ``oem console`` - this dumps U-Boot console record buffer - ``oem board`` - this executes a custom board function which is defined by the vendor -Support for both eMMC and NAND devices is included. +Support for eMMC, NAND and SPI flash memory devices is included. Client installation ------------------- @@ -97,8 +97,9 @@ Raw partition descriptors ^^^^^^^^^^^^^^^^^^^^^^^^^ In cases where no partition table is present, a raw partition descriptor can be -defined, specifying the offset, size, and optionally the MMC hardware partition -number for a given partition name. +defined, specifying the memory offset and size. + +Currently, this support is available only for eMMC and SPI flash memory devices. This is useful when using fastboot to flash files (e.g. SPL or U-Boot) to a specific offset in the eMMC boot partition, without having to update the entire @@ -106,6 +107,15 @@ boot partition. To define a raw partition descriptor, add an environment variable similar to:: + fastboot_raw_partition_<raw partition name>=<offset> <size> + +for example:: + + fastboot_raw_partition_boot=0x100 0x1f00 + +Optionally, in the eMMC case, the hardware partition number can also be +specified for a given partition name:: + fastboot_raw_partition_<raw partition name>=<offset> <size> [mmcpart <num>] for example:: diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst new file mode 100644 index 00000000000..a1f526fd4cc --- /dev/null +++ b/doc/board/nxp/imx93_frdm.rst @@ -0,0 +1,75 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx93_frdm +========== + +U-Boot for the NXP i.MX93 FRDM board + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot +- Boot from the SD card + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.8 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx93 bl31 + $ cp build/imx93/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +---------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin + $ chmod +x firmware-sentinel-0.11.bin + $ ./firmware-sentinel-0.11.bin + $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx93_frdm_defconfig + $ make + +Copy the flash.bin binary to the MicroSD card at offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1k seek=32; sync + +Boot from the SD card +--------------------- + +- Configure SW1 boot switches to SD boot mode: + 0011 SW1[3:0] - ("USDHC2 4-bit SD3.0" Boot Mode) +- Insert the SD card in the SD slot (P13) of the board. +- Connect a USB Type-C cable into the P16 Debug USB Port and connect + using a terminal emulator at 115200 bps, 8n1. The console will show up + at /dev/ttyACM0. +- Power on the board by connecting a USB Type-C cable into the P1 + Power USB Port. diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index e7ec725cc04..aa7d857346d 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -15,6 +15,7 @@ NXP Semiconductors imx91_11x11_evk imx93_9x9_qsb imx93_11x11_evk + imx93_frdm imx95_evk imxrt1020-evk imxrt1050-evk diff --git a/doc/board/qualcomm/debugging.rst b/doc/board/qualcomm/debugging.rst index 1c35d1909d1..c3289c9e4e3 100644 --- a/doc/board/qualcomm/debugging.rst +++ b/doc/board/qualcomm/debugging.rst @@ -1,5 +1,5 @@ .. SPDX-License-Identifier: GPL-2.0+ -.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org> +.. sectionauthor:: Casey Connolly <casey.connolly@linaro.org> Qualcomm debugging ================== diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index ccf834208e9..3238a68e859 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -6,10 +6,11 @@ Qualcomm .. toctree:: :maxdepth: 2 + board + debugging dragonboard410c - rb3gen2 dragonwing - board + rb3gen2 + iq8 phones - debugging rdp diff --git a/doc/board/qualcomm/iq8.rst b/doc/board/qualcomm/iq8.rst new file mode 100644 index 00000000000..f3df0ee00bc --- /dev/null +++ b/doc/board/qualcomm/iq8.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. sectionauthor:: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> + +Qualcomm DragonWing IQ8 +======================================== + +The Dragonwing IQ8 Series (which includes QCS8300) powers computeheavy and AI-based devices, and is designed +to operate in an expanded temperature range with available built-in safety features. +Dragonwing IQ8 Series delivers industrial-grade AI performance of up to 40 TOPS, an octa-core +Qualcomm Kryo Gen 6 CPU, a powerful Qualcomm Adreno 623 GPU, support for +up to 12 concurrent cameras, and 4K video encode and decode alongside multiple displays. + +More information can be found on the `Qualcomm's IQ8 product page`_. + +.. _Qualcomm's IQ8 product page: https://docs.qualcomm.com/bundle/publicresource/87-83839-1_REV_A_Qualcomm_IQ8_Series_Product_Brief________.pdf + +Installation +------------ +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``QCS8300``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make qcom_qcs8300_defconfig + $ make -j8 u-boot.mbn + +This will build the signed ``u-boot.mbn`` in the configured output directory. +The firmware expects firmware ELF images to be "signed". The signature +does not provide any security in this case, but it provides the firmware +with some required metadata. + +Then flash the resulting ``u-boot.mbn`` to the ``uefi_a`` partition +on your device with ``fastboot flash uefi_a u-boot.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +Note that fastboot is not yet supported in U-Boot on Dragonwing IQ8, as a result, to flash +back the original firmware, or new versoins of the U-Boot, EDL mode must be used. + +A tool like bkerler's `edl`_ can be used for flashing. + +$ edl.py --loader /path/to/prog_firehose_ddr.elf w uefi_a u-boot.mbn + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _edl: https://github.com/bkerler/edl diff --git a/doc/board/qualcomm/phones.rst b/doc/board/qualcomm/phones.rst index 1d27196cf54..8afc7587731 100644 --- a/doc/board/qualcomm/phones.rst +++ b/doc/board/qualcomm/phones.rst @@ -1,5 +1,5 @@ .. SPDX-License-Identifier: GPL-2.0+ -.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org> +.. sectionauthor:: Casey Connolly <casey.connolly@linaro.org> ====================================== Booting U-Boot on Qualcomm smartphones diff --git a/doc/board/qualcomm/rb3gen2.rst b/doc/board/qualcomm/rb3gen2.rst index 4240606224f..518d01c4c3a 100644 --- a/doc/board/qualcomm/rb3gen2.rst +++ b/doc/board/qualcomm/rb3gen2.rst @@ -1,5 +1,5 @@ .. SPDX-License-Identifier: GPL-2.0+ -.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org> +.. sectionauthor:: Casey Connolly <casey.connolly@linaro.org> Qualcomm Robotics RB3 Gen 2 =========================== diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst index 0a7b6fc0c9d..b435fa8b353 100644 --- a/doc/board/samsung/e850-96.rst +++ b/doc/board/samsung/e850-96.rst @@ -43,17 +43,19 @@ Legend: BL31 in terms of ARM boot flow * ``LDFW``: Loadable Firmware -Build Procedure +Unbricking Note --------------- -.. warning:: - At the moment USB is not enabled in U-Boot for this board. Although eMMC is - enabled, you won't be able to flash images over USB (fastboot). So flashing - U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can - be used then to perform USB boot and flash LittleKernel bootloader binary [7]_ - to unbrick and revive the board. Flashing U-Boot binary might be helpful for - developers or anybody who want to check current state of U-Boot enablement on - E850-96 (which is mostly serial console, eMMC and related blocks). +In case the board is bricked for some reason, the ``dltool`` [8]_ can be used to +unbrick and revive it. This tool performs USB boot, and uploads the LittleKernel +bootloader over USB, which is then being executed on the board. The loaded +bootloader further enters fastboot mode, so that the user can flash the +functional bootloader binary (U-Boot or LittleKernel [7]_) to eMMC using +``fastboot`` tool. Please read the ``dltool`` README file for more details about +the procedure. + +Build Procedure +--------------- Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): @@ -64,8 +66,9 @@ Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): make e850-96_defconfig make -Boot E850-96 board into fastboot mode as described in board software doc [9]_, -and flash U-Boot binary into ``bootloader`` eMMC partition: +The original E850-96 board is shipped with LittleKernel-based bootloader flashed +in eMMC. To replace it with U-Boot, boot into fastboot mode (as described in +the board software documentation [9]_), and flash U-Boot binary: .. prompt:: bash $ @@ -74,6 +77,66 @@ and flash U-Boot binary into ``bootloader`` eMMC partition: U-Boot will boot up to the shell. +Flashing +-------- + +User area of eMMC contains GPT partition table (either Linux or Android). Boot +Partition A (``mmc0boot0``) contains all firmware/bootloaders. Boot Partition +B (``mmc0boot1``) contains U-Boot environment. + +First make sure to format eMMC accordingly. Prepare the initial environment: + +.. prompt:: bash => + + env default -f -a + env save + +For Linux, just format eMMC using default ``$partitions`` definitions: + +.. prompt:: bash => + + gpt write mmc 0 $partitions + +For Android, use ``$partitions_android`` instead: + +.. prompt:: bash => + + setenv partitions_linux $partitions + setenv partitions $partitions_android + env save + gpt write mmc 0 $partitions + +In case of Linux, there are two partitions available: ``esp`` (EFI System +Partition) and ``rootfs``. It is recommended to use fastboot to flash images to +those partitions. Enter fastboot mode on your device: + +.. prompt:: bash => + + fastboot usb 0 + +And then flash the images: + +.. prompt:: bash $ + + fastboot flash esp esp.img + fastboot flash rootfs rootfs.img + +To update the firmware, it's easier to use DFU. Enter DFU mode on the board: + +.. prompt:: bash => + + dfu 0 mmc 0 + +To update U-Boot: + +.. prompt:: bash $ + + dfu-util -D u-boot.bin -a bootloader + +It's also possible to use fastboot to flash the whole ``mmc0boot0`` HW +partition, but it's not so straightforward, as one have to prepare the image for +the whole ``boot0`` partition containing all firmware binaries first. + References ---------- diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst index 349fb394d74..22442874110 100644 --- a/doc/board/ti/j784s4_evm.rst +++ b/doc/board/ti/j784s4_evm.rst @@ -90,6 +90,15 @@ Set the variables corresponding to this platform: export OPTEE_PLATFORM=k3-j784s4 export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8" +.. note:: + + For AM69-SK, use the following U_BOOT_CFG instead: + + .. prompt:: bash + + export UBOOT_CFG_CORTEXR=am69_sk_r5_defconfig + export UBOOT_CFG_CORTEXA=am69_sk_a72_defconfig + .. j784s4_evm_rst_include_start_build_steps 1. Trusted Firmware-A diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index f2ffcf3d331..7aa36166a5d 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -55,7 +55,7 @@ Current Status * U-Boot v2025.07 was released on Monday, 07 July 2025. -* The Merge Window for the next release (|next_ver|) is **open** until the -rc1 +* The Merge Window for the next release (|next_ver|) is **closed** with the -rc1 release on Monday, 28 July 2025. * The next branch is now **closed** until the -rc2 release on Monday, 11 August @@ -69,9 +69,9 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -.. For the next scheduled release, release candidates were made on:: +For the next scheduled release, release candidates were made on:: -.. * U-Boot |next_ver|-rc1 was released on Mon 28 July 2025. +* U-Boot |next_ver|-rc1 was released on Mon 28 July 2025. .. * U-Boot |next_ver|-rc2 was released on Mon 11 August 2025. diff --git a/doc/develop/uefi/u-boot_on_efi.rst b/doc/develop/uefi/u-boot_on_efi.rst index 245b4af1fa3..177e887ebd9 100644 --- a/doc/develop/uefi/u-boot_on_efi.rst +++ b/doc/develop/uefi/u-boot_on_efi.rst @@ -45,15 +45,15 @@ First choose a board that has EFI support and obtain an EFI implementation for that board. It will be either 32-bit or 64-bit. Alternatively, you can opt for using QEMU [1] and the OVMF [2], as detailed below. -To build U-Boot as an EFI application, enable CONFIG_EFI and CONFIG_EFI_APP. -The efi-x86_app32 and efi-x86_app64 configs are set up for this. Just build -U-Boot as normal, e.g.:: +To build U-Boot as an EFI application, enable CONFIG_EFI_CLIENT and +CONFIG_EFI_APP. The efi-x86_app32 and efi-x86_app64 configs are set up for +this. Just build U-Boot as normal, e.g.:: make efi-x86_app32_defconfig make To build U-Boot as an EFI payload (32-bit or 64-bit EFI can be used), enable -CONFIG_EFI, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or +CONFIG_EFI_CLIENT, CONFIG_EFI_STUB, and select either CONFIG_EFI_STUB_32BIT or CONFIG_EFI_STUB_64BIT. The efi-x86_payload configs (efi-x86_payload32_defconfig and efi-x86_payload32_defconfig) are set up for this. Then build U-Boot as normal, e.g.:: @@ -113,7 +113,7 @@ implemented completely differently. EFI Application ~~~~~~~~~~~~~~~ For the application the whole of U-Boot is built as a shared library. The -efi_main() function is in lib/efi/efi_app.c. It sets up some basic EFI +efi_main() function is in lib/efi_client/efi_app.c. It sets up some basic EFI functions with efi_init(), sets up U-Boot global_data, allocates memory for U-Boot's malloc(), etc. and enters the normal init sequence (board_init_f() and board_init_r()). @@ -121,7 +121,7 @@ and board_init_r()). Since U-Boot limits its memory access to the allocated regions very little special code is needed. The CONFIG_EFI_APP option controls a few things that need to change so 'git grep CONFIG_EFI_APP' may be instructive. -The CONFIG_EFI option controls more general EFI adjustments. +The CONFIG_EFI_CLIENT option controls more general EFI adjustments. The only available driver is the serial driver. This calls back into EFI 'boot services' to send and receive characters. Although it is implemented @@ -149,7 +149,7 @@ image (including device tree) into a small EFI stub application responsible for booting it. The stub application is built as a normal EFI application except that it has a lot of data attached to it. -The stub application is implemented in lib/efi/efi_stub.c. The efi_main() +The stub application is implemented in lib/efi_client/efi_stub.c. The efi_main() function is called by EFI. It is responsible for copying U-Boot from its original location into memory, disabling EFI boot services and starting U-Boot. U-Boot then starts as normal, relocates, starts all drivers, etc. @@ -192,7 +192,7 @@ careful to build the correct one so that your UEFI firmware can start it. Most UEFI images are 64-bit at present. The payload stub can be build as either 32- or 64-bits. Only a small amount -of code is built this way (see the extra- line in lib/efi/Makefile). +of code is built this way (see the extra- line in lib/efi_client/Makefile). Everything else is built as a normal U-Boot, so is always 32-bit on x86 at present. @@ -353,7 +353,7 @@ This work could be extended in a number of ways: Where is the code? ------------------ -lib/efi +lib/efi_client payload stub, application, support code. Mostly arch-neutral arch/x86/cpu/efi diff --git a/doc/git-mailrc b/doc/git-mailrc index 1982785f60e..747ceda3307 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -13,7 +13,7 @@ alias u-boot uboot alias abiessmann Andreas Bießmann <andreas@biessmann.org> alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com> alias afleming Andy Fleming <afleming@gmail.com> -alias ag Anatolij Gustschin <agust@denx.de> +alias ag Anatolij Gustschin <ag.dev.uboot@gmail.com> alias agraf Alexander Graf <agraf@csgraf.de> alias alexnemirovsky Alex Nemirovsky <alex.nemirovsky@cortina-access.com> alias alisonwang Alison Wang <alison.wang@nxp.com> diff --git a/doc/usage/fit/signature.rst b/doc/usage/fit/signature.rst index b868dcbf9fd..e5b5a8432e9 100644 --- a/doc/usage/fit/signature.rst +++ b/doc/usage/fit/signature.rst @@ -433,16 +433,14 @@ CONFIG_LEGACY_IMAGE_FORMAT Testing ------- -An easy way to test signing and verification is to use the test script -provided in test/vboot/vboot_test.sh. This uses sandbox (a special version +An easy way to test signing and verification is to use the vboot tests +provided in the pytest suite. This uses sandbox (a special version of U-Boot which runs under Linux) to show the operation of a 'bootm' command loading and verifying images. A sample run is show below:: - $ make O=sandbox sandbox_config - $ make O=sandbox - $ O=sandbox ./test/vboot/vboot_test.sh + $ ./test/py/test.py --bd sandbox --build -k vboot Simple Verified Boot Test diff --git a/doc/usage/fit/x86-fit-boot.rst b/doc/usage/fit/x86-fit-boot.rst index 9e3e32204d5..18704af3bac 100644 --- a/doc/usage/fit/x86-fit-boot.rst +++ b/doc/usage/fit/x86-fit-boot.rst @@ -259,11 +259,12 @@ Why Bother? References ---------- -In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for +In the Linux kernel, `Documentation/arch/x86/boot.rst +<https://docs.kernel.org/arch/x86/boot.html>`_ defines the boot protocol for the kernel including the setup.bin format. This is handled in U-Boot in arch/x86/lib/zimage.c and arch/x86/lib/bootm.c. -Various files in the same directory as this file describe the FIT format. - +The FIT file format is described in the `Flattened Image Tree Specification +<https://fitspec.osfw.foundation/>`_. .. sectionauthor:: Simon Glass <sjg@chromium.org> 7-Oct-2014 diff --git a/doc/usage/index.rst b/doc/usage/index.rst index e9e0bd04e05..b9de87a6ed9 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -12,6 +12,7 @@ Use U-Boot fit/index netconsole partitions + pxe cmdline semihosting measured_boot diff --git a/doc/usage/pxe.rst b/doc/usage/pxe.rst new file mode 100644 index 00000000000..c2dc11f218d --- /dev/null +++ b/doc/usage/pxe.rst @@ -0,0 +1,346 @@ +.. SPDX-License-Identifier: GPL-2.0+ + Copyright 2010-2011 Calxeda, Inc. + +PXE Boot and extlinux.conf +========================== + +The ``pxe`` commands provide a near subset of the functionality +provided by the PXELINUX boot loader. This allows U-Boot based systems +to be controlled remotely using the same PXE based techniques that +many non U-Boot based servers use. + +The ``sysboot`` command and Extlinux boot method use the same file +format as PXE boot for ``extlinux.conf``. + +Commands +-------- + +``pxe get`` + **Syntax:** ``pxe get`` + + follows PXELINUX's rules for retrieving configuration files + from a tftp server, and supports a subset of PXELINUX's config + file syntax. It requires certain environment variables to be + set, see the Environment section below. + + **File Paths** + + ``pxe get`` repeatedly tries to download config files until it + either successfully downloads one or runs out of paths to + try. The order and contents of paths it tries mirrors exactly + that of PXELINUX - you can read in more detail about it at: + + http://syslinux.zytor.com/wiki/index.php/Doc/pxelinux + +``pxe boot`` + **Syntax:** ``pxe boot [pxefile_addr_r]`` + + Interprets a pxe file stored in memory. + + ``pxefile_addr_r`` is an optional argument giving the location + of the pxe file. The file must be terminated with a NUL byte. + + There are some environment variables that may need to be set, + depending on conditions, see the Environment section below. + +``sysboot`` + **Syntax:** ``sysboot [-p] <interface> <dev[:part]> <ext2|fat|any> [addr] [filename]`` + + Load and boot an ``extlinux.conf`` file from a local + filesystem. Paths in the ``extlinux.conf`` file (kernel, + initrd, FDT and overlays) will be interpreted within that + filesystem. + + Example: + + ``sysboot mmc 0.0:2 any ${pxefile_addr_r} /boot/extlinux.conf`` + +Environment +----------- + +``pxefile_addr_r`` + Should be set to a location in RAM large enough to hold pxe + files while they're being processed. Up to 16 config files may + be held in memory at once. The exact number and size of the + files varies with how the system is being used. A typical + config file is a few hundred bytes long. Required for ``pxe + get``, for ``pxe boot`` if the optional argument + ``pxefile_addr_r`` is not supplied. + +``bootfile`` + Typically set in the DHCP response handler, required for ``pxe + get``. For ``pxe boot``, this path is used to generate the + base directory that all other paths to files retrieved by + ``pxe boot`` will use. If no bootfile is specified, paths used + in pxe files will be used as is. + +``serverip`` + Typically set in the DHCP response handler, this is the IP + address of the tftp server from which other files will be + retrieved. Required for ``pxe get``. + +``kernel_addr_r``, ``initrd_addr_r`` + Locations in RAM to store the kernel (or FIT image) and + initrd. These locations will be passed to the ``bootm`` + command to boot the kernel. These environment variables are + required to be set. + +``fdt_addr_r`` + Location in RAM to store the retrieved fdt blob. Retrieval is + possible if ``fdt`` label is defined in pxe file and + ``fdt_addr_r`` is set. If retrieval is possible, + ``fdt_addr_r`` will be passed to ``bootm`` command to boot the + kernel. + +``fdt_addr`` + Location of a fdt blob. ``fdt_addr`` will be passed to + ``bootm`` command if it is set and ``fdt_addr_r`` is not + passed to bootm command. + +``fdtoverlay_addr_r`` + Location in RAM to temporarily store fdt overlay(s) before + applying them to the fdt blob stored at + ``fdt_addr_r``. Required to use the ``fdtoverlays`` command in + the PXE file. + +``pxe_label_override`` + Override label to be used, if exists, instead of the default + label. This will allow consumers to choose a pxe label at + runtime instead of having to prompt the user. If + ``pxe_label_override`` is set but does not exist in the pxe + menu, pxe would fallback to the default label if given, and no + failure is returned but rather a warning message. + +``ethaddr`` + This is the standard MAC address for the ethernet adapter in + use. ``pxe get`` uses it to look for a configuration file + specific to a system's MAC address. + +``pxeuuid`` + This is a UUID in standard form using lower case hexadecimal + digits, for example, + 550e8400-e29b-41d4-a716-446655440000. ``pxe get`` uses it to + look for a configuration file based on the system's UUID. + +pxe file format +--------------- + +The pxe file format is nearly a subset of the PXELINUX file format; +see http://syslinux.zytor.com/wiki/index.php/PXELINUX. It's composed +of one line commands - global commands, and commands specific to +labels. Lines beginning with # are treated as comments. White space +between and at the beginning of lines is ignored. + +The size of pxe files and the number of labels is only limited by the amount +of RAM available to U-Boot. Memory for labels is dynamically allocated as +they're parsed, and memory for pxe files is statically allocated, and its +location is given by the pxefile_addr_r environment variable. The pxe code is +not aware of the size of the pxefile memory and will outgrow it if pxe files +are too large. + +Supported global commands +^^^^^^^^^^^^^^^^^^^^^^^^^ +Unrecognized commands are ignored. + +``default <label>`` + The label named here is treated as the default and is the + first label 'pxe boot' attempts to boot. + +``fallback <label>`` + The label named here is treated as a fallback option that may + be attempted should it be detected that booting of the default + has failed to complete, for example via U-Boot's boot count + limit functionality. + +``menu title <string>`` + Sets a title for the menu of labels being displayed. + +``menu include <path>`` + Use tftp to retrieve the pxe file at ``<path>``, which is then + immediately parsed as if the start of its contents were the + next line in the current file. nesting of include up to 16 + files deep is supported. + +``prompt <flag>`` + If 1, always prompt the user to enter a label to boot from. If + 0, only prompt the user if timeout expires. + +``timeout <num>`` + Wait for user input for <num>/10 seconds before auto-booting a + node. + +``label <name>`` + Begin a label definition. Labels continue until a command not + recognized as a label command is seen, or EOF is reached. + +Supported label commands +^^^^^^^^^^^^^^^^^^^^^^^^ +Labels end when a command not recognized as a label command is reached, or EOF. + +``menu default`` + set this label as the default label to boot; this is the same + behavior as the global default command but specified in a + different way + +``kernel <path>`` + If this label is chosen, use tftp to retrieve the kernel (or + FIT image) at ``<path>``. it will be stored at the address + indicated in the ``kernel_addr_r`` environment variable, and + that address will be passed to ``bootm`` to boot this + kernel. For FIT image, the configuration specification can be + appended to the file name, with the format: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + It will be passed to bootm with that address (see: + doc/uImage.FIT/command_syntax_extensions.txt). It is useful + for overlay selection in pxe file (see + :doc:`./fit/overlay-fdt-boot`). + +``fdtoverlays <path> [...]`` + If this label is chosen, use tftp to retrieve the DT + overlay(s) at ``<path>``. It will be temporarily stored at the + address indicated in the ``fdtoverlay_addr_r`` environment + variable, and then applied in the load order to the fdt blob + stored at the address indicated in the ``fdt_addr_r`` + environment variable. + +``devicetree-overlay <path> [...]`` + if this label is chosen, use tftp to retrieve the DT + overlay(s) at ``<path>``. It will be temporarily stored at the + address indicated in the ``fdtoverlay_addr_r`` environment + variable, and then applied in the load order to the fdt blob + stored at the address indicated in the ``fdt_addr_r`` + environment variable. Alias for fdtoverlays. + +``kaslrseed`` + set this label to request random number from hwrng as kaslr seed. + +``append <string>`` + Use ``<string>`` as the kernel command line when booting this + label. Environment variable references like ``${var}`` are + substituted before boot. + +``initrd <path>`` + If this label is chosen, use tftp to retrieve the initrd at + ``<path>``. it will be stored at the address indicated in the + ``initrd_addr_r`` environment variable, and that address will + be passed to ``bootm``. For FIT image, the initrd can be + provided with the same value than kernel, including + configuration: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + In this case, ``kernel_addr_r`` is passed to ``bootm``. + +``fdt <path>`` + If this label is chosen, use tftp to retrieve the fdt blob at + ``<path>``. It will be stored at the address indicated in the + ``fdt_addr_r`` environment variable, and that address will be + passed to ``bootm``. For FIT image, the device tree can be + provided with the same value than kernel, including + configuration: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + In this case, ``kernel_addr_r`` is passed to ``bootm``. + +``devicetree <path>`` + If this label is chosen, use tftp to retrieve the fdt blob at + ``<path>``. it will be stored at the address indicated in the + ``fdt_addr_r`` environment variable, and that address will be + passed to ``bootm``. Alias for fdt. + +``fdtdir <path>`` + If this label is chosen, use tftp to retrieve a fdt blob + relative to ``<path>``. If the ``fdtfile`` environment + variable is set, ``<path>/<fdtfile>`` is retrieved. Otherwise, + the filename is generated from the ``soc`` and ``board`` + environment variables, i.e. ``<path>/<soc>-<board>.dtb`` is + retrieved. If the ``fdt`` command is specified, ``fdtdir`` is + ignored. + +``localboot <flag>`` + Run the command defined by ``localcmd`` in the + environment. ``<flag>`` is ignored and is only here to match + the syntax of PXELINUX config files. + +Example +------- +Here's a couple of example files to show how this works. + +.. code-block:: + :caption: /tftpboot/pxelinux.cfg/menus/base.menu + + menu title Linux selections + + # This is the default label + label install + menu label Default Install Image + kernel kernels/install.bin + append console=ttyAMA0,38400 debug earlyprintk + initrd initrds/uzInitrdDebInstall + + # Just another label + label linux-2.6.38 + kernel kernels/linux-2.6.38.bin + append root=/dev/sdb1 + + # The locally installed kernel + label local + menu label Locally installed kernel + append root=/dev/sdb1 + localboot 1 + +.. code-block:: + :caption: /tftpboot/pxelinux.cfg/default + + menu include pxelinux.cfg/menus/base.menu + timeout 500 + + default linux-2.6.38 + +When a pxe client retrieves and boots the default pxe file, ``pxe +boot`` will wait for user input for 5 seconds before booting the +``linux-2.6.38`` label, which will cause +``/tftpboot/kernels/linux-2.6.38.bin`` to be downloaded, and boot with +the command line ``root=/dev/sdb1`` + +Differences with PXELINUX +------------------------- + +The biggest difference between U-Boot's pxe and PXELINUX is that since +U-Boot's pxe support is written entirely in C, it can run on any platform +with network support in U-Boot. Here are some other differences between +PXELINUX and U-Boot's pxe support. + +- U-Boot's pxe does not support the PXELINUX DHCP option codes specified + in RFC 5071, but could be extended to do so. + +- when U-Boot's pxe fails to boot, it will return control to U-Boot, + allowing another command to run, other U-Boot command, instead of resetting + the machine like PXELINUX. + +- U-Boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it + only uses U-Boot. + +- U-Boot's pxe doesn't provide the full menu implementation that PXELINUX + does, only a simple text based menu using the commands described in + this README. With PXELINUX, it's possible to have a graphical boot + menu, submenus, passwords, etc. U-Boot's pxe could be extended to support + a more robust menuing system like that of PXELINUX's. + +- U-Boot's pxe expects U-Boot uimg's as kernels. Anything that would work + with the 'bootm' command in U-Boot could work with the 'pxe boot' command. + +- U-Boot's pxe only recognizes a single file on the initrd command line. It + could be extended to support multiple. + +- in U-Boot's pxe, the localboot command doesn't necessarily cause a local + disk boot - it will do whatever is defined in the 'localcmd' env + variable. And since it doesn't support a full UNDI/PXE stack, the + type field is ignored. + +- the interactive prompt in U-Boot's pxe only allows you to choose a label + from the menu. If you want to boot something not listed, you can ctrl+c + out of 'pxe boot' and use existing U-Boot commands to accomplish it. diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c index f593fb6447b..d671df79f68 100644 --- a/drivers/adc/imx93-adc.c +++ b/drivers/adc/imx93-adc.c @@ -221,7 +221,7 @@ static int imx93_adc_stop(struct udevice *dev) static int imx93_adc_probe(struct udevice *dev) { struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; ret = imx93_adc_calibration(adc); if (ret < 0) @@ -238,7 +238,7 @@ static int imx93_adc_of_to_plat(struct udevice *dev) { struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; adc->regs = dev_read_addr_ptr(dev); if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) { diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 750b0bd2082..c6c148ebd17 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -96,7 +96,7 @@ config TPL_BLOCK_CACHE config EFI_MEDIA bool "Support EFI media drivers" - default y if EFI || SANDBOX + default y if EFI_CLIENT || SANDBOX select BLK help Enable this to support media devices on top of UEFI. This enables diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index f3ac8db9464..73c24fd9176 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -611,30 +611,6 @@ static int blk_flags_check(struct udevice *dev, enum blk_flag_t req_flags) return flags & req_flags ? 0 : 1; } -int blk_find_first(enum blk_flag_t flags, struct udevice **devp) -{ - int ret; - - for (ret = uclass_find_first_device(UCLASS_BLK, devp); - *devp && !blk_flags_check(*devp, flags); - ret = uclass_find_next_device(devp)) - return 0; - - return -ENODEV; -} - -int blk_find_next(enum blk_flag_t flags, struct udevice **devp) -{ - int ret; - - for (ret = uclass_find_next_device(devp); - *devp && !blk_flags_check(*devp, flags); - ret = uclass_find_next_device(devp)) - return 0; - - return -ENODEV; -} - int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp) { for (uclass_first_device(UCLASS_BLK, devp); diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 6cca861f81c..96cc2bc3abc 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o obj-$(CONFIG_AT91_SAM9X60_USB) += clk-sam9x60-usb.o obj-$(CONFIG_SAMA7G5) += sama7g5.o +obj-$(CONFIG_SAMA7D65) += sama7d65.o obj-$(CONFIG_SAM9X60) += sam9x60.o obj-$(CONFIG_SAM9X7) += sam9x7.o else diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index d28775d64d3..cdc5271fa83 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -37,7 +37,7 @@ #define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) -#define MASTER_MAX_ID 4 +#define MASTER_MAX_ID 10 struct clk_master { void __iomem *base; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index df8172bccac..65be2775ac3 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -32,7 +32,7 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define PLL_MAX_ID 7 +#define PLL_MAX_ID 8 struct sam9x60_pll { void __iomem *base; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c new file mode 100644 index 00000000000..8d2c25e6fa9 --- /dev/null +++ b/drivers/clk/at91/sama7d65.c @@ -0,0 +1,1451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SAMA7D65 PMC clock support. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <Ryan.Wanner@microchip.com> + * + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/at91.h> +#include <linux/clk-provider.h> + +#include "pmc.h" + +/** + * Clock identifiers to be used in conjunction with macros like + * AT91_TO_CLK_ID() + * + * @ID_MD_SLCK: TD slow clock identifier + * @ID_TD_SLCK: MD slow clock identifier + * @ID_MAIN_XTAL: Main Xtal clock identifier + * @ID_MAIN_RC: Main RC clock identifier + * @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier + * @ID_MAIN_OSC: Main Oscillator clock identifier + * @ID_MAINCK: MAINCK clock identifier + * @ID_PLL_CPU_FRAC: CPU PLL fractional clock identifier + * @ID_PLL_CPU_DIV: CPU PLL divider clock identifier + * @ID_PLL_SYS_FRAC: SYS PLL fractional clock identifier + * @ID_PLL_SYS_DIV: SYS PLL divider clock identifier + * @ID_PLL_DDR_FRAC: DDR PLL fractional clock identifier + * @ID_PLL_DDR_DIV: DDR PLL divider clock identifier + * @ID_PLL_GPU_FRAC: GPU PLL fractional clock identifier + * @ID_PLL_GPU_DIV: GPU PLL divider clock identifier + * @ID_PLL_BAUD_FRAC: Baud PLL fractional clock identifier + * @ID_PLL_BAUD_DIV: Baud PLL divider clock identifier + * @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier + * @ID_PLL_AUDIO_DIVPMC: Audio PLL PMC divider clock identifier + * @ID_PLL_AUDIO_DIVIO: Audio PLL IO divider clock identifier + * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier + * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier + * @ID_PLL_LVDS_FRAC: LVDS PLL fractional clock identifier + * @ID_PLL_LVDS_DIV: LVDS PLL divider clock identifier + * @ID_PLL_USB_FRAC: USB PLL fractional clock identifier + * @ID_PLL_USB_DIV: USB PLL divider clock identifier + + * @ID_MCK0_PRES: MCK0 PRES clock identifier + * @ID_MCK0_DIV: MCK0 DIV clock identifier + * @ID_MCK1: MCK1 clock identifier + * @ID_MCK2: MCK2 clock identifier + * @ID_MCK3: MCK3 clock identifier + * @ID_MCK4: MCK4 clock identifier + + * @ID_UTMI: UTMI clock identifier + + * @ID_PROG0: Programmable 0 clock identifier + * @ID_PROG1: Programmable 1 clock identifier + * @ID_PROG2: Programmable 2 clock identifier + * @ID_PROG3: Programmable 3 clock identifier + * @ID_PROG4: Programmable 4 clock identifier + * @ID_PROG5: Programmable 5 clock identifier + * @ID_PROG6: Programmable 6 clock identifier + * @ID_PROG7: Programmable 7 clock identifier + + * @ID_PCK0: System clock 0 clock identifier + * @ID_PCK1: System clock 1 clock identifier + * @ID_PCK2: System clock 2 clock identifier + * @ID_PCK3: System clock 3 clock identifier + * @ID_PCK4: System clock 4 clock identifier + * @ID_PCK5: System clock 5 clock identifier + * @ID_PCK6: System clock 6 clock identifier + * @ID_PCK7: System clock 7 clock identifier + */ +enum pmc_clk_ids { + ID_MD_SLCK = 0, + ID_TD_SLCK = 1, + ID_MAIN_XTAL = 2, + ID_MAIN_RC = 3, + ID_MAIN_RC_OSC = 4, + ID_MAIN_OSC = 5, + ID_MAINCK = 6, + + ID_PLL_CPU_FRAC = 7, + ID_PLL_CPU_DIV = 8, + ID_PLL_SYS_FRAC = 9, + ID_PLL_SYS_DIV = 10, + ID_PLL_DDR_FRAC = 11, + ID_PLL_DDR_DIV = 12, + ID_PLL_GPU_FRAC = 13, + ID_PLL_GPU_DIV = 14, + ID_PLL_BAUD_FRAC = 15, + ID_PLL_BAUD_DIV = 16, + ID_PLL_AUDIO_FRAC = 17, + ID_PLL_AUDIO_DIVPMC = 18, + ID_PLL_AUDIO_DIVIO = 19, + ID_PLL_ETH_FRAC = 20, + ID_PLL_ETH_DIV = 21, + ID_PLL_LVDS_FRAC = 22, + ID_PLL_LVDS_DIV = 23, + ID_PLL_USB_FRAC = 24, + ID_PLL_USB_DIV = 25, + + ID_MCK0_DIV = 26, + ID_MCK1 = 27, + ID_MCK2 = 28, + ID_MCK3 = 29, + ID_MCK4 = 30, + ID_MCK5 = 31, + ID_MCK6 = 32, + ID_MCK7 = 33, + ID_MCK8 = 34, + ID_MCK9 = 35, + + ID_UTMI = 36, + + ID_PROG0 = 37, + ID_PROG1 = 38, + ID_PROG2 = 39, + ID_PROG3 = 40, + ID_PROG4 = 41, + ID_PROG5 = 42, + ID_PROG6 = 43, + ID_PROG7 = 44, + + ID_PCK0 = 45, + ID_PCK1 = 46, + ID_PCK2 = 47, + ID_PCK3 = 48, + ID_PCK4 = 49, + ID_PCK5 = 50, + ID_PCK6 = 51, + ID_PCK7 = 52, + + ID_MCK0_PRES = 53, + + ID_MAX, +}; + +/** + * PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +/* Clock names used as parents for multiple clocks. */ +static const char *clk_names[] = { + [ID_MAIN_RC] = "main_rc", + [ID_MAIN_RC_OSC] = "main_rc_osc", + [ID_MAIN_OSC] = "main_osc", + [ID_MAINCK] = "mainck", + [ID_PLL_CPU_DIV] = "cpupll_divpmcck", + [ID_PLL_SYS_DIV] = "syspll_divpmcck", + [ID_PLL_DDR_DIV] = "ddrpll_divpmcck", + [ID_PLL_GPU_DIV] = "gpupll_divpmcck", + [ID_PLL_BAUD_DIV] = "baudpll_divpmcck", + [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", + [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", + [ID_PLL_ETH_DIV] = "ethpll_divpmcck", + [ID_PLL_LVDS_DIV] = "lvdspll_divpmcck", + [ID_PLL_USB_DIV] = "usbpll_divpmcck", + [ID_MCK0_DIV] = "mck0_div", + [ID_MCK0_PRES] = "mck0_pres", +}; + +/* Fractional PLL output range. */ +static const struct clk_range pll_outputs[] = { + { .min = 2343750, .max = 1200000000 }, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics pll_characteristics = { + .input = { .min = 12000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(pll_outputs), + .output = pll_outputs, + .core_output = core_outputs, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_layout_frac = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, +}; + +/* Layout for DIVPMC dividers. */ +static const struct clk_pll_layout pll_layout_divpmc = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_layout_divio = { + .div_mask = GENMASK(19, 12), + .endiv_mask = BIT(30), + .div_shift = 12, + .endiv_shift = 30, +}; + +/* MCK0 characteristics. */ +static const struct clk_master_characteristics mck0_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, +}; + +/* MCK0 layout. */ +static const struct clk_master_layout mck0_layout = { + .mask = 0x773, + .pres_shift = 4, + .offset = 0x28, +}; + +/* Programmable clock layout. */ +static const struct clk_programmable_layout programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +/* Peripheral clock layout. */ +static const struct clk_pcr_layout sama7d65_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +/** + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: true if clock is critical and cannot be disabled + * @id: clock id corresponding to PLL driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + u8 c; + u8 id; + u8 cid; +} sama7d65_plls[] = { + { + .n = "cpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_FRAC, + }, + + { + .n = "cpupll_divpmcck", + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_DIV, + }, + + { + .n = "syspll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_FRAC, + }, + + { + .n = "syspll_divpmcck", + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_DIV, + }, + + { + .n = "ddrpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_FRAC, + }, + + { + .n = "ddrpll_divpmcck", + .p = "ddrpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_DIV, + }, + + { + .n = "gpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 3, + .cid = ID_PLL_GPU_FRAC, + }, + + { + .n = "gpupll_divpmcck", + .p = "gpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 3, + .cid = ID_PLL_GPU_DIV + }, + + { + .n = "baudpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 4, + .cid = ID_PLL_BAUD_FRAC, + }, + + { + .n = "baudpll_divpmcck", + .p = "baudpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 4, + .cid = ID_PLL_BAUD_DIV, + }, + + { + .n = "audiopll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 5, + .cid = ID_PLL_AUDIO_FRAC, + }, + + { + .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVPMC, + }, + + { + .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVIO, + }, + + { + .n = "ethpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 6, + .cid = ID_PLL_ETH_FRAC, + }, + + { + .n = "ethpll_divpmcck", + .p = "ethpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 6, + .cid = ID_PLL_ETH_DIV, + }, + { + .n = "lvdspll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 7, + .cid = ID_PLL_LVDS_FRAC, + }, + { + .n = "lvdspll_divpmcck", + .p = "lvdspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 7, + .cid = ID_PLL_LVDS_DIV, + }, + { + .n = "usbpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 8, + .cid = ID_PLL_USB_FRAC, + }, + { + .n = "usbpll_divmpcck", + .p = "usbpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 8, + .cid = ID_PLL_USB_DIV, + }, +}; + +/** + * Master clock (MCK[1..9]) description + * @n: clock name + * @ep: extra parents names array + * @ep_chg_chg_id: index in parents array that specifies the changeable + * parent + * @ep_count: extra parents count + * @ep_mux_table: mux table for extra parents + * @ep_clk_mux_table: mux table to deal with subsystem clock ids + * @id: clock id corresponding to MCK driver + * @cid: clock id corresponding to clock subsystem + * @c: true if clock is critical and cannot be disabled + */ +static const struct { + const char *n; + const char *ep[4]; + u8 ep_count; + u8 ep_mux_table[4]; + u8 ep_clk_mux_table[4]; + u8 id; + u8 cid; + u8 c; +} sama7d65_mckx[] = { + { + .n = "mck1", + .id = 1, + .cid = ID_MCK1, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck2", + .id = 2, + .cid = ID_MCK2, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + .c = 1, + }, + + { + .n = "mck3", + .id = 3, + .cid = ID_MCK3, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + }, + + { + .n = "mck4", + .id = 4, + .cid = ID_MCK4, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck5", + .id = 5, + .cid = ID_MCK5, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + + { + .n = "mck6", + .id = 6, + .cid = ID_MCK6, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck7", + .id = 7, + .cid = ID_MCK7, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck8", + .id = 8, + .cid = ID_MCK8, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck9", + .id = 9, + .cid = ID_MCK9, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + +}; + +/** + * Programmable clock description + * @n: clock name + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + u8 cid; +} sama7d65_prog[] = { + { .n = "prog0", .cid = ID_PROG0, }, + { .n = "prog1", .cid = ID_PROG1, }, + { .n = "prog2", .cid = ID_PROG2, }, + { .n = "prog3", .cid = ID_PROG3, }, + { .n = "prog4", .cid = ID_PROG4, }, + { .n = "prog5", .cid = ID_PROG5, }, + { .n = "prog6", .cid = ID_PROG6, }, + { .n = "prog7", .cid = ID_PROG7, }, +}; + +/* Mux table for programmable clocks. */ +static u32 sama7d65_prog_mux_table[] = { 0, 1, 2, 3, 5, 7, 8, 9, 10, 12, }; + +/** + * System clock description + * @n: clock name + * @p: parent clock name + * @id: clock id corresponding to system clock driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + u8 id; + u8 cid; +} sama7d65_systemck[] = { + { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, + { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, + { .n = "pck2", .p = "prog2", .id = 10, .cid = ID_PCK2, }, + { .n = "pck3", .p = "prog3", .id = 11, .cid = ID_PCK3, }, + { .n = "pck4", .p = "prog4", .id = 12, .cid = ID_PCK4, }, + { .n = "pck5", .p = "prog5", .id = 13, .cid = ID_PCK5, }, + { .n = "pck6", .p = "prog6", .id = 14, .cid = ID_PCK6, }, + { .n = "pck7", .p = "prog7", .id = 15, .cid = ID_PCK7, }, +}; + +/** + * Peripheral clock description + * @n: clock name + * @p: clock parent name + * @r: clock range values + * @id: clock id + */ +static const struct { + const char *n; + const char *p; + struct clk_range r; + u8 id; +} sama7d65_periphck[] = { + { .n = "pioA_clk", .p = "mck0_div", .id = 10, }, + { .n = "sfr_clk", .p = "mck7", .id = 18, }, + { .n = "hsmc_clk", .p = "mck5", .id = 20, }, + { .n = "xdmac0_clk", .p = "mck6", .id = 21, }, + { .n = "xdmac1_clk", .p = "mck6", .id = 22, }, + { .n = "xdmac2_clk", .p = "mck1", .id = 23, }, + { .n = "acc_clk", .p = "mck7", .id = 24, }, + { .n = "aes_clk", .p = "mck6", .id = 26, }, + { .n = "tzaesbasc_clk", .p = "mck8", .id = 27, }, + { .n = "asrc_clk", .p = "mck9", .id = 29, .r = { .max = 200000000, }, }, + { .n = "cpkcc_clk", .p = "mck0_div", .id = 30, }, + { .n = "eic_clk", .p = "mck7", .id = 33, }, + { .n = "flex0_clk", .p = "mck7", .id = 34, }, + { .n = "flex1_clk", .p = "mck7", .id = 35, }, + { .n = "flex2_clk", .p = "mck7", .id = 36, }, + { .n = "flex3_clk", .p = "mck7", .id = 37, }, + { .n = "flex4_clk", .p = "mck8", .id = 38, }, + { .n = "flex5_clk", .p = "mck8", .id = 39, }, + { .n = "flex6_clk", .p = "mck8", .id = 40, }, + { .n = "flex7_clk", .p = "mck8", .id = 41, }, + { .n = "flex8_clk", .p = "mck9", .id = 42, }, + { .n = "flex9_clk", .p = "mck9", .id = 43, }, + { .n = "flex10_clk", .p = "mck9", .id = 44, }, + { .n = "gmac0_clk", .p = "mck6", .id = 46, }, + { .n = "gmac1_clk", .p = "mck6", .id = 47, }, + { .n = "gmac0_tsu_clk", .p = "mck1", .id = 49, }, + { .n = "gmac1_tsu_clk", .p = "mck1", .id = 50, }, + { .n = "icm_clk", .p = "mck5", .id = 53, }, + { .n = "i2smcc0_clk", .p = "mck9", .id = 54, .r = { .max = 200000000, }, }, + { .n = "i2smcc1_clk", .p = "mck9", .id = 55, .r = { .max = 200000000, }, }, + { .n = "matrix_clk", .p = "mck5", .id = 57, }, + { .n = "mcan0_clk", .p = "mck5", .id = 58, .r = { .max = 200000000, }, }, + { .n = "mcan1_clk", .p = "mck5", .id = 59, .r = { .max = 200000000, }, }, + { .n = "mcan2_clk", .p = "mck5", .id = 60, .r = { .max = 200000000, }, }, + { .n = "mcan3_clk", .p = "mck5", .id = 61, .r = { .max = 200000000, }, }, + { .n = "mcan4_clk", .p = "mck5", .id = 62, .r = { .max = 200000000, }, }, + { .n = "pdmc0_clk", .p = "mck9", .id = 64, .r = { .max = 200000000, }, }, + { .n = "pdmc1_clk", .p = "mck9", .id = 65, .r = { .max = 200000000, }, }, + { .n = "pit64b0_clk", .p = "mck7", .id = 66, }, + { .n = "pit64b1_clk", .p = "mck7", .id = 67, }, + { .n = "pit64b2_clk", .p = "mck7", .id = 68, }, + { .n = "pit64b3_clk", .p = "mck8", .id = 69, }, + { .n = "pit64b4_clk", .p = "mck8", .id = 70, }, + { .n = "pit64b5_clk", .p = "mck8", .id = 71, }, + { .n = "pwm_clk", .p = "mck7", .id = 72, }, + { .n = "qspi0_clk", .p = "mck5", .id = 73, }, + { .n = "qspi1_clk", .p = "mck5", .id = 74, }, + { .n = "sdmmc0_clk", .p = "mck1", .id = 75, }, + { .n = "sdmmc1_clk", .p = "mck1", .id = 76, }, + { .n = "sdmmc2_clk", .p = "mck1", .id = 77, }, + { .n = "sha_clk", .p = "mck6", .id = 78, }, + { .n = "spdifrx_clk", .p = "mck9", .id = 79, .r = { .max = 200000000, }, }, + { .n = "spdiftx_clk", .p = "mck9", .id = 80, .r = { .max = 200000000, }, }, + { .n = "ssc0_clk", .p = "mck7", .id = 81, .r = { .max = 200000000, }, }, + { .n = "ssc1_clk", .p = "mck8", .id = 82, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch0_clk", .p = "mck8", .id = 83, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch1_clk", .p = "mck8", .id = 84, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch2_clk", .p = "mck8", .id = 85, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch0_clk", .p = "mck5", .id = 86, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch1_clk", .p = "mck5", .id = 87, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch2_clk", .p = "mck5", .id = 88, .r = { .max = 200000000, }, }, + { .n = "tcpca_clk", .p = "mck5", .id = 89, }, + { .n = "tcpcb_clk", .p = "mck5", .id = 90, }, + { .n = "tdes_clk", .p = "mck6", .id = 91, }, + { .n = "trng_clk", .p = "mck6", .id = 92, }, + { .n = "udphsa_clk", .p = "mck5", .id = 99, }, + { .n = "udphsb_clk", .p = "mck5", .id = 100, }, + { .n = "uhphs_clk", .p = "mck5", .id = 101, }, +}; + +/** + * Generic clock description + * @n: clock name + * @ep: extra parents names + * @ep_mux_table: extra parents mux table + * @ep_clk_mux_table: extra parents clock mux table (for CCF) + * @r: clock output range + * @ep_count: extra parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *ep[8]; + const char ep_mux_table[8]; + const char ep_clk_mux_table[8]; + struct clk_range r; + u8 ep_count; + u8 id; +} sama7d65_gck[] = { + { + .n = "adc_gclk", + .id = 25, + .r = { .max = 100000000, }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", }, + .ep_mux_table = { 8, 9, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 2, + }, + + { + .n = "asrc_gclk", + .id = 29, + .r = { .max = 200000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "flex0_gclk", + .id = 34, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex1_gclk", + .id = 35, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex2_gclk", + .id = 36, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex3_gclk", + .id = 37, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex4_gclk", + .id = 38, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex5_gclk", + .id = 39, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex6_gclk", + .id = 40, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex7_gclk", + .id = 41, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex8_gclk", + .id = 42, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex9_gclk", + .id = 43, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex10_gclk", + .id = 44, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_gclk", + .id = 46, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_mux_table = { 10, }, + .ep_count = 1, + }, + + { + .n = "gmac1_gclk", + .id = 47, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_mux_table = { 10, }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_tsu_gclk", + .id = 49, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "gmac1_tsu_gclk", + .id = 50, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "i2smcc0_gclk", + .id = 54, + .r = { .max = 100000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "i2smcc1_gclk", + .id = 55, + .r = { .max = 100000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "mcan0_gclk", + .id = 58, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV }, + .ep_count = 1, + }, + + { + .n = "mcan1_gclk", + .id = 59, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan2_gclk", + .id = 60, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan3_gclk", + .id = 61, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan4_gclk", + .id = 62, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "pdmc0_gclk", + .id = 64, + .r = { .max = 80000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pdmc1_gclk", + .id = 65, + .r = { .max = 80000000, }, + .ep = { "audiopll_divpmcck",}, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pit64b0_gclk", + .id = 66, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b1_gclk", + .id = 67, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b2_gclk", + .id = 68, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b3_gclk", + .id = 69, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b4_gclk", + .id = 70, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b5_gclk", + .id = 71, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "qspi0_gclk", + .id = 73, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "qspi1_gclk", + .id = 74, + .r = { .max = 266000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc0_gclk", + .id = 75, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "sdmmc1_gclk", + .id = 76, + .r = { .max = 208000000 }, + .ep = { "baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc2_gclk", + .id = 77, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck",}, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "spdifrx_gclk", + .id = 79, + .r = { .max = 150000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "spdiftx_gclk", + .id = 80, + .r = { .max = 25000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = {9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "tcb0_ch0_gclk", + .id = 83, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "tcb1_ch0_gclk", + .id = 86, + .r = { .max = 67000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "DSI_gclk", + .id = 103, + .r = {.max = 27000000}, + .ep = {"syspll_divpmcck"}, + .ep_mux_table = {5}, + .ep_clk_mux_table = {ID_PLL_SYS_DIV}, + .ep_count = 1, + }, + + { + .n = "I3CC_gclk", + .id = 105, + .r = {.max = 125000000}, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, +}; + +/* Clock setup description */ +static const struct pmc_clk_setup sama7d65_clk_setup[] = { + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC), + .rate = 625000000, + }, + + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV), + .rate = 625000000, + }, +}; + +#define SAMA7D65_MAX_MUX_ALLOCS (64) + +#define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \ + do { \ + int _i; \ + if ((_index) >= SAMA7D65_MAX_MUX_ALLOCS) { \ + debug("%s(): AT91: MUX: insufficient space\n", \ + __func__); \ + goto _label; \ + } \ + (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \ + if (!(_dst)) \ + goto _label; \ + (_allocs)[(_index)++] = (_dst); \ + for (_i = 0; _i < (_num); _i++) \ + (_dst)[_i] = (_src)[_i]; \ + } while (0) + +static int sama7d65_clk_probe(struct udevice *dev) +{ + void __iomem *base = (void *)devfdt_get_addr(dev); + unsigned int *clkmuxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + unsigned int *muxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + const char *p[12]; + unsigned int cm[12], m[12], *tmpclkmux, *tmpmux; + struct clk clk, *c; + bool main_osc_bypass; + int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; + + if (IS_ERR(base)) + return PTR_ERR(base); + + memset(muxallocs, 0, ARRAY_SIZE(muxallocs)); + memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs)); + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_TD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 2, &clk); + if (ret) + return ret; + clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk), + strlen(clk_hw_get_name(&clk)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MAIN_XTAL]) + return -ENOMEM; + + main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass"); + + /* Register main rc oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), + at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC], + NULL)); + + /* Register main oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), + at91_clk_main_osc(base, clk_names[ID_MAIN_OSC], + clk_names[ID_MAIN_XTAL], main_osc_bypass)); + + /* Register mainck. */ + p[0] = clk_names[ID_MAIN_RC_OSC]; + p[1] = clk_names[ID_MAIN_OSC]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), + at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p, 2, + tmpclkmux, PMC_TYPE_CORE)); + + /* Register PLL fracs clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_FRAC) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_frac_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register PLL div clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_DIV) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_div_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register MCK0_PRES clock. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_MAINCK]; + p[2] = clk_names[ID_PLL_CPU_DIV]; + p[3] = clk_names[ID_PLL_SYS_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_CPU_DIV); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), + at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], + p, 4, &mck0_layout, + &mck0_characteristics, + tmpclkmux)); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), + at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], + clk_names[ID_MCK0_PRES], + &mck0_layout, + &mck0_characteristics)); + + /* Register MCK1-9 clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + for (i = 0; i < ARRAY_SIZE(sama7d65_mckx); i++) { + for (j = 0; j < sama7d65_mckx[i].ep_count; j++) { + p[4 + j] = sama7d65_mckx[i].ep[j]; + m[4 + j] = sama7d65_mckx[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_mckx[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_mckx[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_mckx[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_mckx[i].cid), + at91_clk_sama7g5_register_master(base, sama7d65_mckx[i].n, p, + 4 + sama7d65_mckx[i].ep_count, + tmpmux, tmpclkmux, + sama7d65_mckx[i].c, + sama7d65_mckx[i].id)); + } + + /* Register programmable clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + p[4] = clk_names[ID_PLL_SYS_DIV]; + p[5] = clk_names[ID_PLL_GPU_DIV]; + p[6] = clk_names[ID_PLL_BAUD_DIV]; + p[7] = clk_names[ID_PLL_AUDIO_DIVPMC]; + p[8] = clk_names[ID_PLL_ETH_DIV]; + p[9] = clk_names[ID_PLL_USB_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_GPU_DIV); + cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_BAUD_DIV); + cm[7] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_AUDIO_DIVPMC); + cm[8] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV); + cm[9] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_USB_DIV); + + for (i = 0; i < ARRAY_SIZE(sama7d65_prog); i++) { + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 10, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_prog[i].cid), + at91_clk_register_programmable(base, sama7d65_prog[i].n, + p, 10, i, + &programmable_layout, + tmpclkmux, + sama7d65_prog_mux_table)); + } + + /* System clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sama7d65_systemck[i].cid), + at91_clk_register_system(base, sama7d65_systemck[i].n, + sama7d65_systemck[i].p, + sama7d65_systemck[i].id)); + } + + /* Peripheral clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_periphck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL, sama7d65_periphck[i].id), + at91_clk_register_sam9x5_peripheral(base, + &sama7d65_pcr_layout, + sama7d65_periphck[i].n, + sama7d65_periphck[i].p, + sama7d65_periphck[i].id, + &sama7d65_periphck[i].r)); + } + + /* Generic clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK1]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK1); + for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) { + for (j = 0; j < sama7d65_gck[i].ep_count; j++) { + p[4 + j] = sama7d65_gck[i].ep[j]; + m[4 + j] = sama7d65_gck[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_gck[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_gck[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_gck[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sama7d65_gck[i].id), + at91_clk_register_generic(base, &sama7d65_pcr_layout, + sama7d65_gck[i].n, p, + tmpclkmux, tmpmux, + 4 + sama7d65_gck[i].ep_count, + sama7d65_gck[i].id, + &sama7d65_gck[i].r)); + } + + /* Setup clocks. */ + ret = at91_clk_setup(sama7d65_clk_setup, ARRAY_SIZE(sama7d65_clk_setup)); + if (ret) + goto fail; + + return 0; + +fail: + for (i = 0; i < ARRAY_SIZE(muxallocs); i++) + kfree(muxallocs[i]); + + for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++) + kfree(clkmuxallocs[i]); + + return -ENOMEM; +} + +static const struct udevice_id sama7d65_clk_ids[] = { + { .compatible = "microchip,sama7d65-pmc" }, + { /* Sentinel. */ }, +}; + +U_BOOT_DRIVER(at91_sama7d65_pmc) = { + .name = "at91-sama7d65-pmc", + .id = UCLASS_CLK, + .of_match = sama7d65_clk_ids, + .ops = &at91_clk_ops, + .probe = sama7d65_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f44db76c182..1c1cc82719c 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -129,4 +129,18 @@ config CLK_SUN50I_A100 This enables common clock driver support for platforms based on Allwinner A100/A133 SoCs. +config CLK_SUN55I_A523 + bool "Clock driver for Allwinner A523/T527" + default MACH_SUN55I_A523 + help + This enables common clock driver support for platforms based + on Allwinner A523/T527 SoC. + +config CLK_SUN55I_A523_R + bool "Clock driver for Allwinner A523 generation PRCM" + default MACH_SUN55I_A523 + help + This enables common clock driver support for the PRCM + in Allwinner A523/T527 SoCs. + endif # CLK_SUNXI diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 7ff71c756e0..93b542cebcd 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -25,3 +25,5 @@ obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o +obj-$(CONFIG_CLK_SUN55I_A523) += clk_a523.o +obj-$(CONFIG_CLK_SUN55I_A523_R) += clk_a523_r.o diff --git a/drivers/clk/sunxi/clk_a523.c b/drivers/clk/sunxi/clk_a523.c new file mode 100644 index 00000000000..1de95fbaf2f --- /dev/null +++ b/drivers/clk/sunxi/clk_a523.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <clk/sunxi.h> +#include <linux/bitops.h> + +#include <dt-bindings/clock/sun55i-a523-ccu.h> +#include <dt-bindings/reset/sun55i-a523-ccu.h> + +static struct ccu_clk_gate a523_gates[] = { + [CLK_PLL_PERIPH0_200M] = GATE_DUMMY, + [CLK_APB1] = GATE_DUMMY, + + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_SPI0] = GATE(0x940, BIT(31)), + [CLK_SPI1] = GATE(0x944, BIT(31)), + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)), + + [CLK_EMAC0_25M] = GATE(0x970, BIT(30) | BIT(31)), + [CLK_EMAC1_25M] = GATE(0x974, BIT(30) | BIT(31)), + [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)), + [CLK_BUS_EMAC1] = GATE(0x98c, BIT(0)), + + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)), + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)), + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)), + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)), + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)), + [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)), + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)), +}; + +static struct ccu_reset a523_resets[] = { + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), + [RST_BUS_UART0] = RESET(0x90c, BIT(16)), + [RST_BUS_UART1] = RESET(0x90c, BIT(17)), + [RST_BUS_UART2] = RESET(0x90c, BIT(18)), + [RST_BUS_UART3] = RESET(0x90c, BIT(19)), + [RST_BUS_UART4] = RESET(0x90c, BIT(20)), + [RST_BUS_UART5] = RESET(0x90c, BIT(21)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), + + [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)), + [RST_BUS_EMAC1] = RESET(0x98c, BIT(16) | BIT(17)), + + [RST_USB_PHY0] = RESET(0xa70, BIT(30)), + [RST_USB_PHY1] = RESET(0xa74, BIT(30)), + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)), + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)), + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)), + [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)), + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)), +}; + +const struct ccu_desc a523_ccu_desc = { + .gates = a523_gates, + .resets = a523_resets, + .num_gates = ARRAY_SIZE(a523_gates), + .num_resets = ARRAY_SIZE(a523_resets), +}; diff --git a/drivers/clk/sunxi/clk_a523_r.c b/drivers/clk/sunxi/clk_a523_r.c new file mode 100644 index 00000000000..01e613d20aa --- /dev/null +++ b/drivers/clk/sunxi/clk_a523_r.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <clk/sunxi.h> +#include <dt-bindings/clock/sun55i-a523-r-ccu.h> +#include <dt-bindings/reset/sun55i-a523-r-ccu.h> +#include <linux/bitops.h> + +static struct ccu_clk_gate a523_r_gates[] = { + [CLK_R_AHB] = GATE_DUMMY, + [CLK_R_APB0] = GATE_DUMMY, + [CLK_R_APB1] = GATE_DUMMY, + [CLK_BUS_R_TWD] = GATE(0x12c, BIT(0)), + [CLK_BUS_R_I2C0] = GATE(0x19c, BIT(0)), + [CLK_BUS_R_I2C1] = GATE(0x19c, BIT(1)), + [CLK_BUS_R_I2C2] = GATE(0x19c, BIT(2)), + [CLK_BUS_R_RTC] = GATE(0x20c, BIT(0)), +}; + +static struct ccu_reset a523_r_resets[] = { + [RST_BUS_R_TWD] = RESET(0x12c, BIT(16)), + [RST_BUS_R_UART0] = RESET(0x18c, BIT(16)), + [RST_BUS_R_I2C0] = RESET(0x19c, BIT(16)), + [RST_BUS_R_I2C1] = RESET(0x19c, BIT(17)), + [RST_BUS_R_I2C2] = RESET(0x19c, BIT(18)), + [RST_BUS_R_PPU1] = RESET(0x1ac, BIT(17)), + [RST_BUS_R_RTC] = RESET(0x20c, BIT(16)), +}; + +const struct ccu_desc a523_r_ccu_desc = { + .gates = a523_r_gates, + .resets = a523_r_resets, + .num_gates = ARRAY_SIZE(a523_r_gates), + .num_resets = ARRAY_SIZE(a523_r_resets), +}; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index e0765cbc6dc..842a0541bd6 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -126,6 +126,8 @@ extern const struct ccu_desc a100_ccu_desc; extern const struct ccu_desc h6_r_ccu_desc; extern const struct ccu_desc r40_ccu_desc; extern const struct ccu_desc v3s_ccu_desc; +extern const struct ccu_desc a523_ccu_desc; +extern const struct ccu_desc a523_r_ccu_desc; static const struct udevice_id sunxi_clk_ids[] = { #ifdef CONFIG_CLK_SUN4I_A10 @@ -224,6 +226,14 @@ static const struct udevice_id sunxi_clk_ids[] = { { .compatible = "allwinner,suniv-f1c100s-ccu", .data = (ulong)&f1c100s_ccu_desc }, #endif +#ifdef CONFIG_CLK_SUN55I_A523 + { .compatible = "allwinner,sun55i-a523-ccu", + .data = (ulong)&a523_ccu_desc }, +#endif +#ifdef CONFIG_CLK_SUN55I_A523_R + { .compatible = "allwinner,sun55i-a523-r-ccu", + .data = (ulong)&a523_r_ccu_desc }, +#endif { } }; diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index ce5e61bbaa6..5365ac68f9e 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -261,17 +261,14 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) return 0; } -int uclass_find_next_device(struct udevice **devp) +void uclass_find_next_device(struct udevice **devp) { struct udevice *dev = *devp; *devp = NULL; - if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) - return 0; - - *devp = list_entry(dev->uclass_node.next, struct udevice, uclass_node); - - return 0; + if (!list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) + *devp = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); } int uclass_find_device_by_namelen(enum uclass_id id, const char *name, int len, @@ -675,11 +672,8 @@ int uclass_first_device_check(enum uclass_id id, struct udevice **devp) int uclass_next_device_check(struct udevice **devp) { - int ret; + uclass_find_next_device(devp); - ret = uclass_find_next_device(devp); - if (ret) - return ret; if (!*devp) return 0; diff --git a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c index 31b6209416b..84156a1e8ad 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c +++ b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c @@ -64,7 +64,7 @@ static u8 center_high_element_get(u8 dir, u8 pbs_element, u16 lambda, u8 pbs_max static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*copt)[MAX_BUS_NUM], u8 (*pbs_result)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*vw_size)[MAX_BUS_NUM], u8 mode, u16 param0, u8 param1); -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs); +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs); static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_result, u8 *copt); static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v, u8 vw_num, u8 *v_opt, u8 *t_opt); @@ -659,7 +659,7 @@ static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WID } /* if_id */ /* restore cs enable value*/ - for (if_id = 0; if_id < MAX_INTERFACE_NUM - 1; if_id++) { + for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, cs_ena_reg_val[if_id], MASK_ALL_BITS); @@ -895,7 +895,7 @@ static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_res * It provides with a solution for a single subphy (8 bits). * The calling function is responsible for any additional pbs taps for dqs */ -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs) +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs) { u8 dq_idx; u32 pbs_max_val = 0; @@ -952,7 +952,8 @@ static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 m int t_opt_temp = 0, v_opt_temp = 0; int vw_avg = 0, v_avg = 0; int s0 = 0, s1 = 0, s2 = 0, slope = 1, r_sq = 0; - u32 d_min = 10000, reg_val = 0; + u32 reg_val = 0; + int d_min = 10000; int status; /* @@ -2189,7 +2190,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI for (dq = 0; dq < BUS_WIDTH_IN_BITS; dq++) { idx = dq + subphy * BUS_WIDTH_IN_BITS; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; @@ -2267,7 +2268,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI idx = dq + subphy * BUS_WIDTH_IN_BITS; pad = dq_map_table[idx]; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 70207573de2..843171902ae 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -91,7 +91,7 @@ config FASTBOOT_USB_DEV config FASTBOOT_FLASH bool "Enable FASTBOOT FLASH command" default y if ARCH_SUNXI || ARCH_ROCKCHIP - depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) + depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) || DM_SPI_FLASH select IMAGE_SPARSE help The fastboot protocol includes a "flash" command for writing @@ -119,6 +119,10 @@ config FASTBOOT_FLASH_NAND bool "FASTBOOT on NAND" depends on MTD_RAW_NAND && CMD_MTDPARTS +config FASTBOOT_FLASH_SPI + bool "FASTBOOT on SPI flash" + depends on DM_SPI_FLASH + endchoice config FASTBOOT_FLASH_MMC_DEV diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index 048af5aa823..adedba0bf24 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -5,3 +5,4 @@ obj-y += fb_getvar.o obj-y += fb_command.o obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o +obj-$(CONFIG_FASTBOOT_FLASH_SPI) += fb_spi_flash.o diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 2cdbac50ac4..791088bc094 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -10,6 +10,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <part.h> #include <stdlib.h> #include <vsprintf.h> @@ -344,6 +345,10 @@ static void __maybe_unused flash(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_write(cmd_parameter, fastboot_buf_addr, + image_size, response); } /** @@ -362,6 +367,9 @@ static void __maybe_unused erase(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_erase(cmd_parameter, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_erase(cmd_parameter, response); } /** @@ -405,7 +413,7 @@ static void __maybe_unused run_acmd(char *cmd_parameter, char *response) return; } - if (strlen(cmd_parameter) > sizeof(g_a_cmd_buff)) { + if (strlen(cmd_parameter) >= sizeof(g_a_cmd_buff)) { pr_err("too long command\n"); fastboot_fail("too long command", response); return; diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 9c2ce65a4e5..6775ea397ab 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -8,6 +8,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <fs.h> #include <part.h> #include <version.h> @@ -123,6 +124,11 @@ static int getvar_get_part_info(const char *part_name, char *response, r = fastboot_nand_get_part_info(part_name, &part_info, response); if (r >= 0 && size) *size = part_info->size; + } else if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) { + r = fastboot_spi_flash_get_part_info(part_name, &disk_part, + response); + if (r >= 0 && size) + *size = disk_part.size * disk_part.blksz; } else { fastboot_fail("this storage is not supported in bootloader", response); r = -ENODEV; diff --git a/drivers/fastboot/fb_spi_flash.c b/drivers/fastboot/fb_spi_flash.c new file mode 100644 index 00000000000..691be7c7ef7 --- /dev/null +++ b/drivers/fastboot/fb_spi_flash.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Collabora Ltd. + */ + +#include <blk.h> +#include <config.h> +#include <env.h> +#include <fastboot.h> +#include <image-sparse.h> +#include <spi.h> +#include <spi_flash.h> +#include <dm.h> +#include <dm/device-internal.h> + +static struct spi_flash *flash; + +__weak int board_fastboot_spi_flash_write_setup(void) +{ + return 0; +} + +__weak int board_fastboot_spi_flash_erase_setup(void) +{ + return 0; +} + +static int raw_part_get_info_by_name(const char *name, + struct disk_partition *part_info) +{ + /* strlen("fastboot_raw_partition_") + PART_NAME_LEN + 1 */ + char env_desc_name[23 + PART_NAME_LEN + 1]; + char *raw_part_desc; + const char *argv[2]; + const char **parg = argv; + + /* check for raw partition descriptor */ + strcpy(env_desc_name, "fastboot_raw_partition_"); + strlcat(env_desc_name, name, sizeof(env_desc_name)); + raw_part_desc = strdup(env_get(env_desc_name)); + if (!raw_part_desc) + return -ENODEV; + + /* parse partition descriptor: <start> <size> */ + for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) { + *parg = strsep(&raw_part_desc, " "); + if (!*parg) { + pr_err("Invalid number of arguments.\n"); + return -ENODEV; + } + } + + part_info->start = simple_strtoul(argv[0], NULL, 0); + part_info->size = simple_strtoul(argv[1], NULL, 0); + strlcpy((char *)part_info->name, name, PART_NAME_LEN); + + return 0; +} + +static int fastboot_spi_flash_probe(void) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + struct udevice *new, *bus_dev; + int ret; + + /* Remove the old device, otherwise probe will just be a nop */ + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); + if (!ret) + device_remove(new, DM_REMOVE_NORMAL); + + spi_flash_probe_bus_cs(bus, cs, &new); + flash = dev_get_uclass_priv(new); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + return 0; +} + +static int fastboot_spi_flash_unlock(struct spi_flash *flash, + struct disk_partition *part_info) +{ + int ret = spi_flash_protect(flash, part_info->start, part_info->size, + false); + + if (ret && ret != -EOPNOTSUPP) { + printf("Failed to unlock SPI flash (%d)\n", ret); + return ret; + } + + return 0; +} + +static lbaint_t fb_spi_flash_sparse_write(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, + const void *buffer) +{ + size_t len = blkcnt * info->blksz; + u32 offset = blk * info->blksz; + int ret; + + ret = spi_flash_erase(flash, offset, ROUND(len, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase sparse chunk (%d)\n", ret); + return ret; + } + + ret = spi_flash_write(flash, offset, len, buffer); + if (ret < 0) { + printf("Failed to write sparse chunk (%d)\n", ret); + return ret; + } + + return blkcnt; +} + +static lbaint_t fb_spi_flash_sparse_reserve(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt) +{ + return blkcnt; +} + +/** + * fastboot_spi_flash_get_part_info() - Lookup SPI partition by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + * Return: 0 if OK, -ENOENT if no partition name was given, -ENODEV on invalid + * raw partition descriptor + */ +int fastboot_spi_flash_get_part_info(const char *part_name, + struct disk_partition *part_info, + char *response) +{ + int ret; + + if (!part_name || !strcmp(part_name, "")) { + fastboot_fail("partition not given", response); + return -ENOENT; + } + + /* TODO: Support partitions on the device */ + ret = raw_part_get_info_by_name(part_name, part_info); + if (ret < 0) + fastboot_fail("invalid partition or device", response); + + return ret; +} + +/** + * fastboot_spi_flash_write() - Write image to SPI for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_write_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + if (is_sparse_image(download_buffer)) { + struct sparse_storage sparse; + + sparse.blksz = flash->sector_size; + sparse.start = part_info.start / sparse.blksz; + sparse.size = part_info.size / sparse.blksz; + sparse.write = fb_spi_flash_sparse_write; + sparse.reserve = fb_spi_flash_sparse_reserve; + sparse.mssg = fastboot_fail; + + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + ret = write_sparse_image(&sparse, cmd, download_buffer, + response); + } else { + printf("Flashing raw image at offset " LBAFU "\n", + part_info.start); + + ret = spi_flash_erase(flash, part_info.start, + ROUND(download_bytes, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase raw image (%d)\n", ret); + return; + } + ret = spi_flash_write(flash, part_info.start, download_bytes, + download_buffer); + if (ret < 0) { + printf("Failed to write raw image (%d)\n", ret); + return; + } + printf("........ wrote %u bytes\n", download_bytes); + } + + if (ret) + fastboot_fail("error writing the image", response); + else + fastboot_okay(NULL, response); +} + +/** + * fastboot_spi_flash_erase() - Erase SPI for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_erase(const char *cmd, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_erase_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + ret = spi_flash_erase(flash, part_info.start, part_info.size); + if (ret < 0) { + pr_err("failed erasing from SPI flash"); + fastboot_fail("failed erasing from SPI flash", response); + return; + } + + fastboot_okay(NULL, response); +} diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index d18ae523b6b..e07ec3929b2 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -500,11 +500,8 @@ static int zynqmp_firmware_bind(struct udevice *dev) if (!smc_call_handler) return -EINVAL; - if ((IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) || - (!IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) { + if (CONFIG_IS_ENABLED(POWER_DOMAIN) && + IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) { ret = device_bind_driver_to_node(dev, "zynqmp_power_domain", "zynqmp_power_domain", dev_ofnode(dev), &child); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3de9011ac06..e1514fc56d0 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -14,6 +14,7 @@ #include <log.h> #include <ACEX1K.h> /* ACEX device family */ #include <linux/delay.h> +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 62cb77b098c..9456ca3149a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -15,6 +15,7 @@ config FPGA_ALTERA config FPGA_SOCFPGA bool "Enable Gen5 and Arria10 common FPGA drivers" + depends on ARCH_SOCFPGA select FPGA_ALTERA help Say Y here to enable the Gen5 and Arria10 common FPGA driver diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index f88267e01b6..2297fefd149 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -16,20 +16,6 @@ static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; -/* - * fpga_no_sup - * 'no support' message function - */ -static void fpga_no_sup(char *fn, char *msg) -{ - if (fn && msg) - printf("%s: No support for %s.\n", fn, msg); - else if (msg) - printf("No support for %s.\n", msg); - else - printf("No FPGA support!\n"); -} - /* fpga_get_desc * map a device number to a descriptor */ @@ -39,8 +25,8 @@ const fpga_desc *fpga_get_desc(int devnum) if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; - debug("%s: found fpga descriptor #%d @ 0x%p\n", - __func__, devnum, desc); + log_debug("found fpga descriptor #%d @ 0x%p\n", + devnum, desc); } return desc; @@ -51,15 +37,15 @@ const fpga_desc *fpga_get_desc(int devnum) * generic parameter checking code */ const fpga_desc *fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) + size_t bsize) { const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) - printf("%s: Invalid device number %d\n", fn, devnum); + log_err("Invalid device number %d\n", devnum); if (!buf) { - printf("%s: Null buffer.\n", fn); + log_err("Null buffer.\n"); return NULL; } return desc; @@ -75,40 +61,40 @@ static int fpga_dev_info(int devnum) const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { - debug("%s: Device Descriptor @ 0x%p\n", - __func__, desc->devdesc); + log_info("Device Descriptor @ 0x%p\n", + desc->devdesc); switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); + log_info("Xilinx Device\nDescriptor @ 0x%p\n", desc); ret_val = xilinx_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - printf("Altera Device\nDescriptor @ 0x%p\n", desc); + log_info("Altera Device\nDescriptor @ 0x%p\n", desc); ret_val = altera_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) - printf("Lattice Device\nDescriptor @ 0x%p\n", desc); + log_info("Lattice Device\nDescriptor @ 0x%p\n", desc); ret_val = lattice_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } else { - printf("%s: Invalid device number %d\n", __func__, devnum); + log_err("Invalid device number %d\n", devnum); } return ret_val; @@ -144,23 +130,22 @@ int fpga_add(fpga_type devtype, void *desc) int devnum = FPGA_INVALID_DEVICE; if (!desc) { - printf("%s: NULL device descriptor\n", __func__); + log_err("NULL device descriptor\n"); return devnum; } if (next_desc < 0) { - printf("%s: FPGA support not initialized!\n", __func__); + log_err("FPGA support not initialized!\n"); } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { if (next_desc < CONFIG_MAX_FPGA_DEVICES) { devnum = next_desc; desc_table[next_desc].devtype = devtype; desc_table[next_desc++].devdesc = desc; } else { - printf("%s: Exceeded Max FPGA device count\n", - __func__); + log_err("Exceeded Max FPGA device count\n"); } } else { - printf("%s: Unsupported FPGA type %d\n", __func__, devtype); + log_err("Unsupported FPGA type %d\n", devtype); } return devnum; @@ -181,7 +166,7 @@ int __weak fpga_is_partial_data(int devnum, size_t img_len) int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype) { - printf("Bitstream support not implemented for this FPGA device\n"); + log_err("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } @@ -190,8 +175,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -200,12 +184,12 @@ int fpga_fsload(int devnum, const void *buf, size_t size, ret_val = xilinx_loadfs(desc->devdesc, buf, size, fpga_fsinfo); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -219,8 +203,7 @@ int fpga_loads(int devnum, const void *buf, size_t size, { int ret_val = FPGA_FAIL; - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -229,12 +212,12 @@ int fpga_loads(int devnum, const void *buf, size_t size, ret_val = xilinx_loads(desc->devdesc, buf, size, fpga_sec_info); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -265,8 +248,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, { int ret_val = FPGA_FAIL; /* assume failure */ int ret_notify; - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -275,26 +257,26 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, ret_val = xilinx_load(desc->devdesc, buf, bsize, bstype, flags); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -312,8 +294,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -321,26 +302,26 @@ int fpga_dump(int devnum, const void *buf, size_t bsize) #if defined(CONFIG_FPGA_XILINX) ret_val = xilinx_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -363,7 +344,7 @@ int fpga_info(int devnum) return FPGA_SUCCESS; } else { - printf("%s: No FPGA devices available.\n", __func__); + log_err("No FPGA devices available.\n"); return FPGA_FAIL; } } diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c index 3c9a01e5110..37d5c5ec9ec 100644 --- a/drivers/fpga/ivm_core.c +++ b/drivers/fpga/ivm_core.c @@ -33,6 +33,7 @@ #include <linux/string.h> #include <malloc.h> #include <lattice.h> +#include <vsprintf.h> #define vme_out_char(c) printf("%c", c) #define vme_out_hex(c) printf("%x", c) @@ -291,7 +292,7 @@ unsigned short g_usLVDSPairCount; */ static signed char ispVMDataCode(void); -static long int ispVMDataSize(void); +static long ispVMDataSize(void); static void ispVMData(unsigned char *Data); static signed char ispVMShift(signed char Code); static signed char ispVMAmble(signed char Code); @@ -589,7 +590,7 @@ void ispVMFreeMem(void) * */ -long int ispVMDataSize() +long ispVMDataSize(void) { /* 09/11/07 NN added local variables initialization */ long int iSize = 0; @@ -614,7 +615,7 @@ long int ispVMDataSize() * */ -signed char ispVMCode() +signed char ispVMCode(void) { /* 09/11/07 NN added local variables initialization */ unsigned short iRepeatSize = 0; @@ -1113,7 +1114,7 @@ signed char ispVMCode() * */ -signed char ispVMDataCode() +signed char ispVMDataCode(void) { /* 09/11/07 NN added local variables initialization */ signed char cDataByte = 0; @@ -2475,7 +2476,7 @@ void ispVMStateMachine(signed char cNextJTAGState) * */ -void ispVMStart() +void ispVMStart(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); @@ -2504,7 +2505,7 @@ void ispVMStart() * */ -void ispVMEnd() +void ispVMEnd(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index 3f481e38565..29cf2f60974 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -350,8 +350,8 @@ int lattice_info(Lattice_desc *desc) printf("Unsupported interface type, %d\n", desc->iface); } - printf("Device Size: \t%d bytes\n", - desc->size); + printf("Device Size: \t%zu bytes\n", + desc->size); if (desc->iface_fns) { printf("Device Function Table @ 0x%p\n", diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 906649ea181..792e4033428 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -9,6 +9,7 @@ #include <config.h> /* core U-Boot definitions */ #include <log.h> #include <spartan2.h> /* Spartan-II device family */ +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 73fecd9dca5..3f984385316 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -5,92 +5,41 @@ */ #include <altera.h> +#include <stratixII.h> #include <linux/delay.h> -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure); -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize); - /****************************************************************/ /* Stratix II Generic Implementation */ -int StratixII_load (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0); - break; - case fast_passive_parallel: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0); - break; - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1); - break; - - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - case fast_passive_parallel: - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_dump (desc, buf, bsize); - break; - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_info (Altera_desc * desc) -{ - return FPGA_SUCCESS; -} - -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) +int StratixII_ps_fpp_dump(Altera_desc *desc, const void *buf, size_t bsize) { - printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); + printf("Stratix II Fast Passive Parallel dump is not implemented\n"); return FPGA_FAIL; } -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure) +int StratixII_ps_fpp_load(Altera_desc *desc, const void *buf, size_t bsize, + int isSerial, int isSecure) { altera_board_specific_func *fns; int cookie; int ret_val = FPGA_FAIL; int bytecount; - char *buff = buf; + const char *buff = buf; int i; if (!desc) { - printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__); + log_err("Altera_desc missing\n"); return FPGA_FAIL; } if (!buff) { - printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__); + log_err("buffer is missing\n"); return FPGA_FAIL; } if (!bsize) { - printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__); + log_err("size is zero\n"); return FPGA_FAIL; } if (!desc->iface_fns) { - printf - ("%s(%d) Altera_desc function interface table is missing\n", - __FUNCTION__, __LINE__); + log_err("Altera_desc function interface table is missing\n"); return FPGA_FAIL; } fns = (altera_board_specific_func *) (desc->iface_fns); @@ -99,9 +48,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, if (! (fns->config && fns->status && fns->done && fns->data && fns->abort)) { - printf - ("%s(%d) Missing some function in the function interface table\n", - __FUNCTION__, __LINE__); + log_err("Missing some function in the function interface table\n"); return FPGA_FAIL; } @@ -124,13 +71,12 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, bytecount = 0; fns->clk (0, 1, cookie); - printf ("loading to fpga "); + printf("loading to fpga "); while (bytecount < bsize) { /* 3.1 check stratix has not signaled us an error */ if (fns->status (cookie) != 1) { - printf - ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n", - __FUNCTION__, __LINE__, bytecount); + log_err("\nStratix failed (byte transferred till failure 0x%x)\n", + bytecount); fns->abort (cookie); return FPGA_FAIL; } @@ -162,7 +108,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, /* 3.5 while clk is deasserted it is safe to print some progress indication */ if ((bytecount % (bsize / 100)) == 0) { - printf ("\b\b\b%02d\%", bytecount * 100 / bsize); + printf("\b\b\b%02zu\%%", bytecount * 100 / bsize); } } @@ -170,11 +116,11 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, fns->clk (1, 1, cookie); udelay(100); if (!fns->done (cookie)) { - printf (" error!.\n"); + printf(" error!.\n"); fns->abort (cookie); return FPGA_FAIL; } else { - printf ("\b\b\b done.\n"); + printf("\b\b\b done.\n"); } /* 5. call lower layer post configuration */ @@ -187,3 +133,47 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, return FPGA_SUCCESS; } + +int StratixII_load(Altera_desc *desc, const void *buf, size_t size) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 1, 0); + break; + case fast_passive_parallel: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 0); + break; + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 1); + break; + + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + case fast_passive_parallel: + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_dump(desc, buf, bsize); + break; + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_info(Altera_desc *desc) +{ + return FPGA_SUCCESS; +} diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c index 372f16d92d1..4b251994598 100644 --- a/drivers/fpga/stratixv.c +++ b/drivers/fpga/stratixv.c @@ -48,7 +48,7 @@ int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) int spi_dev; int ret = 0; - if ((u32)rbf_data & 0x3) { + if ((size_t)rbf_data & 0x3) { puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); return -EINVAL; } diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d691f135e89..624493ad838 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -6,7 +6,6 @@ #include <cpu_func.h> #include <log.h> -#include <asm/arch/sys_proto.h> #include <memalign.h> #include <versalpl.h> #include <zynqmp_firmware.h> diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8e2c12bb58b..805cbac8082 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -19,6 +19,7 @@ #include <log.h> #include <virtex2.h> #include <linux/delay.h> +#include <time.h> /* * If the SelectMap interface can be overrun by the processor, enable @@ -301,6 +302,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) size_t bytecount = 0; unsigned char *data = (unsigned char *)buf; int cookie = desc->cookie; + unsigned long ts; ret_val = virtex2_slave_pre(fn, cookie); if (ret_val != FPGA_SUCCESS) diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c46513226d9..28c68faba55 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -49,7 +49,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ - desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); + desc = fpga_validate(devnum, dataptr, 0); /* Assign xilinx device description */ xdesc = desc->devdesc; diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2b62bbbe3cf..1199b249e36 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -191,8 +191,8 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((ulong)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%px)\n", - __func__, buf); + log_err("Bitstream has to be placed above 1MB (%px)\n", + buf); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 3e86d854a01..5a37a33b0a7 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -360,8 +360,8 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); + log_err("Bitstream has to be placed above 1MB (%x)\n", + (u32)buf); return FPGA_FAIL; } diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 7db58c70663..ef4f33f84e9 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -184,6 +184,7 @@ static const struct zynq_platform_data zynq_gpio_def = { * pin * @bank_pin_num: an output parameter used to return pin number within a bank * for the given gpio pin + * @dev: Pointer to our device structure. * * Returns the bank number and pin offset within the bank. */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 775b2b4e9af..108b24b3dd2 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -181,6 +181,7 @@ config SYS_I2C_IPROC config SYS_I2C_FSL bool "Freescale I2C bus driver" + depends on M68K || PPC help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -240,7 +241,7 @@ config SYS_I2C_DW config SYS_I2C_DW_PCI bool "Designware PCI I2C Controller" - depends on SYS_I2C_DW && PCI && ACPIGEN + depends on SYS_I2C_DW && PCI && ACPIGEN && X86 default y help Say yes here to select the Designware PCI I2C Host Controller. @@ -277,6 +278,7 @@ config SYS_I2C_INTEL config SYS_I2C_IMX_LPI2C bool "NXP i.MX LPI2C driver" + depends on MACH_IMX help Add support for the NXP i.MX LPI2C driver. @@ -314,6 +316,7 @@ config SYS_I2C_MICROCHIP config SYS_I2C_MXC bool "NXP MXC I2C driver" + depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || MACH_IMX help Add support for the NXP I2C driver. This supports up to four bus channels and operating on standard mode up to 100 kbits/s and fast @@ -485,7 +488,7 @@ endif config SYS_I2C_NEXELL bool "Nexell I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_NEXELL help Add support for the Nexell I2C driver. This is used with various Nexell parts such as S5Pxx18 series SoCs. All chips @@ -494,6 +497,7 @@ config SYS_I2C_NEXELL config SYS_I2C_NPCM bool "Nuvoton NPCM I2C driver" + depends on ARCH_NPCM help Support for Nuvoton I2C controller driver. @@ -533,7 +537,7 @@ config SYS_I2C_RCAR_IIC config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_ROCKCHIP help Add support for the Rockchip I2C driver. This is used with various Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips @@ -751,6 +755,7 @@ config SYS_I2C_MV config SYS_I2C_MVTWSI bool "Marvell I2C driver" + depends on ARCH_KIRKWOOD || ARCH_MVEBU || ARCH_SUNXI help Support for Marvell I2C controllers as used on the orion5x and kirkwood SoC families. diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c index 6570f64fe77..8f94dfe117e 100644 --- a/drivers/i2c/iproc_i2c.c +++ b/drivers/i2c/iproc_i2c.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <config.h> #include <dm.h> +#include <linux/delay.h> #include <linux/printk.h> #include "errno.h" #include <i2c.h> diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index cd5579aa55a..65319bb6fd8 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -25,6 +25,13 @@ config I2C_ARB_GPIO_CHALLENGE response mechanism where masters have to claim the bus by asserting a GPIO. +config I2C_MUX_PCA9541 + tristate "NXP PCA9541 I2C Master Selector" + depends on I2C_MUX + help + If you say yes here you get support for the NXP PCA9541 + I2C Master Selector. + config I2C_MUX_PCA954x tristate "TI PCA954x I2C Mux/switches" depends on I2C_MUX diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index b690821199f..844d4520e43 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -3,5 +3,6 @@ # Copyright (c) 2015 Google, Inc obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o +obj-$(CONFIG_I2C_MUX_PCA9541) += pca9541.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o diff --git a/drivers/i2c/muxes/pca9541.c b/drivers/i2c/muxes/pca9541.c new file mode 100644 index 00000000000..021088acaee --- /dev/null +++ b/drivers/i2c/muxes/pca9541.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it> + * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it> + * Copyright (c) 2010 Ericsson AB. + * Copyright (c) 2025 Advanced Micro Devices, Inc. + */ + +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <log.h> +#include <malloc.h> +#include <linux/delay.h> + +/* + * The PCA9541 is a bus master selector. It supports two I2C masters connected + * to a single slave bus. + * + * Before each bus transaction, a master has to acquire bus ownership. After the + * transaction is complete, bus ownership has to be released. This fits well + * into the I2C multiplexer framework, which provides select and release + * functions for this purpose. For this reason, this driver is modeled as + * single-channel I2C bus multiplexer. + * + * This driver assumes that the two bus masters are controlled by two different + * hosts. If a single host controls both masters, platform code has to ensure + * that only one of the masters is instantiated at any given time. + */ + +#define PCA9541_CONTROL 0x01 +#define PCA9541_ISTAT 0x02 + +#define PCA9541_CTL_MYBUS BIT(0) +#define PCA9541_CTL_NMYBUS BIT(1) +#define PCA9541_CTL_BUSON BIT(2) +#define PCA9541_CTL_NBUSON BIT(3) +#define PCA9541_CTL_BUSINIT BIT(4) +#define PCA9541_CTL_TESTON BIT(6) +#define PCA9541_CTL_NTESTON BIT(7) + +#define PCA9541_ISTAT_INTIN BIT(0) +#define PCA9541_ISTAT_BUSINIT BIT(1) +#define PCA9541_ISTAT_BUSOK BIT(2) +#define PCA9541_ISTAT_BUSLOST BIT(3) +#define PCA9541_ISTAT_MYTEST BIT(6) +#define PCA9541_ISTAT_NMYTEST BIT(7) + +#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON) +#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS) + +/* arbitration timeouts, in jiffies */ +#define ARB_TIMEOUT_US 125000 /* 125 ms until forcing bus ownership */ +#define ARB2_TIMEOUT_US 250000 /* 250 ms until acquisition failure */ + +/* arbitration retry delays, in us */ +#define SELECT_DELAY_SHORT 50 +#define SELECT_DELAY_LONG 1000 + +struct pca9541_plat { + u32 addr; +}; + +struct pca9541_priv { + u32 addr; + unsigned long select_timeout; + long arb_timeout; +}; + +static inline int mybus(int x) +{ + return !(x & MYBUS) || ((x & MYBUS) == MYBUS); +} + +static inline int busoff(int x) +{ + return !(x & BUSON) || ((x & BUSON) == BUSON); +} + +static int pca9541_reg_write(struct udevice *mux, struct pca9541_priv *client, + u8 command, u8 val) +{ + return dm_i2c_write(mux, command, &val, 1); +} + +static int pca9541_reg_read(struct udevice *mux, struct pca9541_priv *client, + u8 command) +{ + int ret; + uchar byte; + + ret = dm_i2c_read(mux, command, &byte, 1); + + return ret ?: byte; +} + +/* + * Arbitration management functions + */ + +/* Release bus. Also reset NTESTON and BUSINIT if it was set. */ +static void pca9541_release_bus(struct udevice *mux, struct pca9541_priv *client) +{ + int reg; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg >= 0 && !busoff(reg) && mybus(reg)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + (reg & PCA9541_CTL_NBUSON) >> 1); +} + +/* + * Arbitration is defined as a two-step process. A bus master can only activate + * the slave bus if it owns it; otherwise it has to request ownership first. + * This multi-step process ensures that access contention is resolved + * gracefully. + * + * Bus Ownership Other master Action + * state requested access + * ---------------------------------------------------- + * off - yes wait for arbitration timeout or + * for other master to drop request + * off no no take ownership + * off yes no turn on bus + * on yes - done + * on no - wait for arbitration timeout or + * for other master to release bus + * + * The main contention point occurs if the slave bus is off and both masters + * request ownership at the same time. In this case, one master will turn on + * the slave bus, believing that it owns it. The other master will request + * bus ownership. Result is that the bus is turned on, and master which did + * _not_ own the slave bus before ends up owning it. + */ + +/* Control commands per PCA9541 datasheet */ +static const u8 pca9541_control[16] = { + 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1 +}; + +/* + * Channel arbitration + * + * Return values: + * <0: error + * 0 : bus not acquired + * 1 : bus acquired + */ +static int pca9541_arbitrate(struct udevice *mux, struct pca9541_priv *client) +{ + int reg, ret = 0; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg < 0) + return reg; + + if (busoff(reg)) { + int istat; + + /* + * Bus is off. Request ownership or turn it on unless + * other master requested ownership. + */ + istat = pca9541_reg_read(mux, client, PCA9541_ISTAT); + if (!(istat & PCA9541_ISTAT_NMYTEST) || + client->arb_timeout <= 0) { + /* + * Other master did not request ownership, + * or arbitration timeout expired. Take the bus. + */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_NTESTON); + client->select_timeout = SELECT_DELAY_SHORT; + } else { + /* + * Other master requested ownership. + * Set extra long timeout to give it time to acquire it. + */ + client->select_timeout = SELECT_DELAY_LONG * 2; + } + } else if (mybus(reg)) { + /* + * Bus is on, and we own it. We are done with acquisition. + * Reset NTESTON and BUSINIT, then return success. + */ + if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg & ~(PCA9541_CTL_NTESTON + | PCA9541_CTL_BUSINIT)); + ret = 1; + } else { + /* + * Other master owns the bus. + * If arbitration timeout has expired, force ownership. + * Otherwise request it. + */ + client->select_timeout = SELECT_DELAY_LONG; + if (client->arb_timeout <= 0) { + /* Time is up, take the bus and reset it. */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_BUSINIT + | PCA9541_CTL_NTESTON); + } else { + /* Request bus ownership if needed */ + if (!(reg & PCA9541_CTL_NTESTON)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg | PCA9541_CTL_NTESTON); + } + } + + return ret; +} + +static int pca9541_select_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + int ret; + long timeout = ARB2_TIMEOUT_US; /* Give up after this time */ + + /* Force bus ownership after this time */ + priv->arb_timeout = ARB_TIMEOUT_US; + do { + ret = pca9541_arbitrate(mux, priv); + if (ret) + return ret < 0 ? ret : 0; + + udelay(priv->select_timeout); + timeout -= priv->select_timeout; + priv->arb_timeout -= priv->select_timeout; + } while (timeout > 0); + + debug("I2C Arbitration select timeout\n"); + + return -ETIMEDOUT; +} + +static int pca9541_release_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + + pca9541_release_bus(mux, priv); + + return 0; +} + +/* + * I2C init/probing/exit functions + */ +static int pca9541_of_to_plat(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_u32_default(dev, "reg", 0); + if (!plat->addr) { + debug("Reg property is not found\n"); + return -ENODEV; + } + + debug("Device %s at 0x%x\n", dev->name, plat->addr); + + return 0; +} + +static int pca9541_probe(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + struct pca9541_priv *priv = dev_get_priv(dev); + + priv->addr = plat->addr; + + return 0; +} + +static const struct i2c_mux_ops pca9541_ops = { + .select = pca9541_select_chan, + .deselect = pca9541_release_chan, +}; + +static const struct udevice_id pca9541_ids[] = { + { .compatible = "nxp,pca9541", }, + { } +}; + +U_BOOT_DRIVER(pca9541) = { + .name = "pca9541", + .id = UCLASS_I2C_MUX, + .of_match = pca9541_ids, + .probe = pca9541_probe, + .ops = &pca9541_ops, + .of_to_plat = pca9541_of_to_plat, + .plat_auto = sizeof(struct pca9541_plat), + .priv_auto = sizeof(struct pca9541_priv), +}; diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 9dd26972703..d13947a0d9c 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -22,6 +22,7 @@ enum pca_type { MAX7369, PCA9543, PCA9544, + PCA9545, PCA9546, PCA9547, PCA9548, @@ -79,6 +80,10 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_ismux, .width = 4, }, + [PCA9545] = { + .muxtype = pca954x_isswi, + .width = 4, + }, [PCA9546] = { .muxtype = pca954x_isswi, .width = 4, @@ -141,6 +146,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "maxim,max7369", .data = MAX7369 }, { .compatible = "nxp,pca9543", .data = PCA9543 }, { .compatible = "nxp,pca9544", .data = PCA9544 }, + { .compatible = "nxp,pca9545", .data = PCA9545 }, { .compatible = "nxp,pca9546", .data = PCA9546 }, { .compatible = "nxp,pca9547", .data = PCA9547 }, { .compatible = "nxp,pca9548", .data = PCA9548 }, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 966783e4b62..0f753b9dbb9 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -641,6 +641,14 @@ config ESM_K3 help Support ESM (Error Signaling Module) on TI K3 SoCs. +config K3_BIST + bool "Enable K3 BIST driver" + depends on ARCH_K3 + help + Support BIST (Built-In Self Test) module on TI K3 SoCs. This driver + supports running both PBIST (Memory BIST) and LBIST (Logic BIST) on + a region or IP in the SoC. + config MICROCHIP_FLEXCOM bool "Enable Microchip Flexcom driver" depends on MISC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 09dfd8072db..f7422c8e95a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o +obj-$(CONFIG_K3_BIST) += k3_bist.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o diff --git a/drivers/misc/k3_bist.c b/drivers/misc/k3_bist.c new file mode 100644 index 00000000000..3acb1a1ac1f --- /dev/null +++ b/drivers/misc/k3_bist.c @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Neha Malcom Francis <n-francis@ti.com> + * + */ + +#include <dm.h> +#include <errno.h> +#include <clk.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <asm/arch/hardware.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <remoteproc.h> +#include <power-domain.h> +#include <k3_bist.h> + +#include "k3_bist_static_data.h" + +/* PBIST Timeout Value */ +#define PBIST_MAX_TIMEOUT_VALUE 100000000 + +/** + * struct k3_bist_privdata - K3 BIST structure + * @dev: device pointer + * @pbist_base: base of register set for PBIST + * @instance: PBIST instance number + * @intr_num: corresponding interrupt ID of the PBIST instance + * @lbist_ctrl_mmr: base of CTRL MMR register set for LBIST + */ +struct k3_bist_privdata { + struct udevice *dev; + void *pbist_base; + u32 instance; + u32 intr_num; + void *lbist_ctrl_mmr; + struct pbist_inst_info *pbist_info; + struct lbist_inst_info *lbist_info; +}; + +static struct k3_bist_privdata *k3_bist_priv; + +/** + * check_post_pbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_pbist_result(void) +{ + bool is_done, timed_out; + u32 mask; + u32 post_reg_val, shift; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST PBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* HW POST: PBIST was completed on this device, check the result */ + mask = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK; + + if ((post_reg_val & mask) != 0) { + printf("%s: PBIST was completed, but the test failed\n", __func__); + return -EINVAL; + } + debug("%s: HW POST PBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * check_post_lbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_lbist_result(void) +{ + bool is_done, timed_out; + u32 post_reg_val, shift; + u32 calculated_misr, expected_misr; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST LBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* Get the output MISR and the expected MISR which 0 for MCU domain */ + lbist_get_misr((void *)MCU_LBIST_BASE, &calculated_misr); + expected_misr = readl(MCU_CTRL_MMR0_CFG0_BASE + MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG); + + if (calculated_misr != expected_misr) { + /* HW POST: LBIST was completed, but the test failed for this core */ + printf("%s: calculated MISR != expected MISR\n", __func__); + debug("%s: calculated MISR = %x\n", __func__, calculated_misr); + debug("%s: expected MISR = %x\n", __func__, expected_misr); + return -EINVAL; + } + debug("%s: HW POST LBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * pbist_self_test() - Run PBIST_TEST on specified cores + * @config: pbist_config structure for PBIST test + * + * Function to run PBIST_TEST + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_self_test(struct pbist_config *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set algorithm bitmap */ + writel(config->algorithms_bit_map, base + PBIST_ALGO); + + /* Set Memory group bitmap */ + writel(config->memory_groups_bit_map, base + PBIST_RINFO); + + /* Zero out override register */ + writel(config->override, base + PBIST_OVER); + + /* Set Scramble value - 64 bit*/ + writel(config->scramble_value_lo, base + PBIST_SCR_LO); + writel(config->scramble_value_hi, base + PBIST_SCR_HI); + + /* Set DLR register for ROM based testing and Config Access */ + writel(PBIST_DLR_DLR0_ROM_MASK + | PBIST_DLR_DLR0_CAM_MASK, base + PBIST_DLR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_neg_self_test() - Run PBIST_negTEST on specified cores + * @config: pbist_config_neg structure for PBIST negative test + * + * Function to run PBIST failure insertion test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_neg_self_test(struct pbist_config_neg *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_FAILURE_INSERTION_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x10, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x0513FC02, base + PBIST_RF1L); + writel(0x00000002, base + PBIST_RF1U); + writel(0x00000003, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x00000004, base + PBIST_RF3L); + writel(0x00000028, base + PBIST_RF3U); + writel(0x64000044, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + writel(0x0006A006, base + PBIST_RF5L); + writel(0x00000000, base + PBIST_RF5U); + writel(0x00000007, base + PBIST_RF6L); + writel(0x0000A0A0, base + PBIST_RF6U); + writel(0x00000008, base + PBIST_RF7L); + writel(0x00000064, base + PBIST_RF7U); + writel(0x00000009, base + PBIST_RF8L); + writel(0x0000A5A5, base + PBIST_RF8U); + writel(0x0000000A, base + PBIST_RF9L); + writel(0x00000079, base + PBIST_RF9U); + writel(0x00000000, base + PBIST_RF10L); + writel(0x00000001, base + PBIST_RF10U); + writel(0xAAAAAAAA, base + PBIST_D); + writel(0xAAAAAAAA, base + PBIST_E); + + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF) == 0) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_rom_self_test() - Run PBIST_ROM_TEST on specified cores + * @config: pbist_config_rom structure for PBIST negative test + * + * Function to run PBIST test of ROM + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_rom_self_test(struct pbist_config_rom *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(0x1, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(0xf, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x310, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x7A400183, base + PBIST_RF1L); + writel(0x00000060, base + PBIST_RF1U); + writel(0x00000184, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x7B600181, base + PBIST_RF3L); + writel(0x00000061, base + PBIST_RF3U); + writel(0x00000000, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + + writel(config->D, base + PBIST_D); + writel(config->E, base + PBIST_E); + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * lbist_program_config() - Program LBIST config + * @config: lbist_config structure for LBIST test + */ +static void lbist_program_config(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + + lbist_set_clock_delay(base, config->dc_def); + lbist_set_divide_ratio(base, config->divide_ratio); + lbist_clear_load_div(base); + lbist_set_load_div(base); + lbist_set_num_stuck_at_patterns(base, config->static_pc_def); + lbist_set_num_set_patterns(base, config->set_pc_def); + lbist_set_num_reset_patterns(base, config->reset_pc_def); + lbist_set_num_chain_test_patterns(base, config->scan_pc_def); + lbist_set_seed(base, config->prpg_def_l, config->prpg_def_u); +} + +/** + * lbist_enable_isolation() - LBIST Enable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_enable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val | (LBIST_SPARE0_LBIST_SELFTEST_EN_MASK), base + LBIST_SPARE0); +} + +/** + * lbist_disable_isolation() - LBIST Disable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_disable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val & (~(LBIST_SPARE0_LBIST_SELFTEST_EN_MASK)), base + LBIST_SPARE0); +} + +/** + * lbist_enable_run_bist_mode() - LBIST Enable run BIST mode + * @config: lbist_config structure for LBIST test + */ +static void lbist_enable_run_bist_mode(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT), + base + LBIST_CTRL); +} + +/** + * lbist_start() - Start LBIST test + * @config: lbist_config structure for LBIST test + */ +static void lbist_start(struct lbist_config *config) +{ + struct udevice *dev = k3_bist_priv->dev; + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + u32 timeout_count = 0; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_STAT); + if ((reg_val & LBIST_STAT_BIST_RUNNING_MASK) != 0) + debug("%s(dev=%p): LBIST is running\n", __func__, dev); + + while (((!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK))) && + (timeout_count++ < PBIST_MAX_TIMEOUT_VALUE)) { + } + + if (!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK)) + printf("%s(dev=%p): test failed\n", __func__, dev); +} + +/** + * lbist_check_result() - Check LBIST test result + * @config: lbist_config structure for LBIST test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int lbist_check_result(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + struct lbist_inst_info *info = k3_bist_priv->lbist_info; + u32 calculated_misr; + u32 expected_misr; + + lbist_get_misr(base, &calculated_misr); + expected_misr = info->expected_misr; + lbist_clear_run_bist_mode(base); + lbist_stop(base); + lbist_reset(base); + + if (calculated_misr != expected_misr) { + printf("calculated_misr != expected_misr\n %x %x\n", + calculated_misr, expected_misr); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist(void) +{ + /* Check whether HW POST successfully completely LBIST on the MCU domain */ + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + + lbist_program_config(&info_lbist->lbist_conf); + lbist_enable_isolation(); + lbist_reset(&info_lbist->lbist_conf); + lbist_enable_run_bist_mode(&info_lbist->lbist_conf); + lbist_start(&info_lbist->lbist_conf); + if (lbist_check_result(&info_lbist->lbist_conf)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist_post(void) +{ + if (check_post_lbist_result()) { + printf("HW POST LBIST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_post(void) +{ + /* Check whether HW POST successfully completely PBIST on the MCU domain */ + if (check_post_pbist_result()) { + printf("HW POST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist(void) +{ + /* Run PBIST test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_self_test(&info->pbist_config_run[j])) { + printf("failed to run PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +static int k3_run_pbist_neg(void) +{ + /* Run PBIST failure insertion test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + + if (pbist_neg_self_test(&info->pbist_neg_config_run)) { + printf("failed to run PBIST negative test\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_rom(void) +{ + /* Run PBIST test on ROM */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_rom_test_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_rom_self_test(&info->pbist_rom_test_config_run[j])) { + printf("failed to run ROM PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +int prepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (proc_ops->proc_request(handle, cut[0].proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_request(handle, cut[1].proc_id)) { + printf("%s: requesting secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0x1)) { + printf("%s: local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0x1)) { + printf("%s: local reset secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[0].dev_id)) { + printf("%s: power on primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[1].dev_id)) { + printf("%s: power on secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, info_pbist->dev_id)) { + printf("%s: power on PBIST failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (dev_ops->put_device(handle, info_pbist->dev_id)) { + printf("%s: power off PBIST failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0)) { + printf("%s: putting secondary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[0].proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[1].proc_id)) { + printf("%s: release secondary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int prepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (proc_ops->proc_request(handle, cut->proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0x3)) { + printf("%s: module and local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: putting primary core into retention failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + lbist_disable_isolation(); + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: retention primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, 0)) { + printf("%s: retention secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut->proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * k3_bist_probe() - Basic probe + * @dev: corresponding BIST device + * + * Parses BIST info from device tree, and configures the module accordingly. + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_bist_probe(struct udevice *dev) +{ + int ret = 0; + struct k3_bist_privdata *priv = dev_get_priv(dev); + struct pbist_inst_info *info; + struct lbist_inst_info *info_lbist; + void *reg; + + debug("%s(dev=%p)\n", __func__, dev); + + priv = dev_get_priv(dev); + priv->dev = dev; + + k3_bist_priv = priv; + + reg = dev_read_addr_name_ptr(dev, "cfg"); + if (!reg) { + dev_err(dev, "No reg property for BIST\n"); + return -EINVAL; + } + priv->pbist_base = reg; + + reg = dev_read_addr_name_ptr(dev, "ctrl_mmr"); + if (!reg) { + dev_err(dev, "No reg property for CTRL MMR\n"); + return -EINVAL; + } + priv->lbist_ctrl_mmr = reg; + + ret = dev_read_u32(dev, "ti,sci-dev-id", &priv->instance); + if (!priv->instance) + return -ENODEV; + + switch (priv->instance) { + case PBIST14_DEV_ID: + priv->pbist_info = &pbist14_inst_info; + priv->lbist_info = &lbist_inst_info_main_r5f2_x; + info = priv->pbist_info; + info_lbist = priv->lbist_info; + priv->intr_num = info->intr_num; + break; + default: + dev_err(dev, "%s: PBIST instance %d not supported\n", __func__, priv->instance); + return -ENODEV; + }; + + return 0; +} + +static const struct bist_ops k3_bist_ops = { + .run_lbist = k3_run_lbist, + .run_lbist_post = k3_run_lbist_post, + .run_pbist = k3_run_pbist, + .run_pbist_post = k3_run_pbist_post, + .run_pbist_neg = k3_run_pbist_neg, + .run_pbist_rom = k3_run_pbist_rom, +}; + +static const struct udevice_id k3_bist_ids[] = { + { .compatible = "ti,j784s4-bist" }, + {} +}; + +U_BOOT_DRIVER(k3_bist) = { + .name = "k3_bist", + .of_match = k3_bist_ids, + .id = UCLASS_MISC, + .ops = &k3_bist_ops, + .probe = k3_bist_probe, + .priv_auto = sizeof(struct k3_bist_privdata), +}; diff --git a/drivers/misc/k3_bist_static_data.h b/drivers/misc/k3_bist_static_data.h new file mode 100644 index 00000000000..af371d83724 --- /dev/null +++ b/drivers/misc/k3_bist_static_data.h @@ -0,0 +1,673 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __K3_BIST_STATIC_DATA_H +#define __K3_BIST_STATIC_DATA_H + +/* + * Registers and functions related to PBIST + */ + +#define PBIST_MAX_NUM_RUNS 2 +#define NUM_MAX_PBIST_TEST_ROM_RUNS 13 +#define PBIST14_DFT_PBIST_CPU_0_INTR_NUM 311 + +/* VIM Registers */ +#define VIM_STS_BASE 0x40f80404 +#define VIM_RAW_BASE 0x40f80400 + +#define VIM_STS(i) (VIM_STS_BASE + (i) / 32 * 0x20) +#define VIM_RAW(i) (VIM_RAW_BASE + (i) / 32 * 0x20) +#define VIM_RAW_MASK(i) (BIT((i) % 32)) + +/* PBIST Registers and Flags*/ +#define PBIST_RF0L 0x00000000 +#define PBIST_RF1L 0x00000004 +#define PBIST_RF2L 0x00000008 +#define PBIST_RF3L 0x0000000C +#define PBIST_RF4L 0x0000010 +#define PBIST_RF5L 0x0000014 +#define PBIST_RF6L 0x0000018 +#define PBIST_RF7L 0x000001C +#define PBIST_RF8L 0x0000020 +#define PBIST_RF9L 0x0000024 +#define PBIST_RF10L 0x0000028 +#define PBIST_RF11L 0x000002C +#define PBIST_RF12L 0x0000030 +#define PBIST_RF13L 0x0000034 +#define PBIST_RF14L 0x0000038 +#define PBIST_RF15L 0x000003C +#define PBIST_RF0U 0x0000040 +#define PBIST_RF1U 0x0000044 +#define PBIST_RF2U 0x0000048 +#define PBIST_RF3U 0x000004C +#define PBIST_RF4U 0x0000050 +#define PBIST_RF5U 0x0000054 +#define PBIST_RF6U 0x0000058 +#define PBIST_RF7U 0x000005C +#define PBIST_RF8U 0x0000060 +#define PBIST_RF9U 0x0000064 +#define PBIST_RF10U 0x0000068 +#define PBIST_RF11U 0x000006C +#define PBIST_RF12U 0x0000070 +#define PBIST_RF13U 0x0000074 +#define PBIST_RF14U 0x0000078 +#define PBIST_RF15U 0x000007C +#define PBIST_A0 0x0000100 +#define PBIST_A1 0x0000104 +#define PBIST_A2 0x0000108 +#define PBIST_A3 0x000010C +#define PBIST_L0 0x0000110 +#define PBIST_L1 0x0000114 +#define PBIST_L2 0x0000118 +#define PBIST_L3 0x000011C +#define PBIST_D 0x0000120 +#define PBIST_E 0x0000124 +#define PBIST_CA0 0x0000130 +#define PBIST_CA1 0x0000134 +#define PBIST_CA2 0x0000138 +#define PBIST_CA3 0x000013C +#define PBIST_CL0 0x0000140 +#define PBIST_CL1 0x0000144 +#define PBIST_CL2 0x0000148 +#define PBIST_CL3 0x000014C +#define PBIST_I0 0x0000150 +#define PBIST_I1 0x0000154 +#define PBIST_I2 0x0000158 +#define PBIST_I3 0x000015C +#define PBIST_RAMT 0x0000160 +#define PBIST_DLR 0x0000164 +#define PBIST_CMS 0x0000168 +#define PBIST_STR 0x000016C +#define PBIST_SCR 0x0000170 +#define PBIST_SCR_LO 0x0000170 +#define PBIST_SCR_HI 0x0000174 +#define PBIST_CSR 0x0000178 +#define PBIST_FDLY 0x000017C +#define PBIST_PACT 0x0000180 +#define PBIST_PID 0x0000184 +#define PBIST_OVER 0x0000188 +#define PBIST_FSRF 0x0000190 +#define PBIST_FSRC 0x0000198 +#define PBIST_FSRA 0x00001A0 +#define PBIST_FSRDL0 0x00001A8 +#define PBIST_FSRDL1 0x00001B0 +#define PBIST_MARGIN_MODE 0x00001B4 +#define PBIST_WRENZ 0x00001B8 +#define PBIST_PAGE_PGS 0x00001BC +#define PBIST_ROM 0x00001C0 +#define PBIST_ALGO 0x00001C4 +#define PBIST_RINFO 0x00001C8 + +#define PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK 0x00000003 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT 0x00000002 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK 0x0000000C +#define PBIST_PACT_PACT_MASK 0x00000001 +#define PBIST_DLR_DLR0_ROM_MASK 0x00000004 +#define PBIST_DLR_DLR0_CAM_MASK 0x00000010 +#define PBIST_NOT_DONE 0 +#define PBIST_DONE 1 + +/* PBIST test mode */ +#define PBIST_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | (1 << PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT)) + +/* PBIST Failure Insertion test mode */ +#define PBIST_FAILURE_INSERTION_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK) + +/** + * struct core_under_test - structure for a core under a BIST test + * @dev_id: Device ID of the core + * @proc_id: Processor ID of the core + */ +struct core_under_test { + u32 dev_id; + u32 proc_id; +}; + +/* + * struct pbist_config - Structure for different configuration used for PBIST + * @override: Override value for memory configuration + * @algorithms_bit_map: Bitmap to select algorithms to use for test + * @memory_groups_bit_map: Bitmap to select memory groups to run test on + * @scramble_value_lo: Lower scramble value to be used for test + * @scramble_value_hi: Higher scramble value to be used for test + */ +struct pbist_config { + u32 override; + u32 algorithms_bit_map; + u64 memory_groups_bit_map; + u32 scramble_value_lo; + u32 scramble_value_hi; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * for the failure insertion test to generate negative result + * @CA0: Failure insertion value for CA0 + * @CA1: Failure insertion value for CA1 + * @CA2: Failure insertion value for CA2 + * @CA3: Failure insertion value for CA3 + * @CL0: Failure insertion value for CL0 + * @CL1: Failure insertion value for CL1 + * @CL2: Failure insertion value for CL2 + * @CL3: Failure insertion value for CL3 + * @CMS: Failure insertion value for CMS + * @CSR: Failure insertion value for CSR + * @I0: Failure insertion value for I0 + * @I1: Failure insertion value for I1 + * @I2: Failure insertion value for I2 + * @I3: Failure insertion value for I3 + * @RAMT: Failure insertion value for RAMT + */ +struct pbist_config_neg { + u32 CA0; + u32 CA1; + u32 CA2; + u32 CA3; + u32 CL0; + u32 CL1; + u32 CL2; + u32 CL3; + u32 CMS; + u32 CSR; + u32 I0; + u32 I1; + u32 I2; + u32 I3; + u32 RAMT; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * test of ROM + * @D: ROM test value for D + * @E: ROM test value for E + * @CA2: ROM test value for CA2 + * @CL0: ROM test value for CL0 + * @CA3: ROM test value for CA3 + * @I0: ROM test value for I0 + * @CL1: ROM test value for CL1 + * @I3: ROM test value for I3 + * @I2: ROM test value for I2 + * @CL2: ROM test value for CL2 + * @CA1: ROM test value for CA1 + * @CA0: ROM test value for CA0 + * @CL3: ROM test value for CL3 + * @I1: ROM test value for I1 + * @RAMT: ROM test value for RAMT + * @CSR: ROM test value for CSR + * @CMS: ROM test value for CMS + */ +struct pbist_config_rom { + u32 D; + u32 E; + u32 CA2; + u32 CL0; + u32 CA3; + u32 I0; + u32 CL1; + u32 I3; + u32 I2; + u32 CL2; + u32 CA1; + u32 CA0; + u32 CL3; + u32 I1; + u32 RAMT; + u32 CSR; + u32 CMS; +}; + +/* + * struct pbist_inst_info - Structure for different configuration used for PBIST + * @num_pbist_runs: Number of runs of PBIST test + * @intr_num: Interrupt number triggered by this PBIST instance to MCU R5 VIM + * @pbist_config_run: Configuration for PBIST test + * @pbist_neg_config_run: Configuration for PBIST negative test + * @num_pbist_rom_test_runs: Number of runs of PBIST test on ROM + * @pbist_rom_test_config_run: Configuration for PBIST test on ROM + */ +struct pbist_inst_info { + u32 num_pbist_runs; + u32 intr_num; + u32 dev_id; + struct core_under_test cut[2]; + struct pbist_config pbist_config_run[PBIST_MAX_NUM_RUNS]; + struct pbist_config_neg pbist_neg_config_run; + u32 num_pbist_rom_test_runs; + struct pbist_config_rom pbist_rom_test_config_run[NUM_MAX_PBIST_TEST_ROM_RUNS]; +}; + +/* + * Registers and functions related to LBIST + */ + +#define LBIST_CTRL_DIVIDE_RATIO_MASK 0x0000001F +#define LBIST_CTRL_DIVIDE_RATIO_SHIFT 0x00000000 +#define LBIST_CTRL_DIVIDE_RATIO_MAX 0x0000001F + +#define LBIST_CTRL_LOAD_DIV_MASK 0x00000080 +#define LBIST_CTRL_LOAD_DIV_SHIFT 0x00000007 +#define LBIST_CTRL_LOAD_DIV_MAX 0x00000001 + +#define LBIST_CTRL_DC_DEF_MASK 0x00000300 +#define LBIST_CTRL_DC_DEF_SHIFT 0x00000008 +#define LBIST_CTRL_DC_DEF_MAX 0x00000003 + +#define LBIST_CTRL_RUNBIST_MODE_MASK 0x0000F000 +#define LBIST_CTRL_RUNBIST_MODE_SHIFT 0x0000000C +#define LBIST_CTRL_RUNBIST_MODE_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RUN_MASK 0x0F000000 +#define LBIST_CTRL_BIST_RUN_SHIFT 0x00000018 +#define LBIST_CTRL_BIST_RUN_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RESET_MASK 0x80000000 +#define LBIST_CTRL_BIST_RESET_SHIFT 0x0000001F +#define LBIST_CTRL_BIST_RESET_MAX 0x00000001 + +/* LBIST_PATCOUNT */ + +#define LBIST_PATCOUNT_SCAN_PC_DEF_MASK 0x0000000F +#define LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT 0x00000000 +#define LBIST_PATCOUNT_SCAN_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_RESET_PC_DEF_MASK 0x000000F0 +#define LBIST_PATCOUNT_RESET_PC_DEF_SHIFT 0x00000004 +#define LBIST_PATCOUNT_RESET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_SET_PC_DEF_MASK 0x00000F00 +#define LBIST_PATCOUNT_SET_PC_DEF_SHIFT 0x00000008 +#define LBIST_PATCOUNT_SET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_STATIC_PC_DEF_MASK 0x3FFF0000 +#define LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT 0x00000010 +#define LBIST_PATCOUNT_STATIC_PC_DEF_MAX 0x00003FFF + +/* LBIST_SEED0 */ + +#define LBIST_SEED0_PRPG_DEF_MASK 0xFFFFFFFF +#define LBIST_SEED0_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED0_PRPG_DEF_MAX 0xFFFFFFFF + +/* LBIST_SEED1 */ + +#define LBIST_SEED1_PRPG_DEF_MASK 0x001FFFFF +#define LBIST_SEED1_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED1_PRPG_DEF_MAX 0x001FFFFF + +/* LBIST_SPARE0 */ + +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MASK 0x00000001 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_SHIFT 0x00000000 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MASK 0x00000002 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_SHIFT 0x00000001 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_SPARE0_MASK 0xFFFFFFFC +#define LBIST_SPARE0_SPARE0_SHIFT 0x00000002 +#define LBIST_SPARE0_SPARE0_MAX 0x3FFFFFFF + +/* LBIST_SPARE1 */ + +#define LBIST_SPARE1_SPARE1_MASK 0xFFFFFFFF +#define LBIST_SPARE1_SPARE1_SHIFT 0x00000000 +#define LBIST_SPARE1_SPARE1_MAX 0xFFFFFFFF + +/* LBIST_STAT */ + +#define LBIST_STAT_MISR_MUX_CTL_MASK 0x000000FF +#define LBIST_STAT_MISR_MUX_CTL_SHIFT 0x00000000 +#define LBIST_STAT_MISR_MUX_CTL_MAX 0x000000FF + +#define LBIST_STAT_OUT_MUX_CTL_MASK 0x00000300 +#define LBIST_STAT_OUT_MUX_CTL_SHIFT 0x00000008 +#define LBIST_STAT_OUT_MUX_CTL_MAX 0x00000003 + +#define LBIST_STAT_BIST_RUNNING_MASK 0x00008000 +#define LBIST_STAT_BIST_RUNNING_SHIFT 0x0000000F +#define LBIST_STAT_BIST_RUNNING_MAX 0x00000001 + +#define LBIST_STAT_BIST_DONE_MASK 0x80000000 +#define LBIST_STAT_BIST_DONE_SHIFT 0x0000001F +#define LBIST_STAT_BIST_DONE_MAX 0x00000001 + +/* LBIST_MISR */ + +#define LBIST_MISR_MISR_RESULT_MASK 0xFFFFFFFF +#define LBIST_MISR_MISR_RESULT_SHIFT 0x00000000 +#define LBIST_MISR_MISR_RESULT_MAX 0xFFFFFFFF + +#define CTRL_MMR0_CFG0_BASE 0x00100000 +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL 0x0000C1A0 +#define MAIN_R5F2_LBIST_BASE (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL) + +#define LBIST_CTRL 0x00000000 +#define LBIST_PATCOUNT 0x00000004 +#define LBIST_SEED0 0x00000008 +#define LBIST_SEED1 0x0000000C +#define LBIST_SPARE0 0x00000010 +#define LBIST_SPARE1 0x00000014 +#define LBIST_STAT 0x00000018 +#define LBIST_MISR 0x0000001C + +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG 0x0000C2C0 +#define MAIN_R5F2_LBIST_SIG (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG) +#define MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0 284 + +/* Lbist Parameters */ +#define LBIST_DC_DEF 0x3 +#define LBIST_DIVIDE_RATIO 0x02 +#define LBIST_STATIC_PC_DEF 0x3ac0 +#define LBIST_RESET_PC_DEF 0x0f +#define LBIST_SET_PC_DEF 0x00 +#define LBIST_SCAN_PC_DEF 0x04 +#define LBIST_PRPG_DEF_L 0xFFFFFFFF +#define LBIST_PRPG_DEF_U 0x1FFFFF + +/* + * LBIST setup parameters for each core + */ + +#define LBIST_MAIN_R5_STATIC_PC_DEF LBIST_STATIC_PC_DEF +#define LBIST_C7X_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72_STATIC_PC_DEF 0x3fc0 +#define LBIST_DMPAC_STATIC_PC_DEF 0x1880 +#define LBIST_VPAC_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72SS_STATIC_PC_DEF 0x13c0 + +/* + * LBIST expected MISR's (using parameters above) + */ + +#define MAIN_R5_MISR_EXP_VAL 0x71d66f87 +#define A72_MISR_EXP_VAL 0x14df0200 +#define C7X_MISR_EXP_VAL 0x57b0478f +#define VPAC_MISR_EXP_VAL 0xec6abe22 +#define VPAC0_MISR_EXP_VAL 0x5c43b468 +#define DMPAC_MISR_EXP_VAL 0x53e1ef7b +#define A72SS_MISR_EXP_VAL 0x87da5a92 + +/** + * lbist_set_clock_delay() - Set seed for LBIST + * @ctrl_mmr_base: CTRL MMR base + * @clock_delay: clock delay + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_clock_delay(void *ctrl_mmr_base, u32 clock_delay) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base); + writel(reg_val & LBIST_CTRL_DC_DEF_MASK, ctrl_mmr_base); + + reg_val = readl(ctrl_mmr_base); + writel(reg_val | ((clock_delay & LBIST_CTRL_DC_DEF_MAX) + << LBIST_CTRL_DC_DEF_SHIFT), ctrl_mmr_base); +} + +/** + * lbist_set_seed() - Set seed for LBIST + * @config: lbist_config structure for LBIST test + * @seed: seed + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_seed(void *ctrl_mmr_base, u32 seed_l, u32 seed_u) +{ + writel(seed_l & LBIST_SEED0_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED0); + writel(seed_u & LBIST_SEED1_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED1); +} + +/** + * set_num_chain_test_patterns() - Set chain test patterns + * @ctrl_mmr_base: CTRL MMR base + * @chain_test_patterns: chain test patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_chain_test_patterns(void *ctrl_mmr_base, u32 chain_test_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SCAN_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((chain_test_patterns & LBIST_PATCOUNT_SCAN_PC_DEF_MAX) + << LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_reset_patterns() - Set reset patterns + * @ctrl_mmr_base: CTRL MMR base + * @reset_patterns: reset patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_reset_patterns(void *ctrl_mmr_base, u32 reset_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_RESET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((reset_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_RESET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_set_patterns() - Set patterns + * @ctrl_mmr_base: CTRL MMR base + * @set_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_set_patterns(void *ctrl_mmr_base, u32 set_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((set_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_SET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_stuck_at_patterns() - Set + * @ctrl_mmr_base: CTRL MMR base + * @stuck_at_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_stuck_at_patterns(void *ctrl_mmr_base, u32 stuck_at_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_STATIC_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((stuck_at_patterns & LBIST_PATCOUNT_STATIC_PC_DEF_MAX) + << LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_divide_ratio() - Set divide ratio + * @ctrl_mmr_base: CTRL MMR base + * @divide_ratio: divide ratio + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_divide_ratio(void *ctrl_mmr_base, u32 divide_ratio) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_DIVIDE_RATIO_MASK)), ctrl_mmr_base + LBIST_CTRL); + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (divide_ratio & LBIST_CTRL_DIVIDE_RATIO_MASK), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * clear_load_div() - Clear load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_LOAD_DIV_MASK)), ctrl_mmr_base + LBIST_CTRL); +} + +/** + * set_load_div() - Set load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_LOAD_DIV_MASK), ctrl_mmr_base + LBIST_CTRL); +} + +/* MACRO DEFINES */ +#define LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR 0x0 + +#define LBIST_STAT_OUT_MUX_CTL_CTRLMMR_PID 0x0 +#define LBIST_STAT_OUT_MUX_CTL_CTRL_ID 0x1 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1 0x2 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_2 0x3 + +/** + * lbist_get_misr() - Get MISR + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_get_misr(void *ctrl_mmr_base, u32 *p_misr_val) +{ + u32 reg_val; + u32 mux_val; + + reg_val = LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR; + mux_val = LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1; + reg_val |= (mux_val << LBIST_STAT_OUT_MUX_CTL_SHIFT); + writel(reg_val, ctrl_mmr_base + LBIST_STAT); + *p_misr_val = readl(ctrl_mmr_base + LBIST_MISR); +} + +/** + * lbist_clear_run_bist_mode() - Clear RUN_BIST_MODE + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_run_bist_mode(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_stop() - Stop running LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_stop(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_reset() - Reset LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_reset(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/* + * struct lbist_config - Structure containing different configuration used for LBIST + * @dc_def: Clock delay after scan_enable switching + * @divide_ratio: LBIST clock divide ratio + * @static_pc_def: Bitmap of stuck-at patterns to run + * @set_pc_def: Bitmap of set patterns to run + * @reset_pc_def: Bitmap of reset patterns to run + * @scan_pc_def: Bitmap of chain test patterns to run + * @prpg_def: Initial seed for Pseudo Random Pattern generator (PRPG) + */ +struct lbist_config { + u32 dc_def; + u32 divide_ratio; + u32 static_pc_def; + u32 set_pc_def; + u32 reset_pc_def; + u32 scan_pc_def; + u32 prpg_def_l; + u32 prpg_def_u; +}; + +/* + * struct lbist_inst_info - Structure for different configuration used for LBIST + * @lbist_signature: Pointer to LBIST signature + * @intr_num: Interrupt number triggered by this LBIST instance to MCU R5 VIM + * @expected_misr: Expected signature + * @lbist_config: Configuration for LBIST test + */ +struct lbist_inst_info { + u32 *lbist_signature; + u32 intr_num; + u32 expected_misr; + struct lbist_config lbist_conf; + struct core_under_test cut; +}; + +#if IS_ENABLED(CONFIG_SOC_K3_J784S4) + +#include "k3_j784s4_bist_static_data.h" + +#endif /* CONFIG_SOC_K3_J784S4 */ +#endif /* __K3_BIST_STATIC_DATA_H */ diff --git a/drivers/misc/k3_j784s4_bist_static_data.h b/drivers/misc/k3_j784s4_bist_static_data.h new file mode 100644 index 00000000000..7f9378e917f --- /dev/null +++ b/drivers/misc/k3_j784s4_bist_static_data.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST logic for J784S4 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +/* Device IDs of IPs that can be tested under BIST */ +#define TISCI_DEV_MCU_R5FSS2_CORE0 343 +#define TISCI_DEV_MCU_R5FSS2_CORE1 344 +#define TISCI_DEV_RTI32 365 +#define TISCI_DEV_RTI33 366 + +/* WKUP CTRL MMR Registers */ +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT 0x0000C2C0 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT 0x00000008 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT 0x00000001 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT 0x00000009 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT 0x00000005 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK 0x00008000 + +/* MCU CTRL MMR Register */ +#define MCU_CTRL_MMR0_CFG0_BASE 0x40f00000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL 0x0000c000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG 0x0000c280 +#define MCU_LBIST_BASE (MCU_CTRL_MMR0_CFG0_BASE + \ + MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL) + +/* Properties of PBIST instances in: PBIST14 */ +#define PBIST14_DEV_ID 234 +#define PBIST14_NUM_TEST_VECTORS 0x1 +#define PBIST14_ALGO_BITMAP_0 0x00000003 +#define PBIST14_MEM_BITMAP_0 0x000CCCCC +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0 0x0000007F +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1 0x00000003 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR 0x20000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I0 0x00000001 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I1 0x00000004 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 0x011D2528 + +static struct pbist_inst_info pbist14_inst_info = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .num_pbist_runs = 1, + .intr_num = PBIST14_DFT_PBIST_CPU_0_INTR_NUM, + .dev_id = TISCI_DEV_PBIST14, + .cut = { + { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, + { + .dev_id = TISCI_DEV_R5FSS2_CORE1, + .proc_id = PROC_ID_MCU_R5FSS2_CORE1, + } + }, + .pbist_config_run = { + { + .override = 0, + .algorithms_bit_map = PBIST14_ALGO_BITMAP_0, + .memory_groups_bit_map = PBIST14_MEM_BITMAP_0, + .scramble_value_lo = 0x76543210, + .scramble_value_hi = 0xFEDCBA98, + }, + { + .override = 0, + .algorithms_bit_map = 0, + .memory_groups_bit_map = 0, + .scramble_value_lo = 0, + .scramble_value_hi = 0, + }, + }, + .pbist_neg_config_run = { + .CA0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0, + .CA1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1, + .CA2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2, + .CA3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3, + .CL0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0, + .CL1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1, + .CL2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2, + .CL3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3, + .CMS = PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS, + .CSR = PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR, + .I0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I0, + .I1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I1, + .I2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I2, + .I3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I3, + .RAMT = PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT + }, + .num_pbist_rom_test_runs = 1, + .pbist_rom_test_config_run = { + { + .D = 0xF412605Eu, + .E = 0xF412605Eu, + .CA2 = 0x7FFFu, + .CL0 = 0x3FFu, + .CA3 = 0x0u, + .I0 = 0x1u, + .CL1 = 0x1Fu, + .I3 = 0x0u, + .I2 = 0xEu, + .CL2 = 0xEu, + .CA1 = 0x7FFFu, + .CA0 = 0x0u, + .CL3 = 0x7FFFu, + .I1 = 0x20u, + .RAMT = 0x08002020u, + .CSR = 0x00000001u, + .CMS = 0x01u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + }, +}; + +static struct lbist_inst_info lbist_inst_info_main_r5f2_x = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .lbist_signature = (u32 *)(MAIN_R5F2_LBIST_SIG), + .intr_num = MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0, + .expected_misr = MAIN_R5_MISR_EXP_VAL, + .lbist_conf = { + .dc_def = LBIST_DC_DEF, + .divide_ratio = LBIST_DIVIDE_RATIO, + .static_pc_def = LBIST_MAIN_R5_STATIC_PC_DEF, + .set_pc_def = LBIST_SET_PC_DEF, + .reset_pc_def = LBIST_RESET_PC_DEF, + .scan_pc_def = LBIST_SCAN_PC_DEF, + .prpg_def_l = LBIST_PRPG_DEF_L, + .prpg_def_u = LBIST_PRPG_DEF_U, + }, + .cut = { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, +}; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index c8bf89d6d35..12e37cb4b78 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -373,6 +373,12 @@ static const struct udevice_id exynos_dwmmc_ids[] = { .compatible = "samsung,exynos4412-dw-mshc", .data = (ulong)&exynos4_drv_data, }, { + .compatible = "samsung,exynos5420-dw-mshc-smu", + .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos5420-dw-mshc", + .data = (ulong)&exynos5_drv_data, + }, { .compatible = "samsung,exynos-dwmmc", .data = (ulong)&exynos5_drv_data, }, { diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 90fcf2679bb..928c05872ca 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -155,6 +155,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, struct mmc_cmd cmd; struct mmc_data data; int timeout_ms = 1000; + int err; if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", @@ -181,9 +182,13 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, data.blocksize = mmc->write_bl_len; data.flags = MMC_DATA_WRITE; - if (mmc_send_cmd(mmc, &cmd, &data)) { + err = mmc_send_cmd(mmc, &cmd, &data); + if (err) { printf("mmc write failed\n"); - return 0; + /* + * Don't return 0 here since the emmc will still be in data + * transfer mode continue to send the STOP_TRANSMISSION command + */ } /* SPI multiblock writes terminate using a special @@ -203,6 +208,9 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, if (mmc_poll_for_busy(mmc, timeout_ms)) return 0; + if (err) + return 0; + return blkcnt; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 278019f02ab..c80033d8752 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -141,14 +141,6 @@ static int do_sdhci_init(struct sdhci_host *host) } } - if (dm_gpio_is_valid(&host->cd_gpio)) { - ret = dm_gpio_get_value(&host->cd_gpio); - if (ret) { - debug("no SD card detected (%d)\n", ret); - return -ENODEV; - } - } - return s5p_sdhci_core_init(host); } @@ -183,8 +175,6 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, &host->pwr_gpio, GPIOD_IS_OUT); - gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, - &host->cd_gpio, GPIOD_IS_IN); return 0; } @@ -236,6 +226,7 @@ static int s5p_sdhci_bind(struct udevice *dev) static const struct udevice_id s5p_sdhci_ids[] = { { .compatible = "samsung,exynos4412-sdhci"}, + { .compatible = "samsung,exynos4210-sdhci"}, { } }; diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 06c1e09bf26..e28c81afffe 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -99,6 +99,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) */ if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) pll_hz /= 2; + + /* + * The A523/T527 uses PERIPH0_400M as the MMC0/1 input clock, + * and PERIPH0_800M for MMC2. There is also the hidden divider + * of 2. The clock code reports 600 MHz for PERIPH0. + * Adjust the calculation accordingly: 600 * hidden2 / 3 for + * MMC0/1, and 600 * hidden2 / 3 * 2 for MMC2. + */ + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) { + pll_hz /= 3; + if (priv->mmc_no == 2) + pll_hz *= 2; + } } div = pll_hz / hz; @@ -153,6 +166,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) CCM_MMC_CTRL_SCLK_DLY(sclk_dly); } + /* The A523 has a second divider, not a shift. */ + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + n = (1U << n) - 1; + writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_M(div) | val, priv->mclkreg); @@ -559,7 +576,8 @@ struct mmc *sunxi_mmc_init(int sdc_no) cfg->host_caps = MMC_MODE_4BIT; if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_MACH_SUN55I_A523)) && + (sdc_no == 2)) cfg->host_caps = MMC_MODE_8BIT; cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index 15670d6d24a..c698a07c784 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -42,7 +42,7 @@ static int eth_raw_bus_post_bind(struct udevice *dev) device_probe(child); priv = dev_get_priv(child); if (priv) { - strcpy(priv->host_ifname, i->if_name); + strlcpy(priv->host_ifname, i->if_name, IFNAMSIZ); priv->host_ifindex = i->if_index; priv->local = local; } diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 555651937f8..56f877c20a6 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -346,7 +346,7 @@ static bool isrxready(struct axi_mrmac_priv *priv) * axi_mrmac_recv - MRMAC Rx function * @dev: udevice structure * @flags: flags from network stack - * @packetp pointer to received data + * @packetp: pointer to received data * * Return: received data length on success, negative value on errors * @@ -399,7 +399,7 @@ static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp) * axi_mrmac_free_pkt - MRMAC free packet function * @dev: udevice structure * @packet: receive buffer pointer - * @length received data length + * @length: received data length * * Return: 0 on success, negative value on errors * diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index d3fe90d939e..c297fa03ea7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -259,6 +259,15 @@ config MT76X8_USB_PHY This PHY is found on MT76x8 devices supporting USB. +config PHY_EXYNOS_USBDRD + bool "Exynos SoC series USB DRD PHY driver" + depends on PHY && CLK + depends on ARCH_EXYNOS + select REGMAP + select SYSCON + help + Enable USB DRD PHY support for Exynos SoC series. + config PHY_MTK_TPHY bool "MediaTek T-PHY Driver" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index b4d01fc700d..98c1ef8683b 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o +obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-exynos-usbdrd.c b/drivers/phy/phy-exynos-usbdrd.c new file mode 100644 index 00000000000..db5815ed184 --- /dev/null +++ b/drivers/phy/phy-exynos-usbdrd.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + * + * Samsung Exynos SoC series USB DRD PHY driver. + * Based on Linux kernel PHY driver: drivers/phy/samsung/phy-exynos5-usbdrd.c + */ + +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> + +/* Offset of PMU register controlling USB PHY output isolation */ +#define EXYNOS_USBDRD_PHY_CONTROL 0x0704 +#define EXYNOS_PHY_ENABLE BIT(0) + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ2 0x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_26MHZ 0x6 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* Exynos850: USB DRD PHY registers */ +#define EXYNOS850_DRD_LINKCTRL 0x04 +#define LINKCTRL_FORCE_QACT BIT(8) +#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4) + +#define EXYNOS850_DRD_CLKRST 0x20 +#define CLKRST_LINK_SW_RST BIT(0) +#define CLKRST_PORT_RST BIT(1) +#define CLKRST_PHY_SW_RST BIT(3) + +#define EXYNOS850_DRD_SSPPLLCTL 0x30 +#define SSPPLLCTL_FSEL GENMASK(2, 0) + +#define EXYNOS850_DRD_UTMI 0x50 +#define UTMI_FORCE_SLEEP BIT(0) +#define UTMI_FORCE_SUSPEND BIT(1) +#define UTMI_DM_PULLDOWN BIT(2) +#define UTMI_DP_PULLDOWN BIT(3) +#define UTMI_FORCE_BVALID BIT(4) +#define UTMI_FORCE_VBUSVALID BIT(5) + +#define EXYNOS850_DRD_HSP 0x54 +#define HSP_COMMONONN BIT(8) +#define HSP_EN_UTMISUSPEND BIT(9) +#define HSP_VBUSVLDEXT BIT(12) +#define HSP_VBUSVLDEXTSEL BIT(13) +#define HSP_FSV_OUT_EN BIT(24) + +#define EXYNOS850_DRD_HSP_TEST 0x5c +#define HSP_TEST_SIDDQ BIT(24) + +#define KHZ 1000 +#define MHZ (KHZ * KHZ) + +/** + * struct exynos_usbdrd_phy - driver data for Exynos USB PHY + * @reg_phy: USB PHY controller register memory base + * @clk: clock for register access + * @core_clk: core clock for phy (ref clock) + * @reg_pmu: regmap for PMU block + * @extrefclk: frequency select settings when using 'separate reference clocks' + */ +struct exynos_usbdrd_phy { + void __iomem *reg_phy; + struct clk *clk; + struct clk *core_clk; + struct regmap *reg_pmu; + u32 extrefclk; +}; + +static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate) +{ + unsigned int val; + + if (!reg_pmu) + return; + + val = isolate ? 0 : EXYNOS_PHY_ENABLE; + regmap_update_bits(reg_pmu, EXYNOS_USBDRD_PHY_CONTROL, + EXYNOS_PHY_ENABLE, val); +} + +/* + * Convert the supplied clock rate to the value that can be written to the PHY + * register. + */ +static unsigned int exynos_rate_to_clk(unsigned long rate, u32 *reg) +{ + switch (rate) { + case 9600 * KHZ: + *reg = EXYNOS5_FSEL_9MHZ6; + break; + case 10 * MHZ: + *reg = EXYNOS5_FSEL_10MHZ; + break; + case 12 * MHZ: + *reg = EXYNOS5_FSEL_12MHZ; + break; + case 19200 * KHZ: + *reg = EXYNOS5_FSEL_19MHZ2; + break; + case 20 * MHZ: + *reg = EXYNOS5_FSEL_20MHZ; + break; + case 24 * MHZ: + *reg = EXYNOS5_FSEL_24MHZ; + break; + case 26 * MHZ: + *reg = EXYNOS5_FSEL_26MHZ; + break; + case 50 * MHZ: + *reg = EXYNOS5_FSEL_50MHZ; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void exynos850_usbdrd_utmi_init(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This will force + * QACTIVE signal in Q-Channel interface to HIGH level, to make sure + * the PHY clock is not gated by the hardware. + */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_FORCE_QACT; + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + /* Start PHY Reset (POR=high) */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_PHY_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + + /* Enable UTMI+ */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN | + UTMI_DM_PULLDOWN); + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); + reg &= ~SSPPLLCTL_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); + break; + default: + dev_warn(phy->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); + + /* Power up PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg &= ~HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Finish PHY reset (POR=low) */ + udelay(10); /* required before doing POR=low */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(75); /* required after POR=low for guaranteed PHY clock */ + + /* Disable single ended signal out */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg &= ~HSP_FSV_OUT_EN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); +} + +static void exynos850_usbdrd_utmi_exit(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); + reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Power down PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg |= HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Link reset */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(10); /* required before doing POR=low */ + reg &= ~CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); +} + +static int exynos_usbdrd_phy_init(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + exynos850_usbdrd_utmi_init(phy); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static int exynos_usbdrd_phy_exit(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + exynos850_usbdrd_utmi_exit(phy); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static int exynos_usbdrd_phy_power_on(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + int ret; + + dev_dbg(phy->dev, "Request to power_on usbdrd_phy phy\n"); + + ret = clk_prepare_enable(phy_drd->core_clk); + if (ret) + return ret; + + /* Power-on PHY */ + exynos_usbdrd_phy_isol(phy_drd->reg_pmu, false); + + return 0; +} + +static int exynos_usbdrd_phy_power_off(struct phy *phy) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev); + + dev_dbg(phy->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Power-off the PHY */ + exynos_usbdrd_phy_isol(phy_drd->reg_pmu, true); + + clk_disable_unprepare(phy_drd->core_clk); + + return 0; +} + +static int exynos_usbdrd_phy_init_clk(struct udevice *dev) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev); + unsigned long ref_rate; + int err; + + phy_drd->clk = devm_clk_get(dev, "phy"); + if (IS_ERR(phy_drd->clk)) { + err = PTR_ERR(phy_drd->clk); + dev_err(dev, "Failed to get phy clock (err=%d)\n", err); + return err; + } + + phy_drd->core_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(phy_drd->core_clk)) { + err = PTR_ERR(phy_drd->core_clk); + dev_err(dev, "Failed to get ref clock (err=%d)\n", err); + return err; + } + + ref_rate = clk_get_rate(phy_drd->core_clk); + err = exynos_rate_to_clk(ref_rate, &phy_drd->extrefclk); + if (err) { + dev_err(dev, "Clock rate %lu not supported\n", ref_rate); + return err; + } + + return 0; +} + +static int exynos_usbdrd_phy_probe(struct udevice *dev) +{ + struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev); + int err; + + phy_drd->reg_phy = dev_read_addr_ptr(dev); + if (!phy_drd->reg_phy) + return -EINVAL; + + err = exynos_usbdrd_phy_init_clk(dev); + if (err) + return err; + + phy_drd->reg_pmu = syscon_regmap_lookup_by_phandle(dev, + "samsung,pmu-syscon"); + if (IS_ERR(phy_drd->reg_pmu)) { + err = PTR_ERR(phy_drd->reg_pmu); + dev_err(dev, "Failed to lookup PMU regmap\n"); + return err; + } + + return 0; +} + +static const struct phy_ops exynos_usbdrd_phy_ops = { + .init = exynos_usbdrd_phy_init, + .exit = exynos_usbdrd_phy_exit, + .power_on = exynos_usbdrd_phy_power_on, + .power_off = exynos_usbdrd_phy_power_off, +}; + +static const struct udevice_id exynos_usbdrd_phy_of_match[] = { + { + .compatible = "samsung,exynos850-usbdrd-phy", + }, + { } +}; + +U_BOOT_DRIVER(exynos_usbdrd_phy) = { + .name = "exynos-usbdrd-phy", + .id = UCLASS_PHY, + .of_match = exynos_usbdrd_phy_of_match, + .probe = exynos_usbdrd_phy_probe, + .ops = &exynos_usbdrd_phy_ops, + .priv_auto = sizeof(struct exynos_usbdrd_phy), +}; diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 65e8192a99a..54314992299 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -139,4 +139,14 @@ config PINCTRL_SUN20I_D1 default MACH_SUN8I_R528 select PINCTRL_SUNXI +config PINCTRL_SUN55I_A523 + bool "Support for the Allwinner A523 PIO" + default MACH_SUN55I_A523 + select PINCTRL_SUNXI + +config PINCTRL_SUN55I_A523_R + bool "Support for the Allwinner A523 R-PIO" + default MACH_SUN55I_A523 + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index c38edf7d4f5..03cfe23aaf8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -759,6 +759,29 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = .num_banks = 9, }; +static const struct sunxi_pinctrl_function sun55i_a523_pinctrl_functions[] = { + { "emac0", 5 }, /* PI0-PI16 */ + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "mmc0", 2 }, /* PF0-PF5 */ + { "mmc1", 2 }, /* PG0-PG5 */ + { "mmc2", 3 }, /* PC0-PC16 */ + { "spi0", 4 }, /* PC0-PC7, PC15-PC16 */ +#if IS_ENABLED(CONFIG_UART0_PORT_F) + { "uart0", 3 }, /* PF2-PF4 */ +#else + { "uart0", 2 }, /* PH0-PH1 */ +#endif + { "uart1", 2 }, /* PG6-PG7 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_pinctrl_desc = { + .functions = sun55i_a523_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun55i_a523_pinctrl_functions), + .first_bank = SUNXI_GPIO_A, + .num_banks = 11, +}; + static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { { "gpio_in", 0 }, { "gpio_out", 1 }, @@ -809,6 +832,21 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc .num_banks = 1, }; +static const struct sunxi_pinctrl_function sun55i_a523_r_pinctrl_functions[] = { + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "r_i2c0", 2 }, /* PL0-PL1 */ + { "r_spi", 6 }, /* PL10-PL13 */ + { "r_uart", 2 }, /* PL2-PL3 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun55i_a523_r_pinctrl_desc = { + .functions = sun55i_a523_r_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun55i_a523_r_pinctrl_functions), + .first_bank = SUNXI_GPIO_L, + .num_banks = 2, +}; + static const struct udevice_id sunxi_pinctrl_ids[] = { #ifdef CONFIG_PINCTRL_SUNIV_F1C100S { @@ -984,6 +1022,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = { .data = (ulong)&sun50i_a100_r_pinctrl_desc, }, #endif +#ifdef CONFIG_PINCTRL_SUN55I_A523 + { + .compatible = "allwinner,sun55i-a523-pinctrl", + .data = (ulong)&sun55i_a523_pinctrl_desc, + }, +#endif +#ifdef CONFIG_PINCTRL_SUN55I_A523_R + { + .compatible = "allwinner,sun55i-a523-r-pinctrl", + .data = (ulong)&sun55i_a523_r_pinctrl_desc, + }, +#endif {} }; diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index b44aae78e6d..a7e64971a2a 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -468,6 +468,8 @@ out_clk_disable: static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, struct ofnode_phandle_args *args) { + power_domain->id = 0; + return 0; } diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c index c300fd2bbc2..1204ec00f8d 100644 --- a/drivers/power/pmic/axp.c +++ b/drivers/power/pmic/axp.c @@ -89,6 +89,7 @@ static const struct udevice_id axp_pmic_ids[] = { { .compatible = "x-powers,axp221", .data = AXP221_ID }, { .compatible = "x-powers,axp223", .data = AXP223_ID }, { .compatible = "x-powers,axp313a", .data = AXP313_ID }, + { .compatible = "x-powers,axp323", .data = AXP323_ID }, { .compatible = "x-powers,axp717", .data = AXP717_ID }, { .compatible = "x-powers,axp803", .data = AXP803_ID }, { .compatible = "x-powers,axp806", .data = AXP806_ID }, diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c index 75cdbca30f6..7794a4f5d92 100644 --- a/drivers/power/regulator/axp_regulator.c +++ b/drivers/power/regulator/axp_regulator.c @@ -318,6 +318,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = { [AXP221_ID] = axp22x_regulators, [AXP223_ID] = axp22x_regulators, [AXP313_ID] = axp313_regulators, + [AXP323_ID] = axp313_regulators, [AXP717_ID] = axp717_regulators, [AXP803_ID] = axp803_regulators, [AXP806_ID] = axp806_regulators, diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 09567eb9dbb..2a59a1b79c2 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -260,13 +260,13 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) *devp = NULL; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret) { - dev_dbg(dev, "ret=%d\n", ret); - continue; - } + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) { + dev_dbg(dev, "ret=%d\n", ret); + return ret; + } + for (; dev; uclass_find_next_device(&dev)) { uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) continue; @@ -410,9 +410,12 @@ static bool regulator_name_is_unique(struct udevice *check_dev, int ret; int len; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == check_dev) + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) + return true; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == check_dev) continue; uc_pdata = dev_get_uclass_plat(dev); diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 3233ff80419..2dbd3a21cea 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -55,9 +55,12 @@ static int for_each_remoteproc_device(int (*fn) (struct udevice *dev, struct dm_rproc_uclass_pdata *uc_pdata; int ret; - for (ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == skip_dev) + ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); + if (ret) + return ret; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == skip_dev) continue; uc_pdata = dev_get_uclass_plat(dev); ret = fn(dev, uc_pdata, data); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a3513f0a3ef..1ae36b5a348 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -351,6 +351,8 @@ config MTK_SPIM config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" + depends on ARCH_MVEBU && ARM64 + select CLK_MVEBU select CLK_ARMADA_3720 help Enable the Marvell Armada 3700 SPI driver. This driver can be diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 6f89d3add5d..4696c09f754 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -559,9 +559,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, u8 opcode; if (priv->dtr) - txlen += txlen & 1; - - if (priv->dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index aa83073c96a..67edf004205 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -176,7 +176,7 @@ config SYSRESET_PALMAS config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW - select SPL_ARM_PSCI_FW if SPL + select SPL_ARM_PSCI_FW if SPL_SYSRESET help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 21452ad1569..3cda2b74b7e 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -704,6 +704,7 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, { .compatible = "fsl,imx8mq-dwc3" }, { .compatible = "intel,tangier-dwc3" }, + { .compatible = "samsung,exynos850-dwusb3" }, { } }; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi new file mode 100644 index 00000000000..ee485899ba0 --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun55i-a523.dtsi @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2023-2024 Arm Ltd. + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun6i-rtc.h> +#include <dt-bindings/clock/sun55i-a523-ccu.h> +#include <dt-bindings/clock/sun55i-a523-r-ccu.h> +#include <dt-bindings/reset/sun55i-a523-ccu.h> +#include <dt-bindings/reset/sun55i-a523-r-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x000>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x300>; + enable-method = "psci"; + }; + + cpu4: cpu@400 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x400>; + enable-method = "psci"; + }; + + cpu5: cpu@500 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x500>; + enable-method = "psci"; + }; + + cpu6: cpu@600 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x600>; + enable-method = "psci"; + }; + + cpu7: cpu@700 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x700>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + pio: pinctrl@2000000 { + compatible = "allwinner,sun55i-a523-pinctrl"; + reg = <0x2000000 0x800>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; + allwinner,pinmux = <2>; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; + allwinner,pinmux = <2>; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", "PC13", "PC14", + "PC15", "PC16"; + allwinner,pinmux = <3>; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + allwinner,pinmux = <2>; + function = "uart0"; + }; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun55i-a523-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; + clock-names = "hosc", "losc", + "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + wdt: watchdog@2050000 { + compatible = "allwinner,sun55i-a523-wdt"; + reg = <0x2050000 0x20>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "okay"; + }; + + uart0: serial@2500000 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500000 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@2500400 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500400 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@2500800 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500800 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@2500c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500c00 0x400>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@2501000 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@2501400 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501400 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@2501800 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501800 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@2501c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501c00 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@2503000 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2503000 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5: i2c@2503400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2503400 0x400>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C5>; + resets = <&ccu RST_BUS_I2C5>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@3400000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #interrupt-cells = <3>; + #size-cells = <1>; + ranges; + interrupt-controller; + reg = <0x3400000 0x10000>, + <0x3460000 0x100000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + dma-noncoherent; + + its: msi-controller@3440000 { + compatible = "arm,gic-v3-its"; + reg = <0x3440000 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun55i-a523-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + extcon = <&usbphy 0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun55i-a523-usb-phy", + "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&osc24M>, + <&osc24M>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun55i-a523-r-ccu"; + reg = <0x7010000 0x250>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_200M>, + <&ccu CLK_PLL_AUDIO0_4X>; + clock-names = "hosc", + "losc", + "iosc", + "pll-periph", + "pll-audio"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun55i-a523-nmi"; + reg = <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0" ,"PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + }; + }; + + r_i2c0: i2c@7081400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_BUS_R_I2C0>; + resets = <&r_ccu RST_BUS_R_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + rtc: rtc@7090000 { + compatible = "allwinner,sun55i-a523-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts new file mode 100644 index 00000000000..ad9bd6da424 --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun55i-a527-cubie-a5e.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2025 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Radxa A5E"; + compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the USB-C connector */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_cldo3>; + vcc-pe-supply = <®_aldo2>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_cldo3>; + vcc-pj-supply = <®_cldo4>; + vcc-pk-supply = <®_cldo1>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@34 { + compatible = "x-powers,axp717"; + reg = <0x34>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-iowifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pm-lpddr4"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi-cam"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc-and-their-dog"; + }; + + reg_cldo2: cldo2 { + /* not connected */ + }; + + reg_cldo3: cldo3 { + /* IO, USB-2, 3V3, card, NAND, sensor, PI */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pj-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-mipi-dsi"; + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* RISC-V management core supply */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The USB-C port is the primary power supply, so in this configuration + * relies on the other end of the USB cable to supply the VBUS power. + * So use this port in peripheral mode. + * It is possible to supply the board with the 5V pins on the GPIO + * header, and since the DCIN_5V line is hardwired to the USB-C VBUS + * pins, the port turns into a host port, unconditionally supplying + * power. The dr_mode property should be changed to "host" here, if + * users choose this setup. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +/* + * The schematic describes USB0_ID (PL10), measuring VBUS_5V, which looks to + * be always on. Also there is USB-VBUSDET (PL2), which is measuring the same + * VBUS_5V. There is also DCIN_DET, which measures DCIN_5V, so the power + * input rail. + * None of them seem to make any sense in relation to detecting USB devices + * or whether there is power provided via any USB pins: they would always + * report high, otherwise the system wouldn't be running. + * The AXP717C provides proper USB-C CC pin functionality, but the PMIC is + * not connected to those pins of the USB-C connector. + */ +&usbphy { + usb0_vbus-supply = <®_vcc5v>; + usb1_vbus-supply = <®_usb_vbus>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-h728-x96qpro+.dts b/dts/upstream/src/arm64/allwinner/sun55i-h728-x96qpro+.dts new file mode 100644 index 00000000000..59db103546f --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun55i-h728-x96qpro+.dts @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "X96Q Pro+"; + compatible = "amediatech,x96q-pro-plus", "allwinner,sun55i-h728"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the barrel plug */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* 3.3V dummy supply for the SD card */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + regulator-always-on; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + disable-wp; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_cldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_dcdc4>; + vcc-pe-supply = <®_dcdc4>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_dcdc4>; + vcc-pj-supply = <®_dcdc4>; + vcc-pk-supply = <®_bldo3>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@34 { + compatible = "x-powers,axp717"; + reg = <0x34>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.0(?) GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd-dcdc4"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-aldo3"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-bldo3"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-codec-sd"; + }; + + reg_cldo2: cldo2 { + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-codec-eth-sd"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd-dcdc3"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* USB0 is a USB-A receptacle, always powered, so force host mode. */ + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts b/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts new file mode 100644 index 00000000000..dea2acc1849 --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun55i-t527-avaota-a1.dts @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Avaota A1"; + compatible = "yuzukihd,avaota-a1", "allwinner,sun55i-t527"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc12v: vcc12v { + /* DC input jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the 12V->5V regulator */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc12v>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + gpio = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + enable-active-high; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + bus-width = <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_cldo1>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_dcdc4>; + vcc-pe-supply = <®_dcdc4>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_dcdc4>; + vcc-pj-supply = <®_dcdc4>; + vcc-pk-supply = <®_bldo3>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@35 { + compatible = "x-powers,axp717"; + reg = <0x35>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1160000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd-io"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl-pm"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-cvp-pk-vid1v8"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + /* not connected */ + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The CC pins of the USB-C port have two pull-down resistors + * connected to GND, which fixes this port to a peripheral role. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power, but without the CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb_vbus>; + usb0_vbus_det-gpios = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */ + status = "okay"; +}; diff --git a/fs/exfat/exfat.h b/fs/exfat/exfat.h index ca6f22b9d58..bd2965c3942 100644 --- a/fs/exfat/exfat.h +++ b/fs/exfat/exfat.h @@ -237,8 +237,10 @@ int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path); void exfat_utimes(struct exfat_node* node, const struct timespec tv[2]); void exfat_update_atime(struct exfat_node* node); void exfat_update_mtime(struct exfat_node* node); +#ifndef __UBOOT__ const char* exfat_get_label(struct exfat* ef); int exfat_set_label(struct exfat* ef, const char* label); +#endif /* __UBOOT__ */ int exfat_soil_super_block(const struct exfat* ef); int exfat_mount(struct exfat* ef, const char* spec, const char* options); diff --git a/fs/exfat/node.c b/fs/exfat/node.c index 88b1357189c..b7406fbf3ed 100644 --- a/fs/exfat/node.c +++ b/fs/exfat/node.c @@ -1188,6 +1188,7 @@ void exfat_update_mtime(struct exfat_node* node) node->is_dirty = true; } +#ifndef __UBOOT__ const char* exfat_get_label(struct exfat* ef) { return ef->label; @@ -1241,3 +1242,4 @@ int exfat_set_label(struct exfat* ef, const char* label) strcpy(ef->label, label); return 0; } +#endif /* __UBOOT__ */ diff --git a/include/axp_pmic.h b/include/axp_pmic.h index ae62ef0d76d..1806a7270a0 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -33,6 +33,7 @@ enum { AXP221_ID, AXP223_ID, AXP313_ID, + AXP323_ID, AXP717_ID, AXP803_ID, AXP806_ID, diff --git a/include/blk.h b/include/blk.h index 488d04cf32a..8d1b70cabd3 100644 --- a/include/blk.h +++ b/include/blk.h @@ -782,51 +782,6 @@ int blk_first_device_err(enum blk_flag_t flags, struct udevice **devp); int blk_next_device_err(enum blk_flag_t flags, struct udevice **devp); /** - * blk_find_first() - Return the first matching block device - * @flags: Indicates type of device to return - * @devp: Returns pointer to device, or NULL on error - * - * The device is not prepared for use - this is an internal function. - * The function uclass_get_device_tail() can be used to probe the device. - * - * Note that some devices are considered removable until they have been probed - * - * @return 0 if found, -ENODEV if not found - */ -int blk_find_first(enum blk_flag_t flags, struct udevice **devp); - -/** - * blk_find_next() - Return the next matching block device - * @flags: Indicates type of device to return - * @devp: On entry, pointer to device to lookup. On exit, returns pointer - * to the next device in the same uclass, or NULL if none - * - * The device is not prepared for use - this is an internal function. - * The function uclass_get_device_tail() can be used to probe the device. - * - * Note that some devices are considered removable until they have been probed - * - * @return 0 if found, -ENODEV if not found - */ -int blk_find_next(enum blk_flag_t flags, struct udevice **devp); - -/** - * blk_foreach() - iterate through block devices - * - * This creates a for() loop which works through the available block devices in - * order from start to end. - * - * If for some reason the uclass cannot be found, this does nothing. - * - * @_flags: Indicates type of device to return - * @_pos: struct udevice * to hold the current device. Set to NULL when there - * are no more devices. - */ -#define blk_foreach(_flags, _pos) \ - for (int _ret = blk_find_first(_flags, &_pos); !_ret && _pos; \ - _ret = blk_find_next(_flags, &_pos)) - -/** * blk_foreach_probe() - Helper function to iteration through block devices * * This creates a for() loop which works through the available devices in diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h index 4607b3089b2..63e85332bd8 100644 --- a/include/configs/e850-96.h +++ b/include/configs/e850-96.h @@ -9,4 +9,25 @@ #ifndef __E850_96_H #define __E850_96_H +/* GUIDs for capsule updatable firmware images */ +#define E850_96_FWBL1_IMAGE_GUID \ + EFI_GUID(0x181cd3f2, 0xe375, 0x44d2, 0x80, 0x78, \ + 0x32, 0x21, 0xe1, 0xdf, 0xb9, 0x5e) + +#define E850_96_EPBL_IMAGE_GUID \ + EFI_GUID(0x66c1a54d, 0xd149, 0x415d, 0xaa, 0xda, \ + 0xb8, 0xae, 0xe4, 0x99, 0xb3, 0x70) + +#define E850_96_BL2_IMAGE_GUID \ + EFI_GUID(0x89471c2a, 0x6c8d, 0x4158, 0xac, 0xad, \ + 0x23, 0xd3, 0xb2, 0x87, 0x3d, 0x35) + +#define E850_96_BOOTLOADER_IMAGE_GUID \ + EFI_GUID(0x629578c3, 0xffb3, 0x4a89, 0xac, 0x0c, \ + 0x61, 0x18, 0x40, 0x72, 0x77, 0x79) + +#define E850_96_EL3_MON_IMAGE_GUID \ + EFI_GUID(0xdf5718a2, 0x930a, 0x4916, 0xbb, 0x19, \ + 0x32, 0x13, 0x21, 0x4d, 0x84, 0x86) + #endif /* __E850_96_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index e1b62f78b21..01ab6edb05f 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2025 Tony Dinh <mibodhi@gmail.com> * Copyright (C) 2011-2012 * Gerald Kerma <dreagle@doukki.net> * Luka Perkov <luka@openwrt.org> @@ -11,19 +12,34 @@ #include "mv-common.h" /* - * Environment variables configuration - */ - -/* - * Default environment variables + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ +#include "mv-common.h" -#define CFG_EXTRA_ENV_SETTINGS \ +#define EXTRA_ENV_SETTINGS_LEGACY \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x2c00000) +#define RAMDISK_ADDR_R __stringify(0x01100000) +#define SCRIPT_ADDR_R __stringify(0x200000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS_LEGACY \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" + /* * SATA driver configuration */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 94355cf61e4..e7db0161126 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -6,8 +6,6 @@ #ifndef __IMX93_EVK_H #define __IMX93_EVK_H -#include <linux/sizes.h> -#include <linux/stringify.h> #include <asm/arch/imx-regs.h> #define CFG_SYS_UBOOT_BASE \ diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h new file mode 100644 index 00000000000..987fcacb999 --- /dev/null +++ b/include/configs/imx93_frdm.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX93_FRDM_H +#define __IMX93_FRDM_H + +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_XPL_BUILD +#define CFG_MALLOC_F_ADDR 0x204D0000 +#endif + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 3a243d789c0..b6e6958599c 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -10,8 +10,7 @@ #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CFG_PRAM ((CONFIG_KM_PNVRAM + \ - CONFIG_KM_PHRAM + \ - CONFIG_KM_RESERVED_PRAM) >> 10) + CONFIG_KM_PHRAM) >> 10) #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e7ae18ec5f9..de41b998ea4 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -158,11 +158,10 @@ /****************************************************************************** * (PRAM usage) * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |ROOTFSSIZE | PNVRAM |PHRAM | END_OF_RAM | * ... |<------------------- pram -------------------------->| * ... ------------------------------------------------------- * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose * @CONFIG_KM_PHRAM: address for /var * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) */ diff --git a/include/configs/sama7d65_curiosity.h b/include/configs/sama7d65_curiosity.h new file mode 100644 index 00000000000..9316b104ee3 --- /dev/null +++ b/include/configs/sama7d65_curiosity.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA7D65 Curiosity Board. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +/* SDRAM */ +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 + +#endif diff --git a/include/configs/sun55i.h b/include/configs/sun55i.h new file mode 100644 index 00000000000..70649366c1c --- /dev/null +++ b/include/configs/sun55i.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Placeholder wrapper to allow addressing Allwinner devices with Cortex-A55 + * cores separately. Please do not add anything in here. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */ diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index 3ddcdd21439..9cb3f090271 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -149,10 +149,8 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp); * * The device is not prepared for use - this is an internal function. * The function uclass_get_device_tail() can be used to probe the device. - * - * Return: 0 if OK (found or not found), -ve on error */ -int uclass_find_next_device(struct udevice **devp); +void uclass_find_next_device(struct udevice **devp); /** * uclass_find_device_by_namelen() - Find uclass device based on ID and name diff --git a/include/env/pg-wcom/ls102xa.env b/include/env/pg-wcom/ls102xa.env index abbec424574..88aaac8f008 100644 --- a/include/env/pg-wcom/ls102xa.env +++ b/include/env/pg-wcom/ls102xa.env @@ -8,7 +8,6 @@ checkfdt=true cramfsloadfdt=cramfsload $fdt_addr_r fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb ethrotate=no hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,asrc,spdif,lpuart1,ftm1 -netdev=eth2 newenv=protect off CONFIG_ENV_ADDR_REDUND +0x40000 && erase CONFIG_ENV_ADDR_REDUND +0x40000 && diff --git a/include/env/ti/ti_armv7_keystone2.env b/include/env/ti/ti_armv7_keystone2.env index e0395d302cb..1b2aaa2808a 100644 --- a/include/env/ti/ti_armv7_keystone2.env +++ b/include/env/ti/ti_armv7_keystone2.env @@ -12,6 +12,7 @@ dfu_alt_info_mmc= uEnv.txt fat 0 1 bootdir=/boot +bootm_size=0x10000000 tftp_root=/ nfs_root=/export mem_lpae=1 diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index 7029d12bf20..03e3267ef8a 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -8,7 +8,6 @@ rdaddr=0x88080000 ramdisk_addr_r=0x88080000 scriptaddr=0x80000000 pxefile_addr_r=0x80100000 -bootm_size=0x10000000 boot_fdt=try boot_fit=0 diff --git a/include/fb_spi_flash.h b/include/fb_spi_flash.h new file mode 100644 index 00000000000..904654748a4 --- /dev/null +++ b/include/fb_spi_flash.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Collabora Ltd. + */ + +#ifndef _FB_SPI_FLASH_H_ +#define _FB_SPI_FLASH_H_ + +#include <part.h> + +/** + * fastboot_spi_flash_get_part_info() - Lookup SPI flash partition by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + * Return: 0 if OK, -ENOENT if no partition name was given, -ENODEV on invalid + * raw partition descriptor + */ +int fastboot_spi_flash_get_part_info(const char *part_name, + struct disk_partition *part_info, + char *response); + +/** + * fastboot_spi_flash_write() - Write image to SPI flash for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response); + +/** + * fastboot_spi_flash_erase() - Erase SPI flash for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_erase(const char *cmd, char *response); +#endif diff --git a/include/fpga.h b/include/fpga.h index 4cc44164b2f..a144238e66a 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -79,7 +79,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); const fpga_desc *fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); + size_t bsize); int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ diff --git a/include/init.h b/include/init.h index 2c10171359c..1e375da4893 100644 --- a/include/init.h +++ b/include/init.h @@ -18,7 +18,7 @@ * In case of the EFI app the UEFI firmware provides the low-level * initialisation. */ -#ifdef CONFIG_EFI +#ifdef CONFIG_EFI_CLIENT #define ll_boot_init() false #else #include <asm/global_data.h> diff --git a/include/k3_bist.h b/include/k3_bist.h new file mode 100644 index 00000000000..cc650f5a8c4 --- /dev/null +++ b/include/k3_bist.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Neha Malcom Francis <n-francis@ti.com> + * + */ + +#ifndef _INCLUDE_BIST_H_ +#define _INCLUDE_BIST_H_ + +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_ID_MCU_R5FSS2_CORE0 0x0A +#define PROC_ID_MCU_R5FSS2_CORE1 0x0B +#define PROC_BOOT_CTRL_FLAG_R5_LPSC 0x00000002 + +#define TISCI_DEV_PBIST14 237 +#define TISCI_DEV_R5FSS2_CORE0 343 +#define TISCI_DEV_R5FSS2_CORE1 344 + +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF 0 +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION 1 +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_ON 2 + +#define TISCI_BIT(n) ((1) << (n)) + +struct bist_ops { + int (*run_lbist)(void); + int (*run_lbist_post)(void); + int (*run_pbist_post)(void); + int (*run_pbist_neg)(void); + int (*run_pbist_rom)(void); + int (*run_pbist)(void); +}; + +void lbist_enable_isolation(void); +void lbist_disable_isolation(void); +int prepare_pbist(struct ti_sci_handle *handle); +int deprepare_pbist(struct ti_sci_handle *handle); +int prepare_lbist(struct ti_sci_handle *handle); +int deprepare_lbist(struct ti_sci_handle *handle); + +#endif /* _INCLUDE_BIST_H_ */ diff --git a/include/stratixII.h b/include/stratixII.h index 3c06bb2955a..785cdf41cb8 100644 --- a/include/stratixII.h +++ b/include/stratixII.h @@ -6,8 +6,8 @@ #ifndef _STRATIXII_H_ #define _STRATIXII_H_ -extern int StratixII_load (Altera_desc * desc, void *image, size_t size); -extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize); -extern int StratixII_info (Altera_desc * desc); +int StratixII_load(Altera_desc *desc, const void *buf, size_t size); +int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize); +int StratixII_info(Altera_desc *desc); #endif /* _STRATIXII_H_ */ diff --git a/lib/Kconfig b/lib/Kconfig index 6a89f797bef..fbc9de90669 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1096,7 +1096,7 @@ config VPL_OF_LIBFDT_ASSUME_MASK unsafe execution. See FDT_ASSUME_PERFECT, etc. in libfdt_internal.h menu "System tables" - depends on (!EFI && !SYS_COREBOOT) || (ARM && EFI_LOADER) + depends on (!EFI_CLIENT && !SYS_COREBOOT) || (ARM && EFI_LOADER) config BLOBLIST_TABLES bool "Put tables in a bloblist" diff --git a/lib/Makefile b/lib/Makefile index 18ae0cd87bf..2643bfc867c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -5,7 +5,7 @@ ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_EFI) += efi/ +obj-$(CONFIG_EFI_CLIENT) += efi_client/ obj-$(CONFIG_EFI_LOADER) += efi_driver/ obj-$(CONFIG_EFI_LOADER) += efi_loader/ obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += efi_selftest/ diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig index 81ed3e66b34..fc6d5b6d6c2 100644 --- a/lib/efi/Kconfig +++ b/lib/efi/Kconfig @@ -1,79 +1,12 @@ -menu "U-Boot as UEFI application" - depends on X86 +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Simon Glass <sjg@chromium.org> +# config EFI - bool "Support running U-Boot from EFI" - depends on X86 - imply X86_TSC_READ_BASE + bool help - U-Boot can be started from EFI on certain platforms. This allows - EFI to perform most of the system init and then jump to U-Boot for - final system boot. Another option is to run U-Boot as an EFI - application, with U-Boot using EFI's drivers instead of its own. + Indicates that EFI functionality is enabled, either via EFI_CLIENT or + EFI_LOADER -choice - prompt "Select EFI mode to use" - depends on X86 && EFI - -config EFI_APP - bool "Support running as an EFI application" - select CHARSET - help - Build U-Boot as an application which can be started from EFI. This - is useful for examining a platform in the early stages of porting - U-Boot to it. It allows only very basic functionality, such as a - command prompt and memory and I/O functions. Use 'reset' to return - to EFI. - -config EFI_STUB - bool "Support running as an EFI payload" - -endchoice - -choice - prompt "EFI app 32/64-bit selection" - depends on EFI_APP - help - EFI does not support mixing 32-bit and 64-bit modes. This is a - significant problem because it means that you must build a stub with - the correct type for EFI to load it correctly. If you are using - 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do - this may produce no error message - it just won't start! - -config EFI_APP_32BIT - bool "Produce an app for running with 32-bit EFI" - -config EFI_APP_64BIT - bool "Produce an app for running with 64-bit EFI" - -endchoice - -choice - prompt "EFI stub 32/64-bit selection" - depends on EFI_STUB - help - EFI does not support mixing 32-bit and 64-bit modes. This is a - significant problem because it means that you must build a stub with - the correct type for EFI to load it correctly. If you are using - 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do - this may produce no error message - it just won't start! - -config EFI_STUB_32BIT - bool "Produce a stub for running with 32-bit EFI" - -config EFI_STUB_64BIT - bool "Produce a stub for running with 64-bit EFI" - -endchoice - -config EFI_RAM_SIZE - hex "Amount of EFI RAM for U-Boot" - depends on EFI_APP - default 0x10000000 - help - Set the amount of EFI RAM which is claimed by U-Boot for its own - use. U-Boot allocates this from EFI on start-up (along with a few - other smaller amounts) and it can never be increased after that. - It is used as the RAM size in with U-Boot. - -endmenu + This is used to provide libraries shared by both. diff --git a/lib/efi_client/Kconfig b/lib/efi_client/Kconfig new file mode 100644 index 00000000000..723c98d2a75 --- /dev/null +++ b/lib/efi_client/Kconfig @@ -0,0 +1,80 @@ +menu "U-Boot as UEFI application" + depends on X86 + +config EFI_CLIENT + bool "Support running U-Boot from EFI" + depends on X86 + imply X86_TSC_READ_BASE + select EFI + help + U-Boot can be started from EFI on certain platforms. This allows + EFI to perform most of the system init and then jump to U-Boot for + final system boot. Another option is to run U-Boot as an EFI + application, with U-Boot using EFI's drivers instead of its own. + +choice + prompt "Select EFI mode to use" + depends on X86 && EFI_CLIENT + +config EFI_APP + bool "Support running as an EFI application" + select CHARSET + help + Build U-Boot as an application which can be started from EFI. This + is useful for examining a platform in the early stages of porting + U-Boot to it. It allows only very basic functionality, such as a + command prompt and memory and I/O functions. Use 'reset' to return + to EFI. + +config EFI_STUB + bool "Support running as an EFI payload" + +endchoice + +choice + prompt "EFI app 32/64-bit selection" + depends on EFI_APP + help + EFI does not support mixing 32-bit and 64-bit modes. This is a + significant problem because it means that you must build a stub with + the correct type for EFI to load it correctly. If you are using + 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do + this may produce no error message - it just won't start! + +config EFI_APP_32BIT + bool "Produce an app for running with 32-bit EFI" + +config EFI_APP_64BIT + bool "Produce an app for running with 64-bit EFI" + +endchoice + +choice + prompt "EFI stub 32/64-bit selection" + depends on EFI_STUB + help + EFI does not support mixing 32-bit and 64-bit modes. This is a + significant problem because it means that you must build a stub with + the correct type for EFI to load it correctly. If you are using + 32-bit EFI, select 32-bit here, else select 64-bit. Failure to do + this may produce no error message - it just won't start! + +config EFI_STUB_32BIT + bool "Produce a stub for running with 32-bit EFI" + +config EFI_STUB_64BIT + bool "Produce a stub for running with 64-bit EFI" + +endchoice + +config EFI_RAM_SIZE + hex "Amount of EFI RAM for U-Boot" + depends on EFI_APP + default 0x10000000 + help + Set the amount of EFI RAM which is claimed by U-Boot for its own + use. U-Boot allocates this from EFI on start-up (along with a few + other smaller amounts) and it can never be increased after that. + It is used as the RAM size in with U-Boot. + +endmenu diff --git a/lib/efi/Makefile b/lib/efi_client/Makefile index 232fa684360..232fa684360 100644 --- a/lib/efi/Makefile +++ b/lib/efi_client/Makefile diff --git a/lib/efi/efi.c b/lib/efi_client/efi.c index bcb34d67465..bcb34d67465 100644 --- a/lib/efi/efi.c +++ b/lib/efi_client/efi.c diff --git a/lib/efi/efi_app.c b/lib/efi_client/efi_app.c index 9b94a93ee4f..9b94a93ee4f 100644 --- a/lib/efi/efi_app.c +++ b/lib/efi_client/efi_app.c diff --git a/lib/efi/efi_app_init.c b/lib/efi_client/efi_app_init.c index c5e4192fe06..c5e4192fe06 100644 --- a/lib/efi/efi_app_init.c +++ b/lib/efi_client/efi_app_init.c diff --git a/lib/efi/efi_info.c b/lib/efi_client/efi_info.c index 5b564c5651d..5b564c5651d 100644 --- a/lib/efi/efi_info.c +++ b/lib/efi_client/efi_info.c diff --git a/lib/efi/efi_stub.c b/lib/efi_client/efi_stub.c index a083c7f1e9b..a083c7f1e9b 100644 --- a/lib/efi/efi_stub.c +++ b/lib/efi_client/efi_stub.c diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 077466f01f0..c2aa88f59fb 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -16,6 +16,7 @@ config EFI_LOADER depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT depends on !EFI_APP default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8 + select EFI select CHARSET # We need to send DM events, dynamically, in the EFI block driver select DM_EVENT @@ -595,6 +596,8 @@ config BOOTEFI_TESTAPP_COMPILE endif +source "lib/efi_client/Kconfig" + source "lib/efi/Kconfig" endmenu diff --git a/lib/efi_loader/efi_debug_support.c b/lib/efi_loader/efi_debug_support.c index 186bdbce750..490b0bb7088 100644 --- a/lib/efi_loader/efi_debug_support.c +++ b/lib/efi_loader/efi_debug_support.c @@ -22,7 +22,7 @@ struct efi_debug_image_info_table_header efi_m_debug_info_table_header = { */ static u32 efi_m_max_table_entries; -#define EFI_DEBUG_TABLE_ENTRY_SIZE (sizeof(union efi_debug_image_info *)) +#define EFI_DEBUG_TABLE_ENTRY_SIZE (sizeof(union efi_debug_image_info)) /** * efi_initialize_system_table_pointer() - Initialize system table pointer diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 75501e21557..216df83de67 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -332,6 +332,8 @@ static efi_status_t efi_fill_image_desc_array( return EFI_BUFFER_TOO_SMALL; } + if (!image_info) + return EFI_INVALID_PARAMETER; *image_info_size = total_size; ret = efi_gen_capsule_guids(); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 6dfc698a247..b77c2f980cc 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -714,6 +714,8 @@ efi_status_t efi_realloc(void **ptr, size_t size) sizeof(struct efi_pool_allocation); new_ptr = efi_alloc(size); + if (!new_ptr) + return EFI_OUT_OF_RESOURCES; /* copy old data to new alloced buffer */ memcpy(new_ptr, *ptr, min(size, old_size)); diff --git a/lib/efi_selftest/efi_selftest_debug_support.c b/lib/efi_selftest/efi_selftest_debug_support.c index 9ca8b3f82f5..ac77caaf561 100644 --- a/lib/efi_selftest/efi_selftest_debug_support.c +++ b/lib/efi_selftest/efi_selftest_debug_support.c @@ -9,6 +9,7 @@ #include <efi_loader.h> #include <efi_selftest.h> +#include <linux/sizes.h> /** * efi_st_debug_support_execute() - execute test @@ -21,6 +22,12 @@ static int efi_st_debug_support_execute(void) { struct efi_debug_image_info_table_header *efi_st_debug_info_table_header = NULL; efi_guid_t efi_debug_image_info_table_guid = EFI_DEBUG_IMAGE_INFO_TABLE_GUID; + struct efi_mem_desc *memory_map; + efi_uintn_t map_size = 0; + efi_uintn_t map_key; + efi_uintn_t desc_size; + u32 desc_version; + efi_status_t ret; /* get EFI_DEBUG_IMAGE_INFO_TABLE */ efi_st_debug_info_table_header = efi_st_get_config_table(&efi_debug_image_info_table_guid); @@ -30,7 +37,66 @@ static int efi_st_debug_support_execute(void) return EFI_ST_FAILURE; } - return EFI_ST_SUCCESS; + /* Load memory map */ + ret = st_boottime->get_memory_map(&map_size, NULL, &map_key, &desc_size, + &desc_version); + if (ret != EFI_BUFFER_TOO_SMALL) { + efi_st_error + ("GetMemoryMap did not return EFI_BUFFER_TOO_SMALL\n"); + return EFI_ST_FAILURE; + } + /* Allocate extra space for newly allocated memory */ + map_size += sizeof(struct efi_mem_desc); + ret = st_boottime->allocate_pool(EFI_BOOT_SERVICES_DATA, map_size, + (void **)&memory_map); + if (ret != EFI_SUCCESS) { + efi_st_error("AllocatePool failed\n"); + return EFI_ST_FAILURE; + } + ret = st_boottime->get_memory_map(&map_size, memory_map, &map_key, + &desc_size, &desc_version); + if (ret != EFI_SUCCESS) { + efi_st_error("GetMemoryMap failed\n"); + return EFI_ST_FAILURE; + } + /* Find the system table pointer */ + for (efi_uintn_t i = 0; map_size; ++i, map_size -= desc_size) { + struct efi_mem_desc *entry = &memory_map[i]; + u64 end; + + if (entry->type != EFI_RUNTIME_SERVICES_DATA) + continue; + + end = entry->physical_start + + (entry->num_pages << EFI_PAGE_SHIFT); + for (u64 pos = ALIGN(entry->physical_start, SZ_4M); + pos <= end; pos += SZ_4M) { + struct efi_system_table_pointer *systab_pointer = + (void *)(uintptr_t)pos; + + /* check for overflow */ + if (pos < entry->physical_start) + break; + if (systab_pointer->signature == + EFI_SYSTEM_TABLE_SIGNATURE) { + if (systab_pointer->efi_system_table_base != + (uintptr_t)st_systable) { + efi_st_error("Wrong system table address\n"); + ret = EFI_ST_FAILURE; + goto out; + } + ret = EFI_ST_SUCCESS; + goto out; + } + } + } + efi_st_error("System table pointer not found\n"); + ret = EFI_ST_FAILURE; + +out: + st_boottime->free_pool(memory_map); + + return ret; } EFI_UNIT_TEST(debug_support) = { diff --git a/lib/efi_selftest/efi_selftest_esrt.c b/lib/efi_selftest/efi_selftest_esrt.c index b7688deb496..7eadac90fbc 100644 --- a/lib/efi_selftest/efi_selftest_esrt.c +++ b/lib/efi_selftest/efi_selftest_esrt.c @@ -69,10 +69,12 @@ EFIAPI efi_test_fmp_get_image_info(struct efi_firmware_management_protocol *this if (package_version_name) *package_version_name = NULL; - if (*image_info_size < sizeof(*image_info)) { - *image_info_size = *descriptor_size * *descriptor_count; + if (*image_info_size < sizeof(*image_info) * TEST_ESRT_NUM_ENTRIES) { + *image_info_size = sizeof(*image_info) * TEST_ESRT_NUM_ENTRIES; return EFI_BUFFER_TOO_SMALL; } + if (!image_info) + return EFI_INVALID_PARAMETER; for (int idx = 0; idx < TEST_ESRT_NUM_ENTRIES; idx++) image_info[idx] = static_img_info[idx]; diff --git a/lib/lmb.c b/lib/lmb.c index e5a0677e3f9..e2d9fe86c14 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -8,6 +8,7 @@ #include <alist.h> #include <efi_loader.h> +#include <env.h> #include <event.h> #include <image.h> #include <mapmem.h> @@ -214,8 +215,6 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, coalesced++; break; - - return -1; } } @@ -538,6 +537,7 @@ static void lmb_reserve_uboot_region(void) int bank; ulong end, bank_end; phys_addr_t rsv_start; + ulong pram = 0; rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE; end = gd->ram_top; @@ -548,6 +548,11 @@ static void lmb_reserve_uboot_region(void) */ debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start); +#ifdef CFG_PRAM + pram = env_get_ulong("pram", 10, CFG_PRAM); + pram = pram << 10; /* size is in kB */ +#endif + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { if (!gd->bd->bi_dram[bank].size || rsv_start < gd->bd->bi_dram[bank].start) @@ -560,7 +565,8 @@ static void lmb_reserve_uboot_region(void) if (bank_end > end) bank_end = end - 1; - lmb_reserve(rsv_start, bank_end - rsv_start + 1, LMB_NOOVERWRITE); + lmb_reserve(rsv_start, bank_end - rsv_start - pram + 1, + LMB_NOOVERWRITE); if (gd->flags & GD_FLG_SKIP_RELOC) lmb_reserve((phys_addr_t)(uintptr_t)_start, diff --git a/lib/uuid.c b/lib/uuid.c index a1c88b9a622..8d99b540d9f 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -94,7 +94,7 @@ static const struct { "system", "EFI System Partition", PARTITION_SYSTEM_GUID, }, -#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI) +#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_CLIENT) { NULL, "Device Path", PARTITION_SYSTEM_GUID, @@ -281,7 +281,7 @@ static const struct { EFI_CERT_TYPE_PKCS7_GUID, }, #endif -#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI) +#if defined(CONFIG_CMD_EFIDEBUG) || defined(CONFIG_EFI_CLIENT) { "EFI_LZMA_COMPRESSED", NULL, EFI_LZMA_COMPRESSED }, { "EFI_DXE_SERVICES", NULL, EFI_DXE_SERVICES }, { "EFI_HOB_LIST", NULL, EFI_HOB_LIST }, diff --git a/test/dm/blk.c b/test/dm/blk.c index aa5cbc63777..1b928b27d9c 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -229,30 +229,7 @@ static int dm_test_blk_flags(struct unit_test_state *uts) { struct udevice *dev; - /* Iterate through devices without probing them */ - ut_assertok(blk_find_first(BLKF_BOTH, &dev)); - ut_assertnonnull(dev); - ut_asserteq_str("mmc2.blk", dev->name); - - ut_assertok(blk_find_next(BLKF_BOTH, &dev)); - ut_assertnonnull(dev); - ut_asserteq_str("mmc1.blk", dev->name); - - ut_assertok(blk_find_next(BLKF_BOTH, &dev)); - ut_assertnonnull(dev); - ut_asserteq_str("mmc0.blk", dev->name); - - ut_asserteq(-ENODEV, blk_find_next(BLKF_BOTH, &dev)); - ut_assertnull(dev); - - /* All devices are removable until probed */ - ut_asserteq(-ENODEV, blk_find_first(BLKF_FIXED, &dev)); - - ut_assertok(blk_find_first(BLKF_REMOVABLE, &dev)); - ut_assertnonnull(dev); - ut_asserteq_str("mmc2.blk", dev->name); - - /* Now probe them and iterate again */ + /* Probe and look through block devices */ ut_assertok(blk_first_device_err(BLKF_BOTH, &dev)); ut_assertnonnull(dev); ut_asserteq_str("mmc2.blk", dev->name); @@ -289,30 +266,13 @@ static int dm_test_blk_flags(struct unit_test_state *uts) } DM_TEST(dm_test_blk_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT); -/* Test blk_foreach() and friend */ +/* Test blk_foreach_probe() */ static int dm_test_blk_foreach(struct unit_test_state *uts) { struct udevice *dev; int found; - /* Test blk_foreach() - use the 3rd bytes of the name (0/1/2) */ - found = 0; - blk_foreach(BLKF_BOTH, dev) - found |= 1 << dectoul(&dev->name[3], NULL); - ut_asserteq(7, found); - - /* All devices are removable until probed */ - found = 0; - blk_foreach(BLKF_FIXED, dev) - found |= 1 << dectoul(&dev->name[3], NULL); - ut_asserteq(0, found); - - found = 0; - blk_foreach(BLKF_REMOVABLE, dev) - found |= 1 << dectoul(&dev->name[3], NULL); - ut_asserteq(7, found); - - /* Now try again with the probing functions */ + /* The test device tree has two fixed and one removable block device(s) */ found = 0; blk_foreach_probe(BLKF_BOTH, dev) found |= 1 << dectoul(&dev->name[3], NULL); diff --git a/test/dm/core.c b/test/dm/core.c index 959b834576f..53693f4f7ed 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -167,8 +167,6 @@ static int dm_test_autobind_uclass_pdata_alloc(struct unit_test_state *uts) for (uclass_find_first_device(UCLASS_TEST, &dev); dev; uclass_find_next_device(&dev)) { - ut_assertnonnull(dev); - uc_pdata = dev_get_uclass_plat(dev); ut_assert(uc_pdata); } @@ -223,8 +221,6 @@ static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts) for (uclass_find_first_device(UCLASS_TEST, &dev); dev; uclass_find_next_device(&dev)) { - ut_assertnonnull(dev); - uc_pdata = dev_get_uclass_plat(dev); ut_assert(uc_pdata); ut_assert(uc_pdata->intval1 == TEST_UC_PDATA_INTVAL1); @@ -734,114 +730,90 @@ static int dm_test_device_reparent(struct unit_test_state *uts) /* Re-parent top-level children with no grandchildren. */ ut_assertok(device_reparent(top[3], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(top[4], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Re-parent top-level children with grandchildren. */ ut_assertok(device_reparent(top[2], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(top[5], top[2])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Re-parent grandchildren. */ ut_assertok(device_reparent(grandchild[0], top[1])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(grandchild[1], top[1])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Remove re-pareneted devices. */ ut_assertok(device_remove(top[3], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[4], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[5], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[2], DM_REMOVE_NORMAL)); - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(grandchild[0], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(grandchild[1], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Try the same with unbind */ ut_assertok(device_unbind(top[3])); @@ -1090,12 +1062,9 @@ static int dm_test_uclass_devices_find(struct unit_test_state *uts) struct udevice *dev; int ret; - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(uclass_find_first_device(UCLASS_TEST_DUMMY, &dev)); ut_assertnull(dev); @@ -1121,18 +1090,16 @@ static int dm_test_uclass_devices_find_by_name(struct unit_test_state *uts) * this will fail on checking condition: testdev == finddev, since the * uclass_find_device_by_name(), returns the first device by given name. */ - for (ret = uclass_find_first_device(UCLASS_TEST_FDT, &testdev); - testdev; - ret = uclass_find_next_device(&testdev)) { - ut_assertok(ret); - ut_assertnonnull(testdev); + ret = uclass_find_first_device(UCLASS_TEST_FDT, &testdev); + ut_assertok(ret); + ut_assertnonnull(testdev); + for (; testdev; uclass_find_next_device(&testdev)) { findret = uclass_find_device_by_name(UCLASS_TEST_FDT, testdev->name, &finddev); ut_assertok(findret); - ut_assert(testdev); ut_asserteq_str(testdev->name, finddev->name); ut_asserteq_ptr(testdev, finddev); } diff --git a/test/lib/abuf.c b/test/lib/abuf.c index 97b128c01c0..3dced1ddb11 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -12,6 +12,7 @@ static char test_data[] = "1234"; #define TEST_DATA_LEN sizeof(test_data) +#define HUGE_ALLOC_SIZE 0x60000000 /* Test abuf_set() */ static int lib_test_abuf_set(struct unit_test_state *uts) @@ -93,13 +94,6 @@ static int lib_test_abuf_realloc(struct unit_test_state *uts) { struct abuf buf; ulong start; - void *ptr; - - /* - * TODO: crashes on sandbox sometimes due to an apparent bug in - * realloc(). - */ - return 0; start = ut_check_free(); @@ -116,23 +110,18 @@ static int lib_test_abuf_realloc(struct unit_test_state *uts) ut_assertnonnull(buf.data); ut_asserteq(TEST_DATA_LEN, buf.size); ut_asserteq(true, buf.alloced); - ptr = buf.data; /* - * Make it smaller; the pointer should remain the same. Note this relies - * on knowledge of how U-Boot's realloc() works + * Make it smaller. */ ut_asserteq(true, abuf_realloc(&buf, TEST_DATA_LEN - 1)); ut_asserteq(TEST_DATA_LEN - 1, buf.size); ut_asserteq(true, buf.alloced); - ut_asserteq_ptr(ptr, buf.data); /* - * Make it larger, forcing reallocation. Note this relies on knowledge - * of how U-Boot's realloc() works + * Make it larger. */ ut_asserteq(true, abuf_realloc(&buf, 0x1000)); - ut_assert(buf.data != ptr); ut_asserteq(0x1000, buf.size); ut_asserteq(true, buf.alloced); @@ -210,19 +199,12 @@ static int lib_test_abuf_large(struct unit_test_state *uts) ulong start; size_t size; int delta; - void *ptr; - - /* - * This crashes at present due to trying to allocate more memory than - * available, which breaks something on sandbox. - */ - return 0; start = ut_check_free(); /* Try an impossible size */ abuf_init(&buf); - ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN)); + ut_asserteq(false, abuf_realloc(&buf, HUGE_ALLOC_SIZE)); ut_assertnull(buf.data); ut_asserteq(0, buf.size); ut_asserteq(false, buf.alloced); @@ -237,13 +219,11 @@ static int lib_test_abuf_large(struct unit_test_state *uts) ut_assertnonnull(buf.data); ut_asserteq(TEST_DATA_LEN, buf.size); ut_asserteq(true, buf.alloced); - ptr = buf.data; delta = ut_check_delta(start); ut_assert(delta > 0); /* try to increase it */ - ut_asserteq(false, abuf_realloc(&buf, CONFIG_SYS_MALLOC_LEN)); - ut_asserteq_ptr(ptr, buf.data); + ut_asserteq(false, abuf_realloc(&buf, HUGE_ALLOC_SIZE)); ut_asserteq(TEST_DATA_LEN, buf.size); ut_asserteq(true, buf.alloced); ut_asserteq(delta, ut_check_delta(start)); @@ -254,8 +234,8 @@ static int lib_test_abuf_large(struct unit_test_state *uts) /* Start with a huge unallocated buf and try to move it */ abuf_init(&buf); - abuf_map_sysmem(&buf, 0, CONFIG_SYS_MALLOC_LEN); - ut_asserteq(CONFIG_SYS_MALLOC_LEN, buf.size); + abuf_map_sysmem(&buf, 0, HUGE_ALLOC_SIZE); + ut_asserteq(HUGE_ALLOC_SIZE, buf.size); ut_asserteq(false, buf.alloced); ut_assertnull(abuf_uninit_move(&buf, &size)); @@ -278,12 +258,6 @@ static int lib_test_abuf_uninit_move(struct unit_test_state *uts) start = ut_check_free(); - /* - * TODO: crashes on sandbox sometimes due to an apparent bug in - * realloc(). - */ - return 0; - /* Move an empty buffer */ abuf_init(&buf); ut_assertnull(abuf_uninit_move(&buf, &size)); @@ -383,12 +357,6 @@ static int lib_test_abuf_init_move(struct unit_test_state *uts) struct abuf buf; void *ptr; - /* - * TODO: crashes on sandbox sometimes due to an apparent bug in - * realloc(). - */ - return 0; - ptr = strdup(test_data); ut_assertnonnull(ptr); diff --git a/test/py/tests/test_fit_mkimage_validate.py b/test/py/tests/test_fit_mkimage_validate.py index af56f08ca10..ef974c8c762 100644 --- a/test/py/tests/test_fit_mkimage_validate.py +++ b/test/py/tests/test_fit_mkimage_validate.py @@ -7,6 +7,7 @@ import os import subprocess import pytest import fit_util +import re @pytest.mark.boardspec('sandbox') @pytest.mark.requiredtool('dtc') @@ -56,3 +57,47 @@ def test_fit_invalid_image_reference(ubman): assert result.returncode != 0, "mkimage should fail due to missing image reference" assert "references undefined image 'notexist'" in result.stderr +def test_fit_invalid_default_config(ubman): + """Test that mkimage fails when default config is missing""" + + its_fname = fit_util.make_fname(ubman, "invalid.its") + itb_fname = fit_util.make_fname(ubman, "invalid.itb") + kernel = fit_util.make_kernel(ubman, 'kernel.bin', 'kernel') + + # Write ITS with an invalid reference to a nonexistent default config + its_text = ''' +/dts-v1/; + +/ { + images { + kernel@1 { + description = "Test Kernel"; + data = /incbin/("kernel.bin"); + type = "kernel"; + arch = "sandbox"; + os = "linux"; + compression = "none"; + load = <0x40000>; + entry = <0x40000>; + }; + }; + + configurations { + default = "conf@1"; + conf@2 { + kernel = "kernel@1"; + }; + }; +}; +''' + + with open(its_fname, 'w') as f: + f.write(its_text) + + mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage') + cmd = [mkimage, '-f', its_fname, itb_fname] + + result = subprocess.run(cmd, capture_output=True, text=True) + + assert result.returncode != 0, "mkimage should fail due to missing default config" + assert re.search(r"Default configuration '.*' not found under /configurations", result.stderr) diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py index 5879f377231..9cc4b756b3f 100644 --- a/tools/binman/etype/cbfs.py +++ b/tools/binman/etype/cbfs.py @@ -5,6 +5,7 @@ # Entry-type module for a Coreboot Filesystem (CBFS) # +from __future__ import annotations from collections import OrderedDict from binman import cbfs_util diff --git a/tools/binman/etype/mkimage.py b/tools/binman/etype/mkimage.py index 75e59c3d3a3..9fba902bdad 100644 --- a/tools/binman/etype/mkimage.py +++ b/tools/binman/etype/mkimage.py @@ -5,6 +5,7 @@ # Entry-type module for producing an image using mkimage # +from __future__ import annotations from collections import OrderedDict from binman.entry import Entry diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py index 03c4f7c6ec7..6a26d687056 100644 --- a/tools/binman/etype/section.py +++ b/tools/binman/etype/section.py @@ -8,6 +8,7 @@ Sections are entries which can contain other entries. This allows hierarchical images to be created. """ +from __future__ import annotations from collections import OrderedDict import concurrent.futures import re diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index ceb7a25ad4d..5b4c75f8400 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:jammy-20250404 +FROM ubuntu:jammy-20250714 LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>" LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container" @@ -125,6 +125,7 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ python3-dev \ python3-pip \ python3-sphinx \ + python3-tomli \ python3-venv \ rpm2cpio \ sbsigntool \ @@ -218,13 +219,10 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ - git checkout v8.2.0 && \ + git checkout v10.0.2 && \ # config user.name and user.email to make 'git am' happy git config user.name u-boot && \ git config user.email u-boot@denx.de && \ - git format-patch 0c7ffc977195~..0c7ffc977195 && \ - git am 0001-hw-net-cadence_gem-Fix-MDIO_OP_xxx-values.patch && \ - git cherry-pick d3c79c3974 && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu @@ -294,8 +292,8 @@ RUN mkdir /tmp/trace && \ rm -rf /tmp/trace # Build coreboot -RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp -xJ && \ - cd /tmp/coreboot-24.08 && \ +RUN wget -O - https://coreboot.org/releases/coreboot-25.03.tar.xz | tar -C /tmp -xJ && \ + cd /tmp/coreboot-25.03 && \ make crossgcc-i386 CPUS=$(nproc) && \ make -C payloads/coreinfo olddefconfig && \ make -C payloads/coreinfo && \ @@ -306,7 +304,7 @@ RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp make -j $(nproc) && \ sudo mkdir /opt/coreboot && \ sudo cp build/coreboot.rom build/cbfstool /opt/coreboot/ && \ - rm -rf /tmp/coreboot-24.08 + rm -rf /tmp/coreboot-25.03 # Create our user/group RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot diff --git a/tools/fit_image.c b/tools/fit_image.c index ad0ffa39c6a..331be5ae71d 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -756,6 +756,8 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) } confs = fdt_path_offset(fdt, FIT_CONFS_PATH); + const char *default_conf = + (char *)fdt_getprop(fdt, confs, FIT_DEFAULT_PROP, NULL); static const char * const props[] = { FIT_KERNEL_PROP, FIT_RAMDISK_PROP, FIT_FDT_PROP, @@ -764,6 +766,14 @@ static int fit_import_data(struct image_tool_params *params, const char *fname) FIT_FIRMWARE_PROP, FIT_SCRIPT_PROP}; + if (default_conf && fdt_subnode_offset(fdt, confs, default_conf) < 0) { + fprintf(stderr, + "Error: Default configuration '%s' not found under /configurations\n", + default_conf); + ret = FDT_ERR_NOTFOUND; + goto err_munmap; + } + fdt_for_each_subnode(node, fdt, confs) { const char *conf_name = fdt_get_name(fdt, node, NULL); diff --git a/tools/patman/test_cseries.py b/tools/patman/test_cseries.py index e58f2f68333..4c211c8ee89 100644 --- a/tools/patman/test_cseries.py +++ b/tools/patman/test_cseries.py @@ -3278,7 +3278,7 @@ Date: .* self.assertIn('bootm.c:1: check: Avoid CamelCase: <Fix>', err.getvalue()) self.assertIn( - 'Cc: Anatolij Gustschin <agust@denx.de>', out.getvalue()) + 'Cc: Anatolij Gustschin <ag.dev.uboot@gmail.com>', out.getvalue()) self.assertTrue(os.path.exists(os.path.join( self.tmpdir, '0001-video-Some-video-improvements.patch'))) |