diff options
200 files changed, 11155 insertions, 9765 deletions
@@ -125,7 +125,7 @@ Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.pala Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com> Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com> Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com> -Stefan Roese <sr@denx.de> <stroese> +Stefan Roese <stefan.roese@mailbox.org> <stroese> Stefano Babic <sbabic@nabladev.com> Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com> No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org> @@ -27,8 +27,22 @@ config DEPRECATED code that relies on deprecated features that will be removed and the conversion deadline has passed. +config COMPILE_TEST + bool "Compile also drivers which will not load" + help + Some drivers can be compiled on a different platform than they are + intended to be run on. Despite they cannot be loaded there (or even + when they load they cannot be used due to missing HW support), + developers still, opposing to distributors, might want to build such + drivers to compile-test them. + + If you are a developer and want to build everything available, say Y + here. If you are a user/distributor, say N here to exclude useless + drivers to be distributed. + config WERROR bool "Compile U-Boot with warnings as errors" + default COMPILE_TEST help A U-Boot build should not cause any compiler warnings, and this enables the '-Werror' flag to enforce that rule. @@ -523,6 +537,7 @@ config BUILD_TARGET config HAS_BOARD_SIZE_LIMIT bool "Define a maximum size for the U-Boot image" + depends on !COMPILE_TEST default y if RCAR_32 || RCAR_64 help In some cases, we need to enforce a hard limit on how big the U-Boot @@ -541,6 +556,7 @@ config BOARD_SIZE_LIMIT config SYS_CUSTOM_LDSCRIPT bool "Use a custom location for the U-Boot linker script" + depends on !COMPILE_TEST help Normally when linking U-Boot we will look in the board directory, the CPU directory and finally the "cpu" directory of the architecture diff --git a/MAINTAINERS b/MAINTAINERS index d5264c8f5df..f914fc54f54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -361,7 +361,7 @@ S: Maintained F: drivers/misc/ls2_sfp.c ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: arch/arm/mach-kirkwood/ @@ -384,7 +384,7 @@ F: drivers/watchdog/orion_wdt.c F: include/configs/mv-common.h ARM MARVELL PCIE CONTROLLER DRIVERS -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/pci/pci-aardvark.c @@ -400,7 +400,7 @@ F: include/configs/pxa1908.h ARM MARVELL SERIAL DRIVERS M: Pali Rohár <pali@kernel.org> -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/serial/serial_mvebu_a3700.c @@ -1022,7 +1022,7 @@ S: Maintained F: cmd/cat.c CFI FLASH -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-cfi-flash.git F: drivers/mtd/cfi_flash.c @@ -1053,7 +1053,7 @@ F: cmd/cpu.c F: doc/usage/cpu.rst CYCLIC -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained F: cmd/cyclic.c F: common/cyclic.c @@ -1251,7 +1251,7 @@ F: drivers/i2c/ KWBIMAGE / KWBOOT TOOLS M: Pali Rohár <pali@kernel.org> M: Marek Behún <kabel@kernel.org> -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: doc/README.kwbimage @@ -1576,6 +1576,7 @@ M: Yao Zi <ziyao@disroot.org> S: Maintained F: arch/riscv/cpu/th1520/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/net/dwmac_thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/ram/thead/th1520_ddr.c @@ -1864,7 +1865,7 @@ F: common/spl_reloc.c F: include/vbe.h VIDEO -M: Anatolij Gustschin <agust@denx.de> +M: Anatolij Gustschin <ag.dev.uboot@gmail.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-video.git F: drivers/video/ @@ -1883,7 +1884,7 @@ F: test/dm/virtio.c F: doc/develop/driver-model/virtio.rst WATCHDOG -M: Stefan Roese <sr@denx.de> +M: Stefan Roese <stefan.roese@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git F: cmd/wdt.c @@ -416,8 +416,8 @@ HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null) HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null) HOST_LFS_LIBS := $(shell getconf LFS_LIBS 2>/dev/null) -HOSTCC = gcc -HOSTCXX = g++ +HOSTCC = cc +HOSTCXX = c++ KBUILD_HOSTCFLAGS := -Wall -Wstrict-prototypes -O2 \ -fomit-frame-pointer -std=gnu11 $(HOST_LFS_CFLAGS) \ $(HOSTCFLAGS) #-Wmissing-prototypes Enable it and fix warnings @@ -635,8 +635,9 @@ ifeq ($(config-targets),1) # Read arch specific Makefile to set KBUILD_DEFCONFIG as needed. # KBUILD_DEFCONFIG may point out an alternative default configuration # used for 'make defconfig' -# Modified for U-Boot --include arch/$(SRCARCH)/Makefile +# Modified for U-Boot: we don't include arch/$(SRCARCH)/Makefile for config +# targets, which is useless since U-Boot has no architecture defining its own +# KBUILD_{DEF,K}CONFIG, or CROSS_COMPILE. export KBUILD_DEFCONFIG KBUILD_KCONFIG CC_VERSION_TEXT config: scripts_basic outputmakefile FORCE @@ -724,8 +725,10 @@ endif ARCH_CPPFLAGS := ARCH_AFLAGS := ARCH_CFLAGS := -# Modified for U-Boot --include arch/$(SRCARCH)/Makefile +# Modified for U-Boot: we put off the include of arch/$(SRCARCH)/Makefile until +# making sure include/config/auto.conf is up-to-date and include of config.mk, +# because the architecture-specific Makefile may make use of variables defined +# in config.mk. See also the comment about autoconf_is_old. ifeq ($(dot-config),1) ifeq ($(may-sync-config),1) @@ -1394,10 +1394,6 @@ Low Level (hardware related) configuration options: VPL. Code that needs phase-specific behaviour can check this, or (where possible) use xpl_phase() instead. - Note that CONFIG_XPL_BUILD *is* always defined when either - of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be - counter-intuitive and should perhaps be changed. - - CONFIG_TPL_BUILD Set when the currently running compilation is for an artifact that will end up in the TPL build (as opposed to SPL, VPL or diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 5a8c382ed75..ef9087d0197 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -84,6 +84,28 @@ config SYS_FSL_SFP_VER_3_4 endchoice +config FSL_SEC_MON + bool + help + Freescale Security Monitor block is responsible for monitoring + system states. + Security Monitor can be transitioned on any security failures, + like software violations or hardware security violations. + +choice + prompt "Security monitor interaction endianess" + depends on FSL_SEC_MON + default SYS_FSL_SEC_MON_BE if PPC + default SYS_FSL_SEC_MON_LE + +config SYS_FSL_SEC_MON_LE + bool "Security monitor interactions are little endian" + +config SYS_FSL_SEC_MON_BE + bool "Security monitor interactions are big endian" + +endchoice + config SPL_UBOOT_KEY_HASH string "Non-SRK key hash for U-Boot public/private key pair" depends on SPL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9ed55e6cfac..4e7593616d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -835,6 +835,9 @@ config ARCH_K3 select FIT_SIGNATURE if ARM64 select LTO imply TI_SECURE_DEVICE + imply DM_RNG if ARM64 + imply TEE if ARM64 + imply OPTEE if ARM64 config ARCH_OMAP2PLUS bool "TI OMAP2+" @@ -906,6 +909,7 @@ config ARCH_IMX8 config ARCH_IMX8M bool "NXP i.MX8M platform" + select ARCH_MISC_INIT if FSL_CAAM select ARM64 select GPIO_EXTRA_HEADER select MACH_IMX @@ -955,6 +959,7 @@ config ARCH_IMXRT config ARCH_MX23 bool "NXP i.MX23 family" + select ARCH_MISC_INIT select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX @@ -962,17 +967,12 @@ config ARCH_MX23 config ARCH_MX28 bool "NXP i.MX28 family" + select ARCH_MISC_INIT select CPU_ARM926EJS select GPIO_EXTRA_HEADER select MACH_IMX select SUPPORT_SPL -config ARCH_MX31 - bool "NXP i.MX31 family" - select CPU_ARM1136 - select GPIO_EXTRA_HEADER - select MACH_IMX - config ARCH_MX7ULP bool "NXP MX7ULP" select BOARD_POSTCLK_INIT @@ -1109,6 +1109,7 @@ config ARCH_QEMU config ARCH_RENESAS bool "Renesas ARM SoCs" + select ARCH_MISC_INIT if DISPLAY_CPUINFO && !(RZA1 || RZN1) select DM select DM_SERIAL select GPIO_EXTRA_HEADER @@ -1118,7 +1119,6 @@ config ARCH_RENESAS imply FAT_WRITE imply OF_UPSTREAM imply SYS_THUMB_BUILD - imply ARCH_MISC_INIT if DISPLAY_CPUINFO config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" @@ -1547,7 +1547,6 @@ config TARGET_LX2160AQDS config TARGET_LX2162AQDS bool "Support lx2162aqds" select ARCH_LX2162A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -1960,7 +1959,6 @@ config TARGET_SL28 config TARGET_TEN64 bool "Support ten64" select ARCH_LS1088A - select ARCH_MISC_INIT select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT @@ -2318,8 +2316,6 @@ source "arch/arm/mach-octeontx2/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" -source "arch/arm/mach-imx/mx3/Kconfig" - source "arch/arm/mach-imx/mx5/Kconfig" source "arch/arm/mach-imx/mx6/Kconfig" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 46ace7e5fd6..5c8839583aa 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1021A bool + select ARCH_MISC_INIT if FSL_CAAM select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI select LS102XA_STREAM_ID diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 080fe3fc327..20883fe6825 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -77,11 +77,11 @@ config ARCH_LS1043A select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 if !TFABOOT - select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A008997 if USB + select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009660 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT - select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A009798 if USB select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE select SYS_FSL_ERRATUM_A010539 @@ -328,6 +328,7 @@ config ARCH_LX2160A config FSL_LSCH2 bool + select ARCH_MISC_INIT if FSL_CAAM select SKIP_LOWLEVEL_INIT select SYS_FSL_CCSR_GUR_BE select SYS_FSL_CCSR_SCFG_BE diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index 6e799621678..1b5b6270068 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -27,10 +27,6 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - chosen { - stdout-path = &uart0; - }; - vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi index 5ec3b1c51d6..9bf8f9834c9 100644 --- a/arch/arm/dts/imx95-u-boot.dtsi +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -22,12 +22,12 @@ type = "nxp-header-ddrfw"; imx-lpddr-imem { - filename = "lpddr5_imem_v202311.bin"; + filename = "lpddr5_imem_v202409.bin"; type = "blob-ext"; }; imx-lpddr-dmem { - filename = "lpddr5_dmem_v202311.bin"; + filename = "lpddr5_dmem_v202409.bin"; type = "blob-ext"; }; }; @@ -36,12 +36,12 @@ type = "nxp-header-ddrfw"; imx-lpddr-imem-qb { - filename = "lpddr5_imem_qb_v202311.bin"; + filename = "lpddr5_imem_qb_v202409.bin"; type = "blob-ext"; }; imx-lpddr-dmem-qb { - filename = "lpddr5_dmem_qb_v202311.bin"; + filename = "lpddr5_dmem_qb_v202409.bin"; type = "blob-ext"; }; }; diff --git a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts index ec8e7dee271..1068f1a288a 100644 --- a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts +++ b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts @@ -51,6 +51,26 @@ &i2c0 { status = "okay"; + + pca9547@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ivm@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "MAIN_CTRL"; + }; + }; + }; }; &dspi1 { diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts index 03ce3ab4e47..3e8c54d83c9 100644 --- a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts +++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts @@ -44,6 +44,26 @@ &i2c0 { status = "okay"; + + pca9547@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ivm@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "MAIN_CTRL"; + }; + }; + }; }; &ifc { diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 60499189b2c..a9152814245 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -21,11 +21,6 @@ extern void mx27_uart1_init_pins(void); extern void mx27_fec_init_pins(void); #endif /* CONFIG_FEC_MXC */ -#ifdef CONFIG_MMC_MXC -extern void mx27_sd1_init_pins(void); -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MMC_MXC */ - /* AIPI */ struct aipi_regs { u32 psr0; diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h deleted file mode 100644 index e99e115f79e..00000000000 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define MXC_HCLK CONFIG_MX31_HCLK_FREQ - -#define MXC_CLK32 CONFIG_MX31_CLK32 - -enum mxc_clock { - MXC_ARM_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_CSPI_CLK, - MXC_UART_CLK, - MXC_IPU_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); -extern u32 imx_get_uartclk(void); -extern void mx31_gpio_mux(unsigned long mode); -extern void mx31_set_pad(enum iomux_pins pin, u32 config); -extern void mx31_set_gpr(enum iomux_gp_func gp, char en); - -void mx31_uart1_hw_init(void); -void mx31_uart2_hw_init(void); -void mx31_spi2_hw_init(void); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h deleted file mode 100644 index 1bfe28f95c9..00000000000 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> - */ - -#ifndef __ASM_ARCH_MX31_GPIO_H -#define __ASM_ARCH_MX31_GPIO_H - -#include <asm/mach-imx/gpio.h> - -#endif diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h deleted file mode 100644 index a608732f765..00000000000 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ /dev/null @@ -1,905 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - */ - -#ifndef __ASM_ARCH_MX31_IMX_REGS_H -#define __ASM_ARCH_MX31_IMX_REGS_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* Clock control module registers */ -struct clock_control_regs { - u32 ccmr; - u32 pdr0; - u32 pdr1; - u32 rcsr; - u32 mpctl; - u32 upctl; - u32 spctl; - u32 cosr; - u32 cgr0; - u32 cgr1; - u32 cgr2; - u32 wimr0; - u32 ldc; - u32 dcvr0; - u32 dcvr1; - u32 dcvr2; - u32 dcvr3; - u32 ltr0; - u32 ltr1; - u32 ltr2; - u32 ltr3; - u32 ltbr0; - u32 ltbr1; - u32 pmcr0; - u32 pmcr1; - u32 pdr2; -}; - -/* IIM control registers */ -struct iim_regs { - u32 iim_stat; - u32 iim_statm; - u32 iim_err; - u32 iim_emask; - u32 iim_fctl; - u32 iim_ua; - u32 iim_la; - u32 iim_sdat; - u32 iim_prev; - u32 iim_srev; - u32 iim_prg_p; - u32 iim_scs0; - u32 iim_scs1; - u32 iim_scs2; - u32 iim_scs3; - u32 res[0x1f1]; - struct fuse_bank { - u32 fuse_regs[0x20]; - u32 fuse_rsvd[0xe0]; - } bank[3]; -}; - -struct fuse_bank0_regs { - u32 fuse0_5[6]; - u32 usr; - u32 fuse7_15[9]; -}; - -struct fuse_bank2_regs { - u32 fuse0; - u32 uid[8]; - u32 fuse9_15[7]; -}; - -struct iomuxc_regs { - u32 unused1; - u32 unused2; - u32 gpr; -}; - -struct mx3_cpu_type { - u8 srev; - u32 v; -}; - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN(6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN(5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN(4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN(3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN(2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN(1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN(0, 323), - MX31_PIN_PWMO = IOMUX_PIN(9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN(8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN(7, 327), -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* Bit definitions for RCSR register in CCM */ -#define CCM_RCSR_NF16B (1 << 31) -#define CCM_RCSR_NFMS (1 << 30) - -/* WEIM CS control registers */ -struct mx31_weim_cscr { - u32 upper; - u32 lower; - u32 additional; - u32 reserved; -}; - -struct mx31_weim { - struct mx31_weim_cscr cscr[6]; -}; - -/* ESD control registers */ -struct esdc_regs { - u32 ctl0; - u32 cfg0; - u32 ctl1; - u32 cfg1; - u32 misc; - u32 dly[5]; - u32 dlyl; -}; - -#endif - -#define ARCH_MXC - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -#define CCM_BASE 0x53f80000 -#define CCM_CCMR (CCM_BASE + 0x00) -#define CCM_PDR0 (CCM_BASE + 0x04) -#define CCM_PDR1 (CCM_BASE + 0x08) -#define CCM_RCSR (CCM_BASE + 0x0c) -#define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x14) -#define CCM_SPCTL (CCM_BASE + 0x18) -#define CCM_COSR (CCM_BASE + 0x1C) -#define CCM_CGR0 (CCM_BASE + 0x20) -#define CCM_CGR1 (CCM_BASE + 0x24) -#define CCM_CGR2 (CCM_BASE + 0x28) - -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) - -#define MX31_IIM_BASE_ADDR 0x5001C000 -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR - -#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26) -#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) - -#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30) -#define PDR1_USB_PODF(x) (((x) & 0x7) << 27) -#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24) -#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18) -#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15) -#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9) -#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6) -#define PDR1_SSI1_PODF(x) ((x) & 0x3f) - -#define PLL_BRMO(x) (((x) & 0x1) << 31) -#define PLL_PD(x) (((x) & 0xf) << 26) -#define PLL_MFD(x) (((x) & 0x3ff) << 16) -#define PLL_MFI(x) (((x) & 0xf) << 10) -#define PLL_MFN(x) (((x) & 0x3ff) << 0) - -#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f) -#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7) -#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f) -#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7) -#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7) -#define GET_PDR0_IPG_PODF(x) (((x) >> 6) & 0x3) -#define GET_PDR0_MAX_PODF(x) (((x) >> 3) & 0x7) -#define GET_PDR0_MCU_PODF(x) ((x) & 0x7) - -#define GET_PLL_PD(x) (((x) >> 26) & 0xf) -#define GET_PLL_MFD(x) (((x) >> 16) & 0x3ff) -#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) -#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - -#define WEIM_ESDCTL0 0xB8001000 -#define WEIM_ESDCFG0 0xB8001004 -#define WEIM_ESDCTL1 0xB8001008 -#define WEIM_ESDCFG1 0xB800100C -#define WEIM_ESDMISC 0xB8001010 - -#define UART1_BASE 0x43F90000 -#define UART2_BASE 0x43F94000 -#define UART3_BASE 0x5000C000 -#define UART4_BASE 0x43FB0000 -#define UART5_BASE 0x43FB4000 - -#define UART_BASE_ADDR(n) ( \ - !!sizeof(struct { \ - static_assert((n) >= 1 && (n) <= 5); \ - int pad; \ - }) * ( \ - (n) == 1 ? UART1_BASE : \ - (n) == 2 ? UART2_BASE : \ - (n) == 3 ? UART3_BASE : \ - (n) == 4 ? UART4_BASE : \ - UART5_BASE_ADDR) \ - ) - -#define I2C1_BASE_ADDR 0x43f80000 -#define I2C1_CLK_OFFSET 26 -#define I2C2_BASE_ADDR 0x43F98000 -#define I2C2_CLK_OFFSET 28 -#define I2C3_BASE_ADDR 0x43f84000 -#define I2C3_CLK_OFFSET 30 - -#define ESDCTL_SDE (1 << 31) -#define ESDCTL_CMD_RW (0 << 28) -#define ESDCTL_CMD_PRECHARGE (1 << 28) -#define ESDCTL_CMD_AUTOREFRESH (2 << 28) -#define ESDCTL_CMD_LOADMODEREG (3 << 28) -#define ESDCTL_CMD_MANUALREFRESH (4 << 28) -#define ESDCTL_ROW_13 (2 << 24) -#define ESDCTL_ROW(x) ((x) << 24) -#define ESDCTL_COL_9 (1 << 20) -#define ESDCTL_COL(x) ((x) << 20) -#define ESDCTL_DSIZ(x) ((x) << 16) -#define ESDCTL_SREFR(x) ((x) << 13) -#define ESDCTL_PWDT(x) ((x) << 10) -#define ESDCTL_FP(x) ((x) << 8) -#define ESDCTL_BL(x) ((x) << 7) -#define ESDCTL_PRCT(x) ((x) << 0) - -#define ESDCTL_BASE_ADDR 0xB8001000 - -/* 13 fields of the upper CS control register */ -#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ - cnc, wsc, ew, wws, edc) \ - ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\ - (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\ - (wws) << 4 | (edc) << 0) -/* 12 fields of the lower CS control register */ -#define CSCR_L(oea, oen, ebwa, ebwn, \ - csa, ebc, dsz, csn, psr, cre, wrap, csen) \ - ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\ - (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\ - (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0) -/* 14 fields of the additional CS control register */ -#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ - wwu, age, cnc2, fce) \ - ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\ - (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\ - (dww) << 6 | (dct) << 4 | (wwu) << 3 |\ - (age) << 2 | (cnc2) << 1 | (fce) << 0) - -#define WEIM_BASE 0xb8002000 - -#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) - -#define IPU_BASE 0x53fc0000 -#define IPU_CONF IPU_BASE - -#define IPU_CONF_PXL_ENDIAN (1<<8) -#define IPU_CONF_DU_EN (1<<7) -#define IPU_CONF_DI_EN (1<<6) -#define IPU_CONF_ADC_EN (1<<5) -#define IPU_CONF_SDC_EN (1<<4) -#define IPU_CONF_PF_EN (1<<3) -#define IPU_CONF_ROT_EN (1<<2) -#define IPU_CONF_IC_EN (1<<1) -#define IPU_CONF_CSI_EN (1<<0) - -#define ARM_PPMRR 0x40000015 - -#define WDOG1_BASE_ADDR 0x53FDC000 - -/* - * GPIO - */ -#define GPIO1_BASE_ADDR 0x53FCC000 -#define GPIO2_BASE_ADDR 0x53FD0000 -#define GPIO3_BASE_ADDR 0x53FA4000 -#define GPIO_DR 0x00000000 /* data register */ -#define GPIO_GDIR 0x00000004 /* direction register */ -#define GPIO_PSR 0x00000008 /* pad status register */ - -/* - * Signal Multiplexing (IOMUX) - */ - -/* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) - -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_CSPI3_MISO 0x0c -#define MUX_CTL_CSPI3_SCLK 0x0d -#define MUX_CTL_CSPI3_SPI_RDY 0x0e -#define MUX_CTL_CSPI3_MOSI 0x13 - -#define MUX_CTL_SD1_DATA1 0x18 -#define MUX_CTL_SD1_DATA2 0x19 -#define MUX_CTL_SD1_DATA3 0x1a -#define MUX_CTL_SD1_CMD 0x1d -#define MUX_CTL_SD1_CLK 0x1e -#define MUX_CTL_SD1_DATA0 0x1f - -#define MUX_CTL_USBH2_DATA1 0x40 -#define MUX_CTL_USBH2_DIR 0x44 -#define MUX_CTL_USBH2_STP 0x45 -#define MUX_CTL_USBH2_NXT 0x46 -#define MUX_CTL_USBH2_DATA0 0x47 -#define MUX_CTL_USBH2_CLK 0x4B - -#define MUX_CTL_TXD2 0x70 -#define MUX_CTL_RTS2 0x71 -#define MUX_CTL_CTS2 0x72 -#define MUX_CTL_RXD2 0x77 - -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -#define MUX_CTL_CSPI2_SS0 0x85 -#define MUX_CTL_CSPI2_SS1 0x86 -#define MUX_CTL_CSPI2_SS2 0x87 -#define MUX_CTL_CSPI1_SS2 0x88 -#define MUX_CTL_CSPI1_SCLK 0x89 -#define MUX_CTL_CSPI1_SPI_RDY 0x8a -#define MUX_CTL_CSPI2_MOSI 0x8b -#define MUX_CTL_CSPI1_MOSI 0x8c -#define MUX_CTL_CSPI1_MISO 0x8d -#define MUX_CTL_CSPI1_SS0 0x8e -#define MUX_CTL_CSPI1_SS1 0x8f -#define MUX_CTL_STXD6 0x90 -#define MUX_CTL_SRXD6 0x91 -#define MUX_CTL_SCK6 0x92 -#define MUX_CTL_SFS6 0x93 - -#define MUX_CTL_STXD3 0x9C -#define MUX_CTL_SRXD3 0x9D -#define MUX_CTL_SCK3 0x9E -#define MUX_CTL_SFS3 0x9F - -#define MUX_CTL_NFC_WP 0xD0 -#define MUX_CTL_NFC_CE 0xD1 -#define MUX_CTL_NFC_RB 0xD2 -#define MUX_CTL_NFC_WE 0xD4 -#define MUX_CTL_NFC_RE 0xD5 -#define MUX_CTL_NFC_ALE 0xD6 -#define MUX_CTL_NFC_CLE 0xD7 - -#define MUX_CTL_CAPTURE 0x150 -#define MUX_CTL_COMPARE 0x151 - -/* - * Helper macros for the MUX_[contact name]__[pin function] macros - */ -#define IOMUX_MODE_POS 9 -#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact)) - -/* - * These macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC) -#define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC) -#define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC) -#define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC) - -#define MUX_RXD2__UART2_RXD_MUX IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC) -#define MUX_TXD2__UART2_TXD_MUX IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC) -#define MUX_RTS2__UART2_RTS_B IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC) -#define MUX_CTS2__UART2_CTS_B IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC) - -#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC) -#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC) -#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC) -#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC) -#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) -#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) -#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) -#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) -#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) -#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ - IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) -#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) - -#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) -#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) - -/* PAD control registers for SDR/DDR */ -#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) -#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) -#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) -#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) -#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) -#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) -#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) -#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) -#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) -#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) -#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) -#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) -#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) -#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) -#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) -#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) -#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) -#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) -#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) -#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) -#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) -#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) -#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) -#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) -#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) -#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) -#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) -#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) -#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) - -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE 0x70000000 -#define CSD0_BASE 0x80000000 -#define CSD1_BASE 0x90000000 -#define CS0_BASE 0xA0000000 -#define CS1_BASE 0xA8000000 -#define CS2_BASE 0xB0000000 -#define CS3_BASE 0xB2000000 -#define CS4_BASE 0xB4000000 -#define CS4_PSRAM_BASE 0xB5000000 -#define CS5_BASE 0xB6000000 -#define PCMCIA_MEM_BASE 0xC0000000 - -/* - * NAND controller - */ -#define NFC_BASE_ADDR 0xB8000000 - -/* SD card controller */ -#define SDHC1_BASE_ADDR 0x50004000 -#define SDHC2_BASE_ADDR 0x50008000 - -/* - * Internal RAM (16KB) - */ -#define IRAM_BASE_ADDR 0x1FFFC000 -#define IRAM_SIZE (16 * 1024) - -#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000) -#define IMX_USB_PORT_OFFSET 0x200 - -/* - * CSPI register definitions - */ -#define MXC_SPI_BASE_ADDRESSES \ - 0x43fa4000, \ - 0x50010000, \ - 0x53f84000, - -/* - * Generic timer support - */ -#ifdef CONFIG_MX31_CLK32 -#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 -#else -#define CFG_SYS_TIMER_RATE 32768 -#endif - -#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h deleted file mode 100644 index 29fc0fda0e6..00000000000 --- a/arch/arm/include/asm/arch-mx31/sys_proto.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - -#ifndef _MX31_SYS_PROTO_H_ -#define _MX31_SYS_PROTO_H_ - -#include <asm/mach-imx/sys_proto.h> - -struct mxc_weimcs { - u32 upper; - u32 lower; - u32 additional; -}; - -void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); -int mxc_mmc_init(struct bd_info *bis); -#endif diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 19d12696a1e..64b243dcaaa 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -134,6 +134,8 @@ struct ele_get_info_data { u32 sha_fw[8]; u32 oem_srkh[16]; u32 state; + u32 oem_pqc_srkh[16]; + u32 reserved[8]; }; int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index f84e23f4b2a..3a9e6dcf225 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -66,7 +66,7 @@ static bool is_v2x_fw_container(ulong addr) struct boot_img_t *img_entry; phdr = (struct container_hdr *)addr; - if (phdr->tag != 0x87 || phdr->version != 0x0) { + if ((phdr->tag != 0x87 && phdr->tag != 0x82) || phdr->version != 0x0) { debug("Wrong container header\n"); return false; } diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 3cdb71a2528..1fe083ae94f 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1151,7 +1151,7 @@ int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { "/gpu@38000000", - "/soc@/gpu@38000000" + "/soc@0/gpu@38000000" }; static const char * const nodes_path_8mp[] = { diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 8fe70e2424f..e85cb0dd252 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -279,7 +279,7 @@ int print_cpuinfo(void) if (!ret) { ret = thermal_get_temp(udev, &temp); if (!ret) - printf("CPU current temperature: %d\n", temp); + printf("CPU current temperature: %dC\n", temp); else debug(" - failed to get CPU current temperature\n"); } else { diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 280d255c086..95bd1823531 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -22,15 +22,18 @@ config IMX93 config IMX91 bool select IMX9 + select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS config IMX95 bool + select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS select IMX9 select DM_MAILBOX select SCMI_FIRMWARE select SPL_IMX_CONTAINER_USE_TRAMPOLINE + select IMX_PQC_SUPPORT config SYS_SOC default "imx9" diff --git a/arch/arm/mach-imx/imx9/scmi/container.cfg b/arch/arm/mach-imx/imx9/scmi/container.cfg index 441d9beedd1..b25f3b726c5 100644 --- a/arch/arm/mach-imx/imx9/scmi/container.cfg +++ b/arch/arm/mach-imx/imx9/scmi/container.cfg @@ -3,6 +3,7 @@ * Copyright 2025 NXP */ +CNTR_VERSION 2 BOOT_FROM SD SOC_TYPE IMX9 CONTAINER diff --git a/arch/arm/mach-imx/imx9/scmi/imximage.cfg b/arch/arm/mach-imx/imx9/scmi/imximage.cfg index 6af1c4ba628..c2c92174c1c 100644 --- a/arch/arm/mach-imx/imx9/scmi/imximage.cfg +++ b/arch/arm/mach-imx/imx9/scmi/imximage.cfg @@ -3,13 +3,14 @@ * Copyright 2025 NXP */ +CNTR_VERSION 2 BOOT_FROM SD SOC_TYPE IMX9 -APPEND mx95a0-ahab-container.img +APPEND mx95b0-ahab-container.img CONTAINER +DUMMY_DDR IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000 HOLD 0x10000 -IMAGE OEI oei-m33-tcm.bin 0x1ffc0000 IMAGE M33 m33_image.bin 0x1ffc0000 IMAGE A55 spl/u-boot-spl.bin 0x20480000 DUMMY_V2X 0x8b000000 diff --git a/arch/arm/mach-imx/mx3/Kconfig b/arch/arm/mach-imx/mx3/Kconfig deleted file mode 100644 index 42bba4822e6..00000000000 --- a/arch/arm/mach-imx/mx3/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -if ARCH_MX31 - -config MX31 - bool - default y -choice - prompt "MX31 board select" - optional - -config TARGET_MX31PDK - bool "Support the i.MX31 PDK board from Freescale/NXP" - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - select SUPPORT_SPL - -endchoice - -config MX31_HCLK_FREQ - int "i.MX31 HCLK frequency" - default 26000000 - help - Frequency in Hz of the high frequency input clock. Typically - 26000000 Hz. - -config MX31_CLK32 - int "i.MX31 CLK32 Frequency" - default 32768 - help - Frequency in Hz of the low frequency input clock. Typically - 32768 or 32000 Hz. - - -endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 2f873ed6ddf..3f5e91da204 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -63,6 +63,7 @@ config MX6UL config MX6ULL bool "i.MX 6ULL SoC support" + select ARCH_MISC_INIT select ROM_UNIFIED_SECTIONS select SYSCOUNTER_TIMER select SYS_L2CACHE_OFF diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 46abf070f9d..dff4f1cf202 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -9,6 +9,7 @@ choice config TARGET_AM335X_EVM bool "Support am335x_evm" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO @@ -70,6 +71,7 @@ config TARGET_AM335X_SHC config TARGET_AM335X_GUARDIAN bool "Support am335x based guardian board from bosch" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_SERIAL @@ -116,6 +118,7 @@ config TARGET_ETAMIN config TARGET_PCM051 bool "Support pcm051" + select ARCH_MISC_INIT select DM select DM_GPIO select DM_SERIAL @@ -123,6 +126,7 @@ config TARGET_PCM051 config TARGET_PHYCORE_AM335X_R2 bool "Support phyCORE AM335X R2" + select ARCH_MISC_INIT select DM select DM_GPIO select DM_SERIAL @@ -130,6 +134,7 @@ config TARGET_PHYCORE_AM335X_R2 config TARGET_PXM2 bool "Support pxm2" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO @@ -148,6 +153,7 @@ config TARGET_RASTABAN config TARGET_RUT bool "Support rut" + select ARCH_MISC_INIT select BOARD_LATE_INIT select DM select DM_GPIO diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 5d2186bba55..6105cdcf96e 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -42,6 +42,7 @@ config TARGET_OCTEON_EBB7304 config TARGET_OCTEON_NIC23 bool "Marvell Octeon NIC23" + select ARCH_MISC_INIT select OCTEON_CN73XX help Choose this for the Octeon NIC23 board diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c index 91007c0a3d3..8a0ca26785e 100644 --- a/arch/riscv/cpu/th1520/dram.c +++ b/arch/riscv/cpu/th1520/dram.c @@ -19,3 +19,19 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capable + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > SZ_4G) + return SZ_4G; + + return gd->ram_top; +} diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index 9b255f8243c..eecd3e9832a 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ model = "Sipeed Lichee Module 4A"; compatible = "sipeed,lichee-module-4a", "thead,th1520"; + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; @@ -38,6 +43,120 @@ status = "okay"; }; +&gmac0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins = "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function = "gmac0"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins = "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <25>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function = "gmac1"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins = "GMAC0_MDC"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mdio-pins { + pins = "GMAC0_MDIO"; + function = "gmac0"; + bias-disable; + drive-strength = <13>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + &sdio0 { bus-width = <4>; max-frequency = <198000000>; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index 8306eda5521..c46925a132a 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -177,6 +177,48 @@ status = "disabled"; }; + gmac1: ethernet@ffe7060000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; + reg-names = "dwmac", "apb"; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; + clock-names = "stmmaceth", "pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gmac0: ethernet@ffe7070000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; + reg-names = "dwmac", "apb"; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; + clock-names = "stmmaceth", "pclk"; + snps,pbl = <32>; + snps,fixed-burst; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + emmc: mmc@ffe7080000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 7026c73bc69..bb696c5ef7f 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -2150,6 +2150,10 @@ }; }; }; + + aes-engine { + compatible = "software-aes-engine"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 6e3f9547fee..11ed89e0071 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -8,6 +8,10 @@ #include <linux/types.h> +static inline void sync(void) +{ +} + enum sandboxio_size_t { SB_SIZE_8, SB_SIZE_16, diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 6c374e25e32..3833af59b09 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -165,3 +165,11 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr) writel(addr, CONFIG_SYSFLAGS_ADDR); } #endif + +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c index d9a87193434..88bbc2e1af8 100644 --- a/board/gateworks/venice/eeprom.c +++ b/board/gateworks/venice/eeprom.c @@ -356,7 +356,7 @@ static int eeprom_info(bool verbose) return 0; } -int venice_eeprom_init(int quiet) +struct venice_board_info *venice_eeprom_init(int quiet) { char rev_pcb; int rev_bom; @@ -466,10 +466,10 @@ int venice_eeprom_init(int quiet) if (!strncmp(venice_model, "GW7901-SP486", 12) && strcmp(venice_model, "GW7901-SP486-C")) { - return 2048; + som_info.sdram_size++; } - return (16 << som_info.sdram_size); + return &som_info; } void board_gsc_info(void) diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h index a0f449299aa..817277f6276 100644 --- a/board/gateworks/venice/eeprom.h +++ b/board/gateworks/venice/eeprom.h @@ -18,13 +18,14 @@ struct venice_board_info { u8 sdram_size; /* 0x2B: (16 << n) MB */ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */ u8 sdram_width; /* 0x2D: (8 << n) bit */ - u8 res3[2]; /* 0x2E */ + u8 sdram_variant; /* 0x2E */ + u8 res3[1]; /* 0x2D */ char model[16]; /* 0x30: model string */ u8 config[14]; /* 0x40: model config */ u8 chksum[2]; /* 0x4E */ }; -int venice_eeprom_init(int quiet); +struct venice_board_info *venice_eeprom_init(int quiet); const char *eeprom_get_model(void); const char *eeprom_get_som_model(void); const char *eeprom_get_baseboard_model(void); diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 21997f6fb2a..e4aa8b6821c 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -6,6 +6,7 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -extern struct dram_timing_info *spl_dram_init(const char *model, int sizemb); +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc); #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c index 956071c5125..896a5c66eb6 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mm.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c @@ -10,6 +10,8 @@ #include <asm/arch/ddr.h> #include <asm/arch/lpddr4_define.h> +#include "eeprom.h" + /* ddr phy trained csr */ static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { { 0x200b2, 0x0 }, @@ -1890,6 +1892,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -2161,56 +2164,26 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, { 0x54034, 0x6600 }, @@ -2223,69 +2196,33 @@ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P1 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, @@ -2298,69 +2235,33 @@ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P2 message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, @@ -2373,69 +2274,35 @@ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x11 }, - { 0x54007, 0x0 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, { 0x5400d, 0x100 }, - { 0x5400e, 0x0 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, - { 0x54011, 0x0 }, { 0x54012, 0x110 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, { 0x5401c, 0x4d00 }, - { 0x5401d, 0x0 }, { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, { 0x54022, 0x4d00 }, - { 0x54023, 0x0 }, { 0x54024, 0x16 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, { 0x54034, 0x6600 }, @@ -2448,13 +2315,6 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = { { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, { 0x5403d, 0x1600 }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, { 0xd0000, 0x1 }, }; @@ -2549,6 +2409,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -3065,6 +2926,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = { { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, { 0x3d400250, 0x29001701 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, @@ -3558,9 +3420,36 @@ static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = { { 0x120a5, 0x2 }, }; -struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +/* 4GB single Die patch (MT53E1G32D2FW-046 revC) */ +static struct dram_cfg_param ddr_ddrc_cfg_4gb_single_die_patch[] = { + { 0x3d400000, 0xa1080020 }, + { 0x3d400064, 0x5b011d }, + { 0x3d40011c, 0x402 }, + { 0x3d400138, 0x123 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400200, 0x1f }, + { 0x3d40021c, 0xf07 }, + { 0x3d402064, 0xc0026 }, + { 0x3d40211c, 0x302 }, + { 0x3d402138, 0x27 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403064, 0x3000a }, + { 0x3d40311c, 0x302 }, + { 0x3d403138, 0xa }, + { 0x3d4030f4, 0x599 } +}; + +static struct dram_cfg_param fsp_msg_4gb_single_die_patch[] = { + { 0x00054012, 0x110 }, + { 0x0005402c, 0x1 }, +}; + +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) { struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); + int i; switch (sizemb) { case 512: @@ -3574,6 +3463,21 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb) break; case 4096: dram_timing = &dram_timing_4gb; + if (info->sdram_variant == 1) { + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); + apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num, + ddr_ddrc_cfg_4gb_single_die_patch, + ARRAY_SIZE(ddr_ddrc_cfg_4gb_single_die_patch)); + for (i = 0; i < 4; i++) { + apply_cfg_patch(dram_timing->fsp_msg[i].fsp_cfg, + dram_timing->fsp_msg[i].fsp_cfg_num, + fsp_msg_4gb_single_die_patch, + ARRAY_SIZE(fsp_msg_4gb_single_die_patch)); + } + } else if (dram_desc) { + strlcpy(dram_desc, "dual-die", sz_desc); + } break; default: printf("unsupported"); @@ -3593,5 +3497,8 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb) ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch)); } + if (ddr_init(dram_timing)) + return NULL; + return dram_timing; } diff --git a/board/gateworks/venice/lpddr4_timing_imx8mn.c b/board/gateworks/venice/lpddr4_timing_imx8mn.c index e7d04822c9c..cad4fc0d31c 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mn.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mn.c @@ -4,6 +4,8 @@ #include <string.h> #include <asm/arch/ddr.h> +#include "eeprom.h" + /* * Generated code from MX8M_DDR_tool v3.20 using RPAv15 */ @@ -2369,26 +2371,36 @@ static struct dram_timing_info dram_timing_2gb_dual_die = { .fsp_table = { 3200, 400, 100, }, }; -struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) { struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); switch (sizemb) { case 1024: dram_timing = &dram_timing_1gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); break; case 2048: if (!strcmp(model, "GW7902-SP466-A") || !strcmp(model, "GW7902-SP466-B")) { dram_timing = &dram_timing_2gb_dual_die; + if (dram_desc) + strlcpy(dram_desc, "dual-die", sz_desc); } else { dram_timing = &dram_timing_2gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); } break; default: printf("unsupported"); dram_timing = &dram_timing_2gb_dual_die; } + if (ddr_init(dram_timing)) + return NULL; return dram_timing; } diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c index 36c4cb147e8..f2d5d9ce565 100644 --- a/board/gateworks/venice/lpddr4_timing_imx8mp.c +++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c @@ -1,8 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ #include <linux/kernel.h> +#include <string.h> #include <asm/arch/ddr.h> +#include "eeprom.h" + /* * Generated code from MX8M_DDR_tool v3.30 using MX8M_Plus RPAv7 */ @@ -2378,21 +2381,29 @@ static struct dram_timing_info dram_timing_4gb_dual_die = { .fsp_table = { 4000, 400, 100, }, }; -struct dram_timing_info *spl_dram_init(const char *model, int sizemb) +struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info, + char *dram_desc, size_t sz_desc) { struct dram_timing_info *dram_timing; + int sizemb = (16 << info->sdram_size); switch (sizemb) { case 1024: dram_timing = &dram_timing_1gb_single_die; + if (dram_desc) + strlcpy(dram_desc, "single-die", sz_desc); break; case 4096: dram_timing = &dram_timing_4gb_dual_die; + if (dram_desc) + strlcpy(dram_desc, "dual-die", sz_desc); break; default: printf("unsupported"); dram_timing = &dram_timing_4gb_dual_die; } + if (ddr_init(dram_timing)) + return NULL; return dram_timing; } diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index e813f3e763e..2c303211d32 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -188,9 +188,10 @@ static int power_init_board(const char *model, struct udevice *gsc) void board_init_f(ulong dummy) { struct dram_timing_info *dram_timing; + struct venice_board_info *eeprom; struct udevice *bus, *dev; const char *model; - int dram_szmb; + char dram_desc[32]; int i, ret; arch_cpu_init(); @@ -249,23 +250,89 @@ void board_init_f(ulong dummy) break; mdelay(1); } - dram_szmb = venice_eeprom_init(0); + eeprom = venice_eeprom_init(0); model = eeprom_get_model(); /* PMIC */ power_init_board(model, dev); /* DDR initialization */ - printf("DRAM : LPDDR4 "); - if (dram_szmb > 512) - printf("%d GiB", dram_szmb / 1024); - else - printf("%d MiB", dram_szmb); - dram_timing = spl_dram_init(model, dram_szmb); - printf(" %dMT/s %dMHz\n", - dram_timing->fsp_msg[0].drate, - dram_timing->fsp_msg[0].drate / 2); - ddr_init(dram_timing); + dram_desc[0] = 0; + dram_timing = spl_dram_init(model, eeprom, dram_desc, sizeof(dram_desc)); + if (dram_timing) { + int dram_szmb = (16 << eeprom->sdram_size); + + printf("DRAM : LPDDR4 "); + if (dram_szmb > 512) + printf("%d GiB", dram_szmb / 1024); + else + printf("%d MiB", dram_szmb); + printf(" %dMT/s %dMHz %s", + dram_timing->fsp_msg[0].drate, + dram_timing->fsp_msg[0].drate / 2, + dram_desc[0] ? dram_desc : ""); + +#ifdef DEBUG + u8 mr[9] = { 0 }; + /* Read MR5-MR8 to obtain details about DRAM part (and verify DRAM working) */ + for (i = 5; i < 9; i++) + mr[i] = lpddr4_mr_read(0xf, i) & 0xff; + + printf(" (0x%02x%02x%02x%02x", mr[5], mr[6], mr[7], mr[8]); + /* MR5 MFG_ID */ + switch (mr[5]) { + case 0xff: + printf(" Micron"); + break; + default: + break; + } + /* MR8 OP[7:6] Width */ + i = 0; + switch ((mr[8] >> 6) & 0x3) { + case 0: + i = 16; + break; + case 1: + i = 8; + break; + } + if (i) + printf(" x%d", i); + /* MR8 OP[5:2] Density */ + i = 0; + switch ((mr[8] >> 2) & 0xf) { + case 0: + i = 4; + break; + case 1: + i = 6; + break; + case 2: + i = 8; + break; + case 3: + i = 12; + break; + case 4: + i = 16; + break; + case 5: + i = 24; + break; + case 6: + i = 32; + break; + default: + break; + } + if (i) + printf(" %dGb per die", i); +#endif + puts(")\n"); + } else { + hang(); + } board_init_r(NULL, 0); } diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 41458813858..b68c10f85e4 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -29,14 +29,6 @@ config KM_PHRAM help Start address of the physical RAM, which is the mounted /var folder. -config KM_RESERVED_PRAM - hex "Reserved RAM" - default 0x0 if MPC83xx - default 0x1000 if MPC85xx || ARCH_LS1021A - depends on !ARCH_SOCFPGA - help - Reserved physical RAM area at the end of memory for special purposes. - config KM_CRAMFS_ADDR hex "CRAMFS Address" default 0x83000000 if ARCH_LS1021A diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 25897af2d8a..4bdaf90deff 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -53,7 +53,7 @@ int set_km_env(void) char *p; pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; + CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -61,12 +61,10 @@ int set_km_env(void) p = env_get("rootfssize"); if (p) strict_strtoul(p, 16, &rootfssize); - pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM) / 0x400; + pram = (rootfssize + CONFIG_KM_PHRAM + CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram); - varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); env_set("varaddr", envval); diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index c8299483299..f8f8d5edede 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -18,6 +18,11 @@ #define DIRECT_OFF 0x18 #define GPRT_OFF 0x1c +// used to keep track of the user settings for the input/output +static u32 gprt_user[2] = { 0x0, 0x0 }; +// convert the bank offset to the correct static user gprt +#define QRIO_USER_GRPT_BANK(bank) gprt_user[(bank - 0x40) / 0x20] + void show_qrio(void) { void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; @@ -72,12 +77,13 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) mask = 1U << gpio_nr; - gprt = in_be32(qrio_base + port_off + GPRT_OFF); + gprt = QRIO_USER_GRPT_BANK(port_off); if (value) gprt |= mask; else gprt &= ~mask; + QRIO_USER_GRPT_BANK(port_off) = gprt; out_be32(qrio_base + port_off + GPRT_OFF, gprt); } diff --git a/board/keymile/pg-wcom-ls102xa/MAINTAINERS b/board/keymile/pg-wcom-ls102xa/MAINTAINERS index ed5baf269a7..7d80cfbf64f 100644 --- a/board/keymile/pg-wcom-ls102xa/MAINTAINERS +++ b/board/keymile/pg-wcom-ls102xa/MAINTAINERS @@ -1,6 +1,6 @@ Hitachi Power Grids LS102XA BOARD -M: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com> -M: Rainer Boschung <rainer.boschung@hitachienergy.com> +M: Holger Brunck <holger.brunck@hitachienergy.com> +M: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com> S: Maintained F: board/keymile/pg-wcom-ls102xa/ F: board/keymile/common/ diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env index 1054dbf9f54..c1c73b7da49 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=EXPU1 +netdev=eth2 diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 409a55ebda6..7db75f4df3e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -38,7 +38,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) { show_qrio(); - + i2c_deblock_gpio_cfg(); return 0; } @@ -96,8 +96,6 @@ int board_early_init_f(void) qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false); - i2c_deblock_gpio_cfg(); - /* enable the Unit LED (red) & Boot LED (on) */ qrio_set_leds(); diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env index 1232fe9da8b..bbfa8194a7e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env @@ -1,3 +1,4 @@ #include <env/pg-wcom/ls102xa.env> hostname=SELI8 +netdev=eth2 diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index 6b6984eae3f..ba622e38ee5 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -73,13 +73,22 @@ int board_fit_config_name_match(const char *name) for (int i = 0; i < list_len; i++) { int len, match; const char *compat; + char copy[64]; char *devendored; compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); if (!compat) return -EINVAL; - strtok((char *)compat, ","); + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); devendored = strtok(NULL, ","); if (!devendored) diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index 69690aa92e4..9a129a0a4bf 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -1,82 +1,28 @@ -#include <env/phytec/rauc.env> -#include <env/phytec/overlays.env> - bootcmd= if test ${dofastboot} = 1; then fastboot 0; fi; - mmc dev ${mmcdev}; - if mmc rescan; then - run spiprobe; - if test ${doraucboot} = 1; then - run raucinit; - fi; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; -console=ttymxc0,115200 + bootflow scan -lb; +bootmeths=script efi +boot_targets=mmc2 mmc1 usb ethernet bootenv_addr_r=0x49100000 -fdtoverlay_addr_r=0x49000000 +boot_script_dhcp=boot.scr.uimg +console=ttymxc0,115200 dofastboot=0 -emmc_dev=2 fastboot_raw_partition_all=0 4194304 fastboot_raw_partition_bootloader=64 8128 fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image +fdtoverlay_addr_r=0x49000000 ip_dyn=yes +kernel_addr_r=0x5A080000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 mtdparts=30bb0000.spi:3840k(u-boot),128k(env),128k(env_redund),-(none) mtdids=nor0=30bb0000.spi -spiprobe=true -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -mmcargs= - setenv bootargs ${mcore_clk} console=${console} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw mmcautodetect=yes -mmcboot= - echo Booting from mmc ...; - if test ${no_bootenv} = 0; then - if run mmc_load_bootenv; then - env import -t ${bootenv_addr_r} ${filesize}; - fi; - fi; - run mmcargs; - if run loadfdt; then - run mmc_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=2 -netargs= - setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp - nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${no_bootenv} = 0; then - if run net_load_bootenv; then - env import -t ${bootenv_addr_r} ${filesize}; - fi; - fi; - ${get_cmd} ${loadaddr} ${image}; - run netargs; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run net_apply_overlays; - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; nfsroot=/srv/nfs -prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted -sd_dev=1 +pxefile_addr_r=0x58600000 +ramdisk_addr_r=0x5E000000 +scriptaddr=0x40000000 diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index 3b4bd64dd00..9c8c7a6ecdc 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,6 +1,5 @@ CAPRICORN BOARD M: Alexander Sverdlin <alexander.sverdlin@siemens.com> -M: Anatolij Gustschin <agust@denx.de> M: Heiko Schocher <hs@denx.de> M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS index 1e726e93603..6e7eee9c3e3 100644 --- a/board/terasic/de1-soc/MAINTAINERS +++ b/board/terasic/de1-soc/MAINTAINERS @@ -1,5 +1,5 @@ DE1-SoC BOARD -M: Anatolij Gustschin <agust@denx.de> +M: Anatolij Gustschin <ag.dev.uboot@gmail.com> S: Maintained F: board/terasic/de1-soc/ F: include/configs/socfpga_de1_soc.h diff --git a/board/ti/am64x/rm-cfg.yaml b/board/ti/am64x/rm-cfg.yaml index 88b37b5972c..1cc4cd34430 100644 --- a/board/ti/am64x/rm-cfg.yaml +++ b/board/ti/am64x/rm-cfg.yaml @@ -1,1215 +1,1215 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # -# Resource management configuration for AM64x +# Resource management configuration for AM64X # --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 12 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 30 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - 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a/board/ti/j7200/rm-cfg.yaml b/board/ti/j7200/rm-cfg.yaml index f83184bbfc0..9da0ea91ada 100644 --- a/board/ti/j7200/rm-cfg.yaml +++ b/board/ti/j7200/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J7200 # @@ -7,1779 +7,1779 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 2 - host_id: 5 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 0xAAAAAAAA - allowed_priority: 0xAAAA - allowed_sched_priority: 0xAA - - # 3 - host_id: 12 - allowed_atype: 0b101010 - allowed_qos: 0xAAAA - allowed_orderid: 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num_resource: 1 + type: 15119 + host_id: 12 + reserved: 0 + - + start_resource: 1 + num_resource: 1 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 11 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j721e/rm-cfg.yaml b/board/ti/j721e/rm-cfg.yaml index 0163e3e1717..88ec2026db0 100644 --- a/board/ti/j721e/rm-cfg.yaml +++ b/board/ti/j721e/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721E # @@ -7,2751 +7,2751 @@ --- rm-cfg: - rm_boardcfg: - rev: - boardcfg_abi_maj: 0x0 - boardcfg_abi_min: 0x1 - host_cfg: - subhdr: - magic: 0x4C41 - size: 356 - host_cfg_entries: - - # 1 - host_id: 3 - allowed_atype: 0x2A - allowed_qos: 0xAAAA - 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reserved: 0 + - + start_resource: 37 + num_resource: 1 + type: 15117 + host_id: 21 + reserved: 0 + - + start_resource: 38 + num_resource: 1 + type: 15117 + host_id: 26 + reserved: 0 + - + start_resource: 39 + num_resource: 1 + type: 15117 + host_id: 28 + reserved: 0 + - + start_resource: 40 + num_resource: 2 + type: 15117 + host_id: 35 + reserved: 0 + - + start_resource: 42 + num_resource: 1 + type: 15117 + host_id: 37 + reserved: 0 + - + start_resource: 43 + num_resource: 3 + type: 15117 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 0 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 0 + num_resource: 2 + type: 15119 + host_id: 3 + reserved: 0 + - + start_resource: 12 + num_resource: 20 + type: 15168 + host_id: 3 + reserved: 0 + - + start_resource: 36 + num_resource: 28 + type: 15168 + host_id: 5 + reserved: 0 diff --git a/board/ti/j722s/rm-cfg.yaml b/board/ti/j722s/rm-cfg.yaml index e32beb84795..62730adf216 100644 --- a/board/ti/j722s/rm-cfg.yaml +++ b/board/ti/j722s/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 diff --git a/board/ti/j722s/tifs-rm-cfg.yaml b/board/ti/j722s/tifs-rm-cfg.yaml index 4a2af0ebcaf..7b2e58a89b3 100644 --- a/board/ti/j722s/tifs-rm-cfg.yaml +++ b/board/ti/j722s/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J722S # @@ -16,224 +16,224 @@ tifs-rm-cfg: magic: 0x4C41 size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 20 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 22 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #5 + - # 5 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #6 + - # 6 host_id: 38 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 @@ -248,746 +248,746 @@ tifs-rm-cfg: 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num_resource: 32 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 32 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 4557ed1f1f2..168840764a1 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -36,7 +36,7 @@ #define VCC_USBO1 TEGRA_GPIO(T, 5) #define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4) -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) { diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 02e8f8eb1fe..2c785da41ea 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; static int pci_reset_status; #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index d432fd2b843..05c3377a60b 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU_SUPPLYENE_SYSINEN (1<<5) #define PMU_SUPPLYENE_EXITSLREQ (1<<1) -int arch_misc_init(void) +int misc_init_r(void) { /* Disable PMIC sleep mode on low supply voltage */ struct udevice *dev; diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 342673ac506..1b091ea1694 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -18,7 +18,7 @@ #include "pinmux-config-colibri_t30.h" #include "../common/tdx-common.h" -int arch_misc_init(void) +int misc_init_r(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == NVBOOTTYPE_RECOVERY) diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index eca2cc8bc7f..100cfb90eb1 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -95,7 +95,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 43d1c9312fe..a7124ecf823 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -124,7 +124,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 1020078afea..3c2d0ba1dd4 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -53,7 +53,9 @@ void spl_dram_init(void) void spl_board_init(void) { +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) arch_misc_init(); +#endif } #ifdef CONFIG_SPL_LOAD_FIT diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 066e8db678f..04c918a079f 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -100,7 +100,7 @@ static void select_dt_from_module_version(void) break; } - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e57ec3b6896..34ce25512e8 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -90,7 +90,7 @@ static void select_dt_from_module_version(void) else strlcpy(&variant[0], "nonwifi", sizeof(variant)); - if (strcmp(variant, env_variant)) { + if (!env_variant || strcmp(variant, env_variant)) { printf("Setting variant to %s\n", variant); env_set("variant", variant); } diff --git a/boot/android_ab.c b/boot/android_ab.c index a287eac04fe..13e82dbcb7f 100644 --- a/boot/android_ab.c +++ b/boot/android_ab.c @@ -101,8 +101,7 @@ static int ab_control_create_from_disk(struct blk_desc *dev_desc, abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control), part_info->blksz); if (abc_offset + abc_blocks > part_info->size) { - log_err("ANDROID: boot control partition too small. Need at"); - log_err(" least %lu blocks but have %lu blocks.\n", + log_err("ANDROID: boot control partition too small. Need at least %lu blocks but have " LBAF " blocks.\n", abc_offset + abc_blocks, part_info->size); return -EINVAL; } diff --git a/boot/bootflow.c b/boot/bootflow.c index 4054a966af8..d79f303486d 100644 --- a/boot/bootflow.c +++ b/boot/bootflow.c @@ -245,7 +245,7 @@ static int iter_incr(struct bootflow_iter *iter) if (iter->flags & BOOTFLOWIF_SINGLE_DEV) { ret = -ENOENT; } else { - int method_flags; + int method_flags = 0; ret = 0; dev = iter->dev; @@ -264,7 +264,6 @@ static int iter_incr(struct bootflow_iter *iter) } else if (IS_ENABLED(CONFIG_BOOTSTD_FULL) && iter->flags & BOOTFLOWIF_SINGLE_MEDIA) { log_debug("next in single\n"); - method_flags = 0; do { /* * Move to the next bootdev child of this media @@ -296,6 +295,7 @@ static int iter_incr(struct bootflow_iter *iter) log_debug("looking for next device %s: %s\n", iter->dev->name, dev ? dev->name : "<none>"); + method_flags = BOOTFLOW_METHF_SINGLE_UCLASS; } else { dev = NULL; } @@ -306,7 +306,6 @@ static int iter_incr(struct bootflow_iter *iter) } } else { ret = bootdev_next_prio(iter, &dev); - method_flags = 0; } } log_debug("ret=%d, dev=%p %s\n", ret, dev, diff --git a/cmd/Kconfig b/cmd/Kconfig index 2d3a8062625..b3b5be1ea79 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2629,6 +2629,7 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" depends on !MX6ULL && !MX6SLL && !MX6SL + depends on SYS_FSL_SEC_COMPAT >= 4 select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M help This is used with the Freescale secure boot mechanism. diff --git a/cmd/aes.c b/cmd/aes.c index 87ad1ab82b9..3fd83013ffe 100644 --- a/cmd/aes.c +++ b/cmd/aes.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * Copyright (C) 2025 Ion Agorria <ion@agorria.com> * - * Command for en/de-crypting block of memory with AES-[128/192/256]-CBC cipher. + * Command for AES-[128/192/256] operations. */ #include <command.h> @@ -12,6 +13,8 @@ #include <linux/compiler.h> #include <mapmem.h> #include <vsprintf.h> +#include <dm/uclass.h> +#include <dm/device.h> u32 aes_get_key_len(char *command) { @@ -25,29 +28,30 @@ u32 aes_get_key_len(char *command) return key_len; } -/** - * do_aes() - Handle the "aes" command-line command - * @cmdtp: Command data struct pointer - * @flag: Command flag - * @argc: Command-line argument count - * @argv: Array of command-line arguments - * - * Returns zero on success, CMD_RET_USAGE in case of misuse and negative - * on error. - */ -static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +int aes_get_driver(struct udevice **dev) +{ + int ret; + + ret = uclass_get_device(UCLASS_AES, 0, dev); + if (ret) { + printf("Failed to get AES driver: %d\n", ret); + return ret; + } + + return 0; +} + +int cmd_aes_cbc_simple(int argc, char *const argv[], u32 key_len) { uint32_t key_addr, iv_addr, src_addr, dst_addr, len; uint8_t *key_ptr, *iv_ptr, *src_ptr, *dst_ptr; u8 key_exp[AES256_EXPAND_KEY_LENGTH]; - u32 aes_blocks, key_len; + u32 aes_blocks; int enc; if (argc != 7) return CMD_RET_USAGE; - key_len = aes_get_key_len(argv[0]); - if (!strncmp(argv[1], "enc", 3)) enc = 1; else if (!strncmp(argv[1], "dec", 3)) @@ -84,26 +88,257 @@ static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) unmap_sysmem(src_ptr); unmap_sysmem(dst_ptr); - return 0; + return CMD_RET_SUCCESS; +} + +int cmd_aes_get_slots(void) +{ + struct udevice *dev; + u8 slots; + int ret; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + slots = dm_aes_get_available_key_slots(dev); + printf("Available slots: %d\n", slots); + + return CMD_RET_SUCCESS; +} + +int cmd_aes_set_key(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 key_addr, slot; + u8 *key_ptr; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + key_addr = hextoul(argv[2], NULL); + slot = hextoul(argv[3], NULL); + + key_ptr = (uint8_t *)map_sysmem(key_addr, key_len); + + ret = dm_aes_set_key_for_key_slot(dev, key_len * 8, key_ptr, slot); + unmap_sysmem(key_ptr); + if (ret) { + printf("Unable to set key at slot: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_select_slot(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 slot; + int ret; + + if (argc != 3) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + slot = hextoul(argv[2], NULL); + + ret = dm_aes_select_key_slot(dev, key_len * 8, slot); + if (ret) { + printf("Unable to select key slot: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_ecb(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 src_addr, dst_addr, len; + u8 *src_ptr, *dst_ptr; + u32 aes_blocks; + int enc, ret; + + if (argc != 6) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + src_addr = hextoul(argv[3], NULL); + dst_addr = hextoul(argv[4], NULL); + len = hextoul(argv[5], NULL); + + src_ptr = (uint8_t *)map_sysmem(src_addr, len); + dst_ptr = (uint8_t *)map_sysmem(dst_addr, len); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_BLOCK_LENGTH); + + if (enc) + ret = dm_aes_ecb_encrypt(dev, src_ptr, dst_ptr, aes_blocks); + else + ret = dm_aes_ecb_decrypt(dev, src_ptr, dst_ptr, aes_blocks); + + unmap_sysmem(src_ptr); + unmap_sysmem(dst_ptr); + + if (ret) { + printf("Unable to do ecb operation: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +int cmd_aes_cbc(int argc, char *const argv[], u32 key_len) +{ + struct udevice *dev; + u32 iv_addr, src_addr, dst_addr, len; + u8 *iv_ptr, *src_ptr, *dst_ptr; + u32 aes_blocks; + int enc, ret; + + if (argc != 7) + return CMD_RET_USAGE; + + ret = aes_get_driver(&dev); + if (ret) + return ret; + + if (!strncmp(argv[1], "enc", 3)) + enc = 1; + else if (!strncmp(argv[1], "dec", 3)) + enc = 0; + else + return CMD_RET_USAGE; + + iv_addr = hextoul(argv[3], NULL); + src_addr = hextoul(argv[4], NULL); + dst_addr = hextoul(argv[5], NULL); + len = hextoul(argv[6], NULL); + + iv_ptr = (uint8_t *)map_sysmem(iv_addr, AES_BLOCK_LENGTH); + src_ptr = (uint8_t *)map_sysmem(src_addr, len); + dst_ptr = (uint8_t *)map_sysmem(dst_addr, len); + + /* Calculate the number of AES blocks to encrypt. */ + aes_blocks = DIV_ROUND_UP(len, AES_BLOCK_LENGTH); + + if (enc) + ret = dm_aes_cbc_encrypt(dev, iv_ptr, src_ptr, dst_ptr, aes_blocks); + else + ret = dm_aes_cbc_decrypt(dev, iv_ptr, src_ptr, dst_ptr, aes_blocks); + + unmap_sysmem(iv_ptr); + unmap_sysmem(src_ptr); + unmap_sysmem(dst_ptr); + + if (ret) { + printf("Unable to do cbc operation: %d\n", ret); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +/** + * do_aes() - Handle the "aes" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +static int do_aes(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u32 key_len; + + if (argc < 2) + return CMD_RET_USAGE; + + key_len = aes_get_key_len(argv[0]); + + if (!strncmp(argv[1], "enc", 3) || !strncmp(argv[1], "dec", 3)) + return cmd_aes_cbc_simple(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "get_slots", 9)) + return cmd_aes_get_slots(); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "set_key", 7)) + return cmd_aes_set_key(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "select_slot", 11)) + return cmd_aes_select_slot(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "ecb", 3)) + return cmd_aes_ecb(argc, argv, key_len); + else if (CONFIG_IS_ENABLED(DM_AES) && !strncmp(argv[1], "cbc", 3)) + return cmd_aes_cbc(argc, argv, key_len); + else + return CMD_RET_USAGE; } /***************************************************/ U_BOOT_LONGHELP(aes, - "[.128,.192,.256] enc key iv src dst len - Encrypt block of data $len bytes long\n" + "[.128,.192,.256] enc key iv src dst len - CBC encrypt block of data $len bytes long\n" " at address $src using a key at address\n" " $key with initialization vector at address\n" " $iv. Store the result at address $dst.\n" " The $len size must be multiple of 16 bytes.\n" " The $key and $iv must be 16 bytes long.\n" - "aes [.128,.192,.256] dec key iv src dst len - Decrypt block of data $len bytes long\n" + "aes [.128,.192,.256] dec key iv src dst len - CBC decrypt block of data $len bytes long\n" " at address $src using a key at address\n" " $key with initialization vector at address\n" " $iv. Store the result at address $dst.\n" " The $len size must be multiple of 16 bytes.\n" - " The $key and $iv must be 16 bytes long."); + " The $key and $iv must be 16 bytes long." + +#if CONFIG_IS_ENABLED(DM_AES) + "\n" + "aes get_slots - Gives number of available key slots\n" + "aes [.128,.192,.256] set_key key slot - Load key at address $key into the slot $slot\n" + "aes [.128,.192,.256] select_slot slot - Select current active key slot\n" + "aes [.128,.192,.256] ecb enc src dst len - ECB encrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + "aes [.128,.192,.256] ecb dec src dst len - ECB decrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + "aes [.128,.192,.256] cbc enc iv src dst len - CBC encrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot with initialization vector at address\n" + " $iv. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + " The $iv must be 16 bytes long.\n" + "aes [.128,.192,.256] cbc dec iv src dst len - CBC decrypt block of data $len bytes long\n" + " at address $src using a key at current\n" + " slot with initialization vector at address\n" + " $iv. Store the result at address $dst.\n" + " The $len size must be multiple of 16 bytes.\n" + " The $iv must be 16 bytes long." +#endif +); U_BOOT_CMD( aes, 7, 1, do_aes, - "AES 128/192/256 CBC encryption", + "AES 128/192/256 operations", aes_help_text ); diff --git a/cmd/i2c.c b/cmd/i2c.c index 7246c4fa3e7..f0aae93073f 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -917,9 +917,9 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, #endif /* NOPROBES */ int ret; #if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *bus, *dev; + struct udevice *cur_bus, *dev; - if (i2c_get_cur_bus(&bus)) + if (i2c_get_cur_bus(&cur_bus)) return CMD_RET_FAILURE; #endif @@ -943,7 +943,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, continue; #endif #if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_probe(bus, j, 0, &dev); + ret = dm_i2c_probe(cur_bus, j, 0, &dev); #else ret = i2c_probe(j); #endif diff --git a/cmd/ufetch.c b/cmd/ufetch.c index 46bd16824e6..bc5db08eee1 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -93,7 +93,7 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, const char *model, *compatible; char *ipaddr; int n_cmds, n_cpus = 0, compatlen; - size_t size; + size_t size = 0; ofnode np; bool skip_ascii = false; diff --git a/common/Kconfig b/common/Kconfig index 17539079f90..a2f653f7e72 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -704,8 +704,9 @@ config ARCH_EARLY_INIT_R enabled. This can be used to set up architecture-specific devices. config ARCH_MISC_INIT - bool "Call arch-specific init after relocation, when console is ready" + bool help + Call arch-specific init after relocation, when console is ready. With this option U-Boot will call arch_misc_init() after relocation to allow miscellaneous arch-dependent initialisation to be performed. This function should be defined by the board diff --git a/common/autoboot.c b/common/autoboot.c index 0a254498d40..e39f4a32f95 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -410,7 +410,7 @@ static int abortboot_single_key(int bootdelay) udelay(10000); } while (!abort && get_timer(ts) < 1000); - printf("\b\b\b%2d ", bootdelay); + printf("\rHit any key to stop autoboot: %1d\033[K", bootdelay); } putc('\n'); diff --git a/common/avb_verify.c b/common/avb_verify.c index cff9117d92f..29a3272579c 100644 --- a/common/avb_verify.c +++ b/common/avb_verify.c @@ -320,7 +320,7 @@ static unsigned long mmc_read_and_flush(struct mmc_part *part, } if ((start + sectors) > (part->info.start + part->info.size)) { sectors = part->info.start + part->info.size - start; - printf("%s: read sector aligned to partition bounds (%ld)\n", + printf("%s: read sector aligned to partition bounds (" LBAF ")\n", __func__, sectors); } @@ -363,7 +363,7 @@ static unsigned long mmc_write(struct mmc_part *part, lbaint_t start, } if ((start + sectors) > (part->info.start + part->info.size)) { sectors = part->info.start + part->info.size - start; - printf("%s: sector aligned to partition bounds (%ld)\n", + printf("%s: sector aligned to partition bounds (" LBAF ")\n", __func__, sectors); } if (unaligned) { diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 4e26b3940d8..ac25fcea21d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -132,6 +132,7 @@ config SPL_BSS_START_ADDR choice prompt "Enforce SPL BSS limit" depends on !PPC + default SPL_NO_BSS_LIMIT if COMPILE_TEST default SPL_BSS_LIMIT help In some platforms we only want to enforce a limit on the size of the @@ -370,6 +371,13 @@ config SPL_IMX_CONTAINER_USE_TRAMPOLINE help Enable SPL load reader to load data to a trampoline buffer. +config IMX_PQC_SUPPORT + bool "Enable to support i.MX ROM PQC Container" + depends on SPL && SPL_LOAD_IMX_CONTAINER + help + Support i.MX ROM new PQC container format. If your chip does not use + PQC container, say 'n'. + config IMX_CONTAINER_CFG string "i.MX8 Container config file" depends on SPL && SPL_LOAD_IMX_CONTAINER diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index f61e701e3c9..05853317fea 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index a184989ea50..099a4828a7f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_BEAGLEPLAY=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 2c04d32195d..4da668396d0 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_A53_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 162be534ce4..ba6396c9dfc 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index dfd586b1c14..da0d51a844b 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Apalis iMX8 # " CONFIG_CMD_CPU=y @@ -46,6 +47,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y @@ -66,11 +68,11 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y +CONFIG_FSL_CAAM=y CONFIG_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -88,6 +90,7 @@ CONFIG_IMX8_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index de30fa1b961..846c7bde234 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -27,7 +27,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index e9c9cfe940e..57e1eb733a8 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -22,7 +22,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index 04defac9a71..7774f7b2388 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -80,7 +80,7 @@ CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv b_mode 0; run b_default;" CONFIG_SYS_I2C_MXC=y CONFIG_MMC_BROKEN_CD=y # CONFIG_SPL_DM_MMC is not set -CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 431987d3f90..6880caf9208 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_PBSIZE=2068 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="Colibri iMX8X # " CONFIG_CMD_CPU=y @@ -47,6 +48,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y @@ -67,12 +69,12 @@ CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_IMX8=y +CONFIG_FSL_CAAM=y CONFIG_GPIO_HOG=y CONFIG_FXL6408_GPIO=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -89,6 +91,7 @@ CONFIG_IMX8_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index c8a17cd40a2..02e33ba5e3c 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_PBSIZE=1055 CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 8d7a6bf7060..63b695c1e54 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -21,7 +21,7 @@ CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/imx6ulz_smm_m2b_defconfig b/configs/imx6ulz_smm_m2b_defconfig index c0eb1093d8b..36f5922ea10 100644 --- a/configs/imx6ulz_smm_m2b_defconfig +++ b/configs/imx6ulz_smm_m2b_defconfig @@ -44,6 +44,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX6UL=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_FLASH=y @@ -65,6 +67,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y @@ -76,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x877fffc0 CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index bb110225488..6937aa224a1 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SYS_MEM_TOP_HIDE=0x400000 +# CONFIG_DEBUG_UART is not set CONFIG_TARGET_MICROCHIP_ICICLE=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index cb38898a245..975d061e7ba 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -31,10 +31,13 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_USE_BOOTCOMMAND is not set CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 @@ -57,9 +60,11 @@ CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_VBE is not set +CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -76,17 +81,12 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +# CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -172,7 +172,6 @@ CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 910a41fa052..92a159e7466 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 546cee09575..73517e04d0a 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 84cc4cf82d8..b9ba7a677d9 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -37,6 +37,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 1cefaa0a138..374dcb1d5ba 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -136,6 +136,8 @@ CONFIG_CLK_K210=y CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index d6768e291d0..2eba02e1f07 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -185,6 +185,8 @@ CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CLK_SCMI=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index f0a69a414db..e81941fb14f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -74,6 +74,7 @@ CONFIG_CMD_QFW=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_AES=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y @@ -114,6 +115,8 @@ CONFIG_CLK_K210=y CONFIG_CLK_K210_SET_RATE=y CONFIG_SANDBOX_CLK_CCF=y CONFIG_CPU=y +CONFIG_DM_AES=y +CONFIG_AES_SOFTWARE=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 78e3b25ab82..2763cbb428a 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -76,7 +76,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y -CONFIG_NO_NET=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_BLOCK_CACHE is not set CONFIG_DWAPB_GPIO=y # CONFIG_I2C is not set @@ -90,6 +90,11 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_SNPS=y # CONFIG_MTD is not set +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_ETH_DESIGNWARE_THEAD=y CONFIG_PINCTRL=y # CONFIG_POWER is not set CONFIG_RAM=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 3e7e4264b12..0489f444115 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -154,6 +154,7 @@ CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 584c416bd83..e36b55faec1 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_VERDIN_AM62_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -169,6 +170,7 @@ CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -176,6 +178,8 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y @@ -194,3 +198,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_HEXDUMP=y +# CONFIG_OPTEE_LIB is not set diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index c3a2a582f86..5cc7d050c33 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_VERDIN_AM62_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig index 28f48ba773e..7e6132cde53 100644 --- a/configs/verdin-am62p_a53_defconfig +++ b/configs/verdin-am62p_a53_defconfig @@ -169,6 +169,7 @@ CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_REMOTEPROC_TI_K3_DSP=y CONFIG_RESET_TI_SCI=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y @@ -176,6 +177,8 @@ CONFIG_SOC_TI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y @@ -194,3 +197,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_HEXDUMP=y +# CONFIG_OPTEE_LIB is not set diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 7db6e81ee6d..ea085acd28f 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -76,6 +76,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_UUID=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set @@ -99,6 +100,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x44200000 CONFIG_FASTBOOT_FLASH=y @@ -108,7 +110,6 @@ CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y @@ -139,6 +140,7 @@ CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y @@ -161,4 +163,5 @@ CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_SHA_HW_ACCEL is not set CONFIG_HEXDUMP=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 4cc69de041b..065520071d1 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -162,6 +162,7 @@ CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_POWER_I2C=y +CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/doc/README.pxe b/doc/README.pxe deleted file mode 100644 index ba189080e8c..00000000000 --- a/doc/README.pxe +++ /dev/null @@ -1,292 +0,0 @@ -SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Calxeda, Inc. - */ - -The 'pxe' commands provide a near subset of the functionality provided by -the PXELINUX boot loader. This allows U-Boot based systems to be controlled -remotely using the same PXE based techniques that many non U-Boot based servers -use. - -Commands -======== - -pxe get -------- - syntax: pxe get - - follows PXELINUX's rules for retrieving configuration files from a tftp - server, and supports a subset of PXELINUX's config file syntax. - - Environment - ----------- - 'pxe get' requires two environment variables to be set: - - pxefile_addr_r - should be set to a location in RAM large enough to hold - pxe files while they're being processed. Up to 16 config files may be - held in memory at once. The exact number and size of the files varies with - how the system is being used. A typical config file is a few hundred bytes - long. - - bootfile,serverip - these two are typically set in the DHCP response - handler, and correspond to fields in the DHCP response. - - 'pxe get' optionally supports these two environment variables being set: - - ethaddr - this is the standard MAC address for the ethernet adapter in use. - 'pxe get' uses it to look for a configuration file specific to a system's - MAC address. - - pxeuuid - this is a UUID in standard form using lower case hexadecimal - digits, for example, 550e8400-e29b-41d4-a716-446655440000. 'pxe get' uses - it to look for a configuration file based on the system's UUID. - - File Paths - ---------- - 'pxe get' repeatedly tries to download config files until it either - successfully downloads one or runs out of paths to try. The order and - contents of paths it tries mirrors exactly that of PXELINUX - you can - read in more detail about it at: - - http://syslinux.zytor.com/wiki/index.php/Doc/pxelinux - -pxe boot --------- - syntax: pxe boot [pxefile_addr_r] - - Interprets a pxe file stored in memory. - - pxefile_addr_r is an optional argument giving the location of the pxe file. - The file must be terminated with a NUL byte. - - Environment - ----------- - There are some environment variables that may need to be set, depending - on conditions. - - pxefile_addr_r - if the optional argument pxefile_addr_r is not supplied, - an environment variable named pxefile_addr_r must be supplied. This is - typically the same value as is used for the 'pxe get' command. - - bootfile - typically set in the DHCP response handler based on the - same field in the DHCP respone, this path is used to generate the base - directory that all other paths to files retrieved by 'pxe boot' will use. - If no bootfile is specified, paths used in pxe files will be used as is. - - serverip - typically set in the DHCP response handler, this is the IP - address of the tftp server from which other files will be retrieved. - - kernel_addr_r, initrd_addr_r - locations in RAM at which 'pxe boot' will - store the kernel(or FIT image) and initrd it retrieves from tftp. These - locations will be passed to the bootm command to boot the kernel. These - environment variables are required to be set. - - fdt_addr_r - location in RAM at which 'pxe boot' will store the fdt blob it - retrieves from tftp. The retrieval is possible if 'fdt' label is defined in - pxe file and 'fdt_addr_r' is set. If retrieval is possible, 'fdt_addr_r' - will be passed to bootm command to boot the kernel. - - fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm - command if it is set and 'fdt_addr_r' is not passed to bootm command. - - fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store - fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'. - - pxe_label_override - override label to be used, if exists, instead of the - default label. This will allow consumers to choose a pxe label at - runtime instead of having to prompt the user. If "pxe_label_override" is set - but does not exist in the pxe menu, pxe would fallback to the default label if - given, and no failure is returned but rather a warning message. - -pxe file format -=============== -The pxe file format is nearly a subset of the PXELINUX file format; see -http://syslinux.zytor.com/wiki/index.php/PXELINUX. It's composed of one line -commands - global commands, and commands specific to labels. Lines begining -with # are treated as comments. White space between and at the beginning of -lines is ignored. - -The size of pxe files and the number of labels is only limited by the amount -of RAM available to U-Boot. Memory for labels is dynamically allocated as -they're parsed, and memory for pxe files is statically allocated, and its -location is given by the pxefile_addr_r environment variable. The pxe code is -not aware of the size of the pxefile memory and will outgrow it if pxe files -are too large. - -Supported global commands -------------------------- -Unrecognized commands are ignored. - -default <label> - the label named here is treated as the default and is - the first label 'pxe boot' attempts to boot. - -fallback <label> - the label named here is treated as a fallback option that - may be attempted should it be detected that booting of - the default has failed to complete, for example via - U-Boot's boot count limit functionality. - -menu title <string> - sets a title for the menu of labels being displayed. - -menu include <path> - use tftp to retrieve the pxe file at <path>, which - is then immediately parsed as if the start of its - contents were the next line in the current file. nesting - of include up to 16 files deep is supported. - -prompt <flag> - if 1, always prompt the user to enter a label to boot - from. if 0, only prompt the user if timeout expires. - -timeout <num> - wait for user input for <num>/10 seconds before - auto-booting a node. - -label <name> - begin a label definition. labels continue until - a command not recognized as a label command is seen, - or EOF is reached. - -Supported label commands ------------------------- -labels end when a command not recognized as a label command is reached, or EOF. - -menu default - set this label as the default label to boot; this is - the same behavior as the global default command but - specified in a different way - -kernel <path> - if this label is chosen, use tftp to retrieve the kernel - (or FIT image) at <path>. it will be stored at the address - indicated in the kernel_addr_r environment variable, and - that address will be passed to bootm to boot this kernel. - For FIT image, The configuration specification can be - appended to the file name, with the format: - <path>#<conf>[#<extra-conf[#...]] - It will passed to bootm with that address. - (see: doc/uImage.FIT/command_syntax_extensions.txt) - It useful for overlay selection in pxe file - (see: doc/usage/fit/overlay-fdt-boot.rst). - -fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT - overlay(s) at <path>. it will be temporarily stored at the - address indicated in the fdtoverlay_addr_r environment variable, - and then applied in the load order to the fdt blob stored at the - address indicated in the fdt_addr_r environment variable. - -devicetree-overlay <path> [...] - if this label is chosen, use tftp to retrieve the DT - overlay(s) at <path>. it will be temporarily stored at the - address indicated in the fdtoverlay_addr_r environment variable, - and then applied in the load order to the fdt blob stored at the - address indicated in the fdt_addr_r environment variable. - Alias for fdtoverlays. - -kaslrseed - set this label to request random number from hwrng as kaslr seed. - -append <string> - use <string> as the kernel command line when booting this - label. Environment variable references like ${var} are - substituted before boot. - -initrd <path> - if this label is chosen, use tftp to retrieve the initrd - at <path>. it will be stored at the address indicated in - the initrd_addr_r environment variable, and that address - will be passed to bootm. - For FIT image, the initrd can be provided with the same value than - kernel, including configuration: - <path>#<conf>[#<extra-conf[#...]] - In this case, kernel_addr_r is passed to bootm. - -fdt <path> - if this label is chosen, use tftp to retrieve the fdt blob - at <path>. it will be stored at the address indicated in - the fdt_addr_r environment variable, and that address will - be passed to bootm. - For FIT image, the device tree can be provided with the same value - than kernel, including configuration: - <path>#<conf>[#<extra-conf[#...]] - In this case, kernel_addr_r is passed to bootm. - -devicetree <path> - if this label is chosen, use tftp to retrieve the fdt blob - at <path>. it will be stored at the address indicated in - the fdt_addr_r environment variable, and that address will - be passed to bootm. Alias for fdt. - -fdtdir <path> - if this label is chosen, use tftp to retrieve a fdt blob - relative to <path>. If the fdtfile environment variable - is set, <path>/<fdtfile> is retrieved. Otherwise, the - filename is generated from the soc and board environment - variables, i.e. <path>/<soc>-<board>.dtb is retrieved. - If the fdt command is specified, fdtdir is ignored. - -localboot <flag> - Run the command defined by "localcmd" in the environment. - <flag> is ignored and is only here to match the syntax of - PXELINUX config files. - -Example -------- -Here's a couple of example files to show how this works. - -------------/tftpboot/pxelinux.cfg/menus/base.menu----------- -menu title Linux selections - -# This is the default label -label install - menu label Default Install Image - kernel kernels/install.bin - append console=ttyAMA0,38400 debug earlyprintk - initrd initrds/uzInitrdDebInstall - -# Just another label -label linux-2.6.38 - kernel kernels/linux-2.6.38.bin - append root=/dev/sdb1 - -# The locally installed kernel -label local - menu label Locally installed kernel - append root=/dev/sdb1 - localboot 1 -------------------------------------------------------------- - -------------/tftpboot/pxelinux.cfg/default------------------- -menu include pxelinux.cfg/menus/base.menu -timeout 500 - -default linux-2.6.38 -------------------------------------------------------------- - -When a pxe client retrieves and boots the default pxe file, -'pxe boot' will wait for user input for 5 seconds before booting -the linux-2.6.38 label, which will cause /tftpboot/kernels/linux-2.6.38.bin -to be downloaded, and boot with the command line "root=/dev/sdb1" - -Differences with PXELINUX -========================= -The biggest difference between U-Boot's pxe and PXELINUX is that since -U-Boot's pxe support is written entirely in C, it can run on any platform -with network support in U-Boot. Here are some other differences between -PXELINUX and U-Boot's pxe support. - -- U-Boot's pxe does not support the PXELINUX DHCP option codes specified - in RFC 5071, but could be extended to do so. - -- when U-Boot's pxe fails to boot, it will return control to U-Boot, - allowing another command to run, other U-Boot command, instead of resetting - the machine like PXELINUX. - -- U-Boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it - only uses U-Boot. - -- U-Boot's pxe doesn't provide the full menu implementation that PXELINUX - does, only a simple text based menu using the commands described in - this README. With PXELINUX, it's possible to have a graphical boot - menu, submenus, passwords, etc. U-Boot's pxe could be extended to support - a more robust menuing system like that of PXELINUX's. - -- U-Boot's pxe expects U-Boot uimg's as kernels. Anything that would work - with the 'bootm' command in U-Boot could work with the 'pxe boot' command. - -- U-Boot's pxe only recognizes a single file on the initrd command line. It - could be extended to support multiple. - -- in U-Boot's pxe, the localboot command doesn't necessarily cause a local - disk boot - it will do whatever is defined in the 'localcmd' env - variable. And since it doesn't support a full UNDI/PXE stack, the - type field is ignored. - -- the interactive prompt in U-Boot's pxe only allows you to choose a label - from the menu. If you want to boot something not listed, you can ctrl+c - out of 'pxe boot' and use existing U-Boot commands to accomplish it. diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 6f92cd28eb1..19e2ee9d407 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -32,7 +32,7 @@ The following OEM commands are supported (if enabled): - ``oem console`` - this dumps U-Boot console record buffer - ``oem board`` - this executes a custom board function which is defined by the vendor -Support for both eMMC and NAND devices is included. +Support for eMMC, NAND and SPI flash memory devices is included. Client installation ------------------- @@ -97,8 +97,9 @@ Raw partition descriptors ^^^^^^^^^^^^^^^^^^^^^^^^^ In cases where no partition table is present, a raw partition descriptor can be -defined, specifying the offset, size, and optionally the MMC hardware partition -number for a given partition name. +defined, specifying the memory offset and size. + +Currently, this support is available only for eMMC and SPI flash memory devices. This is useful when using fastboot to flash files (e.g. SPL or U-Boot) to a specific offset in the eMMC boot partition, without having to update the entire @@ -106,6 +107,15 @@ boot partition. To define a raw partition descriptor, add an environment variable similar to:: + fastboot_raw_partition_<raw partition name>=<offset> <size> + +for example:: + + fastboot_raw_partition_boot=0x100 0x1f00 + +Optionally, in the eMMC case, the hardware partition number can also be +specified for a given partition name:: + fastboot_raw_partition_<raw partition name>=<offset> <size> [mmcpart <num>] for example:: diff --git a/doc/board/nxp/imx95_evk.rst b/doc/board/nxp/imx95_evk.rst index 9121f7561ab..27cd15eb7c9 100644 --- a/doc/board/nxp/imx95_evk.rst +++ b/doc/board/nxp/imx95_evk.rst @@ -23,9 +23,9 @@ Note: srctree is U-Boot source directory .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin - $ sh firmware-ele-imx-1.3.0-17945fc.bin --auto-accept - $ cp firmware-ele-imx-1.3.0-17945fc/mx95a0-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) Get DDR PHY Firmware Images -------------------------------------- @@ -34,9 +34,9 @@ Note: srctree is U-Boot source directory .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.26-d4c33ab.bin - $ sh firmware-imx-8.26-d4c33ab.bin --auto-accept - $ cp firmware-imx-8.26-d4c33ab/firmware/ddr/synopsys/lpddr5*v202311.bin $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) Get and Build OEI Images -------------------------------------- diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index ccf834208e9..3238a68e859 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -6,10 +6,11 @@ Qualcomm .. toctree:: :maxdepth: 2 + board + debugging dragonboard410c - rb3gen2 dragonwing - board + rb3gen2 + iq8 phones - debugging rdp diff --git a/doc/board/qualcomm/iq8.rst b/doc/board/qualcomm/iq8.rst new file mode 100644 index 00000000000..f3df0ee00bc --- /dev/null +++ b/doc/board/qualcomm/iq8.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. sectionauthor:: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> + +Qualcomm DragonWing IQ8 +======================================== + +The Dragonwing IQ8 Series (which includes QCS8300) powers computeheavy and AI-based devices, and is designed +to operate in an expanded temperature range with available built-in safety features. +Dragonwing IQ8 Series delivers industrial-grade AI performance of up to 40 TOPS, an octa-core +Qualcomm Kryo Gen 6 CPU, a powerful Qualcomm Adreno 623 GPU, support for +up to 12 concurrent cameras, and 4K video encode and decode alongside multiple displays. + +More information can be found on the `Qualcomm's IQ8 product page`_. + +.. _Qualcomm's IQ8 product page: https://docs.qualcomm.com/bundle/publicresource/87-83839-1_REV_A_Qualcomm_IQ8_Series_Product_Brief________.pdf + +Installation +------------ +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``QCS8300``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make qcom_qcs8300_defconfig + $ make -j8 u-boot.mbn + +This will build the signed ``u-boot.mbn`` in the configured output directory. +The firmware expects firmware ELF images to be "signed". The signature +does not provide any security in this case, but it provides the firmware +with some required metadata. + +Then flash the resulting ``u-boot.mbn`` to the ``uefi_a`` partition +on your device with ``fastboot flash uefi_a u-boot.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +Note that fastboot is not yet supported in U-Boot on Dragonwing IQ8, as a result, to flash +back the original firmware, or new versoins of the U-Boot, EDL mode must be used. + +A tool like bkerler's `edl`_ can be used for flashing. + +$ edl.py --loader /path/to/prog_firehose_ddr.elf w uefi_a u-boot.mbn + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _edl: https://github.com/bkerler/edl diff --git a/doc/git-mailrc b/doc/git-mailrc index 50f896de8e8..747ceda3307 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -13,7 +13,7 @@ alias u-boot uboot alias abiessmann Andreas Bießmann <andreas@biessmann.org> alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com> alias afleming Andy Fleming <afleming@gmail.com> -alias ag Anatolij Gustschin <agust@denx.de> +alias ag Anatolij Gustschin <ag.dev.uboot@gmail.com> alias agraf Alexander Graf <agraf@csgraf.de> alias alexnemirovsky Alex Nemirovsky <alex.nemirovsky@cortina-access.com> alias alisonwang Alison Wang <alison.wang@nxp.com> @@ -46,7 +46,7 @@ alias sbabic Stefano Babic <sbabic@nabladev.com> alias simongoldschmidt Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> alias sjg Simon Glass <sjg@chromium.org> alias smcnutt Scott McNutt <smcnutt@psyent.com> -alias stroese Stefan Roese <sr@denx.de> +alias stroese Stefan Roese <stefan.roese@mailbox.org> alias tienfong Tien Fong Chee <tien.fong.chee@intel.com> alias trini Tom Rini <trini@konsulko.com> alias wd Wolfgang Denk <wd@denx.de> diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 12c5772684d..8572c15ef68 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -10,7 +10,7 @@ MarkupSafe==3.0.2 packaging==24.1 pip==24.2 Pygments==2.18.0 -requests==2.32.3 +requests==2.32.4 six==1.16.0 snowballstemmer==2.2.0 Sphinx==8.1.3 @@ -24,4 +24,4 @@ sphinxcontrib-jquery==4.1 sphinxcontrib-jsmath==1.0.1 sphinxcontrib-qthelp==2.0.0 sphinxcontrib-serializinghtml==2.0.0 -urllib3==2.2.3 +urllib3==2.5.0 diff --git a/doc/usage/fit/x86-fit-boot.rst b/doc/usage/fit/x86-fit-boot.rst index 9e3e32204d5..18704af3bac 100644 --- a/doc/usage/fit/x86-fit-boot.rst +++ b/doc/usage/fit/x86-fit-boot.rst @@ -259,11 +259,12 @@ Why Bother? References ---------- -In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for +In the Linux kernel, `Documentation/arch/x86/boot.rst +<https://docs.kernel.org/arch/x86/boot.html>`_ defines the boot protocol for the kernel including the setup.bin format. This is handled in U-Boot in arch/x86/lib/zimage.c and arch/x86/lib/bootm.c. -Various files in the same directory as this file describe the FIT format. - +The FIT file format is described in the `Flattened Image Tree Specification +<https://fitspec.osfw.foundation/>`_. .. sectionauthor:: Simon Glass <sjg@chromium.org> 7-Oct-2014 diff --git a/doc/usage/index.rst b/doc/usage/index.rst index e9e0bd04e05..b9de87a6ed9 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -12,6 +12,7 @@ Use U-Boot fit/index netconsole partitions + pxe cmdline semihosting measured_boot diff --git a/doc/usage/pxe.rst b/doc/usage/pxe.rst new file mode 100644 index 00000000000..c2dc11f218d --- /dev/null +++ b/doc/usage/pxe.rst @@ -0,0 +1,346 @@ +.. SPDX-License-Identifier: GPL-2.0+ + Copyright 2010-2011 Calxeda, Inc. + +PXE Boot and extlinux.conf +========================== + +The ``pxe`` commands provide a near subset of the functionality +provided by the PXELINUX boot loader. This allows U-Boot based systems +to be controlled remotely using the same PXE based techniques that +many non U-Boot based servers use. + +The ``sysboot`` command and Extlinux boot method use the same file +format as PXE boot for ``extlinux.conf``. + +Commands +-------- + +``pxe get`` + **Syntax:** ``pxe get`` + + follows PXELINUX's rules for retrieving configuration files + from a tftp server, and supports a subset of PXELINUX's config + file syntax. It requires certain environment variables to be + set, see the Environment section below. + + **File Paths** + + ``pxe get`` repeatedly tries to download config files until it + either successfully downloads one or runs out of paths to + try. The order and contents of paths it tries mirrors exactly + that of PXELINUX - you can read in more detail about it at: + + http://syslinux.zytor.com/wiki/index.php/Doc/pxelinux + +``pxe boot`` + **Syntax:** ``pxe boot [pxefile_addr_r]`` + + Interprets a pxe file stored in memory. + + ``pxefile_addr_r`` is an optional argument giving the location + of the pxe file. The file must be terminated with a NUL byte. + + There are some environment variables that may need to be set, + depending on conditions, see the Environment section below. + +``sysboot`` + **Syntax:** ``sysboot [-p] <interface> <dev[:part]> <ext2|fat|any> [addr] [filename]`` + + Load and boot an ``extlinux.conf`` file from a local + filesystem. Paths in the ``extlinux.conf`` file (kernel, + initrd, FDT and overlays) will be interpreted within that + filesystem. + + Example: + + ``sysboot mmc 0.0:2 any ${pxefile_addr_r} /boot/extlinux.conf`` + +Environment +----------- + +``pxefile_addr_r`` + Should be set to a location in RAM large enough to hold pxe + files while they're being processed. Up to 16 config files may + be held in memory at once. The exact number and size of the + files varies with how the system is being used. A typical + config file is a few hundred bytes long. Required for ``pxe + get``, for ``pxe boot`` if the optional argument + ``pxefile_addr_r`` is not supplied. + +``bootfile`` + Typically set in the DHCP response handler, required for ``pxe + get``. For ``pxe boot``, this path is used to generate the + base directory that all other paths to files retrieved by + ``pxe boot`` will use. If no bootfile is specified, paths used + in pxe files will be used as is. + +``serverip`` + Typically set in the DHCP response handler, this is the IP + address of the tftp server from which other files will be + retrieved. Required for ``pxe get``. + +``kernel_addr_r``, ``initrd_addr_r`` + Locations in RAM to store the kernel (or FIT image) and + initrd. These locations will be passed to the ``bootm`` + command to boot the kernel. These environment variables are + required to be set. + +``fdt_addr_r`` + Location in RAM to store the retrieved fdt blob. Retrieval is + possible if ``fdt`` label is defined in pxe file and + ``fdt_addr_r`` is set. If retrieval is possible, + ``fdt_addr_r`` will be passed to ``bootm`` command to boot the + kernel. + +``fdt_addr`` + Location of a fdt blob. ``fdt_addr`` will be passed to + ``bootm`` command if it is set and ``fdt_addr_r`` is not + passed to bootm command. + +``fdtoverlay_addr_r`` + Location in RAM to temporarily store fdt overlay(s) before + applying them to the fdt blob stored at + ``fdt_addr_r``. Required to use the ``fdtoverlays`` command in + the PXE file. + +``pxe_label_override`` + Override label to be used, if exists, instead of the default + label. This will allow consumers to choose a pxe label at + runtime instead of having to prompt the user. If + ``pxe_label_override`` is set but does not exist in the pxe + menu, pxe would fallback to the default label if given, and no + failure is returned but rather a warning message. + +``ethaddr`` + This is the standard MAC address for the ethernet adapter in + use. ``pxe get`` uses it to look for a configuration file + specific to a system's MAC address. + +``pxeuuid`` + This is a UUID in standard form using lower case hexadecimal + digits, for example, + 550e8400-e29b-41d4-a716-446655440000. ``pxe get`` uses it to + look for a configuration file based on the system's UUID. + +pxe file format +--------------- + +The pxe file format is nearly a subset of the PXELINUX file format; +see http://syslinux.zytor.com/wiki/index.php/PXELINUX. It's composed +of one line commands - global commands, and commands specific to +labels. Lines beginning with # are treated as comments. White space +between and at the beginning of lines is ignored. + +The size of pxe files and the number of labels is only limited by the amount +of RAM available to U-Boot. Memory for labels is dynamically allocated as +they're parsed, and memory for pxe files is statically allocated, and its +location is given by the pxefile_addr_r environment variable. The pxe code is +not aware of the size of the pxefile memory and will outgrow it if pxe files +are too large. + +Supported global commands +^^^^^^^^^^^^^^^^^^^^^^^^^ +Unrecognized commands are ignored. + +``default <label>`` + The label named here is treated as the default and is the + first label 'pxe boot' attempts to boot. + +``fallback <label>`` + The label named here is treated as a fallback option that may + be attempted should it be detected that booting of the default + has failed to complete, for example via U-Boot's boot count + limit functionality. + +``menu title <string>`` + Sets a title for the menu of labels being displayed. + +``menu include <path>`` + Use tftp to retrieve the pxe file at ``<path>``, which is then + immediately parsed as if the start of its contents were the + next line in the current file. nesting of include up to 16 + files deep is supported. + +``prompt <flag>`` + If 1, always prompt the user to enter a label to boot from. If + 0, only prompt the user if timeout expires. + +``timeout <num>`` + Wait for user input for <num>/10 seconds before auto-booting a + node. + +``label <name>`` + Begin a label definition. Labels continue until a command not + recognized as a label command is seen, or EOF is reached. + +Supported label commands +^^^^^^^^^^^^^^^^^^^^^^^^ +Labels end when a command not recognized as a label command is reached, or EOF. + +``menu default`` + set this label as the default label to boot; this is the same + behavior as the global default command but specified in a + different way + +``kernel <path>`` + If this label is chosen, use tftp to retrieve the kernel (or + FIT image) at ``<path>``. it will be stored at the address + indicated in the ``kernel_addr_r`` environment variable, and + that address will be passed to ``bootm`` to boot this + kernel. For FIT image, the configuration specification can be + appended to the file name, with the format: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + It will be passed to bootm with that address (see: + doc/uImage.FIT/command_syntax_extensions.txt). It is useful + for overlay selection in pxe file (see + :doc:`./fit/overlay-fdt-boot`). + +``fdtoverlays <path> [...]`` + If this label is chosen, use tftp to retrieve the DT + overlay(s) at ``<path>``. It will be temporarily stored at the + address indicated in the ``fdtoverlay_addr_r`` environment + variable, and then applied in the load order to the fdt blob + stored at the address indicated in the ``fdt_addr_r`` + environment variable. + +``devicetree-overlay <path> [...]`` + if this label is chosen, use tftp to retrieve the DT + overlay(s) at ``<path>``. It will be temporarily stored at the + address indicated in the ``fdtoverlay_addr_r`` environment + variable, and then applied in the load order to the fdt blob + stored at the address indicated in the ``fdt_addr_r`` + environment variable. Alias for fdtoverlays. + +``kaslrseed`` + set this label to request random number from hwrng as kaslr seed. + +``append <string>`` + Use ``<string>`` as the kernel command line when booting this + label. Environment variable references like ``${var}`` are + substituted before boot. + +``initrd <path>`` + If this label is chosen, use tftp to retrieve the initrd at + ``<path>``. it will be stored at the address indicated in the + ``initrd_addr_r`` environment variable, and that address will + be passed to ``bootm``. For FIT image, the initrd can be + provided with the same value than kernel, including + configuration: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + In this case, ``kernel_addr_r`` is passed to ``bootm``. + +``fdt <path>`` + If this label is chosen, use tftp to retrieve the fdt blob at + ``<path>``. It will be stored at the address indicated in the + ``fdt_addr_r`` environment variable, and that address will be + passed to ``bootm``. For FIT image, the device tree can be + provided with the same value than kernel, including + configuration: + + ``<path>#<conf>[#<extra-conf[#...]]`` + + In this case, ``kernel_addr_r`` is passed to ``bootm``. + +``devicetree <path>`` + If this label is chosen, use tftp to retrieve the fdt blob at + ``<path>``. it will be stored at the address indicated in the + ``fdt_addr_r`` environment variable, and that address will be + passed to ``bootm``. Alias for fdt. + +``fdtdir <path>`` + If this label is chosen, use tftp to retrieve a fdt blob + relative to ``<path>``. If the ``fdtfile`` environment + variable is set, ``<path>/<fdtfile>`` is retrieved. Otherwise, + the filename is generated from the ``soc`` and ``board`` + environment variables, i.e. ``<path>/<soc>-<board>.dtb`` is + retrieved. If the ``fdt`` command is specified, ``fdtdir`` is + ignored. + +``localboot <flag>`` + Run the command defined by ``localcmd`` in the + environment. ``<flag>`` is ignored and is only here to match + the syntax of PXELINUX config files. + +Example +------- +Here's a couple of example files to show how this works. + +.. code-block:: + :caption: /tftpboot/pxelinux.cfg/menus/base.menu + + menu title Linux selections + + # This is the default label + label install + menu label Default Install Image + kernel kernels/install.bin + append console=ttyAMA0,38400 debug earlyprintk + initrd initrds/uzInitrdDebInstall + + # Just another label + label linux-2.6.38 + kernel kernels/linux-2.6.38.bin + append root=/dev/sdb1 + + # The locally installed kernel + label local + menu label Locally installed kernel + append root=/dev/sdb1 + localboot 1 + +.. code-block:: + :caption: /tftpboot/pxelinux.cfg/default + + menu include pxelinux.cfg/menus/base.menu + timeout 500 + + default linux-2.6.38 + +When a pxe client retrieves and boots the default pxe file, ``pxe +boot`` will wait for user input for 5 seconds before booting the +``linux-2.6.38`` label, which will cause +``/tftpboot/kernels/linux-2.6.38.bin`` to be downloaded, and boot with +the command line ``root=/dev/sdb1`` + +Differences with PXELINUX +------------------------- + +The biggest difference between U-Boot's pxe and PXELINUX is that since +U-Boot's pxe support is written entirely in C, it can run on any platform +with network support in U-Boot. Here are some other differences between +PXELINUX and U-Boot's pxe support. + +- U-Boot's pxe does not support the PXELINUX DHCP option codes specified + in RFC 5071, but could be extended to do so. + +- when U-Boot's pxe fails to boot, it will return control to U-Boot, + allowing another command to run, other U-Boot command, instead of resetting + the machine like PXELINUX. + +- U-Boot's pxe doesn't rely on or provide an UNDI/PXE stack in memory, it + only uses U-Boot. + +- U-Boot's pxe doesn't provide the full menu implementation that PXELINUX + does, only a simple text based menu using the commands described in + this README. With PXELINUX, it's possible to have a graphical boot + menu, submenus, passwords, etc. U-Boot's pxe could be extended to support + a more robust menuing system like that of PXELINUX's. + +- U-Boot's pxe expects U-Boot uimg's as kernels. Anything that would work + with the 'bootm' command in U-Boot could work with the 'pxe boot' command. + +- U-Boot's pxe only recognizes a single file on the initrd command line. It + could be extended to support multiple. + +- in U-Boot's pxe, the localboot command doesn't necessarily cause a local + disk boot - it will do whatever is defined in the 'localcmd' env + variable. And since it doesn't support a full UNDI/PXE stack, the + type field is ignored. + +- the interactive prompt in U-Boot's pxe only allows you to choose a label + from the menu. If you want to boot something not listed, you can ctrl+c + out of 'pxe boot' and use existing U-Boot commands to accomplish it. diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 6c74d66037e..9cb27561a97 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; static unsigned long host_block_read(struct udevice *dev, - unsigned long start, lbaint_t blkcnt, + lbaint_t start, lbaint_t blkcnt, void *buffer) { struct blk_desc *desc = dev_get_uclass_plat(dev); @@ -26,7 +26,7 @@ static unsigned long host_block_read(struct udevice *dev, struct host_sb_plat *plat = dev_get_plat(host_dev); if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { - printf("ERROR: Invalid block %lx\n", start); + printf("ERROR: Invalid block " LBAF "\n", start); return -1; } ssize_t len = os_read(plat->fd, buffer, blkcnt * desc->blksz); @@ -37,7 +37,7 @@ static unsigned long host_block_read(struct udevice *dev, } static unsigned long host_block_write(struct udevice *dev, - unsigned long start, lbaint_t blkcnt, + lbaint_t start, lbaint_t blkcnt, const void *buffer) { struct blk_desc *desc = dev_get_uclass_plat(dev); @@ -45,7 +45,7 @@ static unsigned long host_block_write(struct udevice *dev, struct host_sb_plat *plat = dev_get_plat(host_dev); if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { - printf("ERROR: Invalid block %lx\n", start); + printf("ERROR: Invalid block " LBAF "\n", start); return -1; } ssize_t len = os_write(plat->fd, buffer, blkcnt * desc->blksz); diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 364454644a6..7c49e99c005 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -193,6 +193,7 @@ static const struct gate_clk sm8650_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x39088, BIT(0)), }; static int sm8650_enable(struct clk *clk) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index b80ad05b8ad..822cf0809d5 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -32,6 +32,7 @@ struct ccu_internal { struct ccu_div_internal { u8 shift; u8 width; + unsigned long flags; }; struct ccu_common { @@ -79,6 +80,7 @@ struct ccu_pll { { \ .shift = _shift, \ .width = _width, \ + .flags = _flags, \ } #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ @@ -182,7 +184,7 @@ static unsigned long ccu_div_get_rate(struct clk *clk) val = val >> cd->div.shift; val &= GENMASK(cd->div.width - 1, 0); rate = divider_recalc_rate(clk, clk_get_parent_rate(clk), val, NULL, - 0, cd->div.width); + cd->div.flags, cd->div.width); return rate; } diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 26e014d5c53..e040e3f2806 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1961,6 +1961,12 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, ofnode uboot; *bootscr_flash_offset = 0; + + if (!bootscr_flash_size) { + dm_warn("bootscr-flash-size is zero. Ignoring properties!\n"); + return -EINVAL; + } + *bootscr_flash_size = 0; uboot = ofnode_path("/options/u-boot"); @@ -1979,12 +1985,6 @@ int ofnode_read_bootscript_flash(u64 *bootscr_flash_offset, if (ret) return -EINVAL; - if (!bootscr_flash_size) { - dm_warn("bootscr-flash-size is zero. Ignoring properties!\n"); - *bootscr_flash_offset = 0; - return -EINVAL; - } - return 0; } diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 8b49997030b..d26f87364f9 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -2,6 +2,8 @@ menu "Hardware crypto devices" source "drivers/crypto/hash/Kconfig" +source "drivers/crypto/aes/Kconfig" + source "drivers/crypto/fsl/Kconfig" source "drivers/crypto/aspeed/Kconfig" diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index b9105186097..2bd99fc2763 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -4,6 +4,7 @@ # http://www.samsung.com obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-y += aes/ obj-y += rsa_mod_exp/ obj-y += fsl/ obj-y += hash/ diff --git a/drivers/crypto/aes/Kconfig b/drivers/crypto/aes/Kconfig new file mode 100644 index 00000000000..7e1b1b2875d --- /dev/null +++ b/drivers/crypto/aes/Kconfig @@ -0,0 +1,12 @@ +config DM_AES + bool "Enable Driver Model for AES crypto operations" + depends on DM + help + If you want to use driver model for AES crypto operations, say Y. + +config AES_SOFTWARE + bool "Enable driver for AES in software" + depends on DM_AES && AES + help + Enable driver for AES crypto operations in software. Uses U-Boot + AES library. diff --git a/drivers/crypto/aes/Makefile b/drivers/crypto/aes/Makefile new file mode 100644 index 00000000000..d38a2e1526d --- /dev/null +++ b/drivers/crypto/aes/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_$(PHASE_)DM_AES) += aes-uclass.o +obj-$(CONFIG_$(PHASE_)AES_SOFTWARE) += aes-sw.o diff --git a/drivers/crypto/aes/aes-sw.c b/drivers/crypto/aes/aes-sw.c new file mode 100644 index 00000000000..a65200fb79b --- /dev/null +++ b/drivers/crypto/aes/aes-sw.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <uboot_aes.h> + +#define SW_KEY_SLOTS 2 + +struct sw_aes_priv { + u8 key_slots[SW_KEY_SLOTS][AES256_KEY_LENGTH]; + u8 key_schedule[AES256_EXPAND_KEY_LENGTH]; + u8 selected_slot; + u32 selected_key_size; + bool key_expanded; +}; + +static int prepare_aes(struct sw_aes_priv *priv) +{ + if (!priv->selected_key_size) { + log_debug("%s: AES key size not set, setup a slot first\n", __func__); + return 1; + } + + if (priv->key_expanded) + return 0; + + priv->key_expanded = 1; + + aes_expand_key(priv->key_slots[priv->selected_slot], priv->selected_key_size, + priv->key_schedule); + + return 0; +} + +static int sw_aes_ops_available_key_slots(struct udevice *dev) +{ + return SW_KEY_SLOTS; +} + +static int sw_aes_ops_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + + if (slot >= SW_KEY_SLOTS) + return 1; + + priv->selected_slot = slot; + priv->selected_key_size = key_size; + priv->key_expanded = 0; + + return 0; +} + +static int sw_aes_ops_set_key_for_key_slot(struct udevice *dev, u32 key_size, + u8 *key, u8 slot) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + + if (slot >= SW_KEY_SLOTS) + return 1; + + memcpy(priv->key_slots[slot], key, key_size / 8); + + if (priv->selected_slot == slot) + priv->selected_key_size = key_size; + + priv->key_expanded = 0; + + return 0; +} + +static int sw_aes_ops_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + while (num_aes_blocks > 0) { + aes_encrypt(priv->selected_key_size, src, priv->key_schedule, dst); + num_aes_blocks -= 1; + src += AES_BLOCK_LENGTH; + dst += AES_BLOCK_LENGTH; + } + + return 0; +} + +static int sw_aes_ops_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + while (num_aes_blocks > 0) { + aes_decrypt(priv->selected_key_size, src, priv->key_schedule, dst); + num_aes_blocks -= 1; + src += AES_BLOCK_LENGTH; + dst += AES_BLOCK_LENGTH; + } + + return 0; +} + +static int sw_aes_ops_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + aes_cbc_encrypt_blocks(priv->selected_key_size, priv->key_schedule, iv, + src, dst, num_aes_blocks); + + return 0; +} + +static int sw_aes_ops_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + struct sw_aes_priv *priv = dev_get_priv(dev); + int ret; + + ret = prepare_aes(priv); + if (ret) + return ret; + + aes_cbc_decrypt_blocks(priv->selected_key_size, priv->key_schedule, + iv, src, dst, num_aes_blocks); + + return 0; +} + +static const struct aes_ops aes_ops_sw = { + .available_key_slots = sw_aes_ops_available_key_slots, + .select_key_slot = sw_aes_ops_select_key_slot, + .set_key_for_key_slot = sw_aes_ops_set_key_for_key_slot, + .aes_ecb_encrypt = sw_aes_ops_aes_ecb_encrypt, + .aes_ecb_decrypt = sw_aes_ops_aes_ecb_decrypt, + .aes_cbc_encrypt = sw_aes_ops_aes_cbc_encrypt, + .aes_cbc_decrypt = sw_aes_ops_aes_cbc_decrypt, +}; + +static const struct udevice_id sw_aes_ids[] = { + { .compatible = "software-aes-engine" }, + { } +}; + +U_BOOT_DRIVER(aes_sw) = { + .name = "aes_sw", + .id = UCLASS_AES, + .of_match = sw_aes_ids, + .ops = &aes_ops_sw, + .priv_auto = sizeof(struct sw_aes_priv), +}; diff --git a/drivers/crypto/aes/aes-uclass.c b/drivers/crypto/aes/aes-uclass.c new file mode 100644 index 00000000000..745c6ce57a9 --- /dev/null +++ b/drivers/crypto/aes/aes-uclass.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_AES + +#include <dm.h> +#include <malloc.h> +#include <log.h> +#include <uboot_aes.h> +#include <linux/string.h> + +int dm_aes_get_available_key_slots(struct udevice *dev) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->available_key_slots) + return -ENOSYS; + + return ops->available_key_slots(dev); +} + +int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->select_key_slot) + return -ENOSYS; + + return ops->select_key_slot(dev, key_size, slot); +} + +int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->set_key_for_key_slot) + return -ENOSYS; + + return ops->set_key_for_key_slot(dev, key_size, key, slot); +} + +int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_ecb_encrypt) + return -ENOSYS; + + return ops->aes_ecb_encrypt(dev, src, dst, num_aes_blocks); +} + +int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_ecb_decrypt) + return -ENOSYS; + + return ops->aes_ecb_decrypt(dev, src, dst, num_aes_blocks); +} + +int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_cbc_encrypt) + return -ENOSYS; + + return ops->aes_cbc_encrypt(dev, iv, src, dst, num_aes_blocks); +} + +int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const struct aes_ops *ops; + + if (!dev) + return -ENODEV; + + ops = aes_get_ops(dev); + + if (!ops->aes_cbc_decrypt) + return -ENOSYS; + + return ops->aes_cbc_decrypt(dev, iv, src, dst, num_aes_blocks); +} + +static void left_shift_vector(u8 *in, u8 *out, int size) +{ + int carry = 0; + int i; + + for (i = size - 1; i >= 0; i--) { + out[i] = (in[i] << 1) | carry; + carry = in[i] >> 7; /* get most significant bit */ + } +} + +int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + const u8 AES_CMAC_CONST_RB = 0x87; /* from RFC 4493, Figure 2.2 */ + const u32 TMP_BUFFER_LEN = 128; + u8 tmp_block[AES128_KEY_LENGTH] = { }; + u8 k1[AES128_KEY_LENGTH]; + u8 *tmp_buffer; + int ret; + + log_debug("%s: 0x%p -> %p blocks %d\n", __func__, src, dst, num_aes_blocks); + + if (!num_aes_blocks) { + log_debug("%s: called with 0 blocks!\n", __func__); + return -1; + } + + /* Compute K1 constant needed by AES-CMAC calculation */ + ret = dm_aes_cbc_encrypt(dev, (u8 *)AES_ZERO_BLOCK, (u8 *)AES_ZERO_BLOCK, tmp_block, 1); + if (ret) + return -1; + + left_shift_vector(tmp_block, k1, AES_BLOCK_LENGTH); + + if ((tmp_block[0] >> 7) != 0) /* get MSB of L */ + k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB; + + /* Set what will be the initial IV as zero */ + memset(tmp_block, 0, AES_BLOCK_LENGTH); + + /* Process all blocks except last by calling engine several times per dma buffer size */ + if (num_aes_blocks > 1) { + tmp_buffer = malloc(AES_BLOCK_LENGTH * min(num_aes_blocks - 1, TMP_BUFFER_LEN)); + while (num_aes_blocks > 1) { + u32 blocks = min(num_aes_blocks - 1, TMP_BUFFER_LEN); + + /* Encrypt the current remaining set of blocks that fits in tmp buffer */ + ret = dm_aes_cbc_encrypt(dev, tmp_block, src, tmp_buffer, blocks); + if (ret) + return -1; + + num_aes_blocks -= blocks; + src += blocks * AES_BLOCK_LENGTH; + + /* Copy the last encrypted block to tmp_block as IV */ + memcpy(tmp_block, tmp_buffer + ((blocks - 1) * AES_BLOCK_LENGTH), + AES_BLOCK_LENGTH); + } + free(tmp_buffer); + } + + if (num_aes_blocks != 1) { + log_debug("%s: left with %d blocks! must be 1\n", __func__, num_aes_blocks); + return -1; + } + + /* XOR last IV with K1 */ + aes_apply_cbc_chain_data(tmp_block, k1, tmp_block); + + /* Encrypt the last src block already with tmp_block as IV and output to dst */ + return dm_aes_cbc_encrypt(dev, tmp_block, src, dst, 1); +} + +UCLASS_DRIVER(aes) = { + .id = UCLASS_AES, + .name = "aes", +}; diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 756569217bb..eefdf44ec87 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -147,7 +147,7 @@ int dfu_config_interfaces(char *env) break; a = strsep(&s, "&"); if (!a) - a = s; + a = d; do { part = strsep(&a, ";"); part = skip_spaces(part); diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 70207573de2..843171902ae 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -91,7 +91,7 @@ config FASTBOOT_USB_DEV config FASTBOOT_FLASH bool "Enable FASTBOOT FLASH command" default y if ARCH_SUNXI || ARCH_ROCKCHIP - depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) + depends on MMC || (MTD_RAW_NAND && CMD_MTDPARTS) || DM_SPI_FLASH select IMAGE_SPARSE help The fastboot protocol includes a "flash" command for writing @@ -119,6 +119,10 @@ config FASTBOOT_FLASH_NAND bool "FASTBOOT on NAND" depends on MTD_RAW_NAND && CMD_MTDPARTS +config FASTBOOT_FLASH_SPI + bool "FASTBOOT on SPI flash" + depends on DM_SPI_FLASH + endchoice config FASTBOOT_FLASH_MMC_DEV diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index 048af5aa823..adedba0bf24 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -5,3 +5,4 @@ obj-y += fb_getvar.o obj-y += fb_command.o obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o +obj-$(CONFIG_FASTBOOT_FLASH_SPI) += fb_spi_flash.o diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 2cdbac50ac4..791088bc094 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -10,6 +10,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <part.h> #include <stdlib.h> #include <vsprintf.h> @@ -344,6 +345,10 @@ static void __maybe_unused flash(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_write(cmd_parameter, fastboot_buf_addr, + image_size, response); } /** @@ -362,6 +367,9 @@ static void __maybe_unused erase(char *cmd_parameter, char *response) if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_erase(cmd_parameter, response); + + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) + fastboot_spi_flash_erase(cmd_parameter, response); } /** @@ -405,7 +413,7 @@ static void __maybe_unused run_acmd(char *cmd_parameter, char *response) return; } - if (strlen(cmd_parameter) > sizeof(g_a_cmd_buff)) { + if (strlen(cmd_parameter) >= sizeof(g_a_cmd_buff)) { pr_err("too long command\n"); fastboot_fail("too long command", response); return; diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 9c2ce65a4e5..6775ea397ab 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -8,6 +8,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <fb_spi_flash.h> #include <fs.h> #include <part.h> #include <version.h> @@ -123,6 +124,11 @@ static int getvar_get_part_info(const char *part_name, char *response, r = fastboot_nand_get_part_info(part_name, &part_info, response); if (r >= 0 && size) *size = part_info->size; + } else if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_SPI)) { + r = fastboot_spi_flash_get_part_info(part_name, &disk_part, + response); + if (r >= 0 && size) + *size = disk_part.size * disk_part.blksz; } else { fastboot_fail("this storage is not supported in bootloader", response); r = -ENODEV; diff --git a/drivers/fastboot/fb_spi_flash.c b/drivers/fastboot/fb_spi_flash.c new file mode 100644 index 00000000000..691be7c7ef7 --- /dev/null +++ b/drivers/fastboot/fb_spi_flash.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Collabora Ltd. + */ + +#include <blk.h> +#include <config.h> +#include <env.h> +#include <fastboot.h> +#include <image-sparse.h> +#include <spi.h> +#include <spi_flash.h> +#include <dm.h> +#include <dm/device-internal.h> + +static struct spi_flash *flash; + +__weak int board_fastboot_spi_flash_write_setup(void) +{ + return 0; +} + +__weak int board_fastboot_spi_flash_erase_setup(void) +{ + return 0; +} + +static int raw_part_get_info_by_name(const char *name, + struct disk_partition *part_info) +{ + /* strlen("fastboot_raw_partition_") + PART_NAME_LEN + 1 */ + char env_desc_name[23 + PART_NAME_LEN + 1]; + char *raw_part_desc; + const char *argv[2]; + const char **parg = argv; + + /* check for raw partition descriptor */ + strcpy(env_desc_name, "fastboot_raw_partition_"); + strlcat(env_desc_name, name, sizeof(env_desc_name)); + raw_part_desc = strdup(env_get(env_desc_name)); + if (!raw_part_desc) + return -ENODEV; + + /* parse partition descriptor: <start> <size> */ + for (; parg < argv + sizeof(argv) / sizeof(*argv); ++parg) { + *parg = strsep(&raw_part_desc, " "); + if (!*parg) { + pr_err("Invalid number of arguments.\n"); + return -ENODEV; + } + } + + part_info->start = simple_strtoul(argv[0], NULL, 0); + part_info->size = simple_strtoul(argv[1], NULL, 0); + strlcpy((char *)part_info->name, name, PART_NAME_LEN); + + return 0; +} + +static int fastboot_spi_flash_probe(void) +{ + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + struct udevice *new, *bus_dev; + int ret; + + /* Remove the old device, otherwise probe will just be a nop */ + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); + if (!ret) + device_remove(new, DM_REMOVE_NORMAL); + + spi_flash_probe_bus_cs(bus, cs, &new); + flash = dev_get_uclass_priv(new); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + + return 0; +} + +static int fastboot_spi_flash_unlock(struct spi_flash *flash, + struct disk_partition *part_info) +{ + int ret = spi_flash_protect(flash, part_info->start, part_info->size, + false); + + if (ret && ret != -EOPNOTSUPP) { + printf("Failed to unlock SPI flash (%d)\n", ret); + return ret; + } + + return 0; +} + +static lbaint_t fb_spi_flash_sparse_write(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, + const void *buffer) +{ + size_t len = blkcnt * info->blksz; + u32 offset = blk * info->blksz; + int ret; + + ret = spi_flash_erase(flash, offset, ROUND(len, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase sparse chunk (%d)\n", ret); + return ret; + } + + ret = spi_flash_write(flash, offset, len, buffer); + if (ret < 0) { + printf("Failed to write sparse chunk (%d)\n", ret); + return ret; + } + + return blkcnt; +} + +static lbaint_t fb_spi_flash_sparse_reserve(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt) +{ + return blkcnt; +} + +/** + * fastboot_spi_flash_get_part_info() - Lookup SPI partition by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + * Return: 0 if OK, -ENOENT if no partition name was given, -ENODEV on invalid + * raw partition descriptor + */ +int fastboot_spi_flash_get_part_info(const char *part_name, + struct disk_partition *part_info, + char *response) +{ + int ret; + + if (!part_name || !strcmp(part_name, "")) { + fastboot_fail("partition not given", response); + return -ENOENT; + } + + /* TODO: Support partitions on the device */ + ret = raw_part_get_info_by_name(part_name, part_info); + if (ret < 0) + fastboot_fail("invalid partition or device", response); + + return ret; +} + +/** + * fastboot_spi_flash_write() - Write image to SPI for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_write_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + if (is_sparse_image(download_buffer)) { + struct sparse_storage sparse; + + sparse.blksz = flash->sector_size; + sparse.start = part_info.start / sparse.blksz; + sparse.size = part_info.size / sparse.blksz; + sparse.write = fb_spi_flash_sparse_write; + sparse.reserve = fb_spi_flash_sparse_reserve; + sparse.mssg = fastboot_fail; + + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + ret = write_sparse_image(&sparse, cmd, download_buffer, + response); + } else { + printf("Flashing raw image at offset " LBAFU "\n", + part_info.start); + + ret = spi_flash_erase(flash, part_info.start, + ROUND(download_bytes, flash->erase_size)); + if (ret < 0) { + printf("Failed to erase raw image (%d)\n", ret); + return; + } + ret = spi_flash_write(flash, part_info.start, download_bytes, + download_buffer); + if (ret < 0) { + printf("Failed to write raw image (%d)\n", ret); + return; + } + printf("........ wrote %u bytes\n", download_bytes); + } + + if (ret) + fastboot_fail("error writing the image", response); + else + fastboot_okay(NULL, response); +} + +/** + * fastboot_spi_flash_erase() - Erase SPI for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_erase(const char *cmd, char *response) +{ + struct disk_partition part_info; + int ret; + + if (fastboot_spi_flash_get_part_info(cmd, &part_info, response)) + return; + + if (fastboot_spi_flash_probe()) + return; + + if (board_fastboot_spi_flash_erase_setup()) + return; + + if (fastboot_spi_flash_unlock(flash, &part_info)) + return; + + ret = spi_flash_erase(flash, part_info.start, part_info.size); + if (ret < 0) { + pr_err("failed erasing from SPI flash"); + fastboot_fail("failed erasing from SPI flash", response); + return; + } + + fastboot_okay(NULL, response); +} diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fd227d46f5a..58e464106a3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -88,7 +88,7 @@ config DM_GPIO_LOOKUP_LABEL for the same functionality in board code. config SPL_DM_GPIO_LOOKUP_LABEL - bool "Enable searching for gpio labelnames" + bool "Enable searching for gpio labelnames in SPL" depends on SPL_DM_GPIO help This option enables searching for gpio names in @@ -719,5 +719,10 @@ config SPL_ADP5585_GPIO depends on SPL_DM_GPIO && SPL_I2C help Support ADP5585 GPIO expander in SPL. +config MPFS_GPIO + bool "Enable Polarfire SoC GPIO driver" + depends on DM_GPIO + help + Enable to support the GPIO driver on Polarfire SoC endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e8422b94f53..83e10c79b91 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -64,7 +64,7 @@ obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(PHASE_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o +obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o qcom_spmi_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o @@ -80,3 +80,4 @@ obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o obj-$(CONFIG_FTGPIO010) += ftgpio010.o obj-$(CONFIG_$(PHASE_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o +obj-$(CONFIG_MPFS_GPIO) += mpfs_gpio.o diff --git a/drivers/gpio/mpfs_gpio.c b/drivers/gpio/mpfs_gpio.c new file mode 100644 index 00000000000..9bbeada4ef5 --- /dev/null +++ b/drivers/gpio/mpfs_gpio.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. + * Eoin Dickson <eoin.dickson@microchip.com> + */ + +#include <dm.h> +#include <asm-generic/gpio.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/gpio.h> +#include <linux/bitops.h> + +#define MPFS_INP_REG 0x84 +#define COREGPIO_INP_REG 0x90 +#define MPFS_OUTP_REG 0x88 +#define COREGPIO_OUTP_REG 0xA0 +#define MPFS_GPIO_CTRL(i) (0x4 * (i)) +#define MPFS_MAX_NUM_GPIO 32 +#define MPFS_GPIO_EN_OUT_BUF BIT(2) +#define MPFS_GPIO_EN_IN BIT(1) +#define MPFS_GPIO_EN_OUT BIT(0) + +struct mpfs_gpio_reg_offsets { + u8 inp; + u8 outp; +}; + +struct mchp_gpio_plat { + void *base; + const struct mpfs_gpio_reg_offsets *regs; +}; + +static void mchp_update_gpio_reg(void *bptr, u32 offset, bool value) +{ + void __iomem *ptr = (void __iomem *)bptr; + + u32 old = readl(ptr); + + if (value) + writel(old | offset, ptr); + else + writel(old & ~offset, ptr); +} + +static int mchp_gpio_direction_input(struct udevice *dev, u32 offset) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + if (offset > uc_priv->gpio_count) + return -EINVAL; + + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_IN, true); + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT, false); + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT_BUF, false); + + return 0; +} + +static int mchp_gpio_direction_output(struct udevice *dev, u32 offset, int value) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + if (offset > uc_priv->gpio_count) + return -EINVAL; + + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_IN, false); + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT, true); + mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT_BUF, true); + + mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value); + + return 0; +} + +static bool mchp_gpio_get_value(struct udevice *dev, u32 offset) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int val, input; + + if (offset > uc_priv->gpio_count) + return -EINVAL; + + input = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN; + + if (input) + val = (readl(plat->base + plat->regs->inp) & BIT(offset)); + else + val = (readl(plat->base + plat->regs->outp) & BIT(offset)); + + return val >> offset; +} + +static int mchp_gpio_set_value(struct udevice *dev, u32 offset, int value) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + if (offset > uc_priv->gpio_count) + return -EINVAL; + + mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value); + + return 0; +} + +static int mchp_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 outdir, indir, val; + + if (offset > uc_priv->gpio_count) + return -EINVAL; + + /* Get direction of the pin */ + outdir = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_OUT; + indir = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN; + + if (outdir) + val = GPIOF_OUTPUT; + else if (indir) + val = GPIOF_INPUT; + else + val = GPIOF_UNUSED; + + return val; +} + +static int mchp_gpio_probe(struct udevice *dev) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + char name[18], *str; + + plat->regs = dev_get_driver_data(dev); + sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base); + str = strdup(name); + if (!str) + return -ENOMEM; + uc_priv->bank_name = str; + uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", MPFS_MAX_NUM_GPIO); + + return 0; +} + +static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = { + .inp = MPFS_INP_REG, + .outp = MPFS_OUTP_REG, +}; + +static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = { + .inp = COREGPIO_INP_REG, + .outp = COREGPIO_OUTP_REG, +}; + +static const struct udevice_id mchp_gpio_match[] = { + { + .compatible = "microchip,mpfs-gpio", + .data = &mpfs_reg_offsets, + }, { + .compatible = "microchip,coregpio-rtl-v3", + .data = &coregpio_reg_offsets, + }, + { /* end of list */ } +}; + +static const struct dm_gpio_ops mchp_gpio_ops = { + .direction_input = mchp_gpio_direction_input, + .direction_output = mchp_gpio_direction_output, + .get_value = mchp_gpio_get_value, + .set_value = mchp_gpio_set_value, + .get_function = mchp_gpio_get_function, +}; + +static int mchp_gpio_of_to_plat(struct udevice *dev) +{ + struct mchp_gpio_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(gpio_mpfs) = { + .name = "gpio_mpfs", + .id = UCLASS_GPIO, + .of_match = mchp_gpio_match, + .of_to_plat = of_match_ptr(mchp_gpio_of_to_plat), + .plat_auto = sizeof(struct mchp_gpio_plat), + .ops = &mchp_gpio_ops, + .probe = mchp_gpio_probe, +}; diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index cd9f3926ac4..4458c55cd3d 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -69,17 +69,6 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) -/** - * pmic_gpio_match_data - platform specific configuration - * - * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. - * This is a workaround for an unknown bug on some platforms where trying to write the - * GPIO configuration registers causes the board to hang. - */ -enum pmic_gpio_quirks { - QCOM_PMIC_QUIRK_READONLY = (1 << 0), -}; - struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -128,13 +117,8 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); - ulong quirks = dev_get_driver_data(dev); int ret = 0; - /* Some PMICs don't like their GPIOs being configured */ - if (quirks & QCOM_PMIC_QUIRK_READONLY) - return 0; - /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); @@ -278,7 +262,6 @@ static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); - ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -292,7 +275,7 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - quirks, dev_ofnode(dev), &child); + 0, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); @@ -365,7 +348,6 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pms405-gpio" }, { .compatible = "qcom,pm6125-gpio" }, { .compatible = "qcom,pm8150-gpio" }, - { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, { } }; diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c new file mode 100644 index 00000000000..22c8072534e --- /dev/null +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -0,0 +1,1035 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm generic pmic gpio driver + * + * Based on the original qcom_spmi_pmic_gpio driver from: + * Copyright (c) 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * Updated from the Linux pinctrl-spmi-gpio driver from: + * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> +#include <dm/device_compat.h> +#include <log.h> +#include <power/pmic.h> +#include <spmi/spmi.h> +#include <asm/io.h> +#include <stdlib.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#define PMIC_MAX_GPIOS 36 + +#define PMIC_GPIO_ADDRESS_RANGE 0x100 + +/* type and subtype registers base address offsets */ +#define PMIC_GPIO_REG_TYPE 0x4 +#define PMIC_GPIO_REG_SUBTYPE 0x5 + +/* GPIO peripheral type and subtype out_values */ +#define PMIC_GPIO_TYPE 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 +#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 +#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 +#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd +#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 +#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12 +#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13 + +#define PMIC_MPP_REG_RT_STS 0x10 +#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 + +/* control register base address offsets */ +#define PMIC_GPIO_REG_MODE_CTL 0x40 +#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 +#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 +#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 + #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 +#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 +#define PMIC_GPIO_REG_EN_CTL 0x46 + #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A + +/* PMIC_GPIO_REG_MODE_CTL */ +#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 +#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 +#define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 +#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 +#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 + +#define PMIC_GPIO_MODE_DIGITAL_INPUT 0 +#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 +#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 +#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 +#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 + +/* PMIC_GPIO_REG_DIG_VIN_CTL */ +#define PMIC_GPIO_REG_VIN_SHIFT 0 +#define PMIC_GPIO_REG_VIN_MASK 0x7 + +/* PMIC_GPIO_REG_DIG_PULL_CTL */ +#define PMIC_GPIO_REG_PULL_SHIFT 0 +#define PMIC_GPIO_REG_PULL_MASK 0x7 + +#define PMIC_GPIO_PULL_DOWN 4 +#define PMIC_GPIO_PULL_DISABLE 5 + +/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 +#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF + +/* PMIC_GPIO_REG_DIG_IN_CTL */ +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 +#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf + +/* PMIC_GPIO_REG_DIG_OUT_CTL */ +#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 +#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 +#define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 +#define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 + +/* + * Output type - indicates pin should be configured as push-pull, + * open drain or open source. + */ +#define PMIC_GPIO_OUT_BUF_CMOS 0 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 +#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 + +#define PMIC_GPIO_OUT_STRENGTH_LOW 1 +#define PMIC_GPIO_OUT_STRENGTH_HIGH 3 + +/* PMIC_GPIO_REG_EN_CTL */ +#define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 + +#define PMIC_GPIO_PHYSICAL_OFFSET 1 + +/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ +#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 + +/* The index of each function in spmi_pmic_gpio_functions[] array */ +enum spmi_pmic_gpio_func_index { + PMIC_GPIO_FUNC_INDEX_NORMAL, + PMIC_GPIO_FUNC_INDEX_PAIRED, + PMIC_GPIO_FUNC_INDEX_FUNC1, + PMIC_GPIO_FUNC_INDEX_FUNC2, + PMIC_GPIO_FUNC_INDEX_FUNC3, + PMIC_GPIO_FUNC_INDEX_FUNC4, + PMIC_GPIO_FUNC_INDEX_DTEST1, + PMIC_GPIO_FUNC_INDEX_DTEST2, + PMIC_GPIO_FUNC_INDEX_DTEST3, + PMIC_GPIO_FUNC_INDEX_DTEST4, +}; + +static const char *const spmi_pmic_gpio_functions[] = { + [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, + [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, + [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, + [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, + [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, + [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, + [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, + [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, + [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, + [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, +}; + +/** + * struct spmi_pmic_gpio_pad - keep current GPIO settings + * @base: Address base in SPMI device. + * @is_enabled: Set to false when GPIO should be put in high Z state. + * @out_value: Cached pin output value + * @have_buffer: Set to true if GPIO output could be configured in push-pull, + * open-drain or open-source mode. + * @output_enabled: Set to true if GPIO output logic is enabled. + * @input_enabled: Set to true if GPIO input buffer logic is enabled. + * @analog_pass: Set to true if GPIO is in analog-pass-through mode. + * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). + * @num_sources: Number of power-sources supported by this GPIO. + * @power_source: Current power-source used. + * @buffer_type: Push-pull, open-drain or open-source. + * @pullup: Constant current which flow trough GPIO output buffer. + * @strength: No, Low, Medium, High + * @function: See spmi_pmic_gpio_functions[] + * @atest: the ATEST selection for GPIO analog-pass-through mode + * @dtest_buffer: the DTEST buffer selection for digital input mode. + */ +struct spmi_pmic_gpio_pad { + u16 base; + bool is_enabled; + bool out_value; + bool have_buffer; + bool output_enabled; + bool input_enabled; + bool analog_pass; + bool lv_mv_type; + unsigned int num_sources; + unsigned int power_source; + unsigned int buffer_type; + unsigned int pullup; + unsigned int strength; + unsigned int function; + unsigned int atest; + unsigned int dtest_buffer; +}; + +struct qcom_spmi_pmic_gpio_data { + struct udevice *dev; + u32 pid; /* Peripheral ID on SPMI bus */ + struct udevice *pmic; /* Reference to pmic device for read/write */ + u32 pin_count; + struct spmi_pmic_gpio_pad *pads; +}; + +static int qcom_spmi_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector, + unsigned int param, unsigned int arg); + +static int spmi_pmic_gpio_read(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + unsigned int addr) +{ + return pmic_reg_read(plat->pmic, pad->base + addr); +} + +static int spmi_pmic_gpio_write(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + unsigned int addr, unsigned int val) +{ + return pmic_reg_write(plat->pmic, pad->base + addr, val); +} + +static void spmi_pmic_gpio_get_state(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad, + char *buf, int size) +{ + int ret, val, function, cnt; + + static const char *const biases[] = { + "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", + "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" + }; + static const char *const buffer_types[] = { + "push-pull", "open-drain", "open-source" + }; + static const char *const strengths[] = { + "no", "low", "medium", "high" + }; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_EN_CTL); + + if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { + cnt = snprintf(buf, size, "disabled"); + } else { + if (pad->input_enabled) { + ret = spmi_pmic_gpio_read(plat, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return; + + ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; + pad->out_value = ret; + } + /* + * For the non-LV/MV subtypes only 2 special functions are + * available, offsetting the dtest function values by 2. + */ + function = pad->function; + if (!pad->lv_mv_type && + pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) + function += PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3; + + if (pad->analog_pass) + cnt = snprintf(buf, size, "analog-pass"); + else + cnt = snprintf(buf, size, "%-4s", + pad->output_enabled ? "out" : "in"); + buf += cnt; + size -= cnt; + + snprintf(buf, size, " %-4s %-7s vin-%d %-27s %-10s %-7s atest-%d dtest-%d", + pad->out_value ? "high" : "low", + spmi_pmic_gpio_functions[function], + pad->power_source, + biases[pad->pullup], + buffer_types[pad->buffer_type], + strengths[pad->strength], + pad->atest, + pad->dtest_buffer); + } +} + +static int qcom_spmi_pmic_gpio_set(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad) +{ + unsigned int val; + int ret; + + val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); + if (ret < 0) + return ret; + + val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); + if (ret < 0) + return ret; + + val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; + val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); + if (ret < 0) + return ret; + + if (pad->dtest_buffer == 0) { + val = 0; + } else { + if (pad->lv_mv_type) { + val = pad->dtest_buffer - 1; + val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; + } else { + val = BIT(pad->dtest_buffer - 1); + } + } + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); + if (ret < 0) + return ret; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, + val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, + val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); + if (ret) + return ret; + + return 0; +} + +static int spmi_pmic_gpio_populate(struct qcom_spmi_pmic_gpio_data *plat, + struct spmi_pmic_gpio_pad *pad) +{ + int type, subtype, val, dir; + + type = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_TYPE); + if (type < 0) + return type; + + if (type != PMIC_GPIO_TYPE) { + dev_err(plat->dev, "incorrect block type 0x%x at 0x%x\n", + type, pad->base); + return -ENODEV; + } + + subtype = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_SUBTYPE); + if (subtype < 0) + return subtype; + + switch (subtype) { + case PMIC_GPIO_SUBTYPE_GPIO_4CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_4CH: + pad->num_sources = 4; + break; + case PMIC_GPIO_SUBTYPE_GPIO_8CH: + pad->have_buffer = true; + fallthrough; + case PMIC_GPIO_SUBTYPE_GPIOC_8CH: + pad->num_sources = 8; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV: + pad->num_sources = 1; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3: + pad->num_sources = 3; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + default: + dev_err(plat->dev, "unknown GPIO type 0x%x\n", subtype); + return -ENODEV; + } + + if (pad->lv_mv_type) { + val = spmi_pmic_gpio_read(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); + if (val < 0) + return val; + + pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); + pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; + } else { + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; + dir &= PMIC_GPIO_REG_MODE_DIR_MASK; + pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; + } + + switch (dir) { + case PMIC_GPIO_MODE_DIGITAL_INPUT: + pad->input_enabled = true; + pad->output_enabled = false; + break; + case PMIC_GPIO_MODE_DIGITAL_OUTPUT: + pad->input_enabled = false; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: + pad->input_enabled = true; + pad->output_enabled = true; + break; + case PMIC_GPIO_MODE_ANALOG_PASS_THRU: + if (!pad->lv_mv_type) + return -ENODEV; + pad->analog_pass = true; + break; + default: + dev_err(plat->dev, "unknown GPIO direction\n"); + return -ENODEV; + } + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_VIN_CTL); + if (val < 0) + return val; + + pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; + pad->power_source &= PMIC_GPIO_REG_VIN_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_PULL_CTL); + if (val < 0) + return val; + + pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; + pad->pullup &= PMIC_GPIO_REG_PULL_MASK; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_IN_CTL); + if (val < 0) + return val; + + if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) + pad->dtest_buffer = + (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; + else if (!pad->lv_mv_type) + pad->dtest_buffer = ffs(val); + else + pad->dtest_buffer = 0; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_DIG_OUT_CTL); + if (val < 0) + return val; + + pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; + pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; + + pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; + pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; + + if (pad->lv_mv_type) { + val = spmi_pmic_gpio_read(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); + if (val < 0) + return val; + + pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; + } + + /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ + pad->is_enabled = true; + return 0; +} + +static int qcom_spmi_pmic_gpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + pad->input_enabled = flags & GPIOD_IS_IN; + pad->output_enabled = flags & GPIOD_IS_OUT; + + if (pad->output_enabled) { + pad->out_value = flags & GPIOD_IS_OUT_ACTIVE; + + if ((flags & GPIOD_OPEN_DRAIN) && pad->have_buffer) + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; + else if ((flags & GPIOD_OPEN_SOURCE) && pad->have_buffer) + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; + else + pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; + } + + if (flags & GPIOD_PULL_UP) + pad->pullup = PMIC_GPIO_PULL_UP_30; + else if (flags & GPIOD_PULL_DOWN) + pad->pullup = PMIC_GPIO_PULL_DOWN; + + return qcom_spmi_pmic_gpio_set(plat, pad); +} + +static int qcom_spmi_pmic_gpio_get_flags(struct udevice *dev, unsigned int offset, + ulong *flagsp) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + ulong flags = 0; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + if (pad->input_enabled) + flags |= GPIOD_IS_IN; + + if (pad->output_enabled) { + flags |= GPIOD_IS_OUT; + + if (pad->out_value) + flags |= GPIOD_IS_OUT_ACTIVE; + + switch (pad->buffer_type) { + case PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS: + flags |= GPIOD_OPEN_DRAIN; + break; + case PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS: + flags |= GPIOD_OPEN_SOURCE; + break; + } + } + + if (pad->pullup == PMIC_GPIO_PULL_DOWN) + flags |= GPIOD_PULL_DOWN; + else if (pad->pullup != PMIC_GPIO_PULL_DISABLE) + flags |= GPIOD_PULL_UP; + + if (pad->analog_pass) + flags |= GPIOD_IS_AF; + + *flagsp = flags; + + return 0; +} + +static int qcom_spmi_pmic_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + int ret; + + if (offset >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[offset]; + + if (!pad->is_enabled) + return -EINVAL; + + if (pad->input_enabled) { + ret = spmi_pmic_gpio_read(plat, pad, PMIC_MPP_REG_RT_STS); + if (ret < 0) + return ret; + + pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; + } + + return !!pad->out_value; +} + +static int qcom_spmi_pmic_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + int val; + + if (offset >= plat->pin_count) + return GPIOF_UNKNOWN; + + pad = &plat->pads[offset]; + + val = spmi_pmic_gpio_read(plat, pad, PMIC_GPIO_REG_EN_CTL); + if (!(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) + return GPIOF_UNKNOWN; + else if (pad->analog_pass) + return GPIOF_FUNC; + else if (pad->output_enabled) + return GPIOF_OUTPUT; + + return GPIOF_INPUT; +} + +static int qcom_spmi_pmic_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + if (args->args_count < 1) + return -EINVAL; + + /* GPIOs in DT are 1-based */ + desc->offset = args->args[0] - 1; + if (desc->offset >= uc_priv->gpio_count) + return -EINVAL; + + if (args->args_count < 2) + return 0; + + desc->flags = gpio_flags_xlate(args->args[1]); + + return 0; +} + +static const struct dm_gpio_ops qcom_spmi_pmic_gpio_ops = { + .set_flags = qcom_spmi_pmic_gpio_set_flags, + .get_flags = qcom_spmi_pmic_gpio_get_flags, + .get_value = qcom_spmi_pmic_gpio_get_value, + .get_function = qcom_spmi_pmic_gpio_get_function, + .xlate = qcom_spmi_pmic_gpio_xlate, +}; + +static int qcom_spmi_pmic_gpio_bind(struct udevice *dev) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct udevice *child; + struct driver *drv; + int ret; + + drv = lists_driver_lookup_name("qcom_spmi_pmic_pinctrl"); + if (!drv) { + log_warning("Cannot find driver '%s'\n", "qcom_spmi_pmic_pinctrl"); + return -ENOENT; + } + + /* Bind the GPIO driver as a child of the PMIC. */ + ret = device_bind_with_driver_data(dev, drv, + dev->name, + 0, dev_ofnode(dev), &child); + if (ret) + return log_msg_ret("bind", ret); + + dev_set_plat(child, plat); + + return 0; +} + +static int qcom_spmi_pmic_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct ofnode_phandle_args args; + int i, ret; + u64 pid; + + plat->dev = dev; + plat->pmic = dev->parent; + + pid = dev_read_addr(dev); + if (pid == FDT_ADDR_T_NONE) + return log_msg_ret("bad address", -EINVAL); + + plat->pid = pid; + + /* + * Parse basic GPIO count specified via the gpio-ranges property + * as specified in upstream devicetrees + */ + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", + NULL, 3, 0, &args); + if (ret) + return log_msg_ret("gpio-ranges", ret); + + plat->pin_count = min_t(u32, args.args[2], PMIC_MAX_GPIOS); + + uc_priv->gpio_count = plat->pin_count; + + uc_priv->bank_name = strchr(dev_read_string(dev, "compatible"), ','); + if (uc_priv->bank_name) + uc_priv->bank_name += 1; /* skip the , */ + else + uc_priv->bank_name = dev->name; + + plat->pads = calloc(plat->pin_count, sizeof(struct spmi_pmic_gpio_pad)); + if (!plat->pads) + return -ENOMEM; + + for (i = 0; i < plat->pin_count; ++i) { + struct spmi_pmic_gpio_pad *pad = &plat->pads[i]; + + pad->base = plat->pid + i * PMIC_GPIO_ADDRESS_RANGE; + + ret = spmi_pmic_gpio_populate(plat, pad); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = { + { .compatible = "qcom,pm8550-gpio" }, + { .compatible = "qcom,pm8550b-gpio" }, + { .compatible = "qcom,pm8550ve-gpio" }, + { .compatible = "qcom,pm8550vs-gpio" }, + { .compatible = "qcom,pmk8550-gpio" }, + { .compatible = "qcom,pmr735d-gpio" }, + { } +}; + +U_BOOT_DRIVER(qcom_spmi_pmic_gpio) = { + .name = "qcom_spmi_pmic_gpio", + .id = UCLASS_GPIO, + .of_match = qcom_spmi_pmic_gpio_ids, + .bind = qcom_spmi_pmic_gpio_bind, + .probe = qcom_spmi_pmic_gpio_probe, + .ops = &qcom_spmi_pmic_gpio_ops, + .plat_auto = sizeof(struct qcom_spmi_pmic_gpio_data), + .flags = DM_FLAG_ALLOC_PDATA, +}; + +/* Qualcomm specific pin configurations */ +#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) +#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) +#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) +#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) +#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) + +static const struct pinconf_param qcom_spmi_pmic_pinctrl_conf_params[] = { + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, PMIC_GPIO_PULL_UP_30 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "output-high", PIN_CONFIG_OUTPUT, 1 }, + { "output-low", PIN_CONFIG_OUTPUT, 0 }, + { "qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, + { "qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, + { "qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, + { "qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, + { "qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, +}; + +static int qcom_spmi_pmic_pinctrl_get_pins_count(struct udevice *dev) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + + return plat->pin_count; +} + +static const char *qcom_spmi_pmic_pinctrl_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + static char name[8]; + + /* DT indexes from 1 */ + snprintf(name, sizeof(name), "gpio%u", selector + 1); + + return name; +} + +static int qcom_spmi_pmic_pinctrl_get_pin_muxing(struct udevice *dev, + unsigned int selector, + char *buf, int size) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + + spmi_pmic_gpio_get_state(plat, pad, buf, size); + + return 0; +} + +static int qcom_spmi_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector, + unsigned int param, unsigned int arg) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + pad->is_enabled = true; + + switch (param) { + case PIN_CONFIG_DRIVE_PUSH_PULL: + pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; + break; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + if (!pad->have_buffer) + return -EINVAL; + pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; + break; + case PIN_CONFIG_BIAS_DISABLE: + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_PULL_UP: + pad->pullup = PMIC_GPIO_PULL_UP_30; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg) + pad->pullup = PMIC_GPIO_PULL_DOWN; + else + pad->pullup = PMIC_GPIO_PULL_DISABLE; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + pad->is_enabled = false; + break; + case PIN_CONFIG_POWER_SOURCE: + if (arg >= pad->num_sources) + return -EINVAL; + pad->power_source = arg; + break; + case PIN_CONFIG_INPUT_ENABLE: + pad->input_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + pad->output_enabled = arg ? true : false; + break; + case PIN_CONFIG_OUTPUT: + pad->output_enabled = true; + pad->out_value = arg; + break; + case PMIC_GPIO_CONF_PULL_UP: + if (arg > PMIC_GPIO_PULL_UP_1P5_30) + return -EINVAL; + pad->pullup = arg; + break; + case PMIC_GPIO_CONF_STRENGTH: + if (arg > PMIC_GPIO_STRENGTH_LOW) + return -EINVAL; + switch (arg) { + case PMIC_GPIO_STRENGTH_HIGH: + pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH; + break; + case PMIC_GPIO_STRENGTH_LOW: + pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW; + break; + default: + pad->strength = arg; + break; + } + break; + case PMIC_GPIO_CONF_ATEST: + if (!pad->lv_mv_type || arg > 4) + return -EINVAL; + pad->atest = arg; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + if (!pad->lv_mv_type) + return -EINVAL; + pad->analog_pass = true; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + if (arg > 4) + return -EINVAL; + pad->dtest_buffer = arg; + break; + default: + return -EINVAL; + } + + return qcom_spmi_pmic_gpio_set(plat, pad); +} + +static const char *qcom_spmi_pmic_pinctrl_get_function_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= ARRAY_SIZE(spmi_pmic_gpio_functions)) + return NULL; + + return spmi_pmic_gpio_functions[selector]; +} + +static int qcom_spmi_pmic_pinctrl_get_functions_count(struct udevice *dev) +{ + return ARRAY_SIZE(spmi_pmic_gpio_functions); +} + +static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned int selector, + unsigned int function) +{ + struct qcom_spmi_pmic_gpio_data *plat = dev_get_plat(dev); + struct spmi_pmic_gpio_pad *pad; + unsigned int val; + int ret; + + if (selector >= plat->pin_count) + return -EINVAL; + + pad = &plat->pads[selector]; + + /* + * Non-LV/MV subtypes only support 2 special functions, + * offsetting the dtestx function values by 2 + */ + if (!pad->lv_mv_type) { + if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || + function == PMIC_GPIO_FUNC_INDEX_FUNC4) { + pr_err("LV/MV subtype doesn't have func3/func4\n"); + return -EINVAL; + } + if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) + function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3); + } + + pad->function = function; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; + + if (pad->lv_mv_type) { + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + + val = pad->atest - 1; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, + val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = spmi_pmic_gpio_write(plat, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, + val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); +} + +struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { + .get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count, + .get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinconf_num_params = ARRAY_SIZE(qcom_spmi_pmic_pinctrl_conf_params), + .pinconf_params = qcom_spmi_pmic_pinctrl_conf_params, + .pinconf_set = qcom_spmi_pmic_pinctrl_pinconf_set, + .get_function_name = qcom_spmi_pmic_pinctrl_get_function_name, + .get_functions_count = qcom_spmi_pmic_pinctrl_get_functions_count, + .pinmux_set = qcom_spmi_pmic_pinctrl_pinmux_set_mux, + .get_pin_muxing = qcom_spmi_pmic_pinctrl_get_pin_muxing, +}; + +U_BOOT_DRIVER(qcom_spmi_pmic_pinctrl) = { + .name = "qcom_spmi_pmic_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &qcom_spmi_pmic_pinctrl_ops, +}; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 146bc621c7e..108b24b3dd2 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -181,6 +181,7 @@ config SYS_I2C_IPROC config SYS_I2C_FSL bool "Freescale I2C bus driver" + depends on M68K || PPC help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -240,7 +241,7 @@ config SYS_I2C_DW config SYS_I2C_DW_PCI bool "Designware PCI I2C Controller" - depends on SYS_I2C_DW && PCI && ACPIGEN + depends on SYS_I2C_DW && PCI && ACPIGEN && X86 default y help Say yes here to select the Designware PCI I2C Host Controller. @@ -277,6 +278,7 @@ config SYS_I2C_INTEL config SYS_I2C_IMX_LPI2C bool "NXP i.MX LPI2C driver" + depends on MACH_IMX help Add support for the NXP i.MX LPI2C driver. @@ -314,6 +316,7 @@ config SYS_I2C_MICROCHIP config SYS_I2C_MXC bool "NXP MXC I2C driver" + depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || MACH_IMX help Add support for the NXP I2C driver. This supports up to four bus channels and operating on standard mode up to 100 kbits/s and fast @@ -485,7 +488,7 @@ endif config SYS_I2C_NEXELL bool "Nexell I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_NEXELL help Add support for the Nexell I2C driver. This is used with various Nexell parts such as S5Pxx18 series SoCs. All chips @@ -494,6 +497,7 @@ config SYS_I2C_NEXELL config SYS_I2C_NPCM bool "Nuvoton NPCM I2C driver" + depends on ARCH_NPCM help Support for Nuvoton I2C controller driver. @@ -533,7 +537,7 @@ config SYS_I2C_RCAR_IIC config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" - depends on DM_I2C + depends on DM_I2C && ARCH_ROCKCHIP help Add support for the Rockchip I2C driver. This is used with various Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips @@ -615,6 +619,7 @@ endif config SYS_I2C_SOFT bool "Legacy software I2C interface" + depends on !COMPILE_TEST help Enable the legacy software defined I2C interface @@ -750,6 +755,7 @@ config SYS_I2C_MV config SYS_I2C_MVTWSI bool "Marvell I2C driver" + depends on ARCH_KIRKWOOD || ARCH_MVEBU || ARCH_SUNXI help Support for Marvell I2C controllers as used on the orion5x and kirkwood SoC families. diff --git a/drivers/i2c/iproc_i2c.c b/drivers/i2c/iproc_i2c.c index 6570f64fe77..8f94dfe117e 100644 --- a/drivers/i2c/iproc_i2c.c +++ b/drivers/i2c/iproc_i2c.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <config.h> #include <dm.h> +#include <linux/delay.h> #include <linux/printk.h> #include "errno.h" #include <i2c.h> diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index cd5579aa55a..65319bb6fd8 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -25,6 +25,13 @@ config I2C_ARB_GPIO_CHALLENGE response mechanism where masters have to claim the bus by asserting a GPIO. +config I2C_MUX_PCA9541 + tristate "NXP PCA9541 I2C Master Selector" + depends on I2C_MUX + help + If you say yes here you get support for the NXP PCA9541 + I2C Master Selector. + config I2C_MUX_PCA954x tristate "TI PCA954x I2C Mux/switches" depends on I2C_MUX diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index b690821199f..844d4520e43 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -3,5 +3,6 @@ # Copyright (c) 2015 Google, Inc obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o +obj-$(CONFIG_I2C_MUX_PCA9541) += pca9541.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o diff --git a/drivers/i2c/muxes/pca9541.c b/drivers/i2c/muxes/pca9541.c new file mode 100644 index 00000000000..021088acaee --- /dev/null +++ b/drivers/i2c/muxes/pca9541.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it> + * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it> + * Copyright (c) 2010 Ericsson AB. + * Copyright (c) 2025 Advanced Micro Devices, Inc. + */ + +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <log.h> +#include <malloc.h> +#include <linux/delay.h> + +/* + * The PCA9541 is a bus master selector. It supports two I2C masters connected + * to a single slave bus. + * + * Before each bus transaction, a master has to acquire bus ownership. After the + * transaction is complete, bus ownership has to be released. This fits well + * into the I2C multiplexer framework, which provides select and release + * functions for this purpose. For this reason, this driver is modeled as + * single-channel I2C bus multiplexer. + * + * This driver assumes that the two bus masters are controlled by two different + * hosts. If a single host controls both masters, platform code has to ensure + * that only one of the masters is instantiated at any given time. + */ + +#define PCA9541_CONTROL 0x01 +#define PCA9541_ISTAT 0x02 + +#define PCA9541_CTL_MYBUS BIT(0) +#define PCA9541_CTL_NMYBUS BIT(1) +#define PCA9541_CTL_BUSON BIT(2) +#define PCA9541_CTL_NBUSON BIT(3) +#define PCA9541_CTL_BUSINIT BIT(4) +#define PCA9541_CTL_TESTON BIT(6) +#define PCA9541_CTL_NTESTON BIT(7) + +#define PCA9541_ISTAT_INTIN BIT(0) +#define PCA9541_ISTAT_BUSINIT BIT(1) +#define PCA9541_ISTAT_BUSOK BIT(2) +#define PCA9541_ISTAT_BUSLOST BIT(3) +#define PCA9541_ISTAT_MYTEST BIT(6) +#define PCA9541_ISTAT_NMYTEST BIT(7) + +#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON) +#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS) + +/* arbitration timeouts, in jiffies */ +#define ARB_TIMEOUT_US 125000 /* 125 ms until forcing bus ownership */ +#define ARB2_TIMEOUT_US 250000 /* 250 ms until acquisition failure */ + +/* arbitration retry delays, in us */ +#define SELECT_DELAY_SHORT 50 +#define SELECT_DELAY_LONG 1000 + +struct pca9541_plat { + u32 addr; +}; + +struct pca9541_priv { + u32 addr; + unsigned long select_timeout; + long arb_timeout; +}; + +static inline int mybus(int x) +{ + return !(x & MYBUS) || ((x & MYBUS) == MYBUS); +} + +static inline int busoff(int x) +{ + return !(x & BUSON) || ((x & BUSON) == BUSON); +} + +static int pca9541_reg_write(struct udevice *mux, struct pca9541_priv *client, + u8 command, u8 val) +{ + return dm_i2c_write(mux, command, &val, 1); +} + +static int pca9541_reg_read(struct udevice *mux, struct pca9541_priv *client, + u8 command) +{ + int ret; + uchar byte; + + ret = dm_i2c_read(mux, command, &byte, 1); + + return ret ?: byte; +} + +/* + * Arbitration management functions + */ + +/* Release bus. Also reset NTESTON and BUSINIT if it was set. */ +static void pca9541_release_bus(struct udevice *mux, struct pca9541_priv *client) +{ + int reg; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg >= 0 && !busoff(reg) && mybus(reg)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + (reg & PCA9541_CTL_NBUSON) >> 1); +} + +/* + * Arbitration is defined as a two-step process. A bus master can only activate + * the slave bus if it owns it; otherwise it has to request ownership first. + * This multi-step process ensures that access contention is resolved + * gracefully. + * + * Bus Ownership Other master Action + * state requested access + * ---------------------------------------------------- + * off - yes wait for arbitration timeout or + * for other master to drop request + * off no no take ownership + * off yes no turn on bus + * on yes - done + * on no - wait for arbitration timeout or + * for other master to release bus + * + * The main contention point occurs if the slave bus is off and both masters + * request ownership at the same time. In this case, one master will turn on + * the slave bus, believing that it owns it. The other master will request + * bus ownership. Result is that the bus is turned on, and master which did + * _not_ own the slave bus before ends up owning it. + */ + +/* Control commands per PCA9541 datasheet */ +static const u8 pca9541_control[16] = { + 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1 +}; + +/* + * Channel arbitration + * + * Return values: + * <0: error + * 0 : bus not acquired + * 1 : bus acquired + */ +static int pca9541_arbitrate(struct udevice *mux, struct pca9541_priv *client) +{ + int reg, ret = 0; + + reg = pca9541_reg_read(mux, client, PCA9541_CONTROL); + if (reg < 0) + return reg; + + if (busoff(reg)) { + int istat; + + /* + * Bus is off. Request ownership or turn it on unless + * other master requested ownership. + */ + istat = pca9541_reg_read(mux, client, PCA9541_ISTAT); + if (!(istat & PCA9541_ISTAT_NMYTEST) || + client->arb_timeout <= 0) { + /* + * Other master did not request ownership, + * or arbitration timeout expired. Take the bus. + */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_NTESTON); + client->select_timeout = SELECT_DELAY_SHORT; + } else { + /* + * Other master requested ownership. + * Set extra long timeout to give it time to acquire it. + */ + client->select_timeout = SELECT_DELAY_LONG * 2; + } + } else if (mybus(reg)) { + /* + * Bus is on, and we own it. We are done with acquisition. + * Reset NTESTON and BUSINIT, then return success. + */ + if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg & ~(PCA9541_CTL_NTESTON + | PCA9541_CTL_BUSINIT)); + ret = 1; + } else { + /* + * Other master owns the bus. + * If arbitration timeout has expired, force ownership. + * Otherwise request it. + */ + client->select_timeout = SELECT_DELAY_LONG; + if (client->arb_timeout <= 0) { + /* Time is up, take the bus and reset it. */ + pca9541_reg_write(mux, client, PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_BUSINIT + | PCA9541_CTL_NTESTON); + } else { + /* Request bus ownership if needed */ + if (!(reg & PCA9541_CTL_NTESTON)) + pca9541_reg_write(mux, client, PCA9541_CONTROL, + reg | PCA9541_CTL_NTESTON); + } + } + + return ret; +} + +static int pca9541_select_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + int ret; + long timeout = ARB2_TIMEOUT_US; /* Give up after this time */ + + /* Force bus ownership after this time */ + priv->arb_timeout = ARB_TIMEOUT_US; + do { + ret = pca9541_arbitrate(mux, priv); + if (ret) + return ret < 0 ? ret : 0; + + udelay(priv->select_timeout); + timeout -= priv->select_timeout; + priv->arb_timeout -= priv->select_timeout; + } while (timeout > 0); + + debug("I2C Arbitration select timeout\n"); + + return -ETIMEDOUT; +} + +static int pca9541_release_chan(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct pca9541_priv *priv = dev_get_priv(mux); + + pca9541_release_bus(mux, priv); + + return 0; +} + +/* + * I2C init/probing/exit functions + */ +static int pca9541_of_to_plat(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_u32_default(dev, "reg", 0); + if (!plat->addr) { + debug("Reg property is not found\n"); + return -ENODEV; + } + + debug("Device %s at 0x%x\n", dev->name, plat->addr); + + return 0; +} + +static int pca9541_probe(struct udevice *dev) +{ + struct pca9541_plat *plat = dev_get_plat(dev); + struct pca9541_priv *priv = dev_get_priv(dev); + + priv->addr = plat->addr; + + return 0; +} + +static const struct i2c_mux_ops pca9541_ops = { + .select = pca9541_select_chan, + .deselect = pca9541_release_chan, +}; + +static const struct udevice_id pca9541_ids[] = { + { .compatible = "nxp,pca9541", }, + { } +}; + +U_BOOT_DRIVER(pca9541) = { + .name = "pca9541", + .id = UCLASS_I2C_MUX, + .of_match = pca9541_ids, + .probe = pca9541_probe, + .ops = &pca9541_ops, + .of_to_plat = pca9541_of_to_plat, + .plat_auto = sizeof(struct pca9541_plat), + .priv_auto = sizeof(struct pca9541_priv), +}; diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 9dd26972703..d13947a0d9c 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -22,6 +22,7 @@ enum pca_type { MAX7369, PCA9543, PCA9544, + PCA9545, PCA9546, PCA9547, PCA9548, @@ -79,6 +80,10 @@ static const struct chip_desc chips[] = { .muxtype = pca954x_ismux, .width = 4, }, + [PCA9545] = { + .muxtype = pca954x_isswi, + .width = 4, + }, [PCA9546] = { .muxtype = pca954x_isswi, .width = 4, @@ -141,6 +146,7 @@ static const struct udevice_id pca954x_ids[] = { { .compatible = "maxim,max7369", .data = MAX7369 }, { .compatible = "nxp,pca9543", .data = PCA9543 }, { .compatible = "nxp,pca9544", .data = PCA9544 }, + { .compatible = "nxp,pca9545", .data = PCA9545 }, { .compatible = "nxp,pca9546", .data = PCA9546 }, { .compatible = "nxp,pca9547", .data = PCA9547 }, { .compatible = "nxp,pca9548", .data = PCA9548 }, diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index c09f0ae795e..47ce0ea690f 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -98,6 +98,7 @@ config I8042_KEYB config TEGRA_KEYBOARD bool "NVIDIA Tegra internal matrix keyboard controller support" + depends on ARCH_TEGRA help A matrix keyboard connected directly to the internal keyboard controller on Tegra SoCs. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 8b8f6309ada..966783e4b62 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -290,39 +290,9 @@ config CROS_EC_SPI provides a faster and more robust interface than I2C but the bugs are less interesting. -config DS4510 - bool "Enable support for DS4510 CPU supervisor" - help - Enable support for the Maxim DS4510 CPU supervisor. It has an - integrated 64-byte EEPROM, four programmable non-volatile I/O pins - and a configurable timer for the supervisor function. The device is - connected over I2C. - config FSL_IIM bool "Enable FSL IC Identification Module (IIM) driver" - depends on ARCH_MX31 || ARCH_MX5 - -config FSL_SEC_MON - bool "Enable FSL SEC_MON Driver" - help - Freescale Security Monitor block is responsible for monitoring - system states. - Security Monitor can be transitioned on any security failures, - like software violations or hardware security violations. - -choice - prompt "Security monitor interaction endianess" - depends on FSL_SEC_MON - default SYS_FSL_SEC_MON_BE if PPC - default SYS_FSL_SEC_MON_LE - -config SYS_FSL_SEC_MON_LE - bool "Security monitor interactions are little endian" - -config SYS_FSL_SEC_MON_BE - bool "Security monitor interactions are big endian" - -endchoice + depends on ARCH_MX5 config IRQ bool "Interrupt controller" @@ -458,19 +428,6 @@ config SPL_PWRSEQ device. When the device is started up, its power sequence can be initiated. -config PCA9551_LED - bool "Enable PCA9551 LED driver" - help - Enable driver for PCA9551 LED controller. This controller - is connected via I2C. So I2C needs to be enabled. - -config PCA9551_I2C_ADDR - hex "I2C address of PCA9551 LED controller" - depends on PCA9551_LED - default 0x60 - help - The I2C address of the PCA9551 LED controller. - config STM32MP_FUSE bool "Enable STM32MP fuse wrapper providing the fuse API" depends on ARCH_STM32MP && MISC @@ -672,7 +629,7 @@ config GDSYS_SOC config IHS_FPGA bool "Enable IHS FPGA driver" - depends on MISC + depends on MISC && (GDSYS_LEGACY_DRIVERS || SYS_FPGA_FLAVOR_GAZERBEAM) help Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on gdsys devices, which supply the majority of the functionality offered diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 248068d5b43..09dfd8072db 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -32,7 +32,6 @@ endif obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o -obj-$(CONFIG_DS4510) += ds4510.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o @@ -59,7 +58,6 @@ obj-$(CONFIG_NPCM_OTP) += npcm_otp.o obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o -obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_$(PHASE_)PWRSEQ) += pwrseq-uclass.o ifdef CONFIG_QFW obj-y += qfw.o diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 3ac690a3733..432b1fbb0c4 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -540,7 +540,7 @@ static int process_cmd(struct ec_state *ec, const struct ec_params_vstore_write *req = req_data; struct vstore_slot *slot; - if (req->slot >= EC_VSTORE_SLOT_MAX) + if (req->slot >= VSTORE_SLOT_COUNT) return -EINVAL; slot = &ec->slot[req->slot]; slot->locked = true; @@ -553,7 +553,7 @@ static int process_cmd(struct ec_state *ec, struct ec_response_vstore_read *resp = resp_data; struct vstore_slot *slot; - if (req->slot >= EC_VSTORE_SLOT_MAX) + if (req->slot >= VSTORE_SLOT_COUNT) return -EINVAL; slot = &ec->slot[req->slot]; memcpy(resp->data, slot->data, EC_VSTORE_SLOT_SIZE); diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c deleted file mode 100644 index 302015e2793..00000000000 --- a/drivers/misc/ds4510.c +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - */ - -/* - * Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM, - * and 4 programmable non-volatile GPIO pins. - */ - -#include <i2c.h> -#include <command.h> -#include <linux/delay.h> -#include "ds4510.h" - -enum { - DS4510_CMD_INFO, - DS4510_CMD_DEVICE, - DS4510_CMD_NV, - DS4510_CMD_RSTDELAY, - DS4510_CMD_OUTPUT, - DS4510_CMD_INPUT, - DS4510_CMD_PULLUP, - DS4510_CMD_EEPROM, - DS4510_CMD_SEEPROM, - DS4510_CMD_SRAM, -}; - -/* - * Write to DS4510, taking page boundaries into account - */ -static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) -{ - int wrlen; - int i = 0; - - do { - wrlen = DS4510_EEPROM_PAGE_SIZE - - DS4510_EEPROM_PAGE_OFFSET(offset); - if (count < wrlen) - wrlen = count; - if (i2c_write(chip, offset, 1, &buf[i], wrlen)) - return -1; - - /* - * This delay isn't needed for SRAM writes but shouldn't delay - * things too much, so do it unconditionally for simplicity - */ - udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000); - count -= wrlen; - offset += wrlen; - i += wrlen; - } while (count > 0); - - return 0; -} - -/* - * General read from DS4510 - */ -static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) -{ - return i2c_read(chip, offset, 1, buf, count); -} - -/* - * Write SEE bit in config register. - * nv = 0 - Writes to SEEPROM registers behave like EEPROM - * nv = 1 - Writes to SEEPROM registers behave like SRAM - */ -static int ds4510_see_write(uint8_t chip, uint8_t nv) -{ - uint8_t data; - - if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) - return -1; - - if (nv) /* Treat SEEPROM bits as EEPROM */ - data &= ~DS4510_CFG_SEE; - else /* Treat SEEPROM bits as SRAM */ - data |= DS4510_CFG_SEE; - - return ds4510_mem_write(chip, DS4510_CFG, &data, 1); -} - -/* - * Write de-assertion of reset signal delay - */ -static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) -{ - uint8_t data; - - if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) - return -1; - - data &= ~DS4510_RSTDELAY_MASK; - data |= delay & DS4510_RSTDELAY_MASK; - - return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1); -} - -/* - * Write pullup characteristics of IO pins - */ -static int ds4510_pullup_write(uint8_t chip, uint8_t val) -{ - val &= DS4510_IO_MASK; - - return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1); -} - -/* - * Read pullup characteristics of IO pins - */ -static int ds4510_pullup_read(uint8_t chip) -{ - uint8_t val; - - if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1)) - return -1; - - return val & DS4510_IO_MASK; -} - -/* - * Write drive level of IO pins - */ -static int ds4510_gpio_write(uint8_t chip, uint8_t val) -{ - uint8_t data; - int i; - - for (i = 0; i < DS4510_NUM_IO; i++) { - if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) - return -1; - - if (val & (0x1 << i)) - data |= 0x1; - else - data &= ~0x1; - - if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1)) - return -1; - } - - return 0; -} - -/* - * Read drive level of IO pins - */ -static int ds4510_gpio_read(uint8_t chip) -{ - uint8_t data; - int val = 0; - int i; - - for (i = 0; i < DS4510_NUM_IO; i++) { - if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) - return -1; - - if (data & 1) - val |= (1 << i); - } - - return val; -} - -/* - * Read physical level of IO pins - */ -static int ds4510_gpio_read_val(uint8_t chip) -{ - uint8_t val; - - if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1)) - return -1; - - return val & DS4510_IO_MASK; -} - -/* - * Display DS4510 information - */ -static int ds4510_info(uint8_t chip) -{ - int i; - int tmp; - uint8_t data; - - printf("DS4510 @ 0x%x:\n\n", chip); - - if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) - return -1; - printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK); - - if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) - return -1; - printf("config = 0x%x\n", data); - printf(" /ready = %d\n", data & DS4510_CFG_READY ? 1 : 0); - printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0); - printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0); - printf(" /see = %d\n", data & DS4510_CFG_SEE ? 1 : 0); - printf(" swrst = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0); - - printf("gpio pins: 3210\n"); - printf("---------------\n"); - printf("pullup "); - - tmp = ds4510_pullup_read(chip); - if (tmp == -1) - return tmp; - for (i = DS4510_NUM_IO - 1; i >= 0; i--) - printf("%d", (tmp & (1 << i)) ? 1 : 0); - printf("\n"); - - printf("driven "); - tmp = ds4510_gpio_read(chip); - if (tmp == -1) - return -1; - for (i = DS4510_NUM_IO - 1; i >= 0; i--) - printf("%d", (tmp & (1 << i)) ? 1 : 0); - printf("\n"); - - printf("read "); - tmp = ds4510_gpio_read_val(chip); - if (tmp == -1) - return -1; - for (i = DS4510_NUM_IO - 1; i >= 0; i--) - printf("%d", (tmp & (1 << i)) ? 1 : 0); - printf("\n"); - - return 0; -} - -struct cmd_tbl cmd_ds4510[] = { - U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""), - U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""), - U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""), - U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""), - U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""), - U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""), - U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""), - U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""), - U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""), - U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""), -}; - -int do_ds4510(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - static uint8_t chip = 0x51; - struct cmd_tbl *c; - ulong ul_arg2 = 0; - ulong ul_arg3 = 0; - int tmp; - ulong addr; - ulong off; - ulong cnt; - int end; - int (*rw_func)(uint8_t, int, uint8_t *, int); - - c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510)); - - /* All commands but "device" require 'maxargs' arguments */ - if (!c || !((argc == (c->maxargs)) || - (((int)c->cmd == DS4510_CMD_DEVICE) && - (argc == (c->maxargs - 1))))) { - return cmd_usage(cmdtp); - } - - /* arg2 used as chip addr and pin number */ - if (argc > 2) - ul_arg2 = hextoul(argv[2], NULL); - - /* arg3 used as output/pullup value */ - if (argc > 3) - ul_arg3 = hextoul(argv[3], NULL); - - switch ((int)c->cmd) { - case DS4510_CMD_DEVICE: - if (argc == 3) - chip = ul_arg2; - printf("Current device address: 0x%x\n", chip); - return 0; - case DS4510_CMD_NV: - return ds4510_see_write(chip, ul_arg2); - case DS4510_CMD_OUTPUT: - tmp = ds4510_gpio_read(chip); - if (tmp == -1) - return -1; - if (ul_arg3) - tmp |= (1 << ul_arg2); - else - tmp &= ~(1 << ul_arg2); - return ds4510_gpio_write(chip, tmp); - case DS4510_CMD_INPUT: - tmp = ds4510_gpio_read_val(chip); - if (tmp == -1) - return -1; - return (tmp & (1 << ul_arg2)) != 0; - case DS4510_CMD_PULLUP: - tmp = ds4510_pullup_read(chip); - if (tmp == -1) - return -1; - if (ul_arg3) - tmp |= (1 << ul_arg2); - else - tmp &= ~(1 << ul_arg2); - return ds4510_pullup_write(chip, tmp); - case DS4510_CMD_INFO: - return ds4510_info(chip); - case DS4510_CMD_RSTDELAY: - return ds4510_rstdelay_write(chip, ul_arg2); - case DS4510_CMD_EEPROM: - end = DS4510_EEPROM + DS4510_EEPROM_SIZE; - off = DS4510_EEPROM; - break; - case DS4510_CMD_SEEPROM: - end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE; - off = DS4510_SEEPROM; - break; - case DS4510_CMD_SRAM: - end = DS4510_SRAM + DS4510_SRAM_SIZE; - off = DS4510_SRAM; - break; - default: - /* We should never get here... */ - return 1; - } - - /* Only eeprom, seeprom, and sram commands should make it here */ - if (strcmp(argv[2], "read") == 0) - rw_func = ds4510_mem_read; - else if (strcmp(argv[2], "write") == 0) - rw_func = ds4510_mem_write; - else - return cmd_usage(cmdtp); - - addr = hextoul(argv[3], NULL); - off += hextoul(argv[4], NULL); - cnt = hextoul(argv[5], NULL); - - if ((off + cnt) > end) { - printf("ERROR: invalid len\n"); - return -1; - } - - return rw_func(chip, off, (uint8_t *)addr, cnt); -} - -U_BOOT_CMD( - ds4510, 6, 1, do_ds4510, - "ds4510 eeprom/seeprom/sram/gpio access", - "device [dev]\n" - " - show or set current device address\n" - "ds4510 info\n" - " - display ds4510 info\n" - "ds4510 output pin 0|1\n" - " - set pin low or high-Z\n" - "ds4510 input pin\n" - " - read value of pin\n" - "ds4510 pullup pin 0|1\n" - " - disable/enable pullup on specified pin\n" - "ds4510 nv 0|1\n" - " - make gpio and seeprom writes volatile/non-volatile" - "\n" - "ds4510 rstdelay 0-3\n" - " - set reset output delay" - "\n" - "ds4510 eeprom read addr off cnt\n" - "ds4510 eeprom write addr off cnt\n" - " - read/write 'cnt' bytes at EEPROM offset 'off'\n" - "ds4510 seeprom read addr off cnt\n" - "ds4510 seeprom write addr off cnt\n" - " - read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n" - "ds4510 sram read addr off cnt\n" - "ds4510 sram write addr off cnt\n" - " - read/write 'cnt' bytes at SRAM offset 'off'" -); diff --git a/drivers/misc/ds4510.h b/drivers/misc/ds4510.h deleted file mode 100644 index 5c7a1a8c737..00000000000 --- a/drivers/misc/ds4510.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - */ - -#ifndef __DS4510_H_ -#define __DS4510_H_ - -/* General defines */ -#define DS4510_NUM_IO 0x04 -#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) -#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* EEPROM from 0x00 - 0x39 */ -#define DS4510_EEPROM 0x00 -#define DS4510_EEPROM_SIZE 0x40 -#define DS4510_EEPROM_PAGE_SIZE 0x08 -#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) - -/* SEEPROM from 0xf0 - 0xf7 */ -#define DS4510_SEEPROM 0xf0 -#define DS4510_SEEPROM_SIZE 0x08 - -/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ -#define DS4510_PULLUP 0xF0 -#define DS4510_PULLUP_DIS 0x00 -#define DS4510_PULLUP_EN 0x01 -#define DS4510_RSTDELAY 0xF1 -#define DS4510_RSTDELAY_MASK 0x03 -#define DS4510_RSTDELAY_125 0x00 -#define DS4510_RSTDELAY_250 0x01 -#define DS4510_RSTDELAY_500 0x02 -#define DS4510_RSTDELAY_1000 0x03 -#define DS4510_IO3 0xF4 -#define DS4510_IO2 0xF5 -#define DS4510_IO1 0xF6 -#define DS4510_IO0 0xF7 - -/* Status configuration registers from 0xf8 - 0xf9*/ -#define DS4510_IO_STATUS 0xF8 -#define DS4510_CFG 0xF9 -#define DS4510_CFG_READY 0x80 -#define DS4510_CFG_TRIP_POINT 0x40 -#define DS4510_CFG_RESET 0x20 -#define DS4510_CFG_SEE 0x10 -#define DS4510_CFG_SWRST 0x08 - -/* SRAM from 0xfa - 0xff */ -#define DS4510_SRAM 0xfa -#define DS4510_SRAM_SIZE 0x06 - -#endif /* __DS4510_H_ */ diff --git a/drivers/misc/pca9551_led.c b/drivers/misc/pca9551_led.c deleted file mode 100644 index 040d0d5cf48..00000000000 --- a/drivers/misc/pca9551_led.c +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Stefan Roese <sr@denx.de> - */ - -#include <errno.h> -#include <i2c.h> -#include <status_led.h> - -#ifndef CONFIG_PCA9551_I2C_ADDR -#error "CONFIG_PCA9551_I2C_ADDR not defined!" -#endif - -#define PCA9551_REG_INPUT 0x00 /* Input register (read only) */ -#define PCA9551_REG_PSC0 0x01 /* Frequency prescaler 0 */ -#define PCA9551_REG_PWM0 0x02 /* PWM0 */ -#define PCA9551_REG_PSC1 0x03 /* Frequency prescaler 1 */ -#define PCA9551_REG_PWM1 0x04 /* PWM1 */ -#define PCA9551_REG_LS0 0x05 /* LED0 to LED3 selector */ -#define PCA9551_REG_LS1 0x06 /* LED4 to LED7 selector */ - -#define PCA9551_CTRL_AI (1 << 4) /* Auto-increment flag */ - -#define PCA9551_LED_STATE_ON 0x00 -#define PCA9551_LED_STATE_OFF 0x01 -#define PCA9551_LED_STATE_BLINK0 0x02 -#define PCA9551_LED_STATE_BLINK1 0x03 - -struct pca9551_blink_rate { - u8 psc; /* Frequency preescaler, see PCA9551_7.pdf p. 6 */ - u8 pwm; /* Pulse width modulation, see PCA9551_7.pdf p. 6 */ -}; - -static int freq_last = -1; -static int mask_last = -1; -static int idx_last = -1; -static int mode_last; - -static int pca9551_led_get_state(int led, int *state) -{ - unsigned int reg; - u8 shift, buf; - int ret; - - if (led < 0 || led > 7) { - return -EINVAL; - } else if (led < 4) { - reg = PCA9551_REG_LS0; - shift = led << 1; - } else { - reg = PCA9551_REG_LS1; - shift = (led - 4) << 1; - } - - ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); - if (ret) - return ret; - - *state = (buf >> shift) & 0x03; - return 0; -} - -static int pca9551_led_set_state(int led, int state) -{ - unsigned int reg; - u8 shift, buf, mask; - int ret; - - if (led < 0 || led > 7) { - return -EINVAL; - } else if (led < 4) { - reg = PCA9551_REG_LS0; - shift = led << 1; - } else { - reg = PCA9551_REG_LS1; - shift = (led - 4) << 1; - } - mask = 0x03 << shift; - - ret = i2c_read(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); - if (ret) - return ret; - - buf = (buf & ~mask) | ((state & 0x03) << shift); - - ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, &buf, 1); - if (ret) - return ret; - - return 0; -} - -static int pca9551_led_set_blink_rate(int idx, struct pca9551_blink_rate rate) -{ - unsigned int reg; - int ret; - - switch (idx) { - case 0: - reg = PCA9551_REG_PSC0; - break; - case 1: - reg = PCA9551_REG_PSC1; - break; - default: - return -EINVAL; - } - reg |= PCA9551_CTRL_AI; - - ret = i2c_write(CONFIG_PCA9551_I2C_ADDR, reg, 1, (u8 *)&rate, 2); - if (ret) - return ret; - - return 0; -} - -/* - * Functions referenced by cmd_led.c or status_led.c - */ -void __led_init(led_id_t id, int state) -{ -} - -void __led_set(led_id_t mask, int state) -{ - if (state == CONFIG_LED_STATUS_OFF) - pca9551_led_set_state(mask, PCA9551_LED_STATE_OFF); - else - pca9551_led_set_state(mask, PCA9551_LED_STATE_ON); -} - -void __led_toggle(led_id_t mask) -{ - int state = 0; - - pca9551_led_get_state(mask, &state); - pca9551_led_set_state(mask, !state); -} - -void __led_blink(led_id_t mask, int freq) -{ - struct pca9551_blink_rate rate; - int mode; - int idx; - - if ((freq == freq_last) || (mask == mask_last)) { - idx = idx_last; - mode = mode_last; - } else { - /* Toggle blink index */ - if (idx_last == 0) { - idx = 1; - mode = PCA9551_LED_STATE_BLINK1; - } else { - idx = 0; - mode = PCA9551_LED_STATE_BLINK0; - } - - idx_last = idx; - mode_last = mode; - } - freq_last = freq; - mask_last = mask; - - rate.psc = ((freq * 38) / 1000) - 1; - rate.pwm = 128; /* 50% duty cycle */ - - pca9551_led_set_blink_rate(idx, rate); - pca9551_led_set_state(mask, mode); -} diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 1c9b6898bff..4c46df0ffb8 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -284,7 +284,7 @@ config MMC_DW_K3 config MMC_DW_ROCKCHIP bool "Rockchip SD/MMC controller support" - depends on OF_CONTROL + depends on OF_CONTROL && ARCH_ROCKCHIP depends on MMC_DW help This enables support for the Rockchip SD/MMM controller, which is @@ -333,15 +333,6 @@ config MMC_MESON_GX help Support for EMMC host controller on Meson GX ARM SoCs platform (S905) -config MMC_MXC - bool "Freescale i.MX21/27/31 or MPC512x Multimedia Card support" - help - This selects the Freescale i.MX21, i.MX27, i.MX31 or MPC512x - Multimedia Card Interface. If you have an i.MX or MPC512x platform - with a Multimedia Card slot, say Y here. - - If unsure, say N. - config MMC_OWL bool "Actions OWL Multimedia Card Interface support" depends on ARCH_OWL @@ -391,6 +382,7 @@ config MVEBU_MMC config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" + depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS select DM_REGULATOR_PBIAS if DM_REGULATOR help This selects the TI OMAP High Speed Multimedia card Interface. @@ -597,7 +589,7 @@ config MMC_SDHCI_BCM2835 config MMC_SDHCI_BCMSTB tristate "SDHCI support for the BCMSTB SD/MMC Controller" - depends on MMC_SDHCI + depends on MMC_SDHCI && (ARCH_BCMSTB || ARCH_BCM283X) help This selects the Broadcom set-top box SD/MMC controller. @@ -660,19 +652,9 @@ config MMC_SDHCI_F_SDH30 If you have a controller with this interface, say Y here. If unsure, say N. -config MMC_SDHCI_KONA - bool "SDHCI support on Broadcom KONA platform" - depends on MMC_SDHCI - help - This selects the Broadcom Kona Secure Digital Host Controller - Interface(SDHCI) support. - This is used in Broadcom mobile SoCs. - - If you have a controller with this interface, say Y here. - config MMC_SDHCI_MSM bool "Qualcomm SDHCI controller" - depends on MMC_SDHCI + depends on MMC_SDHCI && ARCH_SNAPDRAGON help Enables support for SDHCI 2.0 controller present on some Qualcomm Snapdragon devices. This device is compatible with eMMC v4.5 and @@ -718,7 +700,7 @@ config MMC_SDHCI_ROCKCHIP config MMC_SDHCI_S5P bool "SDHCI support on Samsung S5P SoC" - depends on MMC_SDHCI + depends on MMC_SDHCI && S5P help This selects the Secure Digital Host Controller Interface (SDHCI) on Samsung S5P SoCs. @@ -740,7 +722,7 @@ config MMC_SDHCI_SNPS config MMC_SDHCI_STI bool "SDHCI support for STMicroelectronics SoC" - depends on MMC_SDHCI && OF_CONTROL + depends on MMC_SDHCI && OF_CONTROL && ARCH_STI help This selects the Secure Digital Host Controller Interface (SDHCI) on STMicroelectronics STiH410 SoC. @@ -794,6 +776,7 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" depends on OF_CONTROL + depends on ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 || ARCH_ZYNQ || ARCH_ZYNQMP depends on MMC_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform @@ -852,7 +835,7 @@ config GENERIC_ATMEL_MCI config STM32_SDMMC2 bool "STMicroelectronics STM32H7 SD/MMC Host Controller support" - depends on OF_CONTROL + depends on OF_CONTROL && (ARCH_STM32 || ARCH_STM32MP) help This selects support for the SD/MMC controller on STM32H7 SoCs. If you have a board based on such a SoC and with a SD/MMC slot, @@ -886,6 +869,7 @@ config FSL_SDHC_V2_3 config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" + depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || PPC select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \ || ARCH_C29X help @@ -938,6 +922,7 @@ config ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" + depends on MACH_IMX help This selects support for the i.MX eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 360706f53d2..a23336d7d8d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o -obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxsmmc.o obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o obj-$(CONFIG_MMC_OWL) += owl_mmc.o @@ -64,7 +63,6 @@ obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence6.o obj-$(CONFIG_MMC_SDHCI_CV1800B) += cv1800b_sdhci.o obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o -obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o obj-$(CONFIG_MMC_SDHCI_MSM) += msm_sdhci.o obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o obj-$(CONFIG_MMC_SDHCI_NPCM) += npcm_sdhci.o diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c deleted file mode 100644 index 83f14122632..00000000000 --- a/drivers/mmc/kona_sdhci.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <malloc.h> -#include <sdhci.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/kona-common/clk.h> - -#define SDHCI_CORECTRL_OFFSET 0x00008000 -#define SDHCI_CORECTRL_EN 0x01 -#define SDHCI_CORECTRL_RESET 0x02 - -#define SDHCI_CORESTAT_OFFSET 0x00008004 -#define SDHCI_CORESTAT_CD_SW 0x01 - -#define SDHCI_COREIMR_OFFSET 0x00008008 -#define SDHCI_COREIMR_IP 0x01 - -static int init_kona_mmc_core(struct sdhci_host *host) -{ - unsigned int mask; - unsigned int timeout; - - if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) { - printf("%s: sd host controller reset error\n", __func__); - return -EBUSY; - } - - /* For kona a hardware reset before anything else. */ - mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; - sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); - - /* Wait max 100 ms */ - timeout = 1000; - do { - if (timeout == 0) { - printf("%s: reset timeout error\n", __func__); - return -ETIMEDOUT; - } - timeout--; - udelay(100); - } while (0 == - (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & - SDHCI_CORECTRL_RESET)); - - /* Clear the reset bit. */ - mask = mask & ~SDHCI_CORECTRL_RESET; - sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); - - /* Enable AHB clock */ - mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); - sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); - - /* Enable interrupts */ - sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); - - /* Make sure Card is detected in controller */ - mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); - sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); - - /* Wait max 100 ms */ - timeout = 1000; - while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { - if (timeout == 0) { - printf("%s: CARD DETECT timeout error\n", __func__); - return -ETIMEDOUT; - } - timeout--; - udelay(100); - } - return 0; -} - -int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) -{ - int ret = 0; - u32 max_clk; - void *reg_base; - struct sdhci_host *host = NULL; - - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("%s: sdhci host malloc fail!\n", __func__); - return -ENOMEM; - } - switch (dev_index) { - case 0: - reg_base = (void *)CONFIG_SYS_SDIO_BASE0; - ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, - &max_clk); - break; - case 1: - reg_base = (void *)CONFIG_SYS_SDIO_BASE1; - ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, - &max_clk); - break; - case 2: - reg_base = (void *)CONFIG_SYS_SDIO_BASE2; - ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, - &max_clk); - break; - case 3: - reg_base = (void *)CONFIG_SYS_SDIO_BASE3; - ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, - &max_clk); - break; - default: - printf("%s: sdio dev index %d not supported\n", - __func__, dev_index); - ret = -EINVAL; - } - if (ret) { - free(host); - return ret; - } - - host->name = "kona-sdhci"; - host->ioaddr = reg_base; - host->quirks = quirks; - host->max_clk = max_clk; - - if (init_kona_mmc_core(host)) { - free(host); - return -EINVAL; - } - - add_sdhci(host, 0, min_clk); - return ret; -} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 2c1f4f9c336..5f2efbe6df9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2365,8 +2365,10 @@ static int mmc_startup_v4(struct mmc *mmc) return -ENOMEM; memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN); #endif - if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions)) - return -EINVAL; + if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions)) { + err = -EINVAL; + goto error; + } mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]]; diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c deleted file mode 100644 index 1acea6f820b..00000000000 --- a/drivers/mmc/mxcmmc.c +++ /dev/null @@ -1,523 +0,0 @@ -/* - * This is a driver for the SDHC controller found in Freescale MX2/MX3 - * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). - * Unlike the hardware found on MX1, this hardware just works and does - * not need all the quirks found in imxmmc.c, hence the seperate driver. - * - * Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com> - * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> - * - * derived from pxamci.c by Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <config.h> -#include <command.h> -#include <mmc.h> -#include <part.h> -#include <malloc.h> -#include <mmc.h> -#include <time.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> - -#define DRIVER_NAME "mxc-mmc" - -struct mxcmci_regs { - u32 str_stp_clk; - u32 status; - u32 clk_rate; - u32 cmd_dat_cont; - u32 res_to; - u32 read_to; - u32 blk_len; - u32 nob; - u32 rev_no; - u32 int_cntr; - u32 cmd; - u32 arg; - u32 pad; - u32 res_fifo; - u32 buffer_access; -}; - -#define STR_STP_CLK_RESET (1 << 3) -#define STR_STP_CLK_START_CLK (1 << 1) -#define STR_STP_CLK_STOP_CLK (1 << 0) - -#define STATUS_CARD_INSERTION (1 << 31) -#define STATUS_CARD_REMOVAL (1 << 30) -#define STATUS_YBUF_EMPTY (1 << 29) -#define STATUS_XBUF_EMPTY (1 << 28) -#define STATUS_YBUF_FULL (1 << 27) -#define STATUS_XBUF_FULL (1 << 26) -#define STATUS_BUF_UND_RUN (1 << 25) -#define STATUS_BUF_OVFL (1 << 24) -#define STATUS_SDIO_INT_ACTIVE (1 << 14) -#define STATUS_END_CMD_RESP (1 << 13) -#define STATUS_WRITE_OP_DONE (1 << 12) -#define STATUS_DATA_TRANS_DONE (1 << 11) -#define STATUS_READ_OP_DONE (1 << 11) -#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) -#define STATUS_CARD_BUS_CLK_RUN (1 << 8) -#define STATUS_BUF_READ_RDY (1 << 7) -#define STATUS_BUF_WRITE_RDY (1 << 6) -#define STATUS_RESP_CRC_ERR (1 << 5) -#define STATUS_CRC_READ_ERR (1 << 3) -#define STATUS_CRC_WRITE_ERR (1 << 2) -#define STATUS_TIME_OUT_RESP (1 << 1) -#define STATUS_TIME_OUT_READ (1 << 0) -#define STATUS_ERR_MASK 0x2f - -#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) -#define CMD_DAT_CONT_STOP_READWAIT (1 << 11) -#define CMD_DAT_CONT_START_READWAIT (1 << 10) -#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) -#define CMD_DAT_CONT_INIT (1 << 7) -#define CMD_DAT_CONT_WRITE (1 << 4) -#define CMD_DAT_CONT_DATA_ENABLE (1 << 3) -#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) -#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) -#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) - -#define INT_SDIO_INT_WKP_EN (1 << 18) -#define INT_CARD_INSERTION_WKP_EN (1 << 17) -#define INT_CARD_REMOVAL_WKP_EN (1 << 16) -#define INT_CARD_INSERTION_EN (1 << 15) -#define INT_CARD_REMOVAL_EN (1 << 14) -#define INT_SDIO_IRQ_EN (1 << 13) -#define INT_DAT0_EN (1 << 12) -#define INT_BUF_READ_EN (1 << 4) -#define INT_BUF_WRITE_EN (1 << 3) -#define INT_END_CMD_RES_EN (1 << 2) -#define INT_WRITE_OP_DONE_EN (1 << 1) -#define INT_READ_OP_EN (1 << 0) - -struct mxcmci_host { - struct mmc *mmc; - struct mxcmci_regs *base; - int irq; - int detect_irq; - int dma; - int do_dma; - unsigned int power_mode; - - struct mmc_cmd *cmd; - struct mmc_data *data; - - unsigned int dma_nents; - unsigned int datasize; - unsigned int dma_dir; - - u16 rev_no; - unsigned int cmdat; - - int clock; -}; - -static struct mxcmci_host mxcmci_host; - -/* maintainer note: do we really want to have a global host pointer? */ -static struct mxcmci_host *host = &mxcmci_host; - -static inline int mxcmci_use_dma(struct mxcmci_host *host) -{ - return host->do_dma; -} - -static void mxcmci_softreset(struct mxcmci_host *host) -{ - int i; - - /* reset sequence */ - writel(STR_STP_CLK_RESET, &host->base->str_stp_clk); - writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, - &host->base->str_stp_clk); - - for (i = 0; i < 8; i++) - writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); - - writel(0xff, &host->base->res_to); -} - -static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) -{ - unsigned int nob = data->blocks; - unsigned int blksz = data->blocksize; - unsigned int datasize = nob * blksz; - - host->data = data; - - writel(nob, &host->base->nob); - writel(blksz, &host->base->blk_len); - host->datasize = datasize; -} - -static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd, - unsigned int cmdat) -{ - if (host->cmd != NULL) - printf("mxcmci: error!\n"); - host->cmd = cmd; - - switch (cmd->resp_type) { - case MMC_RSP_R1: /* short CRC, OPCODE */ - case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */ - cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; - break; - case MMC_RSP_R2: /* long 136 bit + CRC */ - cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; - break; - case MMC_RSP_R3: /* short */ - cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; - break; - case MMC_RSP_NONE: - break; - default: - printf("mxcmci: unhandled response type 0x%x\n", - cmd->resp_type); - return -EINVAL; - } - - writel(cmd->cmdidx, &host->base->cmd); - writel(cmd->cmdarg, &host->base->arg); - writel(cmdat, &host->base->cmd_dat_cont); - - return 0; -} - -static void mxcmci_finish_request(struct mxcmci_host *host, - struct mmc_cmd *cmd, struct mmc_data *data) -{ - host->cmd = NULL; - host->data = NULL; -} - -static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) -{ - int data_error = 0; - - if (stat & STATUS_ERR_MASK) { - printf("request failed. status: 0x%08x\n", - stat); - if (stat & STATUS_CRC_READ_ERR) { - data_error = -EILSEQ; - } else if (stat & STATUS_CRC_WRITE_ERR) { - u32 err_code = (stat >> 9) & 0x3; - if (err_code == 2) /* No CRC response */ - data_error = -ETIMEDOUT; - else - data_error = -EILSEQ; - } else if (stat & STATUS_TIME_OUT_READ) { - data_error = -ETIMEDOUT; - } else { - data_error = -EIO; - } - } - - host->data = NULL; - - return data_error; -} - -static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) -{ - struct mmc_cmd *cmd = host->cmd; - int i; - u32 a, b, c; - u32 *resp = (u32 *)cmd->response; - - if (!cmd) - return 0; - - if (stat & STATUS_TIME_OUT_RESP) { - printf("CMD TIMEOUT\n"); - return -ETIMEDOUT; - } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) { - printf("cmd crc error\n"); - return -EILSEQ; - } - - if (cmd->resp_type & MMC_RSP_PRESENT) { - if (cmd->resp_type & MMC_RSP_136) { - for (i = 0; i < 4; i++) { - a = readl(&host->base->res_fifo) & 0xFFFF; - b = readl(&host->base->res_fifo) & 0xFFFF; - resp[i] = a << 16 | b; - } - } else { - a = readl(&host->base->res_fifo) & 0xFFFF; - b = readl(&host->base->res_fifo) & 0xFFFF; - c = readl(&host->base->res_fifo) & 0xFFFF; - resp[0] = a << 24 | b << 8 | c >> 8; - } - } - return 0; -} - -static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) -{ - u32 stat; - unsigned long timeout = get_ticks() + CONFIG_SYS_HZ; - - do { - stat = readl(&host->base->status); - if (stat & STATUS_ERR_MASK) - return stat; - if (timeout < get_ticks()) - return STATUS_TIME_OUT_READ; - if (stat & mask) - return 0; - } while (1); -} - -static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) -{ - unsigned int stat; - u32 *buf = _buf; - - while (bytes > 3) { - stat = mxcmci_poll_status(host, - STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); - if (stat) - return stat; - *buf++ = readl(&host->base->buffer_access); - bytes -= 4; - } - - if (bytes) { - u8 *b = (u8 *)buf; - u32 tmp; - - stat = mxcmci_poll_status(host, - STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); - if (stat) - return stat; - tmp = readl(&host->base->buffer_access); - memcpy(b, &tmp, bytes); - } - - return 0; -} - -static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes) -{ - unsigned int stat; - const u32 *buf = _buf; - - while (bytes > 3) { - stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); - if (stat) - return stat; - writel(*buf++, &host->base->buffer_access); - bytes -= 4; - } - - if (bytes) { - const u8 *b = (u8 *)buf; - u32 tmp; - - stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); - if (stat) - return stat; - - memcpy(&tmp, b, bytes); - writel(tmp, &host->base->buffer_access); - } - - stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); - if (stat) - return stat; - - return 0; -} - -static int mxcmci_transfer_data(struct mxcmci_host *host) -{ - struct mmc_data *data = host->data; - int stat; - unsigned long length; - - length = data->blocks * data->blocksize; - host->datasize = 0; - - if (data->flags & MMC_DATA_READ) { - stat = mxcmci_pull(host, data->dest, length); - if (stat) - return stat; - host->datasize += length; - } else { - stat = mxcmci_push(host, (const void *)(data->src), length); - if (stat) - return stat; - host->datasize += length; - stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); - if (stat) - return stat; - } - return 0; -} - -static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) -{ - int datastat; - int ret; - - ret = mxcmci_read_response(host, stat); - - if (ret) { - mxcmci_finish_request(host, host->cmd, host->data); - return ret; - } - - if (!host->data) { - mxcmci_finish_request(host, host->cmd, host->data); - return 0; - } - - datastat = mxcmci_transfer_data(host); - ret = mxcmci_finish_data(host, datastat); - mxcmci_finish_request(host, host->cmd, host->data); - return ret; -} - -static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct mxcmci_host *host = mmc->priv; - unsigned int cmdat = host->cmdat; - u32 stat; - int ret; - - host->cmdat &= ~CMD_DAT_CONT_INIT; - if (data) { - mxcmci_setup_data(host, data); - - cmdat |= CMD_DAT_CONT_DATA_ENABLE; - - if (data->flags & MMC_DATA_WRITE) - cmdat |= CMD_DAT_CONT_WRITE; - } - - if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) { - mxcmci_finish_request(host, cmd, data); - return ret; - } - - do { - stat = readl(&host->base->status); - writel(stat, &host->base->status); - } while (!(stat & STATUS_END_CMD_RESP)); - - return mxcmci_cmd_done(host, stat); -} - -static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) -{ - unsigned int divider; - int prescaler = 0; - unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK); - - while (prescaler <= 0x800) { - for (divider = 1; divider <= 0xF; divider++) { - int x; - - x = (clk_in / (divider + 1)); - - if (prescaler) - x /= (prescaler * 2); - - if (x <= clk_ios) - break; - } - if (divider < 0x10) - break; - - if (prescaler == 0) - prescaler = 1; - else - prescaler <<= 1; - } - - writel((prescaler << 4) | divider, &host->base->clk_rate); -} - -static int mxcmci_set_ios(struct mmc *mmc) -{ - struct mxcmci_host *host = mmc->priv; - if (mmc->bus_width == 4) - host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; - else - host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; - - if (mmc->clock) { - mxcmci_set_clk_rate(host, mmc->clock); - writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); - } else { - writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk); - } - - host->clock = mmc->clock; - - return 0; -} - -static int mxcmci_init(struct mmc *mmc) -{ - struct mxcmci_host *host = mmc->priv; - - mxcmci_softreset(host); - - host->rev_no = readl(&host->base->rev_no); - if (host->rev_no != 0x400) { - printf("wrong rev.no. 0x%08x. aborting.\n", - host->rev_no); - return -ENODEV; - } - - /* recommended in data sheet */ - writel(0x2db4, &host->base->read_to); - - writel(0, &host->base->int_cntr); - - return 0; -} - -static const struct mmc_ops mxcmci_ops = { - .send_cmd = mxcmci_request, - .set_ios = mxcmci_set_ios, - .init = mxcmci_init, -}; - -static struct mmc_config mxcmci_cfg = { - .name = "MXC MCI", - .ops = &mxcmci_ops, - .host_caps = MMC_MODE_4BIT, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; - -static int mxcmci_initialize(struct bd_info *bis) -{ - host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; - - mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; - mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - - host->mmc = mmc_create(&mxcmci_cfg, host); - if (host->mmc == NULL) - return -1; - - return 0; -} - -int mxc_mmc_init(struct bd_info *bis) -{ - return mxcmci_initialize(bis); -} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 950ed0f25a9..d942fa4e202 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -411,6 +411,14 @@ config ETH_DESIGNWARE_S700 This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. +config ETH_DESIGNWARE_THEAD + bool "T-Head glue driver for Synopsys Designware Ethernet MAC" + depends on ETH_DESIGNWARE + select DW_ALTDESCRIPTOR + help + This provides glue layer to use Synopsys Designware Ethernet MAC + present on T-Head SoCs. + config DW_ALTDESCRIPTOR bool "Designware Ethernet MAC uses alternate (enhanced) descriptors" depends on ETH_DESIGNWARE diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 67bba3a8536..79cc8b422b0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_ETH_DESIGNWARE) += designware.o obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o +obj-$(CONFIG_ETH_DESIGNWARE_THEAD) += dwmac_thead.o obj-$(CONFIG_ETH_SANDBOX) += sandbox.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c index 7e35e1fd41d..6588eb3a806 100644 --- a/drivers/net/airoha_eth.c +++ b/drivers/net/airoha_eth.c @@ -97,6 +97,7 @@ (_n) == 2 ? GDM2_BASE : GDM1_BASE) #define REG_GDM_FWD_CFG(_n) GDM_BASE(_n) +#define GDM_PAD_EN BIT(28) #define GDM_DROP_CRC_ERR BIT(23) #define GDM_IP4_CKSUM BIT(22) #define GDM_TCP_CKSUM BIT(21) @@ -354,13 +355,37 @@ static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) #define airoha_switch_wr(eth, offset, val) \ airoha_wr((eth)->switch_regs, (offset), (val)) +static inline dma_addr_t dma_map_unaligned(void *vaddr, size_t len, + enum dma_data_direction dir) +{ + uintptr_t start, end; + + start = ALIGN_DOWN((uintptr_t)vaddr, ARCH_DMA_MINALIGN); + end = ALIGN((uintptr_t)(vaddr + len), ARCH_DMA_MINALIGN); + + return dma_map_single((void *)start, end - start, dir); +} + +static inline void dma_unmap_unaligned(dma_addr_t addr, size_t len, + enum dma_data_direction dir) +{ + uintptr_t start, end; + + start = ALIGN_DOWN((uintptr_t)addr, ARCH_DMA_MINALIGN); + end = ALIGN((uintptr_t)(addr + len), ARCH_DMA_MINALIGN); + dma_unmap_single(start, end - start, dir); +} + static void airoha_fe_maccr_init(struct airoha_eth *eth) { int p; for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) { - /* Disable any kind of CRC drop or offload */ - airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), 0); + /* + * Disable any kind of CRC drop or offload. + * Enable padding of short TX packets to 60 bytes. + */ + airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), GDM_PAD_EN); } } @@ -371,13 +396,14 @@ static int airoha_fe_init(struct airoha_eth *eth) return 0; } -static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index, - uchar *rx_packet) +static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index) { struct airoha_qdma_desc *desc; + uchar *rx_packet; u32 val; desc = &q->desc[index]; + rx_packet = net_rx_packets[index]; index = (index + 1) % q->ndesc; dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE); @@ -391,7 +417,7 @@ static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index, val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN); WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); - dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); + dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE); } static void airoha_qdma_init_rx_desc(struct airoha_queue *q) @@ -399,7 +425,7 @@ static void airoha_qdma_init_rx_desc(struct airoha_queue *q) int i; for (i = 0; i < q->ndesc; i++) - airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]); + airoha_qdma_reset_rx_desc(q, i); } static int airoha_qdma_init_rx_queue(struct airoha_queue *q, @@ -423,10 +449,14 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q, RX_RING_SIZE_MASK, FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); + /* + * See arht_eth_free_pkt() for the reasons used to fill + * REG_RX_CPU_IDX(qid) register. + */ airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, FIELD_PREP(RX_RING_THR_MASK, 0)); airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, - FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 1)); + FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 3)); airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); @@ -804,6 +834,11 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) u32 val; int i; + /* + * There is no need to pad short TX packets to 60 bytes since the + * GDM_PAD_EN bit set in the corresponding REG_GDM_FWD_CFG(n) register. + */ + dma_addr = dma_map_single(packet, length, DMA_TO_DEVICE); qid = 0; @@ -826,14 +861,14 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length) WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); - dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE); + dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE); airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); for (i = 0; i < 100; i++) { - dma_unmap_single(virt_to_phys(desc), sizeof(*desc), - DMA_FROM_DEVICE); + dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); if (desc->ctrl & QDMA_DESC_DONE_MASK) break; @@ -864,8 +899,8 @@ static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp) q = &qdma->q_rx[qid]; desc = &q->desc[q->head]; - dma_unmap_single(virt_to_phys(desc), sizeof(*desc), - DMA_FROM_DEVICE); + dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc), + DMA_FROM_DEVICE); if (!(desc->ctrl & QDMA_DESC_DONE_MASK)) return -EAGAIN; @@ -885,6 +920,7 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) struct airoha_qdma *qdma = ð->qdma[0]; struct airoha_queue *q; int qid; + u16 prev, pprev; if (!packet) return 0; @@ -892,13 +928,24 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length) qid = 0; q = &qdma->q_rx[qid]; - dma_map_single(packet, length, DMA_TO_DEVICE); - - airoha_qdma_reset_rx_desc(q, q->head, packet); + /* + * Due to cpu cache issue the airoha_qdma_reset_rx_desc() function + * will always touch 2 descriptors: + * - if current descriptor is even, then the previous and the one + * before previous descriptors will be touched (previous cacheline) + * - if current descriptor is odd, then only current and previous + * descriptors will be touched (current cacheline) + * + * Thus, to prevent possible destroying of rx queue, only (q->ndesc - 2) + * descriptors might be used for packet receiving. + */ + prev = (q->head + q->ndesc - 1) % q->ndesc; + pprev = (q->head + q->ndesc - 2) % q->ndesc; + q->head = (q->head + 1) % q->ndesc; + airoha_qdma_reset_rx_desc(q, prev); airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, - FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); - q->head = (q->head + 1) % q->ndesc; + FIELD_PREP(RX_RING_CPU_IDX_MASK, pprev)); return 0; } @@ -926,6 +973,7 @@ static int arht_eth_write_hwaddr(struct udevice *dev) static const struct udevice_id airoha_eth_ids[] = { { .compatible = "airoha,en7581-eth" }, + { } }; static const struct eth_ops airoha_eth_ops = { diff --git a/drivers/net/dwmac_thead.c b/drivers/net/dwmac_thead.c new file mode 100644 index 00000000000..138d71a6202 --- /dev/null +++ b/drivers/net/dwmac_thead.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD DWMAC platform driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + * + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <phy.h> + +#include "designware.h" + +#define GMAC_CLK_EN 0x00 +#define GMAC_TX_CLK_EN BIT(1) +#define GMAC_TX_CLK_N_EN BIT(2) +#define GMAC_TX_CLK_OUT_EN BIT(3) +#define GMAC_RX_CLK_EN BIT(4) +#define GMAC_RX_CLK_N_EN BIT(5) +#define GMAC_EPHY_REF_CLK_EN BIT(6) +#define GMAC_RXCLK_DELAY_CTRL 0x04 +#define GMAC_RXCLK_BYPASS BIT(15) +#define GMAC_RXCLK_INVERT BIT(14) +#define GMAC_RXCLK_DELAY GENMASK(4, 0) +#define GMAC_TXCLK_DELAY_CTRL 0x08 +#define GMAC_TXCLK_BYPASS BIT(15) +#define GMAC_TXCLK_INVERT BIT(14) +#define GMAC_TXCLK_DELAY GENMASK(4, 0) +#define GMAC_PLLCLK_DIV 0x0c +#define GMAC_PLLCLK_DIV_EN BIT(31) +#define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0) +#define GMAC_GTXCLK_SEL 0x18 +#define GMAC_GTXCLK_SEL_PLL BIT(0) +#define GMAC_INTF_CTRL 0x1c +#define PHY_INTF_MASK BIT(0) +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) +#define GMAC_TXCLK_OEN 0x20 +#define TXCLK_DIR_MASK BIT(0) +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) + +#define GMAC_RGMII_CLK_RATE 125000000 + +struct dwmac_thead_plat { + struct dw_eth_pdata dw_eth_pdata; + void __iomem *apb_base; +}; + +static int dwmac_thead_set_phy_if(struct dwmac_thead_plat *plat) +{ + u32 phyif; + + switch (plat->dw_eth_pdata.eth_pdata.phy_interface) { + case PHY_INTERFACE_MODE_MII: + phyif = PHY_INTF_MII_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + phyif = PHY_INTF_RGMII; + break; + default: + return -EINVAL; + } + + writel(phyif, plat->apb_base + GMAC_INTF_CTRL); + return 0; +} + +static int dwmac_thead_set_txclk_dir(struct dwmac_thead_plat *plat) +{ + u32 txclk_dir; + + switch (plat->dw_eth_pdata.eth_pdata.phy_interface) { + case PHY_INTERFACE_MODE_MII: + txclk_dir = TXCLK_DIR_INPUT; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + txclk_dir = TXCLK_DIR_OUTPUT; + break; + default: + return -EINVAL; + } + + writel(txclk_dir, plat->apb_base + GMAC_TXCLK_OEN); + return 0; +} + +static unsigned long dwmac_thead_rgmii_tx_rate(int speed) +{ + switch (speed) { + case 10: + return 2500000; + case 100: + return 25000000; + case 1000: + return 125000000; + } + + return -EINVAL; +} + +static int dwmac_thead_set_clk_tx_rate(struct dwmac_thead_plat *plat, + struct dw_eth_dev *edev, + unsigned long tx_rate) +{ + unsigned long rate; + u32 div, reg; + + rate = clk_get_rate(&edev->clocks[0]); + + writel(0, plat->apb_base + GMAC_PLLCLK_DIV); + + div = rate / tx_rate; + if (rate != tx_rate * div) { + pr_err("invalid gmac rate %lu\n", rate); + return -EINVAL; + } + + reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) | + FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div); + writel(reg, plat->apb_base + GMAC_PLLCLK_DIV); + + return 0; +} + +static int dwmac_thead_enable_clk(struct dwmac_thead_plat *plat) +{ + u32 reg; + + switch (plat->dw_eth_pdata.eth_pdata.phy_interface) { + case PHY_INTERFACE_MODE_MII: + reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* use pll */ + writel(GMAC_GTXCLK_SEL_PLL, plat->apb_base + GMAC_GTXCLK_SEL); + reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; + break; + + default: + return -EINVAL; + } + + writel(reg, plat->apb_base + GMAC_CLK_EN); + return 0; +} + +static int dwmac_thead_eth_start(struct udevice *dev) +{ + struct dwmac_thead_plat *plat = dev_get_plat(dev); + struct dw_eth_dev *edev = dev_get_priv(dev); + phy_interface_t interface; + bool is_rgmii; + long tx_rate; + int ret; + + interface = plat->dw_eth_pdata.eth_pdata.phy_interface; + is_rgmii = (interface == PHY_INTERFACE_MODE_RGMII) | + (interface == PHY_INTERFACE_MODE_RGMII_ID) | + (interface == PHY_INTERFACE_MODE_RGMII_RXID) | + (interface == PHY_INTERFACE_MODE_RGMII_TXID); + + /* + * When operating in RGMII mode, the TX clock is generated by an + * internal divider and fed to the MAC. Configure and enable it before + * initializing the MAC. + */ + if (is_rgmii) { + ret = dwmac_thead_set_clk_tx_rate(plat, edev, + GMAC_RGMII_CLK_RATE); + if (ret) + return ret; + } + + ret = designware_eth_init(edev, plat->dw_eth_pdata.eth_pdata.enetaddr); + if (ret) + return ret; + + if (is_rgmii) { + tx_rate = dwmac_thead_rgmii_tx_rate(edev->phydev->speed); + if (tx_rate < 0) + return tx_rate; + + ret = dwmac_thead_set_clk_tx_rate(plat, edev, tx_rate); + if (ret) + return ret; + } + + ret = designware_eth_enable(edev); + if (ret) + return ret; + + return 0; +} + +static int dwmac_thead_probe(struct udevice *dev) +{ + struct dwmac_thead_plat *plat = dev_get_plat(dev); + unsigned int reg; + int ret; + + ret = designware_eth_probe(dev); + if (ret) + return ret; + + ret = dwmac_thead_set_phy_if(plat); + if (ret) { + pr_err("failed to set phy interface: %d\n", ret); + return ret; + } + + ret = dwmac_thead_set_txclk_dir(plat); + if (ret) { + pr_err("failed to set TX clock direction: %d\n", ret); + return ret; + } + + reg = readl(plat->apb_base + GMAC_RXCLK_DELAY_CTRL); + reg &= ~(GMAC_RXCLK_DELAY); + reg |= FIELD_PREP(GMAC_RXCLK_DELAY, 0); + writel(reg, plat->apb_base + GMAC_RXCLK_DELAY_CTRL); + + reg = readl(plat->apb_base + GMAC_TXCLK_DELAY_CTRL); + reg &= ~(GMAC_TXCLK_DELAY); + reg |= FIELD_PREP(GMAC_TXCLK_DELAY, 0); + writel(reg, plat->apb_base + GMAC_TXCLK_DELAY_CTRL); + + ret = dwmac_thead_enable_clk(plat); + if (ret) + pr_err("failed to enable clock: %d\n", ret); + + return ret; +} + +static int dwmac_thead_of_to_plat(struct udevice *dev) +{ + struct dwmac_thead_plat *pdata = dev_get_plat(dev); + + pdata->apb_base = dev_read_addr_index_ptr(dev, 1); + if (!pdata->apb_base) { + pr_err("failed to get apb registers\n"); + return -ENOENT; + } + + return designware_eth_of_to_plat(dev); +} + +static const struct eth_ops dwmac_thead_eth_ops = { + .start = dwmac_thead_eth_start, + .send = designware_eth_send, + .recv = designware_eth_recv, + .free_pkt = designware_eth_free_pkt, + .stop = designware_eth_stop, + .write_hwaddr = designware_eth_write_hwaddr, +}; + +static const struct udevice_id dwmac_thead_match[] = { + { .compatible = "thead,th1520-gmac" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwmac_thead) = { + .name = "dwmac_thead", + .id = UCLASS_ETH, + .of_match = dwmac_thead_match, + .of_to_plat = dwmac_thead_of_to_plat, + .probe = dwmac_thead_probe, + .ops = &dwmac_thead_eth_ops, + .priv_auto = sizeof(struct dw_eth_dev), + .plat_auto = sizeof(struct dwmac_thead_plat), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c index 25a98e0f935..a2589a2ad31 100644 --- a/drivers/net/mtk_eth/an8855.c +++ b/drivers/net/mtk_eth/an8855.c @@ -909,7 +909,7 @@ static void an8855_port_isolation(struct an8855_switch_priv *priv) /* Set port mode to user port */ an8855_reg_write(priv, AN8855_PVC(i), - (0x8100 << AN8855_STAG_VPID_S) | + (0x9100 << AN8855_STAG_VPID_S) | (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S)); } } diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 59894d2430b..c370f8c6400 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -385,8 +385,10 @@ static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, int ret; ret = pci_get_bus(PCI_BUS(bdf), &bus); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } return pci_bus_read_config(bus, bdf, offset, valuep, size); } @@ -408,8 +410,10 @@ int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } *valuep = value; return 0; @@ -421,8 +425,10 @@ int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); - if (ret) + if (ret) { + *valuep = 0xffff; return ret; + } *valuep = value; return 0; @@ -434,8 +440,10 @@ int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) int ret; ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); - if (ret) + if (ret) { + *valuep = 0xff; return ret; + } *valuep = value; return 0; @@ -447,8 +455,10 @@ int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); - if (ret) + if (ret) { + *valuep = 0xff; return ret; + } *valuep = value; return 0; @@ -460,8 +470,10 @@ int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); - if (ret) + if (ret) { + *valuep = 0xffff; return ret; + } *valuep = value; return 0; @@ -473,8 +485,10 @@ int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep) int ret; ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); - if (ret) + if (ret) { + *valuep = 0xffffffff; return ret; + } *valuep = value; return 0; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index d9c76898a96..58e070bfe1e 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -317,8 +317,7 @@ int pinctrl_select_state(struct udevice *dev, const char *statename) if (!dev_has_ofnode(dev)) return 0; /* - * Try full-implemented pinctrl first. - * If it fails or is not implemented, try simple one. + * If full-implemented pinctrl is not implemented, try simple one. */ if (CONFIG_IS_ENABLED(PINCTRL_FULL)) return pinctrl_select_state_full(dev, statename); diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 7d022ce718a..78efed6b66a 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -39,7 +39,7 @@ static void scsi_print_error(struct scsi_cmd *pccb) #ifdef CONFIG_SYS_64BIT_LBA void scsi_setup_read16(struct scsi_cmd *pccb, lbaint_t start, - unsigned long blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_READ16; pccb->cmd[1] = 0; @@ -83,7 +83,7 @@ static void scsi_setup_inquiry(struct scsi_cmd *pccb) } static void scsi_setup_sync_cache(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_SYNC_CACHE; pccb->cmd[1] = 0; @@ -100,7 +100,7 @@ static void scsi_setup_sync_cache(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_READ10; pccb->cmd[1] = 0; @@ -121,7 +121,7 @@ static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { pccb->cmd[0] = SCSI_WRITE10; pccb->cmd[1] = 0; @@ -143,7 +143,7 @@ static void scsi_setup_write_ext(struct scsi_cmd *pccb, lbaint_t start, } static void scsi_setup_erase_ext(struct scsi_cmd *pccb, lbaint_t start, - unsigned short blocks) + lbaint_t blocks) { u8 *param = tempbuff; const u8 param_size = 24; @@ -193,9 +193,8 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, struct blk_desc *block_dev = dev_get_uclass_plat(dev); struct udevice *bdev = dev->parent; struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev); - lbaint_t start, blks, max_blks; + lbaint_t start, blks, max_blks, blocks; uintptr_t buf_addr; - unsigned short smallblks = 0; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; /* Setup device */ @@ -217,7 +216,6 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, pccb->dma_dir = DMA_FROM_DEVICE; #ifdef CONFIG_SYS_64BIT_LBA if (start > SCSI_LBA48_READ) { - unsigned long blocks; blocks = min_t(lbaint_t, blks, max_blks); pccb->datalen = block_dev->blksz * blocks; scsi_setup_read16(pccb, start, blocks); @@ -227,20 +225,20 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, #endif if (blks > max_blks) { pccb->datalen = block_dev->blksz * max_blks; - smallblks = max_blks; - scsi_setup_read_ext(pccb, start, smallblks); + blocks = max_blks; + scsi_setup_read_ext(pccb, start, blocks); start += max_blks; blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; - smallblks = (unsigned short)blks; - scsi_setup_read_ext(pccb, start, smallblks); + blocks = blks; + scsi_setup_read_ext(pccb, start, blocks); start += blks; blks = 0; } debug("scsi_read_ext: startblk " LBAF - ", blccnt %x buffer %lX\n", - start, smallblks, buf_addr); + ", blccnt " LBAF " buffer %lX\n", + start, blocks, buf_addr); if (scsi_exec(bdev, pccb)) { scsi_print_error(pccb); blkcnt -= blks; @@ -249,7 +247,7 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, buf_addr += pccb->datalen; } while (blks != 0); debug("scsi_read_ext: end startblk " LBAF - ", blccnt %x buffer %lX\n", start, smallblks, buf_addr); + ", blccnt " LBAF " buffer %lX\n", start, blocks, buf_addr); return blkcnt; } @@ -263,9 +261,8 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, struct blk_desc *block_dev = dev_get_uclass_plat(dev); struct udevice *bdev = dev->parent; struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev); - lbaint_t start, blks, max_blks; + lbaint_t start, blks, max_blks, blocks; uintptr_t buf_addr; - unsigned short smallblks; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; /* Setup device */ @@ -286,19 +283,19 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, pccb->dma_dir = DMA_TO_DEVICE; if (blks > max_blks) { pccb->datalen = block_dev->blksz * max_blks; - smallblks = max_blks; - scsi_setup_write_ext(pccb, start, smallblks); + blocks = max_blks; + scsi_setup_write_ext(pccb, start, blocks); start += max_blks; blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; - smallblks = (unsigned short)blks; - scsi_setup_write_ext(pccb, start, smallblks); + blocks = blks; + scsi_setup_write_ext(pccb, start, blocks); start += blks; blks = 0; } - debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n", - __func__, start, smallblks, buf_addr); + debug("%s: startblk " LBAF ", blccnt " LBAF " buffer %lx\n", + __func__, start, blocks, buf_addr); if (scsi_exec(bdev, pccb)) { scsi_print_error(pccb); blkcnt -= blks; @@ -312,8 +309,8 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, if (scsi_exec(bdev, pccb)) scsi_print_error(pccb); - debug("%s: end startblk " LBAF ", blccnt %x buffer %lX\n", - __func__, start, smallblks, buf_addr); + debug("%s: end startblk " LBAF ", blccnt " LBAF " buffer %lX\n", + __func__, start, blocks, buf_addr); return blkcnt; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 589b526381f..1f2f2468eb0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -762,7 +762,7 @@ config MCFUART config MXC_UART bool "IMX serial port support" - depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M + depends on MX5 || MX6 || MX7 || IMX8M help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index 234b1688272..a84b257fb1a 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -16,6 +16,7 @@ #include <linux/delay.h> #include <linux/types.h> #include <linux/sizes.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -97,6 +98,8 @@ DECLARE_GLOBAL_DATA_PTR; #define REG_X4_TX_DATA (0x4c) #define REG_FRAMESUP (0x50) +#define MAX_CS_COUNT 1 + /** * struct mchp_coreqspi - Defines qspi driver instance * @regs: Address of the QSPI controller registers @@ -113,6 +116,7 @@ struct mchp_coreqspi { u8 *rxbuf; int tx_len; int rx_len; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; }; static void mchp_coreqspi_init_hw(struct mchp_coreqspi *qspi) @@ -172,7 +176,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word) while (qspi->tx_len >= 4) { while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) ; - data = *(u32 *)qspi->txbuf; + data = qspi->txbuf ? *((u32 *)qspi->txbuf) : 0xFF; qspi->txbuf += 4; qspi->tx_len -= 4; writel(data, qspi->regs + REG_X4_TX_DATA); @@ -184,7 +188,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word) while (qspi->tx_len--) { while (readl(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) ; - data = *qspi->txbuf++; + data = qspi->txbuf ? *qspi->txbuf++ : 0xFF; writel(data, qspi->regs + REG_TX_DATA); } } @@ -471,6 +475,110 @@ static int mchp_coreqspi_probe(struct udevice *dev) /* Init the mpfs qspi hw */ mchp_coreqspi_init_hw(qspi); + if (CONFIG_IS_ENABLED(DM_GPIO)) { + int i; + + ret = gpio_request_list_by_name(dev, "cs-gpios", qspi->cs_gpios, + ARRAY_SIZE(qspi->cs_gpios), 0); + + if (ret < 0) { + pr_err("Can't get %s gpios! Error: %d", dev->name, ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(qspi->cs_gpios); i++) { + if (!dm_gpio_is_valid(&qspi->cs_gpios[i])) + continue; + dm_gpio_set_dir_flags(&qspi->cs_gpios[i], GPIOD_IS_OUT); + } + } + + u32 control = readl(qspi->regs + REG_CONTROL); + + control |= (CONTROL_MASTER | CONTROL_ENABLE); + control &= ~CONTROL_CLKIDLE; + writel(control, qspi->regs + REG_CONTROL); + + return 0; +} + +static void mchp_coreqspi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct mchp_coreqspi *qspi = dev_get_priv(bus); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + u32 cs = slave_plat->cs[0]; + + if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&qspi->cs_gpios[cs])) + dm_gpio_set_value(&qspi->cs_gpios[cs], 1); +} + +static void mchp_coreqspi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct mchp_coreqspi *qspi = dev_get_priv(bus); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + u32 cs = slave_plat->cs[0]; + + if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&qspi->cs_gpios[cs])) + dm_gpio_set_value(&qspi->cs_gpios[cs], 0); +} + +static int mchp_coreqspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct mchp_coreqspi *qspi = dev_get_priv(bus); + struct spi_slave *slave = dev_get_parent_priv(dev); + uint total_bytes = bitlen >> 3; /* fixed 8-bit word length */ + u32 control, frames; + + int err = 0; + + err = mchp_coreqspi_wait_for_ready(slave); + if (err) + return err; + + control = readl(qspi->regs + REG_CONTROL); + control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0); + writel(control, qspi->regs + REG_CONTROL); + + frames = total_bytes & BYTESUPPER_MASK; + writel(frames, qspi->regs + REG_FRAMESUP); + + frames |= FRAMES_FLAGBYTE; + writel(frames, qspi->regs + REG_FRAMES); + + if (flags & SPI_XFER_BEGIN) + mchp_coreqspi_cs_activate(dev); + + if (bitlen == 0) + goto out; + + if (bitlen % 8) { // Non byte aligned SPI transfer + flags |= SPI_XFER_END; + goto out; + } + + qspi->txbuf = (u8 *)dout; + qspi->rxbuf = (u8 *)din; + + while (total_bytes) { + qspi->tx_len = 1; + qspi->rx_len = 1; + total_bytes--; + + if (din) { + mchp_coreqspi_write_op(qspi, true); + mchp_coreqspi_read_op(qspi); + } else { + mchp_coreqspi_write_op(qspi, true); + } + } +out: + if (flags & SPI_XFER_END) + mchp_coreqspi_cs_deactivate(dev); + return 0; } @@ -483,6 +591,7 @@ static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = { static const struct dm_spi_ops mchp_coreqspi_ops = { .claim_bus = mchp_coreqspi_claim_bus, .release_bus = mchp_coreqspi_release_bus, + .xfer = mchp_coreqspi_xfer, .set_speed = mchp_coreqspi_set_speed, .set_mode = mchp_coreqspi_set_mode, .mem_ops = &mchp_coreqspi_mem_ops, diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index 0ffc1b6444b..9e52ba8905c 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,7 +20,7 @@ config W1_GPIO config W1_MXC bool "Enable 1-wire controller on i.MX processors" - depends on ARCH_MX31 || ARCH_MX5 + depends on ARCH_MX5 help Support the one wire controller found in some members of the NXP i.MX SoC family. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 45eb9b4d3f9..e9ea874d0e3 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -27,7 +27,7 @@ config WATCHDOG_AUTOSTART config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" - default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SNAPDRAGON default 30000 if ARCH_SOCFPGA diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index adbb5aacdc3..4b972cff72c 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -63,10 +63,7 @@ int qcom_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) writel(bark_timeout_s, wdt_addr(wdt, WDT_BARK_TIME)); writel(bite_timeout_s, wdt_addr(wdt, WDT_BITE_TIME)); writel(BIT(0), wdt_addr(wdt, WDT_EN)); - if (readl(wdt_addr(wdt, WDT_EN)) != 1) { - dev_err(dev, "Failed to enable Qualcomm watchdog!\n"); - return -EIO; - } + return 0; } diff --git a/env/Kconfig b/env/Kconfig index c30785de48b..c667e8f2da1 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -759,6 +759,7 @@ config SCSI_ENV_PART_UUID config ENV_USE_DEFAULT_ENV_TEXT_FILE bool "Create default environment from file" + depends on !COMPILE_TEST help Normally, the default environment is automatically generated based on the settings of various CONFIG_* options, as well diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 5726981b19c..71b0b55b9c6 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -972,12 +972,10 @@ int __btrfs_map_block(struct btrfs_fs_info *fs_info, int rw, again: ce = search_cache_extent(&map_tree->cache_tree, logical); if (!ce) { - kfree(multi); *length = (u64)-1; return -ENOENT; } if (ce->start > logical) { - kfree(multi); *length = ce->start - logical; return -ENOENT; } diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c index dcdc883e34c..db86928511e 100644 --- a/fs/erofs/fs.c +++ b/fs/erofs/fs.c @@ -11,12 +11,15 @@ static struct erofs_ctxt { int erofs_dev_read(int device_id, void *buf, u64 offset, size_t len) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, len, buf)) return 0; diff --git a/fs/exfat/io.c b/fs/exfat/io.c index 77cd2dfb6dc..6c86688cd6c 100644 --- a/fs/exfat/io.c +++ b/fs/exfat/io.c @@ -442,12 +442,15 @@ off_t exfat_get_size(const struct exfat_dev* dev) ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size, off_t offset) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, size, buffer)) return 0; @@ -457,12 +460,15 @@ ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size, ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size, off_t offset) { - lbaint_t sect = offset >> ctxt.cur_dev->log2blksz; - int off = offset & (ctxt.cur_dev->blksz - 1); + lbaint_t sect; + int off; if (!ctxt.cur_dev) return -EIO; + sect = offset >> ctxt.cur_dev->log2blksz; + off = offset & (ctxt.cur_dev->blksz - 1); + if (fs_devwrite(ctxt.cur_dev, &ctxt.cur_part_info, sect, off, size, buffer)) return 0; @@ -473,43 +479,40 @@ ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size, ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node, void* buffer, size_t size, off_t offset) { - uint64_t uoffset = offset; cluster_t cluster; char* bufp = buffer; off_t lsize, loffset, remainder; - if (offset < 0) - return -EINVAL; - if (uoffset >= node->size) + if (offset >= node->size) return 0; if (size == 0) return 0; - if (uoffset + size > node->valid_size) + if (offset + size > node->valid_size) { ssize_t bytes = 0; - if (uoffset < node->valid_size) + if (offset < node->valid_size) { bytes = exfat_generic_pread(ef, node, buffer, - node->valid_size - uoffset, offset); - if (bytes < 0 || (size_t) bytes < node->valid_size - uoffset) + node->valid_size - offset, offset); + if (bytes < 0 || (size_t)bytes < node->valid_size - offset) return bytes; } memset(buffer + bytes, 0, MIN(size - bytes, node->size - node->valid_size)); - return MIN(size, node->size - uoffset); + return MIN(size, node->size - offset); } - cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb)); + cluster = exfat_advance_cluster(ef, node, offset / CLUSTER_SIZE(*ef->sb)); if (CLUSTER_INVALID(*ef->sb, cluster)) { exfat_error("invalid cluster 0x%x while reading", cluster); return -EIO; } - loffset = uoffset % CLUSTER_SIZE(*ef->sb); - remainder = MIN(size, node->size - uoffset); + loffset = offset % CLUSTER_SIZE(*ef->sb); + remainder = MIN(size, node->size - offset); while (remainder > 0) { if (CLUSTER_INVALID(*ef->sb, cluster)) @@ -531,43 +534,40 @@ ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node, } if (!(node->attrib & EXFAT_ATTRIB_DIR) && !ef->ro && !ef->noatime) exfat_update_atime(node); - return MIN(size, node->size - uoffset) - remainder; + return MIN(size, node->size - offset) - remainder; } ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, const void* buffer, size_t size, off_t offset) { - uint64_t uoffset = offset; int rc; cluster_t cluster; const char* bufp = buffer; off_t lsize, loffset, remainder; - if (offset < 0) - return -EINVAL; - if (uoffset > node->size) + if (offset > node->size) { - rc = exfat_truncate(ef, node, uoffset, true); + rc = exfat_truncate(ef, node, offset, true); if (rc != 0) return rc; } - if (uoffset + size > node->size) + if (offset + size > node->size) { - rc = exfat_truncate(ef, node, uoffset + size, false); + rc = exfat_truncate(ef, node, offset + size, false); if (rc != 0) return rc; } if (size == 0) return 0; - cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb)); + cluster = exfat_advance_cluster(ef, node, offset / CLUSTER_SIZE(*ef->sb)); if (CLUSTER_INVALID(*ef->sb, cluster)) { exfat_error("invalid cluster 0x%x while writing", cluster); return -EIO; } - loffset = uoffset % CLUSTER_SIZE(*ef->sb); + loffset = offset % CLUSTER_SIZE(*ef->sb); remainder = size; while (remainder > 0) { @@ -586,7 +586,7 @@ ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node, bufp += lsize; loffset = 0; remainder -= lsize; - node->valid_size = MAX(node->valid_size, uoffset + size - remainder); + node->valid_size = MAX(node->valid_size, offset + size - remainder); cluster = exfat_next_cluster(ef, node, cluster); } if (!(node->attrib & EXFAT_ATTRIB_DIR)) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index cc150cf824f..8e6531fa3f0 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -198,16 +198,18 @@ void put_ext4(uint64_t off, const void *buf, uint32_t size) uint64_t remainder; unsigned char *temp_ptr = NULL; struct ext_filesystem *fs = get_fs(); - int log2blksz = fs->dev_desc->log2blksz; + int log2blksz; + + if (!fs->dev_desc) + return; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, fs->dev_desc->blksz); + log2blksz = fs->dev_desc->log2blksz; startblock = off >> log2blksz; startblock += part_offset; remainder = off & (uint64_t)(fs->dev_desc->blksz - 1); - if (fs->dev_desc == NULL) - return; - if ((startblock + (size >> log2blksz)) > (part_offset + fs->total_sect)) { printf("part_offset is " LBAFU "\n", part_offset); diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index d109ed6e90d..dd8ed40f888 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -877,19 +877,19 @@ int ext4fs_write(const char *fname, const char *buffer, if (ext4fs_init() != 0) { printf("error in File System init\n"); - return -1; + goto fail; } missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP; if (missing_feat) { log_err("Unsupported features found %08x, not writing.\n", missing_feat); - return -1; + goto fail; } missing_feat = le32_to_cpu(fs->sb->feature_ro_compat) & ~EXT4_FEATURE_RO_COMPAT_SUPP; if (missing_feat) { log_err("Unsupported RO compat features found %08x, not writing.\n", missing_feat); - return -1; + goto fail; } inodes_per_block = fs->blksz / fs->inodesz; diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 9be99594f50..3c79a889bc2 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -277,7 +277,7 @@ int ext4fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) sizeof(struct ext2_dirent), (char *)&dirent, &actread); if (ret < 0) - return -ret; + return ret; if (!dirent.direntlen) return -EIO; diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 3a243d789c0..b6e6958599c 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -10,8 +10,7 @@ #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CFG_PRAM ((CONFIG_KM_PNVRAM + \ - CONFIG_KM_PHRAM + \ - CONFIG_KM_RESERVED_PRAM) >> 10) + CONFIG_KM_PHRAM) >> 10) #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e7ae18ec5f9..de41b998ea4 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -158,11 +158,10 @@ /****************************************************************************** * (PRAM usage) * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM + * ... |ROOTFSSIZE | PNVRAM |PHRAM | END_OF_RAM | * ... |<------------------- pram -------------------------->| * ... ------------------------------------------------------- * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose * @CONFIG_KM_PHRAM: address for /var * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 270088ad94f..5c0fd6d171b 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -38,6 +38,7 @@ enum uclass_id { /* U-Boot uclasses start here - in alphabetical order */ UCLASS_ACPI_PMC, /* (x86) Power-management controller (PMC) */ UCLASS_ADC, /* Analog-to-digital converter */ + UCLASS_AES, /* AES cryptographic engine */ UCLASS_AHCI, /* SATA disk controller */ UCLASS_AUDIO_CODEC, /* Audio codec with control and data path */ UCLASS_AXI, /* AXI bus */ diff --git a/include/env/pg-wcom/ls102xa.env b/include/env/pg-wcom/ls102xa.env index abbec424574..88aaac8f008 100644 --- a/include/env/pg-wcom/ls102xa.env +++ b/include/env/pg-wcom/ls102xa.env @@ -8,7 +8,6 @@ checkfdt=true cramfsloadfdt=cramfsload $fdt_addr_r fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb ethrotate=no hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,asrc,spdif,lpuart1,ftm1 -netdev=eth2 newenv=protect off CONFIG_ENV_ADDR_REDUND +0x40000 && erase CONFIG_ENV_ADDR_REDUND +0x40000 && diff --git a/include/env/ti/ti_armv7_keystone2.env b/include/env/ti/ti_armv7_keystone2.env index e0395d302cb..1b2aaa2808a 100644 --- a/include/env/ti/ti_armv7_keystone2.env +++ b/include/env/ti/ti_armv7_keystone2.env @@ -12,6 +12,7 @@ dfu_alt_info_mmc= uEnv.txt fat 0 1 bootdir=/boot +bootm_size=0x10000000 tftp_root=/ nfs_root=/export mem_lpae=1 diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index 7029d12bf20..03e3267ef8a 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -8,7 +8,6 @@ rdaddr=0x88080000 ramdisk_addr_r=0x88080000 scriptaddr=0x80000000 pxefile_addr_r=0x80100000 -bootm_size=0x10000000 boot_fdt=try boot_fit=0 diff --git a/include/fb_spi_flash.h b/include/fb_spi_flash.h new file mode 100644 index 00000000000..904654748a4 --- /dev/null +++ b/include/fb_spi_flash.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 Collabora Ltd. + */ + +#ifndef _FB_SPI_FLASH_H_ +#define _FB_SPI_FLASH_H_ + +#include <part.h> + +/** + * fastboot_spi_flash_get_part_info() - Lookup SPI flash partition by name + * + * @part_name: Named device to lookup + * @part_info: Pointer to returned struct disk_partition + * @response: Pointer to fastboot response buffer + * Return: 0 if OK, -ENOENT if no partition name was given, -ENODEV on invalid + * raw partition descriptor + */ +int fastboot_spi_flash_get_part_info(const char *part_name, + struct disk_partition *part_info, + char *response); + +/** + * fastboot_spi_flash_write() - Write image to SPI flash for fastboot + * + * @cmd: Named device to write image to + * @download_buffer: Pointer to image data + * @download_bytes: Size of image data + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_write(const char *cmd, void *download_buffer, + u32 download_bytes, char *response); + +/** + * fastboot_spi_flash_erase() - Erase SPI flash for fastboot + * + * @cmd: Named device to erase + * @response: Pointer to fastboot response buffer + */ +void fastboot_spi_flash_erase(const char *cmd, char *response); +#endif diff --git a/include/imx8image.h b/include/imx8image.h index e0d25c5b6c9..d0e05811ff9 100644 --- a/include/imx8image.h +++ b/include/imx8image.h @@ -45,6 +45,7 @@ #define DCD_ENTRY_ADDR_IN_SCFW 0x240 #define CONTAINER_ALIGNMENT 0x400 +#define CONTAINER_PQC_ALIGNMENT 0x4000 #define CONTAINER_FLAGS_DEFAULT 0x10 #define CONTAINER_FUSE_DEFAULT 0x0 @@ -160,6 +161,8 @@ enum imx8image_cmd { CMD_DATA, CMD_DUMMY_V2X, CMD_HOLD, + CMD_CNTR_VERSION, + CMD_DUMMY_DDR, }; enum imx8image_core_type { @@ -216,6 +219,8 @@ typedef enum option_type { OEI, DUMMY_V2X, HOLD, + CNTR_VERSION, + DUMMY_DDR, } option_type_t; typedef struct { @@ -262,6 +267,7 @@ typedef struct { #define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */ #define IMG_TYPE_PROV 0x07 /* Provisioning image type */ #define IMG_TYPE_DEK 0x08 /* DEK validation type */ +#define IMG_TYPE_DDR_DUMMY 0x0D /* DDR training data dummy entry */ #define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */ #define IMG_TYPE_SHIFT 0 diff --git a/include/imx_container.h b/include/imx_container.h index 691c764b3e5..684fc3bc988 100644 --- a/include/imx_container.h +++ b/include/imx_container.h @@ -12,7 +12,11 @@ #define IV_MAX_LEN 32 #define HASH_MAX_LEN 64 +#if IS_ENABLED(CONFIG_IMX_PQC_SUPPORT) +#define CONTAINER_HDR_ALIGNMENT 0x4000 +#else #define CONTAINER_HDR_ALIGNMENT 0x400 +#endif #define CONTAINER_HDR_EMMC_OFFSET 0 #define CONTAINER_HDR_MMCSD_OFFSET SZ_32K #define CONTAINER_HDR_QSPI_OFFSET SZ_4K @@ -72,7 +76,14 @@ int get_container_size(ulong addr, u16 *header_length); static inline bool valid_container_hdr(struct container_hdr *container) { +#if IS_ENABLED(CONFIG_IMX_PQC_SUPPORT) + return (container->tag == CONTAINER_HDR_TAG || + container->tag == 0x82) && + (container->version == CONTAINER_HDR_VERSION || + container->version == 0x2); +#else return container->tag == CONTAINER_HDR_TAG && container->version == CONTAINER_HDR_VERSION; +#endif } #endif diff --git a/include/limits.h b/include/limits.h index 1d0bbf69be7..a032bc5b84d 100644 --- a/include/limits.h +++ b/include/limits.h @@ -3,11 +3,61 @@ #ifndef _LIMITS_H #define _LIMITS_H -#define INT_MAX 0x7fffffff -#define UINT_MAX 0xffffffffU +#define SCHAR_MAX __SCHAR_MAX__ +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define UCHAR_MAX (SCHAR_MAX * 2 + 1) + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MAX UCHAR_MAX +#define CHAR_MIN 0 +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif + +#define SHRT_MAX __SHRT_MAX__ +#define SHRT_MIN (-SHRT_MAX - 1) +#define USHRT_MAX (SHRT_MAX * 2 + 1) + +#define INT_MAX __INT_MAX__ +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (INT_MAX * 2U + 1U) + +#define LONG_MAX __LONG_MAX__ +#define LONG_MIN (-LONG_MAX - 1L) +#define ULONG_MAX (LONG_MAX * 2UL + 1UL) + +#define LLONG_MAX __LONG_LONG_MAX__ +#define LLONG_MIN (-LLONG_MAX - 1LL) +#define ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL) + +#define U8_MAX UCHAR_MAX +#define S8_MAX SCHAR_MAX +#define S8_MIN SCHAR_MIN +#define U16_MAX USHRT_MAX +#define S16_MAX SHRT_MAX +#define S16_MIN SHRT_MIN +#define U32_MAX UINT_MAX +#define S32_MAX INT_MAX +#define S32_MIN INT_MIN +#define U64_MAX ULLONG_MAX +#define S64_MAX LLONG_MAX +#define S64_MIN LLONG_MIN + +#define UINT8_MAX U8_MAX +#define INT8_MAX S8_MAX +#define INT8_MIN S8_MIN +#define UINT16_MAX U16_MAX +#define INT16_MAX S16_MAX +#define INT16_MIN S16_MIN +#define UINT32_MAX U32_MAX +#define INT32_MAX S32_MAX +#define INT32_MIN S32_MIN +#define UINT64_MAX U64_MAX +#define INT64_MAX S64_MAX +#define INT64_MIN S64_MIN + #define CHAR_BIT 8 -#define UINT32_MAX 0xffffffffU -#define UINT64_MAX 0xffffffffffffffffULL #if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD)) diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 9467edd65ab..e0443ecac84 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -5,32 +5,6 @@ #include <linux/printk.h> /* for printf/pr_* utilities */ #include <limits.h> -#define USHRT_MAX ((u16)(~0U)) -#define SHRT_MAX ((s16)(USHRT_MAX>>1)) -#define SHRT_MIN ((s16)(-SHRT_MAX - 1)) -#define INT_MIN (-INT_MAX - 1) -#define LONG_MAX ((long)(~0UL>>1)) -#define LONG_MIN (-LONG_MAX - 1) -#define ULONG_MAX (~0UL) -#define LLONG_MAX ((long long)(~0ULL>>1)) -#define LLONG_MIN (-LLONG_MAX - 1) -#define ULLONG_MAX (~0ULL) - -#define U8_MAX ((u8)~0U) -#define S8_MAX ((s8)(U8_MAX>>1)) -#define S8_MIN ((s8)(-S8_MAX - 1)) -#define U16_MAX ((u16)~0U) -#define S16_MAX ((s16)(U16_MAX>>1)) -#define S16_MIN ((s16)(-S16_MAX - 1)) -#define U32_MAX ((u32)~0U) -#define S32_MAX ((s32)(U32_MAX>>1)) -#define S32_MIN ((s32)(-S32_MAX - 1)) -#define U64_MAX ((u64)~0ULL) -#define S64_MAX ((s64)(U64_MAX>>1)) -#define S64_MIN ((s64)(-S64_MAX - 1)) - -#define INT32_MAX S32_MAX - #define STACK_MAGIC 0xdeadbeef #define REPEAT_BYTE(x) ((~0ul / 0xff) * (x)) diff --git a/include/stdint.h b/include/stdint.h index dea83c8226a..90fd2bdee08 100644 --- a/include/stdint.h +++ b/include/stdint.h @@ -9,6 +9,6 @@ #ifndef __UB_STDINT_H #define __UB_STDINT_H -#define UINT8_MAX 0xff +#include <limits.h> #endif diff --git a/include/uboot_aes.h b/include/uboot_aes.h index d2583bed992..592b7dbee43 100644 --- a/include/uboot_aes.h +++ b/include/uboot_aes.h @@ -7,6 +7,8 @@ #ifndef _AES_REF_H_ #define _AES_REF_H_ +#include <errno.h> + #ifdef USE_HOSTCC /* Define compat stuff for use in fw_* tools. */ typedef unsigned char u8; @@ -107,4 +109,253 @@ void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); +/* An AES block filled with zeros */ +static const u8 AES_ZERO_BLOCK[AES_BLOCK_LENGTH] = { 0 }; +struct udevice; + +/** + * struct struct aes_ops - Driver model for AES related operations + * + * The uclass interface is implemented by AES crypto devices which use driver model. + * + * Some AES crypto devices use key slots to store the key for the encrypt/decrypt + * operations, while others may simply pass the key on each operation. + * + * In case the device does not implement hardware slots, driver can emulate or simply + * store one active key slot at 0 in the driver state and pass it on each underlying + * hw calls for AES operations. + * + * Note that some devices like Tegra AES engine may contain preloaded keys by bootrom, + * thus in those cases the set_key_for_key_slot() may be skipped. + * + * Sequence for a series of AES CBC encryption, one decryption and a CMAC hash example + * with 128bits key at slot 0 would be as follow: + * + * set_key_for_key_slot(DEV, 128, KEY, 0); + * select_key_slot(DEV, 128, 0); + * aes_cbc_encrypt(DEV, IV1, SRC1, DST1, LEN1); + * aes_cbc_encrypt(DEV, IV2, SRC2, DST2, LEN2); + * aes_cbc_decrypt(DEV, IV3, SRC3, DST3, LEN3); + */ +struct aes_ops { + /** + * available_key_slots() - How many key slots this AES device has + * + * @dev The AES udevice + * @return Available slots to use, 0 for none + */ + int (*available_key_slots)(struct udevice *dev); + + /** + * select_key_slot() - Selects the AES key slot to use for following operations + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @slot The key slot to set as selected + * @return 0 on success, negative value on failure + */ + int (*select_key_slot)(struct udevice *dev, u32 key_size, u8 slot); + + /** + * set_key_for_key_slot() - Sets the AES key to use for specified key slot + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @key An AES key to set + * @slot The slot to load the key at + * @return 0 on success, negative value on failure + */ + int (*set_key_for_key_slot)(struct udevice *dev, u32 key_size, u8 *key, + u8 slot); + + /** + * aes_ecb_encrypt() - Encrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_ecb_encrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_ecb_decrypt() - Decrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_ecb_decrypt)(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_cbc_encrypt() - Encrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_cbc_encrypt)(struct udevice *dev, u8 *iv, + u8 *src, u8 *dst, u32 num_aes_blocks); + + /** + * aes_cbc_decrypt() - Decrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * @return 0 on success, negative value on failure + */ + int (*aes_cbc_decrypt)(struct udevice *dev, u8 *iv, + u8 *src, u8 *dst, u32 num_aes_blocks); +}; + +#define aes_get_ops(dev) ((struct aes_ops *)(dev)->driver->ops) + +#if CONFIG_IS_ENABLED(DM_AES) + +/** + * dm_aes_get_available_key_slots - How many key slots this AES device has + * + * @dev The AES udevice + * Return: Available slots to use, 0 for none, -ve on failure + */ +int dm_aes_get_available_key_slots(struct udevice *dev); + +/** + * dm_aes_select_key_slot - Selects the AES key slot to use for following operations + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @slot The key slot to set as selected + * Return: 0 on success, -ve on failure + */ +int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot); + +/** + * dm_aes_set_key_for_key_slot - Sets the AES key to use for specified key slot + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @key An AES key to set + * @slot The slot to load the key at + * Return: 0 on success, negative value on failure + */ +int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, u8 slot); + +/** + * dm_aes_ecb_encrypt - Encrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_ecb_decrypt - Decrypt multiple blocks of data with AES ECB. + * + * @dev The AES udevice + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cbc_encrypt - Encrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cbc_decrypt - Decrypt multiple blocks of data with AES CBC. + * + * @dev The AES udevice + * @iv Initialization vector + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination data of length 'num_aes_blocks' blocks + * @num_aes_blocks Number of AES blocks to encrypt/decrypt + * Return: 0 on success, negative value on failure + */ +int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, u8 *dst, u32 num_aes_blocks); + +/** + * dm_aes_cmac - Hashes the input data with AES-CMAC, putting the result into dst. + * The key slot must be selected already. + * + * @dev The AES udevice + * @key_size Size of the aes key (in bits) + * @src Source data of length 'num_aes_blocks' blocks + * @dst Destination for hash result + * @num_aes_blocks Number of AES blocks to encrypt + * Return: 0 on success, negative value on failure. + */ +int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks); + +#else + +static inline int dm_aes_get_available_key_slots(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int dm_aes_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + return -ENOSYS; +} + +static inline int dm_aes_set_key_for_key_slot(struct udevice *dev, u32 key_size, u8 *key, + u8 slot) +{ + return -ENOSYS; +} + +static inline int dm_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +static inline int dm_aes_cmac(struct udevice *dev, u8 *src, u8 *dst, u32 num_aes_blocks) +{ + return -ENOSYS; +} + +#endif /* CONFIG_DM_AES */ + #endif /* _AES_REF_H_ */ diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c index 7415d685ee1..c4bfb2cec61 100644 --- a/lib/ecdsa/ecdsa-libcrypto.c +++ b/lib/ecdsa/ecdsa-libcrypto.c @@ -519,10 +519,12 @@ static int do_add(struct signer *ctx, void *fdt, const char *key_node_name, if (ret < 0) return ret; - ret = fdt_setprop_string(fdt, key_node, FIT_KEY_REQUIRED, - info->require_keys); - if (ret < 0) - return ret; + if (info->require_keys) { + ret = fdt_setprop_string(fdt, key_node, FIT_KEY_REQUIRED, + info->require_keys); + if (ret < 0) + return ret; + } return key_node; } diff --git a/lib/lmb.c b/lib/lmb.c index e5a0677e3f9..e2d9fe86c14 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -8,6 +8,7 @@ #include <alist.h> #include <efi_loader.h> +#include <env.h> #include <event.h> #include <image.h> #include <mapmem.h> @@ -214,8 +215,6 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, coalesced++; break; - - return -1; } } @@ -538,6 +537,7 @@ static void lmb_reserve_uboot_region(void) int bank; ulong end, bank_end; phys_addr_t rsv_start; + ulong pram = 0; rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE; end = gd->ram_top; @@ -548,6 +548,11 @@ static void lmb_reserve_uboot_region(void) */ debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start); +#ifdef CFG_PRAM + pram = env_get_ulong("pram", 10, CFG_PRAM); + pram = pram << 10; /* size is in kB */ +#endif + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { if (!gd->bd->bi_dram[bank].size || rsv_start < gd->bd->bi_dram[bank].start) @@ -560,7 +565,8 @@ static void lmb_reserve_uboot_region(void) if (bank_end > end) bank_end = end - 1; - lmb_reserve(rsv_start, bank_end - rsv_start + 1, LMB_NOOVERWRITE); + lmb_reserve(rsv_start, bank_end - rsv_start - pram + 1, + LMB_NOOVERWRITE); if (gd->flags & GD_FLG_SKIP_RELOC) lmb_reserve((phys_addr_t)(uintptr_t)_start, diff --git a/test/dm/Makefile b/test/dm/Makefile index 917dafe7d22..d15859eca30 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -29,6 +29,7 @@ obj-(CONFIG_DM_GPIO) += gpio.o obj-y += irq.o endif obj-$(CONFIG_ADC) += adc.o +obj-$(CONFIG_AES_SOFTWARE) += aes.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_AXI) += axi.o obj-$(CONFIG_BLK) += blk.o diff --git a/test/dm/aes.c b/test/dm/aes.c new file mode 100644 index 00000000000..702e4db2b35 --- /dev/null +++ b/test/dm/aes.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for the driver model AES API + * + * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/test.h> +#include <uboot_aes.h> +#include <test/test.h> +#include <test/ut.h> + +#define AES128_KEYSIZE 128 + +static int dm_test_aes(struct unit_test_state *uts) +{ + struct udevice *dev; + u8 test_key[AES128_KEY_LENGTH] = { 0x63, 0x68, 0x69, 0x63, 0x6b, 0x65, 0x6e, 0x20, + 0x74, 0x65, 0x72, 0x69, 0x79, 0x61, 0x6b, 0x69 }; + u8 test_iv[AES128_KEY_LENGTH] = { 0 }; + + u8 test_input[AES_BLOCK_LENGTH] = { 0x49, 0x20, 0x77, 0x6f, 0x75, 0x6c, 0x64, 0x20, + 0x6c, 0x69, 0x6b, 0x65, 0x20, 0x74, 0x68, 0x65 }; + u8 exp_output[AES_BLOCK_LENGTH] = { 0x97, 0x68, 0x72, 0x68, 0xd6, 0xec, 0xcc, 0xc0, + 0xc0, 0x7b, 0x25, 0xe2, 0x5e, 0xcf, 0xe5, 0x84 }; + u8 exp_cmac[AES_BLOCK_LENGTH] = { 0xfc, 0x89, 0x20, 0xc8, 0x46, 0x97, 0xb1, 0x3d, + 0x31, 0x2c, 0xc2, 0x49, 0x5c, 0x5a, 0x0b, 0x9f }; + u8 test_output[AES_BLOCK_LENGTH]; + + ut_assertok(uclass_first_device_err(UCLASS_AES, &dev)); + + /* software AES exposes 2 key slots */ + ut_asserteq(2, dm_aes_get_available_key_slots(dev)); + + ut_assertok(dm_aes_select_key_slot(dev, AES128_KEYSIZE, 0)); + ut_assertok(dm_aes_set_key_for_key_slot(dev, AES128_KEYSIZE, test_key, 0)); + + ut_assertok(dm_aes_ecb_encrypt(dev, test_input, test_output, 1)); + ut_assertok(memcmp(exp_output, test_output, 16)); + + ut_assertok(dm_aes_ecb_decrypt(dev, test_output, test_output, 1)); + ut_assertok(memcmp(test_input, test_output, 16)); + + ut_assertok(dm_aes_cbc_encrypt(dev, test_iv, test_input, test_output, 1)); + ut_assertok(memcmp(exp_output, test_output, 16)); + + ut_assertok(dm_aes_cbc_decrypt(dev, test_iv, test_output, test_output, 1)); + ut_assertok(memcmp(test_input, test_output, 16)); + + ut_assertok(dm_aes_cmac(dev, test_input, test_output, 1)); + ut_assertok(memcmp(exp_cmac, test_output, 16)); + + return 0; +} + +DM_TEST(dm_test_aes, UTF_SCAN_FDT); diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py index 5879f377231..9cc4b756b3f 100644 --- a/tools/binman/etype/cbfs.py +++ b/tools/binman/etype/cbfs.py @@ -5,6 +5,7 @@ # Entry-type module for a Coreboot Filesystem (CBFS) # +from __future__ import annotations from collections import OrderedDict from binman import cbfs_util diff --git a/tools/binman/etype/mkimage.py b/tools/binman/etype/mkimage.py index 75e59c3d3a3..9fba902bdad 100644 --- a/tools/binman/etype/mkimage.py +++ b/tools/binman/etype/mkimage.py @@ -5,6 +5,7 @@ # Entry-type module for producing an image using mkimage # +from __future__ import annotations from collections import OrderedDict from binman.entry import Entry diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py index 03c4f7c6ec7..6a26d687056 100644 --- a/tools/binman/etype/section.py +++ b/tools/binman/etype/section.py @@ -8,6 +8,7 @@ Sections are entries which can contain other entries. This allows hierarchical images to be created. """ +from __future__ import annotations from collections import OrderedDict import concurrent.futures import re diff --git a/tools/bmp_logo.c b/tools/bmp_logo.c index 74fcadca63e..40213b7887f 100644 --- a/tools/bmp_logo.c +++ b/tools/bmp_logo.c @@ -15,7 +15,7 @@ typedef struct bitmap_s { /* bitmap description */ #define DEFAULT_CMAP_SIZE 16 /* size of default color map */ -void usage(const char *prog) +static void usage(const char *prog) { fprintf(stderr, "Usage: %s [--gen-info|--gen-data|--gen-bmp] file\n", prog); @@ -24,7 +24,7 @@ void usage(const char *prog) /* * Neutralize little endians. */ -uint16_t le_short(uint16_t x) +static uint16_t le_short(uint16_t x) { uint16_t val; uint8_t *p = (uint8_t *)(&x); @@ -35,14 +35,14 @@ uint16_t le_short(uint16_t x) return val; } -void skip_bytes (FILE *fp, int n) +static void skip_bytes(FILE *fp, int n) { while (n-- > 0) fgetc (fp); } __attribute__ ((__noreturn__)) -int error (char * msg, FILE *fp) +static int error(char *msg, FILE *fp) { fprintf (stderr, "ERROR: %s\n", msg); @@ -51,7 +51,7 @@ int error (char * msg, FILE *fp) exit (EXIT_FAILURE); } -void gen_info(bitmap_t *b, uint16_t n_colors) +static void gen_info(bitmap_t *b, uint16_t n_colors) { printf("/*\n" " * Automatically generated by \"tools/bmp_logo\"\n" diff --git a/tools/fit_image.c b/tools/fit_image.c index 8717dc9a3b1..ad0ffa39c6a 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -846,7 +846,7 @@ static int fit_handle_file(struct image_tool_params *params) char tmpfile[MKIMAGE_MAX_TMPFILE_LEN]; char bakfile[MKIMAGE_MAX_TMPFILE_LEN + 4] = {0}; char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN]; - size_t size_inc; + int size_inc; int ret = EXIT_FAILURE; /* Flattened Image Tree (FIT) format handling */ diff --git a/tools/gen_ethaddr_crc.c b/tools/gen_ethaddr_crc.c index e73d0429a04..27717207580 100644 --- a/tools/gen_ethaddr_crc.c +++ b/tools/gen_ethaddr_crc.c @@ -16,12 +16,12 @@ #define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1) /* with separators */ #define ARP_HLEN_LAZY (ARP_HLEN * 2) /* separatorless hardware address length */ -uint8_t nibble_to_hex(const char *nibble, bool lo) +static uint8_t nibble_to_hex(const char *nibble, bool lo) { return (strtol(nibble, NULL, 16) << (lo ? 0 : 4)) & (lo ? 0x0f : 0xf0); } -int process_mac(const char *mac_address) +static int process_mac(const char *mac_address) { uint8_t ethaddr[ARP_HLEN + 1] = { 0x00 }; uint_fast8_t i = 0; @@ -45,7 +45,7 @@ int process_mac(const char *mac_address) return 0; } -void print_usage(char *cmdname) +static void print_usage(char *cmdname) { printf("Usage: %s <mac_address>\n", cmdname); puts("<mac_address> may be with or without separators."); diff --git a/tools/imx8image.c b/tools/imx8image.c index cad55fd3cf2..5a76643c06e 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -19,6 +19,7 @@ static bool dcd_skip; static image_t param_stack[IMG_STACK_SIZE]; static uint8_t fuse_version; static uint16_t sw_version; +static uint8_t cntr_version; static uint32_t custom_partition; static uint32_t scfw_flags; @@ -57,6 +58,8 @@ static table_entry_t imx8image_cmds[] = { {CMD_DATA, "DATA", "new data", }, {CMD_DUMMY_V2X, "DUMMY_V2X", "v2x", }, {CMD_HOLD, "HOLD", "hold", }, + {CMD_CNTR_VERSION, "CNTR_VERSION", "cntr version", }, + {CMD_DUMMY_DDR, "DUMMY_DDR", "ddr", }, {-1, "", "", } }; @@ -157,6 +160,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t cmd, char *token, param_stack[p_idx].option = HOLD; param_stack[p_idx].entry = (uint32_t)strtoll(token, NULL, 0); param_stack[p_idx++].filename = NULL; + break; + case CMD_CNTR_VERSION: + cntr_version = (uint8_t)(strtoll(token, NULL, 0) & 0xFF); + break; default: break; } @@ -177,6 +184,8 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token, if (*cmd == CMD_CONTAINER) { fprintf(stdout, "New Container: \t%d\n", ++container); param_stack[p_idx++].option = NEW_CONTAINER; + } else if (*cmd == CMD_DUMMY_DDR) { + param_stack[p_idx++].option = DUMMY_DDR; } break; case CFG_CORE_TYPE: @@ -588,7 +597,8 @@ static void set_image_array_entry(flash_header_v3_t *container, img->offset = offset; /* Is re-adjusted later */ img->size = size; - if (type != DUMMY_V2X) { + /* skip hash generation here if dummy image */ + if (type != DUMMY_V2X && type != DUMMY_DDR) { set_image_hash(img, tmp_filename, IMAGE_HASH_ALGO_DEFAULT); } @@ -632,6 +642,15 @@ static void set_image_array_entry(flash_header_v3_t *container, img->entry = entry; img->meta = meta; custom_partition = 0; + + if (container->num_images) { + /* if at least 2 images in container, [0] and [1] */ + boot_img_t *ddr_dummy = &container->img[container->num_images - 1]; + if ((ddr_dummy->hab_flags & 0x0F) == IMG_TYPE_DDR_DUMMY) { + ddr_dummy->offset = img->offset + img->size; + set_image_hash(ddr_dummy, "/dev/null", IMAGE_HASH_ALGO_DEFAULT); + } + } break; case AP: if (soc == QX && core == CORE_CA35) { @@ -751,6 +770,11 @@ static void set_image_array_entry(flash_header_v3_t *container, img->entry = entry; img->size = 0; /* dummy image has no size */ break; + case DUMMY_DDR: + img->hab_flags |= IMG_TYPE_DDR_DUMMY; + tmp_name = "DDR Dummy"; + img->size = 0; /* dummy image has no size */ + break; default: fprintf(stderr, "unrecognized image type (%d)\n", type); exit(EXIT_FAILURE); @@ -776,22 +800,27 @@ void set_container(flash_header_v3_t *container, uint16_t sw_version, static int get_container_image_start_pos(image_t *image_stack, uint32_t align, uint32_t *v2x) { image_t *img_sp = image_stack; - /*8K total container header*/ - int file_off = CONTAINER_IMAGE_ARRAY_START_OFFSET; + /* + * 8K total container header for legacy container, for version 2 + * container, the total container header is 0x4000 * 3 = 0xC000. + */ + int file_off = cntr_version ? 0xC000 : CONTAINER_IMAGE_ARRAY_START_OFFSET; + size_t size = cntr_version ? SZ_32K : SZ_4K; + uint32_t cntr_header_len = cntr_version ? CONTAINER_PQC_ALIGNMENT : FIRST_CONTAINER_HEADER_LENGTH; FILE *fd = NULL; flash_header_v3_t *header; flash_header_v3_t *header2; void *p; int ret; - p = calloc(1, SZ_4K); + p = calloc(1, size); if (!p) { - fprintf(stderr, "Fail to alloc 4K memory\n"); + fprintf(stderr, "Fail to alloc %lx memory\n", size); exit(EXIT_FAILURE); } header = p; - header2 = p + FIRST_CONTAINER_HEADER_LENGTH; + header2 = p + cntr_header_len; while (img_sp->option != NO_IMG) { if (img_sp->option == APPEND) { @@ -801,7 +830,7 @@ static int get_container_image_start_pos(image_t *image_stack, uint32_t align, u exit(EXIT_FAILURE); } - ret = fread(header, SZ_4K, 1, fd); + ret = fread(header, size, 1, fd); if (ret != 1) { printf("Failure Read header %d\n", ret); exit(EXIT_FAILURE); @@ -813,11 +842,11 @@ static int get_container_image_start_pos(image_t *image_stack, uint32_t align, u fprintf(stderr, "header tag mismatched \n"); exit(EXIT_FAILURE); } else { - if (header2->tag != IVT_HEADER_TAG_B0) { + if ((header2->tag != IVT_HEADER_TAG_B0) && (header2->tag != 0x82)) { file_off += header->img[header->num_images - 1].size; file_off = ALIGN(file_off, align); } else { - file_off = header2->img[header2->num_images - 1].offset + FIRST_CONTAINER_HEADER_LENGTH; + file_off = header2->img[header2->num_images - 1].offset + cntr_header_len; file_off += header2->img[header2->num_images - 1].size; file_off = ALIGN(file_off, align); fprintf(stderr, "Has 2nd container %x\n", file_off); @@ -839,7 +868,7 @@ static void set_imx_hdr_v3(imx_header_v3_t *imxhdr, uint32_t cont_id) /* Set magic number, Only >= B0 supported */ fhdr_v3->tag = IVT_HEADER_TAG_B0; - fhdr_v3->version = IVT_VERSION_B0; + fhdr_v3->version = cntr_version ? 0x2 : IVT_VERSION_B0; } static uint8_t *flatten_container_header(imx_header_v3_t *imx_header, @@ -921,6 +950,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, char *tmp_filename = NULL; uint32_t size = 0; uint32_t file_padding = 0; + uint32_t cntr_header_len = cntr_version ? CONTAINER_PQC_ALIGNMENT : FIRST_CONTAINER_HEADER_LENGTH; uint32_t v2x = false; int ret; @@ -978,6 +1008,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, break; case DUMMY_V2X: + case DUMMY_DDR: if (container < 0) { fprintf(stderr, "No container found\n"); exit(EXIT_FAILURE); @@ -1023,7 +1054,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size, case NEW_CONTAINER: container++; set_container(&imx_header.fhdr[container], sw_version, - CONTAINER_ALIGNMENT, + cntr_version ? CONTAINER_PQC_ALIGNMENT : CONTAINER_ALIGNMENT, CONTAINER_FLAGS_DEFAULT, fuse_version); scfw_flags = 0; @@ -1073,9 +1104,9 @@ static int build_container(soc_type_t soc, uint32_t sector_size, if (img_sp->option == APPEND) { copy_file(ofd, img_sp->filename, 0, 0); if (v2x) - file_padding += FIRST_CONTAINER_HEADER_LENGTH * 2; + file_padding += cntr_header_len * 2; else - file_padding += FIRST_CONTAINER_HEADER_LENGTH; + file_padding += cntr_header_len; } img_sp++; } while (img_sp->option != NO_IMG); diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index 885cdb1390e..944ec82e761 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -47,7 +47,7 @@ static void usage(const char *exec_name) exec_name); } -long int xstrtol(const char *s) +static long int xstrtol(const char *s) { long int tmp; diff --git a/tools/patman/requirements.txt b/tools/patman/requirements.txt index ce9a3854527..d4fcb1061c2 100644 --- a/tools/patman/requirements.txt +++ b/tools/patman/requirements.txt @@ -1,6 +1,6 @@ -aiohttp==3.9.1 +aiohttp==3.10.11 ConfigParser==7.1.0 importlib_resources==6.5.2 pygit2==1.14.1 -Requests==2.32.3 -setuptools==75.8.0 +requests==2.32.4 +setuptools==78.1.1 diff --git a/tools/ublimage.c b/tools/ublimage.c index a1bd807bfa0..8926d5b178b 100644 --- a/tools/ublimage.c +++ b/tools/ublimage.c @@ -219,7 +219,7 @@ static void ublimage_set_header(void *ptr, struct stat *sbuf, int ifd, parse_cfg_file(ublhdr, params->imagename); } -int ublimage_check_params(struct image_tool_params *params) +static int ublimage_check_params(struct image_tool_params *params) { if (!params) return CFG_INVALID; |