diff options
557 files changed, 10447 insertions, 36941 deletions
diff --git a/.gitignore b/.gitignore index d9a64d742fd..be137040a2c 100644 --- a/.gitignore +++ b/.gitignore @@ -64,6 +64,9 @@ fit-dtb.blob* /tpl/ /defconfig /generated_defconfig +/Test* +/capsule.*.efi-capsule +/capsule*.map # # Generated include files @@ -30,6 +30,7 @@ Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com> Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com> Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com> +Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org> Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> @@ -715,6 +715,20 @@ config SYS_CLK_FREQ A static value for the CPU frequency. Note that if not required for a given SoC, this can be left at 0. +config HAS_LDR + bool + help + Enables building .ldr targets for U-Boot and SPL. This does not + automatically build any additional targets with make or buildman. + +config LDR_CPU + string "CPU name to be passed to LDR utility." + depends on HAS_LDR + help + Set the CPU name for the -T parameter in the LDR utility. This is + generally used on processors from Analog Devices, but may be also + be useful for other vendors. + source "api/Kconfig" endmenu # General setup @@ -1360,7 +1360,7 @@ u-boot-nodtb.bin: u-boot FORCE u-boot.ldr: u-boot $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) # binman @@ -1963,6 +1963,7 @@ define filechk_version.h echo \#define U_BOOT_VERSION_NUM $(VERSION); \ echo \#define U_BOOT_VERSION_NUM_PATCH $$(echo $(PATCHLEVEL) | \ sed -e "s/^0*//"); \ + echo \#define HOST_ARCH $(HOST_ARCH); \ echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \ echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; ) endef @@ -2199,7 +2200,8 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \ mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \ itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \ mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \ - idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb + idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \ + Test* capsule.*.efi-capsule capsule*.map # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl vpl \ diff --git a/arch/Kconfig b/arch/Kconfig index f9aaf372478..abd406d4884 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -254,7 +254,6 @@ config X86 imply CMD_PCI imply CMD_SF imply CMD_SF_TEST - imply CMD_ZBOOT imply DM_GPIO imply DM_KEYBOARD imply DM_MMC diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index 0eb44bcf33d..bde1c3d8af3 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -12,6 +12,6 @@ obj-y += reset.o obj-y += ints_low.o obj-y += init_helpers.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e19330..23ee25269a2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1078,6 +1078,7 @@ config ARCH_SNAPDRAGON select DM_GPIO select DM_SERIAL select DM_RESET + select POWER_DOMAIN select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL @@ -1320,6 +1321,14 @@ config ARCH_ZYNQMP select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_MAILBOX if SPL imply SPL_FIRMWARE if SPL + imply SPL_FS_FAT if SPL + imply SPL_LIBCOMMON_SUPPORT if SPL + imply SPL_LIBDISK_SUPPORT if SPL + imply SPL_LIBGENERIC_SUPPORT if SPL + imply SPL_MMC if SPL && MMC_SDHCI_ZYNQ + imply SPL_SERIAL if SPL + imply SPL_SPI if SPL && ZYNQ_QSPI + imply SPL_SPI_FLASH_SUPPORT if SPL && ZYNQ_QSPI select SPL_SEPARATE_BSS if SPL select SUPPORT_SPL imply ZYNQMP_IPI if DM_MAILBOX diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 697334086fd..57d06f0575d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -326,6 +326,8 @@ static void map_range(u64 virt, u64 phys, u64 size, int level, /* Going one level down */ if (pte_type(&table[i]) == PTE_TYPE_FAULT) set_pte_table(&table[i], create_table()); + else if (pte_type(&table[i]) != PTE_TYPE_TABLE) + split_block(&table[i], level); next_table = (u64 *)(table[i] & GENMASK_ULL(47, PAGE_SHIFT)); next_size = min(map_size - (virt & (map_size - 1)), size); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7b7788f7550..08dfbdd557b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -47,33 +47,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-atl-sbx81lifkw.dtb \ - kirkwood-atl-sbx81lifxcat.dtb \ - kirkwood-blackarmor-nas220.dtb \ - kirkwood-d2net.dtb \ - kirkwood-dns325.dtb \ - kirkwood-dockstar.dtb \ - kirkwood-dreamplug.dtb \ - kirkwood-ds109.dtb \ - kirkwood-goflexnet.dtb \ - kirkwood-guruplug-server-plus.dtb \ - kirkwood-ib62x0.dtb \ - kirkwood-iconnect.dtb \ - kirkwood-is2.dtb \ - kirkwood-lsxhl.dtb \ - kirkwood-lschlv2.dtb \ - kirkwood-net2big.dtb \ - kirkwood-ns2.dtb \ - kirkwood-ns2lite.dtb \ - kirkwood-ns2max.dtb \ - kirkwood-ns2mini.dtb \ - kirkwood-nsa310s.dtb \ - kirkwood-nsa325.dtb \ - kirkwood-openrd-base.dtb \ - kirkwood-openrd-client.dtb \ - kirkwood-openrd-ultimate.dtb \ - kirkwood-pogo_e02.dtb \ - kirkwood-pogoplug-series-4.dtb \ - kirkwood-sheevaplug.dtb + kirkwood-atl-sbx81lifxcat.dtb dtb-$(CONFIG_MACH_S900) += \ bubblegum_96.dtb @@ -219,40 +193,8 @@ dtb-$(CONFIG_ARCH_S5P4418) += \ s5p4418-nanopi2.dtb dtb-$(CONFIG_ARCH_MESON) += \ - meson-a1-ad401.dtb \ - meson-axg-s400.dtb \ - meson-axg-jethome-jethub-j100.dtb \ - meson-gxl-s805x-libretech-ac.dtb \ - meson-gxl-s905d-libretech-pc.dtb \ - meson-gxl-s905w-jethome-jethub-j80.dtb \ - meson-gxl-s905x-khadas-vim.dtb \ - meson-gxl-s905x-libretech-cc.dtb \ - meson-gxl-s905x-libretech-cc-v2.dtb \ - meson-gxl-s905x-p212.dtb \ - meson-gxm-gt1-ultimate.dtb \ - meson-gxm-khadas-vim2.dtb \ - meson-gxm-s912-libretech-pc.dtb \ - meson-gxm-wetek-core2.dtb \ - meson-g12a-radxa-zero.dtb \ - meson-g12a-sei510.dtb \ - meson-g12a-u200.dtb \ - meson-g12b-a311d-bananapi-m2s.dtb \ - meson-g12b-a311d-khadas-vim3.dtb \ - meson-g12b-bananapi-cm4-cm4io.dtb \ - meson-g12b-gsking-x.dtb \ - meson-g12b-gtking.dtb \ - meson-g12b-gtking-pro.dtb \ - meson-g12b-odroid-go-ultra.dtb \ - meson-g12b-odroid-n2.dtb \ - meson-g12b-odroid-n2l.dtb \ - meson-g12b-odroid-n2-plus.dtb \ - meson-g12b-radxa-zero2.dtb \ - meson-sm1-bananapi-m2-pro.dtb \ - meson-sm1-bananapi-m5.dtb \ - meson-sm1-khadas-vim3l.dtb \ - meson-sm1-odroid-c4.dtb \ - meson-sm1-odroid-hc4.dtb \ - meson-sm1-sei610.dtb + meson-a1-ad401.dtb + dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ @@ -1082,16 +1024,12 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-phg.dtb \ imx8mm-phyboard-polis-rdk.dtb \ imx8mm-phygate-tauri-l.dtb \ - imx8mm-verdin-wifi-dev.dtb \ imx8mn-bsh-smm-s2.dtb \ imx8mn-bsh-smm-s2pro.dtb \ imx8mq-cm.dtb \ imx8mn-var-som-symphony.dtb \ - imx8mm-beacon-kit.dtb \ - imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ - imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-som-overlay-rev100.dtbo \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ @@ -1104,7 +1042,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mp-verdin-wifi-dev.dtb \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb @@ -1416,7 +1353,6 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb \ k3-am625-beagleplay.dtb \ k3-am625-r5-beagleplay.dtb \ - k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-r5.dtb \ k3-am625-phyboard-lyra-rdk.dtb \ k3-am625-r5-phycore-som-2gb.dtb diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index e9b188ed658..358cf8abc4f 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include "imx6qdl-u-boot.dtsi" +#include "imx6qdl-sr-som-u-boot.dtsi" / { board-detect { diff --git a/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi new file mode 100644 index 00000000000..0bd7df02dd6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <dt-bindings/gpio/gpio.h> + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; + phy-mode = "rgmii-id"; + + /* + * The PHY seems to require a long-enough reset duration to avoid + * some rare issues where the PHY gets stuck in an inconsistent and + * non-functional state at boot-up. 10ms proved to be fine . + */ + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + status = "disabled"; + }; + + ethernet-phy@1 { + status = "disabled"; + }; + + ethernet-phy@4 { + status = "disabled"; + }; + + phy: ethernet-phy@ffffffff { + /* + * The PHY can appear either: + * - AR8035: at address 0 or 4 + * - ADIN1300: at address 1 + * Actual address being detected at runtime. + */ + reg = <0xffffffff>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + adi,phy-output-clock = "125mhz-free-running"; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-beacon-kit.dts b/arch/arm/dts/imx8mm-beacon-kit.dts deleted file mode 100644 index 74a7b0cc10c..00000000000 --- a/arch/arm/dts/imx8mm-beacon-kit.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-beacon-som.dtsi" -#include "imx8mm-beacon-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; - compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi deleted file mode 100644 index cf07987ccc1..00000000000 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_gpio>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - max-speed = <4000000>; - clock-names = "extclk"; - }; -}; - -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&usdhc1_pwrseq>; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi b/arch/arm/dts/imx8mm-verdin-dev.dtsi deleted file mode 100644 index 3c4b8ca125e..00000000000 --- a/arch/arm/dts/imx8mm-verdin-dev.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - sound_card: sound-card { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-nau8822"; - simple-audio-card,routing = - "Headphones", "LHP", - "Headphones", "RHP", - "Speaker", "LSPK", - "Speaker", "RSPK", - "Line Out", "AUXOUT1", - "Line Out", "AUXOUT2", - "LAUX", "Line In", - "RAUX", "Line In", - "LMICP", "Mic In", - "RMICP", "Mic In"; - simple-audio-card,widgets = - "Headphones", "Headphones", - "Line Out", "Line Out", - "Speaker", "Speaker", - "Microphone", "Mic In", - "Line", "Line In"; - - dailink_master: simple-audio-card,codec { - clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; - sound-dai = <&nau8822_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - }; -}; - -/* Verdin SPI_1 */ -&ecspi2 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&gpio_expander_21 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* Audio Codec */ - nau8822_1a: audio-codec@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; - #sound-dai-cells = <0>; - }; -}; - -/* Verdin PCIE_1 */ -&pcie0 { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_1 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm3 { - status = "okay"; -}; - -/* Verdin I2S_1 */ -&sai2 { - status = "okay"; -}; - -/* Verdin UART_3 */ -&uart1 { - status = "okay"; -}; - -/* Verdin UART_1, connector X50 through RS485 transceiver */ -&uart2 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbotg1 { - disable-over-current; - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbotg2 { - disable-over-current; - status = "okay"; -}; - -/* Limit frequency on dev board due to long traces and bad signal integrity */ -&usdhc2 { - max-frequency = <100000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts b/arch/arm/dts/imx8mm-verdin-wifi-dev.dts deleted file mode 100644 index ef952021832..00000000000 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx8mm-verdin.dtsi" -#include "imx8mm-verdin-wifi.dtsi" -#include "imx8mm-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; - compatible = "toradex,verdin-imx8mm-wifi-dev", - "toradex,verdin-imx8mm-wifi", - "toradex,verdin-imx8mm", - "fsl,imx8mm"; -}; diff --git a/arch/arm/dts/imx8mm-verdin-wifi.dtsi b/arch/arm/dts/imx8mm-verdin-wifi.dtsi deleted file mode 100644 index 017db9eab25..00000000000 --- a/arch/arm/dts/imx8mm-verdin-wifi.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PDn_AW-CM276NF"; - startup-delay-us = <2000>; - }; -}; - -&gpio3 { - gpio-line-names = "SODIMM_52", - "SODIMM_54", - "SODIMM_64", - "SODIMM_21", - "SODIMM_206", - "SODIMM_76", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", - "SODIMM_66", - "SODIMM_17", - "", - "", - "", - "SODIMM_244", - "", - "SODIMM_48", - "SODIMM_44", - "SODIMM_42", - "SODIMM_46"; -}; - -&gpio4 { - gpio-line-names = "SODIMM_102", - "SODIMM_90", - "SODIMM_92", - "SODIMM_94", - "SODIMM_96", - "SODIMM_100", - "", - "", - "", - "", - "SODIMM_120", - "SODIMM_104", - "SODIMM_106", - "SODIMM_108", - "SODIMM_112", - "SODIMM_114", - "SODIMM_116", - "", - "SODIMM_118", - "", - "SODIMM_88", - "SODIMM_149", - "SODIMM_147", - "SODIMM_36", - "SODIMM_32", - "SODIMM_30", - "SODIMM_34", - "SODIMM_38", - "SODIMM_252", - "SODIMM_133", - "SODIMM_135", - "SODIMM_129"; -}; - -/* On-module Wi-Fi */ -&usdhc3 { - bus-width = <4>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi deleted file mode 100644 index 6f081158714..00000000000 --- a/arch/arm/dts/imx8mm-verdin.dtsi +++ /dev/null @@ -1,1319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/pwm/pwm.h> -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart1; - }; - - aliases { - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - /* Fixed clock dedicated to SPI CAN controller */ - clk40m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - hdmi_connector: hdmi-connector { - compatible = "hdmi-connector"; - ddc-i2c-bus = <&i2c2>; - /* Verdin PWM_3_DSI (SODIMM 19) */ - hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - label = "hdmi"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; - type = "a"; - status = "disabled"; - }; - - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - status = "disabled"; - }; - - /* Carrier Board Supplies */ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SW"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SW"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "+V5_SW"; - }; - - /* Non PMIC On-module Supplies */ - reg_ethphy: regulator-ethphy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay-us = <500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ETH"; - startup-delay-us = <200000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_1_EN (SODIMM 155) */ - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_1_EN"; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_2_EN (SODIMM 185) */ - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_2_EN"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Use the kernel configuration settings instead */ - /delete-node/ linux,cma; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&cpu_alert0 { - temperature = <95000>; -}; - -&cpu_crit0 { - temperature = <105000>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25000000 { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750000000 { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -/* Verdin SPI_1 */ -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; -}; - -/* Verdin CAN_1 (On-module) */ -&ecspi3 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - - can1: can@0 { - compatible = "microchip,mcp251xfd"; - clocks = <&clk40m>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_int>; - reg = <0>; - spi-max-frequency = <8500000>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&fec1 { - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-supply = <®_ethphy>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; -}; - -/* Verdin QSPI_1 */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_216", - "SODIMM_19", - "", - "", - "", - "", - "", - "", - "SODIMM_220", - "SODIMM_222", - "", - "SODIMM_218", - "SODIMM_155", - "SODIMM_157", - "SODIMM_185", - "SODIMM_187"; -}; - -&gpio2 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_84", - "SODIMM_78", - "SODIMM_74", - "SODIMM_80", - "SODIMM_82", - "SODIMM_70", - "SODIMM_72"; -}; - -&gpio5 { - gpio-line-names = "SODIMM_131", - "", - "SODIMM_91", - "SODIMM_16", - "SODIMM_15", - "SODIMM_208", - "SODIMM_137", - "SODIMM_139", - "SODIMM_141", - "SODIMM_143", - "SODIMM_196", - "SODIMM_200", - "SODIMM_198", - "SODIMM_202", - "", - "", - "SODIMM_55", - "SODIMM_53", - "SODIMM_95", - "SODIMM_93", - "SODIMM_14", - "SODIMM_12", - "", - "", - "", - "", - "SODIMM_210", - "SODIMM_212", - "SODIMM_151", - "SODIMM_153"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <1 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; -}; - -/* On-module I2C */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - interrupt-parent = <&gpio1>; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x25>; - - /* - * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC - * behind this PMIC. - */ - - regulators { - reg_vdd_soc: BUCK1 { - nxp,dvs-run-voltage = <850000>; - nxp,dvs-standby-voltage = <800000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +VDD_SOC (BUCK1)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_arm: BUCK2 { - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1050000>; - regulator-min-microvolt = <805000>; - regulator-name = "On-module +VDD_ARM (BUCK2)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_dram: BUCK3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <805000>; - regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; - }; - - reg_vdd_3v3: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3 (BUCK4)"; - }; - - reg_vdd_1v8: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI (BUCK5)"; - }; - - reg_nvcc_dram: BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "On-module +VDD_DDR (BUCK6)"; - }; - - reg_nvcc_snvs: LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_SNVS (LDO1)"; - }; - - reg_vdd_snvs: LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <800000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +V0.8_SNVS (LDO2)"; - }; - - reg_vdda: LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8A (LDO3)"; - }; - - reg_vdd_phy: LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <900000>; - regulator-name = "On-module +V0.9_MIPI (LDO4)"; - }; - - reg_nvcc_sd: LDO5 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin I2C_1 (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - clock-frequency = <10000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "disabled"; -}; - -/* Verdin I2C_3_HDMI N/A */ - -/* Verdin I2C_4_CSI */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* Verdin I2C_1 */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - gpio_expander_21: gpio-expander@21 { - compatible = "nxp,pcal6416"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x21>; - vcc-supply = <®_3p3v>; - status = "disabled"; - }; - - lvds_ti_sn65dsi84: bridge@2c { - compatible = "ti,sn65dsi84"; - /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x2c>; - status = "disabled"; - }; - - /* Current measurement into module VCC */ - hwmon: hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - status = "disabled"; - }; - - hdmi_lontium_lt8912: hdmi@48 { - compatible = "lontium,lt8912b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x48>; - /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - atmel_mxt_ts: touch@4a { - compatible = "atmel,maxtouch"; - /* - * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) - */ - interrupt-parent = <&gpio3>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; - reg = <0x4a>; - /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - /* Temperature sensor on carrier board */ - hwmon_temp: sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - status = "disabled"; - }; - - /* EEPROM on display adapter (MIPI DSI Display Adapter) */ - eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - status = "disabled"; - }; - - /* EEPROM on carrier board */ - eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x57>; - status = "disabled"; - }; -}; - -/* Verdin PCIE_1 */ -&pcie0 { - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - assigned-clock-rates = <10000000>, <250000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - /* PCIE_1_RESET# (SODIMM 244) */ - reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie_phy { - clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; - clock-names = "ref"; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; -}; - -/* Verdin PWM_3_DSI */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_1>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_1 */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_2>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_2 */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3>; - #pwm-cells = <3>; -}; - -/* Verdin I2S_1 */ -&sai2 { - #sound-dai-cells = <0>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - assigned-clocks = <&clk IMX8MM_CLK_SAI2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux console */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -/* Verdin UART_1 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* Verdin UART_2 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; -}; - -/* - * Verdin UART_4 - * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS - */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -/* Verdin USB_1 */ -&usbotg1 { - adp-disable; - dr_mode = "otg"; - hnp-disable; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - srp-disable; - vbus-supply = <®_usb_otg1_vbus>; -}; - -/* Verdin USB_2 */ -&usbotg2 { - dr_mode = "host"; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - vbus-supply = <®_usb_otg2_vbus>; -}; - -&usbphynop1 { - vcc-supply = <®_vdd_3v3>; -}; - -&usbphynop2 { - power-domains = <&pgc_otg2>; - vcc-supply = <®_vdd_3v3>; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; - vmmc-supply = <®_usdhc2_vmmc>; -}; - -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, - <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, - <&pinctrl_pmic_tpm_ena>; - - pinctrl_can1_int: can1intgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ - }; - - pinctrl_can2_int: can2intgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ - }; - - pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = - <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ - <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ - <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ - <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ - <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ - <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ - <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ - <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ - }; - - pinctrl_fec1: fec1grp { - fsl,pins = - <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, - <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, - <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, - <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, - <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, - <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, - <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, - <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, - <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, - <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, - <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, - <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, - <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, - <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, - <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; - }; - - pinctrl_fec1_sleep: fec1-sleepgrp { - fsl,pins = - <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, - <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, - <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, - <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, - <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, - <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, - <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, - <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, - <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, - <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, - <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, - <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, - <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, - <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, - <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ - <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ - <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ - <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ - <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ - <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ - <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ - <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ - }; - - pinctrl_gpio3: gpio3grp { - fsl,pins = - <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ - }; - - pinctrl_gpio4: gpio4grp { - fsl,pins = - <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ - }; - - pinctrl_gpio6: gpio6grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ - }; - - pinctrl_gpio7: gpio7grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ - }; - - pinctrl_gpio8: gpio8grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ - }; - - /* Verdin GPIO_9_DSI (pulled-up as active-low) */ - pinctrl_gpio_9_dsi: gpio9dsigrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ - }; - - /* Verdin GPIO_10_DSI (pulled-up as active-low) */ - pinctrl_gpio_10_dsi: gpio10dsigrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ - }; - - pinctrl_gpio_hog1: gpiohog1grp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ - <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ - <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ - <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ - <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ - <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ - <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ - <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ - <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ - <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ - <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ - <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ - <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ - <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ - <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ - }; - - pinctrl_gpio_hog2: gpiohog2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ - }; - - pinctrl_gpio_hog3: gpiohog3grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ - <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ - }; - - /* On-module I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ - <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ - <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ - <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ - <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ - <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ - <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ - }; - - /* Verdin I2C_1 */ - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ - <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = - <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ - <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ - }; - - /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ - pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ - }; - - /* Verdin I2S_2_D_OUT shared with SAI5 */ - pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ - /* PMIC_EN_PCIe_CLK, unused */ - <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ - }; - - /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ - pinctrl_pwm_1: pwm1grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ - }; - - pinctrl_pwm_2: pwm2grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ - }; - - pinctrl_pwm_3: pwm3grp { - fsl,pins = - <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ - }; - - /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ - pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ - }; - - pinctrl_reg_eth: regethgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ - }; - - pinctrl_reg_usb1_en: regusb1engrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ - }; - - pinctrl_reg_usb2_en: regusb2engrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ - }; - - pinctrl_sai2: sai2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ - <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ - <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ - <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ - <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ - }; - - pinctrl_sai5: sai5grp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ - <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ - <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ - <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ - }; - - /* control signal for optional ATTPM20P or SE050 */ - pinctrl_pmic_tpm_ena: pmictpmenagrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ - }; - - pinctrl_tsp: tspgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ - <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ - <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ - <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ - <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ - <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ - <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ - <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ - <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ - <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ - <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ - <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ - }; - - pinctrl_uart4: uart4grp { - fsl,pins = - <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ - <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, - <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, - <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, - <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, - <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { - fsl,pins = - <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ - }; - - /* - * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the - * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. - */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; - }; - - /* Avoid backfeeding with removed card power */ - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, - <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, - <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, - <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, - <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, - <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, - <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; - }; - - /* - * On-module Wi-Fi/BT or type specific SDHC interface - * (e.g. on X52 extension slot of Verdin Development Board) - */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, - <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = - <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ - }; - - pinctrl_wifi_ctrl: wifictrlgrp { - fsl,pins = - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ - <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ - <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ - }; - - pinctrl_wifi_i2s: bti2sgrp { - fsl,pins = - <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ - <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ - <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ - <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = - <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ - }; -}; diff --git a/arch/arm/dts/imx8mn-beacon-kit.dts b/arch/arm/dts/imx8mn-beacon-kit.dts deleted file mode 100644 index 1392ce02587..00000000000 --- a/arch/arm/dts/imx8mn-beacon-kit.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-beacon-som.dtsi" -#include "imx8mn-beacon-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit"; - compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi deleted file mode 100644 index 1133cded9be..00000000000 --- a/arch/arm/dts/imx8mn-beacon-som.dtsi +++ /dev/null @@ -1,472 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - spi0 = &flexspi; - }; - - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_gpio>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ -&a53_opp_table { - opp-1200000000 { - opp-microvolt = <950000>; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - phy-supply = <&buck6_reg>; - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MN_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - max-speed = <4000000>; - clock-names = "extclk"; - }; -}; - -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <&buck4_reg>; - vqmmc-supply = <&buck5_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&usdhc1_pwrseq>; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts deleted file mode 100644 index a08057410bd..00000000000 --- a/arch/arm/dts/imx8mp-beacon-kit.dts +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks - */ - -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp.dtsi" -#include "imx8mp-beacon-som.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8MPlus Development kit"; - compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - }; - - chosen { - stdout-path = &uart2; - }; - - clk_xtal25: clock-xtal25 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hs_ep: endpoint { - remote-endpoint = <&usb3_hs_ep>; - }; - }; - port@1 { - reg = <1>; - - ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_in_ep>; - }; - }; - }; - }; - - dmic_codec: dmic-codec { - compatible = "dmic-codec"; - num-channels = <1>; - #sound-dai-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - button-0 { - label = "btn0"; - linux,code = <BTN_0>; - gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-1 { - label = "btn1"; - linux,code = <BTN_1>; - gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-2 { - label = "btn2"; - linux,code = <BTN_2>; - gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - - button-3 { - label = "btn3"; - linux,code = <BTN_3>; - gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - wakeup-source; - }; - }; - - bridge-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7535_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - - led-0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_audio: regulator-wm8962 { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <20000>; - }; - - reg_usb1_host_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_host_vbus"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound-adv7535 { - compatible = "simple-audio-card"; - simple-audio-card,name = "sound-adv7535"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sai5>; - system-clock-direction-out; - }; - - simple-audio-card,codec { - sound-dai = <&adv_bridge>; - }; - }; - - sound-dmic { - compatible = "simple-audio-card"; - simple-audio-card,name = "sound-pdm"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,frame-master = <&dailink_master>; - - dailink_master: simple-audio-card,cpu { - sound-dai = <&micfil>; - }; - - simple-audio-card,codec { - sound-dai = <&dmic_codec>; - }; - }; - - sound-wm8962 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8962"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = "Headphone", "Headphones", - "Microphone", "Headset Mic", - "Speaker", "Speaker"; - simple-audio-card,routing = "Headphones", "HPOUTL", - "Headphones", "HPOUTR", - "Speaker", "SPKOUTL", - "Speaker", "SPKOUTR", - "Headset Mic", "MICBIAS", - "IN3R", "Headset Mic"; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8962>; - clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - frame-master; - bitclock-master; - }; - }; -}; - -&audio_blk_ctrl { - assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-rates = <393216000>, <135475200>; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm: tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm>; - reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; - spi-max-frequency = <18500000>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <150000>; - interrupt-parent = <&gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&gpio2 { - usb-mux-hog { - gpio-hog; - gpios = <20 0>; - output-low; - line-name = "USB-C Mux En"; - }; -}; - -&i2c2 { - clock-frequency = <384000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca6416_3: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - adv_bridge: hdmi@3d { - compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; - adi,dsi-lanes = <4>; - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7535_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - adv7535_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - pcieclk: clock-generator@68 { - compatible = "renesas,9fgv0241"; - reg = <0x68>; - clocks = <&clk_xtal25>; - #clock-cells = <1>; - }; -}; - -&i2c3 { - /* Connected to USB Hub */ - usb-typec@52 { - compatible = "nxp,ptn5110"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "source"; - data-role = "host"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <384000>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wm8962>; - clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <22576000>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - #sound-dai-cells = <0>; - }; - - pca6416: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - usb-hub-hog { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "USB Hub Enable"; - }; - }; - - usb-typec@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hd3ss3220>; - interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hd3ss3220_in_ep: endpoint { - remote-endpoint = <&ss_ep>; - }; - }; - - port@1 { - reg = <1>; - - hd3ss3220_out_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; -}; - -&lcdif1 { - status = "okay"; -}; - -&micfil { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdm>; - assigned-clocks = <&clk IMX8MP_CLK_PDM>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; - assigned-clock-rates = <49152000>; - status = "okay"; -}; - -&mipi_dsi { - samsung,esc-clock-frequency = <10000000>; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dsi_out: endpoint { - remote-endpoint = <&adv7535_in>; - }; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie_phy { - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - clocks = <&pcieclk 1>; - clock-names = "ref"; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MP_CLK_SAI3>, - <&clk IMX8MP_AUDIO_PLL2> ; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <12288000>, <361267200>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&sai5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai5>; - assigned-clocks = <&clk IMX8MP_CLK_SAI5>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MP_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usb3_hs_ep: endpoint { - remote-endpoint = <&hs_ep>; - }; - }; - port@1 { - reg = <1>; - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_out_ep>; - }; - }; - }; -}; - -&usb3_phy0 { - vbus-supply = <®_usb1_host_vbus>; - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140 - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 - >; - }; - - pinctrl_hd3ss3220: hd3ss3220grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */ - MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */ - >; - }; - - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 - MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 - MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 - MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 - >; - }; - - pinctrl_sai5: sai5grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 - >; - }; - - pinctrl_tpm: tpmgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ - MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */ - >; - }; - - pinctrl_typec: typec1grp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_wm8962: wm8962grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi deleted file mode 100644 index 8be251b6937..00000000000 --- a/arch/arm/dts/imx8mp-beacon-som.dtsi +++ /dev/null @@ -1,487 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks - */ - -/ { - aliases { - rtc0 = &rtc; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0xc0000000>, - <0x1 0x00000000 0 0xc0000000>; - }; - - reg_wl_bt: regulator-wifi-bt { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wl_bt>; - regulator-name = "wl-bt-pow-dwn"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - startup-delay-us = <70000>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - snps,force_thresh_dma_mode; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <384000>; - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <384000>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - }; - - rtc: rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MP_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8997-bt"; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wl_bt>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - keep-power-in-suspend; - wakeup-source; - non-removable; - cap-power-off-card; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mwifiex: wifi@1 { - compatible = "marvell,sd8997"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 - >; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 - >; - }; - - pinctrl_reg_wl_bt: reg-wl-btgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 - MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 - MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 - MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 - MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 - MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-verdin-dev.dtsi b/arch/arm/dts/imx8mp-verdin-dev.dtsi deleted file mode 100644 index bdfdd4c782f..00000000000 --- a/arch/arm/dts/imx8mp-verdin-dev.dtsi +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - /* TODO: Audio Codec */ - - reg_eth2phy: regulator-eth2phy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */ - off-on-delay-us = <500000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_ETH"; - startup-delay-us = <200000>; - vin-supply = <®_3p3v>; - }; -}; - -&backlight { - power-supply = <®_3p3v>; -}; - -/* Verdin SPI_1 */ -&ecspi1 { - status = "okay"; -}; - -/* EEPROM on display adapter boards */ -&eeprom_display_adapter { - status = "okay"; -}; - -/* EEPROM on Verdin Development board */ -&eeprom_carrier_board { - status = "okay"; -}; - -&eqos { - status = "okay"; -}; - -&fec { - phy-supply = <®_eth2phy>; - status = "okay"; -}; - -&flexcan1 { - status = "okay"; -}; - -&flexcan2 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - status = "okay"; -}; - -&gpio_expander_21 { - status = "okay"; - vcc-supply = <®_1p8v>; -}; - -/* Current measurement into module VCC */ -&hwmon { - status = "okay"; -}; - -&hwmon_temp { - vs-supply = <®_1p8v>; - status = "okay"; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -/* Verdin I2C_1 */ -&i2c4 { - status = "okay"; - - /* TODO: Audio Codec */ -}; - -/* Verdin PCIE_1 */ -&pcie { - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -/* Verdin PWM_1 */ -&pwm1 { - status = "okay"; -}; - -/* Verdin PWM_2 */ -&pwm2 { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&pwm3 { - status = "okay"; -}; - -®_usdhc2_vmmc { - vin-supply = <®_3p3v>; -}; - -/* TODO: Verdin I2C_1 with Audio Codec */ - -/* Verdin UART_1, connector X50 through RS485 transceiver */ -&uart1 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin UART_2 */ -&uart2 { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux Console */ -&uart3 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usb3_0 { - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usb3_1 { - fsl,permanently-attached; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -/* Limit frequency on dev board due to long traces and bad signal integrity */ -&usdhc2 { - max-frequency = <100000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts b/arch/arm/dts/imx8mp-verdin-wifi-dev.dts deleted file mode 100644 index c1713c28cdc..00000000000 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/dts-v1/; - -#include "imx8mp-verdin.dtsi" -#include "imx8mp-verdin-wifi.dtsi" -#include "imx8mp-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board"; - compatible = "toradex,verdin-imx8mp-wifi-dev", - "toradex,verdin-imx8mp-wifi", - "toradex,verdin-imx8mp", - "fsl,imx8mp"; -}; diff --git a/arch/arm/dts/imx8mp-verdin-wifi.dtsi b/arch/arm/dts/imx8mp-verdin-wifi.dtsi deleted file mode 100644 index ef94f9a57e2..00000000000 --- a/arch/arm/dts/imx8mp-verdin-wifi.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -/ { - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "PDn_AW-CM276NF"; - startup-delay-us = <2000>; - }; -}; - -&gpio5 { - gpio-line-names = "SODIMM_42", - "SODIMM_46", - "SODIMM_187", - "SODIMM_20", - "SODIMM_22", - "SODIMM_15", - "SODIMM_196", - "SODIMM_200", - "SODIMM_198", - "SODIMM_202", - "", - "", - "", - "", - "", - "", - "SODIMM_55", - "SODIMM_53", - "SODIMM_95", - "SODIMM_93", - "SODIMM_14", - "SODIMM_12", - "SODIMM_129", - "SODIMM_131", - "SODIMM_137", - "SODIMM_139", - "SODIMM_147", - "SODIMM_149", - "SODIMM_151", - "SODIMM_153"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, - <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, - <&pinctrl_hdmi_hog>; -}; - -/* On-module Bluetooth */ -&uart4 { - uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_uart>; - status = "okay"; - - bluetooth { - compatible = "mrvl,88w8997"; - max-speed = <921600>; - }; -}; - -/* On-module Wi-Fi */ -&usdhc1 { - bus-width = <4>; - keep-power-in-suspend; - max-frequency = <100000000>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi deleted file mode 100644 index e9e4fcb562f..00000000000 --- a/arch/arm/dts/imx8mp-verdin.dtsi +++ /dev/null @@ -1,1438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2022 Toradex - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/pwm/pwm.h> -#include "imx8mp.dtsi" - -/ { - chosen { - stdout-path = &uart3; - }; - - aliases { - /* Ethernet aliases to ensure correct MAC addresses */ - ethernet0 = &eqos; - ethernet1 = &fec; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - backlight_mezzanine: backlight-mezzanine { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin GPIO 4 (SODIMM 212) */ - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - /* Verdin PWM_2 (SODIMM 16) */ - pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - /* Carrier Board Supplies */ - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SW"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SW"; - }; - - reg_5p0v: regulator-5p0v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "+V5_SW"; - }; - - /* Non PMIC On-module Supplies */ - reg_module_eth1phy: regulator-module-eth1phy { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ - off-on-delay-us = <500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ETH"; - startup-delay-us = <200000>; - vin-supply = <®_vdd_3v3>; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_1_EN (SODIMM 155) */ - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_1_EN"; - }; - - reg_usb2_vbus: regulator-usb2-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_2_EN (SODIMM 185) */ - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2_vbus>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_2_EN"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Use the kernel configuration settings instead */ - /delete-node/ linux,cma; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&cpu_alert0 { - temperature = <95000>; -}; - -&cpu_crit0 { - temperature = <105000>; -}; - -/* Verdin SPI_1 */ -&ecspi1 { - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&eqos { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-supply = <®_module_eth1phy>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - snps,force_thresh_dma_mode; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - eee-broken-100tx; - eee-broken-1000t; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; -}; - -/* Verdin ETH_2_RGMII */ -&fec { - fsl,magic-packet; - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <7>; - }; - }; -}; - -/* Verdin CAN_1 */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -/* Verdin CAN_2 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "disabled"; -}; - -/* Verdin QSPI_1 */ -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; -}; - -&gpio1 { - gpio-line-names = "SODIMM_206", - "SODIMM_208", - "", - "", - "", - "SODIMM_210", - "SODIMM_212", - "SODIMM_216", - "SODIMM_218", - "", - "", - "SODIMM_16", - "SODIMM_155", - "SODIMM_157", - "SODIMM_185", - "SODIMM_91"; -}; - -&gpio2 { - gpio-line-names = "", - "", - "", - "", - "", - "", - "SODIMM_143", - "SODIMM_141", - "", - "", - "SODIMM_161", - "", - "SODIMM_84", - "SODIMM_78", - "SODIMM_74", - "SODIMM_80", - "SODIMM_82", - "SODIMM_70", - "SODIMM_72"; -}; - -&gpio3 { - gpio-line-names = "SODIMM_52", - "SODIMM_54", - "", - "", - "", - "", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", - "SODIMM_66", - "", - "SODIMM_64", - "", - "", - "SODIMM_34", - "SODIMM_19", - "", - "SODIMM_32", - "", - "", - "SODIMM_30", - "SODIMM_59", - "SODIMM_57", - "SODIMM_63", - "SODIMM_61"; -}; - -&gpio4 { - gpio-line-names = "SODIMM_252", - "SODIMM_222", - "SODIMM_36", - "SODIMM_220", - "SODIMM_193", - "SODIMM_191", - "SODIMM_201", - "SODIMM_203", - "SODIMM_205", - "SODIMM_207", - "SODIMM_199", - "SODIMM_197", - "SODIMM_221", - "SODIMM_219", - "SODIMM_217", - "SODIMM_215", - "SODIMM_211", - "SODIMM_213", - "SODIMM_189", - "SODIMM_244", - "SODIMM_38", - "", - "SODIMM_76", - "SODIMM_135", - "SODIMM_133", - "SODIMM_17", - "SODIMM_24", - "SODIMM_26", - "SODIMM_21", - "SODIMM_256", - "SODIMM_48", - "SODIMM_44"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; -}; - -/* On-module I2C */ -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450c"; - interrupt-parent = <&gpio1>; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x25>; - - /* - * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the - * I2C level shifter for the TLA2024 ADC behind this PMIC. - */ - - regulators { - BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <720000>; - regulator-name = "On-module +VDD_SOC (BUCK1)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_arm: BUCK2 { - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1025000>; - regulator-min-microvolt = <720000>; - regulator-name = "On-module +VDD_ARM (BUCK2)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_3v3: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3 (BUCK4)"; - }; - - reg_vdd_1v8: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI (BUCK5)"; - }; - - BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1155000>; - regulator-min-microvolt = <1045000>; - regulator-name = "On-module +VDD_DDR (BUCK6)"; - }; - - LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1950000>; - regulator-min-microvolt = <1650000>; - regulator-name = "On-module +V1.8_SNVS (LDO1)"; - }; - - LDO2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1150000>; - regulator-min-microvolt = <800000>; - regulator-name = "On-module +V0.8_SNVS (LDO2)"; - }; - - LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8A (LDO3)"; - }; - - LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3_ADC (LDO4)"; - }; - - LDO5 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - /* On-module temperature sensor */ - hwmon_temp_module: sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - vs-supply = <®_vdd_1v8>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin I2C_1 (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin I2C_1 ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_2_DSI */ -&i2c2 { - /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ - clock-frequency = <10000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - atmel_mxt_ts_mezzanine: touch-mezzanine@4a { - compatible = "atmel,maxtouch"; - /* Verdin GPIO_3 (SODIMM 210) */ - interrupt-parent = <&gpio1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reg = <0x4a>; - /* Verdin GPIO_2 (SODIMM 208) */ - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; -}; - -/* TODO: Verdin I2C_3_HDMI */ - -/* Verdin I2C_4_CSI */ -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* Verdin I2C_1 */ -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - gpio_expander_21: gpio-expander@21 { - compatible = "nxp,pcal6416"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x21>; - vcc-supply = <®_3p3v>; - status = "disabled"; - }; - - lvds_ti_sn65dsi84: bridge@2c { - compatible = "ti,sn65dsi84"; - /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>; - reg = <0x2c>; - status = "disabled"; - }; - - /* Current measurement into module VCC */ - hwmon: hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - status = "disabled"; - }; - - hdmi_lontium_lt8912: hdmi@48 { - compatible = "lontium,lt8912b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; - reg = <0x48>; - /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ - /* Verdin GPIO_10_DSI (SODIMM 21) */ - reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - atmel_mxt_ts: touch@4a { - compatible = "atmel,maxtouch"; - /* - * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) - */ - interrupt-parent = <&gpio4>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; - reg = <0x4a>; - /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - /* Temperature sensor on carrier board */ - hwmon_temp: sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - status = "disabled"; - }; - - /* EEPROM on display adapter (MIPI DSI Display Adapter) */ - eeprom_display_adapter: eeprom@50 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x50>; - status = "disabled"; - }; - - /* EEPROM on carrier board */ - eeprom_carrier_board: eeprom@57 { - compatible = "st,24c02"; - pagesize = <16>; - reg = <0x57>; - status = "disabled"; - }; -}; - -/* Verdin PCIE_1 */ -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - /* PCIE_1_RESET# (SODIMM 244) */ - reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; -}; - -&pcie_phy { - clocks = <&hsio_blk_ctrl>; - clock-names = "ref"; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; -}; - -/* Verdin PWM_1 */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_1>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_2 */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_2>; - #pwm-cells = <3>; -}; - -/* Verdin PWM_3_DSI */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_3>; - #pwm-cells = <3>; -}; - -/* TODO: Verdin I2S_1 */ - -/* TODO: Verdin I2S_2 */ - -&snvs_pwrkey { - status = "okay"; -}; - -/* Verdin UART_1 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; -}; - -/* Verdin UART_2 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* Verdin UART_3, used as the Linux Console */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -/* Verdin USB_1 */ -&usb3_0 { - fsl,disable-port-power-control; - fsl,over-current-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_oc_n>; -}; - -&usb_dwc3_0 { - /* dual role only, not full featured OTG */ - adp-disable; - dr_mode = "otg"; - hnp-disable; - maximum-speed = "high-speed"; - role-switch-default-mode = "peripheral"; - srp-disable; - usb-role-switch; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - label = "Type-C"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; - self-powered; - type = "micro"; - vbus-supply = <®_usb1_vbus>; - }; -}; - -/* Verdin USB_2 */ -&usb3_1 { - fsl,disable-port-power-control; -}; - -&usb3_phy1 { - vbus-supply = <®_usb2_vbus>; -}; - -&usb_dwc3_1 { - dr_mode = "host"; -}; - -/* Verdin SD_1 */ -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; - vmmc-supply = <®_usdhc2_vmmc>; -}; - -/* On-module eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - status = "okay"; -}; - -&wdog1 { - fsl,ext-reset-output; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt_uart: btuartgrp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, - <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; - }; - - pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ - <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ - <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ - <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ - }; - - /* Connection On Board PHY */ - pinctrl_eqos: eqosgrp { - fsl,pins = - <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, - <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, - <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, - <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, - <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, - <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, - <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, - <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, - <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, - <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, - <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, - <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, - <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, - <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; - }; - - /* ETH_INT# shared with TPM_INT# (usually N/A) */ - pinctrl_eth_tpm_int: ethtpmintgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; - }; - - /* Connection Carrier Board PHY ETH_2 */ - pinctrl_fec: fecgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ - <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ - <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ - <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ - <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ - <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ - <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ - <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ - <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ - <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ - <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ - <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ - <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ - <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ - <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ - <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ - <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ - <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ - <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ - <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ - <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = - <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ - <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ - <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ - <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ - <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ - <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ - <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ - <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ - }; - - pinctrl_gpio2: gpio2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ - }; - - pinctrl_gpio3: gpio3grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ - }; - - pinctrl_gpio4: gpio4grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ - }; - - pinctrl_gpio6: gpio6grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ - }; - - pinctrl_gpio7: gpio7grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ - }; - - pinctrl_gpio8: gpio8grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ - }; - - /* Verdin GPIO_9_DSI (pulled-up as active-low) */ - pinctrl_gpio_9_dsi: gpio9dsigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ - }; - - /* Verdin GPIO_10_DSI */ - pinctrl_gpio_10_dsi: gpio10dsigrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ - }; - - /* Non-wifi MSP usage only */ - pinctrl_gpio_hog1: gpiohog1grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ - <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ - <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ - <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ - }; - - /* USB_2_OC# */ - pinctrl_gpio_hog2: gpiohog2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ - }; - - pinctrl_gpio_hog3: gpiohog3grp { - fsl,pins = - /* CSI_1_MCLK */ - <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ - }; - - /* Wifi usage only */ - pinctrl_gpio_hog4: gpiohog4grp { - fsl,pins = - <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ - <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ - }; - - pinctrl_hdmi_hog: hdmihoggrp { - fsl,pins = - <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ - <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ - <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ - <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ - }; - - /* On-module I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ - <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ - }; - - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ - <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ - <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ - }; - - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ - <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ - }; - - /* Verdin I2C_1 */ - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ - <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ - }; - - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ - <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ - }; - - /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ - pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ - }; - - /* Verdin I2S_2_D_OUT shared with SAI3 */ - pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ - }; - - pinctrl_pcie: pciegrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ - <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ - }; - - pinctrl_pwm_1: pwm1grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ - }; - - pinctrl_pwm_2: pwm2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ - }; - - /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ - pinctrl_pwm_3: pwm3grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ - }; - - /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ - pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ - }; - - pinctrl_reg_eth: regethgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ - }; - - pinctrl_sai1: sai1grp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ - <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ - <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ - <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ - <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ - }; - - pinctrl_sai3: sai3grp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ - <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ - <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ - <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ - <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ - <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ - <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ - <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ - <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ - <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ - <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ - }; - - /* Non-wifi usage only */ - pinctrl_uart4: uart4grp { - fsl,pins = - <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ - <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ - }; - - pinctrl_usb1_vbus: usb1vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ - }; - - /* USB_1_ID */ - pinctrl_usb_1_id: usb1idgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ - }; - - /* USB_1_OC# */ - pinctrl_usb_1_oc_n: usb1ocngrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ - }; - - pinctrl_usb2_vbus: usb2vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ - }; - - pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; - }; - - /* Avoid backfeeding with removed card power */ - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ - }; - - pinctrl_bluetooth_ctrl: bluetoothctrlgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ - }; - - pinctrl_wifi_ctrl: wifictrlgrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ - }; - - pinctrl_wifi_i2s: wifii2sgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ - <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ - <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ - <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = - <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ - }; -}; diff --git a/arch/arm/dts/k3-am62-verdin-dev.dtsi b/arch/arm/dts/k3-am62-verdin-dev.dtsi deleted file mode 100644 index 6701cb8974b..00000000000 --- a/arch/arm/dts/k3-am62-verdin-dev.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM on Development carrier board - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,name = "verdin-nau8822"; - simple-audio-card,routing = - "Headphones", "LHP", - "Headphones", "RHP", - "Speaker", "LSPK", - "Speaker", "RSPK", - "Line Out", "AUXOUT1", - "Line Out", "AUXOUT2", - "LAUX", "Line In", - "RAUX", "Line In", - "LMICP", "Mic In", - "RMICP", "Mic In"; - simple-audio-card,widgets = - "Headphones", "Headphones", - "Line Out", "Line Out", - "Speaker", "Speaker", - "Microphone", "Mic In", - "Line", "Line In"; - - codec_dai: simple-audio-card,codec { - clocks = <&audio_refclk1>; - sound-dai = <&nau8822_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - }; -}; - -/* Verdin ETHs */ -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; - status = "okay"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - status = "okay"; - - cpsw3g_phy1: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - interrupt-parent = <&main_gpio0>; - interrupts = <38 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth2_rgmii_int>; - micrel,led-mode = <0>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - status = "okay"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - phy-handle = <&cpsw3g_phy1>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm0 { - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&epwm1 { - status = "okay"; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, - <&pinctrl_gpio_5>, - <&pinctrl_gpio_6>, - <&pinctrl_gpio_7>, - <&pinctrl_gpio_8>; -}; - -/* Verdin I2C_1 */ -&main_i2c1 { - status = "okay"; - - /* Audio Codec */ - nau8822_1a: audio-codec@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s1_mclk>; - #sound-dai-cells = <0>; - }; - - /* IO Expander */ - gpio_expander_21: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - - /* Current measurement into module VCC */ - hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - /* Temperature sensor */ - sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - }; - - /* EEPROM */ - eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c2 { - status = "okay"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - status = "okay"; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - status = "okay"; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - status = "okay"; -}; - -/* Verdin UART_3 */ -&main_uart0 { - status = "okay"; -}; - -/* Verdin UART_1, connector X50 through RS485 transceiver. */ -&main_uart1 { - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - status = "okay"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - status = "okay"; -}; - -&mcu_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_1>, - <&pinctrl_gpio_2>, - <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - status = "okay"; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - status = "okay"; -}; - -/* Verdin UART_4 */ -&mcu_uart0 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - ti,driver-strength-ohm = <33>; - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbss0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbss1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* Verdin CTRL_WAKE1_MICO# */ -&verdin_gpio_keys { - status = "okay"; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - /* FIXME: WKUP UART0 is used by DM firmware */ - status = "reserved"; -}; diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi deleted file mode 100644 index a6808b10c7b..00000000000 --- a/arch/arm/dts/k3-am62-verdin-wifi.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM WB variant - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - */ - -/ { - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_en>; - reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; - }; -}; - -/* On-module Wi-Fi */ -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci2>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - mmc-pwrseq = <&wifi_pwrseq>; - non-removable; - ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; - vmmc-supply = <®_3v3>; - status = "okay"; -}; - -/* On-module Bluetooth */ -&main_uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8987-bt"; - fw-init-baudrate = <3000000>; - }; -}; diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi deleted file mode 100644 index 5db52f23725..00000000000 --- a/arch/arm/dts/k3-am62-verdin.dtsi +++ /dev/null @@ -1,1443 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * Common dtsi for Verdin AM62 SoM - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - can0 = &main_mcan0; - can1 = &mcu_mcan0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - i2c0 = &main_i2c0; - i2c1 = &main_i2c1; - i2c2 = &main_i2c2; - i2c3 = &mcu_i2c0; - i2c4 = &main_i2c3; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - rtc0 = &rtc_i2c; - rtc1 = &wkup_rtc0; - serial0 = &main_uart1; - serial1 = &wkup_uart0; - serial2 = &main_uart0; - serial3 = &mcu_uart0; - serial4 = &main_uart5; - usb0 = &usb0; - usb1 = &usb1; - }; - - verdin_gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; - status = "disabled"; - - verdin_key_wakeup: key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ - }; - - opp-table { - /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - - /* Module Power Supply */ - reg_vsodimm: regulator-vsodimm { - compatible = "regulator-fixed"; - regulator-name = "+V_SODIMM"; - }; - - /* Non PMIC On-module Supplies */ - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "On-module +V3.3"; - vin-supply = <®_vsodimm>; - }; - - reg_1v2_dsi: regulator-1v2-dsi { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1200000>; - regulator-min-microvolt = <1200000>; - regulator-name = "On-module +V1.2_DSI"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V1.2_DSI */ - reg_1v8_dsi: regulator-1v8-dsi { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_DSI"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V2.5_ETH */ - reg_1v0_eth: regulator-1v0-eth { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <1000000>; - regulator-name = "On-module +V1.0_ETH"; - vin-supply = <®_1v8>; - }; - - /* Enabled by +V2.5_ETH */ - reg_1v8_eth: regulator-1v8-eth { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8_ETH"; - vin-supply = <®_1v8>; - }; - - /* Verdin SD_1 Power Supply */ - reg_sdhc1_vmmc: regulator-sdhci1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_pwr_en>; - enable-active-high; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vsel_sd>; - /* PMIC_VSEL_SD */ - gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; - regulator-name = "LDO1-VSEL-SD (PMIC)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <1800000 0x0>, - <3300000 0x1>; - vin-supply = <®_sd_3v3_1v8>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; -}; - -&main_pmx0 { - /* Verdin PWM_1 */ - pinctrl_epwm0_a: main-epwm0a-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ - >; - }; - - /* Verdin PWM_2 */ - pinctrl_epwm0_b: main-epwm0b-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ - >; - }; - - /* Verdin PWM_3_DSI */ - pinctrl_epwm1_a: main-epwm1a-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ - >; - }; - - /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ - >; - }; - - /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ - >; - }; - - /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ - >; - }; - - /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ - >; - }; - - /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ - >; - }; - - /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ - >; - }; - - /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ - >; - }; - - /* WiFi_W_WKUP_HOST# */ - pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ - >; - }; - - /* WiFi_BT_WKUP_HOST# */ - pinctrl_bt_wkup_host: main-gpio0-16-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ - >; - }; - - /* PMIC_ETH_RESET# */ - pinctrl_eth_reset: main-gpio0-17-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ - >; - }; - - /* PMIC_BRIDGE_RESET# */ - pinctrl_bridge_reset: main-gpio0-20-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ - >; - }; - - /* PMIC_VSEL_SD */ - pinctrl_vsel_sd: main-gpio0-21-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ - >; - }; - - /* PMIC_EN_WIFI */ - pinctrl_wifi_en: main-gpio0-22-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ - >; - }; - - /* PMIC_ETH_INT# */ - pinctrl_eth_int: main-gpio0-25-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ - >; - }; - - /* WiFi_WKUP_BT# */ - pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ - >; - }; - - /* WiFi_WKUP_WLAN# */ - pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ - >; - }; - - /* Verdin SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-29-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ - >; - }; - - /* Verdin DSI_1_BKL_EN */ - pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ - >; - }; - - /* Verdin CTRL_SLEEP_MOCI# */ - pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ - >; - }; - - /* Verdin CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ - >; - }; - - /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ - >; - }; - - /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ - >; - }; - - /* Verdin GPIO_6 */ - pinctrl_gpio_6: main-gpio0-36-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ - >; - }; - - /* Verdin ETH_2_RGMII_INT# */ - pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ - >; - }; - - /* Verdin GPIO_5 */ - pinctrl_gpio_5: main-gpio0-40-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ - >; - }; - - /* Verdin GPIO_7 */ - pinctrl_gpio_7: main-gpio0-41-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ - >; - }; - - /* Verdin GPIO_8 */ - pinctrl_gpio_8: main-gpio0-42-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ - >; - }; - - /* Verdin USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-71-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ - >; - }; - - /* Verdin USB_2_OC# */ - pinctrl_usb2_oc: main-gpio0-72-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ - >; - }; - - /* Verdin PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ - >; - }; - - /* Verdin QSPI_1_DQS as GPIO */ - pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ - >; - }; - - /* Verdin USB_1_ID */ - pinctrl_usb0_id: main-gpio1-19-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ - >; - }; - - /* Verdin DSI_1_INT# (pulled-up as active-low) */ - pinctrl_dsi1_int: main-gpio1-49-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ - >; - }; - - /* On-module I2C - PMIC_I2C */ - pinctrl_i2c0: main-i2c0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ - AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ - >; - }; - - /* Verdin I2C_1 */ - pinctrl_i2c1: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ - AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ - >; - }; - - /* Verdin I2C_2_DSI */ - pinctrl_i2c2: main-i2c2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ - AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ - >; - }; - - /* Verdin I2C_4_CSI */ - pinctrl_i2c3: main-i2c3-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ - AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ - >; - }; - - /* I2S_1_MCLK */ - pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ - >; - }; - - /* Verdin I2S_1 */ - pinctrl_mcasp0: main-mcasp0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ - AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ - AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */ - AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ - >; - }; - - /* Verdin I2S_2 */ - pinctrl_mcasp1: main-mcasp1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ - AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ - AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ - AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ - >; - }; - - /* Verdin CAN_1 */ - pinctrl_mcan0: main-mcan0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ - AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ - >; - }; - - /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ - pinctrl_mdio: main-mdio1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ - >; - }; - - /* On-module eMMC */ - pinctrl_sdhci0: main-mmc0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - /* Verdin SD_1 */ - pinctrl_sdhci1: main-mmc1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ - AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ - >; - }; - - /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ - pinctrl_sdhci2: main-mmc2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ - AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ - AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */ - AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */ - AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */ - AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */ - AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ - >; - }; - - /* Verdin QSPI_1 */ - pinctrl_ospi0: main-ospi0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ - AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ - AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */ - AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */ - AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */ - AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */ - AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ - >; - }; - - /* Verdin ETH_1 RGMII (On-module PHY) */ - pinctrl_rgmii1: main-rgmii1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; - }; - - /* Verdin ETH_2 RGMII */ - pinctrl_rgmii2: main-rgmii2-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ - >; - }; - - /* Verdin SPI_1 */ - pinctrl_spi1: main-spi1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ - AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ - AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ - AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ - >; - }; - - /* ETH_25MHz_CLK */ - pinctrl_eth_clock: main-system-clkout0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ - >; - }; - - /* PMIC_EXTINT# */ - pinctrl_pmic_extint: main-system-extint-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ - >; - }; - - /* Verdin UART_3, used as the Linux console */ - pinctrl_uart0: main-uart0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ - >; - }; - - /* Verdin UART_1 */ - pinctrl_uart1: main-uart1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ - AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ - AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ - AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ - >; - }; - - /* Bluetooth on WB SKUs, module-specific UART otherwise */ - pinctrl_uart5: main-uart5-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ - AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ - AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */ - AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */ - >; - }; - - /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ - >; - }; - - /* Verdin USB_2 */ - pinctrl_usb1: main-usb1-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ - >; - }; - - /* DSS VOUT0 RGB */ - pinctrl_parallel_rgb: main-vout-default-pins { - pinctrl-single,pins = < - AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ - AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ - AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ - AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ - AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ - AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ - AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ - AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ - AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ - AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ - AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ - AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ - AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ - AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ - AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ - AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ - AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ - AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ - AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ - AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ - AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ - AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ - >; - }; -}; - -&mcu_pmx0 { - /* Verdin PCIE_1_RESET# */ - pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ - >; - }; - - /* Verdin GPIO_1 */ - pinctrl_gpio_1: mcu-gpio0-1-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ - >; - }; - - /* Verdin GPIO_2 */ - pinctrl_gpio_2: mcu-gpio0-2-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ - >; - }; - - /* Verdin GPIO_3 */ - pinctrl_gpio_3: mcu-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ - >; - }; - - /* Verdin GPIO_4 */ - pinctrl_gpio_4: mcu-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ - >; - }; - - /* Verdin I2C_3_HDMI */ - pinctrl_mcu_i2c0: mcu-i2c0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ - AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ - >; - }; - - /* Verdin CAN_2 */ - pinctrl_mcu_mcan0: mcu-mcan0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */ - AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */ - >; - }; - - /* Verdin UART_4 - Reserved to Cortex-M4 */ - pinctrl_mcu_uart0: mcu-uart0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ - AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ - >; - }; - - /* Verdin CSI_1_MCLK */ - pinctrl_csi1_mclk: wkup-clkout0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ - >; - }; - - /* Verdin UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-default-pins { - pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ - AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ - AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ - AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ - >; - }; -}; - -/* VERDIN I2S_1_MCLK */ -&audio_refclk1 { - assigned-clock-rates = <25000000>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - status = "disabled"; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - phy-handle = <&cpsw3g_phy0>; - phy-mode = "rgmii-rxid"; - status = "disabled"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - status = "disabled"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - assigned-clocks = <&k3_clks 157 20>; - assigned-clock-parents = <&k3_clks 157 22>; - assigned-clock-rates = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>; - status = "disabled"; - - cpsw3g_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id2000.a231"; - reg = <0>; - interrupt-parent = <&main_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>; - reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <1000>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_parallel_rgb>; - status = "disabled"; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - /* VP2: DPI Output */ - port@1 { - reg = <1>; - - dpi_out: endpoint { - remote-endpoint = <&rgb_in>; - }; - }; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>; - status = "disabled"; -}; - -/* Verdin PWM_3_DSI */ -&epwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm1_a>; - status = "disabled"; -}; - -&main_gpio0 { - gpio-line-names = - "SODIMM_52", /* 0 */ - "", - "", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", /* 10 */ - "SODIMM_54", - "SODIMM_64", - "", - "", - "SODIMM_174", - "SODIMM_172", - "", - "", - "", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_76", - "SODIMM_21", /* 30 */ - "SODIMM_256", - "SODIMM_252", - "", - "SODIMM_46", - "SODIMM_42", - "SODIMM_218", - "", - "SODIMM_189", - "", - "SODIMM_216", /* 40 */ - "SODIMM_220", - "SODIMM_222", - "", - "", - "", - "", - "", - "", - "", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 60 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 70 */ - "SODIMM_157", - "SODIMM_187", - "", - "", - "", - "", - "", - "", - "", - "", /* 80 */ - "", - "", - "", - "", - "", - ""; - - verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <31 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - }; -}; - -&main_gpio1 { - gpio-line-names = - "", /* 0 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "SODIMM_15", - "SODIMM_16", - "SODIMM_19", - "SODIMM_66", - "SODIMM_161", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 30 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 40 */ - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_17", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 60 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 70 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 80 */ - "", - "", - "", - "", - "", - "", - ""; -}; - -/* On-module I2C - PMIC_I2C */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clock-frequency = <400000>; - status = "okay"; - - dsi_bridge: dsi@e { - compatible = "toshiba,tc358778"; - reg = <0xe>; - assigned-clocks = <&k3_clks 157 20>; - assigned-clock-parents = <&k3_clks 157 22>; - assigned-clock-rates = <25000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bridge_reset>; - clocks = <&k3_clks 157 20>; - clock-names = "refclk"; - reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; - vddc-supply = <®_1v2_dsi>; - vddmipi-supply = <®_1v2_dsi>; - vddio-supply = <®_1v8_dsi>; - status = "disabled"; - - dsi_bridge_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - rgb_in: endpoint { - data-lines = <18>; - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - pmic@30 { - compatible = "ti,tps65219"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_extint>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - - buck1-supply = <®_vsodimm>; - buck2-supply = <®_vsodimm>; - buck3-supply = <®_vsodimm>; - ldo1-supply = <®_3v3>; - ldo2-supply = <®_1v8>; - ldo3-supply = <®_3v3>; - ldo4-supply = <®_3v3>; - system-power-controller; - ti,power-button; - - regulators { - reg_vdd_core: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+VDD_CORE (PMIC BUCK1)"; - }; - - reg_1v8: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ - }; - - reg_vdd_ddr: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+VDD_DDR (PMIC BUCK3)"; - }; - - reg_sd_3v3_1v8: ldo1 { - regulator-allow-bypass; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; - }; - - reg_vddr_core: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+VDDR_CORE (PMIC LDO2)"; - }; - - reg_1v8a: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A (PMIC LDO3)"; - }; - - reg_eth_2v5: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "+V2.5_ETH (PMIC LDO4)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin PMIC_I2C ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - pagesize = <16>; - reg = <0x50>; - }; -}; - -/* Verdin I2C_1 */ -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "disabled"; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "disabled"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "disabled"; -}; - -&mailbox0_cluster0 { - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcan0>; - status = "disabled"; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - ti,pindir-d0-out-d1-in; - status = "disabled"; -}; - -/* Verdin UART_3, used as the Linux console */ -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; -}; - -/* Verdin UART_1 */ -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "disabled"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp0>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -/* Verdin I2S_2 */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp1>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <32>; - tx-num-evt = <32>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c0>; - status = "disabled"; -}; - -&mcu_gpio0 { - gpio-line-names = - "SODIMM_244", - "SODIMM_206", - "SODIMM_208", - "SODIMM_210", - "SODIMM_212", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan0>; - status = "disabled"; -}; - -/* Verdin UART_4 - Cortex-M4 UART */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_uart0>; - status = "disabled"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ospi0>; - status = "disabled"; -}; - -/* On-module eMMC */ -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0>; - non-removable; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; - disable-wp; - ti,driver-strength-ohm = <50>; - vmmc-supply = <®_sdhc1_vmmc>; - vqmmc-supply = <®_sdhc1_vqmmc>; - status = "disabled"; -}; - -/* Verdin USB_1 */ -&usbss0 { - ti,vbus-divider; - status = "disabled"; -}; - -/* TODO: role swich using ID pin */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; - status = "disabled"; -}; - -/* Verdin USB_2 */ -&usbss1 { - ti,vbus-divider; - status = "disabled"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - dr_mode = "host"; - status = "disabled"; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index cca0f44b7d8..fb2032068d1 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -41,13 +41,6 @@ clock-frequency = <25000000>; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &sd_pins_default { /* Force to use SDCD card detect pin */ pinctrl-single,pins = < diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index f6138f3058f..94162282068 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -42,13 +42,6 @@ bootph-all; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &fss { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 5b058bd03a0..dfd38d64f63 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -151,11 +151,107 @@ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x40000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl { insert-template = <&ti_spl_template>; fit { images { + + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-secure { content = <&dm>; @@ -189,7 +285,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -247,6 +344,45 @@ fit { images { + tifsstub-hs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { ti-dm { filename = "ti-dm.bin"; @@ -270,7 +406,8 @@ conf-0 { description = "k3-am625-sk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 4e3704809a6..6f5845024f2 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -140,7 +140,7 @@ #ifdef CONFIG_TARGET_VERDIN_AM62_A53 -#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb" +#define SPL_VERDIN_AM62_DTB "spl/dts/ti/k3-am625-verdin-wifi-dev.dtb" #define VERDIN_AM62_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index 28b697b67ae..7fe7ae41543 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -85,13 +85,6 @@ bootph-all; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &fss { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts b/arch/arm/dts/k3-am625-verdin-wifi-dev.dts deleted file mode 100644 index 4b657d6d3e0..00000000000 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2023 Toradex - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/dts-v1/; - -#include "k3-am625.dtsi" -#include "k3-am62-verdin.dtsi" -#include "k3-am62-verdin-wifi.dtsi" -#include "k3-am62-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin AM62 WB on Verdin Development Board"; - compatible = "toradex,verdin-am62-wifi-dev", - "toradex,verdin-am62-wifi", - "toradex,verdin-am62", - "ti,am625"; -}; diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi index 31b89b41748..c42dec16194 100644 --- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -119,10 +119,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &vdd_mmc1 { diff --git a/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi index c166d655390..cf087c6e343 100644 --- a/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62p5-sk-u-boot.dtsi @@ -15,9 +15,4 @@ &dmsc { bootph-pre-ram; - - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-pre-ram; - }; }; diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi index ee6656774d6..705b3baa81c 100644 --- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi @@ -23,13 +23,6 @@ bootph-all; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &sdhci0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index 5dfc40a843b..4677c35e2d9 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -29,10 +29,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &dmss { diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index 7e6b2981346..6fcb11bd04d 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -15,13 +15,6 @@ clock-frequency = <200000000>; }; -&dmsc { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; -}; - &sdhci0 { status = "disabled"; }; diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index d53f133cd63..b6d2c816acc 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -99,10 +99,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi index 4f34347586e..b8fc62f0dd1 100644 --- a/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi @@ -51,10 +51,6 @@ &sms { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &main_pmx0 { diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi index bed330e6d4e..4a82d2fd222 100644 --- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi @@ -23,13 +23,6 @@ bootph-pre-ram; }; -&sms { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-pre-ram; - }; -}; - #ifdef CONFIG_TARGET_J784S4_A72_EVM #define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb" diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index c9fee0ea99b..485f17c5f06 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -57,10 +57,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 116ee373118..e202ae16644 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -92,10 +92,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 9433f3bafae..aa919b40702 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -47,10 +47,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi index 8b205553cdf..8f4f944263e 100644 --- a/arch/arm/dts/k3-j721e-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-sk-u-boot.dtsi @@ -47,10 +47,6 @@ &dmsc { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &k3_pds { diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index a3ebf5996ea..19b2d48c7f8 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -51,10 +51,6 @@ &sms { bootph-all; - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-all; - }; }; &main_pmx0 { diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi index ac749782bfc..8f0307321e8 100644 --- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -22,10 +22,3 @@ "tchanrt", "rflow"; bootph-pre-ram; }; - -&sms { - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - bootph-pre-ram; - }; -}; diff --git a/arch/arm/dts/kirkwood-6192.dtsi b/arch/arm/dts/kirkwood-6192.dtsi deleted file mode 100644 index 396bcba08ad..00000000000 --- a/arch/arm/dts/kirkwood-6192.dtsi +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6192-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-6281.dtsi b/arch/arm/dts/kirkwood-6281.dtsi deleted file mode 100644 index faa05849a40..00000000000 --- a/arch/arm/dts/kirkwood-6281.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6281-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-6282.dtsi b/arch/arm/dts/kirkwood-6282.dtsi deleted file mode 100644 index e732c501ea8..00000000000 --- a/arch/arm/dts/kirkwood-6282.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <9>, <44>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie0_intc 0>, - <0 0 0 2 &pcie0_intc 1>, - <0 0 0 3 &pcie0_intc 2>, - <0 0 0 4 &pcie0_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - - pcie0_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-names = "intx", "error"; - interrupts = <10>, <45>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 18>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; - ocp@f1000000 { - - pinctrl: pin-controller@10000 { - compatible = "marvell,88f6282-pinctrl"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp5", "mpp21", "mpp23"; - marvell,function = "sata0"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp4", "mpp20", "mpp22"; - marvell,function = "sata1"; - }; - - /* - * Default I2C1 pinctrl setting on mpp36/mpp37, - * overwrite marvell,pins on board level if required. - */ - pmx_twsi1: pmx-twsi1 { - marvell,pins = "mpp36", "mpp37"; - marvell,function = "twsi1"; - }; - - pmx_sdio: pmx-sdio { - marvell,pins = "mpp12", "mpp13", "mpp14", - "mpp15", "mpp16", "mpp17"; - marvell,function = "sdio"; - }; - }; - - thermal: thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - rtc: rtc@10300 { - compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <53>; - clocks = <&gate_clk 7>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - sata: sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <21>; - clocks = <&gate_clk 14>, <&gate_clk 15>; - clock-names = "0", "1"; - phys = <&sata_phy0>, <&sata_phy1>; - phy-names = "port0", "port1"; - status = "disabled"; - }; - - sdio: mvsdio@90000 { - compatible = "marvell,orion-sdio"; - reg = <0x90000 0x200>; - interrupts = <28>; - clocks = <&gate_clk 4>; - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - bus-width = <4>; - cap-sdio-irq; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-98dx4122.dtsi b/arch/arm/dts/kirkwood-98dx4122.dtsi deleted file mode 100644 index 299c147298c..00000000000 --- a/arch/arm/dts/kirkwood-98dx4122.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - mbus@f1000000 { - pciec: pcie@82000000 { - compatible = "marvell,kirkwood-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - - pcie0: pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &intc 9>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gate_clk 2>; - status = "disabled"; - }; - }; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - compatible = "marvell,98dx4122-pinctrl"; - - }; - }; -}; - -&sata_phy0 { - status = "disabled"; -}; - -&sata_phy1 { - status = "disabled"; -}; diff --git a/arch/arm/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/dts/kirkwood-blackarmor-nas220.dts deleted file mode 100644 index 07fbfca444d..00000000000 --- a/arch/arm/dts/kirkwood-blackarmor-nas220.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for Seagate Blackarmor NAS220 - * - * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" - -/ { - model = "Seagate Blackarmor NAS220"; - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - gpio_keys { - compatible = "gpio-keys"; - - reset { - label = "Reset"; - linux,code = <KEY_POWER>; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - button { - label = "Power"; - linux,code = <KEY_SLEEP>; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-power { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* - * Serial port routed to connector CN5 - * - * pin 1 - TX (CPU's TX) - * pin 4 - RX (CPU's RX) - * pin 6 - GND - */ -&uart0 { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&pmx_button_reset &pmx_button_power>; - pinctrl-names = "default"; - - pmx_act_sata0: pmx-act-sata0 { - marvell,pins = "mpp15"; - marvell,function = "sata0"; - }; - - pmx_act_sata1: pmx-act-sata1 { - marvell,pins = "mpp16"; - marvell,function = "sata1"; - }; - - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_button_power: pmx-button-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; -}; - -&sata { - status = "okay"; - nr-ports = <2>; -}; - -&i2c0 { - status = "okay"; - - adt7476: thermal@2e { - compatible = "adi,adt7476"; - reg = <0x2e>; - }; -}; - -&nand { - status = "okay"; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-d2net.dts b/arch/arm/dts/kirkwood-d2net.dts deleted file mode 100644 index bd3b266dd76..00000000000 --- a/arch/arm/dts/kirkwood-d2net.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for d2 Network v2 - * - * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org> - * -*/ - -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie d2 Network v2"; - compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "d2net_v2:blue:sata"; - slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "d2net_v2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-dns325.dts b/arch/arm/dts/kirkwood-dns325.dts deleted file mode 100644 index 94d9c06cbbf..00000000000 --- a/arch/arm/dts/kirkwood-dns325.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-dnskw.dtsi" - -/ { - model = "D-Link DNS-325 NAS (Rev A1)"; - compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 - &pmx_led_red_left_hdd &pmx_led_red_right_hdd - &pmx_led_white_usb>; - pinctrl-names = "default"; - - white-power { - label = "dns325:white:power"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - white-usb { - label = "dns325:white:usb"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ - }; - red-l_hdd { - label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - red-r_hdd { - label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - red-usb { - label = "dns325:red:usb"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - - lm75: lm75@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-dnskw.dtsi b/arch/arm/dts/kirkwood-dnskw.dtsi deleted file mode 100644 index cbaf06f2f78..00000000000 --- a/arch/arm/dts/kirkwood-dnskw.dtsi +++ /dev/null @@ -1,235 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "D-Link DNS NASes (kirkwood-based)"; - compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_power &pmx_button_unmount - &pmx_button_reset>; - pinctrl-names = "default"; - - power { - label = "Power button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - eject { - label = "USB unmount button"; - linux,code = <KEY_EJECTCD>; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; - pinctrl-names = "default"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW - &gpio1 13 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 0 - 3000 1 - 6000 2>; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 - &pmx_present_sata1 &pmx_fan_tacho - &pmx_temp_alarm>; - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - pmx_led_red_right_hdd: pmx-led-red-right-hdd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_led_red_left_hdd: pmx-led-red-left-hdd { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_325: pmx-led-red-usb-325 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_button_power: pmx-button-power { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_led_red_usb_320: pmx-led-red-usb-320 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_power_back_on: pmx-power-back-on { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_power_sata0: pmx-power-sata0 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_power_sata1: pmx-power-sata1 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_present_sata0: pmx-present-sata0 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_present_sata1: pmx-present-sata1 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_white_usb: pmx-led-white-usb { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_fan_tacho: pmx-fan-tacho { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_fan_high_speed: pmx-fan-high-speed { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_fan_low_speed: pmx-fan-low-speed { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_button_unmount: pmx-button-unmount { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_temp_alarm: pmx-temp-alarm { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; - pinctrl-names = "default"; - - sata0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 7 0>; - }; - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 8 0>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x500000>; - }; - - partition@600000 { - label = "ramdisk"; - reg = <0x0600000 0x500000>; - }; - - partition@b00000 { - label = "image"; - reg = <0x0b00000 0x6600000>; - }; - - partition@7100000 { - label = "mini firmware"; - reg = <0x7100000 0xa00000>; - }; - - partition@7b00000 { - label = "config"; - reg = <0x7b00000 0x500000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-dockstar.dts b/arch/arm/dts/kirkwood-dockstar.dts deleted file mode 100644 index 6a3f1bf6d9f..00000000000 --- a/arch/arm/dts/kirkwood-dockstar.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led-green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x0500000 0xfb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1116"; - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi new file mode 100644 index 00000000000..59f19a211fa --- /dev/null +++ b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + aliases { + spi0 = &spi0; + }; +}; diff --git a/arch/arm/dts/kirkwood-dreamplug.dts b/arch/arm/dts/kirkwood-dreamplug.dts deleted file mode 100644 index e9eea22fc93..00000000000 --- a/arch/arm/dts/kirkwood-dreamplug.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Dreamplug"; - compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - aliases { - spi0 = &spi0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_bluetooth: pmx-led-bluetooth { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wifi: pmx-led-wifi { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wifi_ap: pmx-led-wifi-ap { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - - partition@100000 { - reg = <0x100000 0x10000>; - label = "u-boot env"; - }; - - partition@180000 { - reg = <0x180000 0x10000>; - label = "dtb"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi - &pmx_led_wifi_ap >; - pinctrl-names = "default"; - - bluetooth { - label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wifi { - label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wifi-ap { - label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ds109.dts b/arch/arm/dts/kirkwood-ds109.dts deleted file mode 100644 index 29982e7acb7..00000000000 --- a/arch/arm/dts/kirkwood-ds109.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Andrew Lunn <andrew@lunn.ch> - * Ben Peddell <klightspeed@killerwolves.net> - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-synology.dtsi" - -/ { - model = "Synology DS109, DS110, DS110jv20"; - compatible = "synology,ds109", "synology,ds110jv20", - "synology,ds110", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-fan-150-32-35 { - status = "okay"; - }; - - gpio-leds-hdd-21-1 { - status = "okay"; - }; -}; - -&rs5c372 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-goflexnet.dts b/arch/arm/dts/kirkwood-goflexnet.dts deleted file mode 100644 index 02d87e0a106..00000000000 --- a/arch/arm/dts/kirkwood-goflexnet.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_0: pmx-led_right_cap_0 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_1: pmx-led_right_cap_1 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_2: pmx-led_right_cap_2 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_right_cap_3: pmx-led_right_cap_3 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_0: pmx-led_left_cap_0 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_1: pmx-led_left_cap_1 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_2: pmx-led_left_cap_2 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_left_cap_3: pmx-led_left_cap_3 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_green: pmx-led_green { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_orange: pmx-led_orange { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_orange - &pmx_led_left_cap_0 &pmx_led_left_cap_1 - &pmx_led_left_cap_2 &pmx_led_left_cap_3 - &pmx_led_right_cap_0 &pmx_led_right_cap_1 - &pmx_led_right_cap_2 &pmx_led_right_cap_3 - >; - pinctrl-names = "default"; - - health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - left0 { - label = "status:white:left0"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - left1 { - label = "status:white:left1"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - left2 { - label = "status:white:left2"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - left3 { - label = "status:white:left3"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - right0 { - label = "status:white:right0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - right1 { - label = "status:white:right1"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - right2 { - label = "status:white:right2"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - right3 { - label = "status:white:right3"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0xd800000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/dts/kirkwood-guruplug-server-plus.dts deleted file mode 100644 index ff1260ee3fe..00000000000 --- a/arch/arm/dts/kirkwood-guruplug-server-plus.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Globalscale Technologies Guruplug Server Plus"; - compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_health_r: pmx-led-health-r { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_health_g: pmx-led-health-g { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_wmode_r: pmx-led-wmode-r { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - pmx_led_wmode_g: pmx-led-wmode-g { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - /* AzureWave AW-GH381 WiFi/BT */ - mvsdio@90000 { - status = "okay"; - non-removable; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g - &pmx_led_wmode_r &pmx_led_wmode_g >; - pinctrl-names = "default"; - - health-r { - label = "guruplug:red:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - health-g { - label = "guruplug:green:health"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - wmode-r { - label = "guruplug:red:wmode"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - wmode-g { - label = "guruplug:green:wmode"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x00100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x00100000 0x00400000>; - }; - - partition@500000 { - label = "data"; - reg = <0x00500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - /* Marvell 88E1121R */ - compatible = "ethernet-phy-id0141.0cb0", - "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-connection-type = "rgmii-id"; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - phy-connection-type = "rgmii-id"; - }; -}; diff --git a/arch/arm/dts/kirkwood-ib62x0.dts b/arch/arm/dts/kirkwood-ib62x0.dts deleted file mode 100644 index 962a910a6f5..00000000000 --- a/arch/arm/dts/kirkwood-ib62x0.dts +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; - compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_led_os_red: pmx-led-os-red { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - pmx_power_off: pmx-power-off { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - pmx_led_os_green: pmx-led-os-green { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - pmx_led_usb_transfer: pmx-led-usb-transfer { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_button_usb_copy: pmx-button-usb-copy { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; - pinctrl-names = "default"; - - copy { - label = "USB Copy"; - linux,code = <KEY_COPY>; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - - green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; - usb-copy { - label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_power_off>; - pinctrl-names = "default"; - gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0xe0000>; - }; - - partition@e0000 { - label = "u-boot environment"; - reg = <0xe0000 0x20000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x600000>; - }; - - partition@700000 { - label = "root"; - reg = <0x0700000 0xf900000>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-iconnect.dts b/arch/arm/dts/kirkwood-iconnect.dts deleted file mode 100644 index 4a512d80912..00000000000 --- a/arch/arm/dts/kirkwood-iconnect.dts +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - linux,initrd-start = <0x4500040>; - linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_button_reset: pmx-button-reset { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - pmx_button_otb: pmx-button-otb { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - pmx_led_level: pmx-led-level { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_led_power_blue: pmx-led-power-blue { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_led_power_red: pmx-power-red { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_usb1: pmx-led-usb1 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_led_usb2: pmx-led-usb2 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - pmx_led_usb3: pmx-led-usb3 { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_usb4: pmx-led-usb4 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - pmx_led_otb: pmx-led-otb { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - }; - i2c@11000 { - status = "okay"; - - lm63: lm63@4c { - compatible = "national,lm63"; - reg = <0x4c>; - }; - }; - serial@12000 { - status = "ok"; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = < &pmx_led_level &pmx_led_power_blue - &pmx_led_power_red &pmx_led_usb1 - &pmx_led_usb2 &pmx_led_usb3 - &pmx_led_usb4 &pmx_led_otb >; - pinctrl-names = "default"; - - led-level { - label = "led_level"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - usb1 { - label = "usb1:blue"; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - usb2 { - label = "usb2:blue"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3:blue"; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - usb4 { - label = "usb4:blue"; - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - otb { - label = "otb:blue"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; - pinctrl-names = "default"; - - otb { - label = "OTB Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - reset { - label = "Reset"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0xc0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0xa0000 0x20000>; - }; - - partition@100000 { - label = "zImage"; - reg = <0x100000 0x300000>; - }; - - partition@540000 { - label = "initrd"; - reg = <0x540000 0x300000>; - }; - - partition@980000 { - label = "boot"; - reg = <0x980000 0x1f400000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@11 { - reg = <11>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-is2.dts b/arch/arm/dts/kirkwood-is2.dts deleted file mode 100644 index 1bc16a5cdba..00000000000 --- a/arch/arm/dts/kirkwood-is2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Internet Space v2"; - compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi index 7fc2d7d3b41..cf33ff822ee 100644 --- a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi +++ b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -ð0 { - status = "disabled"; +/ { + aliases { + spi0 = &spi0; + }; }; &hdd_power { diff --git a/arch/arm/dts/kirkwood-lschlv2.dts b/arch/arm/dts/kirkwood-lschlv2.dts deleted file mode 100644 index 1d737d903f5..00000000000 --- a/arch/arm/dts/kirkwood-lschlv2.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-CHLv2"; - compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x4000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi index 7fc2d7d3b41..cf33ff822ee 100644 --- a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi +++ b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ -ð0 { - status = "disabled"; +/ { + aliases { + spi0 = &spi0; + }; }; &hdd_power { diff --git a/arch/arm/dts/kirkwood-lsxhl.dts b/arch/arm/dts/kirkwood-lsxhl.dts deleted file mode 100644 index a56e0d79777..00000000000 --- a/arch/arm/dts/kirkwood-lsxhl.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-lsxl.dtsi" - -/ { - model = "Buffalo Linkstation LS-XHL"; - compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-lsxl.dtsi b/arch/arm/dts/kirkwood-lsxl.dtsi deleted file mode 100644 index c99c0da0937..00000000000 --- a/arch/arm/dts/kirkwood-lsxl.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - aliases { - spi0 = &spi0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_power_hdd: pmx-power-hdd { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; - pmx_usb_vbus: pmx-usb-vbus { - marvell,pins = "mpp11"; - marvell,function = "gpio"; - }; - pmx_fan_high: pmx-fan-high { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - pmx_fan_low: pmx-fan-low { - marvell,pins = "mpp19"; - marvell,function = "gpo"; - }; - pmx_led_function_blue: pmx-led-function-blue { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - pmx_led_alarm: pmx-led-alarm { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - pmx_led_info: pmx-led-info { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - pmx_led_power: pmx-led-power { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - pmx_fan_lock: pmx-fan-lock { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_button_function: pmx-button-function { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - pmx_power_switch: pmx-power-switch { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - pmx_power_auto_switch: pmx-power-auto-switch { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - pmx_led_function_red: pmx-led-function_red { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - }; - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - spi@10600 { - status = "okay"; - - m25p40@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p40", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x60000>; - label = "uboot"; - read-only; - }; - - partition@60000 { - reg = <0x60000 0x10000>; - label = "dtb"; - read-only; - }; - - partition@70000 { - reg = <0x70000 0x10000>; - label = "uboot_env"; - }; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_function &pmx_power_switch - &pmx_power_auto_switch>; - pinctrl-names = "default"; - - option { - label = "Function Button"; - linux,code = <KEY_OPTION>; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - reserved { - label = "Power-on Switch"; - linux,code = <KEY_RESERVED>; - linux,input-type = <5>; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - power { - label = "Power-auto Switch"; - linux,code = <KEY_ESC>; - linux,input-type = <5>; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm - &pmx_led_info &pmx_led_power - &pmx_led_function_blue>; - pinctrl-names = "default"; - - func_blue { - label = "lsxl:blue:func"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - alarm { - label = "lsxl:red:alarm"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - info { - label = "lsxl:amber:info"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - power { - label = "lsxl:blue:power"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - func_red { - label = "lsxl:red:func"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; - pinctrl-names = "default"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW - &gpio0 18 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = <0 3 - 1500 2 - 3250 1 - 5000 0>; - alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - restart_poweroff { - compatible = "restart-poweroff"; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 11 0>; - }; - hdd_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "HDD Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 0>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-net2big.dts b/arch/arm/dts/kirkwood-net2big.dts deleted file mode 100644 index 3e3ac289e5b..00000000000 --- a/arch/arm/dts/kirkwood-net2big.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree file for LaCie 2Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn <andrew@lunn.ch> - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> - * -*/ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" -#include "kirkwood-netxbig.dtsi" - -/ { - model = "LaCie 2Big Network v2"; - compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - fan { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; -}; - -®ulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - }; - - clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; -}; - -&i2c0 { - g762@3e { - compatible = "gmt,g762"; - reg = <0x3e>; - clocks = <&g762_clk>; - }; -}; diff --git a/arch/arm/dts/kirkwood-netxbig.dtsi b/arch/arm/dts/kirkwood-netxbig.dtsi deleted file mode 100644 index b5737026e24..00000000000 --- a/arch/arm/dts/kirkwood-netxbig.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree common file for LaCie 2Big and 5Big Network v2 - * - * Copyright (C) 2014 - * - * Andrew Lunn <andrew@lunn.ch> - * - * Based on netxbig_v2-setup.c, - * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com> - * -*/ - -#include <dt-bindings/leds/leds-netxbig.h> -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - /* - * esc and power represent a three position rocker - * switch. Thus the conventional KEY_POWER does not fit - */ - exc { - label = "Back power switch (on|auto)"; - linux,code = <KEY_ESC>; - linux,input-type = <5>; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - power { - label = "Back power switch (auto|off)"; - linux,code = <KEY_1>; - linux,input-type = <5>; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - }; - option { - label = "Function button"; - linux,code = <KEY_OPTION>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; - }; - - regulators: regulators { - status = "okay"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd0power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - }; - - netxbig_gpio_ext: netxbig-gpio-ext { - compatible = "lacie,netxbig-gpio-ext"; - - addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH - &gpio1 16 GPIO_ACTIVE_HIGH - &gpio1 17 GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH - &gpio1 14 GPIO_ACTIVE_HIGH>; - enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - netxbig-leds { - compatible = "lacie,netxbig-leds"; - - gpio-ext = <&netxbig_gpio_ext>; - - timers = <NETXBIG_LED_TIMER1 500 500 - NETXBIG_LED_TIMER2 500 1000>; - - blue-power { - label = "netxbig:blue:power"; - mode-addr = <0>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 1 - NETXBIG_LED_TIMER1 3 - NETXBIG_LED_TIMER2 7>; - bright-addr = <1>; - max-brightness = <7>; - }; - red-power { - label = "netxbig:red:power"; - mode-addr = <0>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <1>; - max-brightness = <7>; - }; - blue-sata0 { - label = "netxbig:blue:sata0"; - mode-addr = <3>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 7 - NETXBIG_LED_SATA 1 - NETXBIG_LED_TIMER1 3>; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata0 { - label = "netxbig:red:sata0"; - mode-addr = <3>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <2>; - max-brightness = <7>; - }; - blue-sata1 { - label = "netxbig:blue:sata1"; - mode-addr = <4>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 7 - NETXBIG_LED_SATA 1 - NETXBIG_LED_TIMER1 3>; - bright-addr = <2>; - max-brightness = <7>; - }; - red-sata1 { - label = "netxbig:red:sata1"; - mode-addr = <4>; - mode-val = <NETXBIG_LED_OFF 0 - NETXBIG_LED_ON 2 - NETXBIG_LED_TIMER1 4>; - bright-addr = <2>; - max-brightness = <7>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - - pmx_button_function: pmx-button-function { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - pmx_button_power_off: pmx-button-power-off { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - pmx_button_power_on: pmx-button-power-on { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ns2-common.dtsi b/arch/arm/dts/kirkwood-ns2-common.dtsi deleted file mode 100644 index 51530ea8662..00000000000 --- a/arch/arm/dts/kirkwood-ns2-common.dtsi +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_ns2_sata0: pmx-ns2-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - pmx_ns2_sata1: pmx-ns2-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - spi@10600 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l4005a", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x0 0x80000>; - label = "u-boot"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x50>; - }; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - power { - label = "Power push button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - red-fail { - label = "ns2:red:fail"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-ns2.dts b/arch/arm/dts/kirkwood-ns2.dts deleted file mode 100644 index 7b67083e1ec..00000000000 --- a/arch/arm/dts/kirkwood-ns2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space v2"; - compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-ns2lite.dts b/arch/arm/dts/kirkwood-ns2lite.dts deleted file mode 100644 index b0cb5907ed6..00000000000 --- a/arch/arm/dts/kirkwood-ns2lite.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Lite v2"; - compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue-sata { - label = "ns2:blue:sata"; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - linux,default-trigger = "disk-activity"; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/dts/kirkwood-ns2max.dts b/arch/arm/dts/kirkwood-ns2max.dts deleted file mode 100644 index c0a087e7740..00000000000 --- a/arch/arm/dts/kirkwood-ns2max.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - model = "LaCie Network Space Max v2"; - compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 1500 15 - 1700 14 - 1800 13 - 2100 12 - 3100 11 - 3300 10 - 4300 9 - 5500 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <8>; }; diff --git a/arch/arm/dts/kirkwood-ns2mini.dts b/arch/arm/dts/kirkwood-ns2mini.dts deleted file mode 100644 index 5b9fa14b642..00000000000 --- a/arch/arm/dts/kirkwood-ns2mini.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include <dt-bindings/leds/leds-ns2.h> -#include "kirkwood-ns2-common.dtsi" - -/ { - /* This machine is embedded in the first LaCie CloudBox product. */ - model = "LaCie Network Space Mini v2"; - compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; - }; - - ocp@f1000000 { - sata@80000 { - pinctrl-0 = <&pmx_ns2_sata0>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <1>; - }; - }; - - gpio_fan { - compatible = "gpio-fan"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW - &gpio0 7 GPIO_ACTIVE_LOW - &gpio1 1 GPIO_ACTIVE_LOW - &gpio0 23 GPIO_ACTIVE_LOW>; - gpio-fan,speed-map = - < 0 0 - 3000 15 - 3180 14 - 4140 13 - 4570 12 - 6760 11 - 7140 10 - 7980 9 - 9200 8>; - alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 1 0 - NS_V2_LED_ON 0 1 - NS_V2_LED_ON 1 1 - NS_V2_LED_SATA 0 0>; - }; - }; -}; - -ðphy0 { reg = <0>; }; diff --git a/arch/arm/dts/kirkwood-nsa310s.dts b/arch/arm/dts/kirkwood-nsa310s.dts deleted file mode 100644 index 09ee76c2a2e..00000000000 --- a/arch/arm/dts/kirkwood-nsa310s.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree file for the Zyxel NSA 310S NAS box. - * - * Copyright (c) 2015-2021, Tony Dinh <mibodhi@gmail.com> - * - * Based on - * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> - * Based upon the board setup file created by Peter Schildmann - */ -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Zyxel NSA310S"; - compatible = "zyxel,nsa320s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_sata0: pmx-sata0 { - marvell,pins ; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins ; - marvell,function = "sata1"; - }; - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <1>; - }; - - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - ht1382: rtc@68 { - compatible = "htk,ht1382"; - reg = <0x68>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pmx_usb_power &pmx_pwr_sata1>; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - button@1 { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa310s:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - orange-sys { - label = "nsa310s:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa310s:green:hdd1"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa310s:red:hdd1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa310s:green:hdd2"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa310s:red:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa310s:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa310s:green:copy"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ide-disk"; - }; - red-copy { - label = "nsa310s:red:copy"; - gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - }; - partition@100000 { - label = "stock_uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - compatible = "marvell,88e1510"; - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi new file mode 100644 index 00000000000..dec27b2a87a --- /dev/null +++ b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&nand { + partition@0 { + /delete-property/ read-only; + }; +}; diff --git a/arch/arm/dts/kirkwood-nsa325.dts b/arch/arm/dts/kirkwood-nsa325.dts deleted file mode 100644 index efc57cfa41e..00000000000 --- a/arch/arm/dts/kirkwood-nsa325.dts +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Device tree file for the Zyxel NSA 325 NAS box. - * - * Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll@googlemail.com> - * - * - * Based upon the board setup file created by Peter Schildmann - */ - -/dts-v1/; - -#include "kirkwood-nsa3x0-common.dtsi" - -/ { - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-names = "default"; - - pmx_led_hdd2_green: pmx-led-hdd2-green { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_led_hdd2_red: pmx-led-hdd2-red { - marvell,pins = "mpp13"; - marvell,function = "gpio"; - }; - - pmx_mcu_data: pmx-mcu-data { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - pmx_led_usb_green: pmx-led-usb-green { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_mcu_clk: pmx-mcu-clk { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_mcu_act: pmx-mcu-act { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_led_sys_green: pmx-led-sys-green { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_led_sys_orange: pmx-led-sys-orange { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_green: pmx-led-hdd1-green { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_led_hdd1_red: pmx-led-hdd1-red { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_htp: pmx-htp { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - /* - * Buzzer needs to be switched at around 1kHz so is - * not compatible with the gpio-beeper driver. - */ - pmx_buzzer: pmx-buzzer { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_vid_b1: pmx-vid-b1 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_power_resume_data: pmx-power-resume-data { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - pmx_power_resume_clk: pmx-power-resume-clk { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - pmx_pwr_sata1: pmx-pwr-sata1 { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - - /* This board uses the pcf8563 RTC instead of the SoC RTC */ - rtc@10300 { - status = "disabled"; - }; - - i2c@11000 { - status = "okay"; - - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_pwr_sata1>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - enable-active-high; - }; - - sata1_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red - &pmx_led_usb_green - &pmx_led_sys_green &pmx_led_sys_orange - &pmx_led_copy_green &pmx_led_copy_red - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - - green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; - orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - green-copy { - label = "nsa325:green:copy"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - red-copy { - label = "nsa325:red:copy"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - }; - - /* The following pins are currently not assigned to a driver, - some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 - &pmx_power_resume_data &pmx_power_resume_clk>; */ - }; - -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi deleted file mode 100644 index a21c50d44a4..00000000000 --- a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - power { - label = "Power Button"; - linux,code = <KEY_POWER>; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - copy { - label = "Copy Button"; - linux,code = <KEY_COPY>; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - reset { - label = "Reset Button"; - linux,code = <KEY_RESTART>; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-openrd-base.dts b/arch/arm/dts/kirkwood-openrd-base.dts deleted file mode 100644 index 094191ece3d..00000000000 --- a/arch/arm/dts/kirkwood-openrd-base.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Base Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * base variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Base"; - compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - serial@12100 { - status = "okay"; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-client.dts b/arch/arm/dts/kirkwood-openrd-client.dts deleted file mode 100644 index 74dc23daf64..00000000000 --- a/arch/arm/dts/kirkwood-openrd-client.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Client Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * client variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Client"; - compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - audio-controller@a0000 { - status = "okay"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - #sound-dai-cells = <0>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,cpu { - sound-dai = <&audio0 0>; - }; - - simple-audio-card,codec { - sound-dai = <&cs42l51>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@8 { - reg = <8>; - }; - ethphy1: ethernet-phy@24 { - reg = <24>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd-ultimate.dts b/arch/arm/dts/kirkwood-openrd-ultimate.dts deleted file mode 100644 index 888e13320c1..00000000000 --- a/arch/arm/dts/kirkwood-openrd-ultimate.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD Ultimate Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are specific to OpenRD - * ultimate variant of the Marvell Kirkwood Development Board. - */ - -/dts-v1/; - -#include "kirkwood-openrd.dtsi" - -/ { - model = "OpenRD Ultimate"; - compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - cs42l51: cs42l51@4a { - compatible = "cirrus,cs42l51"; - reg = <0x4a>; - }; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; diff --git a/arch/arm/dts/kirkwood-openrd.dtsi b/arch/arm/dts/kirkwood-openrd.dtsi deleted file mode 100644 index 47f03c69c55..00000000000 --- a/arch/arm/dts/kirkwood-openrd.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Marvell OpenRD (Base|Client|Ultimate) Board Description - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file contains the definitions that are common between the three - * variants of the Marvell Kirkwood Development Board. - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; - pinctrl-names = "default"; - - pmx_select28: pmx-select-rs232-rs485 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_select34: pmx-select-uart-sd { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - - }; - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - mvsdio@90000 { - status = "okay"; - cd-gpios = <&gpio0 29 9>; - }; - gpio@10100 { - p28 { - gpio-hog; - gpios = <28 GPIO_ACTIVE_HIGH>; - /* - * SelRS232or485 selects between RS-232 or RS-485 - * mode for the second UART. - * - * Low: RS-232 - * High: RS-485 - * - * To use the second UART, you need to change also - * the SelUARTorSD. - */ - output-low; - line-name = "SelRS232or485"; - }; - }; - gpio@10140 { - p2 { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - /* - * SelUARTorSD selects between the second UART - * (serial@12100) and SD (mvsdio@90000). - * - * Low: UART - * High: SD - * - * When changing this line make sure the newly - * selected device node is enabled and the - * previously selected device node is disabled. - */ - output-high; /* Select SD by default */ - line-name = "SelUARTorSD"; - }; - }; - }; -}; - -&nand { - status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@600000 { - label = "root"; - reg = <0x0600000 0x1FA00000>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-pogo_e02.dts b/arch/arm/dts/kirkwood-pogo_e02.dts deleted file mode 100644 index f9e95e55f36..00000000000 --- a/arch/arm/dts/kirkwood-pogo_e02.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 - * - * Copyright (C) 2015 Christoph Junghans <ottxor@gentoo.org> - * - * based on information of dts files from - * Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com> - * OpenWrt by Felix Kaechele <heffer@fedoraproject.org> - * - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "Cloud Engines Pogoplug E02"; - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; - }; - - gpio-leds { - compatible = "gpio-leds"; - - health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pinctrl { - pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange - &pmx_led_green >; - pinctrl-names = "default"; - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_led_orange: pmx-led-orange { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&nand { - chip-delay = <40>; - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "pogoplug"; - reg = <0x0500000 0x2000000>; - }; - - partition@2500000 { - label = "root"; - reg = <0x02500000 0x5b00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/dts/kirkwood-pogoplug-series-4.dts deleted file mode 100644 index 5aa4669ae25..00000000000 --- a/arch/arm/dts/kirkwood-pogoplug-series-4.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 - * inspired by the board files made by Kevin Mihelich for ArchLinux, - * and their DTS file. - * - * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> - */ - -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-6192.dtsi" -#include <dt-bindings/input/linux-event-codes.h> - -/ { - model = "Cloud Engines PogoPlug Series 4"; - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { - stdout-path = "uart0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_button_eject>; - pinctrl-names = "default"; - - eject { - debounce-interval = <50>; - wakeup-source; - linux,code = <KEY_EJECTCD>; - label = "Eject Button"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pinctrl { - pmx_sata0: pmx-sata0 { - marvell,pins = "mpp21"; - marvell,function = "sata0"; - }; - - pmx_sata1: pmx-sata1 { - marvell,pins = "mpp20"; - marvell,function = "sata1"; - }; - - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_button_eject: pmx-button-eject { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_led_green: pmx-led-green { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_led_red: pmx-led-red { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* - * This PCIE controller has a USB 3.0 XHCI controller at 1,0 - */ -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&sata { - status = "okay"; - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - nr-ports = <1>; -}; - -&sdio { - status = "okay"; - pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; - pinctrl-names = "default"; - cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -}; - -&nand { - /* 128 MiB of NAND flash */ - chip-delay = <40>; - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x200000>; - read-only; - }; - - partition@200000 { - label = "uImage"; - reg = <0x00200000 0x300000>; - }; - - partition@500000 { - label = "uImage2"; - reg = <0x00500000 0x300000>; - }; - - partition@800000 { - label = "failsafe"; - reg = <0x00800000 0x800000>; - }; - - partition@1000000 { - label = "root"; - reg = <0x01000000 0x7000000>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi deleted file mode 100644 index 0a698d3b739..00000000000 --- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs - * - * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> - */ - -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - - pmx_usb_power_enable: pmx-usb-power-enable { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - pmx_led_red: pmx-led-red { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - pmx_led_blue: pmx-led-blue { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - pmx_sdio_cd: pmx-sdio-cd { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - pmx_sdio_wp: pmx-sdio-wp { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - }; - serial@12000 { - status = "okay"; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_enable>; - pinctrl-names = "default"; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 29 0>; - }; - }; -}; - -&nand { - status = "okay"; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x400000>; - }; - - partition@500000 { - label = "root"; - reg = <0x0500000 0x1fb00000>; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts deleted file mode 100644 index c73cc904e5c..00000000000 --- a/arch/arm/dts/kirkwood-sheevaplug.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug - * - * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> - */ - -/dts-v1/; - -#include "kirkwood-sheevaplug-common.dtsi" - -/ { - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; - pinctrl-names = "default"; - status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - - health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - misc { - label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm/dts/kirkwood-synology.dtsi b/arch/arm/dts/kirkwood-synology.dtsi deleted file mode 100644 index c97ed29a0a0..00000000000 --- a/arch/arm/dts/kirkwood-synology.dtsi +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Nodes for Marvell 628x Synology devices - * - * Andrew Lunn <andrew@lunn.ch> - * Ben Peddell <klightspeed@killerwolves.net> - * - */ - -/ { - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pmx_alarmled_12: pmx-alarmled-12 { - marvell,pins = "mpp12"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_15: pmx-fanctrl-15 { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_16: pmx-fanctrl-16 { - marvell,pins = "mpp16"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_17: pmx-fanctrl-17 { - marvell,pins = "mpp17"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_18: pmx-fanalarm-18 { - marvell,pins = "mpp18"; - marvell,function = "gpo"; - }; - - pmx_hddled_20: pmx-hddled-20 { - marvell,pins = "mpp20"; - marvell,function = "gpio"; - }; - - pmx_hddled_21: pmx-hddled-21 { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_hddled_22: pmx-hddled-22 { - marvell,pins = "mpp22"; - marvell,function = "gpio"; - }; - - pmx_hddled_23: pmx-hddled-23 { - marvell,pins = "mpp23"; - marvell,function = "gpio"; - }; - - pmx_hddled_24: pmx-hddled-24 { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - pmx_hddled_25: pmx-hddled-25 { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - pmx_hddled_26: pmx-hddled-26 { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - pmx_hddled_27: pmx-hddled-27 { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - pmx_hddled_28: pmx-hddled-28 { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - pmx_hdd1_pwr_30: pmx-hdd-pwr-30 { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_32: pmx-fanctrl-32 { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - pmx_fanctrl_33: pmx-fanctrl-33 { - marvell,pins = "mpp33"; - marvell,function = "gpo"; - }; - - pmx_fanctrl_34: pmx-fanctrl-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_35: pmx-fanalarm-35 { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - pmx_hddled_36: pmx-hddled-36 { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_hddled_37: pmx-hddled-37 { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_hddled_38: pmx-hddled-38 { - marvell,pins = "mpp38"; - marvell,function = "gpio"; - }; - - pmx_hddled_39: pmx-hddled-39 { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_hddled_40: pmx-hddled-40 { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - pmx_hddled_41: pmx-hddled-41 { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - pmx_hddled_42: pmx-hddled-42 { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - pmx_hddled_43: pmx-hddled-43 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - pmx_hddled_44: pmx-hddled-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hddled_45: pmx-hddled-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_44: pmx-fanalarm-44 { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - pmx_fanalarm_45: pmx-fanalarm-45 { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - }; - - rtc@10300 { - status = "disabled"; - }; - - spi@10600 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - mode = <0>; - - partition@0 { - reg = <0x00000000 0x00080000>; - label = "RedBoot"; - }; - - partition@80000 { - reg = <0x00080000 0x00200000>; - label = "zImage"; - }; - - partition@280000 { - reg = <0x00280000 0x00140000>; - label = "rd.gz"; - }; - - partition@3c0000 { - reg = <0x003c0000 0x00010000>; - label = "vendor"; - }; - - partition@3d0000 { - reg = <0x003d0000 0x00020000>; - label = "RedBoot config"; - }; - - partition@3f0000 { - reg = <0x003f0000 0x00010000>; - label = "FIS directory"; - }; - }; - }; - - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - - rs5c372: rs5c372@32 { - status = "disabled"; - compatible = "ricoh,rs5c372"; - reg = <0x32>; - }; - - s35390a: s35390a@30 { - status = "disabled"; - compatible = "sii,s35390a"; - reg = <0x30>; - }; - }; - - serial@12000 { - status = "okay"; - }; - - serial@12100 { - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&gate_clk 7>; - }; - - sata@80000 { - pinctrl-0 = <&pmx_sata0 &pmx_sata1>; - pinctrl-names = "default"; - status = "okay"; - nr-ports = <2>; - }; - }; - - gpio-fan-150-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-150-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2200 1 - 2500 2 - 3000 4 - 3300 3 - 3700 5 - 3800 6 - 4200 7 >; - }; - - gpio-fan-100-32-35 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH - &gpio1 1 GPIO_ACTIVE_HIGH - &gpio1 2 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-18 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_18>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-1 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-fan-100-15-35-3 { - status = "disabled"; - compatible = "gpio-fan"; - pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17 - &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>; - pinctrl-names = "default"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH - &gpio0 16 GPIO_ACTIVE_HIGH - &gpio0 17 GPIO_ACTIVE_HIGH>; - alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH - &gpio1 12 GPIO_ACTIVE_HIGH - &gpio1 13 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 2500 1 - 3100 2 - 3800 3 - 4600 4 - 4800 5 - 4900 6 - 5000 7 >; - }; - - gpio-leds-alarm-12 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_alarmled_12>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:alarm"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-20 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22 - &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25 - &pmx_hddled_26 &pmx_hddled_27>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-1 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-21-2 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-36 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38 - &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41 - &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44 - &pmx_hddled_45>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd3-green { - label = "synology:green:hdd3"; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - hdd3-amber { - label = "synology:amber:hdd3"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - - hdd4-green { - label = "synology:green:hdd4"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - }; - - hdd4-amber { - label = "synology:amber:hdd4"; - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; - - hdd5-green { - label = "synology:green:hdd5"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - }; - - hdd5-amber { - label = "synology:amber:hdd5"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds-hdd-38 { - status = "disabled"; - compatible = "gpio-leds"; - pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; - pinctrl-names = "default"; - - hdd1-green { - label = "synology:green:hdd1"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - - hdd1-amber { - label = "synology:amber:hdd1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - - hdd2-green { - label = "synology:green:hdd2"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - hdd2-amber { - label = "synology:amber:hdd2"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - }; - - regulators-hdd-29 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-1 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-2 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-30-4 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34 - &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd1power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-31 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_31>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; - }; - - regulators-hdd-34 { - status = "disabled"; - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44 - &pmx_hdd4_pwr_45>; - pinctrl-names = "default"; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "hdd2power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "hdd3power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "hdd4power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - startup-delay-us = <5000000>; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - device_type = "ethernet-phy"; - reg = <8>; - }; - - ethphy1: ethernet-phy@1 { - device_type = "ethernet-phy"; - reg = <9>; - }; -}; - -ð0 { - status = "okay"; - - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "disabled"; - - ethernet1-port@0 { - phy-handle = <ðphy1>; - }; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood.dtsi b/arch/arm/dts/kirkwood.dtsi deleted file mode 100644 index 81c7eda2c44..00000000000 --- a/arch/arm/dts/kirkwood.dtsi +++ /dev/null @@ -1,393 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/include/ "skeleton.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> - -#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) - -/ { - compatible = "marvell,kirkwood"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,feroceon"; - reg = <0>; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; - }; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; - }; - - mbus@f1000000 { - compatible = "marvell,kirkwood-mbus", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - /* If a board file needs to change this ranges it must replace it completely */ - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ - MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ - MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ - >; - controller = <&mbusc>; - pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ - pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - - nand: nand@12f { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - compatible = "marvell,orion-nand"; - reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; - chip-delay = <25>; - /* set partition map and/or chip-delay in board dts */ - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "disabled"; - }; - - crypto_sram: sa-sram@301 { - compatible = "mmio-sram"; - reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; - clocks = <&gate_clk 17>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x0100000>; - #address-cells = <1>; - #size-cells = <1>; - - pinctrl: pin-controller@10000 { - /* set compatible property in SoC file */ - reg = <0x10000 0x20>; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; - - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - - /* - * Default SPI0 pinctrl setting with CSn on mpp0, - * overwrite marvell,pins on board level if required. - */ - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - - /* - * Default UART pinctrl setting without RTS/CTS, - * overwrite marvell,pins on board level if required. - */ - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; - }; - - core_clk: core-clocks@10030 { - compatible = "marvell,kirkwood-core-clock"; - reg = <0x10030 0x4>; - #clock-cells = <1>; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; - status = "disabled"; - }; - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <35>, <36>, <37>, <38>; - clocks = <&gate_clk 7>; - }; - - gpio1: gpio@10140 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10140 0x40>; - ngpios = <18>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <39>, <40>, <41>; - clocks = <&gate_clk 7>; - }; - - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart0: serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&gate_clk 7>; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; - status = "disabled"; - }; - - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - sysc: system-controller@20000 { - compatible = "marvell,orion-system-controller"; - reg = <0x20000 0x120>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - - gate_clk: clock-gating-control@2011c { - compatible = "marvell,kirkwood-gating-clock"; - reg = <0x2011c 0x4>; - clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - l2: l2-cache@20128 { - compatible = "marvell,kirkwood-cache"; - reg = <0x20128 0x4>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - wdt: watchdog-timer@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupt-parent = <&bridge_intc>; - interrupts = <3>; - clocks = <&gate_clk 7>; - status = "okay"; - }; - - cesa: crypto@30000 { - compatible = "marvell,kirkwood-crypto"; - reg = <0x30000 0x10000>; - reg-names = "regs"; - interrupts = <22>; - clocks = <&gate_clk 17>; - marvell,crypto-srams = <&crypto_sram>; - marvell,crypto-sram-size = <0x800>; - status = "okay"; - }; - - usb0: ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - dma0: xor@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60A00 0x100>; - status = "okay"; - clocks = <&gate_clk 8>; - - xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - dma1: xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60B00 0x100>; - status = "okay"; - clocks = <&gate_clk 16>; - - xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; - }; - xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; - }; - }; - - eth0: ethernet-controller@72000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 0>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - eth0port: ethernet0-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <11>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - - eth1: ethernet-controller@76000 { - compatible = "marvell,kirkwood-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76000 0x4000>; - clocks = <&gate_clk 19>; - marvell,tx-checksum-limit = <1600>; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; - status = "disabled"; - - eth1port: ethernet1-port@0 { - compatible = "marvell,kirkwood-eth-port"; - reg = <0>; - interrupts = <15>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ - }; - }; - - sata_phy0: sata-phy@82000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x82000 0x0334>; - clocks = <&gate_clk 14>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - sata_phy1: sata-phy@84000 { - compatible = "marvell,mvebu-sata-phy"; - reg = <0x84000 0x0334>; - clocks = <&gate_clk 15>; - clock-names = "sata"; - #phy-cells = <0>; - status = "ok"; - }; - - audio0: audio-controller@a0000 { - compatible = "marvell,kirkwood-audio"; - #sound-dai-cells = <0>; - reg = <0xa0000 0x2210>; - interrupts = <24>; - clocks = <&gate_clk 9>; - clock-names = "internal"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts b/arch/arm/dts/meson-axg-jethome-jethub-j100.dts deleted file mode 100644 index 5783732dc6f..00000000000 --- a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in> - * Copyright (c) 2020 JetHome - * Author: Aleksandr Kazantsev <ak@tvip.ru> - * Author: Alexey Shevelkin <ash@tvip.ru> - * Author: Vyacheslav Bocharov <adeep@lexina.in> - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg"; - model = "JetHome JetHub J100"; - aliases { - serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* 1024MB RAM */ - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - reserved-memory { - linux,cma { - size = <0x0 0x400000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&scpi_sensors 0>; - trips { - cpu_passive: cpu-passive { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - onewire { - compatible = "w1-gpio"; - gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; - #gpio-cells = <1>; - }; -}; - -&efuse { - sn: sn@32 { - reg = <0x32 0x20>; - }; - - eth_mac: eth_mac@0 { - reg = <0x0 0x6>; - }; - - bt_mac: bt_mac@6 { - reg = <0x6 0x6>; - }; - - wifi_mac: wifi_mac@c { - reg = <0xc 0x6>; - }; - - bid: bid@12 { - reg = <0x12 0x20>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_x_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */ - eth_phy0: ethernet-phy@0 { - /* compatible = "ethernet-phy-id0243.0c54";*/ - max-speed = <100>; - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Internal I2C bus (on CPU module) */ -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - /* RTC */ - pcf8563: pcf8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; -}; - -/* Peripheral I2C bus (on motherboard) */ -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* UART Bluetooth */ -&uart_B { - status = "okay"; - pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; - }; -}; - -/* UART Console */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* UART Wireless module */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&spicc1 { - status = "okay"; - pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>; - pinctrl-names = "default"; -}; - -&gpio { - gpio-line-names = - "", "", "", "", "", // 0 - 4 - "", "", "", "", "", // 5 - 9 - "UserButton", "", "", "", "", // 10 - 14 - "", "", "", "", "", // 15 - 19 - "", "", "", "", "", // 20 - 24 - "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29 - "Output1", "", "", "", "", // 30 - 34 - "", "ZigBeeBOOT", "", "", "", // 35 - 39 - "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44 - "Input2", "Input1", "", "", "", // 45 - 49 - "", "", "", "", "", // 50 - 54 - "", "", "", "", "", // 55 - 59 - "", "", "", "", "", // 60 - 64 - "", "", "", "", "", // 65 - 69 - "", "", "", "", "", // 70 - 74 - "", "", "", "", "", // 75 - 79 - "", "", "", "", "", // 80 - 84 - "", ""; // 85-86 -}; - -&cpu0 { - #cooling-cells = <2>; -}; - -&cpu1 { - #cooling-cells = <2>; -}; - -&cpu2 { - #cooling-cells = <2>; -}; - -&cpu3 { - #cooling-cells = <2>; -}; diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts deleted file mode 100644 index 359589d1dfa..00000000000 --- a/arch/arm/dts/meson-axg-s400.dts +++ /dev/null @@ -1,602 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include <dt-bindings/input/input.h> - -/ { - compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; - model = "Amlogic Meson AXG S400 Development Board"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-next { - label = "Next"; - linux,code = <KEY_NEXT>; - press-threshold-microvolt = <1116000>; /* 62% */ - }; - - button-prev { - label = "Previous"; - linux,code = <KEY_PREVIOUS>; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-wifi { - label = "Wifi"; - linux,code = <KEY_WLAN>; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-voice { - label = "Voice"; - linux,code = <KEY_VOICECOMMAND>; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - }; - - linein: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "everest,es7241"; - VDDA-supply = <&vcc_3v3>; - VDDP-supply = <&vcc_3v3>; - VDDD-supply = <&vcc_3v3>; - status = "okay"; - sound-name-prefix = "Linein"; - }; - - lineout: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "everest,es7154"; - VDD-supply = <&vcc_3v3>; - PVDD-supply = <&vcc_5v>; - status = "okay"; - sound-name-prefix = "Lineout"; - }; - - spdif_dit: audio-codec-2 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - dmics: audio-codec-3 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <7>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - spdif_dir: audio-codec-4 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - status = "okay"; - sound-name-prefix = "DIR"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - speaker-leds { - compatible = "gpio-leds"; - - aled1 { - label = "speaker:aled1"; - gpios = <&gpio_speaker 7 0>; - }; - - aled2 { - label = "speaker:aled2"; - gpios = <&gpio_speaker 6 0>; - }; - - aled3 { - label = "speaker:aled3"; - gpios = <&gpio_speaker 5 0>; - }; - - aled4 { - label = "speaker:aled4"; - gpios = <&gpio_speaker 4 0>; - }; - - aled5 { - label = "speaker:aled5"; - gpios = <&gpio_speaker 3 0>; - }; - - aled6 { - label = "speaker:aled6"; - gpios = <&gpio_speaker 2 0>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S400"; - audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, - <&tdmin_lb>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "SPDIFOUT IN 2", "FRDDR_C OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 2", "TDM_C Capture", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 2", "TDM_C Capture", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TDMIN_LB IN 5", "TDM_C Capture", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 3", "SPDIFIN Capture", - "TODDR_B IN 3", "SPDIFIN Capture", - "TODDR_C IN 3", "SPDIFIN Capture", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker1 Left", "SPK1 OUT_B", - "Speaker1 Right", "SPK1 OUT_C", - "Speaker1 Right", "SPK1 OUT_D", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - assigned-clocks = <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <589824000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - dai-link-6 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&lineout>; - }; - - codec-1 { - sound-dai = <&speaker_amp1>; - }; - - codec-2 { - sound-dai = <&linein>; - }; - - }; - - dai-link-7 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-8 { - sound-dai = <&spdifin>; - - codec { - sound-dai = <&spdif_dir>; - }; - }; - - dai-link-9 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_y_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - interrupt-parent = <&gpio_intc>; - interrupts = <98 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - speaker_amp1: audio-codec@1b { - compatible = "ti,tas5707"; - reg = <0x1b>; - reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&vcc_3v3>; - DVDD-supply = <&vcc_3v3>; - PVDD_A-supply = <&main_12v>; - PVDD_B-supply = <&main_12v>; - PVDD_C-supply = <&main_12v>; - PVDD_D-supply = <&main_12v>; - sound-name-prefix = "SPK1"; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; - - gpio_speaker: gpio-controller@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vddao_3v3>; - }; -}; - -&pdm { - pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, - <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pcieA { - reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcieB { - reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spdifin { - pinctrl-0 = <&spdif_in_a19_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_a20_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_a { - pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, - <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_b { - pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, - <&tdmb_din3_pins>, <&mclk_b_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_c { - pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, - <&tdmc_din1_pins>, <&tdmc_dout2_pins>, - <&mclk_c_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usb_pwr>; -}; diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi deleted file mode 100644 index 3f5254eeb47..00000000000 --- a/arch/arm/dts/meson-axg.dtsi +++ /dev/null @@ -1,1957 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#include <dt-bindings/clock/axg-aoclkc.h> -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/clock/axg-clkc.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/gpio/meson-axg-gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-axg-reset.h> -#include <dt-bindings/power/meson-axg-power.h> - -/ { - compatible = "amlogic,meson-axg"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - - scpi { - compatible = "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clock-controller { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcieA: pcie@f9800000 { - compatible = "amlogic,axg-pcie", "snps,dw-pcie"; - reg = <0x0 0xf9800000 0x0 0x400000>, - <0x0 0xff646000 0x0 0x2000>, - <0x0 0xf9f00000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; - clock-names = "general", "pclk", "port"; - resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; - reset-names = "port", "apb"; - num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - pcieB: pcie@fa000000 { - compatible = "amlogic,axg-pcie", "snps,dw-pcie"; - reg = <0x0 0xfa000000 0x0 0x400000>, - <0x0 0xff648000 0x0 0x2000>, - <0x0 0xfa400000 0x0 0x100000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; - clock-names = "general", "pclk", "port"; - resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; - reset-names = "port", "apb"; - num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - usb: usb@ffe09080 { - compatible = "amlogic,meson-axg-usb-ctrl"; - reg = <0x0 0xffe09080 0x0 0x20>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; - status = "disabled"; - }; - - pcie_phy: phy@ff644000 { - compatible = "amlogic,axg-pcie-phy"; - reg = <0x0 0xff644000 0x0 0x1c>; - resets = <&reset RESET_PCIE_PHY>; - phys = <&mipi_pcie_analog_dphy>; - phy-names = "analog"; - #phy-cells = <0>; - }; - - pdm: audio-controller@ff632000 { - compatible = "amlogic,axg-pdm"; - reg = <0x0 0xff632000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - periphs: bus@ff634000 { - compatible = "simple-bus"; - reg = <0x0 0xff634000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; - - hwrng: rng@18 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x18 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - - pinctrl_periphs: pinctrl@480 { - compatible = "amlogic,meson-axg-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@480 { - reg = <0x0 0x00480 0x0 0x40>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x3c>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 86>; - }; - - i2c0_pins: i2c0 { - mux { - groups = "i2c0_sck", - "i2c0_sda"; - function = "i2c0"; - bias-disable; - }; - }; - - i2c1_x_pins: i2c1_x { - mux { - groups = "i2c1_sck_x", - "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c1_z_pins: i2c1_z { - mux { - groups = "i2c1_sck_z", - "i2c1_sda_z"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c2_a_pins: i2c2_a { - mux { - groups = "i2c2_sck_a", - "i2c2_sda_a"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c2_x_pins: i2c2_x { - mux { - groups = "i2c2_sck_x", - "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c3_a6_pins: i2c3_a6 { - mux { - groups = "i2c3_sda_a6", - "i2c3_sck_a7"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a12_pins: i2c3_a12 { - mux { - groups = "i2c3_sda_a12", - "i2c3_sck_a13"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a19_pins: i2c3_a19 { - mux { - groups = "i2c3_sda_a19", - "i2c3_sck_a20"; - function = "i2c3"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc_ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - eth_rgmii_x_pins: eth-x-rgmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rgmii_y_pins: eth-y-rgmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_x_pins: eth-x-rmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_y_pins: eth-y-rmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y"; - function = "eth"; - bias-disable; - }; - }; - - mclk_b_pins: mclk_b { - mux { - groups = "mclk_b"; - function = "mclk_b"; - bias-disable; - }; - }; - - mclk_c_pins: mclk_c { - mux { - groups = "mclk_c"; - function = "mclk_c"; - bias-disable; - }; - }; - - pdm_dclk_a14_pins: pdm_dclk_a14 { - mux { - groups = "pdm_dclk_a14"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a19_pins: pdm_dclk_a19 { - mux { - groups = "pdm_dclk_a19"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_pins: pdm_din0 { - mux { - groups = "pdm_din0"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_pins: pdm_din1 { - mux { - groups = "pdm_din1"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_pins: pdm_din2 { - mux { - groups = "pdm_din2"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_pins: pdm_din3 { - mux { - groups = "pdm_din3"; - function = "pdm"; - bias-disable; - }; - }; - - pwm_a_a_pins: pwm_a_a { - mux { - groups = "pwm_a_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x18_pins: pwm_a_x18 { - mux { - groups = "pwm_a_x18"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x20_pins: pwm_a_x20 { - mux { - groups = "pwm_a_x20"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_z_pins: pwm_a_z { - mux { - groups = "pwm_a_z"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_a_pins: pwm_b_a { - mux { - groups = "pwm_b_a"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x_pins: pwm_b_x { - mux { - groups = "pwm_b_x"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_z_pins: pwm_b_z { - mux { - groups = "pwm_b_z"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_a_pins: pwm_c_a { - mux { - groups = "pwm_c_a"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x10_pins: pwm_c_x10 { - mux { - groups = "pwm_c_x10"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x17_pins: pwm_c_x17 { - mux { - groups = "pwm_c_x17"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x11_pins: pwm_d_x11 { - mux { - groups = "pwm_d_x11"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x16_pins: pwm_d_x16 { - mux { - groups = "pwm_d_x16"; - function = "pwm_d"; - bias-disable; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - spdif_in_z_pins: spdif_in_z { - mux { - groups = "spdif_in_z"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a1_pins: spdif_in_a1 { - mux { - groups = "spdif_in_a1"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a7_pins: spdif_in_a7 { - mux { - groups = "spdif_in_a7"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a19_pins: spdif_in_a19 { - mux { - groups = "spdif_in_a19"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a20_pins: spdif_in_a20 { - mux { - groups = "spdif_in_a20"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_a1_pins: spdif_out_a1 { - mux { - groups = "spdif_out_a1"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif_out_a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a19_pins: spdif_out_a19 { - mux { - groups = "spdif_out_a19"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a20_pins: spdif_out_a20 { - mux { - groups = "spdif_out_a20"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_z_pins: spdif_out_z { - mux { - groups = "spdif_out_z"; - function = "spdif_out"; - bias-disable; - }; - }; - - spi0_pins: spi0 { - mux { - groups = "spi0_miso", - "spi0_mosi", - "spi0_clk"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss0_pins: spi0_ss0 { - mux { - groups = "spi0_ss0"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss1_pins: spi0_ss1 { - mux { - groups = "spi0_ss1"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss2_pins: spi0_ss2 { - mux { - groups = "spi0_ss2"; - function = "spi0"; - bias-disable; - }; - }; - - spi1_a_pins: spi1_a { - mux { - groups = "spi1_miso_a", - "spi1_mosi_a", - "spi1_clk_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_a_pins: spi1_ss0_a { - mux { - groups = "spi1_ss0_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss1_pins: spi1_ss1 { - mux { - groups = "spi1_ss1"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_x_pins: spi1_x { - mux { - groups = "spi1_miso_x", - "spi1_mosi_x", - "spi1_clk_x"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_x_pins: spi1_ss0_x { - mux { - groups = "spi1_ss0_x"; - function = "spi1"; - bias-disable; - }; - }; - - tdma_din0_pins: tdma_din0 { - mux { - groups = "tdma_din0"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x14_pins: tdma_dout0_x14 { - mux { - groups = "tdma_dout0_x14"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x15_pins: tdma_dout0_x15 { - mux { - groups = "tdma_dout0_x15"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout1_pins: tdma_dout1 { - mux { - groups = "tdma_dout1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_din1_pins: tdma_din1 { - mux { - groups = "tdma_din1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_pins: tdma_fs { - mux { - groups = "tdma_fs"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_slv_pins: tdma_fs_slv { - mux { - groups = "tdma_fs_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_pins: tdma_sclk { - mux { - groups = "tdma_sclk"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_slv_pins: tdma_sclk_slv { - mux { - groups = "tdma_sclk_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdmb_din0_pins: tdmb_din0 { - mux { - groups = "tdmb_din0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din1_pins: tdmb_din1 { - mux { - groups = "tdmb_din1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din2_pins: tdmb_din2 { - mux { - groups = "tdmb_din2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din3_pins: tdmb_din3 { - mux { - groups = "tdmb_din3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout0_pins: tdmb_dout0 { - mux { - groups = "tdmb_dout0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout1_pins: tdmb_dout1 { - mux { - groups = "tdmb_dout1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout2_pins: tdmb_dout2 { - mux { - groups = "tdmb_dout2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout3_pins: tdmb_dout3 { - mux { - groups = "tdmb_dout3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_pins: tdmb_fs { - mux { - groups = "tdmb_fs"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_slv_pins: tdmb_fs_slv { - mux { - groups = "tdmb_fs_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_pins: tdmb_sclk { - mux { - groups = "tdmb_sclk"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_slv_pins: tdmb_sclk_slv { - mux { - groups = "tdmb_sclk_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmc_fs_pins: tdmc_fs { - mux { - groups = "tdmc_fs"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_fs_slv_pins: tdmc_fs_slv { - mux { - groups = "tdmc_fs_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_pins: tdmc_sclk { - mux { - groups = "tdmc_sclk"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_slv_pins: tdmc_sclk_slv { - mux { - groups = "tdmc_sclk_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din0_pins: tdmc_din0 { - mux { - groups = "tdmc_din0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din1_pins: tdmc_din1 { - mux { - groups = "tdmc_din1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din2_pins: tdmc_din2 { - mux { - groups = "tdmc_din2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din3_pins: tdmc_din3 { - mux { - groups = "tdmc_din3"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout0_pins: tdmc_dout0 { - mux { - groups = "tdmc_dout0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout1_pins: tdmc_dout1 { - mux { - groups = "tdmc_dout1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout2_pins: tdmc_dout2 { - mux { - groups = "tdmc_dout2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout3_pins: tdmc_dout3 { - mux { - groups = "tdmc_dout3"; - function = "tdmc"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_x_pins: uart_b_x { - mux { - groups = "uart_tx_b_x", - "uart_rx_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_x_cts_rts_pins: uart_b_x_cts_rts { - mux { - groups = "uart_cts_b_x", - "uart_rts_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_pins: uart_b_z { - mux { - groups = "uart_tx_b_z", - "uart_rx_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_cts_rts_pins: uart_b_z_cts_rts { - mux { - groups = "uart_cts_b_z", - "uart_rts_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_ao_b_z_pins: uart_ao_b_z { - mux { - groups = "uart_ao_tx_b_z", - "uart_ao_rx_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - - uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { - mux { - groups = "uart_ao_cts_b_z", - "uart_ao_rts_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - }; - }; - - hiubus: bus@ff63c000 { - compatible = "simple-bus"; - reg = <0x0 0xff63c000 0x0 0x1c00>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-axg-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,axg-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-axg-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", - "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <250000000>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - - mipi_pcie_analog_dphy: phy { - compatible = "amlogic,axg-mipi-pcie-analog-phy"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - mailbox: mailbox@ff63c404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xff63c404 0 0x4c>; - interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; - - mipi_dphy: phy@ff640000 { - compatible = "amlogic,axg-mipi-dphy"; - reg = <0x0 0xff640000 0x0 0x100>; - clocks = <&clkc CLKID_MIPI_DSI_PHY>; - clock-names = "pclk"; - resets = <&reset RESET_MIPI_PHY>; - reset-names = "phy"; - phys = <&mipi_pcie_analog_dphy>; - phy-names = "analog"; - #phy-cells = <0>; - status = "disabled"; - }; - - audio: bus@ff642000 { - compatible = "simple-bus"; - reg = <0x0 0xff642000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-axg-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - }; - - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-axg-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 15>; - }; - - i2c_ao_sck_4_pins: i2c_ao_sck_4 { - mux { - groups = "i2c_ao_sck_4"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_8_pins: i2c_ao_sck_8 { - mux { - groups = "i2c_ao_sck_8"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_10_pins: i2c_ao_sck_10 { - mux { - groups = "i2c_ao_sck_10"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_5_pins: i2c_ao_sda_5 { - mux { - groups = "i2c_ao_sda_5"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_9_pins: i2c_ao_sda_9 { - mux { - groups = "i2c_ao_sda_9"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_11_pins: i2c_ao_sda_11 { - mux { - groups = "i2c_ao_sda_11"; - function = "i2c_ao"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_ao_tx_a", - "uart_ao_rx_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_ao_cts_a", - "uart_ao_rts_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_ao_tx_b", - "uart_ao_rx_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_ao_cts_b", - "uart_ao_rts_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x02000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_AO_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x07000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-axg-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x38>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - ge2d: ge2d@ff940000 { - compatible = "amlogic,axg-ge2d"; - reg = <0x0 0xff940000 0x0 0x10000>; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_VAPB>; - resets = <&reset RESET_GE2D>; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x25000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x01004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-axg-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x13000 0x0 0x3c>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC0>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x15000 0x0 0x3c>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC1>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-axg-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - fifo-size = <128>; - }; - }; - - apb: bus@ffe00000 { - compatible = "simple-bus"; - reg = <0x0 0xffe00000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; - - sd_emmc_b: sd@5000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x5000 0x0 0x800>; - interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@7000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x7000 0x0 0x800>; - interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb2_phy1: phy@9020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x9020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - }; - }; - - sram: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0x0 0xfffc0000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfffc0000 0x20000>; - - cpu_scp_lpri: scp-sram@13000 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@13400 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi deleted file mode 100644 index 9dbd50820b1..00000000000 --- a/arch/arm/dts/meson-g12-common.dtsi +++ /dev/null @@ -1,2493 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/g12a-clkc.h> -#include <dt-bindings/clock/g12a-aoclkc.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - mmc0 = &sd_emmc_b; /* SD card */ - mmc1 = &sd_emmc_c; /* eMMC */ - mmc2 = &sd_emmc_a; /* SDIO */ - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-124999998 { - opp-hz = /bits/ 64 <124999998>; - opp-microvolt = <800000>; - }; - opp-249999996 { - opp-hz = /bits/ 64 <249999996>; - opp-microvolt = <800000>; - }; - opp-285714281 { - opp-hz = /bits/ 64 <285714281>; - opp-microvolt = <800000>; - }; - opp-399999994 { - opp-hz = /bits/ 64 <399999994>; - opp-microvolt = <800000>; - }; - opp-499999992 { - opp-hz = /bits/ 64 <499999992>; - opp-microvolt = <800000>; - }; - opp-666666656 { - opp-hz = /bits/ 64 <666666656>; - opp-microvolt = <800000>; - }; - opp-799999987 { - opp-hz = /bits/ 64 <799999987>; - opp-microvolt = <800000>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcie: pcie@fc000000 { - compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; - reg = <0x0 0xfc000000 0x0 0x400000>, - <0x0 0xff648000 0x0 0x2000>, - <0x0 0xfc400000 0x0 0x200000>; - reg-names = "elbi", "cfg", "config"; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, - <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; - - clocks = <&clkc CLKID_PCIE_PHY - &clkc CLKID_PCIE_COMB - &clkc CLKID_PCIE_PLL>; - clock-names = "general", - "pclk", - "port"; - resets = <&reset RESET_PCIE_CTRL_A>, - <&reset RESET_PCIE_APB>; - reset-names = "port", - "apb"; - num-lanes = <1>; - phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; - phy-names = "pcie"; - status = "disabled"; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-g12a-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - apb: bus@ff600000 { - compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - - hdmi_tx: hdmi-tx@0 { - compatible = "amlogic,meson-g12a-dw-hdmi"; - reg = <0x0 0x0 0x0 0x10000>; - interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMITX_PHY>, - <&reset RESET_HDMITX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - - apb_efuse: bus@30000 { - compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - - hwrng: rng@218 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x218 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - }; - - acodec: audio-controller@32000 { - compatible = "amlogic,t9015"; - reg = <0x0 0x32000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_AUDIO_CODEC>; - clock-names = "pclk"; - resets = <&reset RESET_AUDIO_CODEC>; - status = "disabled"; - }; - - periphs: bus@34400 { - compatible = "simple-bus"; - reg = <0x0 0x34400 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; - - periphs_pinctrl: pinctrl@40 { - compatible = "amlogic,meson-g12a-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@40 { - reg = <0x0 0x40 0x0 0x4c>, - <0x0 0xe8 0x0 0x18>, - <0x0 0x120 0x0 0x18>, - <0x0 0x2c0 0x0 0x40>, - <0x0 0x340 0x0 0x1c>; - reg-names = "gpio", - "pull", - "pull-enable", - "mux", - "ds"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 86>; - }; - - cec_ao_a_h_pins: cec_ao_a_h { - mux { - groups = "cec_ao_a_h"; - function = "cec_ao_a_h"; - bias-disable; - }; - }; - - cec_ao_b_h_pins: cec_ao_b_h { - mux { - groups = "cec_ao_b_h"; - function = "cec_ao_b_h"; - bias-disable; - }; - }; - - emmc_ctrl_pins: emmc-ctrl { - mux-0 { - groups = "emmc_cmd"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_4b_pins: emmc-data-4b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_8b_pins: emmc-data-8b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_ddc_pins: hdmitx_ddc { - mux { - groups = "hdmitx_sda", - "hdmitx_sck"; - function = "hdmitx"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_hpd_pins: hdmitx_hpd { - mux { - groups = "hdmitx_hpd_in"; - function = "hdmitx"; - bias-disable; - }; - }; - - - i2c0_sda_c_pins: i2c0-sda-c { - mux { - groups = "i2c0_sda_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - - }; - }; - - i2c0_sck_c_pins: i2c0-sck-c { - mux { - groups = "i2c0_sck_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z0_pins: i2c0-sda-z0 { - mux { - groups = "i2c0_sda_z0"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sck_z1_pins: i2c0-sck-z1 { - mux { - groups = "i2c0_sck_z1"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z7_pins: i2c0-sda-z7 { - mux { - groups = "i2c0_sda_z7"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z8_pins: i2c0-sda-z8 { - mux { - groups = "i2c0_sda_z8"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_x_pins: i2c1-sda-x { - mux { - groups = "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_x_pins: i2c1-sck-x { - mux { - groups = "i2c1_sck_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h2_pins: i2c1-sda-h2 { - mux { - groups = "i2c1_sda_h2"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h3_pins: i2c1-sck-h3 { - mux { - groups = "i2c1_sck_h3"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h6_pins: i2c1-sda-h6 { - mux { - groups = "i2c1_sda_h6"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h7_pins: i2c1-sck-h7 { - mux { - groups = "i2c1_sck_h7"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_x_pins: i2c2-sda-x { - mux { - groups = "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_x_pins: i2c2-sck-x { - mux { - groups = "i2c2_sck_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_z_pins: i2c2-sda-z { - mux { - groups = "i2c2_sda_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_z_pins: i2c2-sck-z { - mux { - groups = "i2c2_sck_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_h_pins: i2c3-sda-h { - mux { - groups = "i2c3_sda_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_h_pins: i2c3-sck-h { - mux { - groups = "i2c3_sck_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_a_pins: i2c3-sda-a { - mux { - groups = "i2c3_sda_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_a_pins: i2c3-sck-a { - mux { - groups = "i2c3_sck_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_a_pins: mclk0-a { - mux { - groups = "mclk0_a"; - function = "mclk0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_a_pins: mclk1-a { - mux { - groups = "mclk1_a"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_x_pins: mclk1-x { - mux { - groups = "mclk1_x"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_z_pins: mclk1-z { - mux { - groups = "mclk1_z"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - pdm_din0_a_pins: pdm-din0-a { - mux { - groups = "pdm_din0_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_c_pins: pdm-din0-c { - mux { - groups = "pdm_din0_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_x_pins: pdm-din0-x { - mux { - groups = "pdm_din0_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_z_pins: pdm-din0-z { - mux { - groups = "pdm_din0_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_a_pins: pdm-din1-a { - mux { - groups = "pdm_din1_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_c_pins: pdm-din1-c { - mux { - groups = "pdm_din1_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_x_pins: pdm-din1-x { - mux { - groups = "pdm_din1_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_z_pins: pdm-din1-z { - mux { - groups = "pdm_din1_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_a_pins: pdm-din2-a { - mux { - groups = "pdm_din2_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_c_pins: pdm-din2-c { - mux { - groups = "pdm_din2_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_x_pins: pdm-din2-x { - mux { - groups = "pdm_din2_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_z_pins: pdm-din2-z { - mux { - groups = "pdm_din2_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_a_pins: pdm-din3-a { - mux { - groups = "pdm_din3_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_c_pins: pdm-din3-c { - mux { - groups = "pdm_din3_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_x_pins: pdm-din3-x { - mux { - groups = "pdm_din3_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_z_pins: pdm-din3-z { - mux { - groups = "pdm_din3_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a_pins: pdm-dclk-a { - mux { - groups = "pdm_dclk_a"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_c_pins: pdm-dclk-c { - mux { - groups = "pdm_dclk_c"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_x_pins: pdm-dclk-x { - mux { - groups = "pdm_dclk_x"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_z_pins: pdm-dclk-z { - mux { - groups = "pdm_dclk_z"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pwm_a_pins: pwm-a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_x7_pins: pwm-b-x7 { - mux { - groups = "pwm_b_x7"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x19_pins: pwm-b-x19 { - mux { - groups = "pwm_b_x19"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_c_pins: pwm-c-c { - mux { - groups = "pwm_c_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x5_pins: pwm-c-x5 { - mux { - groups = "pwm_c_x5"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x8_pins: pwm-c-x8 { - mux { - groups = "pwm_c_x8"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x3_pins: pwm-d-x3 { - mux { - groups = "pwm_d_x3"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x6_pins: pwm-d-x6 { - mux { - groups = "pwm_d_x6"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_z_pins: pwm-f-z { - mux { - groups = "pwm_f_z"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_a_pins: pwm-f-a { - mux { - groups = "pwm_f_a"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm-f-x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_h_pins: pwm-f-h { - mux { - groups = "pwm_f_h"; - function = "pwm_f"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux-0 { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_c"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_z_pins: sdcard_z { - mux-0 { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_z"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - spdif_in_a10_pins: spdif-in-a10 { - mux { - groups = "spdif_in_a10"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a12_pins: spdif-in-a12 { - mux { - groups = "spdif_in_a12"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_h_pins: spdif-in-h { - mux { - groups = "spdif_in_h"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif-out-h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif-out-a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a13_pins: spdif-out-a13 { - mux { - groups = "spdif_out_a13"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spicc0_x_pins: spicc0-x { - mux { - groups = "spi0_mosi_x", - "spi0_miso_x", - "spi0_clk_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_ss0_x_pins: spicc0-ss0-x { - mux { - groups = "spi0_ss0_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_c_pins: spicc0-c { - mux { - groups = "spi0_mosi_c", - "spi0_miso_c", - "spi0_ss0_c", - "spi0_clk_c"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc1_pins: spicc1 { - mux { - groups = "spi1_mosi", - "spi1_miso", - "spi1_clk"; - function = "spi1"; - drive-strength-microamp = <4000>; - }; - }; - - spicc1_ss0_pins: spicc1-ss0 { - mux { - groups = "spi1_ss0"; - function = "spi1"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_a_din0_pins: tdm-a-din0 { - mux { - groups = "tdm_a_din0"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_din1_pins: tdm-a-din1 { - mux { - groups = "tdm_a_din1"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_a_dout0_pins: tdm-a-dout0 { - mux { - groups = "tdm_a_dout0"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_dout1_pins: tdm-a-dout1 { - mux { - groups = "tdm_a_dout1"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_fs_pins: tdm-a-fs { - mux { - groups = "tdm_a_fs"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_sclk_pins: tdm-a-sclk { - mux { - groups = "tdm_a_sclk"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_slv_fs_pins: tdm-a-slv-fs { - mux { - groups = "tdm_a_slv_fs"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_slv_sclk_pins: tdm-a-slv-sclk { - mux { - groups = "tdm_a_slv_sclk"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_b_din0_pins: tdm-b-din0 { - mux { - groups = "tdm_b_din0"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din1_pins: tdm-b-din1 { - mux { - groups = "tdm_b_din1"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din2_pins: tdm-b-din2 { - mux { - groups = "tdm_b_din2"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_a_pins: tdm-b-din3-a { - mux { - groups = "tdm_b_din3_a"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_h_pins: tdm-b-din3-h { - mux { - groups = "tdm_b_din3_h"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_dout0_pins: tdm-b-dout0 { - mux { - groups = "tdm_b_dout0"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout1_pins: tdm-b-dout1 { - mux { - groups = "tdm_b_dout1"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout2_pins: tdm-b-dout2 { - mux { - groups = "tdm_b_dout2"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_a_pins: tdm-b-dout3-a { - mux { - groups = "tdm_b_dout3_a"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_h_pins: tdm-b-dout3-h { - mux { - groups = "tdm_b_dout3_h"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_fs_pins: tdm-b-fs { - mux { - groups = "tdm_b_fs"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_sclk_pins: tdm-b-sclk { - mux { - groups = "tdm_b_sclk"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_slv_fs_pins: tdm-b-slv-fs { - mux { - groups = "tdm_b_slv_fs"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_slv_sclk_pins: tdm-b-slv-sclk { - mux { - groups = "tdm_b_slv_sclk"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_c_din0_a_pins: tdm-c-din0-a { - mux { - groups = "tdm_c_din0_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din0_z_pins: tdm-c-din0-z { - mux { - groups = "tdm_c_din0_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_a_pins: tdm-c-din1-a { - mux { - groups = "tdm_c_din1_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_z_pins: tdm-c-din1-z { - mux { - groups = "tdm_c_din1_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din2_a_pins: tdm-c-din2-a { - mux { - groups = "tdm_c_din2_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_pins: eth { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_c_din2_z_pins: tdm-c-din2-z { - mux { - groups = "tdm_c_din2_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_a_pins: tdm-c-din3-a { - mux { - groups = "tdm_c_din3_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_z_pins: tdm-c-din3-z { - mux { - groups = "tdm_c_din3_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_dout0_a_pins: tdm-c-dout0-a { - mux { - groups = "tdm_c_dout0_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout0_z_pins: tdm-c-dout0-z { - mux { - groups = "tdm_c_dout0_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_a_pins: tdm-c-dout1-a { - mux { - groups = "tdm_c_dout1_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_z_pins: tdm-c-dout1-z { - mux { - groups = "tdm_c_dout1_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_a_pins: tdm-c-dout2-a { - mux { - groups = "tdm_c_dout2_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_z_pins: tdm-c-dout2-z { - mux { - groups = "tdm_c_dout2_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_a_pins: tdm-c-dout3-a { - mux { - groups = "tdm_c_dout3_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_z_pins: tdm-c-dout3-z { - mux { - groups = "tdm_c_dout3_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_a_pins: tdm-c-fs-a { - mux { - groups = "tdm_c_fs_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_z_pins: tdm-c-fs-z { - mux { - groups = "tdm_c_fs_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_a_pins: tdm-c-sclk-a { - mux { - groups = "tdm_c_sclk_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_z_pins: tdm-c-sclk-z { - mux { - groups = "tdm_c_sclk_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { - mux { - groups = "tdm_c_slv_fs_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { - mux { - groups = "tdm_c_slv_fs_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { - mux { - groups = "tdm_c_slv_sclk_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { - mux { - groups = "tdm_c_slv_sclk_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart-b { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart-c { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart-c-cts-rts { - mux { - groups = "uart_c_cts", - "uart_c_rts"; - function = "uart_c"; - bias-disable; - }; - }; - }; - }; - - cpu_temp: temperature-sensor@34800 { - compatible = "amlogic,g12a-cpu-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34800 0x0 0x50>; - interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - ddr_temp: temperature-sensor@34c00 { - compatible = "amlogic,g12a-ddr-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34c00 0x0 0x50>; - interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - usb2_phy0: phy@36000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x36000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY20>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - dmc: bus@38000 { - compatible = "simple-bus"; - reg = <0x0 0x38000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - usb2_phy1: phy@3a000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x3a000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY21>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - hiu: bus@3c000 { - compatible = "simple-bus"; - reg = <0x0 0x3c000 0x0 0x1400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; - - hhi: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,g12a-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-g12a-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&rti>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "rdma", "venci", "vencp", "vdac", - "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - }; - }; - - usb3_pcie_phy: phy@46000 { - compatible = "amlogic,g12a-usb3-pcie-phy"; - reg = <0x0 0x46000 0x0 0x2000>; - clocks = <&clkc CLKID_PCIE_PLL>; - clock-names = "ref_clk"; - resets = <&reset RESET_PCIE_PHY>; - reset-names = "phy"; - assigned-clocks = <&clkc CLKID_PCIE_PLL>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - }; - - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_50M>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <8>; - max-speed = <100>; - }; - }; - }; - }; - - pmu: pmu@ff638000 { - reg = <0x0 0xff638000 0x0 0x100>, - <0x0 0xff638c00 0x0 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - rti: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", - "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-g12a-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - - ao_pinctrl: pinctrl@14 { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; - }; - - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_2_3_pins: uart-ao-b-2-3 { - mux { - groups = "uart_ao_b_tx_2", - "uart_ao_b_rx_3"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_8_9_pins: uart-ao-b-8-9 { - mux { - groups = "uart_ao_b_tx_8", - "uart_ao_b_rx_9"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { - mux { - groups = "uart_ao_b_cts", - "uart_ao_b_rts"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - pwm_a_e_pins: pwm-a-e { - mux { - groups = "pwm_a_e"; - function = "pwm_a_e"; - bias-disable; - }; - }; - - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; - }; - }; - }; - - vrtc: rtc@a8 { - compatible = "amlogic,meson-vrtc"; - reg = <0x0 0x000a8 0x0 0x4>; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_AO CLKID_AO_CEC>; - clock-names = "core"; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - cecb_AO: cec@280 { - compatible = "amlogic,meson-g12a-ao-cec"; - reg = <0x0 0x00280 0x0 0x1c>; - interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; - clock-names = "oscin"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; - reg = <0x0 0x2000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; - reg = <0x0 0x7000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x48>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - vdec: video-decoder@ff620000 { - compatible = "amlogic,g12a-vdec"; - reg = <0x0 0xff620000 0x0 0x10000>, - <0x0 0xffd0e180 0x0 0xe4>; - reg-names = "dos", "esparser"; - interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&rti>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>, - <&clkc CLKID_VDEC_HEVCF>; - clock-names = "dos_parser", "dos", "vdec_1", - "vdec_hevc", "vdec_hevcf"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; - }; - - vpu: vpu@ff900000 { - compatible = "amlogic,meson-g12a-vpu"; - reg = <0x0 0xff900000 0x0 0x100000>, - <0x0 0xff63c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x1004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-g12a-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog: watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x13000 0x0 0x44>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x15000 0x0 0x44>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@14000 { - compatible = "amlogic,meson-gxbb-spifc"; - status = "disabled"; - reg = <0x0 0x14000 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_CLK81>; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x19000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-g12a-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - uart_C: serial@22000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x22000 0x0 0x18>; - interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - fifo-size = <128>; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb: usb@ffe09000 { - status = "disabled"; - compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - resets = <&reset RESET_USB>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>, - <&usb3_pcie_phy PHY_TYPE_USB3>; - phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,parkmode-disable-ss-quirk; - }; - }; - - mali: gpu@ffe40000 { - compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; - reg = <0x0 0xffe40000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - arm,no-tick-in-suspend; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - -}; diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi deleted file mode 100644 index 6a1f4dcf648..00000000000 --- a/arch/arm/dts/meson-g12.dtsi +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#include "meson-g12-common.dtsi" -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/power/meson-g12a-power.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> - -/ { - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; -}; - -&apb { - pdm: audio-controller@40000 { - compatible = "amlogic,g12a-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x40000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; - - audio: bus@42000 { - compatible = "simple-bus"; - reg = <0x0 0x42000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,g12a-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifout_b: audio-controller@680 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x680 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_B"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, - <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>; - status = "disabled"; - }; - - toacodec: audio-controller@740 { - compatible = "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOACODEC"; - resets = <&clkc_audio AUD_RESET_TOACODEC>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_G12A_ETH_ID>; -}; - -&vpu { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&sd_emmc_a { - amlogic,dram-access-quirk; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - diff --git a/arch/arm/dts/meson-g12a-radxa-zero.dts b/arch/arm/dts/meson-g12a-radxa-zero.dts deleted file mode 100644 index e3bb6df42ff..00000000000 --- a/arch/arm/dts/meson-g12a-radxa-zero.dts +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "radxa,zero", "amlogic,g12a"; - model = "Radxa Zero"; - - aliases { - serial0 = &uart_AO; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - cvbs-connector { - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - hdmi_pw: regulator-hdmi_pw { - compatible = "regulator-fixed"; - regulator-name = "HDMI_PW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&ao_5v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "RADXA-ZERO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_pw>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "disabled"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts deleted file mode 100644 index 81269ccc249..00000000000 --- a/arch/arm/dts/meson-g12a-sei510.dts +++ /dev/null @@ -1,566 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "seirobotics,sei510", "amlogic,g12a"; - model = "SEI Robotics SEI510"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-onoff { - label = "On/Off"; - linux,code = <KEY_POWER>; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddao_3v3_t: regultor-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SEI510"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, - <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, - <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts deleted file mode 100644 index a26bfe72550..00000000000 --- a/arch/arm/dts/meson-g12a-u200.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - compatible = "amlogic,u200", "amlogic,g12a"; - model = "Amlogic Meson G12A U200 Development Board"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* i2c Touch */ -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; - pinctrl-names = "default"; -}; - -/* i2c CM */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; - pinctrl-names = "default"; -}; - -/* i2c Audio */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc_5v>; -}; diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi deleted file mode 100644 index 7677764eeee..00000000000 --- a/arch/arm/dts/meson-g12a.dtsi +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12a"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&pmu { - compatible = "amlogic,g12a-ddr-pmu"; -}; diff --git a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts deleted file mode 100644 index 31365316b2e..00000000000 --- a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-bananapi.dtsi" - -/ { - compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b"; - model = "BananaPi M2S"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c3; - }; -}; - -/* Camera (CSI) bus */ -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; - pinctrl-names = "default"; -}; - -/* Display (DSI) bus */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts b/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts deleted file mode 100644 index 124a8090108..00000000000 --- a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/arch/arm/dts/meson-g12b-a311d.dtsi b/arch/arm/dts/meson-g12b-a311d.dtsi deleted file mode 100644 index d61f43052a3..00000000000 --- a/arch/arm/dts/meson-g12b-a311d.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <761000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <781000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <811000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <861000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <901000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <951000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <751000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <771000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <771000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <781000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <791000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <831000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <861000>; - }; - - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <911000>; - }; - - opp-2108000000 { - opp-hz = /bits/ 64 <2108000000>; - opp-microvolt = <951000>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1011000>; - }; - }; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts deleted file mode 100644 index 1b0c3881c6a..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> - */ - -/dts-v1/; - -#include "meson-g12b-bananapi-cm4.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b"; - model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module"; - - aliases { - ethernet0 = ðmac; - i2c0 = &i2c1; - i2c1 = &i2c3; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - hdmi_connector: hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-CM4IO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&cecb_AO { - status = "okay"; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* CSI port */ -&i2c1 { - status = "okay"; -}; - -/* DSI port for touchscreen */ -&i2c3 { - status = "okay"; -}; - -/* miniPCIe port with USB + SIM slot */ -&pcie { - status = "okay"; -}; - -&sd_emmc_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -/* Peripheral Only USB-C port */ -&usb { - dr_mode = "peripheral"; - - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi b/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi deleted file mode 100644 index 97e522921b0..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> - */ - -#include "meson-g12b-a311d.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - aliases { - serial0 = &uart_AO; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddio_c: regulator-vddio-c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>; - gpios-states = <1>; - - states = <1800000 0>, - <3300000 1>; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* Ethernet to be enabled in baseboard DT */ -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-mode = "rgmii-txid"; - phy-handle = <&external_phy>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -/* HDMI to be enabled in baseboard DT */ -&hdmi_tx { - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&dc_in>; -}; - -/* "Camera" I2C bus */ -&i2c1 { - pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; - pinctrl-names = "default"; -}; - -/* Main I2C bus */ -&i2c2 { - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; -}; - -/* "ID" I2C bus */ -&i2c3 { - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - - status = "okay"; -}; - -&saradc { - vref-supply = <&vddao_1v8>; - - status = "okay"; -}; - -/* on-module SDIO WiFi */ -&sd_emmc_a { - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - sd-uhs-sdr104; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; - - status = "okay"; - - rtl8822cs: wifi@1 { - reg = <1>; - }; -}; - -/* SD card to be enabled in baseboard DT */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_c>; -}; - -/* on-module eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -/* on-module UART BT */ -&uart_A { - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; - device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; diff --git a/arch/arm/dts/meson-g12b-bananapi.dtsi b/arch/arm/dts/meson-g12b-bananapi.dtsi deleted file mode 100644 index 83709787eb9..00000000000 --- a/arch/arm/dts/meson-g12b-bananapi.dtsi +++ /dev/null @@ -1,521 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */ - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "RST"; - linux,code = <KEY_POWER>; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; - cooling-levels = <0 120 170 220>; - pwms = <&pwm_cd 1 40000 0>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - dc_in: regulator-dc-in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc-5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - compatible = "pwm-regulator"; - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - pwm-supply = <&dc_in>; - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - compatible = "pwm-regulator"; - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - pwm-supply = <&vsys_3v3>; - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - regulator-boot-on; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb-pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M2S"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* Main i2c bus */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; -}; - -&pcie { - status = "okay"; - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_cd { - status = "okay"; - pinctrl-0 = <&pwm_d_x6_pins>; - pinctrl-names = "default"; - pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - /* enable if WiFi/BT board connected */ - status = "disabled"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - sd-uhs-sdr104; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - rtl8822cs: wifi@1 { - reg = <1>; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - /* enable if WiFi/BT board connected */ - status = "disabled"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; - device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; diff --git a/arch/arm/dts/meson-g12b-gsking-x.dts b/arch/arm/dts/meson-g12b-gsking-x.dts deleted file mode 100644 index 6c7bfacbad7..00000000000 --- a/arch/arm/dts/meson-g12b-gsking-x.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GS-King X"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GSKING-X"; - audio-aux-devs = <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1", - "TDMOUT_A IN 1", "FRDDR_B OUT 1", - "TDMOUT_A IN 2", "FRDDR_C OUT 1", - "TDM_A Playback", "TDMOUT_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&tdmif_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-gtking-pro.dts b/arch/arm/dts/meson-g12b-gtking-pro.dts deleted file mode 100644 index 707daf92787..00000000000 --- a/arch/arm/dts/meson-g12b-gtking-pro.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GT-King Pro"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-white { - label = "power:white"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GTKING-PRO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-gtking.dts b/arch/arm/dts/meson-g12b-gtking.dts deleted file mode 100644 index 5d96c144905..00000000000 --- a/arch/arm/dts/meson-g12b-gtking.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b"; - model = "Beelink GT-King"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "GTKING"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi deleted file mode 100644 index f42cf4b8af2..00000000000 --- a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/ { - model = "Khadas VIM3"; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts b/arch/arm/dts/meson-g12b-odroid-go-ultra.dts deleted file mode 100644 index 1e40709610c..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts +++ /dev/null @@ -1,722 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-GO-Ultra"; - - aliases { - serial0 = &uart_AO; - rtc0 = &vrtc; - }; - - adc-joystick-left { - compatible = "adc-joystick"; - io-channels = <&saradc 2>, <&saradc 3>; - poll-interval = <10>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - linux,code = <ABS_Y>; - abs-range = <3150 950>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - axis@1 { - reg = <1>; - linux,code = <ABS_X>; - abs-range = <700 2900>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - }; - - adc-joystick-right { - compatible = "adc-joystick"; - io-channels = <&saradc 0>, <&saradc 1>; - poll-interval = <10>; - #address-cells = <1>; - #size-cells = <0>; - - axis@0 { - reg = <0>; - linux,code = <ABS_RY>; - abs-range = <3150 950>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - axis@1 { - reg = <1>; - linux,code = <ABS_RX>; - abs-range = <800 3000>; - abs-fuzz = <32>; - abs-flat = <64>; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - codec_clk: codec-clk { - compatible = "fixed-clock"; - clock-frequency = <12288000>; - clock-output-names = "codec_clk"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys-polled"; - poll-interval = <10>; - pinctrl-0 = <&keypad_gpio_pins>; - pinctrl-names = "default"; - - volume-up-button { - label = "VOLUME-UP"; - linux,code = <KEY_VOLUMEUP>; - gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>; - }; - volume-down-button { - label = "VOLUME-DOWN"; - linux,code = <KEY_VOLUMEDOWN>; - gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>; - }; - dpad-up-button { - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>; - }; - dpad-down-button { - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>; - }; - dpad-left-button { - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>; - }; - dpad-right-button { - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>; - }; - a-button { - label = "A"; - linux,code = <BTN_EAST>; - gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>; - }; - b-button { - label = "B"; - linux,code = <BTN_SOUTH>; - gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>; - }; - y-button { - label = "Y"; - linux,code = <BTN_WEST>; - gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - }; - x-button { - label = "X"; - linux,code = <BTN_NORTH>; - gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - }; - f1-button { - label = "F1"; - linux,code = <BTN_TRIGGER_HAPPY1>; - gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>; - }; - f2-button { - label = "F2"; - linux,code = <BTN_TRIGGER_HAPPY2>; - gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; - }; - f3-button { - label = "F3"; - linux,code = <BTN_TRIGGER_HAPPY3>; - gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>; - }; - f4-button { - label = "F4"; - linux,code = <BTN_TRIGGER_HAPPY4>; - gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>; - }; - f5-button { - label = "F5"; - linux,code = <BTN_TRIGGER_HAPPY5>; - gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>; - }; - f6-button { - label = "F6"; - linux,code = <BTN_TRIGGER_HAPPY6>; - gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>; - }; - top-left-button { - label = "TOP Left"; - linux,code = <BTN_TL>; - gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>; - }; - top-left2-button { - label = "TOP Left 2"; - linux,code = <BTN_TL2>; - gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; - }; - top-right-button { - label = "TOP Right"; - linux,code = <BTN_TR>; - gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>; - }; - top-right2-button { - label = "TOP Right 2"; - linux,code = <BTN_TR2>; - gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - vdd_sys: regulator-vdd-sys { - compatible = "regulator-fixed"; - regulator-name = "VDD_SYS"; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "Odroid GO Ultra"; - audio-widgets = "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Internal Speakers"; - audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 1", "TDMIN_B OUT", - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker Amplifier INL", "HPOL", - "Speaker Amplifier INR", "HPOR", - "Internal Speakers", "Speaker Amplifier OUTL", - "Internal Speakers", "Speaker Amplifier OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&toddr_a>; - }; - - dai-link-2 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&rk817>; - }; - }; - }; - - speaker_amp: speaker-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "Speaker Amplifier"; - VCC-supply = <&hp_5v>; - }; -}; - -&arb { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -/* RK817 only supports 12.5mV steps, round up the values */ -&cpu_opp_table_0 { - opp-1000000000 { - opp-microvolt = <737500>; - }; - opp-1200000000 { - opp-microvolt = <737500>; - }; - opp-1398000000 { - opp-microvolt = <762500>; - }; - opp-1512000000 { - opp-microvolt = <800000>; - }; - opp-1608000000 { - opp-microvolt = <837500>; - }; - opp-1704000000 { - opp-microvolt = <862500>; - }; - opp-1896000000 { - opp-microvolt = <987500>; - }; - opp-1992000000 { - opp-microvolt = <1012500>; - }; -}; - -/* RK818 only supports 12.5mV steps, round up the values */ -&cpub_opp_table_1 { - opp-1000000000 { - opp-microvolt = <775000>; - }; - opp-1200000000 { - opp-microvolt = <775000>; - }; - opp-1398000000 { - opp-microvolt = <800000>; - }; - opp-1512000000 { - opp-microvolt = <825000>; - }; - opp-1608000000 { - opp-microvolt = <862500>; - }; - opp-1704000000 { - opp-microvolt = <900000>; - }; - opp-1800000000 { - opp-microvolt = <987500>; - }; - opp-1908000000 { - opp-microvolt = <1025000>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - rk818: pmic@1c { - compatible = "rockchip,rk818"; - reg = <0x1c>; - interrupt-parent = <&gpio_intc>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vcc_2v3>; - vcc8-supply = <&vcc_2v3>; - vcc9-supply = <&vddao_3v3>; - boost-supply = <&vdd_sys>; - switch-supply = <&vdd_sys>; - - regulators { - vddcpu_a: DCDC_REG1 { - regulator-name = "vddcpu_a"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1025000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <775000>; - }; - }; - - vdd_ee: DCDC_REG2 { - regulator-name = "vdd_ee"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1250000>; - regulator-ramp-delay = <6001>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <875000>; - }; - }; - - vddq_1v1: DCDC_REG3 { - regulator-name = "vddq_1v1"; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vddao_3v3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vddao_3v3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - hp_5v: DCDC_BOOST { - regulator-always-on; - regulator-boot-on; - regulator-name = "hp_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddio_ao1v8: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vddio_ao1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vddq_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vddq_1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vddio_c: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vddio_c"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: SWITCH_REG { - regulator-name = "vcc_sd"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - OTG_SWITCH { - regulator-name = "otg_switch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio_intc>; - - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ - - vcc1-supply = <&vdd_sys>; - vcc2-supply = <&vdd_sys>; - vcc3-supply = <&vdd_sys>; - vcc4-supply = <&vdd_sys>; - vcc5-supply = <&vdd_sys>; - vcc6-supply = <&vdd_sys>; - vcc7-supply = <&vdd_sys>; - vcc8-supply = <&vdd_sys>; - vcc9-supply = <&rk817_boost>; - - #sound-dai-cells = <0>; - clocks = <&codec_clk>; - clock-names = "mclk"; - - #clock-cells = <1>; - - regulators { - vddcpu_b: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <737500>; - regulator-max-microvolt = <1012500>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vddcpu_b"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_2v3: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <2400000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_2v3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vdd_codec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_lcd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk817_boost: BOOST { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5400000>; - regulator-name = "rk817_boost"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - usb_host: OTG_SWITCH { - regulator-name = "usb_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&clkc_audio { - status = "okay"; -}; - -ð_phy { - status = "disabled"; -}; - -&frddr_a { - status = "okay"; -}; - -&periphs_pinctrl { - keypad_gpio_pins: keypad-gpio { - mux { - groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", - "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7", - "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", - "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", - "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vddio_c>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vddio_ao1v8>; -}; - - -&tdmif_b { - pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; - -&usb2_phy0 { - status = "okay"; -}; - -&usb2_phy1 { - status = "okay"; - phy-supply = <&usb_host>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts deleted file mode 100644 index ce1198ad34e..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2Plus"; -}; - -&vddcpu_a { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_ab 0 1500 0>; -}; - -&vddcpu_b { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_AO_cd 1 1500 0>; -}; - diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts deleted file mode 100644 index a198a91259e..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2"; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi deleted file mode 100644 index 24d0442dffb..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b-odroid.dtsi" - -/ { - aliases { - rtc0 = &rtc; - }; - - dio2133: audio-amplifier-0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - VCC-supply = <&vcc_5v>; - sound-name-prefix = "U19"; - status = "okay"; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "ODROID-N2"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, - <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, - <&dio2133>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "U19 INL", "ACODEC LOLP", - "U19 INR", "ACODEC LORP", - "Lineout", "U19 OUTL", - "Lineout", "U19 OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", "", "", "", - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "PIN_44", /* GPIOA_0 */ - "PIN_46", /* GPIOA_1 */ - "PIN_45", /* GPIOA_2 */ - "PIN_47", /* GPIOA_3 */ - "PIN_26", /* GPIOA_4 */ - "", "", "", "", "", "", - "PIN_42", /* GPIOA_11 */ - "PIN_32", /* GPIOA_12 */ - "PIN_7", /* GPIOA_13 */ - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_33", /* GPIOX_5 */ - "PIN_35", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_36"; /* GPIOX_19 */ - /* - * WARNING: The USB Hub on the Odroid-N2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - hog-0 { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - * The SW1 slide should also be set to the correct position. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - mx25u64: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&toacodec { - status = "okay"; -}; - -&usb { - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid-n2l.dts b/arch/arm/dts/meson-g12b-odroid-n2l.dts deleted file mode 100644 index 70919f40d59..00000000000 --- a/arch/arm/dts/meson-g12b-odroid-n2l.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-n2l", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2L"; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "ODROID-N2L"; - audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>, - <&tdmin_c>, <&tdmin_lb>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-7 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -ð_phy { - status = "disabled"; -}; - -&vddcpu_a { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_ab 0 1500 0>; -}; - -&vddcpu_b { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_AO_cd 1 1500 0>; -}; - -&usb2_phy0 { - phy-supply = <&usb_pwr_en>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr_en>; -}; diff --git a/arch/arm/dts/meson-g12b-odroid.dtsi b/arch/arm/dts/meson-g12b-odroid.dtsi deleted file mode 100644 index 9e12a34b284..00000000000 --- a/arch/arm/dts/meson-g12b-odroid.dtsi +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>; - /* Using Dummy Speed */ - gpio-fan,speed-map = <0 0>, <1 1>; - #cooling-cells = <2>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - label = "n2:blue"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu_thermal { - trips { - cpu_active: cpu-active { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_active>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ddr_thermal { - trips { - ddr_active: ddr-active { - temperature = <60000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_active>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; diff --git a/arch/arm/dts/meson-g12b-radxa-zero2.dts b/arch/arm/dts/meson-g12b-radxa-zero2.dts deleted file mode 100644 index 890f5bfebb0..00000000000 --- a/arch/arm/dts/meson-g12b-radxa-zero2.dts +++ /dev/null @@ -1,489 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - * Copyright (c) 2022 Radxa Limited - * Author: Yuntian Zhang <yt@radxa.com> - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b"; - model = "Radxa Zero2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_A; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - ao_5v: regulator-ao-5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&ao_5v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&ao_5v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "RADXA-ZERO2"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: clock-0 { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23", - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "EMMC_PWRSEQ", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "SD_CD", "PIN_36", - /* GPIOA */ - "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "", - "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5", - /* GPIOX */ - "", "", "", "", "", "", "SDIO_PWRSEQ", "", - "", "", "", "", "", "", "", "", - "", "BT_SHUTDOWN", "", ""; -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29", - "PIN_33", "PIN_37", "FAN", "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&ao_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "disabled"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts deleted file mode 100644 index 7f66f263a2c..00000000000 --- a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-g12b-bananapi.dtsi" - -/ { - compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b"; - model = "BananaPi M2S"; -}; diff --git a/arch/arm/dts/meson-g12b-s922x.dtsi b/arch/arm/dts/meson-g12b-s922x.dtsi deleted file mode 100644 index 1e5d0ee5d54..00000000000 --- a/arch/arm/dts/meson-g12b-s922x.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1896000000 { - opp-hz = /bits/ 64 <1896000000>; - opp-microvolt = <981000>; - }; - - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <751000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <751000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <751000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <751000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <771000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <771000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <791000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <821000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <861000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <891000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <1022000>; - }; - }; -}; diff --git a/arch/arm/dts/meson-g12b-w400.dtsi b/arch/arm/dts/meson-g12b-w400.dtsi deleted file mode 100644 index feb08850474..00000000000 --- a/arch/arm/dts/meson-g12b-w400.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-g12b.dtsi" -#include "meson-g12b-s922x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP1653 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * MP1652 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb1_pow: regulator-usb1-pow { - compatible = "regulator-fixed"; - regulator-name = "USB1_POW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* connected to SY6280A Power Switch */ - gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to USB3 Type-A Port power enable */ - gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&usb1_pow>; -}; - -&usb2_phy1 { - phy-supply = <&usb1_pow>; -}; diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi deleted file mode 100644 index 75ff00fb2e4..00000000000 --- a/arch/arm/dts/meson-g12b.dtsi +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12b"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu100>; - }; - - core1 { - cpu = <&cpu101>; - }; - - core2 { - cpu = <&cpu102>; - }; - - core3 { - cpu = <&cpu103>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu102: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu103: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; -}; - -&clkc { - compatible = "amlogic,g12b-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&mali { - dma-coherent; -}; - -&pmu { - compatible = "amlogic,g12b-ddr-pmu"; -}; diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi b/arch/arm/dts/meson-gx-libretech-pc.dtsi deleted file mode 100644 index 4e84ab87cc7..00000000000 --- a/arch/arm/dts/meson-gx-libretech-pc.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-update { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <1300000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&vcc5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-PC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Speaker", "7J4-14 LEFT", - "Speaker", "7J4-11 RIGHT"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "7J4-14 LEFT", "AU2 OUTL", - "7J4-11 RIGHT", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - reg = <0>; - max-speed = <1000>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the reset pin of the usb HUB is driven high to take - * it out of reset. - */ - usb1_rst_pins: usb1_rst_irq { - mux { - groups = "GPIODV_3"; - function = "gpio_periphs"; - bias-disable; - output-high; - }; - }; - - /* Make sure the phy irq pin is properly configured as input */ - eth_phy_irq_pins: eth_phy_irq { - mux { - groups = "GPIOZ_15"; - function = "gpio_periphs"; - bias-disable; - output-disable; - }; - }; -}; - -&hdmi_tx { - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc5v>; - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_C { - pinctrl-0 = <&i2c_c_dv18_pins>; - pinctrl-names = "default"; - status = "okay"; - - rtc: rtc@51 { - reg = <0x51>; - compatible = "nxp,pcf8563"; - #clock-cells = <0>; - clock-output-names = "rtc_clkout"; - }; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_3_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&saradc { - vref-supply = <&vddio_ao18>; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <200000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_boot>; - - status = "okay"; -}; - -&spifc { - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - status = "okay"; - - gd25lq128: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <12000000>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb1_rst_pins>; - pinctrl-names = "default"; - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm/dts/meson-gx-mali450.dtsi b/arch/arm/dts/meson-gx-mali450.dtsi deleted file mode 100644 index f9771b51c85..00000000000 --- a/arch/arm/dts/meson-gx-mali450.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/ { - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - mali: gpu@c0000 { - compatible = "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - operating-points-v2 = <&gpu_opp_table>; - }; -}; diff --git a/arch/arm/dts/meson-gx-p23x-q20x.dtsi b/arch/arm/dts/meson-gx-p23x-q20x.dtsi deleted file mode 100644 index dafc841f7c1..00000000000 --- a/arch/arm/dts/meson-gx-p23x-q20x.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either - * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. - */ - -#include <dt-bindings/sound/meson-aiu.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - spdif_dit: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "P230-Q200"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLP", - "AU2 INR", "ACODEC LORP", - "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-4 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-5 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi deleted file mode 100644 index 11f89bfecb5..00000000000 --- a/arch/arm/dts/meson-gx.dtsi +++ /dev/null @@ -1,675 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/meson-gxbb-power.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - mmc0 = &sd_emmc_b; /* SD card */ - mmc1 = &sd_emmc_c; /* eMMC */ - mmc2 = &sd_emmc_a; /* SDIO */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@10000000 { - reg = <0x0 0x10000000 0x0 0x200000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&scpi_sensors 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth-mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - - scpi { - compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clocks-0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cbus: bus@c1100000 { - compatible = "simple-bus"; - reg = <0x0 0xc1100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x9c>; - #reset-cells = <1>; - }; - - aiu: audio-controller@5400 { - compatible = "amlogic,aiu"; - #sound-dai-cells = <2>; - sound-name-prefix = "AIU"; - reg = <0x0 0x5400 0x0 0x2ac>; - interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "i2s", "spdif"; - status = "disabled"; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84c0 0x0 0x18>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - fifo-size = <128>; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84dc 0x0 0x18>; - interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x0 0x8680 0x0 0x34>; - #io-channel-cells = <1>; - interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x8700 0x0 0x18>; - interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc: spi@8d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0x0 0x08d80 0x0 0x80>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,gic-400"; - reg = <0x0 0xc4301000 0 0x1000>, - <0x0 0xc4302000 0 0x2000>, - <0x0 0xc4304000 0 0x2000>, - <0x0 0xc4306000 0 0x2000>; - interrupt-controller; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - sram: sram@c8000000 { - compatible = "mmio-sram"; - reg = <0x0 0xc8000000 0x0 0x14000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc8000000 0x14000>; - - cpu_scp_lpri: scp-sram@0 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@200 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - - aobus: bus@c8100000 { - compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004c0 0x0 0x18>; - interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004e0 0x0 0x18>; - interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x500 0x0 0x20>; - interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; - reg = <0x0 0x00550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@580 { - compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; - }; - }; - - vdec: video-codec@c8820000 { - compatible = "amlogic,gx-vdec"; - reg = <0x0 0xc8820000 0x0 0x10000>, - <0x0 0xc110a580 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&sysctrl_AO>; - amlogic,canvas = <&canvas>; - }; - - periphs: bus@c8834000 { - compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - - hwrng: rng@0 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - }; - - dmcbus: bus@c8838000 { - compatible = "simple-bus"; - reg = <0x0 0xc8838000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - hiubus: bus@c883c000 { - compatible = "simple-bus"; - reg = <0x0 0xc883c000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - pwrc: power-controller { - compatible = "amlogic,meson-gxbb-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; - }; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000>, - <0x0 0xc8834540 0x0 0x4>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; - status = "disabled"; - }; - - apb: apb@d0000000 { - compatible = "simple-bus"; - reg = <0x0 0xd0000000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x800>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sd_emmc_b: mmc@72000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x800>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sd_emmc_c: mmc@74000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x800>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; - - vpu: vpu@d0100000 { - compatible = "amlogic,meson-gx-vpu"; - reg = <0x0 0xd0100000 0x0 0x100000>, - <0x0 0xc883c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - hdmi_tx: hdmi-tx@c883a000 { - compatible = "amlogic,meson-gx-dw-hdmi"; - reg = <0x0 0xc883a000 0x0 0x1c>; - interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - sound-name-prefix = "HDMITX"; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - }; -}; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi deleted file mode 100644 index 478e755cc87..00000000000 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-gx-mali450.dtsi" - -&mali { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_GP0_PLL>; - assigned-clock-rates = <744000000>; -}; diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts deleted file mode 100644 index 213a0705ebd..00000000000 --- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s805x.dtsi" - -/ { - compatible = "libretech,aml-s805x-ac", "amlogic,s805x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S805X-AC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - /* - * The pads are present but no connector is soldered on - * 2J2, so keep this off by default. - */ - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - dc_5v: regulator-dc_5v { - compatible = "regulator-fixed"; - regulator-name = "DC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - - /* - * This is controlled by GPIOAO_9 we reserve this but - * claiming it as done below reset the board anyway - * Need to investigate this - * - * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-AC"; - audio-widgets = "Speaker", "9J5-3 LEFT", - "Speaker", "9J5-2 RIGHT"; - audio-routing = "9J5-3 LEFT", "ACODEC LOLN", - "9J5-2 RIGHT", "ACODEC LORN"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "7J1 Header Pin31", - "", "", "", "", - "IR In", - "HDMI CEC", - "5V VCCK Regulator", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "", "7J1 Header Pin13", - "7J1 Header Pin15", - "7J1 Header Pin7", - "7J1 Header Pin12", - "7J1 Header Pin16", - "7J1 Header Pin18", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", - "", "SPI NOR Chip Select", - /* Bank CARD */ - "", "", "", "", "", "", "", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "7J1 Header Pin27", "7J1 Header Pin28", "", - "7J1 Header Pin29", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "", "", "7J1 Header Pin32", "", "", - /* Bank GPIOCLK */ - "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm/dts/meson-gxl-s805x.dtsi b/arch/arm/dts/meson-gxl-s805x.dtsi deleted file mode 100644 index 29975849822..00000000000 --- a/arch/arm/dts/meson-gxl-s805x.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "amlogic,s805x", "amlogic,meson-gxl"; -}; - -/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ -&gpu_opp_table { - opp-744000000 { - status = "disabled"; - }; -}; - -&mali { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; diff --git a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts b/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts deleted file mode 100644 index 100a1cfeea1..00000000000 --- a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s905d-pc", "amlogic,s905d", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905D-PC"; -}; diff --git a/arch/arm/dts/meson-gxl-s905d.dtsi b/arch/arm/dts/meson-gxl-s905d.dtsi deleted file mode 100644 index 43321919547..00000000000 --- a/arch/arm/dts/meson-gxl-s905d.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905d", "amlogic,meson-gxl"; -}; diff --git a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts deleted file mode 100644 index a18d6d241a5..00000000000 --- a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in> - * Copyright (c) 2020 JetHome - * Author: Aleksandr Kazantsev <ak@tvip.ru> - * Author: Alexey Shevelkin <ash@tvip.ru> - * Author: Vyacheslav Bocharov <adeep@lexina.in> - */ - -/dts-v1/; - -#include "meson-gxl.dtsi" - -/ { - compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl"; - model = "JetHome JetHub J80"; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - reserved-memory { - linux,cma { - size = <0x0 0x1000000>; - }; - }; - - aliases { - serial0 = &uart_AO; /* Console */ - serial1 = &uart_A; /* Bluetooth */ - serial2 = &uart_AO_B; /* Wireless module 1 */ - serial3 = &uart_C; /* Wireless module 2 */ - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&efuse { - bt_mac: bt-mac@6 { - reg = <0x6 0x6>; - }; - - wifi_mac: wifi-mac@c { - reg = <0xc 0x6>; - }; -}; - -&sn { - reg = <0x32 0x20>; -}; - -ð_mac { - reg = <0x0 0x6>; -}; - -&bid { - reg = <0x12 0x20>; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* Console UART */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* S905W only has access to its internal PHY */ -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&internal_phy { - status = "okay"; - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "realtek,rtl8822cs-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_C { - status = "okay"; - pinctrl-0 = <&uart_c_pins>; - pinctrl-names = "default"; -}; - -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&i2c_B { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_b_pins>; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts deleted file mode 100644 index 02f81839d4e..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Khadas VIM"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - aliases { - serial2 = &uart_AO_B; - ethernet0 = ðmac; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "KHADAS-VIM"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - linux,rc-map-name = "rc-khadas"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Power Key In", - "J9 Header Pin35", - "J9 Header Pin16", - "J9 Header Pin15", - "J9 Header Pin33", - "IR In", - "HDMI CEC", - "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Power OFF", - "VCCK Enable", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "SPDIF", - "J9 Header Pin37", - "J9 Header Pin30", - "J9 Header Pin29", - "J9 Header Pin32", - "J9 Header Pin31", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "", "BOOT_MODE", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", - /* Bank GPIOCLK */ - "", "J9 Header Pin39"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; -}; - -&sd_emmc_a { - max-frequency = <100000000>; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&usb { - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts deleted file mode 100644 index 6c4e68e0e62..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts +++ /dev/null @@ -1,313 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC V2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC 1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-CC-V2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - hdmi-supply = <&vcc5v>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vcc_1v8>; - - status = "okay"; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - nor_4u1: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts deleted file mode 100644 index 82bfabfbd39..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-system { - label = "librecomputer:system-status"; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - - led-blue { - label = "librecomputer:blue"; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_card: regulator-vcc-card { - compatible = "regulator-gpio"; - - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "LIBRETECH-CC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Blue LED", - "SDCard Voltage Switch", - "7J1 Header Pin5", - "7J1 Header Pin3", - "7J1 Header Pin12", - "IR In", - "9J3 Switch HDMI CEC/7J1 Header Pin11", - "7J1 Header Pin13", - /* GPIO_TEST_N */ - "7J1 Header Pin15"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "9J1 Header Pin2", - "Analog Audio Mute", - "2J3 Header Pin6", - "2J3 Header Pin5", - "2J3 Header Pin4", - "2J3 Header Pin3", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "Green LED", "VCCK Enable", - "7J1 Header Pin27", "7J1 Header Pin28", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "7J1 Header Pin16", "7J1 Header Pin18", - "7J1 Header Pin32", "7J1 Header Pin29", - "7J1 Header Pin31", - /* Bank GPIOCLK */ - "7J1 Header Pin7", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * even though the schematics don't show it: - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts deleted file mode 100644 index 9b4ea6a4939..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-p212.dts +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905X) P212 Development Board"; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "S905X-P212"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi deleted file mode 100644 index a150cc0e18f..00000000000 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-gxl-s905x.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm/dts/meson-gxl-s905x.dtsi b/arch/arm/dts/meson-gxl-s905x.dtsi deleted file mode 100644 index 40c19f69e9d..00000000000 --- a/arch/arm/dts/meson-gxl-s905x.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905x", "amlogic,meson-gxl"; -}; - -/* S905X only has access to its internal PHY */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi deleted file mode 100644 index 17bcfa4702e..00000000000 --- a/arch/arm/dts/meson-gxl.dtsi +++ /dev/null @@ -1,940 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gx.dtsi" -#include <dt-bindings/clock/gxbb-clkc.h> -#include <dt-bindings/clock/gxbb-aoclkc.h> -#include <dt-bindings/gpio/meson-gxl-gpio.h> -#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> - -/ { - compatible = "amlogic,meson-gxl"; - - soc { - usb: usb@d0078080 { - compatible = "amlogic,meson-gxl-usb-ctrl"; - reg = <0x0 0xd0078080 0x0 0x20>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; - - dwc2: usb@c9100000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@c9000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xc9000000 0x0 0x100000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - acodec: audio-controller@c8832000 { - compatible = "amlogic,t9015"; - reg = <0x0 0xc8832000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_ACODEC>; - clock-names = "pclk"; - resets = <&reset RESET_ACODEC>; - status = "disabled"; - }; - - crypto: crypto@c883e000 { - compatible = "amlogic,gxl-crypto"; - reg = <0x0 0xc883e000 0x0 0x36>; - interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc CLKID_BLKMV>; - clock-names = "blkmv"; - status = "okay"; - }; - }; -}; - -&aiu { - compatible = "amlogic,aiu-gxl", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&apb { - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - usb2_phy1: phy@78020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_0_1_pins: uart_ao_b_0_1 { - mux { - groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_a_8_pins: pwm_ao_a_8 { - mux { - groups = "pwm_ao_a_8"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_b_6_pins: pwm_ao_b_6 { - mux { - groups = "pwm_ao_b_6"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_9_pins: spdif_out_ao_9 { - mux { - groups = "spdif_out_ao_9"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gxl-gpio-intc", - "amlogic,meson-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxl-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 100>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_idle_high_pins: spi-idle-high-pins { - mux { - groups = "spi_sclk"; - bias-pull-up; - }; - }; - - spi_idle_low_pins: spi-idle-low-pins { - mux { - groups = "spi_sclk"; - bias-pull-down; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - i2c_c_dv18_pins: i2c_c_dv18 { - mux { - groups = "i2c_sck_c_dv19", - "i2c_sda_c_dv18"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_pins: eth_c { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_link_led_pins: eth_link_led { - mux { - groups = "eth_link_led"; - function = "eth_led"; - bias-disable; - }; - }; - - eth_act_led_pins: eth_act_led { - mux { - groups = "eth_act_led"; - function = "eth_led"; - }; - }; - - pwm_a_pins: pwm_a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_pins: pwm_c { - mux { - groups = "pwm_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_clk_pins: pwm_f_clk { - mux { - groups = "pwm_f_clk"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ch01_pins: i2s_out_ch01 { - mux { - groups = "i2s_out_ch01"; - function = "i2s_out"; - bias-disable; - }; - }; - i2sout_ch23_z_pins: i2sout_ch23_z { - mux { - groups = "i2sout_ch23_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_z_pins: i2sout_ch45_z { - mux { - groups = "i2sout_ch45_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_z_pins: i2sout_ch67_z { - mux { - groups = "i2sout_ch67_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif_out_ao_h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - bias-disable; - }; - }; - }; - - eth_phy_mux: mdio@558 { - reg = <0x0 0x558 0x0 0xc>; - compatible = "amlogic,gxl-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "ref"; - mdio-parent-bus = <&mdio0>; - - external_mdio: mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - internal_mdio: mdio@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_phy: ethernet-phy@8 { - compatible = "ethernet-phy-id0181.4400"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <8>; - max-speed = <100>; - }; - }; - }; -}; - -&pwrc { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "dvin", "rdma", "venci", "vencp", - "vdac", "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/arch/arm/dts/meson-gxm-gt1-ultimate.dts b/arch/arm/dts/meson-gxm-gt1-ultimate.dts deleted file mode 100644 index 2c267884cc1..00000000000 --- a/arch/arm/dts/meson-gxm-gt1-ultimate.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> - -/ { - compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm"; - model = "Beelink GT1 Ultimate"; - - leds { - compatible = "gpio-leds"; - - led-white { - color = <LED_COLOR_ID_WHITE>; - function = LED_FUNCTION_POWER; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <10000>; - }; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&ir { - linux,rc-map-name = "rc-beelink-gs1"; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts deleted file mode 100644 index 74897a15489..00000000000 --- a/arch/arm/dts/meson-gxm-khadas-vim2.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * Copyright (c) 2017 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/meson-aiu.h> - -/ { - compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; - model = "Khadas VIM2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - gpio_fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH - &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; - /* Dummy RPM values since fan is optional */ - gpio-fan,speed-map = - <0 0>, - <1 1>, - <2 2>, - <3 3>; - #cooling-cells = <2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-1 { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "KHADAS-VIM2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu_cooling_maps { - map0 { - cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* - * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe - * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -/* This one is connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts b/arch/arm/dts/meson-gxm-s912-libretech-pc.dts deleted file mode 100644 index 444c249863c..00000000000 --- a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s912-pc", "amlogic,s912", - "amlogic,meson-gxm"; - model = "Libre Computer AML-S912-PC"; - - typec2_vbus: regulator-typec2_vbus { - compatible = "regulator-fixed"; - regulator-name = "TYPEC2_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v>; - - gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the irq pin of the TYPE C controller is not driven - * by the SoC. - */ - fusb302_irq_pins: fusb302_irq { - mux { - groups = "GPIODV_0"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&i2c_C { - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - pinctrl-0 = <&fusb302_irq_pins>; - pinctrl-names = "default"; - interrupt-parent = <&gpio_intc>; - interrupts = <59 IRQ_TYPE_LEVEL_LOW>; - - vbus-supply = <&typec2_vbus>; - - status = "okay"; - }; -}; - -&usb2_phy2 { - phy-supply = <&typec2_vbus>; -}; diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts deleted file mode 100644 index f8c40340b9c..00000000000 --- a/arch/arm/dts/meson-gxm-wetek-core2.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com> - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> - -/ { - compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm"; - model = "WeTek Core 2"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-update { - label = "update"; - linux,code = <KEY_VENDOR>; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - button-power { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Disabled as Realtek RTL8152 USB provides Ethernet */ -ðmac { - status = "disabled"; -}; - -&internal_phy { - status = "disabled"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi deleted file mode 100644 index 411cc312fc6..00000000000 --- a/arch/arm/dts/meson-gxm.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#include "meson-gxl.dtsi" - -/ { - compatible = "amlogic,meson-gxm"; - - cpus { - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - capacity-dmips-mhz = <1024>; - }; - - cpu1: cpu@1 { - capacity-dmips-mhz = <1024>; - }; - - cpu2: cpu@2 { - capacity-dmips-mhz = <1024>; - }; - - cpu3: cpu@3 { - capacity-dmips-mhz = <1024>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - }; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - usb2_phy2: phy@78040 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78040 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - mali: gpu@c0000 { - compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - operating-points-v2 = <&gpu_opp_table>; - }; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; -}; - -&cpu_cooling_maps { - map0 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&saradc { - compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; -}; - -&scpi_dvfs { - clock-indices = <0 1>; - clock-output-names = "vbig", "vlittle"; -}; - -&vpu { - compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; -}; - -&usb { - compatible = "amlogic,meson-gxm-usb-ctrl"; - - phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; - phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; -}; - -&vdec { - compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; -}; diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi deleted file mode 100644 index 3cf4ecb6d52..00000000000 --- a/arch/arm/dts/meson-khadas-vim3.dtsi +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = <KEY_FN>; - press-threshold-microvolt = <10000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-white { - color = <LED_COLOR_ID_WHITE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-red { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - - sound { - compatible = "amlogic,axg-sound-card"; - model = "KHADAS-VIM3"; - audio-aux-devs = <&tdmin_a>, <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* hdmi glue */ - dai-link-7 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu_thermal { - trips { - cpu_active: cpu-active { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_active>; - cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - khadas_mcu: system-controller@18 { - compatible = "khadas,mcu"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - gpio_expander: gpio-controller@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - vcc-supply = <&vcc_3v3>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q128: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128fw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&tdmif_a { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts b/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts deleted file mode 100644 index 586034316ec..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1-bananapi.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-m2-pro", "amlogic,sm1"; - model = "Banana Pi BPI-M2-PRO"; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M2-PRO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi-m5.dts b/arch/arm/dts/meson-sm1-bananapi-m5.dts deleted file mode 100644 index f045bf85163..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi-m5.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1-bananapi.dtsi" -#include <dt-bindings/sound/meson-g12a-toacodec.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "bananapi,bpi-m5", "amlogic,sm1"; - model = "Banana Pi BPI-M5"; - - /* TOFIX: handle CVBS_DET on SARADC channel 0 */ - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "BPI-M5"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, - <&tdmin_a>, <&tdmin_b>, <&tdmin_c>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "Lineout", "ACODEC LOLP", - "Lineout", "ACODEC LORP"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - - -&clkc_audio { - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toacodec { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; diff --git a/arch/arm/dts/meson-sm1-bananapi.dtsi b/arch/arm/dts/meson-sm1-bananapi.dtsi deleted file mode 100644 index 17045ff81c6..00000000000 --- a/arch/arm/dts/meson-sm1-bananapi.dtsi +++ /dev/null @@ -1,435 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 BayLibre SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-sm1.dtsi" -#include <dt-bindings/leds/common.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-sw3 { - label = "SW3"; - linux,code = <BTN_3>; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key { - label = "SW1"; - linux,code = <BTN_1>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vddio_c: regulator-vddio_c { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_C"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>; - gpios-states = <1>; - - states = <1800000 0>, - <3300000 1>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - /* USB Hub Power Enable */ - vl_pwr_en: regulator-vl_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "VL_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&arb { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii-txid"; - phy-handle = <&external_phy>; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "ETH_MDIO", /* GPIOZ_0 */ - "ETH_MDC", /* GPIOZ_1 */ - "ETH_RXCLK", /* GPIOZ_2 */ - "ETH_RX_DV", /* GPIOZ_3 */ - "ETH_RXD0", /* GPIOZ_4 */ - "ETH_RXD1", /* GPIOZ_5 */ - "ETH_RXD2", /* GPIOZ_6 */ - "ETH_RXD3", /* GPIOZ_7 */ - "ETH_TXCLK", /* GPIOZ_8 */ - "ETH_TXEN", /* GPIOZ_9 */ - "ETH_TXD0", /* GPIOZ_10 */ - "ETH_TXD1", /* GPIOZ_11 */ - "ETH_TXD2", /* GPIOZ_12 */ - "ETH_TXD3", /* GPIOZ_13 */ - "ETH_INTR", /* GPIOZ_14 */ - "ETH_NRST", /* GPIOZ_15 */ - /* GPIOH */ - "HDMI_SDA", /* GPIOH_0 */ - "HDMI_SCL", /* GPIOH_1 */ - "HDMI_HPD", /* GPIOH_2 */ - "HDMI_CEC", /* GPIOH_3 */ - "VL-RST_N", /* GPIOH_4 */ - "CON1-P36", /* GPIOH_5 */ - "VL-PWREN", /* GPIOH_6 */ - "WiFi_3V3_1V8", /* GPIOH_7 */ - "TFLASH_VDD_EN", /* GPIOH_8 */ - /* BOOT */ - "eMMC_D0", /* BOOT_0 */ - "eMMC_D1", /* BOOT_1 */ - "eMMC_D2", /* BOOT_2 */ - "eMMC_D3", /* BOOT_3 */ - "eMMC_D4", /* BOOT_4 */ - "eMMC_D5", /* BOOT_5 */ - "eMMC_D6", /* BOOT_6 */ - "eMMC_D7", /* BOOT_7 */ - "eMMC_CLK", /* BOOT_8 */ - "", - "eMMC_CMD", /* BOOT_10 */ - "", - "eMMC_RST#", /* BOOT_12 */ - "eMMC_DS", /* BOOT_13 */ - "", "", - /* GPIOC */ - "SD_D0_B", /* GPIOC_0 */ - "SD_D1_B", /* GPIOC_1 */ - "SD_D2_B", /* GPIOC_2 */ - "SD_D3_B", /* GPIOC_3 */ - "SD_CLK_B", /* GPIOC_4 */ - "SD_CMD_B", /* GPIOC_5 */ - "CARD_EN_DET", /* GPIOC_6 */ - "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "CON1-P27", /* GPIOA_14 */ - "CON1-P28", /* GPIOA_15 */ - /* GPIOX */ - "CON1-P16", /* GPIOX_0 */ - "CON1-P18", /* GPIOX_1 */ - "CON1-P22", /* GPIOX_2 */ - "CON1-P11", /* GPIOX_3 */ - "CON1-P13", /* GPIOX_4 */ - "CON1-P07", /* GPIOX_5 */ - "CON1-P33", /* GPIOX_6 */ - "CON1-P15", /* GPIOX_7 */ - "CON1-P19", /* GPIOX_8 */ - "CON1-P21", /* GPIOX_9 */ - "CON1-P24", /* GPIOX_10 */ - "CON1-P23", /* GPIOX_11 */ - "CON1-P08", /* GPIOX_12 */ - "CON1-P10", /* GPIOX_13 */ - "CON1-P29", /* GPIOX_14 */ - "CON1-P31", /* GPIOX_15 */ - "CON1-P26", /* GPIOX_16 */ - "CON1-P03", /* GPIOX_17 */ - "CON1-P05", /* GPIOX_18 */ - "CON1-P32"; /* GPIOX_19 */ - - /* - * WARNING: The USB Hub needs a reset signal to be turned high in - * order to be detected by the USB Controller. This signal should - * be handled by a USB specific power sequence to reset the Hub - * when the USB bus is powered down. - */ - usb-hub-hog { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "DEBUG TX", /* GPIOAO_0 */ - "DEBUG RX", /* GPIOAO_1 */ - "SYS_LED2", /* GPIOAO_2 */ - "UPDATE_KEY", /* GPIOAO_3 */ - "CON1-P40", /* GPIOAO_4 */ - "IR_IN", /* GPIOAO_5 */ - "TF_3V3N_1V8_EN", /* GPIOAO_6 */ - "CON1-P35", /* GPIOAO_7 */ - "CON1-P12", /* GPIOAO_8 */ - "CON1-P37", /* GPIOAO_9 */ - "CON1-P38", /* GPIOAO_10 */ - "SYS_LED", /* GPIOAO_11 */ - /* GPIOE */ - "VDDEE_PWM", /* GPIOE_0 */ - "VDDCPU_PWM", /* GPIOE_1 */ - "TF_PWR_EN"; /* GPIOE_2 */ -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&dc_in>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - /* TOFIX: SD card is barely usable in SDR modes */ - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&vddio_c>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&vl_pwr_en>; -}; diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts deleted file mode 100644 index f2c09814359..00000000000 --- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include "meson-khadas-vim3.dtsi" -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "khadas,vim3l", "amlogic,sm1"; - model = "Khadas VIM3L"; - - vddcpu: regulator-vddcpu { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - model = "G12B-KHADAS-VIM3L"; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 13", "TDM_A Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT"; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ - -&sd_emmc_a { - sd-uhs-sdr50; -}; diff --git a/arch/arm/dts/meson-sm1-odroid-c4.dts b/arch/arm/dts/meson-sm1-odroid-c4.dts deleted file mode 100644 index 8c30ce63686..00000000000 --- a/arch/arm/dts/meson-sm1-odroid-c4.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -#include "meson-sm1-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-c4", "amlogic,sm1"; - model = "Hardkernel ODROID-C4"; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - sound { - model = "ODROID-C4"; - }; -}; - -&gpio { - /* - * WARNING: The USB Hub on the Odroid-C4 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - hog-0 { - gpio-hog; - gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&ir { - linux,rc-map-name = "rc-odroid"; -}; diff --git a/arch/arm/dts/meson-sm1-odroid-hc4.dts b/arch/arm/dts/meson-sm1-odroid-hc4.dts deleted file mode 100644 index f3f953225bf..00000000000 --- a/arch/arm/dts/meson-sm1-odroid-hc4.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -/dts-v1/; - -#include "meson-sm1-odroid.dtsi" - -/ { - compatible = "hardkernel,odroid-hc4", "amlogic,sm1"; - model = "Hardkernel ODROID-HC4"; - - aliases { - rtc0 = &rtc; - rtc1 = &vrtc; - }; - - fan0: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; - cooling-levels = <0 120 170 220>; - pwms = <&pwm_cd 1 40000 0>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = <LED_COLOR_ID_BLUE>; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - led-red { - color = <LED_COLOR_ID_RED>; - function = LED_FUNCTION_POWER; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */ - p12v_0: regulator-p12v_0 { - compatible = "regulator-fixed"; - regulator-name = "P12V_0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */ - p12v_1: regulator-p12v_1 { - compatible = "regulator-fixed"; - regulator-name = "P12V_1"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - sound { - model = "ODROID-HC4"; - }; -}; - -&cpu_thermal { - cooling-maps { - map { - trip = <&cpu_passive>; - cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ir { - linux,rc-map-name = "rc-odroid"; -}; - -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - status = "okay"; - compatible = "nxp,pcf8563"; - reg = <0x51>; - wakeup-source; - }; -}; - -&pcie { - status = "okay"; - reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; -}; - -&pwm_cd { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_d_x6_pins>; -}; - -&sd_emmc_c { - status = "disabled"; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&usb { - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; -}; - -&usb2_phy0 { - status = "disabled"; -}; diff --git a/arch/arm/dts/meson-sm1-odroid.dtsi b/arch/arm/dts/meson-sm1-odroid.dtsi deleted file mode 100644 index fd0ad85c165..00000000000 --- a/arch/arm/dts/meson-sm1-odroid.dtsi +++ /dev/null @@ -1,449 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com> - */ - -#include "meson-sm1.dtsi" -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v>; - - enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - - gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", - "PIN_36", /* GPIOH_5 */ - "PIN_26", /* GPIOH_6 */ - "PIN_32", /* GPIOH_7 */ - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_7", /* GPIOX_5 */ - "PIN_33", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_35"; /* GPIOX_19 */ -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "", "", "", "", - "PIN_47", /* GPIOAO_4 */ - "", "", - "PIN_45", /* GPIOAO_7 */ - "PIN_46", /* GPIOAO_8 */ - "PIN_44", /* GPIOAO_9 */ - "PIN_42", /* GPIOAO_10 */ - "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts deleted file mode 100644 index 2194a778973..00000000000 --- a/arch/arm/dts/meson-sm1-sei610.dts +++ /dev/null @@ -1,616 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/meson-g12a-gpio.h> -#include <dt-bindings/sound/meson-g12a-tohdmitx.h> - -/ { - compatible = "seirobotics,sei610", "amlogic,sm1"; - model = "SEI Robotics SEI610"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key1 { - label = "A"; - linux,code = <BTN_0>; - gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <34 IRQ_TYPE_EDGE_BOTH>; - }; - - key2 { - label = "B"; - linux,code = <BTN_1>; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <35 IRQ_TYPE_EDGE_BOTH>; - }; - - key3 { - label = "C"; - linux,code = <BTN_2>; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - }; - - mic_mute { - label = "MicMute"; - linux,code = <SW_MUTE_DEVICE>; - linux,input-type = <EV_SW>; - gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <99 IRQ_TYPE_EDGE_BOTH>; - }; - - power_key { - label = "PowerKey"; - linux,code = <KEY_POWER>; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - led-controller-1 { - compatible = "gpio-leds"; - - led-1 { - label = "sei610:blue:bt"; - gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - default-state = "off"; - }; - }; - - led-controller-2 { - compatible = "pwm-leds"; - - led-2 { - label = "sei610:red:power"; - pwms = <&pwm_AO_ab 0 30518 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - active-low; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1500 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SEI610"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - interrupt-parent = <&gpio_intc>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -/* Exposed via the on-board USB to Serial FT232RL IC */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi deleted file mode 100644 index 56ca0ba2241..00000000000 --- a/arch/arm/dts/meson-sm1.dtsi +++ /dev/null @@ -1,550 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#include "meson-g12-common.dtsi" -#include <dt-bindings/clock/axg-audio-clkc.h> -#include <dt-bindings/power/meson-sm1-power.h> -#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> -#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> - -/ { - compatible = "amlogic,sm1"; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <770000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <780000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <790000>; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <800000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <810000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <850000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - audio: bus@60000 { - compatible = "simple-bus"; - reg = <0x0 0x60000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,sm1-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV5>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <8192>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-sm1-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout_a: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_A"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - toacodec: audio-controller@740 { - compatible = "amlogic,sm1-toacodec", - "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOACODEC"; - resets = <&clkc_audio AUD_RESET_TOACODEC>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,sm1-tohdmitx", - "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - - toddr_d: audio-controller@840 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x840 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_D"; - interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_TODDR_D>; - resets = <&arb AXG_ARB_TODDR_D>, - <&clkc_audio AUD_RESET_TODDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_d: audio-controller@880 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x880 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_D"; - interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkc_audio AUD_CLKID_FRDDR_D>; - resets = <&arb AXG_ARB_FRDDR_D>, - <&clkc_audio AUD_RESET_FRDDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - }; - - pdm: audio-controller@61000 { - compatible = "amlogic,sm1-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x61000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; -}; - -&cecb_AO { - compatible = "amlogic,meson-sm1-ao-cec"; -}; - -&clk_msr { - compatible = "amlogic,meson-sm1-clk-measure"; -}; - - -&clkc { - compatible = "amlogic,sm1-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_SM1_ETH_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson-sm1-gpio-intc", - "amlogic,meson-gpio-intc"; -}; - -&pcie { - power-domains = <&pwrc PWRC_SM1_PCIE_ID>; -}; - -&pmu { - compatible = "amlogic,sm1-ddr-pmu"; -}; - -&pwrc { - compatible = "amlogic,meson-sm1-pwrc"; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,sm1-vdec"; -}; - -&vpu { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&usb { - power-domains = <&pwrc PWRC_SM1_USB_ID>; -}; diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi new file mode 100644 index 00000000000..906f9faa545 --- /dev/null +++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in initramfs + * the VBUS supply will never get turned on. + * https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.connolly@linaro.org/ + */ +&pcie0_3p3v_dual { + regulator-always-on; +}; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index e0517cf4601..5889d436edb 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -50,6 +50,12 @@ #size-cells = <1>; arasan,has-mdma; num-cs = <2>; + nand@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <1>; + nand-ecc-mode = "hw"; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 8517bdad6f4..c1d713b5d89 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - fwuen { + key-fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = <BTN_MISC>; @@ -192,7 +192,7 @@ status = "okay"; /* QSPI should also have PINCTRL setup */ flash@0 { - compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ + compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 5202b7c4819..1727a1cc15c 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -356,6 +356,8 @@ &uart0 { status = "okay"; + rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; assigned-clock-rates = <100000000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 6c29f657413..0a0cbd2b69a 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -66,6 +66,18 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -130,6 +142,14 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 6d0d5c487d2..561b546e37f 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -342,6 +342,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index a4b4465d203..64683e0ccbb 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -63,6 +63,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -97,6 +109,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { @@ -329,6 +349,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 2a3bbe17047..b626d1aacf5 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - j383 { + key-j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index e0e4f1b13ad..e0632883e4e 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw16 { + button-16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index b97f7ee8d44..48ab619472e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -136,8 +136,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -173,8 +172,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index b4e24745a9a..a113e475082 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -46,7 +46,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 6f593e80841..4d7d5d2e5ef 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -46,7 +46,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 7f70904f44e..def3b53cef7 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw1 { + switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 0adb2062aef..41f9a23d06a 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw1 { + switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <BTN_MISC>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b50b83b7723..53a606c340a 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -168,7 +168,7 @@ bootph-all; }; - pmu { + pmu: pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -1001,14 +1001,14 @@ status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1033,14 +1033,14 @@ status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch/arm/include/asm/arch-imx9/mu.h index b8604992914..649b8a60df8 100644 --- a/arch/arm/include/asm/arch-imx9/mu.h +++ b/arch/arm/include/asm/arch-imx9/mu.h @@ -8,6 +8,6 @@ #include <event.h> -int imx9_probe_mu(void *ctx, struct event *event); +int imx9_probe_mu(void); #endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 67275fba616..b55167e9cc0 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -31,7 +31,7 @@ endif obj-$(CONFIG_CPU_V7M) += cmd_boot.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index fbde476a7f1..23d9217fcc2 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -188,6 +188,7 @@ config TARGET_IMX8MP_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DEBIX_MODEL_A bool "Polyhex i.MX8M Plus Debix Model A SBC" @@ -261,12 +262,14 @@ config TARGET_VERDIN_IMX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_VERDIN_IMX8MP bool "Support Toradex Verdin iMX8M Plus module" select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_BEACON bool "imx8mm Beacon Embedded devkit" @@ -276,6 +279,7 @@ config TARGET_IMX8MM_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -285,6 +289,7 @@ config TARGET_IMX8MN_BEACON select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + imply OF_UPSTREAM config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index e2794d6218b..2117489f232 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -622,6 +622,7 @@ int imx9_probe_mu(void) return 0; } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); int timer_init(void) { diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 6ee9864c72c..1bd523329a4 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o endif obj-y += common.o security.o +obj-$(CONFIG_SOC_K3_AM625) += am62x/ diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 6c96e881146..668f9a51ef4 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -14,6 +14,7 @@ #include <dm.h> #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#include <dm/ofnode.h> #define RTC_BASE_ADDRESS 0x2b1f0000 #define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) @@ -24,6 +25,9 @@ #define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 #define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 +/* TISCI DEV ID for A53 Clock */ +#define AM62X_DEV_A53SS0_CORE_0_DEV_ID 135 + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -112,6 +116,62 @@ static __maybe_unused void rtc_erratumi2327_init(void) writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); } +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int get_a53_cpu_clock_index(ofnode node) +{ + int count, i; + struct ofnode_phandle_args *args; + ofnode clknode; + + clknode = ofnode_path("/bus@f0000/system-controller@44043000/clock-controller"); + if (!ofnode_valid(clknode)) + return -1; + + count = ofnode_count_phandle_with_args(node, "assigned-clocks", "#clock-cells", 0); + + for (i = 0; i < count; i++) { + if (!ofnode_parse_phandle_with_args(node, "assigned-clocks", + "#clock-cells", 0, i, args)) { + if (ofnode_equal(clknode, args->node) && + args->args[0] == AM62X_DEV_A53SS0_CORE_0_DEV_ID) + return i; + } + } + + return -1; +} + +static void fixup_a53_cpu_freq_by_speed_grade(void) +{ + int index, size; + u32 *rates; + ofnode node; + + node = ofnode_path("/a53@0"); + if (!ofnode_valid(node)) + return; + + rates = fdt_getprop_w(ofnode_to_fdt(node), ofnode_to_offset(node), + "assigned-clock-rates", &size); + + index = get_a53_cpu_clock_index(node); + + if (!rates || index < 0 || index >= (size / sizeof(u32))) { + printf("Wrong A53 assigned-clocks configuration\n"); + return; + } + + rates[index] = cpu_to_fdt32(k3_get_a53_max_frequency()); + + printf("Changed A53 CPU frequency to %dHz (%c grade) in DT\n", + k3_get_a53_max_frequency(), k3_get_speed_grade()); +} +#else +static void fixup_a53_cpu_freq_by_speed_grade(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -176,6 +236,14 @@ void board_init_f(ulong dummy) } /* + * Relocate boot information to OCRAM (after TIFS has opend this + * region for us) so the next bootloader stages can keep access to + * primary vs backup bootmodes. + */ + if (IS_ENABLED(CONFIG_CPU_V7R)) + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); + + /* * Force probe of clk_k3 driver here to ensure basic default clock * configuration is always done. */ @@ -210,6 +278,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } spl_enable_cache(); + + fixup_a53_cpu_freq_by_speed_grade(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) @@ -235,100 +305,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) } } -static u32 __get_backup_bootmedia(u32 devstat) -{ - u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; - u32 bkup_bootmode_cfg = - (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; - - switch (bkup_bootmode) { - case BACKUP_BOOT_DEVICE_UART: - return BOOT_DEVICE_UART; - - case BACKUP_BOOT_DEVICE_USB: - return BOOT_DEVICE_USB; - - case BACKUP_BOOT_DEVICE_ETHERNET: - return BOOT_DEVICE_ETHERNET; - - case BACKUP_BOOT_DEVICE_MMC: - if (bkup_bootmode_cfg) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BACKUP_BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BACKUP_BOOT_DEVICE_I2C: - return BOOT_DEVICE_I2C; - - case BACKUP_BOOT_DEVICE_DFU: - if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - }; - - return BOOT_DEVICE_RAM; -} - -static u32 __get_primary_bootmedia(u32 devstat) -{ - u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; - u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> - MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; - - switch (bootmode) { - case BOOT_DEVICE_OSPI: - fallthrough; - case BOOT_DEVICE_QSPI: - fallthrough; - case BOOT_DEVICE_XSPI: - fallthrough; - case BOOT_DEVICE_SPI: - return BOOT_DEVICE_SPI; - - case BOOT_DEVICE_ETHERNET_RGMII: - fallthrough; - case BOOT_DEVICE_ETHERNET_RMII: - return BOOT_DEVICE_ETHERNET; - - case BOOT_DEVICE_EMMC: - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_MMC: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> - MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) - return BOOT_DEVICE_MMC2; - return BOOT_DEVICE_MMC1; - - case BOOT_DEVICE_DFU: - if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> - MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) - return BOOT_DEVICE_USB; - return BOOT_DEVICE_DFU; - - case BOOT_DEVICE_NOBOOT: - return BOOT_DEVICE_RAM; - } - - return bootmode; -} - u32 spl_boot_device(void) { - u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); - u32 bootmedia; - - if (bootindex == K3_PRIMARY_BOOTMODE) - bootmedia = __get_primary_bootmedia(devstat); - else - bootmedia = __get_backup_bootmedia(devstat); - - debug("am625_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", - __func__, devstat, bootmedia, bootindex); - - return bootmedia; + return get_boot_device(); } diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig index 7c9bac2ece8..9786751874d 100644 --- a/arch/arm/mach-k3/am62x/Kconfig +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -48,6 +48,7 @@ config TARGET_VERDIN_AM62_A53 select ARM64 select BINMAN select OF_SYSTEM_SETUP + imply OF_UPSTREAM config TARGET_VERDIN_AM62_R5 bool "Toradex Verdin AM62 running on R5" diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile new file mode 100644 index 00000000000..acf09c3426c --- /dev/null +++ b/arch/arm/mach-k3/am62x/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0+ +obj-y += boot.o diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c new file mode 100644 index 00000000000..132b42f7edb --- /dev/null +++ b/arch/arm/mach-k3/am62x/boot.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/am62_spl.h> + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 get_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmode = *(u32 *)(K3_BOOT_PARAM_TABLE_INDEX_OCRAM); + u32 bootmedia; + + if (bootmode == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n", + __func__, devstat, bootmedia, bootmode); + + return bootmedia; +} diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b0fb87b97a2..1a269d6934a 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -24,6 +24,7 @@ #include <asm/io.h> #include <fs_loader.h> #include <fs.h> +#include <efi_loader.h> #include <env.h> #include <elf.h> #include <soc.h> @@ -270,6 +271,17 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } + if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(prueth), + &dev); + if (ret) + printf("Failed to probe prueth driver\n"); + } + /* Default FIT boot on HS-SE devices */ if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); @@ -296,3 +308,14 @@ void setup_qos(void) writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); } #endif + +void efi_add_known_memory(void) +{ + if (IS_ENABLED(CONFIG_EFI_LOADER)) + /* + * Memory over ram_top can be used by various firmware + * Declare to EFI only memory area below ram_top + */ + efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, + EFI_CONVENTIONAL_MEMORY); +} diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 264f8a488b4..bcbc4821c82 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -83,6 +83,7 @@ #define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 @@ -122,6 +123,21 @@ static inline int k3_get_max_temp(void) } } +static inline int k3_get_a53_max_frequency(void) +{ + switch (k3_get_speed_grade()) { + case 'K': + return 800000000; + case 'S': + return 1000000000; + case 'T': + return 1250000000; + case 'G': + default: + return 300000000; + } +} + static inline int k3_has_pru(void) { u32 full_devid = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID); diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index af982e70d17..c724450638c 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -107,4 +107,5 @@ struct rom_extended_boot_data { u32 num_components; }; +u32 get_boot_device(void); #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index c02f8d33099..0f6c294f1eb 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -24,6 +24,9 @@ enum { IMAGE_ID_OPTEE, IMAGE_ID_SPL, IMAGE_ID_DM_FW, + IMAGE_ID_TIFSSTUB_HS, + IMAGE_ID_TIFSSTUB_FS, + IMAGE_ID_T, IMAGE_AMT, }; @@ -33,6 +36,9 @@ static const char *image_os_match[IMAGE_AMT] = { "tee", "U-Boot", "DM", + "tifsstub-hs", + "tifsstub-fs", + "tifsstub-gp", }; #endif @@ -314,6 +320,24 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, break; } } + + if (i < IMAGE_AMT && i > IMAGE_ID_DM_FW) { + int device_type = get_device_type(); + + if ((device_type == K3_DEVICE_TYPE_HS_SE && + strcmp(os, "tifsstub-hs")) || + (device_type == K3_DEVICE_TYPE_HS_FS && + strcmp(os, "tifsstub-fs")) || + (device_type == K3_DEVICE_TYPE_GP && + strcmp(os, "tifsstub-gp"))) { + *p_size = 0; + } else { + debug("tifsstub-type: %s\n", os); + } + + return; + } + /* * Only DM and the DTBs are being authenticated here, * rest will be authenticated when A72 cluster is up diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index c2fff84a686..031d4e5ecd3 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -6,10 +6,12 @@ config FEROCEON_88FR131 config KW88F6192 bool select ARCH_VERY_EARLY_INIT + imply OF_UPSTREAM config KW88F6281 bool select ARCH_VERY_EARLY_INIT + imply OF_UPSTREAM config SHEEVA_88SV131 bool diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 95e7b019ce8..7570f48e25f 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -32,24 +32,28 @@ config MESON_GXBB config MESON_GXL bool "GXL" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S905X/D or S805X config MESON_GXM bool "GXM" select MESON_GX + imply OF_UPSTREAM help Select this if your SoC is an S912 config MESON_AXG bool "AXG" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an A113X/D config MESON_G12A bool "G12A" select MESON64_COMMON + imply OF_UPSTREAM help Select this if your SoC is an S905X/D2 diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 2058c95ca2d..f15d3cc5edb 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -18,6 +18,8 @@ config ARMADA_32BIT select TOOLS_KWBIMAGE if SPL select SPL_SYS_NO_VECTOR_TABLE if SPL select ARCH_VERY_EARLY_INIT + select ARMADA_32BIT_SYSCON_RESET if DM_RESET && PCI_MVEBU + select ARMADA_32BIT_SYSCON_SYSRESET if SYSRESET # ARMv7 SoCs... config ARMADA_375 @@ -456,6 +458,29 @@ config SF_DEFAULT_MODE default 0x0 depends on MVEBU_SPL_BOOT_DEVICE_SPI +config ARMADA_32BIT_SYSCON + bool + depends on ARMADA_32BIT + select REGMAP + select SYSCON + +config ARMADA_32BIT_SYSCON_RESET + bool "Support Armada XP/375/38x/39x reset controller" + depends on ARMADA_32BIT + depends on DM_RESET + select ARMADA_32BIT_SYSCON + help + Build support for Armada XP/375/38x/39x reset controller. This is + needed for PCIe support. + +config ARMADA_32BIT_SYSCON_SYSRESET + bool "Support Armada XP/375/38x/39x sysreset via driver model" + depends on ARMADA_32BIT + depends on SYSRESET + select ARMADA_32BIT_SYSCON + help + Build support for Armada XP/375/38x/39x system reset via driver model. + source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 0584ed2be5b..329c2e49153 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -22,13 +22,14 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o obj-y += lowlevel.o -obj-$(CONFIG_DM_RESET) += system-controller.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_32BIT_SYSCON) += system-controller.o + ifdef CONFIG_ARMADA_38X obj-$(CONFIG_MVEBU_EFUSE) += efuse.o endif diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 8e0de935385..7c62a5dbb6a 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -52,6 +52,7 @@ void lowlevel_init(void) */ } +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) void reset_cpu(void) { struct mvebu_system_registers *reg = @@ -62,6 +63,7 @@ void reset_cpu(void) while (1) ; } +#endif u32 get_boot_device(void) { diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 7cdde11cbd2..682431ee11d 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -1,18 +1,33 @@ // SPDX-License-Identifier: GPL-2.0+ -// (C) 2021 Pali Rohár <pali@kernel.org> +/* + * Copyright (C) 2021 Pali Rohár <pali@kernel.org> + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ #include <common.h> #include <dm.h> +#include <dm/lists.h> +#include <regmap.h> #include <reset-uclass.h> +#include <syscon.h> +#include <sysreset.h> #include <asm/io.h> -#define MVEBU_SOC_CONTROL_1_REG 0x4 +#define MVEBU_SOC_CONTROL_1_REG 0x4 -#define MVEBU_PCIE_ID 0 +#if defined(CONFIG_ARMADA_375) +# define MVEBU_RSTOUTN_MASK_REG 0x54 +# define MVEBU_SYS_SOFT_RST_REG 0x58 +#else +# define MVEBU_RSTOUTN_MASK_REG 0x60 +# define MVEBU_SYS_SOFT_RST_REG 0x64 +#endif -struct mvebu_reset_data { - void *base; -}; +#define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0) + +#define MVEBU_PCIE_ID 0 + +#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) static int mvebu_reset_of_xlate(struct reset_ctl *rst, struct ofnode_phandle_args *args) @@ -46,46 +61,33 @@ static int mvebu_reset_free(struct reset_ctl *rst) static int mvebu_reset_assert(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); - clrbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data)); - return 0; + return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG, + BIT(rst->data), 0); } static int mvebu_reset_deassert(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); - setbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data)); - return 0; + return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG, + BIT(rst->data), BIT(rst->data)); } static int mvebu_reset_status(struct reset_ctl *rst) { - struct mvebu_reset_data *data = dev_get_priv(rst->dev); - - return !(readl(data->base + MVEBU_SOC_CONTROL_1_REG) & BIT(rst->data)); -} - -static int mvebu_reset_of_to_plat(struct udevice *dev) -{ - struct mvebu_reset_data *data = dev_get_priv(dev); + struct regmap *regmap = syscon_get_regmap(rst->dev->parent); + uint val; + int ret; - data->base = dev_read_addr_ptr(dev); - if (!data->base) - return -EINVAL; + ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val); + if (ret < 0) + return ret; - return 0; + return !(val & BIT(rst->data)); } -static const struct udevice_id mvebu_reset_of_match[] = { - { .compatible = "marvell,armada-370-xp-system-controller" }, - { .compatible = "marvell,armada-375-system-controller" }, - { .compatible = "marvell,armada-380-system-controller" }, - { .compatible = "marvell,armada-390-system-controller" }, - { }, -}; - static const struct reset_ops mvebu_reset_ops = { .of_xlate = mvebu_reset_of_xlate, .request = mvebu_reset_request, @@ -98,8 +100,81 @@ static const struct reset_ops mvebu_reset_ops = { U_BOOT_DRIVER(mvebu_reset) = { .name = "mvebu-reset", .id = UCLASS_RESET, - .of_match = mvebu_reset_of_match, - .of_to_plat = mvebu_reset_of_to_plat, - .priv_auto = sizeof(struct mvebu_reset_data), .ops = &mvebu_reset_ops, }; + +#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */ + +#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) + +static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct regmap *regmap = syscon_get_regmap(dev->parent); + uint bit; + + if (type != SYSRESET_COLD) + return -EPROTONOSUPPORT; + + bit = MVEBU_GLOBAL_SOFT_RST_BIT; + + regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit); + regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit); + + /* Loop while waiting for the reset */ + while (1) + ; + + return 0; +} + +static struct sysreset_ops mvebu_sysreset_ops = { + .request = mvebu_sysreset_request, +}; + +U_BOOT_DRIVER(mvebu_sysreset) = { + .name = "mvebu-sysreset", + .id = UCLASS_SYSRESET, + .ops = &mvebu_sysreset_ops, +}; + +#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */ + +static int mvebu_syscon_bind(struct udevice *dev) +{ + int ret = 0; + + /* bind also mvebu-reset, with the same ofnode */ + if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) { + ret = device_bind_driver_to_node(dev, "mvebu-reset", + "mvebu-reset", dev_ofnode(dev), + NULL); + if (ret < 0) + return ret; + } + + /* bind also mvebu-sysreset, with the same ofnode */ + if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) { + ret = device_bind_driver_to_node(dev, "mvebu-sysreset", + "mvebu-sysreset", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + return ret; +} + +static const struct udevice_id mvebu_syscon_of_match[] = { + { .compatible = "marvell,armada-370-xp-system-controller" }, + { .compatible = "marvell,armada-375-system-controller" }, + { .compatible = "marvell,armada-380-system-controller" }, + { .compatible = "marvell,armada-390-system-controller" }, + { }, +}; + +U_BOOT_DRIVER(mvebu_syscon) = { + .name = "mvebu-system-controller", + .id = UCLASS_SYSCON, + .of_match = mvebu_syscon_of_match, + .bind = mvebu_syscon_bind, +}; diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 857171e593d..7a4495c8108 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -3,3 +3,4 @@ # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> obj-y += board.o +obj-$(CONFIG_OF_LIVE) += of_fixup.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index f12f5791a13..3d5994c8788 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -16,6 +16,7 @@ #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <dm/read.h> +#include <power/regulator.h> #include <env.h> #include <init.h> #include <linux/arm-smccc.h> @@ -24,9 +25,12 @@ #include <linux/sizes.h> #include <lmb.h> #include <malloc.h> +#include <fdt_support.h> #include <usb.h> #include <sort.h> +#include "qcom-priv.h" + DECLARE_GLOBAL_DATA_PTR; static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; @@ -93,7 +97,9 @@ void *board_fdt_blob_setup(int *err) * try and use the FDT built into U-Boot if there is one... * This avoids having a hard dependency on the previous stage bootloader */ - if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) { + + if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) || + fdt_check_header((void *)fdt))) { debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt); return (void *)gd->fdt_blob; } @@ -156,7 +162,9 @@ void __weak qcom_board_init(void) int board_init(void) { + regulators_enable_boot_on(false); show_psci_version(); + qcom_of_fixup_nodes(); qcom_board_init(); return 0; } diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c new file mode 100644 index 00000000000..3f7ac227bd0 --- /dev/null +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OF_LIVE devicetree fixup. + * + * This file implements runtime fixups for Qualcomm DT to improve + * compatibility with U-Boot. This includes adjusting the USB nodes + * to only use USB high-speed, as well as remapping volume buttons + * to behave as up/down for navigating U-Boot. + * + * We use OF_LIVE for this rather than early FDT fixup for a couple + * of reasons: it has a much nicer API, is most likely more efficient, + * and our changes are only applied to U-Boot. This allows us to use a + * DT designed for Linux, run U-Boot with a modified version, and then + * boot Linux with the original FDT. + * + * Copyright (c) 2024 Linaro Ltd. + * Author: Caleb Connolly <caleb.connolly@linaro.org> + */ + +#include <dt-bindings/input/linux-event-codes.h> +#include <dm/of_access.h> +#include <dm/of.h> +#include <fdt_support.h> +#include <linux/errno.h> +#include <stdlib.h> +#include <time.h> + +/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 + * USB controllers. Rather than requiring source level DT changes, we fix up + * DT here. This improves compatibility with upstream DT and simplifies the + * porting process for new devices. + */ +static int fixup_qcom_dwc3(struct device_node *glue_np) +{ + struct device_node *dwc3; + int ret, len, hsphy_idx = 1; + const __be32 *phandles; + const char *second_phy_name; + + debug("Fixing up %s\n", glue_np->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + + /* Find the DWC3 node itself */ + dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3"); + if (!dwc3) { + log_err("Failed to find dwc3 node\n"); + return -ENOENT; + } + + phandles = of_get_property(dwc3, "phys", &len); + len /= sizeof(*phandles); + if (len == 1) { + log_debug("Only one phy, not a superspeed controller\n"); + return 0; + } + + /* Figure out if the superspeed phy is present and if so then which phy is it? */ + ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); + if (ret == -ENODATA) { + log_debug("Only one phy, not a super-speed controller\n"); + return 0; + } else if (ret) { + log_err("Failed to read second phy name: %d\n", ret); + return ret; + } + + if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) { + log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n", + second_phy_name); + hsphy_idx = 0; + } + + /* Overwrite the "phys" property to only contain the high-speed phy */ + ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx); + if (ret) { + log_err("Failed to overwrite 'phys' property: %d\n", ret); + return ret; + } + + /* Overwrite "phy-names" to only contain a single entry */ + ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy"); + if (ret) { + log_err("Failed to overwrite 'phy-names' property: %d\n", ret); + return ret; + } + + ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed"); + if (ret) { + log_err("Failed to set 'maximum-speed' property: %d\n", ret); + return ret; + } + + return 0; +} + +static void fixup_usb_nodes(void) +{ + struct device_node *glue_np = NULL; + int ret; + + while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) { + ret = fixup_qcom_dwc3(glue_np); + if (ret) + log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret); + } +} + +/* Remove all references to the rpmhpd device */ +static void fixup_power_domains(void) +{ + struct device_node *pd = NULL, *np = NULL; + struct property *prop; + const __be32 *val; + + /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ + for_each_of_allnodes(pd) { + if (pd->name && !strcmp("power-controller", pd->name)) + break; + } + + /* Sanity check that this is indeed a power domain controller */ + if (!of_find_property(pd, "#power-domain-cells", NULL)) { + log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + return; + } + + /* Remove all references to the power domain controller */ + for_each_of_allnodes(np) { + if (!(prop = of_find_property(np, "power-domains", NULL))) + continue; + + val = prop->value; + if (val[0] == cpu_to_fdt32(pd->phandle)) + of_remove_property(np, prop); + } +} + +#define time_call(func, ...) \ + do { \ + u64 start = timer_get_us(); \ + func(__VA_ARGS__); \ + debug(#func " took %lluus\n", timer_get_us() - start); \ + } while (0) + +void qcom_of_fixup_nodes(void) +{ + time_call(fixup_usb_nodes); + time_call(fixup_power_domains); +} diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h new file mode 100644 index 00000000000..0a7ed5eff8b --- /dev/null +++ b/arch/arm/mach-snapdragon/qcom-priv.h @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __QCOM_PRIV_H__ +#define __QCOM_PRIV_H__ + +#if CONFIG_IS_ENABLED(OF_LIVE) +/** + * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes + * + * Adjusts nodes in the live tree to improve compatibility with U-Boot. + */ +void qcom_of_fixup_nodes(void); +#else +static inline void qcom_of_fixup_nodes(void) +{ + log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n"); +} +#endif /* OF_LIVE */ + +#endif /* __QCOM_PRIV_H__ */ diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 7f2753190c2..e6f1286e71f 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -265,14 +265,15 @@ int dram_init(void) if (uniphier_get_soc_id() == UNIPHIER_LD20_ID) gd->ram_size -= 64; + /* map all the DRAM regions */ + uniphier_mem_map_init(gd->ram_base, prev_top - gd->ram_base); + return 0; } int dram_init_banksize(void) { struct uniphier_dram_map dram_map[3] = {}; - unsigned long base, top; - bool valid_bank_found = false; int ret, i; ret = uniphier_dram_map_get(dram_map); @@ -287,18 +288,7 @@ int dram_init_banksize(void) if (!dram_map[i].size) continue; - - if (!valid_bank_found) - base = dram_map[i].base; - top = dram_map[i].base + dram_map[i].size; - valid_bank_found = true; } - if (!valid_bank_found) - return -EINVAL; - - /* map all the DRAM regions */ - uniphier_mem_map_init(base, top - base); - return 0; } diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 6a7be0b4271..0d2238ace1e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -1,29 +1,5 @@ if ARCH_ZYNQMP -config SPL_FS_FAT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC - default y if MMC_SDHCI_ZYNQ - -config SPL_SERIAL - default y - -config SPL_SPI_FLASH_SUPPORT - default y if ZYNQ_QSPI - -config SPL_SPI - default y if ZYNQ_QSPI - config SYS_BOARD string "Board name" default "zynqmp" @@ -135,7 +111,8 @@ config ZYNQMP_PSU_INIT_ENABLED config SPL_ZYNQMP_PSU_INIT_ENABLED bool "Include psu_init in SPL" - default y if SPL + depends on SPL + default y select BOARD_EARLY_INIT_F help Include psu_init by default in SPL. diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index a0f35f36faa..979ff3aef6c 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -9,6 +9,7 @@ #include <image.h> #include <init.h> #include <log.h> +#include <semihosting.h> #include <spl.h> #include <linux/delay.h> @@ -66,6 +67,11 @@ void spl_board_init(void) } #endif +static u32 jtag_boot_device(void) +{ + return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM; +} + void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -75,7 +81,7 @@ void board_boot_order(u32 *spl_boot_list) if (spl_boot_list[0] == BOOT_DEVICE_MMC2) spl_boot_list[1] = BOOT_DEVICE_MMC1; - spl_boot_list[2] = BOOT_DEVICE_RAM; + spl_boot_list[2] = jtag_boot_device(); } u32 spl_boot_device(void) @@ -85,19 +91,20 @@ u32 spl_boot_device(void) #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED) /* Change default boot mode at run-time */ + reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE; writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT, &crlapb_base->boot_mode); -#endif - +#else reg = readl(&crlapb_base->boot_mode); if (reg >> BOOT_MODE_ALT_SHIFT) reg >>= BOOT_MODE_ALT_SHIFT; +#endif bootmode = reg & BOOT_MODES_MASK; switch (bootmode) { case JTAG_MODE: - return BOOT_DEVICE_RAM; + return jtag_boot_device(); #ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index 6e1fd938f52..5ccd9545cb5 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -8,7 +8,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o obj-y += bdinfo.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o obj-y += time.o diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile index dfd8135f4f2..2f234825f80 100644 --- a/arch/microblaze/lib/Makefile +++ b/arch/microblaze/lib/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-y += muldi3.o diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 1621cc9a1ff..4386eb4d6d1 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -10,7 +10,7 @@ obj-y += reloc.o obj-y += stack.o obj-y += traps.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index a9f3c7100e7..68a5ca007d5 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -4,5 +4,5 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += cache.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-y += libgcc.o diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index bb819dcbb6c..dcce9834927 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -34,7 +34,7 @@ obj-y += ticks.o endif obj-y += reloc.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o obj-y += interrupts.o diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6c26f91f166..7e20ef63bba 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ config TARGET_OPENPITON_RISCV64 config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" + select BOARD_LATE_INIT config TARGET_SIFIVE_UNLEASHED bool "Support SiFive Unleashed Board" @@ -93,6 +94,7 @@ source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" @@ -119,6 +121,26 @@ config ARCH_RV64I endchoice +config FRAMEPOINTER + bool "Build with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + +config SPL_FRAMEPOINTER + bool "Build SPL with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + choice prompt "Code Model" default CMODEL_MEDLOW diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index b3ef87078b5..c36a8533e0f 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -48,6 +48,10 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) +ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y) + ARCH_FLAGS += -fno-omit-frame-pointer +endif + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) CFLAGS_EFI += $(ARCH_FLAGS) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ecfefa1a025..affe70081b5 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -38,35 +38,51 @@ static inline bool supports_extension(char ext) #if CONFIG_IS_ENABLED(RISCV_MMODE) return csr_read(CSR_MISA) & (1 << (ext - 'a')); #elif CONFIG_CPU + char sext[2] = {ext}; struct udevice *dev; - char desc[32]; - int i; + const char *isa; + int ret, i; uclass_find_first_device(UCLASS_CPU, &dev); if (!dev) { debug("unable to find the RISC-V cpu device\n"); return false; } - if (!cpu_get_desc(dev, desc, sizeof(desc))) { - /* - * skip the first 4 characters (rv32|rv64) - */ - for (i = 4; i < sizeof(desc); i++) { - switch (desc[i]) { - case 's': - case 'x': - case 'z': - case '_': - case '\0': - /* - * Any of these characters mean the single - * letter extensions have all been consumed. - */ - return false; - default: - if (desc[i] == ext) - return true; - } + + ret = dev_read_stringlist_search(dev, "riscv,isa-extensions", sext); + if (ret >= 0) + return true; + + /* + * Only if the property is not found (ENODATA) is the fallback to + * riscv,isa used, otherwise the extension is not present in this + * CPU. + */ + if (ret != -ENODATA) + return false; + + isa = dev_read_string(dev, "riscv,isa"); + if (!isa) + return false; + + /* + * Skip the first 4 characters (rv32|rv64). + */ + for (i = 4; i < sizeof(isa); i++) { + switch (isa[i]) { + case 's': + case 'x': + case 'z': + case '_': + case '\0': + /* + * Any of these characters mean the single + * letter extensions have all been consumed. + */ + return false; + default: + if (isa[i] == ext) + return true; } } diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig new file mode 100644 index 00000000000..7225b1210c5 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config SOPHGO_CV1800B + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply CMD_CPU diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile new file mode 100644 index 00000000000..95beb34b51a --- /dev/null +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += dram.o +obj-y += cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c new file mode 100644 index 00000000000..b8051e29e02 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cache.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <cpu_func.h> + +/* + * dcache.ipa rs1 (invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01010 rs1 000 00000 0001011 + * + * dcache.cpa rs1 (clean) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01001 rs1 000 00000 0001011 + * + * dcache.cipa rs1 (clean then invalidate) + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000001 01011 rs1 000 00000 0001011 + * + * sync.s + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | + * 0000000 11001 00000 000 00000 0001011 + */ +#define DCACHE_IPA_A0 ".long 0x02a5000b" +#define DCACHE_CPA_A0 ".long 0x0295000b" +#define DCACHE_CIPA_A0 ".long 0x02b5000b" + +#define SYNC_S ".long 0x0190000b" + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_IPA_A0); + __asm__ __volatile__(SYNC_S); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) + __asm__ __volatile__(DCACHE_CPA_A0); + __asm__ __volatile__(SYNC_S); +} diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c new file mode 100644 index 00000000000..233a6a3d64e --- /dev/null +++ b/arch/riscv/cpu/cv1800b/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c new file mode 100644 index 00000000000..91007c0a3d3 --- /dev/null +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6cecadfac56..a9e19356928 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -418,6 +418,7 @@ call_board_init_r: */ mv a0, s3 /* gd_t */ mv a1, s4 /* dest_addr */ + mv s0, zero /* fp == NULL */ /* * jump to it ... diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts index 3af9e34b3bc..94e64ddce8f 100644 --- a/arch/riscv/dts/cv1800b-milkv-duo.dts +++ b/arch/riscv/dts/cv1800b-milkv-duo.dts @@ -33,6 +33,14 @@ clock-frequency = <25000000>; }; +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi index 165e9e320a8..baf641829e7 100644 --- a/arch/riscv/dts/cv1800b.dtsi +++ b/arch/riscv/dts/cv1800b.dtsi @@ -16,3 +16,7 @@ &clint { compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; }; + +&clk { + compatible = "sophgo,cv1800-clk"; +}; diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index 2d6f4a4b1e5..ec99c4deeb6 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -45,6 +45,13 @@ #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <375000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -53,6 +60,12 @@ dma-noncoherent; ranges; + clk: clock-controller@3002000 { + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; @@ -175,6 +188,15 @@ status = "disabled"; }; + sdhci0: mmc@4310000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4310000 0x1000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index f2c6bec9298..e11babc1cde 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -298,7 +298,7 @@ pinctrl-0 = <&mmc1_pins>; no-sdio; no-mmc; - broken-cd; + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; cap-sd-highspeed; post-power-on-delay-ms = <200>; status = "okay"; diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 94e42c26811..48ee1154956 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -8,6 +8,9 @@ */ /dts-v1/; + +#include "binman.dtsi" + / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index d2776d5b6cb..62d184aeb57 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -12,4 +12,13 @@ u8 get_pcb_revision_from_eeprom(void); u32 get_ddr_size_from_eeprom(void); +/** + * get_product_id_from_eeprom - get product ID string + * + * A string like "VF7110A1-2228-D008E000-00000001" is returned. + * + * Return: product ID string + */ +const char *get_product_id_from_eeprom(void); + #endif /* _ASM_RISCV_EEPROM_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 9a05b662fd6..0b2c88db6ba 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -6,7 +6,7 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation <rick@andestech.com> -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index a26ccc721fd..7350e2ced85 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -60,6 +60,40 @@ static void show_regs(struct pt_regs *regs) #endif } +#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER) +static void show_backtrace(struct pt_regs *regs) +{ + uintptr_t *fp = (uintptr_t *)regs->s0; + unsigned count = 0; + ulong ra; + + printf("backtrace:\n"); + + /* there are a few entry points where the s0 register is + * set to gd, so to avoid changing those, just abort if + * the value is the same */ + while (fp != NULL && fp != (uintptr_t *)gd) { + ra = fp[-1]; + printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT, + count, (ulong)fp, ra); + + if (gd && gd->flags & GD_FLG_RELOC) + printf(" - RA: " REG_FMT " reloc adjusted\n", + ra - gd->reloc_off); + else + printf("\n"); + + fp = (uintptr_t *)fp[-2]; + count++; + } +} +#else +static void show_backtrace(struct pt_regs *regs) +{ + printf("No backtrace support enabled\n"); +} +#endif + /** * instr_len() - get instruction length * @@ -131,6 +165,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_backtrace(regs); show_code(epc); show_efi_loaded_images(epc); panic("\n"); diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 0ce77de2fcb..1c8353d6156 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -58,10 +58,15 @@ config SANDBOX_CRASH_RESET bool "Reset on crash" help If an illegal instruction or an illegal memory access occurs, the - sandbox by default writes a crash dump and exits. If you set this - flag, the sandbox is reset instead. This may be useful when running - test suites like the UEFI self certification test which continue - with the next test after a crash. + sandbox exits with an error by default. + + If the u-boot binary is invoked with --signals (or -S), U-Boot will + handle the signal writing a crash dump before exiting. + + If you additionally set the CONFIG_SANDBOX_CRASH_RESET flag, the + sandbox is reset after writing the crash dump. This may be useful + when running test suites like the UEFI self certification test which + continue with the next test after a crash. config SANDBOX_BITS_PER_LONG int diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 1d50991f8d2..405843800e9 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -69,5 +69,3 @@ EFI_LDS := ${SRCDIR}/../../../arch/riscv/lib/elf_riscv64_efi.lds endif EFI_CRT0 := crt0_sandbox_efi.o EFI_RELOC := reloc_sandbox_efi.o -AFLAGS_crt0_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)" -CFLAGS_reloc_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)" diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c index 92c35aed95d..39ea3b3f012 100644 --- a/arch/sandbox/cpu/eth-raw-os.c +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -105,7 +105,12 @@ static int _raw_packet_start(struct eth_sandbox_raw_priv *priv, /* Make the socket non-blocking */ flags = fcntl(priv->sd, F_GETFL, 0); - fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + ret = fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + if (ret == -1) { + printf("Failed to make socket non-blocking: %d %s\n", errno, + strerror(errno)); + return -errno; + } /* Enable promiscuous mode to receive responses meant for us */ mr.mr_ifindex = device->sll_ifindex; @@ -172,7 +177,12 @@ static int _local_inet_start(struct eth_sandbox_raw_priv *priv) /* Make the socket non-blocking */ flags = fcntl(priv->sd, F_GETFL, 0); - fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + ret = fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + if (ret == -1) { + printf("Failed to make socket non-blocking: %d %s\n", errno, + strerror(errno)); + return -errno; + } /* Include the UDP/IP headers on send and receive */ ret = setsockopt(priv->sd, IPPROTO_IP, IP_HDRINCL, &one, diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 12d3eff5fa7..8392206eea6 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -106,3 +106,7 @@ #if IS_ENABLED(CONFIG_SUPPORT_VPL) #include "sandbox_vpl.dtsi" #endif + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#include "sandbox_capsule.dtsi" +#endif diff --git a/arch/sandbox/dts/sandbox_capsule.dtsi b/arch/sandbox/dts/sandbox_capsule.dtsi new file mode 100644 index 00000000000..34d29916b30 --- /dev/null +++ b/arch/sandbox/dts/sandbox_capsule.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Devicetree file with binman nodes needed for generating EFI + * capsules. + * + */ + +#include <sandbox_efi_capsule.h> + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + capsule1 { + filename = "Test01"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule2 { + filename = "Test02"; + efi-capsule { + image-index = <0x2>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule3 { + filename = "Test03"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_INCORRECT_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule4 { + filename = "Test101"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x5>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule5 { + filename = "Test102"; + efi-capsule { + image-index = <0x2>; + fw-version = <0xa>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule6 { + filename = "Test103"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x2>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule7 { + filename = "Test11"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule8 { + filename = "Test12"; + efi-capsule { + image-index = <0x1>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_INVAL_KEY; + public-key-cert = CAPSULE_INVAL_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule9 { + filename = "Test111"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x5>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; + + capsule10 { + filename = "Test112"; + efi-capsule { + image-index = <0x2>; + fw-version = <0xa>; + image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot-env:New"; + }; + }; + }; + + capsule11 { + filename = "Test113"; + efi-capsule { + image-index = <0x1>; + fw-version = <0x2>; + image-guid = SANDBOX_UBOOT_IMAGE_GUID; + private-key = CAPSULE_PRIV_KEY; + public-key-cert = CAPSULE_PUB_KEY; + monotonic-count = <0x1>; + + text { + text = "u-boot:New"; + }; + }; + }; +}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e264b29554c..a012f5c4c9b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -1990,4 +1990,8 @@ #include "sandbox_vpl.dtsi" #endif +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#include "sandbox_capsule.dtsi" +#endif + #include "cedit.dtsi" diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index a2bc5a7ee60..c4924b23c83 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -7,5 +7,5 @@ obj-y += fdt_fixup.o interrupts.o sections.o obj-$(CONFIG_PCI) += pci_io.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index 8dbcd9ff7dd..44ba8b52e13 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -85,5 +85,7 @@ int do_bootm_linux(int flag, struct bootm_info *bmi) int booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool force_reloc) { - return 0; + log_err("Booting is not supported on the sandbox.\n"); + + return 1; } diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index e7520a328d5..8c3c30293a3 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -6,7 +6,7 @@ extra-y += start.o obj-y += board.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-y += time.o obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 99e59d94c60..23a1e21b29e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE hex default 0x10000 +config X86_HARDFP + bool "Support hardware floating point" + help + U-Boot generally does not make use of floating point. Where this is + needed, it can be enabled using this option. This adjusts the + start-up code for 64-bit mode and changes the compiler options for + 64-bit to enable SSE. + config HAVE_ITSS bool "Enable ITSS" help @@ -1053,4 +1061,12 @@ config SPL_COREBOOT_SYSINFO display, memory and build information. It is stored in struct sysinfo_t after parsing by get_coreboot_info(). +config ZBOOT + bool "Support the zImage format" + default y + help + Enable this to support booting the x86-specific zImage format. This + uses a special, binary format containing information about the Linux + format to boot. + endmenu diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 26ec1af2f0b..2e3a7119e79 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64 + +ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse endif +endif # IS_32BIT + PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections -fvisibility=hidden KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 2647bff891f..5ea746ecce4 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -10,6 +10,7 @@ #include <init.h> #include <asm/cpu.h> #include <asm/global_data.h> +#include <asm/processor-flags.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,11 +40,22 @@ int x86_mp_init(void) return 0; } +/* enable SSE features for hardware floating point */ +static void setup_sse_features(void) +{ + asm ("mov %%cr4, %%rax\n" \ + "or %0, %%rax\n" \ + "mov %%rax, %%cr4\n" \ + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax"); +} + int x86_cpu_reinit_f(void) { /* set the vendor to Intel so that native_calibrate_tsc() works */ gd->arch.x86_vendor = X86_VENDOR_INTEL; gd->arch.has_mtrr = true; + if (IS_ENABLED(CONFIG_X86_HARDFP)) + setup_sse_features(); return 0; } diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index dfce7c2d591..b867468e16c 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -46,6 +46,16 @@ compatible = "coreboot-fb"; }; + bootstd { + compatible = "u-boot,boot-std"; + + theme { + font-size = <30>; + menu-inset = <3>; + menuitem-gap-y = <1>; + }; + }; + sysinfo { compatible = "coreboot,sysinfo"; }; diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 655675b6661..8b542605170 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -30,6 +30,78 @@ #define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 +enum { + ZBOOT_STATE_START = BIT(0), + ZBOOT_STATE_LOAD = BIT(1), + ZBOOT_STATE_SETUP = BIT(2), + ZBOOT_STATE_INFO = BIT(3), + ZBOOT_STATE_GO = BIT(4), + + /* This one doesn't execute automatically, so stop the count before 5 */ + ZBOOT_STATE_DUMP = BIT(5), + ZBOOT_STATE_COUNT = 5, +}; + +/** + * struct zboot_state - Current state of the boot + * + * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already + * been loaded and does not exist (as a cohesive whole) in memory + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @load_address: Address where the bzImage is moved before booting, either + * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR + * This is set up when loading the zimage + * @base_ptr: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + * This is set up when loading the zimage + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block + */ +struct zboot_state { + ulong bzimage_addr; + ulong bzimage_size; + ulong initrd_addr; + ulong initrd_size; + ulong load_address; + struct boot_params *base_ptr; + const char *cmdline; +}; + +extern struct zboot_state state; + +/** + * zimage_dump() - Dump information about a zimage + * + * @base_ptr: Pointer to the boot parameters + * @show_cmdline: true to show the kernel command line + */ +void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); + +/** + * zboot_load() - Load a zimage + * + * Load the zimage into the correct place + * + * Return: 0 if OK, -ve on error + */ +int zboot_load(void); + +/** + * zboot_setup() - Set up the zboot image reeady for booting + * + * Return: 0 if OK, -ve on error + */ +int zboot_setup(void); + +/** + * zboot_go() - Start the image + * + * Return: 0 if OK, -ve on error + */ +int zboot_go(void); + /** * load_zimage() - Load a zImage or bzImage * @@ -62,4 +134,29 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, ulong initrd_addr, ulong initrd_size, ulong cmdline_force); +/** + * zboot_start() - Prepare to boot a zimage + * + * Record information about a zimage so it can be booted + * + * @bzimage_addr: Address of the bzImage to boot + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @base_addr: If non-zero, this indicates that the boot parameters have already + * been loaded by the caller to this address, so the load_zimage() call + * in zboot_load() will be skipped when booting + * @cmdline: Environment variable containing the 'override' command line, or + * NULL to use the one in the setup block + */ +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline); + +/** + * zboot_info() - Show simple info about a zimage + * + * Shows wherer the kernel was loaded and also the setup base + */ +void zboot_info(void); + #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 90a7618ecfd..94aa335ede4 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_X86_32BIT_INIT) += string.o endif ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o endif obj-y += cmd_boot.o obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO) += coreboot/ @@ -48,7 +48,7 @@ obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_CMD_ZBOOT) += zimage.o +obj-$(CONFIG_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o ifndef CONFIG_TPL_BUILD diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index c15f11f8cdf..4e4cf18dec5 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -283,7 +283,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { int ret; - printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); + printf("Jumping to 64-bit U-Boot\n"); ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); debug("ret=%d\n", ret); hang(); diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index a41e1ccf8a6..d7403876c13 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -56,41 +56,8 @@ DECLARE_GLOBAL_DATA_PTR; #define COMMAND_LINE_SIZE 2048 -/** - * struct zboot_state - Current state of the boot - * - * @bzimage_addr: Address of the bzImage to boot - * @bzimage_size: Size of the bzImage, or 0 to detect this - * @initrd_addr: Address of the initial ramdisk, or 0 if none - * @initrd_size: Size of the initial ramdisk, or 0 if none - * @load_address: Address where the bzImage is moved before booting, either - * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR - * @base_ptr: Pointer to the boot parameters, typically at address - * DEFAULT_SETUP_BASE - * @cmdline: Environment variable containing the 'override' command line, or - * NULL to use the one in the setup block - */ -struct zboot_state { - ulong bzimage_addr; - ulong bzimage_size; - ulong initrd_addr; - ulong initrd_size; - ulong load_address; - struct boot_params *base_ptr; - char *cmdline; -} state; - -enum { - ZBOOT_STATE_START = BIT(0), - ZBOOT_STATE_LOAD = BIT(1), - ZBOOT_STATE_SETUP = BIT(2), - ZBOOT_STATE_INFO = BIT(3), - ZBOOT_STATE_GO = BIT(4), - - /* This one doesn't execute automatically, so stop the count before 5 */ - ZBOOT_STATE_DUMP = BIT(5), - ZBOOT_STATE_COUNT = 5, -}; +/* Current state of the boot */ +struct zboot_state state; static void build_command_line(char *command_line, int auto_boot) { @@ -400,56 +367,10 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - const char *s; - - memset(&state, '\0', sizeof(state)); - if (argc >= 2) { - /* argv[1] holds the address of the bzImage */ - s = argv[1]; - } else { - s = env_get("fileaddr"); - } - - if (s) - state.bzimage_addr = hextoul(s, NULL); - - if (argc >= 3) { - /* argv[2] holds the size of the bzImage */ - state.bzimage_size = hextoul(argv[2], NULL); - } - - if (argc >= 4) - state.initrd_addr = hextoul(argv[3], NULL); - if (argc >= 5) - state.initrd_size = hextoul(argv[4], NULL); - if (argc >= 6) { - /* - * When the base_ptr is passed in, we assume that the image is - * already loaded at the address given by argv[1] and therefore - * the original bzImage is somewhere else, or not accessible. - * In any case, we don't need access to the bzImage since all - * the processing is assumed to be done. - * - * So set the base_ptr to the given address, use this arg as the - * load address and set bzimage_addr to 0 so we know that it - * cannot be proceesed (or processed again). - */ - state.base_ptr = (void *)hextoul(argv[5], NULL); - state.load_address = state.bzimage_addr; - state.bzimage_addr = 0; - } - if (argc >= 7) - state.cmdline = env_get(argv[6]); - - return 0; -} - -static int zboot_load(void) +int zboot_load(void) { struct boot_params *base_ptr; + int ret; if (state.base_ptr) { struct boot_params *from = (struct boot_params *)state.base_ptr; @@ -469,23 +390,16 @@ static int zboot_load(void) } state.base_ptr = base_ptr; - return 0; -} - -static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (zboot_load()) - return CMD_RET_FAILURE; - - if (env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)) || - env_set_hex("zbootaddr", state.load_address)) - return CMD_RET_FAILURE; + ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)); + if (!ret) + ret = env_set_hex("zbootaddr", state.load_address); + if (ret) + return ret; return 0; } -static int zboot_setup(void) +int zboot_setup(void) { struct boot_params *base_ptr = state.base_ptr; int ret; @@ -499,33 +413,7 @@ static int zboot_setup(void) return 0; } -static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct boot_params *base_ptr = state.base_ptr; - - if (!base_ptr) { - printf("base is not set: use 'zboot load' first\n"); - return CMD_RET_FAILURE; - } - if (zboot_setup()) { - puts("Setting up boot parameters failed ...\n"); - return CMD_RET_FAILURE; - } - - return 0; -} - -static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - printf("Kernel loaded at %08lx, setup_base=%p\n", - state.load_address, state.base_ptr); - - return 0; -} - -static int zboot_go(void) +int zboot_go(void) { struct boot_params *params = state.base_ptr; struct setup_header *hdr = ¶ms->hdr; @@ -549,35 +437,12 @@ static int zboot_go(void) return ret; } -static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size, + ulong base, char *cmdline) { int ret; - ret = zboot_go(); - printf("Kernel returned! (err=%d)\n", ret); - - return CMD_RET_FAILURE; -} - -int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, - ulong base, char *cmdline) -{ - int ret; - - memset(&state, '\0', sizeof(state)); - - if (base) { - state.base_ptr = map_sysmem(base, 0); - state.load_address = addr; - } else { - state.bzimage_addr = addr; - } - state.bzimage_size = size; - state.initrd_addr = initrd; - state.initrd_size = initrd_size; - state.cmdline = cmdline; - + zboot_start(addr, size, initrd, initrd_size, base, cmdline); ret = zboot_load(); if (ret) return log_msg_ret("ld", ret); @@ -586,7 +451,7 @@ int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, return log_msg_ret("set", ret); ret = zboot_go(); if (ret) - return log_msg_ret("set", ret); + return log_msg_ret("go", ret); return -EFAULT; } @@ -776,97 +641,25 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline) print_num("Kernel info offset", hdr->kernel_info_offset); } -static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr, + ulong initrd_size, ulong base_addr, const char *cmdline) { - struct boot_params *base_ptr = state.base_ptr; - - if (argc > 1) - base_ptr = (void *)hextoul(argv[1], NULL); - if (!base_ptr) { - printf("No zboot setup_base\n"); - return CMD_RET_FAILURE; - } - zimage_dump(base_ptr, true); - - return 0; -} - -/* Note: This defines the complete_zboot() function */ -U_BOOT_SUBCMDS(zboot, - U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""), - U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""), - U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""), - U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""), - U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""), - U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""), -) - -int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], int state_mask) -{ - int i; - - for (i = 0; i < ZBOOT_STATE_COUNT; i++) { - struct cmd_tbl *cmd = &zboot_subcmds[i]; - int mask = 1 << i; - int ret; + memset(&state, '\0', sizeof(state)); - if (mask & state_mask) { - ret = cmd->cmd(cmd, flag, argc, argv); - if (ret) - return ret; - } + state.bzimage_size = bzimage_size; + state.initrd_addr = initrd_addr; + state.initrd_size = initrd_size; + if (base_addr) { + state.base_ptr = map_sysmem(base_addr, 0); + state.load_address = bzimage_addr; + } else { + state.bzimage_addr = bzimage_addr; } - - return 0; + state.cmdline = cmdline; } -int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], int *repeatable) +void zboot_info(void) { - /* determine if we have a sub command */ - if (argc > 1) { - char *endp; - - hextoul(argv[1], &endp); - /* - * endp pointing to nul means that argv[1] was just a valid - * number, so pass it along to the normal processing - */ - if (*endp) - return do_zboot(cmdtp, flag, argc, argv, repeatable); - } - - do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START | - ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP | - ZBOOT_STATE_INFO | ZBOOT_STATE_GO); - - return CMD_RET_FAILURE; + printf("Kernel loaded at %08lx, setup_base=%p\n", + state.load_address, state.base_ptr); } - -U_BOOT_CMDREP_COMPLETE( - zboot, 8, do_zboot_parent, "Boot bzImage", - "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n" - " addr - The optional starting address of the bzimage.\n" - " If not set it defaults to the environment\n" - " variable \"fileaddr\".\n" - " size - The optional size of the bzimage. Defaults to\n" - " zero.\n" - " initrd addr - The address of the initrd image to use, if any.\n" - " initrd size - The size of the initrd image to use, if any.\n" - " setup - The address of the kernel setup region, if this\n" - " is not at addr\n" - " cmdline - Environment variable containing the kernel\n" - " command line, to override U-Boot's normal\n" - " cmdline generation\n" - "\n" - "Sub-commands to do part of the zboot sequence:\n" - "\tstart [addr [arg ...]] - specify arguments\n" - "\tload - load OS image\n" - "\tsetup - set up table\n" - "\tinfo - show summary info\n" - "\tgo - start OS\n" - "\tdump [addr] - dump info (optional address of boot params)", - complete_zboot -); diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile index ad4fe32cb69..bb9157f30f0 100644 --- a/arch/xtensa/lib/Makefile +++ b/arch/xtensa/lib/Makefile @@ -3,6 +3,6 @@ # (C) Copyright 2007 - 2013 Tensilica Inc. # (C) Copyright 2014 - 2016 Cadence Design Systems Inc. -obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_BOOTM) += bootm.o obj-y += cache.o misc.o relocate.o time.o diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c index a29fe362317..85eebcdf18e 100644 --- a/board/CZ.NIC/turris_atsha_otp.c +++ b/board/CZ.NIC/turris_atsha_otp.c @@ -11,6 +11,7 @@ #include <atsha204a-i2c.h> #include "turris_atsha_otp.h" +#include "turris_common.h" #define TURRIS_ATSHA_OTP_VERSION 0 #define TURRIS_ATSHA_OTP_SERIAL 1 @@ -32,26 +33,6 @@ static struct udevice *get_atsha204a_dev(void) return dev; } -static void increment_mac(u8 *mac) -{ - int i; - - for (i = 5; i >= 3; i--) { - mac[i] += 1; - if (mac[i]) - break; - } -} - -static void set_mac_if_invalid(int i, u8 *mac) -{ - u8 oldmac[6]; - - if (is_valid_ethaddr(mac) && - !eth_env_get_enetaddr_by_index("eth", i, oldmac)) - eth_env_set_enetaddr_by_index("eth", i, mac); -} - int turris_atsha_otp_init_mac_addresses(int first_idx) { struct udevice *dev = get_atsha204a_dev(); @@ -84,11 +65,7 @@ int turris_atsha_otp_init_mac_addresses(int first_idx) mac[4] = mac1[2]; mac[5] = mac1[3]; - set_mac_if_invalid((first_idx + 0) % 3, mac); - increment_mac(mac); - set_mac_if_invalid((first_idx + 1) % 3, mac); - increment_mac(mac); - set_mac_if_invalid((first_idx + 2) % 3, mac); + turris_init_mac_addresses(first_idx, mac); return 0; } diff --git a/board/CZ.NIC/turris_common.c b/board/CZ.NIC/turris_common.c new file mode 100644 index 00000000000..1717dda82eb --- /dev/null +++ b/board/CZ.NIC/turris_common.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Marek Behún <kabel@kernel.org> + */ + +#include <env.h> +#include <net.h> + +#include "turris_common.h" + +static void increment_mac(u8 *mac) +{ + int i; + + for (i = 5; i >= 3; i--) { + mac[i] += 1; + if (mac[i]) + break; + } +} + +static void set_mac_if_invalid(int i, u8 *mac) +{ + u8 oldmac[6]; + + if (is_valid_ethaddr(mac) && + !eth_env_get_enetaddr_by_index("eth", i, oldmac)) + eth_env_set_enetaddr_by_index("eth", i, mac); +} + +void turris_init_mac_addresses(int first_idx, const u8 *first_mac) +{ + u8 mac[6]; + + memcpy(mac, first_mac, sizeof(mac)); + + set_mac_if_invalid((first_idx + 0) % 3, mac); + increment_mac(mac); + set_mac_if_invalid((first_idx + 1) % 3, mac); + increment_mac(mac); + set_mac_if_invalid((first_idx + 2) % 3, mac); +} diff --git a/board/CZ.NIC/turris_common.h b/board/CZ.NIC/turris_common.h new file mode 100644 index 00000000000..5565ea9fd2a --- /dev/null +++ b/board/CZ.NIC/turris_common.h @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#ifndef TURRIS_COMMON_H +#define TURRIS_COMMON_H + +#include <asm/types.h> + +void turris_init_mac_addresses(int first_idx, const u8 *first_mac); + +#endif diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 3489bdd74bd..1a2f60e3d19 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -565,13 +565,10 @@ static void handle_reset_button(void) int checkboard(void) { int i, ret, board_version, ram_size, is_sd; - const char *pub_key, *model; + const char *pub_key; const u8 *topology; u64 serial_number; - model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Model: %s\n", model); - ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version, &ram_size, NULL); if (ret < 0) { diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile index dc39b44ae19..341378b4e54 100644 --- a/board/CZ.NIC/turris_omnia/Makefile +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2017 Marek Behún <kabel@kernel.org> -obj-y := turris_omnia.o ../turris_atsha_otp.o +obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index adeb69a205b..3b7a71bdad2 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -18,18 +18,22 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <asm/unaligned.h> #include <dm/uclass.h> #include <dt-bindings/gpio/gpio.h> #include <fdt_support.h> #include <hexdump.h> #include <time.h> +#include <turris-omnia-mcu-interface.h> #include <linux/bitops.h> +#include <linux/bitrev.h> #include <linux/delay.h> #include <u-boot/crc.h> #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> #include "../turris_atsha_otp.h" +#include "../turris_common.h" DECLARE_GLOBAL_DATA_PTR; @@ -59,46 +63,6 @@ DECLARE_GLOBAL_DATA_PTR; #define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704) #define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8) -enum mcu_commands { - CMD_GET_STATUS_WORD = 0x01, - CMD_GET_RESET = 0x09, - CMD_GET_FW_VERSION_APP = 0x0a, - CMD_WATCHDOG_STATE = 0x0b, - CMD_GET_FW_VERSION_BOOT = 0x0e, - - /* available if STS_FEATURES_SUPPORTED bit set in status word */ - CMD_GET_FEATURES = 0x10, - - /* available if EXT_CMD bit set in features */ - CMD_EXT_CONTROL = 0x12, -}; - -enum status_word_bits { - STS_MCU_TYPE_MASK = GENMASK(1, 0), - STS_MCU_TYPE_STM32 = 0, - STS_MCU_TYPE_GD32 = 1, - STS_MCU_TYPE_MKL = 2, - STS_MCU_TYPE_UNKN = 3, - STS_FEATURES_SUPPORTED = BIT(2), - CARD_DET_STSBIT = 0x0010, - MSATA_IND_STSBIT = 0x0020, -}; - -/* CMD_GET_FEATURES */ -enum features_e { - FEAT_PERIPH_MCU = BIT(0), - FEAT_EXT_CMDS = BIT(1), -}; - -/* CMD_EXT_CONTROL */ -enum ext_ctl_e { - EXT_CTL_nRES_LAN = BIT(1), - EXT_CTL_nRES_PHY = BIT(2), - EXT_CTL_nPERST0 = BIT(3), - EXT_CTL_nPERST1 = BIT(4), - EXT_CTL_nPERST2 = BIT(5), -}; - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -172,6 +136,141 @@ static int omnia_mcu_write(u8 cmd, const void *buf, int len) return dm_i2c_write(chip, cmd, buf, len); } +static int omnia_mcu_get_sts_and_features(u16 *psts, u32 *pfeatures) +{ + u16 sts, feat16; + int ret; + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &sts, sizeof(sts)); + if (ret) + return ret; + + if (psts) + *psts = sts; + + if (!pfeatures) + return 0; + + if (sts & STS_FEATURES_SUPPORTED) { + /* try read 32-bit features */ + ret = omnia_mcu_read(CMD_GET_FEATURES, pfeatures, + sizeof(*pfeatures)); + if (ret) { + /* try read 16-bit features */ + ret = omnia_mcu_read(CMD_GET_FEATURES, &feat16, + sizeof(&feat16)); + if (ret) + return ret; + + *pfeatures = feat16; + } else { + if (*pfeatures & FEAT_FROM_BIT_16_INVALID) + *pfeatures &= GENMASK(15, 0); + } + } else { + *pfeatures = 0; + } + + return 0; +} + +static int omnia_mcu_get_sts(u16 *sts) +{ + return omnia_mcu_get_sts_and_features(sts, NULL); +} + +static bool omnia_mcu_has_feature(u32 feature) +{ + u32 features; + + if (omnia_mcu_get_sts_and_features(NULL, &features)) + return false; + + return feature & features; +} + +static u32 omnia_mcu_crc32(const void *p, size_t len) +{ + u32 val, crc = 0; + + compiletime_assert(!(len % 4), "length has to be a multiple of 4"); + + while (len) { + val = bitrev32(get_unaligned_le32(p)); + crc = crc32(crc, (void *)&val, 4); + p += 4; + len -= 4; + } + + return ~bitrev32(crc); +} + +/* Can only be called after relocation, since it needs cleared BSS */ +static int omnia_mcu_board_info(char *serial, u8 *mac, char *version) +{ + static u8 reply[17]; + static bool cached; + + if (!cached) { + u8 csum; + int ret; + + ret = omnia_mcu_read(CMD_BOARD_INFO_GET, reply, sizeof(reply)); + if (ret) + return ret; + + if (reply[0] != 16) + return -EBADMSG; + + csum = reply[16]; + reply[16] = 0; + + if ((omnia_mcu_crc32(&reply[1], 16) & 0xff) != csum) + return -EBADMSG; + + cached = true; + } + + if (serial) { + const char *serial_env; + + serial_env = env_get("serial#"); + if (serial_env && strlen(serial_env) == 16) { + strcpy(serial, serial_env); + } else { + sprintf(serial, "%016llX", + get_unaligned_le64(&reply[1])); + env_set("serial#", serial); + } + } + + if (mac) + memcpy(mac, &reply[9], ETH_ALEN); + + if (version) + sprintf(version, "%u", reply[15]); + + return 0; +} + +static int omnia_mcu_get_board_public_key(char pub_key[static 67]) +{ + u8 reply[34]; + int ret; + + ret = omnia_mcu_read(CMD_CRYPTO_GET_PUBLIC_KEY, reply, sizeof(reply)); + if (ret) + return ret; + + if (reply[0] != 33) + return -EBADMSG; + + bin2hex(pub_key, &reply[1], 33); + pub_key[66] = '\0'; + + return 0; +} + static void enable_a385_watchdog(unsigned int timeout_minutes) { struct sar_freq_modes sar_freq; @@ -219,7 +318,7 @@ static bool disable_mcu_watchdog(void) puts("Disabling MCU watchdog... "); - ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); + ret = omnia_mcu_write(CMD_SET_WATCHDOG_STATE, "\x00", 1); if (ret) { printf("omnia_mcu_write failed: %i\n", ret); return false; @@ -233,7 +332,7 @@ static bool disable_mcu_watchdog(void) static bool omnia_detect_sata(const char *msata_slot) { int ret; - u16 stsword; + u16 sts; puts("MiniPCIe/mSATA card detection... "); @@ -249,24 +348,24 @@ static bool omnia_detect_sata(const char *msata_slot) } } - ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + ret = omnia_mcu_get_sts(&sts); if (ret) { printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", ret); return false; } - if (!(stsword & CARD_DET_STSBIT)) { + if (!(sts & STS_CARD_DET)) { puts("none\n"); return false; } - if (stsword & MSATA_IND_STSBIT) + if (sts & STS_MSATA_IND) puts("mSATA\n"); else puts("MiniPCIe\n"); - return stsword & MSATA_IND_STSBIT ? true : false; + return sts & STS_MSATA_IND; } static bool omnia_detect_wwan_usb3(const char *wwan_slot) @@ -393,32 +492,33 @@ static int omnia_get_ram_size_gb(void) static const char * const omnia_get_mcu_type(void) { - static const char * const mcu_types[] = { - [STS_MCU_TYPE_STM32] = "STM32", - [STS_MCU_TYPE_GD32] = "GD32", - [STS_MCU_TYPE_MKL] = "MKL", - [STS_MCU_TYPE_UNKN] = "unknown", - }; - static const char * const mcu_types_with_perip_resets[] = { - [STS_MCU_TYPE_STM32] = "STM32 (with peripheral resets)", - [STS_MCU_TYPE_GD32] = "GD32 (with peripheral resets)", - [STS_MCU_TYPE_MKL] = "MKL (with peripheral resets)", - [STS_MCU_TYPE_UNKN] = "unknown (with peripheral resets)", - }; - u16 stsword, features; + static char result[] = "xxxxxxx (with peripheral resets)"; + u16 sts; int ret; - ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + ret = omnia_mcu_get_sts(&sts); if (ret) return "unknown"; - if (stsword & STS_FEATURES_SUPPORTED) { - ret = omnia_mcu_read(CMD_GET_FEATURES, &features, sizeof(features)); - if (ret == 0 && (features & FEAT_PERIPH_MCU)) - return mcu_types_with_perip_resets[stsword & STS_MCU_TYPE_MASK]; + switch (sts & STS_MCU_TYPE_MASK) { + case STS_MCU_TYPE_STM32: + strcpy(result, "STM32"); + break; + case STS_MCU_TYPE_GD32: + strcpy(result, "GD32"); + break; + case STS_MCU_TYPE_MKL: + strcpy(result, "MKL"); + break; + default: + strcpy(result, "unknown"); + break; } - return mcu_types[stsword & STS_MCU_TYPE_MASK]; + if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) + strcat(result, " (with peripheral resets)"); + + return result; } static const char * const omnia_get_mcu_version(void) @@ -695,9 +795,6 @@ int board_early_init_f(void) void spl_board_init(void) { - u16 val; - int ret; - /* * If booting from UART, disable MCU watchdog in SPL, since uploading * U-Boot proper can take too much time and trigger it. Instead enable @@ -714,12 +811,8 @@ void spl_board_init(void) * resets then LAN eth switch is initialized automatically by bootstrap * pins when A385 is released from the reset. */ - ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); - if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { - ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); - if (ret == 0 && (val & FEAT_PERIPH_MCU)) - initialize_switch(); - } + if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) + initialize_switch(); } #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP) @@ -914,26 +1007,40 @@ static int fixup_mcu_gpio_in_eth_wan_node(void *blob) return 0; } +static void fixup_atsha_node(void *blob) +{ + int node; + + if (!omnia_mcu_has_feature(FEAT_CRYPTO)) + return; + + node = fdt_node_offset_by_compatible(blob, -1, "atmel,atsha204a"); + if (node < 0) { + printf("Cannot find ATSHA204A node!\n"); + return; + } + + if (fdt_status_disabled(blob, node) < 0) + printf("Cannot disable ATSHA204A node!\n"); + else + debug("Disabled ATSHA204A node\n"); +} + #endif #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { - u16 val; - int ret; - - ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); - if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { - ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); - if (ret == 0 && (val & FEAT_PERIPH_MCU)) { - fixup_mcu_gpio_in_pcie_nodes(blob); - fixup_mcu_gpio_in_eth_wan_node(blob); - } + if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) { + fixup_mcu_gpio_in_pcie_nodes(blob); + fixup_mcu_gpio_in_eth_wan_node(blob); } fixup_msata_port_nodes(blob); fixup_wwan_port_nodes(blob); + fixup_atsha_node(blob); + return 0; } #endif @@ -964,23 +1071,46 @@ int board_late_init(void) int checkboard(void) { - char serial[17]; + char serial[17], version[4], pub_key[67]; + bool has_version; int err; - err = turris_atsha_otp_get_serial_number(serial); - printf("Model: Turris Omnia\n"); printf(" MCU type: %s\n", omnia_get_mcu_type()); printf(" MCU version: %s\n", omnia_get_mcu_version()); printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); + + if (omnia_mcu_has_feature(FEAT_BOARD_INFO)) { + err = omnia_mcu_board_info(serial, NULL, version); + has_version = !err; + } else { + err = turris_atsha_otp_get_serial_number(serial); + has_version = false; + } + + printf(" Board version: %s\n", has_version ? version : "unknown"); printf(" Serial Number: %s\n", !err ? serial : "unknown"); + if (omnia_mcu_has_feature(FEAT_CRYPTO)) { + err = omnia_mcu_get_board_public_key(pub_key); + printf(" ECDSA Public Key: %s\n", !err ? pub_key : "unknown"); + } + return 0; } int misc_init_r(void) { - turris_atsha_otp_init_mac_addresses(1); - turris_atsha_otp_init_serial_number(); + if (omnia_mcu_has_feature(FEAT_BOARD_INFO)) { + char serial[17]; + u8 first_mac[6]; + + if (!omnia_mcu_board_info(serial, first_mac, NULL)) + turris_init_mac_addresses(1, first_mac); + } else { + turris_atsha_otp_init_mac_addresses(1); + turris_atsha_otp_init_serial_number(); + } + return 0; } @@ -1102,6 +1232,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) fixup_msata_port_nodes(blob); fixup_wwan_port_nodes(blob); + fixup_atsha_node(blob); + return 0; } #endif diff --git a/board/amlogic/jethub-j100/MAINTAINERS b/board/amlogic/jethub-j100/MAINTAINERS index 43f6a5fc86b..3edc5d8865c 100644 --- a/board/amlogic/jethub-j100/MAINTAINERS +++ b/board/amlogic/jethub-j100/MAINTAINERS @@ -1,5 +1,5 @@ JetHome JetHub -M: Vyacheslav Bocharov <adeep@lexina.in> +M: Viacheslav Bocharov <adeep@lexina.in> S: Maintained L: u-boot-amlogic@groups.io F: board/amlogic/jethub-j100/ diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 67e3d59b1f3..34094a020b0 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -18,6 +18,19 @@ bool dh_mac_is_in_env(const char *env) return eth_env_get_enetaddr(env, enetaddr); } +int dh_get_mac_is_enabled(const char *alias) +{ + ofnode node = ofnode_path(alias); + + if (!ofnode_valid(node)) + return -EINVAL; + + if (!ofnode_is_enabled(node)) + return -ENODEV; + + return 0; +} + int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias) { struct udevice *dev; @@ -57,6 +70,9 @@ __weak int dh_setup_mac_address(void) if (dh_mac_is_in_env("ethaddr")) return 0; + if (dh_get_mac_is_enabled("ethernet0")) + return 0; + if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) return eth_env_set_enetaddr("ethaddr", enetaddr); diff --git a/board/dhelectronics/common/dh_common.h b/board/dhelectronics/common/dh_common.h index 2b24637d96d..a2de5b1553e 100644 --- a/board/dhelectronics/common/dh_common.h +++ b/board/dhelectronics/common/dh_common.h @@ -12,6 +12,14 @@ bool dh_mac_is_in_env(const char *env); /* + * dh_get_mac_is_enabled - Test if ethernet MAC is enabled in DT + * + * @alias: alias for ethernet MAC device tree node + * Return: 0 if OK, other value on error + */ +int dh_get_mac_is_enabled(const char *alias); + +/* * dh_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr * * @enetaddr: buffer where address is to be stored diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 07fc9b1fe6d..0676587c38a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -92,6 +92,9 @@ int dh_setup_mac_address(void) if (dh_mac_is_in_env("ethaddr")) return 0; + if (dh_get_mac_is_enabled("ethernet0")) + return 0; + if (!dh_imx_get_mac_from_fuse(enetaddr)) goto out; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 5f12d787d38..ff2c0e87215 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -47,6 +47,9 @@ static int dh_imx8_setup_ethaddr(void) if (dh_mac_is_in_env("ethaddr")) return 0; + if (dh_get_mac_is_enabled("ethernet0")) + return 0; + if (!dh_imx_get_mac_from_fuse(enetaddr)) goto out; @@ -66,6 +69,9 @@ static int dh_imx8_setup_eth1addr(void) if (dh_mac_is_in_env("eth1addr")) return 0; + if (dh_get_mac_is_enabled("ethernet1")) + return 0; + if (!dh_imx_get_mac_from_fuse(enetaddr)) goto increment_out; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d1f662d9701..079dfff0389 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -128,6 +128,9 @@ static int dh_stm32_setup_ethaddr(void) if (dh_mac_is_in_env("ethaddr")) return 0; + if (dh_get_mac_is_enabled("ethernet0")) + return 0; + if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) return eth_env_set_enetaddr("ethaddr", enetaddr); @@ -141,6 +144,9 @@ static int dh_stm32_setup_eth1addr(void) if (dh_mac_is_in_env("eth1addr")) return 0; + if (dh_get_mac_is_enabled("ethernet1")) + return 0; + if (dh_stm32_mac_is_in_ks8851()) return 0; diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 181abbbf97d..173245b40e3 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -31,12 +31,6 @@ int is_flash_available(void) int board_init(void) { - /* - * Make sure virtio bus is enumerated so that peripherals - * on the virtio bus can be discovered by their drivers - */ - virtio_init(); - return 0; } @@ -46,6 +40,12 @@ int board_late_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init(); + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + return 0; } diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig index 9a0611820ce..b2a4e0891a4 100644 --- a/board/emulation/qemu-x86/Kconfig +++ b/board/emulation/qemu-x86/Kconfig @@ -18,7 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select QEMU select QFW_PIO if CMD_QFW - select BOARD_ROMSIZE_KB_1024 + select BOARD_ROMSIZE_KB_1024 if TARGET_QEMU_X86 + select BOARD_ROMSIZE_KB_2048 if TARGET_QEMU_X86_64 imply VIRTIO_PCI imply VIRTIO_NET imply VIRTIO_BLK diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 2fd5559195e..7331a20f94c 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) preloader_console_init(); - ret = imx9_probe_mu(NULL, NULL); + ret = imx9_probe_mu(); if (ret) { printf("Fail to init Sentinel API\n"); } else { diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 91a24018c40..618b4c370d1 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -57,3 +57,67 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif + +#if IS_ENABLED(CONFIG_ENV_IS_IN_FAT) || IS_ENABLED(CONFIG_ENV_IS_IN_MMC) +int mmc_get_env_dev(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return 0; + case BOOT_DEVICE_MMC2: + return 1; + }; + + return CONFIG_SYS_MMC_ENV_DEV; +} +#endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + u32 boot_device = get_boot_device(); + + if (prio) + return ENVL_UNKNOWN; + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: + if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT)) + return ENVL_FAT; + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC)) + return ENVL_MMC; + case BOOT_DEVICE_SPI: + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + default: + return ENVL_NOWHERE; + }; +} + +#if IS_ENABLED(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + u32 boot_device = get_boot_device(); + + switch (boot_device) { + case BOOT_DEVICE_MMC1: + env_set_ulong("mmcdev", 0); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_MMC2: + env_set_ulong("mmcdev", 1); + env_set("boot", "mmc"); + break; + case BOOT_DEVICE_SPI: + env_set("boot", "spi"); + break; + case BOOT_DEVICE_ETHERNET: + env_set("boot", "net"); + break; + }; + + return 0; +} +#endif diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index 16303fc187a..f03bfee9ffa 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -122,7 +122,7 @@ void board_init_f(ulong dummy) preloader_console_init(); - ret = imx9_probe_mu(NULL, NULL); + ret = imx9_probe_mu(); if (ret) { printf("Fail to init ELE API\n"); } else { diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 7dffb96f0a2..7f4811d8879 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -378,37 +378,6 @@ static bool has_emmc(void) return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1; } -/* Override the default implementation, DT model is not accurate */ -int checkboard(void) -{ - request_detect_gpios(); - - switch (board_type()) { - case CUBOXI: - puts("Board: MX6 Cubox-i"); - break; - case HUMMINGBOARD: - puts("Board: MX6 HummingBoard"); - break; - case HUMMINGBOARD2: - puts("Board: MX6 HummingBoard2"); - break; - case UNKNOWN: - default: - puts("Board: Unknown\n"); - goto out; - } - - if (is_rev_15_som()) - puts(" (som rev 1.5)\n"); - else - puts("\n"); - - free_detect_gpios(); -out: - return 0; -} - static int find_ethernet_phy(void) { struct mii_dev *bus = NULL; @@ -502,12 +471,15 @@ int board_late_init(void) switch (board_type()) { case CUBOXI: env_set("board_name", "CUBOXI"); + puts("Board: MX6 Cubox-i"); break; case HUMMINGBOARD: env_set("board_name", "HUMMINGBOARD"); + puts("Board: MX6 HummingBoard"); break; case HUMMINGBOARD2: env_set("board_name", "HUMMINGBOARD2"); + puts("Board: MX6 HummingBoard2"); break; case UNKNOWN: default: @@ -519,8 +491,12 @@ int board_late_init(void) else env_set("board_rev", "MX6DL"); - if (is_rev_15_som()) + if (is_rev_15_som()) { env_set("som_rev", "V15"); + puts(" (som rev 1.5)\n"); + } else { + puts("\n"); + } if (has_emmc()) env_set("has_emmc", "yes"); diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig index 2a458f291cc..040a7487f1b 100644 --- a/board/sophgo/milkv_duo/Kconfig +++ b/board/sophgo/milkv_duo/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "sophgo" config SYS_CPU - default "generic" + default "cv1800b" config SYS_CONFIG_NAME default "milkv_duo" @@ -23,6 +23,6 @@ config ENV_SECT_SIZE config BOARD_SPECIFIC_OPTIONS def_bool y - select GENERIC_RISCV + select SOPHGO_CV1800B endif diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 1b49945d11b..45848db6d8b 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <asm/arch/eeprom.h> #include <asm/arch/gpio.h> #include <asm/arch/regs.h> @@ -27,6 +26,26 @@ struct starfive_vf2_pro { const char *value; }; +static const struct starfive_vf2_pro milk_v_mars[] = { + {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, + {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, + + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-adj-enabled", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-100-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,tx-clk-1000-inverted", NULL}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-clk-drv-microamp", "3970"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "motorcomm,rx-data-drv-microamp", "2910"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "rx-internal-delay-ps", "1900"}, + {"/soc/ethernet@16030000/mdio/ethernet-phy@0", + "tx-internal-delay-ps", "1500"}, +}; + static const struct starfive_vf2_pro starfive_vera[] = { {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", "1900"}, @@ -67,6 +86,49 @@ static const struct starfive_vf2_pro starfive_verb[] = { "tx-internal-delay-ps", "0"}, }; +void spl_fdt_fixup_mars(void *fdt) +{ + static const char compat[] = "milkv,mars\0starfive,jh7110"; + u32 phandle; + u8 i; + int offset; + int ret; + + fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", + "Milk-V Mars"); + + /* gmac0 */ + offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); + phandle = fdt_get_phandle(fdt, offset); + offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); + + fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); + fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); + fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", + JH7110_AONCLK_GMAC0_RMII_RTX); + + /* gmac1 */ + fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), + "status", "disabled"); + + for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) { + offset = fdt_path_offset(fdt, milk_v_mars[i].path); + + if (milk_v_mars[i].value) + ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name, + dectoul(milk_v_mars[i].value, NULL)); + else + ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name); + + if (ret) { + pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name); + break; + } + } +} + void spl_fdt_fixup_version_a(void *fdt) { static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110"; @@ -167,22 +229,34 @@ void spl_fdt_fixup_version_b(void *fdt) void spl_perform_fixups(struct spl_image_info *spl_image) { u8 version; + const char *product_id; - version = get_pcb_revision_from_eeprom(); - switch (version) { - case 'a': - case 'A': - spl_fdt_fixup_version_a(spl_image->fdt_addr); - break; - - case 'b': - case 'B': - default: - spl_fdt_fixup_version_b(spl_image->fdt_addr); + product_id = get_product_id_from_eeprom(); + if (!product_id) { + pr_err("Can't read EEPROM\n"); + return; + } + if (!strncmp(product_id, "MARS", 4)) { + spl_fdt_fixup_mars(spl_image->fdt_addr); + } else if (!strncmp(product_id, "VF7110", 6)) { + version = get_pcb_revision_from_eeprom(); + switch (version) { + case 'a': + case 'A': + spl_fdt_fixup_version_a(spl_image->fdt_addr); + break; + + case 'b': + case 'B': + default: + spl_fdt_fixup_version_b(spl_image->fdt_addr); break; + }; + } else { + pr_err("Unknown product %s\n", product_id); }; - /* Update the memory size which read form eeprom or DT */ + /* Update the memory size which read from eeprom or DT */ fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 78e118d5a05..a86bca533b2 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -4,11 +4,11 @@ * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <fdt_support.h> #include <env.h> +#include <log.h> #include <asm/arch/eeprom.h> #include <asm/io.h> #include <asm/sections.h> @@ -17,6 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; #define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000 #define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 +#define FDTFILE_MILK_V_MARS \ + "starfive/jh7110-milkv-mars.dtb" #define FDTFILE_VISIONFIVE2_1_2A \ "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb" #define FDTFILE_VISIONFIVE2_1_3B \ @@ -48,20 +50,38 @@ static void set_fdtfile(void) { u8 version; const char *fdtfile; + const char *product_id; - version = get_pcb_revision_from_eeprom(); - switch (version) { - case 'a': - case 'A': - fdtfile = FDTFILE_VISIONFIVE2_1_2A; - break; - - case 'b': - case 'B': - default: - fdtfile = FDTFILE_VISIONFIVE2_1_3B; - break; - }; + fdtfile = env_get("fdtfile"); + if (fdtfile) + return; + + product_id = get_product_id_from_eeprom(); + if (!product_id) { + log_err("Can't read EEPROM\n"); + return; + } + if (!strncmp(product_id, "MARS", 4)) { + fdtfile = FDTFILE_MILK_V_MARS; + } else if (!strncmp(product_id, "VF7110", 6)) { + version = get_pcb_revision_from_eeprom(); + + switch (version) { + case 'a': + case 'A': + fdtfile = FDTFILE_VISIONFIVE2_1_2A; + break; + + case 'b': + case 'B': + default: + fdtfile = FDTFILE_VISIONFIVE2_1_3B; + break; + } + } else { + log_err("Unknown product\n"); + return; + } env_set("fdtfile", fdtfile); } diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index c36de1a5125..ddef7d61235 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <command.h> #include <env.h> #include <i2c.h> @@ -405,6 +404,14 @@ static void set_product_id(char *string) update_crc(); } +const char *get_product_id_from_eeprom(void) +{ + if (read_eeprom()) + return NULL; + + return pbuf.eeprom.atom1.data.pstr; +} + int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char *cmd; diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS index 4e75980dbd7..3e30d1d5112 100644 --- a/board/toradex/verdin-am62/MAINTAINERS +++ b/board/toradex/verdin-am62/MAINTAINERS @@ -1,12 +1,8 @@ Verdin AM62 F: arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi F: arch/arm/dts/k3-am625-verdin-r5.dts -F: arch/arm/dts/k3-am625-verdin-wifi-dev.dts F: arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi F: arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi -F: arch/arm/dts/k3-am62-verdin-dev.dtsi -F: arch/arm/dts/k3-am62-verdin.dtsi -F: arch/arm/dts/k3-am62-verdin-wifi.dtsi F: board/toradex/verdin-am62/ F: configs/verdin-am62_a53_defconfig F: configs/verdin-am62_r5_defconfig diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS index 8217bbcdc0c..d567f0e1097 100644 --- a/board/toradex/verdin-imx8mm/MAINTAINERS +++ b/board/toradex/verdin-imx8mm/MAINTAINERS @@ -2,10 +2,6 @@ Verdin iMX8M Mini M: Marcel Ziswiler <marcel.ziswiler@toradex.com> W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini S: Maintained -F: arch/arm/dts/imx8mm-verdin.dtsi -F: arch/arm/dts/imx8mm-verdin-dev.dtsi -F: arch/arm/dts/imx8mm-verdin-wifi.dtsi -F: arch/arm/dts/imx8mm-verdin-wifi-dev.dts F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi F: board/toradex/verdin-imx8mm/ F: board/toradex/common/ diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS index 85d6be88163..9fe76d8e42f 100644 --- a/board/toradex/verdin-imx8mp/MAINTAINERS +++ b/board/toradex/verdin-imx8mp/MAINTAINERS @@ -1,8 +1,4 @@ Verdin iMX8M Plus -F: arch/arm/dts/imx8mp-verdin.dtsi -F: arch/arm/dts/imx8mp-verdin-dev.dtsi -F: arch/arm/dts/imx8mp-verdin-wifi.dtsi -F: arch/arm/dts/imx8mp-verdin-wifi-dev.dts F: arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi F: board/toradex/verdin-imx8mp/ F: board/toradex/common/ diff --git a/board/variscite/imx93_var_som/spl.c b/board/variscite/imx93_var_som/spl.c index 36e17219d63..71f346cf77b 100644 --- a/board/variscite/imx93_var_som/spl.c +++ b/board/variscite/imx93_var_som/spl.c @@ -121,7 +121,7 @@ void board_init_f(ulong dummy) preloader_console_init(); - ret = imx9_probe_mu(NULL, NULL); + ret = imx9_probe_mu(); if (ret) { printf("Fail to init ELE API\n"); } else { diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 843198fa0da..5c4ad8f1df9 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -45,6 +45,7 @@ config XILINX_OF_BOARD_DTB_ADDR default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP + default 0x23000000 if TARGET_XILINX_MBV depends on OF_BOARD || OF_SEPARATE help Offset in the memory where the board configuration DTB is placed. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 9641ed307b7..b47d2d23f91 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -12,6 +12,7 @@ #include <env.h> #include <image.h> #include <init.h> +#include <jffs2/load_kernel.h> #include <lmb.h> #include <log.h> #include <asm/global_data.h> @@ -20,6 +21,7 @@ #include <i2c.h> #include <linux/sizes.h> #include <malloc.h> +#include <mtd_node.h> #include "board.h" #include <dm.h> #include <i2c_eeprom.h> @@ -43,7 +45,7 @@ struct efi_fw_image fw_images[] = { .image_index = 1, }, #endif -#if defined(XILINX_UBOOT_IMAGE_GUID) +#if defined(XILINX_UBOOT_IMAGE_GUID) && defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) { .image_type_id = XILINX_UBOOT_IMAGE_GUID, .fw_name = u"XILINX-UBOOT", @@ -103,10 +105,14 @@ static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size) for (i = 0; i < size; i++) { byte = eeprom[i]; - /* Remove all non printable chars but ignore MAC address */ - if ((i < offsetof(struct xilinx_legacy_format, eth_mac) || - i >= offsetof(struct xilinx_legacy_format, unused1)) && - (byte < '!' || byte > '~')) { + /* Ignore MAC address */ + if (i >= offsetof(struct xilinx_legacy_format, eth_mac) && + i < offsetof(struct xilinx_legacy_format, unused1)) { + continue; + } + + /* Remove all non printable chars */ + if (byte < '!' || byte > '~') { eeprom[i] = 0; continue; } @@ -358,6 +364,14 @@ void *board_fdt_blob_setup(int *err) void *fdt_blob; *err = 0; + + if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) { + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; + } + if (!IS_ENABLED(CONFIG_SPL_BUILD) && !IS_ENABLED(CONFIG_VERSAL_NO_DDR) && !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { @@ -693,6 +707,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 buf[MAX_RAND_SIZE]; int nodeoffset, ret; + static const struct node_info nodes[] = { + { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, }, + }; + + if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ)) + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) { debug("No RNG device\n"); return 0; diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index d2dec397ed6..a3a6f212577 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -10,15 +10,25 @@ config SYS_CPU default "generic" config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80400000 if RISCV_SMODE && ARCH_RV32I + default 0x21200000 + +config SPL_TEXT_BASE + default 0x20000000 + +config SPL_OPENSBI_LOAD_ADDR + hex + default 0x20200000 config BOARD_SPECIFIC_OPTIONS def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply BOARD_LATE_INIT + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING + imply OF_HAS_PRIOR_STAGE source "board/xilinx/Kconfig" diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index ccf4395d6ac..c478f7e04a0 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -5,7 +5,17 @@ * Michal Simek <michal.simek@amd.com> */ +#include <spl.h> + int board_init(void) { return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 990ca1650aa..da03024e162 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -371,3 +371,35 @@ int dram_init(void) void reset_cpu(void) { } + +#if defined(CONFIG_ENV_IS_NOWHERE) +enum env_location env_get_location(enum env_operation op, int prio) +{ + u8 bootmode = versal_net_get_bootmode(); + + if (prio) + return ENVL_UNKNOWN; + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT)) + return ENVL_FAT; + if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4)) + return ENVL_EXT4; + return ENVL_NOWHERE; + case OSPI_MODE: + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + return ENVL_NOWHERE; + case JTAG_MODE: + case SELECTMAP_MODE: + default: + return ENVL_NOWHERE; + } +} +#endif diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 8c2e614ad8a..4f6d56119db 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -291,6 +291,7 @@ void reset_cpu(void) { } +#if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) { u32 bootmode = versal_get_bootmode(); @@ -320,3 +321,4 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_NOWHERE; } } +#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba49eb7be22..f370fb7347a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -588,6 +588,7 @@ int mmc_get_env_dev(void) return bootseq; } +#if defined(CONFIG_ENV_IS_NOWHERE) enum env_location env_get_location(enum env_operation op, int prio) { u32 bootmode = zynqmp_get_bootmode(); @@ -621,11 +622,37 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_NOWHERE; } } +#endif #if defined(CONFIG_SET_DFU_ALT_INFO) #define DFU_ALT_BUF_LEN SZ_1K +static void mtd_found_part(u32 *base, u32 *size) +{ + struct mtd_info *part, *mtd; + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (!IS_ERR_OR_NULL(mtd)) { + list_for_each_entry(part, &mtd->partitions, node) { + debug("0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, + part->name); + + if (*base >= part->offset && + *base < part->offset + part->size) { + debug("Found my partition: %d/%s\n", + part->index, part->name); + *base = part->offset; + *size = part->size; + break; + } + } + } +} + void set_dfu_alt_info(char *interface, char *devstr) { int multiboot, bootseq = 0, len = 0; @@ -661,21 +688,38 @@ void set_dfu_alt_info(char *interface, char *devstr) len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", bootseq); #if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) - len += snprintf(buf + len, DFU_ALT_BUF_LEN, ";%s fat %d 1", - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq); + if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + ";%s fat %d 1", + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, + bootseq); #endif break; case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: - len += snprintf(buf + len, DFU_ALT_BUF_LEN, - "sf 0:0=boot.bin raw %x 0x1500000", - multiboot * SZ_32K); + { + u32 base = multiboot * SZ_32K; + u32 size = 0x1500000; + u32 limit = size; + + mtd_found_part(&base, &limit); + +#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) + size = limit; + limit = CONFIG_SYS_SPI_U_BOOT_OFFS; +#endif + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0x%x 0x%x", + base, limit); #if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) && defined(CONFIG_SYS_SPI_U_BOOT_OFFS) - len += snprintf(buf + len, DFU_ALT_BUF_LEN, - ";%s raw 0x%x 0x500000", - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, - multiboot * SZ_32K + CONFIG_SYS_SPI_U_BOOT_OFFS); + if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + ";%s raw 0x%x 0x%x", + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, + base + limit, size - limit); #endif + } break; default: return; diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 0f940bd68f8..846eceb0118 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -17,6 +17,7 @@ bootcmd_usb0=devnum=0; run usb_boot bootcmd_usb1=devnum=1; run usb_boot bootcmd_usb2=devnum=2; run usb_boot bootcmd_usb3=devnum=3; run usb_boot +bootcmd_usb4=devnum=4; run usb_boot bootdelay=2 bootfstype=fat bootm_low=0 @@ -44,7 +45,8 @@ usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boo preboot=setenv boot_targets; setenv modeboot; run board_setup # SOM specific boot methods -som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; fi;" +usb_boot_devices='usb0 usb1 usb2 usb3 usb4' +som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; fi;" som_mmc_boot=setenv boot_targets mmc0 && run distro_bootcmd k26_starter=SMK-K26-XCL2G diff --git a/boot/Kconfig b/boot/Kconfig index 3d7aabd27d6..777e408e243 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -2,39 +2,6 @@ menu "Boot options" menu "Boot images" -config ANDROID_BOOT_IMAGE - bool "Android Boot Images" - default y if FASTBOOT - help - This enables support for booting images which use the Android - image format header. - -config TIMESTAMP - bool "Show image date and time when displaying image information" - default y if CMD_DATE - help - When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of - an image is printed by image commands like bootm or iminfo. This - is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is - enabled, then U-Boot requires FITs to have a timestamp. If a FIT is - loaded that does not, the message 'Wrong FIT format: no timestamp' - is shown. - -config BUTTON_CMD - bool "Support for running a command if a button is held during boot" - depends on CMDLINE - depends on BUTTON - help - For many embedded devices it's useful to enter a special flashing mode - such as fastboot mode when a button is held during boot. This option - allows arbitrary commands to be assigned to specific buttons. These will - be run after "preboot" if the button is held. Configuration is done via - the environment variables "button_cmd_N_name" and "button_cmd_N" where n is - the button number (starting from 0). e.g: - - "button_cmd_0_name=vol_down" - "button_cmd_0=fastboot usb 0" - menuconfig FIT bool "Flattened Image Tree (FIT)" select HASH @@ -558,6 +525,16 @@ config BOOTMETH_EFILOADER This provides a way to try out standard boot on an existing boot flow. +config BOOTMETH_EFI_BOOTMGR + bool "Bootdev support for EFI boot manager" + depends on EFI_BOOTMGR + select BOOTMETH_GLOBAL + default y + help + Enable booting via the UEFI boot manager. Based on the EFI variables + the EFI binary to be launched is determined. To set the EFI variables + use the eficonfig command. + config BOOTMETH_VBE bool "Bootdev support for Verified Boot for Embedded" depends on FIT @@ -711,6 +688,100 @@ config BOOTMETH_SCRIPT endif # BOOTSTD +config BOOTM + bool "Support booting an application image from memory" + default y + help + This is the main boot implementation in U-Boot, supporting a wide + variety of features including FIT and legacy-image boot, kernel and + FDT selection, setting up of the command line for the OS and many + other features. + + This option should normally be enabled. It is used to implement the + 'bootm' command. + +config BOOTM_LINUX + bool "Support booting Linux OS images" + depends on BOOTM || CMD_BOOTZ || CMD_BOOTI + default y + help + Support booting the Linux kernel directly via a command such as bootm + or booti or bootz. + +config BOOTM_NETBSD + bool "Support booting NetBSD (non-EFI) loader images" + depends on BOOTM + default y + help + Support booting NetBSD via the bootm command. + +config BOOTM_OPENRTOS + bool "Support booting OPENRTOS / FreeRTOS images" + depends on BOOTM + help + Support booting OPENRTOS / FreeRTOS via the bootm command. + +config BOOTM_OSE + bool "Support booting Enea OSE images" + depends on (ARM && (ARM64 || CPU_V7A || CPU_V7R) || SANDBOX || PPC || X86) + depends on BOOTM + help + Support booting Enea OSE images via the bootm command. + +config BOOTM_PLAN9 + bool "Support booting Plan9 OS images" + depends on BOOTM + default y + help + Support booting Plan9 images via the bootm command. + +config BOOTM_RTEMS + bool "Support booting RTEMS OS images" + depends on BOOTM + default y + help + Support booting RTEMS images via the bootm command. + +config BOOTM_VXWORKS + bool "Support booting VxWorks OS images" + depends on BOOTM + default y + help + Support booting VxWorks images via the bootm command. + +config ANDROID_BOOT_IMAGE + bool "Android Boot Images" + default y if FASTBOOT + help + This enables support for booting images which use the Android + image format header. + +config TIMESTAMP + bool "Show image date and time when displaying image information" + default y if CMD_DATE + help + When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of + an image is printed by image commands like bootm or iminfo. This + is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is + enabled, then U-Boot requires FITs to have a timestamp. If a FIT is + loaded that does not, the message 'Wrong FIT format: no timestamp' + is shown. + +config BUTTON_CMD + bool "Support for running a command if a button is held during boot" + depends on CMDLINE + depends on BUTTON + help + For many embedded devices it's useful to enter a special flashing mode + such as fastboot mode when a button is held during boot. This option + allows arbitrary commands to be assigned to specific buttons. These will + be run after "preboot" if the button is held. Configuration is done via + the environment variables "button_cmd_N_name" and "button_cmd_N" where n is + the button number (starting from 0). e.g: + + "button_cmd_0_name=vol_down" + "button_cmd_0=fastboot usb 0" + config LEGACY_IMAGE_FORMAT bool "Enable support for the legacy image format" default y if !FIT_SIGNATURE && !TI_SECURE_DEVICE @@ -755,7 +826,7 @@ endif # MEASURED_BOOT config SYS_BOOTM_LEN hex "Maximum size of a decompresed OS image" - depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ + depends on BOOTM || CMD_BOOTI || CMD_BOOTZ || \ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT default 0x4000000 if PPC || ARM64 default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 diff --git a/boot/Makefile b/boot/Makefile index f0a279cde16..bf767fd5356 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -6,7 +6,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_BOOT_RETRY) += bootretry.o -obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o +obj-$(CONFIG_BOOTM) += bootm.o bootm_os.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o @@ -34,8 +34,8 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o +obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFI_BOOTMGR) += bootmeth_efi_mgr.o ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL -obj-$(CONFIG_EFI_BOOTMGR) += bootmeth_efi_mgr.o obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o endif diff --git a/boot/bootm.c b/boot/bootm.c index d071537d692..032f5a4a160 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -242,13 +242,13 @@ static int boot_get_kernel(const char *addr_fit, struct bootm_headers *images, #ifdef CONFIG_LMB static void boot_start_lmb(struct bootm_headers *images) { - ulong mem_start; + phys_addr_t mem_start; phys_size_t mem_size; mem_start = env_get_bootm_low(); mem_size = env_get_bootm_size(); - lmb_init_and_reserve_range(&images->lmb, (phys_addr_t)mem_start, + lmb_init_and_reserve_range(&images->lmb, mem_start, mem_size, NULL); } #else diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c index cd72db8250c..f015f2e1c75 100644 --- a/boot/bootmeth_cros.c +++ b/boot/bootmeth_cros.c @@ -432,9 +432,9 @@ static int cros_boot(struct udevice *dev, struct bootflow *bflow) } if (IS_ENABLED(CONFIG_X86)) { - ret = zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0, - map_to_sysmem(bflow->x86_setup), - bflow->cmdline); + ret = zboot_run(map_to_sysmem(bflow->buf), bflow->size, 0, 0, + map_to_sysmem(bflow->x86_setup), + bflow->cmdline); } else { ret = bootm_boot_start(map_to_sysmem(bflow->buf), bflow->cmdline); diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index c4eb331d69e..aebc5207fc0 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -14,6 +14,7 @@ #include <bootmeth.h> #include <command.h> #include <dm.h> +#include <efi_default_filename.h> #include <efi_loader.h> #include <fs.h> #include <malloc.h> @@ -23,43 +24,7 @@ #include <pxe_utils.h> #include <linux/sizes.h> -#define EFI_DIRNAME "efi/boot/" - -/** - * get_efi_leafname() - Get the leaf name for the EFI file we expect - * - * @str: Place to put leaf name for this architecture, e.g. "bootaa64.efi". - * Must have at least 16 bytes of space - * @max_len: Length of @str, must be >=16 - */ -static int get_efi_leafname(char *str, int max_len) -{ - const char *base; - - if (max_len < 16) - return log_msg_ret("spc", -ENOSPC); - if (IS_ENABLED(CONFIG_ARM64)) - base = "bootaa64"; - else if (IS_ENABLED(CONFIG_ARM)) - base = "bootarm"; - else if (IS_ENABLED(CONFIG_X86_RUN_32BIT)) - base = "bootia32"; - else if (IS_ENABLED(CONFIG_X86_RUN_64BIT)) - base = "bootx64"; - else if (IS_ENABLED(CONFIG_ARCH_RV32I)) - base = "bootriscv32"; - else if (IS_ENABLED(CONFIG_ARCH_RV64I)) - base = "bootriscv64"; - else if (IS_ENABLED(CONFIG_SANDBOX)) - base = "bootsbox"; - else - return -EINVAL; - - strcpy(str, base); - strcat(str, ".efi"); - - return 0; -} +#define EFI_DIRNAME "/EFI/BOOT/" static int get_efi_pxe_arch(void) { @@ -259,10 +224,7 @@ static int distro_efi_try_bootflow_files(struct udevice *dev, return -ENOENT; strcpy(fname, EFI_DIRNAME); - ret = get_efi_leafname(fname + strlen(fname), - sizeof(fname) - strlen(fname)); - if (ret) - return log_msg_ret("leaf", ret); + strcat(fname, BOOTEFI_NAME); if (bflow->blk) desc = dev_get_uclass_plat(bflow->blk); @@ -489,7 +451,7 @@ static const struct udevice_id distro_efi_bootmeth_ids[] = { { } }; -U_BOOT_DRIVER(bootmeth_efi) = { +U_BOOT_DRIVER(bootmeth_4efi) = { .name = "bootmeth_efi", .id = UCLASS_BOOTMETH, .of_match = distro_efi_bootmeth_ids, diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index ed29d7ef021..b7d429f2c3d 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -114,7 +114,7 @@ static const struct udevice_id efi_mgr_bootmeth_ids[] = { { } }; -U_BOOT_DRIVER(bootmeth_efi_mgr) = { +U_BOOT_DRIVER(bootmeth_3efi_mgr) = { .name = "bootmeth_efi_mgr", .id = UCLASS_BOOTMETH, .of_match = efi_mgr_bootmeth_ids, diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index 8d489a11aa4..70f693aa239 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -184,7 +184,7 @@ static const struct udevice_id extlinux_bootmeth_pxe_ids[] = { { } }; -U_BOOT_DRIVER(bootmeth_pxe) = { +U_BOOT_DRIVER(bootmeth_zpxe) = { .name = "bootmeth_pxe", .id = UCLASS_BOOTMETH, .of_match = extlinux_bootmeth_pxe_ids, diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 090d82ee80a..9844c70be80 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -17,6 +17,7 @@ #include <linux/ctype.h> #include <linux/types.h> #include <asm/global_data.h> +#include <asm/unaligned.h> #include <linux/libfdt.h> #include <fdt_support.h> #include <exports.h> @@ -421,13 +422,13 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, for (i = 0; i < n; i++) { if (address_cells == 2) - *(fdt64_t *)p = cpu_to_fdt64(address[i]); + put_unaligned_be64(address[i], p); else *(fdt32_t *)p = cpu_to_fdt32(address[i]); p += 4 * address_cells; if (size_cells == 2) - *(fdt64_t *)p = cpu_to_fdt64(size[i]); + put_unaligned_be64(size[i], p); else *(fdt32_t *)p = cpu_to_fdt32(size[i]); p += 4 * size_cells; diff --git a/boot/image-board.c b/boot/image-board.c index 75f6906cd56..09b6e4e0bdc 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -107,14 +107,12 @@ static int on_loadaddr(const char *name, const char *value, enum env_op op, } U_BOOT_ENV_CALLBACK(loadaddr, on_loadaddr); -ulong env_get_bootm_low(void) +phys_addr_t env_get_bootm_low(void) { char *s = env_get("bootm_low"); - if (s) { - ulong tmp = hextoul(s, NULL); - return tmp; - } + if (s) + return simple_strtoull(s, NULL, 16); #if defined(CFG_SYS_SDRAM_BASE) return CFG_SYS_SDRAM_BASE; @@ -127,14 +125,12 @@ ulong env_get_bootm_low(void) phys_size_t env_get_bootm_size(void) { - phys_size_t tmp, size; - phys_addr_t start; + phys_addr_t start, low; + phys_size_t size; char *s = env_get("bootm_size"); - if (s) { - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); - return tmp; - } + if (s) + return simple_strtoull(s, NULL, 16); start = gd->ram_base; size = gd->ram_size; @@ -144,22 +140,19 @@ phys_size_t env_get_bootm_size(void) s = env_get("bootm_low"); if (s) - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); + low = simple_strtoull(s, NULL, 16); else - tmp = start; + low = start; - return size - (tmp - start); + return size - (low - start); } phys_size_t env_get_bootm_mapsize(void) { - phys_size_t tmp; char *s = env_get("bootm_mapsize"); - if (s) { - tmp = (phys_size_t)simple_strtoull(s, NULL, 16); - return tmp; - } + if (s) + return simple_strtoull(s, NULL, 16); #if defined(CFG_SYS_BOOTMAPSZ) return CFG_SYS_BOOTMAPSZ; @@ -538,7 +531,7 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end) { char *s; - ulong initrd_high; + phys_addr_t initrd_high; int initrd_copy_to_ram = 1; s = env_get("initrd_high"); @@ -553,8 +546,8 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, initrd_high = env_get_bootm_mapsize() + env_get_bootm_low(); } - debug("## initrd_high = 0x%08lx, copy_to_ram = %d\n", - initrd_high, initrd_copy_to_ram); + debug("## initrd_high = 0x%llx, copy_to_ram = %d\n", + (u64)initrd_high, initrd_copy_to_ram); if (rd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 5e4aa9de0d2..2b92bdaff16 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -160,9 +160,11 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) { void *fdt_blob = *of_flat_tree; void *of_start = NULL; - u64 start, size, usable; + phys_addr_t start, size, usable; char *fdt_high; - ulong mapsize, low; + phys_addr_t addr; + phys_addr_t low; + phys_size_t mapsize; ulong of_len = 0; int bank; int err; @@ -185,7 +187,6 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) fdt_high = env_get("fdt_high"); if (fdt_high) { ulong desired_addr = hextoul(fdt_high, NULL); - ulong addr; if (desired_addr == ~0UL) { /* All ones means use fdt in place */ @@ -217,14 +218,14 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) if (start + size < low) continue; - usable = min(start + size, (u64)(low + mapsize)); - /* * At least part of this DRAM bank is usable, try - * using it for LMB allocation. + * using the DRAM bank up to 'usable' address limit + * for LMB allocation. */ - of_start = map_sysmem((ulong)lmb_alloc_base(lmb, - of_len, 0x1000, usable), of_len); + usable = min(start + size, low + mapsize); + addr = lmb_alloc_base(lmb, of_len, 0x1000, usable); + of_start = map_sysmem(addr, of_len); /* Allocation succeeded, use this block. */ if (of_start != NULL) break; @@ -233,7 +234,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) * Reduce the mapping size in the next bank * by the size of attempt in current bank. */ - mapsize -= usable - max(start, (u64)low); + mapsize -= usable - max(start, low); if (!mapsize) break; } diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 96205626750..d5e1bead125 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <bootm.h> #include <command.h> #include <dm.h> #include <env.h> @@ -470,6 +471,220 @@ skip_overlay: #endif /** + * calc_fdt_fname() - Figure out the filename to use for the FDT + * + * Determine the path to the FDT filename, based on the "fdtfile" environment + * variable. Use <soc>-<board>.dtb as a fallback + * + * @fdtdir: Directory to use for the FDT file + * Return: allocated filename (including directory), or NULL if out of memory + */ +static char *calc_fdt_fname(const char *fdtdir) +{ + char *fdtfile; + char *f1, *f2, *f3, *f4, *slash; + int len; + + f1 = env_get("fdtfile"); + if (f1) { + f2 = ""; + f3 = ""; + f4 = ""; + } else { + /* + * For complex cases where this code doesn't generate the + * correct filename, the board code should set $fdtfile during + * early boot, or the boot scripts should set $fdtfile before + * invoking "pxe" or "sysboot". + */ + f1 = env_get("soc"); + f2 = "-"; + f3 = env_get("board"); + f4 = ".dtb"; + if (!f1) { + f1 = ""; + f2 = ""; + } + if (!f3) { + f2 = ""; + f3 = ""; + } + } + + len = strlen(fdtdir); + if (!len) + slash = "./"; + else if (fdtdir[len - 1] != '/') + slash = "/"; + else + slash = ""; + + len = strlen(fdtdir) + strlen(slash) + strlen(f1) + strlen(f2) + + strlen(f3) + strlen(f4) + 1; + fdtfile = malloc(len); + if (!fdtfile) { + printf("malloc fail (FDT filename)\n"); + return NULL; + } + + snprintf(fdtfile, len, "%s%s%s%s%s%s", fdtdir, slash, f1, f2, f3, f4); + + return fdtfile; +} + +/** + * label_run_boot() - Run the correct boot procedure + * + * fdt usage is optional: + * It handles the following scenarios. + * + * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is + * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to + * bootm, and adjust argc appropriately. + * + * If retrieve fails and no exact fdt blob is specified in pxe file with + * "fdt" label, try Scenario 2. + * + * Scenario 2: If there is an fdt_addr specified, pass it along to + * bootm, and adjust argc appropriately. + * + * Scenario 3: If there is an fdtcontroladdr specified, pass it along to + * bootm, and adjust argc appropriately, unless the image type is fitImage. + * + * Scenario 4: fdt blob is not available. + * + * @ctx: PXE context + * @label: Label to process + * @kernel_addr: string containing the kernel address / config + * @initrd_str: string containing the initrd address / size + * @initrd_addr_str: initrd address, or NULL if none + * @initrd_filesize: initrd size in bytes; only valid if initrd_addr_str is not + * NULL + * Returns does not return on success, otherwise returns 0 if a localboot + * label was processed, or 1 on error + */ +static int label_run_boot(struct pxe_context *ctx, struct pxe_label *label, + char *kernel_addr, char *initrd_str, + char *initrd_addr_str, char *initrd_filesize) +{ + struct bootm_info bmi; + const char *fdt_addr; + ulong kernel_addr_r; + void *buf; + int ret; + + if (IS_ENABLED(CONFIG_BOOTM)) + bootm_init(&bmi); + + fdt_addr = env_get("fdt_addr_r"); + + /* For FIT, the label can be identical to kernel one */ + if (label->fdt && !strcmp(label->kernel_label, label->fdt)) { + fdt_addr = kernel_addr; + /* if fdt label is defined then get fdt from server */ + } else if (fdt_addr) { + char *fdtfile = NULL; + char *fdtfilefree = NULL; + + if (label->fdt) { + if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { + if (strcmp("-", label->fdt)) + fdtfile = label->fdt; + } else { + fdtfile = label->fdt; + } + } else if (label->fdtdir) { + fdtfilefree = calc_fdt_fname(label->fdtdir); + if (!fdtfilefree) + return -ENOMEM; + fdtfile = fdtfilefree; + } + + if (fdtfile) { + int err = get_relfile_envaddr(ctx, fdtfile, + "fdt_addr_r", NULL); + + free(fdtfilefree); + if (err < 0) { + fdt_addr = NULL; + + if (label->fdt) { + printf("Skipping %s for failure retrieving FDT\n", + label->name); + return -ENOENT; + } + + if (label->fdtdir) { + printf("Skipping fdtdir %s for failure retrieving dts\n", + label->fdtdir); + } + } + + if (label->kaslrseed) + label_boot_kaslrseed(); + +#ifdef CONFIG_OF_LIBFDT_OVERLAY + if (label->fdtoverlays) + label_boot_fdtoverlay(ctx, label); +#endif + } else { + fdt_addr = NULL; + } + } + + bmi.addr_img = kernel_addr; + + if (initrd_addr_str) + bmi.conf_ramdisk = initrd_str; + + if (!fdt_addr) { + if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { + if (strcmp("-", label->fdt)) + fdt_addr = env_get("fdt_addr"); + } else { + fdt_addr = env_get("fdt_addr"); + } + } + + kernel_addr_r = genimg_get_kernel_addr(kernel_addr); + buf = map_sysmem(kernel_addr_r, 0); + + if (!fdt_addr && genimg_get_format(buf) != IMAGE_FORMAT_FIT) { + if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { + if (strcmp("-", label->fdt)) + fdt_addr = env_get("fdtcontroladdr"); + } else { + fdt_addr = env_get("fdtcontroladdr"); + } + } + + bmi.conf_fdt = fdt_addr; + + /* Try bootm for legacy and FIT format image */ + if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID && + IS_ENABLED(CONFIG_BOOTM)) + ret = bootm_run(&bmi); + /* Try booting an AArch64 Linux kernel image */ + else if (IS_ENABLED(CONFIG_BOOTM)) + ret = booti_run(&bmi); + /* Try booting a Image */ + else if (IS_ENABLED(CONFIG_BOOTM)) + ret = bootz_run(&bmi); + /* Try booting an x86_64 Linux kernel image */ + else if (IS_ENABLED(CONFIG_ZBOOT)) + ret = zboot_run(hextoul(kernel_addr, NULL), 0, + initrd_addr_str ? + hextoul(initrd_addr_str, NULL) : 0, + initrd_addr_str ? + hextoul(initrd_filesize, NULL) : 0, + 0, NULL); + + unmap_sysmem(buf); + + return 0; +} + +/** * label_boot() - Boot according to the contents of a pxe_label * * If we can't boot for any reason, we return. A successful boot never @@ -491,8 +706,6 @@ skip_overlay: */ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) { - char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL }; - char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL }; char *kernel_addr = NULL; char *initrd_addr_str = NULL; char initrd_filesize[10]; @@ -500,11 +713,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) char mac_str[29] = ""; char ip_str[68] = ""; char *fit_addr = NULL; - int bootm_argc = 2; - int zboot_argc = 3; - int len = 0; - ulong kernel_addr_r; - void *buf; + int ret; label_print(label); @@ -545,9 +754,10 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) /* For FIT, the label can be identical to kernel one */ if (label->initrd && !strcmp(label->kernel_label, label->initrd)) { - initrd_addr_str = kernel_addr; + initrd_addr_str = kernel_addr; } else if (label->initrd) { ulong size; + if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r", &size) < 0) { printf("Skipping %s for failure retrieving initrd\n", @@ -593,7 +803,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) } if (label->append) - strncpy(bootargs, label->append, sizeof(bootargs)); + strlcpy(bootargs, label->append, sizeof(bootargs)); strcat(bootargs, ip_str); strcat(bootargs, mac_str); @@ -604,180 +814,8 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) printf("append: %s\n", finalbootargs); } - /* - * fdt usage is optional: - * It handles the following scenarios. - * - * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is - * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to - * bootm, and adjust argc appropriately. - * - * If retrieve fails and no exact fdt blob is specified in pxe file with - * "fdt" label, try Scenario 2. - * - * Scenario 2: If there is an fdt_addr specified, pass it along to - * bootm, and adjust argc appropriately. - * - * Scenario 3: If there is an fdtcontroladdr specified, pass it along to - * bootm, and adjust argc appropriately, unless the image type is fitImage. - * - * Scenario 4: fdt blob is not available. - */ - bootm_argv[3] = env_get("fdt_addr_r"); - - /* For FIT, the label can be identical to kernel one */ - if (label->fdt && !strcmp(label->kernel_label, label->fdt)) { - bootm_argv[3] = kernel_addr; - /* if fdt label is defined then get fdt from server */ - } else if (bootm_argv[3]) { - char *fdtfile = NULL; - char *fdtfilefree = NULL; - - if (label->fdt) { - if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { - if (strcmp("-", label->fdt)) - fdtfile = label->fdt; - } else { - fdtfile = label->fdt; - } - } else if (label->fdtdir) { - char *f1, *f2, *f3, *f4, *slash; - - f1 = env_get("fdtfile"); - if (f1) { - f2 = ""; - f3 = ""; - f4 = ""; - } else { - /* - * For complex cases where this code doesn't - * generate the correct filename, the board - * code should set $fdtfile during early boot, - * or the boot scripts should set $fdtfile - * before invoking "pxe" or "sysboot". - */ - f1 = env_get("soc"); - f2 = "-"; - f3 = env_get("board"); - f4 = ".dtb"; - if (!f1) { - f1 = ""; - f2 = ""; - } - if (!f3) { - f2 = ""; - f3 = ""; - } - } - - len = strlen(label->fdtdir); - if (!len) - slash = "./"; - else if (label->fdtdir[len - 1] != '/') - slash = "/"; - else - slash = ""; - - len = strlen(label->fdtdir) + strlen(slash) + - strlen(f1) + strlen(f2) + strlen(f3) + - strlen(f4) + 1; - fdtfilefree = malloc(len); - if (!fdtfilefree) { - printf("malloc fail (FDT filename)\n"); - goto cleanup; - } - - snprintf(fdtfilefree, len, "%s%s%s%s%s%s", - label->fdtdir, slash, f1, f2, f3, f4); - fdtfile = fdtfilefree; - } - - if (fdtfile) { - int err = get_relfile_envaddr(ctx, fdtfile, - "fdt_addr_r", NULL); - - free(fdtfilefree); - if (err < 0) { - bootm_argv[3] = NULL; - - if (label->fdt) { - printf("Skipping %s for failure retrieving FDT\n", - label->name); - goto cleanup; - } - - if (label->fdtdir) { - printf("Skipping fdtdir %s for failure retrieving dts\n", - label->fdtdir); - } - } - - if (label->kaslrseed) - label_boot_kaslrseed(); - -#ifdef CONFIG_OF_LIBFDT_OVERLAY - if (label->fdtoverlays) - label_boot_fdtoverlay(ctx, label); -#endif - } else { - bootm_argv[3] = NULL; - } - } - - bootm_argv[1] = kernel_addr; - zboot_argv[1] = kernel_addr; - - if (initrd_addr_str) { - bootm_argv[2] = initrd_str; - bootm_argc = 3; - - zboot_argv[3] = initrd_addr_str; - zboot_argv[4] = initrd_filesize; - zboot_argc = 5; - } - - if (!bootm_argv[3]) { - if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { - if (strcmp("-", label->fdt)) - bootm_argv[3] = env_get("fdt_addr"); - } else { - bootm_argv[3] = env_get("fdt_addr"); - } - } - - kernel_addr_r = genimg_get_kernel_addr(kernel_addr); - buf = map_sysmem(kernel_addr_r, 0); - - if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT) { - if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) { - if (strcmp("-", label->fdt)) - bootm_argv[3] = env_get("fdtcontroladdr"); - } else { - bootm_argv[3] = env_get("fdtcontroladdr"); - } - } - - if (bootm_argv[3]) { - if (!bootm_argv[2]) - bootm_argv[2] = "-"; - bootm_argc = 4; - } - - /* Try bootm for legacy and FIT format image */ - if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID && - IS_ENABLED(CONFIG_CMD_BOOTM)) - do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv); - /* Try booting an AArch64 Linux kernel image */ - else if (IS_ENABLED(CONFIG_CMD_BOOTI)) - do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv); - /* Try booting a Image */ - else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) - do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv); - /* Try booting an x86_64 Linux kernel image */ - else if (IS_ENABLED(CONFIG_CMD_ZBOOT)) - do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL); - - unmap_sysmem(buf); + ret = label_run_boot(ctx, label, kernel_addr, initrd_str, + initrd_addr_str, initrd_filesize); cleanup: free(fit_addr); diff --git a/cmd/Kconfig b/cmd/Kconfig index 61e280fb1a4..8eeb99eea5e 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -262,6 +262,7 @@ config CMD_BOOTD config CMD_BOOTM bool "bootm" + depends on BOOTM default y help Boot an application image from the memory. @@ -333,48 +334,6 @@ config CMD_BOOTI help Boot an AArch64 Linux Kernel image from memory. -config BOOTM_LINUX - bool "Support booting Linux OS images" - depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI - default y - help - Support booting the Linux kernel directly via a command such as bootm - or booti or bootz. - -config BOOTM_NETBSD - bool "Support booting NetBSD (non-EFI) loader images" - depends on CMD_BOOTM - default y - help - Support booting NetBSD via the bootm command. - -config BOOTM_OPENRTOS - bool "Support booting OPENRTOS / FreeRTOS images" - depends on CMD_BOOTM - help - Support booting OPENRTOS / FreeRTOS via the bootm command. - -config BOOTM_OSE - bool "Support booting Enea OSE images" - depends on (ARM && (ARM64 || CPU_V7A || CPU_V7R) || SANDBOX || PPC || X86) - depends on CMD_BOOTM - help - Support booting Enea OSE images via the bootm command. - -config BOOTM_PLAN9 - bool "Support booting Plan9 OS images" - depends on CMD_BOOTM - default y - help - Support booting Plan9 images via the bootm command. - -config BOOTM_RTEMS - bool "Support booting RTEMS OS images" - depends on CMD_BOOTM - default y - help - Support booting RTEMS images via the bootm command. - config CMD_SEAMA bool "Support read SEAMA NAND images" depends on MTD_RAW_NAND @@ -391,13 +350,6 @@ config CMD_VBE is used to boot. Updating the parameters is not currently supported. -config BOOTM_VXWORKS - bool "Support booting VxWorks OS images" - depends on CMD_BOOTM - default y - help - Support booting VxWorks images via the bootm command. - config CMD_BOOTEFI bool "bootefi" depends on EFI_LOADER @@ -612,6 +564,8 @@ config THOR_RESET_OFF config CMD_ZBOOT bool "zboot - x86 boot command" + depends on ZBOOT + default y help With x86 machines it is common to boot a bzImage file which contains both a kernel and a setup.bin file. The latter includes @@ -1407,6 +1361,13 @@ config CMD_MTD help MTD commands support. +config CMD_MTD_OTP + bool "mtd otp" + depends on CMD_MTD + select HEXDUMP + help + MTD commands for OTP access. + config CMD_MUX bool "mux" depends on MULTIPLEXER @@ -2878,8 +2839,8 @@ config CMD_TRACE Enables a command to control using of function tracing within U-Boot. This allows recording of call traces including timing information. The command can write data to memory for exporting - for analysis (e.g. using bootchart). See doc/README.trace for full - details. + for analysis (e.g. using bootchart). See doc/develop/trace.rst + for full details. config CMD_AVB bool "avb - Android Verified Boot 2.0 operations" diff --git a/cmd/booti.c b/cmd/booti.c index 898df0f8896..b9637b3ec3d 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -74,7 +74,7 @@ static int booti_start(struct bootm_info *bmi) unmap_sysmem((void *)ld); ret = booti_setup(ld, &relocated_addr, &image_size, false); - if (ret || IS_ENABLED(CONFIG_SANDBOX)) + if (ret) return 1; /* Handle BOOTM_STATE_LOADOS */ diff --git a/cmd/fastboot.c b/cmd/fastboot.c index c3c19231c98..792e83d372c 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -159,7 +159,7 @@ NXTARG: return CMD_RET_USAGE; } - fastboot_init((void *)buf_addr, buf_size); + fastboot_init(buf_addr, buf_size); if (!strcmp(argv[1], "udp")) return do_fastboot_udp(argc, argv, buf_addr, buf_size); diff --git a/cmd/mtd.c b/cmd/mtd.c index 9083a6840ac..9189f45cabd 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -11,6 +11,9 @@ #include <command.h> #include <common.h> #include <console.h> +#if CONFIG_IS_ENABLED(CMD_MTD_OTP) +#include <hexdump.h> +#endif #include <malloc.h> #include <mapmem.h> #include <mtd.h> @@ -202,6 +205,221 @@ static bool mtd_oob_write_is_empty(struct mtd_oob_ops *op) return true; } +#if CONFIG_IS_ENABLED(CMD_MTD_OTP) +static int do_mtd_otp_read(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct mtd_info *mtd; + size_t retlen; + off_t from; + size_t len; + bool user; + int ret; + u8 *buf; + + if (argc != 5) + return CMD_RET_USAGE; + + if (!strcmp(argv[2], "u")) + user = true; + else if (!strcmp(argv[2], "f")) + user = false; + else + return CMD_RET_USAGE; + + mtd = get_mtd_by_name(argv[1]); + if (IS_ERR_OR_NULL(mtd)) + return CMD_RET_FAILURE; + + from = simple_strtoul(argv[3], NULL, 0); + len = simple_strtoul(argv[4], NULL, 0); + + ret = CMD_RET_FAILURE; + + buf = malloc(len); + if (!buf) + goto put_mtd; + + printf("Reading %s OTP from 0x%lx, %zu bytes\n", + user ? "user" : "factory", from, len); + + if (user) + ret = mtd_read_user_prot_reg(mtd, from, len, &retlen, buf); + else + ret = mtd_read_fact_prot_reg(mtd, from, len, &retlen, buf); + if (ret) { + free(buf); + pr_err("OTP read failed: %d\n", ret); + ret = CMD_RET_FAILURE; + goto put_mtd; + } + + if (retlen != len) + pr_err("OTP read returns %zu, but %zu expected\n", + retlen, len); + + print_hex_dump("", 0, 16, 1, buf, retlen, true); + + free(buf); + + ret = CMD_RET_SUCCESS; + +put_mtd: + put_mtd_device(mtd); + + return ret; +} + +static int do_mtd_otp_lock(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct mtd_info *mtd; + off_t from; + size_t len; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + mtd = get_mtd_by_name(argv[1]); + if (IS_ERR_OR_NULL(mtd)) + return CMD_RET_FAILURE; + + from = simple_strtoul(argv[2], NULL, 0); + len = simple_strtoul(argv[3], NULL, 0); + + ret = mtd_lock_user_prot_reg(mtd, from, len); + if (ret) { + pr_err("OTP lock failed: %d\n", ret); + ret = CMD_RET_FAILURE; + goto put_mtd; + } + + ret = CMD_RET_SUCCESS; + +put_mtd: + put_mtd_device(mtd); + + return ret; +} + +static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct mtd_info *mtd; + size_t retlen; + size_t binlen; + u8 *binbuf; + off_t from; + int ret; + + if (argc != 4) + return CMD_RET_USAGE; + + mtd = get_mtd_by_name(argv[1]); + if (IS_ERR_OR_NULL(mtd)) + return CMD_RET_FAILURE; + + from = simple_strtoul(argv[2], NULL, 0); + binlen = strlen(argv[3]) / 2; + + ret = CMD_RET_FAILURE; + binbuf = malloc(binlen); + if (!binbuf) + goto put_mtd; + + hex2bin(binbuf, argv[3], binlen); + + printf("Will write:\n"); + + print_hex_dump("", 0, 16, 1, binbuf, binlen, true); + + printf("to 0x%lx\n", from); + + printf("Continue (y/n)?\n"); + + if (confirm_yesno() != 1) { + pr_err("OTP write canceled\n"); + ret = CMD_RET_SUCCESS; + goto put_mtd; + } + + ret = mtd_write_user_prot_reg(mtd, from, binlen, &retlen, binbuf); + if (ret) { + pr_err("OTP write failed: %d\n", ret); + ret = CMD_RET_FAILURE; + goto put_mtd; + } + + if (retlen != binlen) + pr_err("OTP write returns %zu, but %zu expected\n", + retlen, binlen); + + ret = CMD_RET_SUCCESS; + +put_mtd: + free(binbuf); + put_mtd_device(mtd); + + return ret; +} + +static int do_mtd_otp_info(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct otp_info otp_info; + struct mtd_info *mtd; + size_t retlen; + bool user; + int ret; + + if (argc != 3) + return CMD_RET_USAGE; + + if (!strcmp(argv[2], "u")) + user = true; + else if (!strcmp(argv[2], "f")) + user = false; + else + return CMD_RET_USAGE; + + mtd = get_mtd_by_name(argv[1]); + if (IS_ERR_OR_NULL(mtd)) + return CMD_RET_FAILURE; + + if (user) + ret = mtd_get_user_prot_info(mtd, sizeof(otp_info), &retlen, + &otp_info); + else + ret = mtd_get_fact_prot_info(mtd, sizeof(otp_info), &retlen, + &otp_info); + if (ret) { + pr_err("OTP info failed: %d\n", ret); + ret = CMD_RET_FAILURE; + goto put_mtd; + } + + if (retlen != sizeof(otp_info)) { + pr_err("OTP info returns %zu, but %zu expected\n", + retlen, sizeof(otp_info)); + ret = CMD_RET_FAILURE; + goto put_mtd; + } + + printf("%s OTP region info:\n", user ? "User" : "Factory"); + printf("\tstart: %u\n", otp_info.start); + printf("\tlength: %u\n", otp_info.length); + printf("\tlocked: %u\n", otp_info.locked); + + ret = CMD_RET_SUCCESS; + +put_mtd: + put_mtd_device(mtd); + + return ret; +} +#endif + static int do_mtd_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -551,6 +769,12 @@ U_BOOT_LONGHELP(mtd, "\n" "Specific functions:\n" "mtd bad <name>\n" +#if CONFIG_IS_ENABLED(CMD_MTD_OTP) + "mtd otpread <name> [u|f] <off> <size>\n" + "mtd otpwrite <name> <off> <hex string>\n" + "mtd otplock <name> <off> <size>\n" + "mtd otpinfo <name> [u|f]\n" +#endif "\n" "With:\n" "\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n" @@ -561,10 +785,20 @@ U_BOOT_LONGHELP(mtd, "\t<size>: length of the operation in bytes (default: the entire device)\n" "\t\t* must be a multiple of a block for erase\n" "\t\t* must be a multiple of a page otherwise (special case: default is a page with dump)\n" +#if CONFIG_IS_ENABLED(CMD_MTD_OTP) + "\t<hex string>: hex string without '0x' and spaces. Example: ABCD1234\n" + "\t[u|f]: user or factory OTP region\n" +#endif "\n" "The .dontskipff option forces writing empty pages, don't use it if unsure.\n"); U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils", mtd_help_text, +#if CONFIG_IS_ENABLED(CMD_MTD_OTP) + U_BOOT_SUBCMD_MKENT(otpread, 5, 1, do_mtd_otp_read), + U_BOOT_SUBCMD_MKENT(otpwrite, 4, 1, do_mtd_otp_write), + U_BOOT_SUBCMD_MKENT(otplock, 4, 1, do_mtd_otp_lock), + U_BOOT_SUBCMD_MKENT(otpinfo, 3, 1, do_mtd_otp_info), +#endif U_BOOT_SUBCMD_MKENT(list, 1, 1, do_mtd_list), U_BOOT_SUBCMD_MKENT_COMPLETE(read, 5, 0, do_mtd_io, mtd_name_complete), diff --git a/cmd/rng.c b/cmd/rng.c index b073a6c8492..e5ab8681122 100644 --- a/cmd/rng.c +++ b/cmd/rng.c @@ -17,7 +17,7 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) u8 buf[64]; int devnum; struct udevice *dev; - int ret = CMD_RET_SUCCESS; + int ret = CMD_RET_SUCCESS, err; if (argc == 2 && !strcmp(argv[1], "list")) { int idx = 0; @@ -62,8 +62,9 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) n = min(n, sizeof(buf)); - if (dm_rng_read(dev, buf, n)) { - printf("Reading RNG failed\n"); + err = dm_rng_read(dev, buf, n); + if (err) { + puts(err == -EINTR ? "Abort\n" : "Reading RNG failed\n"); ret = CMD_RET_FAILURE; } else { print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, n); @@ -135,8 +135,9 @@ static int do_spi_flash_probe(int argc, char *const argv[]) } flash = NULL; if (use_dt) { - spi_flash_probe_bus_cs(bus, cs, &new); - flash = dev_get_uclass_priv(new); + ret = spi_flash_probe_bus_cs(bus, cs, &new); + if (!ret) + flash = dev_get_uclass_priv(new); } else { flash = spi_flash_probe(bus, cs, speed, mode); } diff --git a/cmd/sysboot.c b/cmd/sysboot.c index 63a7806debe..d14c570d96a 100644 --- a/cmd/sysboot.c +++ b/cmd/sysboot.c @@ -77,6 +77,10 @@ static int do_sysboot(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 6) { filename = env_get("bootfile"); + if (!filename) { + printf("Specify a filename or set the ${bootfile} environment variable\n"); + return 1; + } } else { filename = argv[5]; env_set("bootfile", filename); diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile index 5f82204c87e..b1f39d3bfde 100644 --- a/cmd/x86/Makefile +++ b/cmd/x86/Makefile @@ -5,3 +5,4 @@ obj-y += mtrr.o obj-$(CONFIG_CMD_EXCEPTION) += exception.o obj-$(CONFIG_USE_HOB) += hob.o obj-$(CONFIG_HAVE_FSP) += fsp.o +obj-$(CONFIG_CMD_ZBOOT) += zboot.o diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c new file mode 100644 index 00000000000..addf28cb4aa --- /dev/null +++ b/cmd/x86/zboot.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + */ + +#include <command.h> +#include <mapmem.h> +#include <vsprintf.h> +#include <asm/zimage.h> + +static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong bzimage_addr = 0, bzimage_size, initrd_addr, initrd_size; + ulong base_addr; + const char *s, *cmdline; + + /* argv[1] holds the address of the bzImage */ + s = cmd_arg1(argc, argv) ? : env_get("fileaddr"); + if (s) + bzimage_addr = hextoul(s, NULL); + bzimage_size = argc > 2 ? hextoul(argv[2], NULL) : 0; + initrd_addr = argc > 3 ? hextoul(argv[3], NULL) : 0; + initrd_size = argc > 4 ? hextoul(argv[4], NULL) : 0; + base_addr = argc > 5 ? hextoul(argv[5], NULL) : 0; + cmdline = argc > 6 ? env_get(argv[6]) : NULL; + + zboot_start(bzimage_addr, bzimage_size, initrd_addr, initrd_size, + base_addr, cmdline); + + return 0; +} + +static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret; + + ret = zboot_load(); + if (ret) + return ret; + + return 0; +} + +static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (!state.base_ptr) { + printf("base is not set: use 'zboot load' first\n"); + return CMD_RET_FAILURE; + } + if (zboot_setup()) { + puts("Setting up boot parameters failed ...\n"); + return CMD_RET_FAILURE; + } + + if (zboot_setup()) + return CMD_RET_FAILURE; + + return 0; +} + +static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + zboot_info(); + + return 0; +} + +static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret; + + ret = zboot_go(); + if (ret) { + printf("Kernel returned! (err=%d)\n", ret); + return CMD_RET_FAILURE; + } + + return 0; +} + +static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct boot_params *base_ptr = state.base_ptr; + + if (argc > 1) + base_ptr = (void *)hextoul(argv[1], NULL); + if (!base_ptr) { + printf("No zboot setup_base\n"); + return CMD_RET_FAILURE; + } + zimage_dump(base_ptr, true); + + return 0; +} + +/* Note: This defines the complete_zboot() function */ +U_BOOT_SUBCMDS(zboot, + U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""), + U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""), + U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""), + U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""), + U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""), + U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""), +) + +int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int state_mask) +{ + int ret; + + if (flag & ZBOOT_STATE_START) + ret = do_zboot_start(cmdtp, flag, argc, argv); + if (!ret && (flag & ZBOOT_STATE_LOAD)) + ret = do_zboot_load(cmdtp, flag, argc, argv); + if (!ret && (flag & ZBOOT_STATE_SETUP)) + ret = do_zboot_setup(cmdtp, flag, argc, argv); + if (!ret && (flag & ZBOOT_STATE_INFO)) + ret = do_zboot_info(cmdtp, flag, argc, argv); + if (!ret && (flag & ZBOOT_STATE_GO)) + ret = do_zboot_go(cmdtp, flag, argc, argv); + if (ret) + return ret; + + return 0; +} + +int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int *repeatable) +{ + /* determine if we have a sub command */ + if (argc > 1) { + char *endp; + + hextoul(argv[1], &endp); + /* + * endp pointing to nul means that argv[1] was just a valid + * number, so pass it along to the normal processing + */ + if (*endp) + return do_zboot(cmdtp, flag, argc, argv, repeatable); + } + + do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START | + ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP | + ZBOOT_STATE_INFO | ZBOOT_STATE_GO); + + return CMD_RET_FAILURE; +} + +U_BOOT_CMDREP_COMPLETE( + zboot, 8, do_zboot_parent, "Boot bzImage", + "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n" + " addr - The optional starting address of the bzimage.\n" + " If not set it defaults to the environment\n" + " variable \"fileaddr\".\n" + " size - The optional size of the bzimage. Defaults to\n" + " zero.\n" + " initrd addr - The address of the initrd image to use, if any.\n" + " initrd size - The size of the initrd image to use, if any.\n" + " setup - The address of the kernel setup region, if this\n" + " is not at addr\n" + " cmdline - Environment variable containing the kernel\n" + " command line, to override U-Boot's normal\n" + " cmdline generation\n" + "\n" + "Sub-commands to do part of the zboot sequence:\n" + "\tstart [addr [arg ...]] - specify arguments\n" + "\tload - load OS image\n" + "\tsetup - set up table\n" + "\tinfo - show summary info\n" + "\tgo - start OS\n" + "\tdump [addr] - dump info (optional address of boot params)", + complete_zboot +); diff --git a/common/board_f.c b/common/board_f.c index 8bada6ff2ee..039d6d712d0 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -718,6 +718,7 @@ static int reloc_bloblist(void) return 0; } +void mcheck_on_ramrelocation(size_t offset); static int setup_reloc(void) { if (!(gd->flags & GD_FLG_SKIP_RELOC)) { @@ -743,6 +744,9 @@ static int setup_reloc(void) if (gd->flags & GD_FLG_SKIP_RELOC) { debug("Skipping relocation due to flag\n"); } else { +#ifdef MCHECK_HEAP_PROTECTION + mcheck_on_ramrelocation(gd->reloc_off); +#endif debug("Relocation Offset is: %08lx\n", gd->reloc_off); debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), diff --git a/common/cli.c b/common/cli.c index a34938294ec..1c33daf1149 100644 --- a/common/cli.c +++ b/common/cli.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "cli: %s: " fmt, __func__ #include <common.h> +#include <ansi.h> #include <bootstage.h> #include <cli.h> #include <cli_hush.h> @@ -336,4 +337,7 @@ void cli_init(void) #if defined(CONFIG_HUSH_INIT_VAR) hush_init_var(); #endif + + if (CONFIG_IS_ENABLED(VIDEO_ANSI)) + printf(ANSI_CURSOR_SHOW "\n"); } diff --git a/common/dlmalloc.c b/common/dlmalloc.c index de3f04225f4..a0616217d49 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -32,6 +32,21 @@ void malloc_stats(); DECLARE_GLOBAL_DATA_PTR; +#ifdef MCHECK_HEAP_PROTECTION + #define STATIC_IF_MCHECK static + #undef MALLOC_COPY + #undef MALLOC_ZERO +static inline void MALLOC_ZERO(void *p, size_t sz) { memset(p, 0, sz); } +static inline void MALLOC_COPY(void *dest, const void *src, size_t sz) { memcpy(dest, src, sz); } +#else + #define STATIC_IF_MCHECK + #define mALLOc_impl mALLOc + #define fREe_impl fREe + #define rEALLOc_impl rEALLOc + #define mEMALIGn_impl mEMALIGn + #define cALLOc_impl cALLOc +#endif + /* Emulation of sbrk for WIN32 All code within the ifdef WIN32 is untested by me. @@ -1270,10 +1285,11 @@ static void malloc_extend_top(nb) INTERNAL_SIZE_T nb; */ +STATIC_IF_MCHECK #if __STD_C -Void_t* mALLOc(size_t bytes) +Void_t* mALLOc_impl(size_t bytes) #else -Void_t* mALLOc(bytes) size_t bytes; +Void_t* mALLOc_impl(bytes) size_t bytes; #endif { mchunkptr victim; /* inspected/selected chunk */ @@ -1555,10 +1571,11 @@ Void_t* mALLOc(bytes) size_t bytes; */ +STATIC_IF_MCHECK #if __STD_C -void fREe(Void_t* mem) +void fREe_impl(Void_t* mem) #else -void fREe(mem) Void_t* mem; +void fREe_impl(mem) Void_t* mem; #endif { mchunkptr p; /* chunk corresponding to mem */ @@ -1696,10 +1713,11 @@ void fREe(mem) Void_t* mem; */ +STATIC_IF_MCHECK #if __STD_C -Void_t* rEALLOc(Void_t* oldmem, size_t bytes) +Void_t* rEALLOc_impl(Void_t* oldmem, size_t bytes) #else -Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; +Void_t* rEALLOc_impl(oldmem, bytes) Void_t* oldmem; size_t bytes; #endif { INTERNAL_SIZE_T nb; /* padded request size */ @@ -1725,7 +1743,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; #ifdef REALLOC_ZERO_BYTES_FREES if (!bytes) { - fREe(oldmem); + fREe_impl(oldmem); return NULL; } #endif @@ -1733,7 +1751,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; if ((long)bytes < 0) return NULL; /* realloc of null is supposed to be same as malloc */ - if (oldmem == NULL) return mALLOc(bytes); + if (oldmem == NULL) return mALLOc_impl(bytes); #if CONFIG_IS_ENABLED(SYS_MALLOC_F) if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { @@ -1758,7 +1776,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; /* Note the extra SIZE_SZ overhead. */ if(oldsize - SIZE_SZ >= nb) return oldmem; /* do nothing */ /* Must alloc, copy, free. */ - newmem = mALLOc(bytes); + newmem = mALLOc_impl(bytes); if (!newmem) return NULL; /* propagate failure */ MALLOC_COPY(newmem, oldmem, oldsize - 2*SIZE_SZ); @@ -1869,7 +1887,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; /* Must allocate */ - newmem = mALLOc (bytes); + newmem = mALLOc_impl (bytes); if (newmem == NULL) /* propagate failure */ return NULL; @@ -1886,7 +1904,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; /* Otherwise copy, free, and exit */ MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); - fREe(oldmem); + fREe_impl(oldmem); return newmem; } else { VALGRIND_RESIZEINPLACE_BLOCK(oldmem, 0, bytes, SIZE_SZ); @@ -1905,7 +1923,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; set_inuse_bit_at_offset(remainder, remainder_size); VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(remainder), remainder_size, SIZE_SZ, false); - fREe(chunk2mem(remainder)); /* let free() deal with it */ + fREe_impl(chunk2mem(remainder)); /* let free() deal with it */ } else { @@ -1939,10 +1957,11 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; */ +STATIC_IF_MCHECK #if __STD_C -Void_t* mEMALIGn(size_t alignment, size_t bytes) +Void_t* mEMALIGn_impl(size_t alignment, size_t bytes) #else -Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; +Void_t* mEMALIGn_impl(alignment, bytes) size_t alignment; size_t bytes; #endif { INTERNAL_SIZE_T nb; /* padded request size */ @@ -1965,7 +1984,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; /* If need less alignment than we give anyway, just relay to malloc */ - if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes); + if (alignment <= MALLOC_ALIGNMENT) return mALLOc_impl(bytes); /* Otherwise, ensure that it is at least a minimum chunk size */ @@ -1974,7 +1993,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; /* Call malloc with worst case padding to hit alignment. */ nb = request2size(bytes); - m = (char*)(mALLOc(nb + alignment + MINSIZE)); + m = (char*)(mALLOc_impl(nb + alignment + MINSIZE)); /* * The attempt to over-allocate (with a size large enough to guarantee the @@ -1990,7 +2009,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; * Use bytes not nb, since mALLOc internally calls request2size too, and * each call increases the size to allocate, to account for the header. */ - m = (char*)(mALLOc(bytes)); + m = (char*)(mALLOc_impl(bytes)); /* Aligned -> return it */ if ((((unsigned long)(m)) % alignment) == 0) return m; @@ -1998,10 +2017,10 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; * Otherwise, try again, requesting enough extra space to be able to * acquire alignment. */ - fREe(m); + fREe_impl(m); /* Add in extra bytes to match misalignment of unexpanded allocation */ extra = alignment - (((unsigned long)(m)) % alignment); - m = (char*)(mALLOc(bytes + extra)); + m = (char*)(mALLOc_impl(bytes + extra)); /* * m might not be the same as before. Validate that the previous value of * extra still works for the current value of m. @@ -2010,7 +2029,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; if (m) { extra2 = alignment - (((unsigned long)(m)) % alignment); if (extra2 > extra) { - fREe(m); + fREe_impl(m); m = NULL; } } @@ -2060,7 +2079,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; set_head(newp, newsize | PREV_INUSE); set_inuse_bit_at_offset(newp, newsize); set_head_size(p, leadsize); - fREe(chunk2mem(p)); + fREe_impl(chunk2mem(p)); p = newp; VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(p), bytes, SIZE_SZ, false); @@ -2078,7 +2097,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; set_head_size(p, nb); VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(remainder), remainder_size, SIZE_SZ, false); - fREe(chunk2mem(remainder)); + fREe_impl(chunk2mem(remainder)); } check_inuse_chunk(p); @@ -2126,10 +2145,11 @@ Void_t* pvALLOc(bytes) size_t bytes; */ +STATIC_IF_MCHECK #if __STD_C -Void_t* cALLOc(size_t n, size_t elem_size) +Void_t* cALLOc_impl(size_t n, size_t elem_size) #else -Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; +Void_t* cALLOc_impl(n, elem_size) size_t n; size_t elem_size; #endif { mchunkptr p; @@ -2145,7 +2165,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; INTERNAL_SIZE_T oldtopsize = chunksize(top); #endif #endif - Void_t* mem = mALLOc (sz); + Void_t* mem = mALLOc_impl (sz); if ((long)n < 0) return NULL; @@ -2205,6 +2225,90 @@ void cfree(mem) Void_t *mem; #endif +#ifdef MCHECK_HEAP_PROTECTION + #include "mcheck_core.inc.h" + #if !__STD_C + #error "must have __STD_C" + #endif + +Void_t *mALLOc(size_t bytes) +{ + mcheck_pedantic_prehook(); + size_t fullsz = mcheck_alloc_prehook(bytes); + void *p = mALLOc_impl(fullsz); + + if (!p) + return p; + return mcheck_alloc_posthook(p, bytes); +} + +void fREe(Void_t *mem) { fREe_impl(mcheck_free_prehook(mem)); } + +Void_t *rEALLOc(Void_t *oldmem, size_t bytes) +{ + mcheck_pedantic_prehook(); + if (bytes == 0) { + if (oldmem) + fREe(oldmem); + return NULL; + } + + if (oldmem == NULL) + return mALLOc(bytes); + + void *p = mcheck_reallocfree_prehook(oldmem); + size_t newsz = mcheck_alloc_prehook(bytes); + + p = rEALLOc_impl(p, newsz); + if (!p) + return p; + return mcheck_alloc_noclean_posthook(p, bytes); +} + +Void_t *mEMALIGn(size_t alignment, size_t bytes) +{ + mcheck_pedantic_prehook(); + size_t fullsz = mcheck_memalign_prehook(alignment, bytes); + void *p = mEMALIGn_impl(alignment, fullsz); + + if (!p) + return p; + return mcheck_memalign_posthook(alignment, p, bytes); +} + +// pvALLOc, vALLOc - redirect to mEMALIGn, defined here, so they need no wrapping. + +Void_t *cALLOc(size_t n, size_t elem_size) +{ + mcheck_pedantic_prehook(); + // NB: here is no overflow check. + size_t fullsz = mcheck_alloc_prehook(n * elem_size); + void *p = cALLOc_impl(1, fullsz); + + if (!p) + return p; + return mcheck_alloc_noclean_posthook(p, n * elem_size); +} + +// mcheck API { +int mcheck_pedantic(mcheck_abortfunc_t f) +{ + mcheck_initialize(f, 1); + return 0; +} + +int mcheck(mcheck_abortfunc_t f) +{ + mcheck_initialize(f, 0); + return 0; +} + +void mcheck_check_all(void) { mcheck_pedantic_check(); } + +enum mcheck_status mprobe(void *__ptr) { return mcheck_mprobe(__ptr); } +// mcheck API } +#endif + /* diff --git a/common/mcheck_core.inc.h b/common/mcheck_core.inc.h new file mode 100644 index 00000000000..69021409922 --- /dev/null +++ b/common/mcheck_core.inc.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Free Software Foundation, Inc. + * Written by Eugene Uriev, based on glibc 2.0 prototype of Mike Haertel. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Library General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Library General Public License for more details. + * <https://www.gnu.org/licenses/> + */ + +/* + * TL;DR: this is a porting of glibc mcheck into U-Boot + * + * This file contains no entities for external linkage. + * So mcheck protection may be used in parallel, e.g. for "malloc_simple(..)" and "malloc(..)". + * To do so, the file should be shared/include twice, - without linkage conflicts. + * I.e. "core"-part is shared as a source, but not as a binary. + * Maybe some optimization here make sense, to engage more binary sharing too. + * But, currently I strive to keep it as simple, as possible. + * And this, programmers'-only, mode don't pretend to be main. + * + * This library is aware of U-Boot specific. It's also aware of ARM alignment concerns. + * Unlike glibc-clients, U-Boot has limited malloc-usage, and only one thread. + * So it's better to make the protection heavier. + * Thus overflow canary here is greater, than glibc's one. Underflow canary is bigger too. + * U-Boot also allows to use fixed-size heap-registry, instead of double-linked list in glibc. + * + * Heavy canary allows to catch not only memset(..)-errors, + * but overflow/underflow of struct-array access: + * { + * struct mystruct* p = malloc(sizeof(struct mystruct) * N); + * p[-1].field1 = 0; + * p[N].field2 = 13; + * } + * TODO: In order to guarantee full coverage of that kind of errors, a user can add variable-size + * canaries here. So pre- and post-canary with size >= reqested_size, could be provided + * (with the price of 3x heap-usage). Therefore, it would catch 100% of changes beyond + * an array, for index(+1/-1) errors. + * + * U-Boot is a BL, not an OS with a lib. Activity of the library is set not in runtime, + * rather in compile-time, by MCHECK_HEAP_PROTECTION macro. That guarantees that + * we haven't missed first malloc. + */ + +/* + * Testing + * This library had been successfully tested for U-Boot @ ARM SoC chip / 64bits. + * Proven for both default and pedantic mode: confirms U-Boot to be clean, and catches + * intentional/testing corruptions. Working with malloc_trim is not tested. + */ +#ifndef _MCHECKCORE_INC_H +#define _MCHECKCORE_INC_H 1 +#include "mcheck.h" + +#if defined(MCHECK_HEAP_PROTECTION) +#define mcheck_flood memset + +// these are from /dev/random: +#define MAGICWORD 0x99ccf430fa562a05ULL +#define MAGICFREE 0x4875e63c0c6fc08eULL +#define MAGICTAIL 0x918dbcd7df78dcd6ULL +#define MALLOCFLOOD ((char)0xb6) +#define FREEFLOOD ((char)0xf5) +#define PADDINGFLOOD ((char)0x58) + +// my normal run demands 4427-6449 chunks: +#define REGISTRY_SZ 6608 +#define CANARY_DEPTH 2 + +// avoid problems with BSS at early stage: +static char mcheck_pedantic_flag __section(".data") = 0; +static void *mcheck_registry[REGISTRY_SZ] __section(".data") = {0}; +static size_t mcheck_chunk_count __section(".data") = 0; +static size_t mcheck_chunk_count_max __section(".data") = 0; + +typedef unsigned long long mcheck_elem; +typedef struct { + mcheck_elem elems[CANARY_DEPTH]; +} mcheck_canary; +struct mcheck_hdr { + size_t size; /* Exact size requested by user. */ + size_t aln_skip; /* Ignored bytes, before the mcheck_hdr, to fulfill alignment */ + mcheck_canary canary; /* Magic number to check header integrity. */ +}; + +static void mcheck_default_abort(enum mcheck_status status, const void *p) +{ + const char *msg; + + switch (status) { + case MCHECK_OK: + msg = "memory is consistent, library is buggy\n"; + break; + case MCHECK_HEAD: + msg = "memory clobbered before allocated block\n"; + break; + case MCHECK_TAIL: + msg = "memory clobbered past end of allocated block\n"; + break; + case MCHECK_FREE: + msg = "block freed twice\n"; + break; + default: + msg = "bogus mcheck_status, library is buggy\n"; + break; + } + printf("\n\nmcheck: %p:%s!!! [%zu]\n\n", p, msg, mcheck_chunk_count_max); +} + +static mcheck_abortfunc_t mcheck_abortfunc = &mcheck_default_abort; + +static inline size_t allign_size_up(size_t sz, size_t grain) +{ + return (sz + grain - 1) & ~(grain - 1); +} + +#define mcheck_allign_customer_size(SZ) allign_size_up(SZ, sizeof(mcheck_elem)) +#define mcheck_evaluate_memalign_prefix_size(ALIGN) allign_size_up(sizeof(struct mcheck_hdr), ALIGN) + +static enum mcheck_status mcheck_OnNok(enum mcheck_status status, const void *p) +{ + (*mcheck_abortfunc)(status, p); + return status; +} + +static enum mcheck_status mcheck_checkhdr(const struct mcheck_hdr *hdr) +{ + int i; + + for (i = 0; i < CANARY_DEPTH; ++i) + if (hdr->canary.elems[i] == MAGICFREE) + return mcheck_OnNok(MCHECK_FREE, hdr + 1); + + for (i = 0; i < CANARY_DEPTH; ++i) + if (hdr->canary.elems[i] != MAGICWORD) + return mcheck_OnNok(MCHECK_HEAD, hdr + 1); + + const size_t payload_size = hdr->size; + const size_t payload_size_aligned = mcheck_allign_customer_size(payload_size); + const size_t padd_size = payload_size_aligned - hdr->size; + + const char *payload = (const char *)&hdr[1]; + + for (i = 0; i < padd_size; ++i) + if (payload[payload_size + i] != PADDINGFLOOD) + return mcheck_OnNok(MCHECK_TAIL, hdr + 1); + + const mcheck_canary *tail = (const mcheck_canary *)&payload[payload_size_aligned]; + + for (i = 0; i < CANARY_DEPTH; ++i) + if (tail->elems[i] != MAGICTAIL) + return mcheck_OnNok(MCHECK_TAIL, hdr + 1); + return MCHECK_OK; +} + +enum { KEEP_CONTENT = 0, CLEAN_CONTENT, ANY_ALIGNMENT = 1 }; +static void *mcheck_free_helper(void *ptr, int clean_content) +{ + if (!ptr) + return ptr; + + struct mcheck_hdr *hdr = &((struct mcheck_hdr *)ptr)[-1]; + int i; + + mcheck_checkhdr(hdr); + for (i = 0; i < CANARY_DEPTH; ++i) + hdr->canary.elems[i] = MAGICFREE; + + if (clean_content) + mcheck_flood(ptr, FREEFLOOD, mcheck_allign_customer_size(hdr->size)); + + for (i = 0; i < REGISTRY_SZ; ++i) + if (mcheck_registry[i] == hdr) { + mcheck_registry[i] = 0; + break; + } + + --mcheck_chunk_count; + return (char *)hdr - hdr->aln_skip; +} + +static void *mcheck_free_prehook(void *ptr) { return mcheck_free_helper(ptr, CLEAN_CONTENT); } +static void *mcheck_reallocfree_prehook(void *ptr) { return mcheck_free_helper(ptr, KEEP_CONTENT); } + +static size_t mcheck_alloc_prehook(size_t sz) +{ + sz = mcheck_allign_customer_size(sz); + return sizeof(struct mcheck_hdr) + sz + sizeof(mcheck_canary); +} + +static void *mcheck_allocated_helper(void *altoghether_ptr, size_t customer_sz, + size_t alignment, int clean_content) +{ + const size_t slop = alignment ? + mcheck_evaluate_memalign_prefix_size(alignment) - sizeof(struct mcheck_hdr) : 0; + struct mcheck_hdr *hdr = (struct mcheck_hdr *)((char *)altoghether_ptr + slop); + int i; + + hdr->size = customer_sz; + hdr->aln_skip = slop; + for (i = 0; i < CANARY_DEPTH; ++i) + hdr->canary.elems[i] = MAGICWORD; + + char *payload = (char *)&hdr[1]; + + if (clean_content) + mcheck_flood(payload, MALLOCFLOOD, customer_sz); + + const size_t customer_size_aligned = mcheck_allign_customer_size(customer_sz); + + mcheck_flood(payload + customer_sz, PADDINGFLOOD, customer_size_aligned - customer_sz); + + mcheck_canary *tail = (mcheck_canary *)&payload[customer_size_aligned]; + + for (i = 0; i < CANARY_DEPTH; ++i) + tail->elems[i] = MAGICTAIL; + + ++mcheck_chunk_count; + if (mcheck_chunk_count > mcheck_chunk_count_max) + mcheck_chunk_count_max = mcheck_chunk_count; + + for (i = 0; i < REGISTRY_SZ; ++i) + if (!mcheck_registry[i]) { + mcheck_registry[i] = hdr; + return payload; // normal end + } + + static char *overflow_msg = "\n\n\nERROR: mcheck registry overflow, pedantic check would be incomplete!!\n\n\n\n"; + + printf("%s", overflow_msg); + overflow_msg = "(mcheck registry full)"; + return payload; +} + +static void *mcheck_alloc_posthook(void *altoghether_ptr, size_t customer_sz) +{ + return mcheck_allocated_helper(altoghether_ptr, customer_sz, ANY_ALIGNMENT, CLEAN_CONTENT); +} + +static void *mcheck_alloc_noclean_posthook(void *altoghether_ptr, size_t customer_sz) +{ + return mcheck_allocated_helper(altoghether_ptr, customer_sz, ANY_ALIGNMENT, KEEP_CONTENT); +} + +static size_t mcheck_memalign_prehook(size_t alig, size_t sz) +{ + return mcheck_evaluate_memalign_prefix_size(alig) + sz + sizeof(mcheck_canary); +} + +static void *mcheck_memalign_posthook(size_t alignment, void *altoghether_ptr, size_t customer_sz) +{ + return mcheck_allocated_helper(altoghether_ptr, customer_sz, alignment, CLEAN_CONTENT); +} + +static enum mcheck_status mcheck_mprobe(void *ptr) +{ + struct mcheck_hdr *hdr = &((struct mcheck_hdr *)ptr)[-1]; + + return mcheck_checkhdr(hdr); +} + +static void mcheck_pedantic_check(void) +{ + int i; + + for (i = 0; i < REGISTRY_SZ; ++i) + if (mcheck_registry[i]) + mcheck_checkhdr(mcheck_registry[i]); +} + +static void mcheck_pedantic_prehook(void) +{ + if (mcheck_pedantic_flag) + mcheck_pedantic_check(); +} + +static void mcheck_initialize(mcheck_abortfunc_t new_func, char pedantic_flag) +{ + mcheck_abortfunc = (new_func) ? new_func : &mcheck_default_abort; + mcheck_pedantic_flag = pedantic_flag; +} + +void mcheck_on_ramrelocation(size_t offset) +{ + char *p; + int i; + // Simple, but inaccurate strategy: drop the pre-reloc heap + for (i = 0; i < REGISTRY_SZ; ++i) + if ((p = mcheck_registry[i]) != NULL ) { + printf("mcheck, WRN: forgetting %p chunk\n", p); + mcheck_registry[i] = 0; + } + + mcheck_chunk_count = 0; +} +#endif +#endif diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index cc17a8b1140..977daf9f090 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFKW/kwbimage.cfg" CONFIG_TEXT_BASE=0x00600000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 +# CONFIG_OF_UPSTREAM is not set CONFIG_TARGET_SBx81LIFKW=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 0612723298e..9bc86140302 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg" CONFIG_TEXT_BASE=0x00600000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 +# CONFIG_OF_UPSTREAM is not set CONFIG_TARGET_SBx81LIFXCAT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xC0000 diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 2621abb8ce1..6dbdd427ecb 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -73,6 +73,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index 4c1e4d7cc42..06c7d31a6f3 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_SYS_BOOTM_LEN=0x800000 -CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_BOOTCOMMAND="run findfdt; run envboot; bootflow scan -lb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -50,6 +50,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index b7057be3d65..179c42a5444 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="ti/k3-am642-evm ti/k3-am642-sk" diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 500335f7e6e..3afa80f45a8 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -73,6 +73,7 @@ CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs)" CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig index 116147fc9af..cb78dabc13a 100644 --- a/configs/bananapi-cm4-cm4io_defconfig +++ b/configs/bananapi-cm4-cm4io_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-bananapi-cm4-cm4io" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 755bccb4a72..196bc4077d6 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m2-pro" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index af8daced622..7b137d5e1c4 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-bananapi-m2s" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index 6de5d5fe7bb..99ed7c9669a 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m5" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index 99e36e970a1..c1e60ede4a0 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gsking-x" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index 00fdad8544b..0e30e13c823 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-gt1-ultimate" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index 5c21d8eeabe..0b644f0e349 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gtking" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index 37bb4cde792..a694617a968 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking-pro" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gtking-pro" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index a5e6bcb64c0..0249dc3128b 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_MEMTEST_END=0x87c00000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=520192 +# CONFIG_BOOTM is not set CONFIG_BOOTDELAY=1 CONFIG_FDT_FIXUP_PARTITIONS=y CONFIG_USE_BOOTCOMMAND=y @@ -33,7 +34,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Colibri VFxx # " # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index dab5eafe160..da42ad0a20a 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi" CONFIG_SYS_PBSIZE=532 CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -59,6 +60,7 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_VIDEO_COPY=y +CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_SPL_ACPI=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index c846dfc2b91..0b103efe16d 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_LOG=y @@ -53,6 +54,7 @@ CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_VIDEO_COPY=y +CONFIG_CONSOLE_TRUETYPE=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_CMD_DHRYSTONE=y # CONFIG_GZIP is not set diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index bb1bcb0aa30..69658a2ba7f 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NET2BIG_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-d2net" CONFIG_IDENT_STRING=" D2 v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index edfe92c5f38..b85f7cac8ef 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_DNS325=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dns325" CONFIG_IDENT_STRING="\nD-Link DNS-325" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 719fa3979e8..7b5f19433a9 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_DOCKSTAR=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dockstar" CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 02a2635af86..8518eabcb2b 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -13,7 +13,7 @@ CONFIG_TARGET_DREAMPLUG=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dreamplug" CONFIG_IDENT_STRING="\nMarvell-DreamPlug" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x100000 diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 304c098c996..ef805eca562 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -14,7 +14,7 @@ CONFIG_TARGET_DS109=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3D0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ds109" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x3D0000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index d577d5807bd..53b2ce97e88 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_GOFLEXHOME=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-goflexnet" CONFIG_IDENT_STRING="\nSeagate GoFlex Home" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 7cb649e29c5..5371ee403b3 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_GURUPLUG=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-guruplug-server-plus" CONFIG_IDENT_STRING="\nMarvell-GuruPlug" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 074384e3872..32b0e1c3958 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_IB62X0=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ib62x0" CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index f7b74c4662e..45ffbd92dba 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_ICONNECT=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-iconnect" CONFIG_IDENT_STRING=" Iomega iConnect" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PCI=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index b926798ae09..0b601bb8624 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -10,7 +10,7 @@ CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_BEACON=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 341ea47d983..eaf8dce3b5f 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit" CONFIG_SPL_TEXT_BASE=0x7E2000 CONFIG_TARGET_IMX8MM_BEACON=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 2d4cd1fd972..e8009c410ab 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -11,7 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_IMX8MN_BEACON_2GB_LPDDR=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index ec933019aa9..ed671cf4a77 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -11,7 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 458afba441e..11c257a756e 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -11,7 +11,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit" CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_BEACON=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 9d09dd4a7ce..fe1678d8ae9 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -12,9 +12,10 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-beacon-kit" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_BEACON=y +CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -27,6 +28,7 @@ CONFIG_ARMV8_SET_SMPEN=y CONFIG_ARMV8_EA_EL3_FIRST=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_PCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -65,6 +67,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -118,8 +121,11 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_IMX=y CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 2e8e3f3928c..3fa7790d77b 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -11,7 +11,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-is2" CONFIG_IDENT_STRING=" IS v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig index c4920052f82..d02a28abfab 100644 --- a/configs/iot_devkit_defconfig +++ b/configs/iot_devkit_defconfig @@ -14,12 +14,12 @@ CONFIG_DEFAULT_DEVICE_TREE="iot_devkit" CONFIG_SYS_CLK_FREQ=16000000 CONFIG_SYS_LOAD_ADDR=0x30000000 CONFIG_LOCALVERSION="-iotdk-1.0" +# CONFIG_BOOTM is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 CONFIG_SYS_PROMPT="IoTDK# " # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_LOADB is not set diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index 863245430a9..9de6b4b44d9 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-jethome-jethub-j100" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_AXG=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index ca0808f7121..85306872f9a 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -8,7 +8,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 59ef33723e4..50f8b306505 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-khadas-vim2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index ee62fe36d41..37b8d6a9256 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index cecbe506179..55d59dd4813 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index 5df4b92143b..32579b8ac36 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index ec4e0dc72e2..95e70275cc4 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 206f8defca6..6372d119894 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index de8fdd83cce..b9f4690045a 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 5ed7c1a4083..ac00e8975e1 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-khadas-vim" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index f0ab19580c6..6ad04570022 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s805x-libretech-ac" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index bb1a37a0cda..beb919ca6e8 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-libretech-cc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index 8949e240c93..784a269fd5b 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-libretech-cc-v2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index a5dc3115fcb..0adc0afdf30 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905d-libretech-pc" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905d-libretech-pc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index 68f462eeff0..cbce0cf4000 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-s912-libretech-pc" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-s912-libretech-pc" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 99bdbc14836..ad060079a77 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -15,7 +15,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-lschlv2" CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_HAS_BOARD_SIZE_LIMIT=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index bb0a5ddf506..b2d9f0c9d8a 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -16,7 +16,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-lsxhl" CONFIG_IDENT_STRING=" LS-XHL" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_HAS_BOARD_SIZE_LIMIT=y diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 548adf174c6..e8413d7aa94 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -17,6 +17,16 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 27ceb22599a..e3aba715aa5 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -28,6 +28,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_SYS_PBSIZE=532 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_FS_EXT4=y diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 7f11e6f5d45..6c5481cd6ed 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 +# CONFIG_BOOTM is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_PBSIZE=528 CONFIG_SPL_SYS_MALLOC=y @@ -21,7 +22,6 @@ CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index f01b26f2dfd..4ea342a0434 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_NAS220=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xA0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-blackarmor-nas220" CONFIG_IDENT_STRING="\nNAS 220" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index dda627aac66..39cbc3384ff 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -12,7 +12,7 @@ CONFIG_NET2BIG_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-net2big" CONFIG_IDENT_STRING=" 2Big v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 742e6205d89..cd416cb1501 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -12,7 +12,7 @@ CONFIG_NETSPACE_LITE_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2lite" CONFIG_IDENT_STRING=" NS v2 Lite" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 7779e6815e2..6a3d9296ac5 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -12,7 +12,7 @@ CONFIG_NETSPACE_MAX_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2max" CONFIG_IDENT_STRING=" NS Max v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 9e3614bb446..e25631b09f4 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -12,7 +12,7 @@ CONFIG_NETSPACE_MINI_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2mini" CONFIG_IDENT_STRING=" NS v2 Mini" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 1583a0adb3a..b6ac2a8b198 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -12,7 +12,7 @@ CONFIG_NETSPACE_V2=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x70000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2" CONFIG_IDENT_STRING=" NS v2" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0x70000 diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 89d8b18b168..e859a43ffa3 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_NSA310S=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-nsa310s" CONFIG_DEBUG_UART_BASE=0xf1012000 CONFIG_DEBUG_UART_CLOCK=166666667 CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig index 5da4a002b40..88a890002ea 100644 --- a/configs/nsa325_defconfig +++ b/configs/nsa325_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_NSA325=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa325" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-nsa325" CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PCI=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index fe1f8612580..4ef1e681666 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-c4" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-odroid-c4" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index 49d628b76ab..06437fe3ae0 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-go-ultra" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-go-ultra" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index 7720ab5eb81..60233fb9cee 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-odroid-hc4" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index 9694f04a66e..a4cc766f84a 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-n2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig index 673e0cffb24..3f657d18812 100644 --- a/configs/odroid-n2l_defconfig +++ b/configs/odroid-n2l_defconfig @@ -7,7 +7,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2l" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-n2l" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 29a14e0927c..057dd28dffd 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -11,7 +11,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-base" CONFIG_IDENT_STRING="\nOpenRD-Base" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index a95a435bdf9..05e4292764f 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -12,7 +12,7 @@ CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_CLIENT=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-client" CONFIG_IDENT_STRING="\nOpenRD-Client" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index e3f5294ff13..6e13c6eabdd 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -12,7 +12,7 @@ CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_ULTIMATE=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-ultimate" CONFIG_IDENT_STRING="\nOpenRD-Ultimate" CONFIG_SYS_LOAD_ADDR=0x800000 # CONFIG_SYS_MALLOC_F is not set diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 6b73607d641..9cf22ca4db7 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-p212" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXL=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 552b7e91396..08a2532d398 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb" CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c80000 diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index e53ccf34c7d..880cb20b220 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_POGO_E02=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-pogo_e02" CONFIG_IDENT_STRING="\nPogo E02" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_BOOTDELAY=3 diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 95e22b3fef6..50046e83b77 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -12,7 +12,7 @@ CONFIG_TEXT_BASE=0x600000 CONFIG_TARGET_POGO_V4=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xC0000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-pogoplug-series-4" CONFIG_IDENT_STRING="\nPogoplug V4" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PCI=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 222db6448ab..1abb57345ff 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -18,33 +18,58 @@ CONFIG_LOG_DEFAULT_LEVEL=4 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +# CONFIG_CMD_BIND is not set CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_CAT=y CONFIG_CMD_BMP=y CONFIG_CMD_LOG=y -# CONFIG_NET is not set +CONFIG_OF_LIVE=y CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_SDM845=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_QUP=y +CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y +CONFIG_IOMMU=y +CONFIG_QCOM_HYP_SMMU=y +CONFIG_MISC=y +CONFIG_NVMEM=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_QCOM=y +CONFIG_RGMII=y CONFIG_PHY=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PINCTRL=y CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SCSI=y CONFIG_MSM_SERIAL=y CONFIG_MSM_GENI_SERIAL=y @@ -55,6 +80,10 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_UFS=y CONFIG_VIDEO=y # CONFIG_VIDEO_FONT_8X16 is not set diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 451af0bda68..008eb46a01c 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x40000 CONFIG_MAX_CPUS=2 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" -CONFIG_SPL_TEXT_BASE=0xfffd8000 +CONFIG_SPL_TEXT_BASE=0xfffd4000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEBUG_UART_BASE=0x3f8 CONFIG_DEBUG_UART_CLOCK=1843200 @@ -17,7 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y -CONFIG_X86_OFFSET_U_BOOT=0xfff00000 +CONFIG_X86_OFFSET_U_BOOT=0xffe00000 CONFIG_SYS_MONITOR_BASE=0x01110000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -80,6 +80,7 @@ CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y +CONFIG_CONSOLE_TRUETYPE=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index b2a221b12a3..947d15cd727 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -57,6 +57,7 @@ CONFIG_NVME_PCI=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y +CONFIG_CONSOLE_TRUETYPE=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_USER=y CONFIG_FRAMEBUFFER_VESA_MODE=0x144 diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index b795681b3f0..92e0a8833cc 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-radxa-zero2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig index 103ff8a321d..5179c58dadc 100644 --- a/configs/radxa-zero_defconfig +++ b/configs/radxa-zero_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-radxa-zero" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index 8e22c95f882..d75d296fa0e 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-s400" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_AXG=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index a62faf77248..2bd4eeaade9 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -135,7 +135,6 @@ CONFIG_CPU=y CONFIG_DM_DEMO=y CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y -CONFIG_DFU_SF=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_ARM_FFA_TRANSPORT=y @@ -268,12 +267,8 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y CONFIG_ERRNO_STR=y CONFIG_GETOPT=y -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y -CONFIG_FWU_MULTI_BANK_UPDATE=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index 137b3c6b82c..f37230151a0 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -281,8 +281,6 @@ CONFIG_TPM=y CONFIG_ZSTD=y CONFIG_SPL_LZMA=y CONFIG_ERRNO_STR=y -CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_UNIT_TEST=y CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index d0cd91ef4fb..f7b92dc8445 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -249,8 +249,6 @@ CONFIG_ZSTD=y CONFIG_SPL_LZMA=y CONFIG_ERRNO_STR=y CONFIG_SPL_HEXDUMP=y -CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_UNIT_TEST=y CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index b138b352de6..72483d8ba10 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -252,8 +252,6 @@ CONFIG_TPM=y CONFIG_ZSTD=y # CONFIG_VPL_LZMA is not set CONFIG_ERRNO_STR=y -CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_UNIT_TEST=y CONFIG_SPL_UNIT_TEST=y CONFIG_UT_TIME=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index c4a49fbd6f0..791979e7449 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-sei510" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index ae254c62f2a..ce5374319ba 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -10,7 +10,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xFFFF0000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-sei610" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 0af87dc4fba..b673b3f6da2 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_SHEEVAPLUG=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug" +CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug" CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_HAS_BOARD_SIZE_LIMIT=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 7a3f1d4dbdf..fa80d489f5e 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -40,7 +40,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" -CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index b54d2cefa10..5de482a0d84 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -12,10 +12,10 @@ CONFIG_FIT_SIGNATURE=y # CONFIG_BOOTSTD_FULL is not set # CONFIG_BOOTMETH_CROS is not set # CONFIG_BOOTMETH_VBE is not set +# CONFIG_BOOTM is not set CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_EXTENSION is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 29148402a1a..f2b39115fef 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -31,6 +31,7 @@ CONFIG_AHCI=y CONFIG_OF_BOARD_FIXUP=y CONFIG_SYS_MEMTEST_START=0x00800000 CONFIG_SYS_MEMTEST_END=0x00ffffff +CONFIG_LTO=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=983040 CONFIG_FIT=y @@ -64,6 +65,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SATA=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -71,6 +73,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_AES=y CONFIG_CMD_HASH=y CONFIG_CMD_BTRFS=y @@ -105,6 +108,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI_MVEBU=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_DM_RNG=y CONFIG_DM_RTC=y CONFIG_RTC_ARMADA38X=y CONFIG_SERIAL_PROBE_ALL=y @@ -112,6 +116,8 @@ CONFIG_SPL_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index 21c90e7678e..879ae0defa7 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-u200" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_G12A=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 15424fedb90..633e9c7398e 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -14,7 +14,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-wifi-dev" +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index afa42c11fac..4f1480c610c 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -8,7 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin-wifi-dev" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_VERDIN_IMX8MM=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index b6194404baa..4490a4a19a3 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -12,7 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin-wifi-dev" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_VERDIN_IMX8MP=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 01ffb8bbd75..c4b126c2b7e 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -6,7 +6,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-wetek-core2" +CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-wetek-core2" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_MESON_GXM=y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 2689495057b..4113409efbb 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -1,30 +1,43 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x21200000 -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 -CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +# CONFIG_SPL_SMP is not set +CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_OF_EMBED=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index c724d1bad74..99381478ac5 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -1,27 +1,40 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x21200000 -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 -CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_TARGET_XILINX_MBV=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000 CONFIG_RISCV_SMODE=y +# CONFIG_SPL_SMP is not set +CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_OF_EMBED=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y CONFIG_DEBUG_UART_ANNOUNCE=y @@ -29,4 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 9d3924cc9cb..143d2622748 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -33,7 +34,6 @@ CONFIG_CLOCKS=y CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 5c949e34442..b0e346208e0 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0" CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 CONFIG_SYS_PBSIZE=1049 @@ -30,7 +31,6 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 04cba5bc72d..559b32c2a19 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1" CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 CONFIG_SYS_PBSIZE=1049 @@ -30,7 +31,6 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 7a110350c2c..c02c6ba40db 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set @@ -31,7 +32,6 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 58945a1cac9..4d4b59a22ff 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_LTO=y # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_LOGLEVEL=0 @@ -32,7 +33,6 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 7dac1ec54eb..317fc8e2e15 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -33,7 +34,6 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig index fc88eee10af..31c44323666 100644 --- a/configs/xilinx_versal_net_mini_emmc_defconfig +++ b/configs/xilinx_versal_net_mini_emmc_defconfig @@ -25,7 +25,7 @@ CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set +# CONFIG_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index d78c9f80599..d0d91f98230 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -30,7 +30,7 @@ CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set +# CONFIG_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index b0567f857a3..48b6d86f9b3 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -31,7 +31,7 @@ CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set +# CONFIG_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 29cebe27136..40c6a29a16e 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -60,6 +60,9 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 7cb8b62d325..7af8b27be93 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -155,7 +155,6 @@ CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_DM_MTD=y -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index 7fdd2eee555..40d4a4a5859 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -26,7 +27,6 @@ CONFIG_CLOCKS=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index bf34832d22c..9cccf5d486f 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y +# CONFIG_BOOTM is not set CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -37,7 +38,6 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index af70ccfae12..3919e23539a 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y +# CONFIG_BOOTM is not set CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -37,7 +38,6 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index d2e920fc573..ae0c3ae7186 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y +# CONFIG_BOOTM is not set CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -27,7 +28,6 @@ CONFIG_CLOCKS=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 31f647357f7..15d471caf70 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y +# CONFIG_BOOTM is not set CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_AUTOBOOT is not set CONFIG_SYS_CBSIZE=1024 @@ -27,7 +28,6 @@ CONFIG_CLOCKS=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 096feeb83cd..071784c493b 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -19,6 +19,7 @@ CONFIG_ZYNQMP_NO_DDR=y CONFIG_SYS_LOAD_ADDR=0x8000000 # CONFIG_EXPERT is not set CONFIG_REMAKE_ELF=y +# CONFIG_BOOTM is not set # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -41,7 +42,6 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 0dbc80442bb..982777b910c 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_REMAKE_ELF=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CBSIZE=1024 @@ -43,7 +44,6 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index d95f7602d68..7d70dae5e9d 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_REMAKE_ELF=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set CONFIG_USE_PREBOOT=y CONFIG_SYS_CBSIZE=1024 @@ -43,7 +44,6 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index dd7f978c494..c7477aa9c61 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -25,6 +25,7 @@ CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds" +# CONFIG_BOOTM is not set # CONFIG_AUTOBOOT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_PREBOOT=y @@ -52,7 +53,6 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set diff --git a/disk/part.c b/disk/part.c index 36b88205eca..2bee6695828 100644 --- a/disk/part.c +++ b/disk/part.c @@ -14,6 +14,7 @@ #include <malloc.h> #include <part.h> #include <ubifs_uboot.h> +#include <dm/uclass.h> #undef PART_DEBUG @@ -305,50 +306,8 @@ static void print_part_header(const char *type, struct blk_desc *desc) CONFIG_IS_ENABLED(ISO_PARTITION) || \ CONFIG_IS_ENABLED(AMIGA_PARTITION) || \ CONFIG_IS_ENABLED(EFI_PARTITION) - puts ("\nPartition Map for "); - switch (desc->uclass_id) { - case UCLASS_IDE: - puts ("IDE"); - break; - case UCLASS_AHCI: - puts ("SATA"); - break; - case UCLASS_SCSI: - puts ("SCSI"); - break; - case UCLASS_USB: - puts ("USB"); - break; - case UCLASS_MMC: - puts ("MMC"); - break; - case UCLASS_HOST: - puts ("HOST"); - break; - case UCLASS_NVME: - puts ("NVMe"); - break; - case UCLASS_PVBLOCK: - puts("PV BLOCK"); - break; - case UCLASS_RKMTD: - puts("RKMTD"); - break; - case UCLASS_VIRTIO: - puts("VirtIO"); - break; - case UCLASS_EFI_MEDIA: - puts("EFI"); - break; - case UCLASS_BLKMAP: - puts("BLKMAP"); - break; - default: - printf("UNKNOWN(%d)", desc->uclass_id); - break; - } - printf (" device %d -- Partition Type: %s\n\n", - desc->devnum, type); + printf("\nPartition Map for %s device %d -- Partition Type: %s\n\n", + uclass_get_name(desc->uclass_id), desc->devnum, type); #endif /* any CONFIG_..._PARTITION */ } @@ -717,8 +676,11 @@ int part_get_info_by_name(struct blk_desc *desc, const char *name, for (i = 1; i < part_drv->max_entries; i++) { ret = part_drv->get_info(desc, i, info); if (ret != 0) { - /* no more entries in table */ - break; + /* + * Partition with this index can't be obtained, but + * further partitions might be, so keep checking. + */ + continue; } if (strcmp(name, (const char *)info->name) == 0) { /* matched */ diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 05d8f777595..9e337cae2cb 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -128,6 +128,7 @@ Boot command When executing the fastboot ``boot`` command, if ``fastboot_bootcmd`` is set then that will be executed in place of ``bootm <CONFIG_FASTBOOT_BUF_ADDR>``. +This is supported if CONFIG_CMDLINE is enabled, which it normally is. Partition Names --------------- diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst index 86acdafa06f..cbf1ea76107 100644 --- a/doc/board/amlogic/jethub-j100.rst +++ b/doc/board/amlogic/jethub-j100.rst @@ -1,9 +1,9 @@ .. SPDX-License-Identifier: GPL-2.0+ -U-Boot for JetHub J100 (A113X) -============================== +U-Boot for JetHub J100/J110 (A113X) +=================================== -JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device +JetHome Jethub D1/D1+ (http://jethome.ru/jethub-d1p) is a home automation controller device manufactured by JetHome with the following specifications: - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz @@ -23,7 +23,10 @@ manufactured by JetHome with the following specifications: The basic version also has: - - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0 + - Zigbee module one from: + - TI CC2538 + CC2592 Zigbee 3.0 Wireless + - TI CC2652P1 Zigbee 3.0 Wireless + - Silicon Labs EFT32MG21 Zigbee 3.0/Thread Wireless - 1 x 1-Wire - 2 x RS-485 - 4 x dry contact digital GPIO inputs diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst index c604e42990e..4eeba46ba7a 100644 --- a/doc/board/emulation/qemu-x86.rst +++ b/doc/board/emulation/qemu-x86.rst @@ -134,7 +134,7 @@ The output will be something like this:: U-Boot SPL 2023.07 (Jul 23 2023 - 08:00:12 -0600) Trying to boot from SPI - Jumping to 64-bit U-Boot: Note many features are missing + Jumping to 64-bit U-Boot U-Boot 2023.07 (Jul 23 2023 - 08:00:12 -0600) diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst index 0c52dc7b095..2762bf74c11 100644 --- a/doc/board/starfive/index.rst +++ b/doc/board/starfive/index.rst @@ -6,4 +6,5 @@ StarFive .. toctree:: :maxdepth: 1 + milk-v_mars.rst visionfive2 diff --git a/doc/board/starfive/milk-v_mars.rst b/doc/board/starfive/milk-v_mars.rst new file mode 100644 index 00000000000..554932ecfd4 --- /dev/null +++ b/doc/board/starfive/milk-v_mars.rst @@ -0,0 +1,111 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Milk-V Mars +=========== + +U-Boot for the Milk-V Mars uses the same U-Boot binaries as the VisionFive 2 +board. In U-Boot SPL the actual board is detected and the device-tree patched +accordingly. + +Building +~~~~~~~~ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + +The M-mode software OpenSBI provides the supervisor binary interface (SBI) and +is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot. +Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use +a current release. + +.. code-block:: console + + git clone https://github.com/riscv/opensbi.git + cd opensbi + make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0 + +Now build the U-Boot SPL and U-Boot proper. + +.. code-block:: console + + cd <U-Boot-dir> + make starfive_visionfive2_defconfig + make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin + +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well +as the FIT image (u-boot.itb) with OpenSBI and U-Boot. + +Device-tree selection +~~~~~~~~~~~~~~~~~~~~~ + +Depending on the board version U-Boot set variable $fdtfile to either +starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or +starfive/jh7110-starfive-visionfive-2-v1.3b.dtb. + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + + setenv fdtfile my_device-tree.dtb + env save + +or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to +provide a default value. + +Boot source selection +~~~~~~~~~~~~~~~~~~~~~ + +The board provides the DIP switches MSEL[1:0] to select the boot device out of +SPI flash, eMMC, SD-card, UART. To select booting from SD-card set the DIP +switches MSEL[1:0] to 10. + +Preparing the SD-Card +~~~~~~~~~~~~~~~~~~~~~ + +The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the +partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free +to choose any partition number. + +With the default configuration U-Boot SPL loads the U-Boot FIT image +(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2). +When formatting it is recommended to use GUID +BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition. + +The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin, +u-boot-nodtb.bin and the device tree blob. + +Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) + +.. code-block:: bash + + sudo sgdisk --clear \ + --set-alignment=2 \ + --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\ + --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \ + --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \ + /dev/sdb + +Copy U-Boot to the SD card + +.. code-block:: bash + + sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1 + sudo dd if=u-boot.itb of=/dev/sdb2 + + sudo mount /dev/sdb3 /mnt/ + sudo cp u-boot-spl.bin.normal.out /mnt/ + sudo cp u-boot.itb /mnt/ + sudo cp Image.gz /mnt/ + sudo cp initramfs.cpio.gz /mnt/ + sudo cp jh7110-starfive-visionfive-2.dtb /mnt/ + sudo umount /mnt + +Booting +~~~~~~~ + +Once you plugin the sdcard and power up, you should see the U-Boot prompt. diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index abda8ac21bc..2c68df3ce4d 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -71,6 +71,24 @@ Now build the U-Boot SPL and U-Boot proper This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well as the FIT image (u-boot.itb) with OpenSBI and U-Boot. +Device-tree selection +~~~~~~~~~~~~~~~~~~~~~ + +Depending on the board version U-Boot set variable $fdtfile to either +starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or +starfive/jh7110-starfive-visionfive-2-v1.3b.dtb. + +To overrule this selection the variable can be set manually and saved in the +environment + +:: + + setenv fdtfile my_device-tree.dtb + env save + +or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to provide +a default value. + Flashing ~~~~~~~~ diff --git a/doc/build/docker.rst b/doc/build/docker.rst index 953d1b28a06..45659b3b89d 100644 --- a/doc/build/docker.rst +++ b/doc/build/docker.rst @@ -11,4 +11,4 @@ Or to use an existing container .. code-block:: bash - sudo docker pull trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020 + sudo docker pull trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024 diff --git a/doc/build/gen_compile_commands.rst b/doc/build/gen_compile_commands.rst index 50305cec4a8..d503764f9e3 100644 --- a/doc/build/gen_compile_commands.rst +++ b/doc/build/gen_compile_commands.rst @@ -42,7 +42,7 @@ needed for it to be usable by the LSP, unless you set a name for the database other than it's default one (compile_commands.json). Compatible IDEs -=============== +--------------- Several popular integrated development environments (IDEs) support the use of JSON compilation databases for C/C++ development, making it easier to @@ -73,7 +73,7 @@ compile_commands.json in the root of the repository should suffice to enable code navigation. Usage -===== +----- For further details on the script's options, please refer to its help message, as in the example below. diff --git a/doc/develop/tests_sandbox.rst b/doc/develop/tests_sandbox.rst index bfd3bdb9270..72923070150 100644 --- a/doc/develop/tests_sandbox.rst +++ b/doc/develop/tests_sandbox.rst @@ -28,8 +28,8 @@ Some of the available tests are: - test/image/test-imagetools.sh - multi-file images - test/py/tests/test-fit.py - FIT images - - tracing: test/trace/test-trace.sh tests the tracing system (see - README.trace) + - tracing: test/trace/test-trace.sh tests the tracing system + (see :doc:`trace`). - verified boot: test/py/tests/test_vboot.py If you change or enhance any U-Boot subsystem, you should write or expand a diff --git a/doc/device-tree-bindings/sysreset/ti,sci-sysreset.txt b/doc/device-tree-bindings/sysreset/ti,sci-sysreset.txt deleted file mode 100644 index 02704c6487e..00000000000 --- a/doc/device-tree-bindings/sysreset/ti,sci-sysreset.txt +++ /dev/null @@ -1,29 +0,0 @@ -Texas Instruments TI SCI System Reset Controller -================================================ - -Some TI SoCs contain a system controller (like the SYSFW, etc...) that is -responsible for controlling the state of the IPs that are present. -Communication between the host processor running an OS and the system -controller happens through a protocol known as TI SCI [1]. - -[1] http://processors.wiki.ti.com/index.php/TISCI - -System Reset Controller Node -============================ -The sysreset controller node represents the reset for the overall SoC -which is managed by the SYSFW. Because this relies on the TI SCI protocol -to communicate with the SYSFW it must be a child of the sysfw node. - -Required Properties: --------------------- - - compatible: Must be "ti,sci-sysreset" - -Example (AM65x): ----------------- - sysfw: sysfw { - compatible = "ti,am654-system-controller"; - ... - k3_sysreset: sysreset-controller { - compatible = "ti,sci-sysreset"; - }; - }; diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 840c6cedfde..5b4df36804b 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -3,7 +3,7 @@ Babel==2.14.0 certifi==2023.11.17 charset-normalizer==3.3.2 docutils==0.20.1 -idna==3.6 +idna==3.7 imagesize==1.4.1 Jinja2==3.1.3 MarkupSafe==2.1.3 diff --git a/doc/usage/cmd/itest.rst b/doc/usage/cmd/itest.rst index ab933db760d..9c307fb4bf4 100644 --- a/doc/usage/cmd/itest.rst +++ b/doc/usage/cmd/itest.rst @@ -86,6 +86,8 @@ Numbers will be truncated according to the postfix before comparing: Postfix .s causes a string compare. The string '0xa1234' is alphabetically smaller than '0xb'. +:: + => if itest.s 0xa1234 < 0xb; then echo true; else echo false; fi true diff --git a/doc/usage/partitions.rst b/doc/usage/partitions.rst index 628469bbec9..acf4573097d 100644 --- a/doc/usage/partitions.rst +++ b/doc/usage/partitions.rst @@ -44,9 +44,20 @@ partname <devtype><devletter><partnum> devtype - A device type like ``mmcsd`` or ``hd``. See the - ``part_set_generic_name`` function in ``disk/part.c`` for a - complete list. + The devtype field is set in dependence of the device class: + + ======= =============== + devtype device class + ======= =============== + hd IDE or SATA + sd SCSI + usbd USB + mmcsd eMMC or SD-card + xx others + ======= =============== + + See the ``part_set_generic_name`` function in ``disk/part.c`` + for the complete list. devletter The device number as an offset from ``a``. For example, device diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c index cf94a3e1b64..0c09ba02de4 100644 --- a/drivers/clk/exynos/clk-exynos850.c +++ b/drivers/clk/exynos/clk-exynos850.c @@ -10,6 +10,13 @@ #include <dt-bindings/clock/exynos850.h> #include "clk.h" +enum exynos850_cmu_id { + CMU_TOP, + CMU_PERI, + CMU_CORE, + CMU_HSI, +}; + /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -19,9 +26,23 @@ #define PLL_CON3_PLL_SHARED0 0x014c #define PLL_CON0_PLL_SHARED1 0x0180 #define PLL_CON3_PLL_SHARED1 0x018c +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 +#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c +#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 +#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 +#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 +#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 +#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c +#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 +#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c +#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 @@ -31,23 +52,40 @@ #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c +#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 -static const struct samsung_pll_clock top_pure_pll_clks[] = { - PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", - PLL_CON3_PLL_SHARED0), - PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", - PLL_CON3_PLL_SHARED1), - PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", - PLL_CON3_PLL_MMC), -}; - -/* List of parent clocks for Muxes in CMU_TOP */ +/* List of parent clocks for Muxes in CMU_TOP: for PURECLKCOMP */ PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" }; PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" }; PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ +PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "dout_shared0_div4" }; +PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared1_div3" }; +PNAME(mout_core_mmc_embd_p) = { "clock-oscclk", "dout_shared0_div2", + "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "mout_mmc_pll", + "clock-oscclk", "clock-oscclk" }; +PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", + "dout_shared0_div4", "dout_shared1_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ +PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2", + "dout_shared1_div2", "dout_shared0_div3", + "dout_shared1_div3", "mout_mmc_pll", + "clock-oscclk", "clock-oscclk" }; +PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", @@ -55,6 +93,17 @@ PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4", "dout_shared1_div4", "clock-oscclk" }; +/* PURECLKCOMP */ + +static const struct samsung_pll_clock top_pure_pll_clks[] = { + PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED0), + PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED1), + PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", + PLL_CON3_PLL_MMC), +}; + static const struct samsung_mux_clock top_pure_mux_clks[] = { MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), @@ -64,15 +113,6 @@ static const struct samsung_mux_clock top_pure_mux_clks[] = { PLL_CON0_PLL_MMC, 4, 1), }; -static const struct samsung_mux_clock top_peri_mux_clks[] = { - MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), - MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), - MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, - CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), -}; - static const struct samsung_div_clock top_pure_div_clks[] = { DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), @@ -88,13 +128,79 @@ static const struct samsung_div_clock top_pure_div_clks[] = { CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), }; -static const struct samsung_div_clock top_peri_div_clks[] = { - DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", - CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), - DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", - CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), - DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", - CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +/* CORE */ + +static const struct samsung_mux_clock top_core_mux_clks[] = { + MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), + MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3), + MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2), +}; + +static const struct samsung_gate_clock top_core_gate_clks[] = { + GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus", + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), + GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci", + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), + GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd", + CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0), + GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss", + CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0), +}; + +static const struct samsung_div_clock top_core_div_clks[] = { + DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), + DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci", + CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4), + DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd", + CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9), + DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss", + CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4), +}; + +/* HSI */ + +static const struct samsung_mux_clock top_hsi_mux_clks[] = { + MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), + MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3), + MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p, + CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2), +}; + +static const struct samsung_gate_clock top_hsi_gate_clks[] = { + GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", + CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), + GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card", + CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0), + GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd", + CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0), +}; + +static const struct samsung_div_clock top_hsi_div_clks[] = { + DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", + CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), + DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card", + CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9), + DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd", + CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4), +}; + +/* PERI */ + +static const struct samsung_mux_clock top_peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), + MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), }; static const struct samsung_gate_clock top_peri_gate_clks[] = { @@ -106,12 +212,31 @@ static const struct samsung_gate_clock top_peri_gate_clks[] = { CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), }; +static const struct samsung_div_clock top_peri_div_clks[] = { + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", + CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), + DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", + CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +}; + static const struct samsung_clk_group top_cmu_clks[] = { /* CMU_TOP_PURECLKCOMP */ { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) }, { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) }, { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) }, + /* CMU_TOP clocks for CMU_CORE */ + { S_CLK_MUX, top_core_mux_clks, ARRAY_SIZE(top_core_mux_clks) }, + { S_CLK_GATE, top_core_gate_clks, ARRAY_SIZE(top_core_gate_clks) }, + { S_CLK_DIV, top_core_div_clks, ARRAY_SIZE(top_core_div_clks) }, + + /* CMU_TOP clocks for CMU_HSI */ + { S_CLK_MUX, top_hsi_mux_clks, ARRAY_SIZE(top_hsi_mux_clks) }, + { S_CLK_GATE, top_hsi_gate_clks, ARRAY_SIZE(top_hsi_gate_clks) }, + { S_CLK_DIV, top_hsi_div_clks, ARRAY_SIZE(top_hsi_div_clks) }, + /* CMU_TOP clocks for CMU_PERI */ { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) }, { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) }, @@ -120,7 +245,7 @@ static const struct samsung_clk_group top_cmu_clks[] = { static int exynos850_cmu_top_probe(struct udevice *dev) { - return samsung_cmu_register_one(dev, top_cmu_clks, + return samsung_cmu_register_one(dev, CMU_TOP, top_cmu_clks, ARRAY_SIZE(top_cmu_clks)); } @@ -129,11 +254,13 @@ static const struct udevice_id exynos850_cmu_top_ids[] = { { } }; +SAMSUNG_CLK_OPS(exynos850_cmu_top, CMU_TOP); + U_BOOT_DRIVER(exynos850_cmu_top) = { .name = "exynos850-cmu-top", .id = UCLASS_CLK, .of_match = exynos850_cmu_top_ids, - .ops = &ccf_clk_ops, + .ops = &exynos850_cmu_top_clk_ops, .probe = exynos850_cmu_top_probe, .flags = DM_FLAG_PRE_RELOC, }; @@ -171,7 +298,8 @@ static const struct samsung_clk_group peri_cmu_clks[] = { static int exynos850_cmu_peri_probe(struct udevice *dev) { - return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top); + return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks, + exynos850_cmu_top); } static const struct udevice_id exynos850_cmu_peri_ids[] = { @@ -179,11 +307,149 @@ static const struct udevice_id exynos850_cmu_peri_ids[] = { { } }; +SAMSUNG_CLK_OPS(exynos850_cmu_peri, CMU_PERI); + U_BOOT_DRIVER(exynos850_cmu_peri) = { .name = "exynos850-cmu-peri", .id = UCLASS_CLK, .of_match = exynos850_cmu_peri_ids, - .ops = &ccf_clk_ops, + .ops = &exynos850_cmu_peri_clk_ops, .probe = exynos850_cmu_peri_probe, .flags = DM_FLAG_PRE_RELOC, }; + +/* ---- CMU_CORE ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_CORE (0x12000000) */ +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 +#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec + +/* List of parent clocks for Muxes in CMU_CORE */ +PNAME(mout_core_bus_user_p) = { "clock-oscclk", "dout_core_bus" }; +PNAME(mout_core_mmc_embd_user_p) = { "clock-oscclk", + "dout_core_mmc_embd" }; + +static const struct samsung_mux_clock core_mux_clks[] = { + MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p, + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user", + mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_div_clock core_div_clks[] = { + DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user", + CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), +}; + +static const struct samsung_gate_clock core_gate_clks[] = { + GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", + "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_clk_group core_cmu_clks[] = { + { S_CLK_MUX, core_mux_clks, ARRAY_SIZE(core_mux_clks) }, + { S_CLK_DIV, core_div_clks, ARRAY_SIZE(core_div_clks) }, + { S_CLK_GATE, core_gate_clks, ARRAY_SIZE(core_gate_clks) }, +}; + +static int exynos850_cmu_core_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, CMU_CORE, core_cmu_clks, + exynos850_cmu_top); +} + +static const struct udevice_id exynos850_cmu_core_ids[] = { + { .compatible = "samsung,exynos850-cmu-core" }, + { } +}; + +SAMSUNG_CLK_OPS(exynos850_cmu_core, CMU_CORE); + +U_BOOT_DRIVER(exynos850_cmu_core) = { + .name = "exynos850-cmu-core", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_core_ids, + .ops = &exynos850_cmu_core_clk_ops, + .probe = exynos850_cmu_core_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ---- CMU_HSI ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI (0x13400000) */ +#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 +#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 +#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c +#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 +#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 +#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c +#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 + +/* List of parent clocks for Muxes in CMU_HSI */ +PNAME(mout_hsi_bus_user_p) = { "clock-oscclk", "dout_hsi_bus" }; +PNAME(mout_hsi_mmc_card_user_p) = { "clock-oscclk", "dout_hsi_mmc_card" }; +PNAME(mout_hsi_usb20drd_user_p) = { "clock-oscclk", "dout_hsi_usb20drd" }; + +static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p, + PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user", + mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user", + mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, + 4, 1), +}; + +static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", + CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0), + GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "clock-oscclk", + CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", + "mout_hsi_mmc_card_user", + CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0), + GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early", + "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0), +}; + +static const struct samsung_clk_group hsi_cmu_clks[] = { + { S_CLK_MUX, hsi_mux_clks, ARRAY_SIZE(hsi_mux_clks) }, + { S_CLK_GATE, hsi_gate_clks, ARRAY_SIZE(hsi_gate_clks) }, +}; + +static int exynos850_cmu_hsi_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, CMU_HSI, hsi_cmu_clks, + exynos850_cmu_hsi); +} + +static const struct udevice_id exynos850_cmu_hsi_ids[] = { + { .compatible = "samsung,exynos850-cmu-hsi" }, + { } +}; + +SAMSUNG_CLK_OPS(exynos850_cmu_hsi, CMU_HSI); + +U_BOOT_DRIVER(exynos850_cmu_hsi) = { + .name = "exynos850-cmu-hsi", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_hsi_ids, + .ops = &exynos850_cmu_hsi_clk_ops, + .probe = exynos850_cmu_hsi_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c index 4aacbc26b25..542d577eaa6 100644 --- a/drivers/clk/exynos/clk-pll.c +++ b/drivers/clk/exynos/clk-pll.c @@ -136,7 +136,7 @@ static struct clk *_samsung_clk_register_pll(void __iomem *base, return clk; } -void samsung_clk_register_pll(void __iomem *base, +void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, const struct samsung_pll_clock *clk_list, unsigned int nr_clk) { @@ -145,10 +145,12 @@ void samsung_clk_register_pll(void __iomem *base, for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_pll_clock *pll_clk; + unsigned long clk_id; pll_clk = &clk_list[cnt]; clk = _samsung_clk_register_pll(base, pll_clk); - clk_dm(pll_clk->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, pll_clk->id); + clk_dm(clk_id, clk); } } diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h index bd79309fa1c..bdc94e7624d 100644 --- a/drivers/clk/exynos/clk-pll.h +++ b/drivers/clk/exynos/clk-pll.h @@ -15,9 +15,15 @@ #include <linux/clk-provider.h> +struct samsung_pll_clock; + enum samsung_pll_type { pll_0822x, pll_0831x, }; +void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk); + #endif /* __EXYNOS_CLK_PLL_H */ diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c index 430767f072d..943e8bd0189 100644 --- a/drivers/clk/exynos/clk.c +++ b/drivers/clk/exynos/clk.c @@ -10,61 +10,67 @@ #include <dm.h> #include "clk.h" -void samsung_clk_register_mux(void __iomem *base, - const struct samsung_mux_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_mux(void __iomem *base, unsigned int cmu_id, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_mux_clock *m; + unsigned long clk_id; m = &clk_list[cnt]; clk = clk_register_mux(NULL, m->name, m->parent_names, m->num_parents, m->flags, base + m->offset, m->shift, m->width, m->mux_flags); - clk_dm(m->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); + clk_dm(clk_id, clk); } } -void samsung_clk_register_div(void __iomem *base, - const struct samsung_div_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_div(void __iomem *base, unsigned int cmu_id, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_div_clock *d; + unsigned long clk_id; d = &clk_list[cnt]; clk = clk_register_divider(NULL, d->name, d->parent_name, d->flags, base + d->offset, d->shift, d->width, d->div_flags); - clk_dm(d->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, d->id); + clk_dm(clk_id, clk); } } -void samsung_clk_register_gate(void __iomem *base, - const struct samsung_gate_clock *clk_list, - unsigned int nr_clk) +static void samsung_clk_register_gate(void __iomem *base, unsigned int cmu_id, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk) { unsigned int cnt; for (cnt = 0; cnt < nr_clk; cnt++) { struct clk *clk; const struct samsung_gate_clock *g; + unsigned long clk_id; g = &clk_list[cnt]; clk = clk_register_gate(NULL, g->name, g->parent_name, g->flags, base + g->offset, g->bit_idx, g->gate_flags, NULL); - clk_dm(g->id, clk); + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, g->id); + clk_dm(clk_id, clk); } } -typedef void (*samsung_clk_register_fn)(void __iomem *base, +typedef void (*samsung_clk_register_fn)(void __iomem *base, unsigned int cmu_id, const void *clk_list, unsigned int nr_clk); @@ -78,34 +84,37 @@ static const samsung_clk_register_fn samsung_clk_register_fns[] = { /** * samsung_cmu_register_clocks() - Register provided clock groups * @base: Base address of CMU registers + * @cmu_id: CMU index number * @clk_groups: list of clock groups * @nr_groups: count of clock groups in @clk_groups * * Having the array of clock groups @clk_groups makes it possible to keep a * correct clocks registration order. */ -void samsung_cmu_register_clocks(void __iomem *base, - const struct samsung_clk_group *clk_groups, - unsigned int nr_groups) +static void samsung_cmu_register_clocks(void __iomem *base, unsigned int cmu_id, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) { unsigned int i; for (i = 0; i < nr_groups; i++) { const struct samsung_clk_group *g = &clk_groups[i]; - samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk); + samsung_clk_register_fns[g->type](base, cmu_id, + g->clk_list, g->nr_clk); } } /** * samsung_cmu_register_one - Register all CMU clocks * @dev: CMU device + * @cmu_id: CMU index number * @clk_groups: list of CMU clock groups * @nr_groups: count of CMU clock groups in @clk_groups * * Return: 0 on success or negative value on error. */ -int samsung_cmu_register_one(struct udevice *dev, +int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id, const struct samsung_clk_group *clk_groups, unsigned int nr_groups) { @@ -115,7 +124,7 @@ int samsung_cmu_register_one(struct udevice *dev, if (!base) return -EINVAL; - samsung_cmu_register_clocks(base, clk_groups, nr_groups); + samsung_cmu_register_clocks(base, cmu_id, clk_groups, nr_groups); return 0; } diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h index 91a51b877a6..ed0a395f0f6 100644 --- a/drivers/clk/exynos/clk.h +++ b/drivers/clk/exynos/clk.h @@ -13,6 +13,51 @@ #include <linux/clk-provider.h> #include "clk-pll.h" +#define _SAMSUNG_CLK_OPS(_name, _cmu) \ +static int _name##_of_xlate(struct clk *clk, \ + struct ofnode_phandle_args *args) \ +{ \ + if (args->args_count > 1) { \ + debug("Invalid args_count: %d\n", args->args_count); \ + return -EINVAL; \ + } \ + \ + if (args->args_count) \ + clk->id = SAMSUNG_TO_CLK_ID(_cmu, args->args[0]); \ + else \ + clk->id = 0; \ + \ + return 0; \ +} \ + \ +static const struct clk_ops _name##_clk_ops = { \ + .set_rate = ccf_clk_set_rate, \ + .get_rate = ccf_clk_get_rate, \ + .set_parent = ccf_clk_set_parent, \ + .enable = ccf_clk_enable, \ + .disable = ccf_clk_disable, \ + .of_xlate = _name##_of_xlate, \ +} + +/** + * SAMSUNG_CLK_OPS - Define clock operations structure for specified CMU. + * @name: name of generated structure + * @cmu: CMU index + * + * Like ccf_clk_ops, but with custom .of_xlate callback. + */ +#define SAMSUNG_CLK_OPS(name, cmu) _SAMSUNG_CLK_OPS(name, cmu) + +/** + * SAMSUNG_TO_CLK_ID - Calculate a global clock index. + * @_cmu: CMU index + * @_id: local clock index (unique across @_cmu) + * + * Return: A global clock index unique across all CMUs. + * Keeps a range of 256 available clocks for every CMU. + */ +#define SAMSUNG_TO_CLK_ID(_cmu, _id) (((_cmu) << 8) | ((_id) & 0xff)) + /** * struct samsung_mux_clock - information about mux clock * @id: platform specific id of the clock @@ -179,29 +224,14 @@ struct samsung_clk_group { unsigned int nr_clk; }; -void samsung_clk_register_mux(void __iomem *base, - const struct samsung_mux_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_div(void __iomem *base, - const struct samsung_div_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_gate(void __iomem *base, - const struct samsung_gate_clock *clk_list, - unsigned int nr_clk); -void samsung_clk_register_pll(void __iomem *base, - const struct samsung_pll_clock *clk_list, - unsigned int nr_clk); - -void samsung_cmu_register_clocks(void __iomem *base, - const struct samsung_clk_group *clk_groups, - unsigned int nr_groups); -int samsung_cmu_register_one(struct udevice *dev, +int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id, const struct samsung_clk_group *clk_groups, unsigned int nr_groups); /** * samsung_register_cmu - Register CMU clocks ensuring parent CMU is present * @dev: CMU device + * @cmu_id: CMU index number * @clk_groups: list of CMU clock groups * @parent_drv: name of parent CMU driver * @@ -210,7 +240,7 @@ int samsung_cmu_register_one(struct udevice *dev, * * Return: 0 on success or negative value on error. */ -#define samsung_register_cmu(dev, clk_groups, parent_drv) \ +#define samsung_register_cmu(dev, cmu_id, clk_groups, parent_drv) \ ({ \ struct udevice *__parent; \ int __ret; \ @@ -220,8 +250,8 @@ int samsung_cmu_register_one(struct udevice *dev, if (__ret || !__parent) \ __ret = -ENOENT; \ else \ - __ret = samsung_cmu_register_one(dev, clk_groups, \ - ARRAY_SIZE(clk_groups)); \ + __ret = samsung_cmu_register_one(dev, cmu_id, \ + clk_groups, ARRAY_SIZE(clk_groups)); \ __ret; \ }) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0df0d1881a4..8dae635ac2c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX config CLK_QCOM bool - depends on CLK && DM_RESET + depends on CLK && DM_RESET && POWER_DOMAIN def_bool n menu "Qualcomm clock drivers" diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e6647f7c41d..5a5868169c8 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -23,11 +23,7 @@ #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) -#define SDCC_M(n) ((n * 0x1000) + 0x4100C) -#define SDCC_N(n) ((n * 0x1000) + 0x41010) -#define SDCC_D(n) ((n * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) @@ -38,31 +34,10 @@ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -static const struct bcr_regs sdc_regs[] = { - { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), - }, - { - .cfg_rcgr = SDCC_CFG_RCGR(2), - .cmd_rcgr = SDCC_CMD_RCGR(2), - .M = SDCC_M(2), - .N = SDCC_N(2), - .D = SDCC_D(2), - } -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -86,7 +61,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); @@ -94,14 +69,6 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - /* UART: 115200 */ int apq8016_clk_init_uart(phys_addr_t base) { @@ -109,7 +76,7 @@ int apq8016_clk_init_uart(phys_addr_t base) clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index a4731613c5e..479f9771a46 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -26,31 +26,15 @@ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ #define SDCC2_AHB_CBCR (0x14008) #define SDCC2_CMD_RCGR (0x14010) -#define SDCC2_CFG_RCGR (0x14014) -#define SDCC2_M (0x14018) -#define SDCC2_N (0x1401C) -#define SDCC2_D (0x14020) #define BLSP2_AHB_CBCR (0x25004) #define BLSP2_UART2_APPS_CBCR (0x29004) #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) -#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) -#define BLSP2_UART2_APPS_M (0x29014) -#define BLSP2_UART2_APPS_N (0x29018) -#define BLSP2_UART2_APPS_D (0x2901C) /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(30) #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC2_CFG_RCGR, - .cmd_rcgr = SDCC2_CMD_RCGR, - .M = SDCC2_M, - .N = SDCC2_N, - .D = SDCC2_D, -}; - static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -69,7 +53,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) int div = 5; clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); @@ -77,21 +61,13 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) return rate; } -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, - .M = BLSP2_UART2_APPS_M, - .N = BLSP2_UART2_APPS_N, - .D = BLSP2_UART2_APPS_D, -}; - static int clk_init_uart(struct msm_clk_priv *priv) { /* Enable AHB clock */ clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7c683e51922..05e5ab7d094 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -22,7 +22,9 @@ #include <linux/bug.h> #include <linux/delay.h> #include <linux/bitops.h> +#include <linux/iopoll.h> #include <reset-uclass.h> +#include <power-domain-uclass.h> #include "clock-qcom.h" @@ -30,6 +32,13 @@ #define CBCR_BRANCH_ENABLE_BIT BIT(0) #define CBCR_BRANCH_OFF_BIT BIT(31) +#define GDSC_SW_COLLAPSE_MASK BIT(0) +#define GDSC_POWER_DOWN_COMPLETE BIT(15) +#define GDSC_POWER_UP_COMPLETE BIT(16) +#define GDSC_PWR_ON_MASK BIT(31) +#define CFG_GDSCR_OFFSET 0x4 +#define GDSC_STATUS_POLL_TIMEOUT_US 1500 + /* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) { @@ -95,7 +104,7 @@ void clk_bcr_update(phys_addr_t apps_cmd_rcgr) * root set rate for clocks with half integer and MND divider * div should be pre-calculated ((div * 2) - 1) */ -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width) { u32 cfg; @@ -111,13 +120,14 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask); /* Program MND values */ - writel(m_val & mask, base + regs->M); - writel(n_val & mask, base + regs->N); - writel(d_val & mask, base + regs->D); + writel(m_val & mask, base + cmd_rcgr + RCG_M_REG); + writel(n_val & mask, base + cmd_rcgr + RCG_N_REG); + writel(d_val & mask, base + cmd_rcgr + RCG_D_REG); /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | + CFG_SRC_DIV_MASK); cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ if (div) @@ -126,20 +136,20 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, if (n && n != m) cfg |= CFG_MODE_DUAL_EDGE; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } /* root set rate for clocks with half integer and mnd_width=0 */ -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source) { u32 cfg; /* setup src select and divider */ - cfg = readl(base + regs->cfg_rcgr); + cfg = readl(base + cmd_rcgr + RCG_CFG_REG); cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ @@ -150,10 +160,10 @@ void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, if (div) cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK; - writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */ /* Inform h/w to start using the new config. */ - clk_bcr_update(base + regs->cmd_rcgr); + clk_bcr_update(base + cmd_rcgr); } const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) @@ -217,12 +227,13 @@ U_BOOT_DRIVER(qcom_clk) = { .ops = &msm_clk_ops, .priv_auto = sizeof(struct msm_clk_priv), .probe = msm_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; int qcom_cc_bind(struct udevice *parent) { struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent); - struct udevice *clkdev, *rstdev; + struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev; struct driver *drv; int ret; @@ -237,20 +248,41 @@ int qcom_cc_bind(struct udevice *parent) if (ret) return ret; - /* Bail out early if resets are not specified for this platform */ - if (!data->resets) - return ret; + if (data->resets) { + /* Get a handle to the common reset handler */ + drv = lists_driver_lookup_name("qcom_reset"); + if (!drv) { + ret = -ENOENT; + goto unbind_clkdev; + } + + /* Register the reset controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, + dev_ofnode(parent), &rstdev); + if (ret) + goto unbind_clkdev; + } - /* Get a handle to the common reset handler */ - drv = lists_driver_lookup_name("qcom_reset"); - if (!drv) - return -ENOENT; + if (data->power_domains) { + /* Get a handle to the common power domain handler */ + drv = lists_driver_lookup_name("qcom_power"); + if (!drv) { + ret = -ENOENT; + goto unbind_rstdev; + } + /* Register the power domain controller */ + ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data, + dev_ofnode(parent), &pwrdev); + if (ret) + goto unbind_rstdev; + } - /* Register the reset controller */ - ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data, - dev_ofnode(parent), &rstdev); - if (ret) - device_unbind(clkdev); + return 0; + +unbind_rstdev: + device_unbind(rstdev); +unbind_clkdev: + device_unbind(clkdev); return ret; } @@ -305,3 +337,80 @@ U_BOOT_DRIVER(qcom_reset) = { .ops = &qcom_reset_ops, .probe = qcom_reset_probe, }; + +static int qcom_power_set(struct power_domain *pwr, bool on) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev); + void __iomem *base = dev_get_priv(pwr->dev); + const struct qcom_power_map *map; + u32 value; + int ret; + + if (pwr->id >= data->num_power_domains) + return -ENODEV; + + map = &data->power_domains[pwr->id]; + + if (!map->reg) + return -ENODEV; + + value = readl(base + map->reg); + + if (on) + value &= ~GDSC_SW_COLLAPSE_MASK; + else + value |= GDSC_SW_COLLAPSE_MASK; + + writel(value, base + map->reg); + + if (on) + ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + value, + (value & GDSC_POWER_UP_COMPLETE) || + (value & GDSC_PWR_ON_MASK), + GDSC_STATUS_POLL_TIMEOUT_US); + + else + ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET, + value, + (value & GDSC_POWER_DOWN_COMPLETE) || + !(value & GDSC_PWR_ON_MASK), + GDSC_STATUS_POLL_TIMEOUT_US); + + + if (ret == -ETIMEDOUT) + printf("WARNING: GDSC %lu is stuck during power on/off\n", + pwr->id); + return ret; +} + +static int qcom_power_on(struct power_domain *pwr) +{ + return qcom_power_set(pwr, true); +} + +static int qcom_power_off(struct power_domain *pwr) +{ + return qcom_power_set(pwr, false); +} + +static const struct power_domain_ops qcom_power_ops = { + .on = qcom_power_on, + .off = qcom_power_off, +}; + +static int qcom_power_probe(struct udevice *dev) +{ + /* Set our priv pointer to the base address */ + dev_set_priv(dev, (void *)dev_read_addr(dev)); + + return 0; +} + +U_BOOT_DRIVER(qcom_power) = { + .name = "qcom_power", + .id = UCLASS_POWER_DOMAIN, + .ops = &qcom_power_ops, + .probe = qcom_power_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 01088c19015..a7f833a4b6d 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -12,6 +12,11 @@ #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) +#define RCG_CFG_REG 0x4 +#define RCG_M_REG 0x8 +#define RCG_N_REG 0xc +#define RCG_D_REG 0x10 + struct pll_vote_clk { uintptr_t status; int status_bit; @@ -24,13 +29,6 @@ struct vote_clk { uintptr_t ena_vote; int vote_bit; }; -struct bcr_regs { - uintptr_t cfg_rcgr; - uintptr_t cmd_rcgr; - uintptr_t M; - uintptr_t N; - uintptr_t D; -}; struct freq_tbl { uint freq; @@ -59,9 +57,15 @@ struct qcom_reset_map { u8 bit; }; +struct qcom_power_map { + unsigned int reg; +}; + struct clk; struct msm_clk_data { + const struct qcom_power_map *power_domains; + unsigned long num_power_domains; const struct qcom_reset_map *resets; unsigned long num_resets; const struct gate_clk *clks; @@ -82,9 +86,9 @@ void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); -void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, +void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); -void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, +void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index 958312b8884..8a897a52bc0 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -28,35 +28,22 @@ #define BLSP1_UART2_BCR (0x3028) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) -#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) -#define BLSP1_UART2_APPS_M (0x303C) -#define BLSP1_UART2_APPS_N (0x3040) -#define BLSP1_UART2_APPS_D (0x3044) /* I2C controller clock control registerss */ #define BLSP1_QUP0_I2C_APPS_CBCR (0x6028) #define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C) -#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030) #define BLSP1_QUP1_I2C_APPS_CBCR (0x2008) #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C) -#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010) #define BLSP1_QUP2_I2C_APPS_CBCR (0x3010) #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000) -#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004) #define BLSP1_QUP3_I2C_APPS_CBCR (0x4020) #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000) -#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004) #define BLSP1_QUP4_I2C_APPS_CBCR (0x5020) #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000) -#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004) /* SD controller clock control registers */ #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) -#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) -#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) -#define SDCC_N(n) (((n) * 0x1000) + 0x41010) -#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) @@ -70,10 +57,6 @@ #define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) #define USB30_MOCK_UTMI_CFG_RCGR (0x39020) #define USB30_MASTER_CMD_RCGR (0x39028) -#define USB30_MASTER_CFG_RCGR (0x3902C) -#define USB30_MASTER_M (0x39030) -#define USB30_MASTER_N (0x39034) -#define USB30_MASTER_D (0x39038) #define USB2A_PHY_SLEEP_CBCR (0x4102C) #define USB_HS_PHY_CFG_AHB_CBCR (0x41030) @@ -83,12 +66,7 @@ #define ETH_SLAVE_AHB_CBCR (0x4e00c) #define ETH_AXI_CBCR (0x4e010) #define EMAC_PTP_CMD_RCGR (0x4e014) -#define EMAC_PTP_CFG_RCGR (0x4e018) #define EMAC_CMD_RCGR (0x4e01c) -#define EMAC_CFG_RCGR (0x4e020) -#define EMAC_M (0x4e024) -#define EMAC_N (0x4e028) -#define EMAC_D (0x4e02c) /* GPLL0 clock control registers */ @@ -103,22 +81,6 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .vote_bit = BIT(10) | BIT(5) | BIT(4), }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, - .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, - .M = BLSP1_UART2_APPS_M, - .N = BLSP1_UART2_APPS_N, - .D = BLSP1_UART2_APPS_D, -}; - -static const struct bcr_regs sdc_regs = { - .cfg_rcgr = SDCC_CFG_RCGR(1), - .cmd_rcgr = SDCC_CMD_RCGR(1), - .M = SDCC_M(1), - .N = SDCC_N(1), - .D = SDCC_D(1), -}; - static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -133,60 +95,6 @@ static struct pll_vote_clk gpll1_vote_clk = { .vote_bit = BIT(1), }; -static const struct bcr_regs usb30_master_regs = { - .cfg_rcgr = USB30_MASTER_CFG_RCGR, - .cmd_rcgr = USB30_MASTER_CMD_RCGR, - .M = USB30_MASTER_M, - .N = USB30_MASTER_N, - .D = USB30_MASTER_D, -}; - -static const struct bcr_regs emac_regs = { - .cfg_rcgr = EMAC_CFG_RCGR, - .cmd_rcgr = EMAC_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs emac_ptp_regs = { - .cfg_rcgr = EMAC_PTP_CFG_RCGR, - .cmd_rcgr = EMAC_PTP_CMD_RCGR, - .M = EMAC_M, - .N = EMAC_N, - .D = EMAC_D, -}; - -static const struct bcr_regs blsp1_qup0_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup1_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup2_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup3_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - -static const struct bcr_regs blsp1_qup4_i2c_apps_regs = { - .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR, - .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR, - /* mnd_width = 0 */ -}; - static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -194,29 +102,29 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, + clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ - clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 125000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 50000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0, CFG_CLK_SRC_GPLL1, 8); else if (rate == 5000000) - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); return rate; } @@ -237,7 +145,7 @@ static int qcs404_clk_enable(struct clk *clk) switch (clk->id) { case GCC_USB30_MASTER_CLK: clk_enable_cbc(priv->base + USB30_MASTER_CBCR); - clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0, + clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); break; case GCC_SYS_NOC_USB3_CLK: @@ -259,14 +167,14 @@ static int qcs404_clk_enable(struct clk *clk) /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_PTP_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_RGMII_CLK: /* SPEED_1000: freq -> 250MHz */ clk_enable_cbc(priv->base + ETH_RGMII_CBCR); clk_enable_gpll0(priv->base, &gpll1_vote_clk); - clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, + clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0, CFG_CLK_SRC_GPLL1, 8); break; case GCC_ETH_SLAVE_AHB_CLK: @@ -280,27 +188,27 @@ static int qcs404_clk_enable(struct clk *clk) break; case GCC_BLSP1_QUP0_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP1_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP2_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP3_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_BLSP1_QUP4_I2C_APPS_CLK: clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR); - clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, + clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0, CFG_CLK_SRC_CXO); break; case GCC_SDCC1_AHB_CLK: diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c index 36ffee79d96..e9c61eb480d 100644 --- a/drivers/clk/qcom/clock-sdm845.c +++ b/drivers/clk/qcom/clock-sdm845.c @@ -19,13 +19,11 @@ #include "clock-qcom.h" -#define SE9_AHB_CBCR 0x25004 -#define SE9_UART_APPS_CBCR 0x29004 #define SE9_UART_APPS_CMD_RCGR 0x18148 -#define SE9_UART_APPS_CFG_RCGR 0x1814C -#define SE9_UART_APPS_M 0x18150 -#define SE9_UART_APPS_N 0x18154 -#define SE9_UART_APPS_D 0x18158 + +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 +#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), @@ -46,14 +44,6 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { { } }; -static const struct bcr_regs uart2_regs = { - .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, - .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, - .M = SE9_UART_APPS_M, - .N = SE9_UART_APPS_N, - .D = SE9_UART_APPS_D, -}; - static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -62,7 +52,7 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 16); return freq->freq; default: @@ -71,6 +61,8 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) } static const struct gate_clk sdm845_clks[] = { + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001), + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), @@ -135,6 +127,25 @@ static int sdm845_clk_enable(struct clk *clk) debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK); + /* These numbers are just pulled from the frequency tables in the Linux driver */ + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, + (4.5 * 2) - 1, 0, 0, 1 << 8, 8); + clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, + 1, 0, 0, 0, 8); + clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, + 1, 0, 0, 0, 8); + break; + case GCC_USB30_SEC_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); + + qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK); + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); + break; + } + qcom_gate_clk_en(priv, clk->id); return 0; @@ -160,11 +171,29 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static const struct qcom_power_map sdm845_gdscs[] = { + [PCIE_0_GDSC] = { 0x6b004 }, + [PCIE_1_GDSC] = { 0x8d004 }, + [UFS_CARD_GDSC] = { 0x75004 }, + [UFS_PHY_GDSC] = { 0x77004 }, + [USB30_PRIM_GDSC] = { 0xf004 }, + [USB30_SEC_GDSC] = { 0x10004 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, + [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, +}; + static struct msm_clk_data sdm845_clk_data = { .resets = sdm845_gcc_resets, .num_resets = ARRAY_SIZE(sdm845_gcc_resets), .clks = sdm845_clks, .num_clks = ARRAY_SIZE(sdm845_clks), + .power_domains = sdm845_gdscs, + .num_power_domains = ARRAY_SIZE(sdm845_gdscs), .enable = sdm845_clk_enable, .set_rate = sdm845_clk_set_rate, @@ -183,5 +212,5 @@ U_BOOT_DRIVER(gcc_sdm845) = { .id = UCLASS_NOP, .of_match = gcc_sdm845_of_match, .bind = qcom_cc_bind, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5d1026b37da..9b1950efe05 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -21,13 +21,13 @@ DECLARE_GLOBAL_DATA_PTR; static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size) { - const char *isa; + const char *cpu; - isa = dev_read_string(dev, "riscv,isa"); - if (size < (strlen(isa) + 1)) + cpu = dev_read_string(dev, "compatible"); + if (size < (strlen(cpu) + 1)) return -ENOSPC; - strcpy(buf, isa); + strcpy(buf, cpu); return 0; } diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 5e5855a76c2..d6e2be09cf7 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -1,5 +1,4 @@ menu "Fastboot support" - depends on CMDLINE config FASTBOOT bool @@ -13,6 +12,10 @@ config FASTBOOT More information about the protocol and usecases: https://android.googlesource.com/platform/system/core/+/refs/heads/master/fastboot/ + Note that enabling CMDLINE is recommended since fastboot allows U-Boot + commands to be executed on request. The CMDLINE option is required + for anything other than simply booting the OS. + config USB_FUNCTION_FASTBOOT bool "Enable USB fastboot gadget" depends on USB_GADGET diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index f95f4e4ae15..b8782bfa7fa 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -11,6 +11,7 @@ #include <fastboot-internal.h> #include <fb_mmc.h> #include <fb_nand.h> +#include <mapmem.h> #include <part.h> #include <stdlib.h> #include <linux/printk.h> @@ -278,6 +279,7 @@ void fastboot_data_download(const void *fastboot_data, { #define BYTES_PER_DOT 0x20000 u32 pre_dot_num, now_dot_num; + void *buf; if (fastboot_data_len == 0 || (fastboot_bytes_received + fastboot_data_len) > @@ -287,8 +289,10 @@ void fastboot_data_download(const void *fastboot_data, return; } /* Download data to fastboot_buf_addr */ - memcpy(fastboot_buf_addr + fastboot_bytes_received, + buf = map_sysmem(fastboot_buf_addr, 0); + memcpy(buf + fastboot_bytes_received, fastboot_data, fastboot_data_len); + unmap_sysmem(buf); pre_dot_num = fastboot_bytes_received / BYTES_PER_DOT; fastboot_bytes_received += fastboot_data_len; @@ -331,13 +335,16 @@ void fastboot_data_complete(char *response) */ static void __maybe_unused flash(char *cmd_parameter, char *response) { + void *buf = map_sysmem(fastboot_buf_addr, 0); + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) - fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr, - image_size, response); + fastboot_mmc_flash_write(cmd_parameter, buf, image_size, + response); if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) - fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, - image_size, response); + fastboot_nand_flash_write(cmd_parameter, buf, image_size, + response); + unmap_sysmem(buf); } /** diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 3576b067729..595954542a6 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -11,6 +11,7 @@ */ #include <bcb.h> +#include <bootm.h> #include <common.h> #include <command.h> #include <env.h> @@ -20,7 +21,7 @@ /** * fastboot_buf_addr - base address of the fastboot download buffer */ -void *fastboot_buf_addr; +ulong fastboot_buf_addr; /** * fastboot_buf_size - size of the fastboot download buffer @@ -142,22 +143,19 @@ void (*fastboot_get_progress_callback(void))(const char *) */ void fastboot_boot(void) { - char *s; + char *s = NULL; - s = env_get("fastboot_bootcmd"); - if (s) { - run_command(s, CMD_FLAG_ENV); - } else if (IS_ENABLED(CONFIG_CMD_BOOTM)) { - static char boot_addr_start[20]; - static char *const bootm_args[] = { - "bootm", boot_addr_start, NULL - }; + if (IS_ENABLED(CONFIG_CMDLINE)) { + s = env_get("fastboot_bootcmd"); + if (s) + run_command(s, CMD_FLAG_ENV); + } - snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, - "0x%p", fastboot_buf_addr); - printf("Booting kernel at %s...\n\n\n", boot_addr_start); + if (!s && IS_ENABLED(CONFIG_BOOTM)) { + int ret; - do_bootm(NULL, 0, 2, bootm_args); + printf("Booting kernel at %lx...\n\n\n", fastboot_buf_addr); + ret = bootm_boot_start(fastboot_buf_addr, NULL); /* * This only happens if image is somehow faulty so we start @@ -214,16 +212,9 @@ void fastboot_set_progress_callback(void (*progress)(const char *msg)) fastboot_progress_callback = progress; } -/* - * fastboot_init() - initialise new fastboot protocol session - * - * @buf_addr: Pointer to download buffer, or NULL for default - * @buf_size: Size of download buffer, or zero for default - */ -void fastboot_init(void *buf_addr, u32 buf_size) +void fastboot_init(ulong buf_addr, u32 buf_size) { - fastboot_buf_addr = buf_addr ? buf_addr : - (void *)CONFIG_FASTBOOT_BUF_ADDR; + fastboot_buf_addr = buf_addr ? buf_addr : CONFIG_FASTBOOT_BUF_ADDR; fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE; fastboot_set_progress_callback(NULL); } diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index ee092185588..6c581b9df9c 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -16,6 +16,7 @@ #include <dm/device.h> #include <dm/device_compat.h> #include <dm/devres.h> +#include <dm/lists.h> #include <linux/bitops.h> #include <linux/compat.h> #include <linux/err.h> @@ -2840,6 +2841,12 @@ static int ti_sci_probe(struct udevice *dev) INIT_LIST_HEAD(&info->dev_list); + if (IS_ENABLED(CONFIG_SYSRESET_TI_SCI)) { + ret = device_bind_driver(dev, "ti-sci-sysreset", "sysreset", NULL); + if (ret) + dev_warn(dev, "cannot bind SYSRESET (ret = %d)\n", ret); + } + return 0; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a7fb1eb3f4c..b050585389b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -665,13 +665,6 @@ config SLG7XL45106_I2C_GPO 8-bit gpo expander, all gpo lines are controlled by writing value into data register. -config TURRIS_OMNIA_MCU - bool "Turris Omnia MCU GPIO driver" - depends on DM_GPIO - default y if TARGET_TURRIS_OMNIA - help - Support for GPIOs on MCU connected to Turris Omnia via i2c. - config FTGPIO010 bool "Faraday Technology FTGPIO010 driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 90711702a69..4a293154350 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -73,7 +73,6 @@ obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o -obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o obj-$(CONFIG_FTGPIO010) += ftgpio010.o obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 5e57b0cbde7..f5d9ab54e81 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -35,19 +35,19 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4) -static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) +static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return; /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE); - return 0; + return; } static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) @@ -84,6 +84,23 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, return 0; } +static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags) +{ + if (flags & GPIOD_IS_OUT_ACTIVE) { + return msm_gpio_direction_output(dev, gpio, 1); + } else if (flags & GPIOD_IS_OUT) { + return msm_gpio_direction_output(dev, gpio, 0); + } else if (flags & GPIOD_IS_IN) { + msm_gpio_direction_input(dev, gpio); + if (flags & GPIOD_PULL_UP) + return msm_gpio_set_value(dev, gpio, 1); + else if (flags & GPIOD_PULL_DOWN) + return msm_gpio_set_value(dev, gpio, 0); + } + + return 0; +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); @@ -110,10 +127,8 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) } static const struct dm_gpio_ops gpio_msm_ops = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, + .set_flags = msm_gpio_set_flags, .get_value = msm_gpio_get_value, - .set_value = msm_gpio_set_value, .get_function = msm_gpio_get_function, }; diff --git a/drivers/gpio/turris_omnia_mcu.c b/drivers/gpio/turris_omnia_mcu.c deleted file mode 100644 index 2d2bf2d1dd6..00000000000 --- a/drivers/gpio/turris_omnia_mcu.c +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// (C) 2022 Pali Rohár <pali@kernel.org> - -#include <common.h> -#include <dm.h> -#include <i2c.h> -#include <asm/gpio.h> -#include <linux/log2.h> - -enum commands_e { - CMD_GET_STATUS_WORD = 0x01, - CMD_GENERAL_CONTROL = 0x02, - - /* available if STS_FEATURES_SUPPORTED bit set in status word */ - CMD_GET_FEATURES = 0x10, - - /* available if FEAT_EXT_CMDS bit is set in features */ - CMD_GET_EXT_STATUS_DWORD = 0x11, - - /* available if FEAT_EXT_CMDS and FEAT_PERIPH_MCU bits are set in featurs */ - CMD_EXT_CONTROL = 0x12, - CMD_GET_EXT_CONTROL_STATUS = 0x13, -}; - -/* CMD_GET_STATUS_WORD */ -enum sts_word_e { - STS_MCU_TYPE_MASK = GENMASK(1, 0), - STS_MCU_TYPE_STM32 = 0, - STS_MCU_TYPE_GD32 = 1, - STS_MCU_TYPE_MKL = 2, - STS_FEATURES_SUPPORTED = BIT(2), - STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3), - STS_CARD_DET = BIT(4), - STS_MSATA_IND = BIT(5), - STS_USB30_OVC = BIT(6), - STS_USB31_OVC = BIT(7), - STS_USB30_PWRON = BIT(8), - STS_USB31_PWRON = BIT(9), - STS_ENABLE_4V5 = BIT(10), - STS_BUTTON_MODE = BIT(11), - STS_BUTTON_PRESSED = BIT(12), - STS_BUTTON_COUNTER_MASK = GENMASK(15, 13) -}; - -/* CMD_GENERAL_CONTROL */ -enum ctl_byte_e { - CTL_LIGHT_RST = BIT(0), - CTL_HARD_RST = BIT(1), - /*CTL_RESERVED = BIT(2),*/ - CTL_USB30_PWRON = BIT(3), - CTL_USB31_PWRON = BIT(4), - CTL_ENABLE_4V5 = BIT(5), - CTL_BUTTON_MODE = BIT(6), - CTL_BOOTLOADER = BIT(7) -}; - -/* CMD_GET_FEATURES */ -enum features_e { - FEAT_PERIPH_MCU = BIT(0), - FEAT_EXT_CMDS = BIT(1), -}; - -struct turris_omnia_mcu_info { - u16 features; -}; - -static int turris_omnia_mcu_get_function(struct udevice *dev, uint offset) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - switch (offset) { - case ilog2(STS_USB30_PWRON): - case ilog2(STS_USB31_PWRON): - case ilog2(STS_ENABLE_4V5): - case ilog2(STS_BUTTON_MODE): - return GPIOF_OUTPUT; - default: - return GPIOF_INPUT; - } - - /* bank 1 - supported only when FEAT_EXT_CMDS is set */ - case (16 + 0) ... (16 + 31): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - return GPIOF_INPUT; - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - return GPIOF_OUTPUT; - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_get_value(struct udevice *dev, uint offset) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val16[2]; - u8 val32[4]; - int ret; - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val16, 2); - if (ret) - return ret; - return ((((u16)val16[1] << 8) | val16[0]) >> offset) & 0x1; - - /* bank 1 - supported only when FEAT_EXT_CMDS is set */ - case (16 + 0) ... (16 + 31): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - ret = dm_i2c_read(dev, CMD_GET_EXT_STATUS_DWORD, val32, 4); - if (ret) - return ret; - return ((((u32)val32[3] << 24) | ((u32)val32[2] << 16) | - ((u32)val32[1] << 8) | val32[0]) >> (offset - 16)) & 0x1; - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - ret = dm_i2c_read(dev, CMD_GET_EXT_CONTROL_STATUS, val16, 2); - if (ret) - return ret; - return ((((u16)val16[1] << 8) | val16[0]) >> (offset - 16 - 32)) & 0x1; - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_set_value(struct udevice *dev, uint offset, int value) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val16[2]; - u8 val32[4]; - - switch (offset) { - /* bank 0 */ - case 0 ... 15: - switch (offset) { - case ilog2(STS_USB30_PWRON): - val16[1] = CTL_USB30_PWRON; - break; - case ilog2(STS_USB31_PWRON): - val16[1] = CTL_USB31_PWRON; - break; - case ilog2(STS_ENABLE_4V5): - val16[1] = CTL_ENABLE_4V5; - break; - case ilog2(STS_BUTTON_MODE): - val16[1] = CTL_BUTTON_MODE; - break; - default: - return -EINVAL; - } - val16[0] = value ? val16[1] : 0; - return dm_i2c_write(dev, CMD_GENERAL_CONTROL, val16, sizeof(val16)); - - /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ - case (16 + 32 + 0) ... (16 + 32 + 15): - if (!(info->features & FEAT_EXT_CMDS)) - return -EINVAL; - if (!(info->features & FEAT_PERIPH_MCU)) - return -EINVAL; - val32[3] = BIT(offset - 16 - 32) >> 8; - val32[2] = BIT(offset - 16 - 32) & 0xff; - val32[1] = value ? val32[3] : 0; - val32[0] = value ? val32[2] : 0; - return dm_i2c_write(dev, CMD_EXT_CONTROL, val32, sizeof(val32)); - - default: - return -EINVAL; - } -} - -static int turris_omnia_mcu_direction_input(struct udevice *dev, uint offset) -{ - int ret; - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - else if (ret != GPIOF_INPUT) - return -EOPNOTSUPP; - - return 0; -} - -static int turris_omnia_mcu_direction_output(struct udevice *dev, uint offset, int value) -{ - int ret; - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - else if (ret != GPIOF_OUTPUT) - return -EOPNOTSUPP; - - return turris_omnia_mcu_set_value(dev, offset, value); -} - -static int turris_omnia_mcu_xlate(struct udevice *dev, struct gpio_desc *desc, - struct ofnode_phandle_args *args) -{ - uint bank, gpio, flags, offset; - int ret; - - if (args->args_count != 3) - return -EINVAL; - - bank = args->args[0]; - gpio = args->args[1]; - flags = args->args[2]; - - switch (bank) { - case 0: - if (gpio >= 16) - return -EINVAL; - offset = gpio; - break; - case 1: - if (gpio >= 32) - return -EINVAL; - offset = 16 + gpio; - break; - case 2: - if (gpio >= 16) - return -EINVAL; - offset = 16 + 32 + gpio; - break; - default: - return -EINVAL; - } - - ret = turris_omnia_mcu_get_function(dev, offset); - if (ret < 0) - return ret; - - desc->offset = offset; - desc->flags = gpio_flags_xlate(flags); - - return 0; -} - -static const struct dm_gpio_ops turris_omnia_mcu_ops = { - .direction_input = turris_omnia_mcu_direction_input, - .direction_output = turris_omnia_mcu_direction_output, - .get_value = turris_omnia_mcu_get_value, - .set_value = turris_omnia_mcu_set_value, - .get_function = turris_omnia_mcu_get_function, - .xlate = turris_omnia_mcu_xlate, -}; - -static int turris_omnia_mcu_probe(struct udevice *dev) -{ - struct turris_omnia_mcu_info *info = dev_get_plat(dev); - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - u16 status; - u8 val[2]; - int ret; - - ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val, 2); - if (ret) { - printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n", ret); - return ret; - } - - status = ((u16)val[1] << 8) | val[0]; - - if (status & STS_FEATURES_SUPPORTED) { - ret = dm_i2c_read(dev, CMD_GET_FEATURES, val, 2); - if (ret) { - printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n", ret); - return ret; - } - info->features = ((u16)val[1] << 8) | val[0]; - } - - uc_priv->bank_name = "mcu_"; - - if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU)) - uc_priv->gpio_count = 16 + 32 + 16; - else if (info->features & FEAT_EXT_CMDS) - uc_priv->gpio_count = 16 + 32; - else - uc_priv->gpio_count = 16; - - return 0; -} - -static const struct udevice_id turris_omnia_mcu_ids[] = { - { .compatible = "cznic,turris-omnia-mcu" }, - { } -}; - -U_BOOT_DRIVER(turris_omnia_mcu) = { - .name = "turris-omnia-mcu", - .id = UCLASS_GPIO, - .ops = &turris_omnia_mcu_ops, - .probe = turris_omnia_mcu_probe, - .plat_auto = sizeof(struct turris_omnia_mcu_info), - .of_match = turris_omnia_mcu_ids, -}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 98043fc2ff3..6b06888454f 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -505,6 +505,17 @@ config TEST_DRV model. This should only be enabled for testing as it is not useful for anything else. +config TURRIS_OMNIA_MCU + bool "Enable Turris Omnia MCU driver" + depends on DM_I2C + depends on DM_GPIO + depends on DM_RNG + depends on SYSRESET + default y if TARGET_TURRIS_OMNIA + help + This enables support for Turris Omnia MCU connected GPIOs and + board power off. + config USB_HUB_USB251XB tristate "USB251XB Hub Controller Configuration Driver" depends on I2C diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1522f6c3b7d..9e829905f12 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o obj-$(CONFIG_TEGRA_CAR) += tegra_car.o obj-$(CONFIG_TEST_DRV) += test_drv.o +obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/turris_omnia_mcu.c b/drivers/misc/turris_omnia_mcu.c new file mode 100644 index 00000000000..6b2f17c0002 --- /dev/null +++ b/drivers/misc/turris_omnia_mcu.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Pali Rohár <pali@kernel.org> + * Copyright (C) 2024 Marek Behún <kabel@kernel.org> + */ + +#include <common.h> +#include <console.h> +#include <dm.h> +#include <dm/lists.h> +#include <i2c.h> +#include <rng.h> +#include <sysreset.h> +#include <turris-omnia-mcu-interface.h> +#include <asm/byteorder.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/log2.h> + +#define CMD_TRNG_MAX_ENTROPY_LEN 64 + +struct turris_omnia_mcu_info { + u32 features; +}; + +static int omnia_gpio_get_function(struct udevice *dev, uint offset) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + case ilog2(STS_USB31_PWRON): + case ilog2(STS_ENABLE_4V5): + case ilog2(STS_BUTTON_MODE): + return GPIOF_OUTPUT; + default: + return GPIOF_INPUT; + } + + /* bank 1 - supported only when FEAT_EXT_CMDS is set */ + case (16 + 0) ... (16 + 31): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + return GPIOF_INPUT; + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + return GPIOF_OUTPUT; + + default: + return -EINVAL; + } +} + +static int omnia_gpio_get_value(struct udevice *dev, uint offset) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + u32 val32; + u16 val16; + int ret; + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + ret = dm_i2c_read(dev->parent, CMD_GET_STATUS_WORD, + (void *)&val16, sizeof(val16)); + if (ret) + return ret; + + return !!(le16_to_cpu(val16) & BIT(offset)); + + /* bank 1 - supported only when FEAT_EXT_CMDS is set */ + case (16 + 0) ... (16 + 31): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + + ret = dm_i2c_read(dev->parent, CMD_GET_EXT_STATUS_DWORD, + (void *)&val32, sizeof(val32)); + if (ret) + return ret; + + return !!(le32_to_cpu(val32) & BIT(offset - 16)); + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + + ret = dm_i2c_read(dev->parent, CMD_GET_EXT_CONTROL_STATUS, + (void *)&val16, sizeof(val16)); + if (ret) + return ret; + + return !!(le16_to_cpu(val16) & BIT(offset - 16 - 32)); + + default: + return -EINVAL; + } +} + +static int omnia_gpio_set_value(struct udevice *dev, uint offset, int value) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + u16 valmask16[2]; + u8 valmask8[2]; + + switch (offset) { + /* bank 0 */ + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + valmask8[1] = CTL_USB30_PWRON; + break; + case ilog2(STS_USB31_PWRON): + valmask8[1] = CTL_USB31_PWRON; + break; + case ilog2(STS_ENABLE_4V5): + valmask8[1] = CTL_ENABLE_4V5; + break; + case ilog2(STS_BUTTON_MODE): + valmask8[1] = CTL_BUTTON_MODE; + break; + default: + return -EINVAL; + } + + valmask8[0] = value ? valmask8[1] : 0; + + return dm_i2c_write(dev->parent, CMD_GENERAL_CONTROL, valmask8, + sizeof(valmask8)); + + /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */ + case (16 + 32 + 0) ... (16 + 32 + 15): + if (!(info->features & FEAT_EXT_CMDS)) + return -EINVAL; + if (!(info->features & FEAT_PERIPH_MCU)) + return -EINVAL; + + valmask16[1] = cpu_to_le16(BIT(offset - 16 - 32)); + valmask16[0] = value ? valmask16[1] : 0; + + return dm_i2c_write(dev->parent, CMD_EXT_CONTROL, + (void *)valmask16, sizeof(valmask16)); + + default: + return -EINVAL; + } +} + +static int omnia_gpio_direction_input(struct udevice *dev, uint offset) +{ + int ret; + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + else if (ret != GPIOF_INPUT) + return -EOPNOTSUPP; + + return 0; +} + +static int omnia_gpio_direction_output(struct udevice *dev, uint offset, int value) +{ + int ret; + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + else if (ret != GPIOF_OUTPUT) + return -EOPNOTSUPP; + + return omnia_gpio_set_value(dev, offset, value); +} + +static int omnia_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + uint bank, gpio, flags, offset; + int ret; + + if (args->args_count != 3) + return -EINVAL; + + bank = args->args[0]; + gpio = args->args[1]; + flags = args->args[2]; + + switch (bank) { + case 0: + if (gpio >= 16) + return -EINVAL; + offset = gpio; + break; + case 1: + if (gpio >= 32) + return -EINVAL; + offset = 16 + gpio; + break; + case 2: + if (gpio >= 16) + return -EINVAL; + offset = 16 + 32 + gpio; + break; + default: + return -EINVAL; + } + + ret = omnia_gpio_get_function(dev, offset); + if (ret < 0) + return ret; + + desc->offset = offset; + desc->flags = gpio_flags_xlate(flags); + + return 0; +} + +static const struct dm_gpio_ops omnia_gpio_ops = { + .direction_input = omnia_gpio_direction_input, + .direction_output = omnia_gpio_direction_output, + .get_value = omnia_gpio_get_value, + .set_value = omnia_gpio_set_value, + .get_function = omnia_gpio_get_function, + .xlate = omnia_gpio_xlate, +}; + +static int omnia_gpio_probe(struct udevice *dev) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = "mcu_"; + + if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU)) + uc_priv->gpio_count = 16 + 32 + 16; + else if (info->features & FEAT_EXT_CMDS) + uc_priv->gpio_count = 16 + 32; + else + uc_priv->gpio_count = 16; + + return 0; +} + +U_BOOT_DRIVER(turris_omnia_mcu_gpio) = { + .name = "turris-omnia-mcu-gpio", + .id = UCLASS_GPIO, + .ops = &omnia_gpio_ops, + .probe = omnia_gpio_probe, +}; + +static int omnia_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct { + u16 magic; + u16 arg; + u32 csum; + } __packed args; + + if (type != SYSRESET_POWER_OFF) + return -EPROTONOSUPPORT; + + args.magic = CMD_POWER_OFF_MAGIC; + args.arg = CMD_POWER_OFF_POWERON_BUTTON; + args.csum = 0xba3b7212; + + return dm_i2c_write(dev->parent, CMD_POWER_OFF, (void *)&args, + sizeof(args)); +} + +static const struct sysreset_ops omnia_sysreset_ops = { + .request = omnia_sysreset_request, +}; + +U_BOOT_DRIVER(turris_omnia_mcu_sysreset) = { + .name = "turris-omnia-mcu-sysreset", + .id = UCLASS_SYSRESET, + .ops = &omnia_sysreset_ops, +}; + +static int omnia_rng_read(struct udevice *dev, void *data, size_t count) +{ + u8 buf[1 + CMD_TRNG_MAX_ENTROPY_LEN]; + size_t len; + int ret; + + while (count) { + ret = dm_i2c_read(dev->parent, CMD_TRNG_COLLECT_ENTROPY, buf, + sizeof(buf)); + if (ret) + return ret; + + len = min_t(size_t, buf[0], + min_t(size_t, CMD_TRNG_MAX_ENTROPY_LEN, count)); + + if (!len) { + /* wait 500ms (fail if interrupted), then try again */ + for (int i = 0; i < 5; ++i) { + mdelay(100); + if (ctrlc()) + return -EINTR; + } + continue; + } + + memcpy(data, &buf[1], len); + data += len; + count -= len; + } + + return 0; +} + +static const struct dm_rng_ops omnia_rng_ops = { + .read = omnia_rng_read, +}; + +U_BOOT_DRIVER(turris_omnia_mcu_trng) = { + .name = "turris-omnia-mcu-trng", + .id = UCLASS_RNG, + .ops = &omnia_rng_ops, +}; + +static int turris_omnia_mcu_bind(struct udevice *dev) +{ + /* bind MCU GPIOs as a child device */ + return device_bind_driver_to_node(dev, "turris-omnia-mcu-gpio", + "turris-omnia-mcu-gpio", + dev_ofnode(dev), NULL); +} + +static int turris_omnia_mcu_probe(struct udevice *dev) +{ + struct turris_omnia_mcu_info *info = dev_get_priv(dev); + u32 dword; + u16 word; + int ret; + + ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, (void *)&word, sizeof(word)); + if (ret < 0) { + printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n", + ret); + return ret; + } + + if (le16_to_cpu(word) & STS_FEATURES_SUPPORTED) { + /* try read 32-bit features */ + ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&dword, + sizeof(dword)); + if (ret < 0) { + /* try read 16-bit features */ + ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&word, + sizeof(word)); + if (ret < 0) { + printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n", + ret); + return ret; + } + + info->features = le16_to_cpu(word); + } else { + info->features = le32_to_cpu(dword); + if (info->features & FEAT_FROM_BIT_16_INVALID) + info->features &= GENMASK(15, 0); + } + } + + /* bind sysreset if poweroff is supported */ + if (info->features & FEAT_POWEROFF_WAKEUP) { + ret = device_bind_driver_to_node(dev, + "turris-omnia-mcu-sysreset", + "turris-omnia-mcu-sysreset", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + /* bind rng if trng is supported */ + if (info->features & FEAT_TRNG) { + ret = device_bind_driver_to_node(dev, "turris-omnia-mcu-trng", + "turris-omnia-mcu-trng", + dev_ofnode(dev), NULL); + if (ret < 0) + return ret; + } + + return 0; +} + +static const struct udevice_id turris_omnia_mcu_ids[] = { + { .compatible = "cznic,turris-omnia-mcu" }, + { } +}; + +U_BOOT_DRIVER(turris_omnia_mcu) = { + .name = "turris-omnia-mcu", + .id = UCLASS_MISC, + .bind = turris_omnia_mcu_bind, + .probe = turris_omnia_mcu_probe, + .priv_auto = sizeof(struct turris_omnia_mcu_info), + .of_match = turris_omnia_mcu_ids, +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index cef05790dd9..f7fe6d1042e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -568,6 +568,19 @@ config MMC_SDHCI_CADENCE If unsure, say N. +config MMC_SDHCI_CV1800B + bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller" + depends on BLK && DM_MMC + depends on MMC_SDHCI + depends on OF_CONTROL + help + This selects the CV1800B SD/SDIO/eMMC driver. + + If you have a controller with this interface, + say Y here. + + If unsure, say N. + config MMC_SDHCI_AM654 bool "SDHCI Controller on TI's Am654 devices" depends on ARCH_K3 diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e9cf1fcc640..3374321e290 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o +obj-$(CONFIG_MMC_SDHCI_CV1800B) += cv1800b_sdhci.o obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c new file mode 100644 index 00000000000..2275c537772 --- /dev/null +++ b/drivers/mmc/cv1800b_sdhci.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <dm.h> +#include <mmc.h> +#include <sdhci.h> +#include <linux/delay.h> + +#define SDHCI_PHY_TX_RX_DLY 0x240 +#define MMC_MAX_CLOCK 375000000 +#define TUNE_MAX_PHCODE 128 + +struct cv1800b_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap) +{ + sdhci_writel(host, tap << 16, SDHCI_PHY_TX_RX_DLY); +} + +static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) + udelay(10); +} + +static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct sdhci_host *host = dev_get_priv(mmc->dev); + + u16 tap; + + int current_size = 0; + int max_size = 0; + int max_window = 0; + + for (tap = 0; tap < TUNE_MAX_PHCODE; tap++) { + cv1800b_set_tap_delay(host, tap); + + if (mmc_send_tuning(host->mmc, opcode, NULL)) { + current_size = 0; + } else { + current_size++; + if (current_size > max_size) { + max_size = current_size; + max_window = tap; + } + } + } + + cv1800b_sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + cv1800b_set_tap_delay(host, max_window - max_size / 2); + + return 0; +} + +const struct sdhci_ops cv1800b_sdhci_sd_ops = { + .platform_execute_tuning = cv1800b_execute_tuning, +}; + +static int cv1800b_sdhci_bind(struct udevice *dev) +{ + struct cv1800b_sdhci_plat *plat = dev_get_plat(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static int cv1800b_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct cv1800b_sdhci_plat *plat = dev_get_plat(dev); + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + host->name = dev->name; + host->ioaddr = devfdt_get_addr_ptr(dev); + + upriv->mmc = &plat->mmc; + host->mmc = &plat->mmc; + host->mmc->priv = host; + host->mmc->dev = dev; + host->ops = &cv1800b_sdhci_sd_ops; + host->max_clk = MMC_MAX_CLOCK; + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 200000); + if (ret) + return ret; + + return sdhci_probe(dev); +} + +static const struct udevice_id cv1800b_sdhci_match[] = { + { .compatible = "sophgo,cv1800b-dwcmshc" }, + { } +}; + +U_BOOT_DRIVER(cv1800b_sdhci) = { + .name = "sdhci-cv1800b", + .id = UCLASS_MMC, + .of_match = cv1800b_sdhci_match, + .bind = cv1800b_sdhci_bind, + .probe = cv1800b_sdhci_probe, + .priv_auto = sizeof(struct sdhci_host), + .plat_auto = sizeof(struct cv1800b_sdhci_plat), + .ops = &sdhci_ops, +}; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bb9994b8626..9f3f1267cbd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -1,6 +1,6 @@ - menuconfig MTD_RAW_NAND bool "Raw NAND Device Support" + if MTD_RAW_NAND config SYS_NAND_SELF_INIT @@ -49,12 +49,12 @@ config SYS_NAND_NO_SUBPAGE_WRITE depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD config DM_NAND_ATMEL - bool "Support Atmel NAND controller with DM support" - select SYS_NAND_SELF_INIT - imply SYS_NAND_USE_FLASH_BBT - help - Enable this driver for NAND flash platforms using an Atmel NAND - controller. + bool "Support Atmel NAND controller with DM support" + select SYS_NAND_SELF_INIT + imply SYS_NAND_USE_FLASH_BBT + help + Enable this driver for NAND flash platforms using an Atmel NAND + controller. config NAND_ATMEL bool "Support Atmel NAND controller" @@ -133,35 +133,35 @@ config NAND_BRCMNAND_6753 Enable support for broadcom nand driver on bcm6753. config NAND_BRCMNAND_68360 - bool "Support Broadcom NAND controller on bcm68360" - depends on NAND_BRCMNAND && BCM6856 - help - Enable support for broadcom nand driver on bcm68360. + bool "Support Broadcom NAND controller on bcm68360" + depends on NAND_BRCMNAND && BCM6856 + help + Enable support for broadcom nand driver on bcm68360. config NAND_BRCMNAND_6838 - bool "Support Broadcom NAND controller on bcm6838" - depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 - help - Enable support for broadcom nand driver on bcm6838. + bool "Support Broadcom NAND controller on bcm6838" + depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 + help + Enable support for broadcom nand driver on bcm6838. config NAND_BRCMNAND_6858 - bool "Support Broadcom NAND controller on bcm6858" - depends on NAND_BRCMNAND && BCM6858 - help - Enable support for broadcom nand driver on bcm6858. + bool "Support Broadcom NAND controller on bcm6858" + depends on NAND_BRCMNAND && BCM6858 + help + Enable support for broadcom nand driver on bcm6858. config NAND_BRCMNAND_63158 - bool "Support Broadcom NAND controller on bcm63158" - depends on NAND_BRCMNAND && BCM63158 - help - Enable support for broadcom nand driver on bcm63158. + bool "Support Broadcom NAND controller on bcm63158" + depends on NAND_BRCMNAND && BCM63158 + help + Enable support for broadcom nand driver on bcm63158. config NAND_BRCMNAND_IPROC - bool "Support Broadcom NAND controller on the iproc family" - depends on NAND_BRCMNAND - help - Enable support for broadcom nand driver on the Broadcom - iproc family such as Northstar (BCM5301x, BCM4708...) + bool "Support Broadcom NAND controller on the iproc family" + depends on NAND_BRCMNAND + help + Enable support for broadcom nand driver on the Broadcom + iproc family such as Northstar (BCM5301x, BCM4708...) config NAND_DAVINCI bool "Support TI Davinci NAND controller" @@ -413,10 +413,10 @@ config NAND_VF610_NFC if NAND_VF610_NFC config NAND_VF610_NFC_DT - bool "Support Vybrid's vf610 NAND controller as a DT device" - depends on OF_CONTROL && DM_MTD - help - Enable the driver for Vybrid's vf610 NAND flash on platforms + bool "Support Vybrid's vf610 NAND controller as a DT device" + depends on OF_CONTROL && DM_MTD + help + Enable the driver for Vybrid's vf610 NAND flash on platforms using device tree. choice @@ -472,11 +472,11 @@ config NAND_SUNXI select SPL_NAND_SUPPORT select SPL_SYS_NAND_SELF_INIT imply CMD_NAND - ---help--- - Enable support for NAND. This option enables the standard and - SPL drivers. - The SPL driver only supports reading from the NAND using DMA - transfers. + help + Enable support for NAND. This option enables the standard and + SPL drivers. + The SPL driver only supports reading from the NAND using DMA + transfers. if NAND_SUNXI @@ -504,6 +504,15 @@ config NAND_ARASAN controller. This uses the hardware ECC for read and write operations. +config NAND_MESON + bool "Meson NAND support" + select SYS_NAND_SELF_INIT + depends on DM_MTD && ARCH_MESON + imply CMD_NAND + help + This enables Nand driver support for Meson raw NAND flash + controller. + config NAND_MXC bool "MXC NAND support" depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 @@ -577,16 +586,16 @@ config NAND_OCTEONTX select SYS_NAND_SELF_INIT imply CMD_NAND help - This enables Nand flash controller hardware found on the OcteonTX - processors. + This enables Nand flash controller hardware found on the OcteonTX + processors. config NAND_OCTEONTX_HW_ECC bool "Support Hardware ECC for OcteonTX NAND controller" depends on NAND_OCTEONTX default y help - This enables Hardware BCH engine found on the OcteonTX processors to - support ECC for NAND flash controller. + This enables Hardware BCH engine found on the OcteonTX processors to + support ECC for NAND flash controller. config NAND_STM32_FMC2 bool "Support for NAND controller on STM32MP SoCs" @@ -751,37 +760,37 @@ config SYS_NAND_BAD_BLOCK_POS config SYS_NAND_U_BOOT_LOCATIONS bool "Define U-Boot binaries locations in NAND" help - Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. - This option should not be enabled when compiling U-Boot for boards - defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h - file. + Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. + This option should not be enabled when compiling U-Boot for boards + defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h + file. config SYS_NAND_U_BOOT_OFFS hex "Location in NAND to read U-Boot from" default 0x800000 if NAND_SUNXI depends on SYS_NAND_U_BOOT_LOCATIONS help - Set the offset from the start of the nand where u-boot should be - loaded from. + Set the offset from the start of the nand where u-boot should be + loaded from. config SYS_NAND_U_BOOT_OFFS_REDUND hex "Location in NAND to read U-Boot from" default SYS_NAND_U_BOOT_OFFS depends on SYS_NAND_U_BOOT_LOCATIONS help - Set the offset from the start of the nand where the redundant u-boot - should be loaded from. + Set the offset from the start of the nand where the redundant u-boot + should be loaded from. config SPL_NAND_AM33XX_BCH bool "Enables SPL-NAND driver which supports ELM based" depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX default y - help + help Hardware ECC correction. This is useful for platforms which have ELM hardware engine and use NAND boot mode. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling - SPL-NAND driver with software ECC correction support. + SPL-NAND driver with software ECC correction support. config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" @@ -810,6 +819,6 @@ config SYS_NAND_HW_ECC_OOBFIRST bool "In SPL, read the OOB first and then the data from NAND" depends on SPL_NAND_SIMPLE -endif +endif # if SPL -endif # if NAND +endif # if MTD_RAW_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index ddbba899e58..46fead6fa48 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o +obj-$(CONFIG_NAND_MESON) += meson_nand.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 14766401bf6..ffcd963b3da 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1232,7 +1232,8 @@ static int arasan_probe(struct udevice *dev) struct nand_config *nand = &info->config; struct mtd_info *mtd; ofnode child; - int err = -1; + int ret; + const char *str; info->reg = dev_read_addr_ptr(dev); mtd = nand_to_mtd(nand_chip); @@ -1258,9 +1259,16 @@ static int arasan_probe(struct udevice *dev) writel(0x0, &info->reg->pgm_reg); /* first scan to find the device and get the page size */ - if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) { + ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); + if (ret) { printf("%s: nand_scan_ident failed\n", __func__); - goto fail; + return ret; + } + + str = ofnode_read_string(nand_chip->flash_node, "nand-ecc-mode"); + if (!str || strcmp(str, "hw") != 0) { + printf("%s ecc mode is not supported\n", str); + return -EINVAL; } nand_chip->ecc.mode = NAND_ECC_HW; @@ -1282,26 +1290,26 @@ static int arasan_probe(struct udevice *dev) nand_chip->ecc.bytes = 0; nand_chip->ecc.layout = &ondie_nand_oob_64; } else { - if (arasan_nand_ecc_init(mtd)) { + ret = arasan_nand_ecc_init(mtd); + if (ret) { printf("%s: nand_ecc_init failed\n", __func__); - goto fail; + return ret; } } - if (nand_scan_tail(mtd)) { + ret = nand_scan_tail(mtd); + if (ret) { printf("%s: nand_scan_tail failed\n", __func__); - goto fail; + return ret; } - if (nand_register(0, mtd)) { + ret = nand_register(0, mtd); + if (ret) { printf("Nand Register Fail\n"); - goto fail; + return ret; } - return 0; -fail: - free(nand); - return err; + return ret; } static const struct udevice_id arasan_nand_dt_ids[] = { diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 0e0441472b8..ee4ec6da587 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1267,7 +1267,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, return ret; /* - * The write cycle timing is directly matching tWC, but is also + * The read cycle timing is directly matching tRC, but is also * dependent on the setup and hold timings we calculated earlier, * which gives: * @@ -1429,8 +1429,6 @@ static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline, return nc->caps->ops->setup_data_interface(nand, csline, conf); } -#define NAND_KEEP_TIMINGS 0x00800000 - static void atmel_nand_init(struct atmel_nand_controller *nc, struct atmel_nand *nand) { diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c new file mode 100644 index 00000000000..12499a79478 --- /dev/null +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -0,0 +1,1247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson Nand Flash Controller Driver + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Liang Yang <liang.yang@amlogic.com> + * + * Copyright (c) 2023 SaluteDevices, Inc. + * Author: Arseniy Krasnov <avkrasnov@salutedevices.com> + */ + +#include <nand.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/ofnode.h> +#include <dm/uclass.h> +#include <linux/bug.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/iopoll.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> +#include <linux/sizes.h> + +#define NFC_CMD_IDLE (0xc << 14) +#define NFC_CMD_CLE (0x5 << 14) +#define NFC_CMD_ALE (0x6 << 14) +#define NFC_CMD_DWR (0x4 << 14) +#define NFC_CMD_DRD (0x8 << 14) +#define NFC_CMD_ADL ((0 << 16) | (3 << 20)) +#define NFC_CMD_ADH ((1 << 16) | (3 << 20)) +#define NFC_CMD_AIL ((2 << 16) | (3 << 20)) +#define NFC_CMD_AIH ((3 << 16) | (3 << 20)) +#define NFC_CMD_SEED ((8 << 16) | (3 << 20)) +#define NFC_CMD_M2N ((0 << 17) | (2 << 20)) +#define NFC_CMD_N2M ((1 << 17) | (2 << 20)) +#define NFC_CMD_RB BIT(20) +#define NFC_CMD_SCRAMBLER_ENABLE BIT(19) +#define NFC_CMD_SCRAMBLER_DISABLE 0 +#define NFC_CMD_SHORTMODE_DISABLE 0 +#define NFC_CMD_RB_INT BIT(14) +#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16)) + +#define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0)) + +#define NFC_REG_CMD 0x00 +#define NFC_REG_CFG 0x04 +#define NFC_REG_DADR 0x08 +#define NFC_REG_IADR 0x0c +#define NFC_REG_BUF 0x10 +#define NFC_REG_INFO 0x14 +#define NFC_REG_DC 0x18 +#define NFC_REG_ADR 0x1c +#define NFC_REG_DL 0x20 +#define NFC_REG_DH 0x24 +#define NFC_REG_CADR 0x28 +#define NFC_REG_SADR 0x2c +#define NFC_REG_PINS 0x30 +#define NFC_REG_VER 0x38 + +#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ + ( \ + (cmd_dir) | \ + (ran) | \ + ((bch) << 14) | \ + ((short_mode) << 13) | \ + (((page_size) & 0x7f) << 6) | \ + ((pages) & 0x3f) \ + ) + +#define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff)) +#define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff)) +#define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff)) +#define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff)) + +#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N) + +#define ECC_CHECK_RETURN_FF -1 + +#define NAND_CE0 (0xe << 10) +#define NAND_CE1 (0xd << 10) + +#define DMA_BUSY_TIMEOUT_US 1000000 +#define CMD_DRAIN_TIMEOUT_US 1000 +#define ECC_POLL_TIMEOUT_US 15 + +#define MAX_CE_NUM 2 + +/* eMMC clock register, misc control */ +#define CLK_SELECT_NAND BIT(31) +#define CLK_ALWAYS_ON_NAND BIT(24) +#define CLK_ENABLE_VALUE 0x245 + +#define DIRREAD 1 +#define DIRWRITE 0 + +#define ECC_PARITY_BCH8_512B 14 +#define ECC_COMPLETE BIT(31) +#define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0)) +#define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0)) +#define ECC_UNCORRECTABLE 0x3f + +#define PER_INFO_BYTE 8 + +#define NFC_SEND_CMD(host, cmd) \ + (writel((cmd), (host)->reg_base + NFC_REG_CMD)) + +#define NFC_GET_CMD(host) \ + (readl((host)->reg_base + NFC_REG_CMD)) + +#define NFC_CMDFIFO_SIZE(host) ((NFC_GET_CMD((host)) >> 22) & GENMASK(4, 0)) + +#define NFC_CMD_MAKE_IDLE(ce, delay) ((ce) | NFC_CMD_IDLE | ((delay) & 0x3ff)) +#define NFC_CMD_MAKE_DRD(ce, size) ((ce) | NFC_CMD_DRD | (size)) +#define NFC_CMD_MAKE_DWR(ce, data) ((ce) | NFC_CMD_DWR | ((data) & 0xff)) +#define NFC_CMD_MAKE_CLE(ce, cmd_val) ((ce) | NFC_CMD_CLE | ((cmd_val) & 0xff)) +#define NFC_CMD_MAKE_ALE(ce, addr) ((ce) | NFC_CMD_ALE | ((addr) & 0xff)) + +#define NAND_TWB_TIME_CYCLE 10 + +#define NFC_DEV_READY_TICK_MAX 5000 + +/* Both values are recommended by vendor, as the most + * tested with almost all SLC NAND flash. Second value + * could be calculated dynamically from timing parameters, + * but we need both values for initial start of the NAND + * controller (e.g. before NAND subsystem processes timings), + * so use hardcoded constants. + */ +#define NFC_DEFAULT_BUS_CYCLE 6 +#define NFC_DEFAULT_BUS_TIMING 7 + +#define NFC_SEED_OFFSET 0xc2 +#define NFC_SEED_MASK 0x7fff + +#define DMA_ADDR_ALIGN 8 + +struct meson_nfc_nand_chip { + struct list_head node; + struct nand_chip nand; + + u32 bch_mode; + u8 *data_buf; + __le64 *info_buf; + u32 nsels; + u8 sels[]; +}; + +struct meson_nfc_param { + u32 chip_select; + u32 rb_select; +}; + +struct meson_nfc { + void __iomem *reg_base; + void __iomem *reg_clk; + struct list_head chips; + struct meson_nfc_param param; + struct udevice *dev; + dma_addr_t daddr; + dma_addr_t iaddr; + u32 data_bytes; + u32 info_bytes; + u64 assigned_cs; +}; + +struct meson_nand_ecc { + u32 bch; + u32 strength; + u32 size; +}; + +enum { + NFC_ECC_BCH8_512 = 1, + NFC_ECC_BCH8_1K, + NFC_ECC_BCH24_1K, + NFC_ECC_BCH30_1K, + NFC_ECC_BCH40_1K, + NFC_ECC_BCH50_1K, + NFC_ECC_BCH60_1K, +}; + +#define MESON_ECC_DATA(b, s, sz) { .bch = (b), .strength = (s), .size = (sz) } + +static struct meson_nand_ecc meson_ecc[] = { + MESON_ECC_DATA(NFC_ECC_BCH8_512, 8, 512), + MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8, 1024), +}; + +static int meson_nand_calc_ecc_bytes(int step_size, int strength) +{ + int ecc_bytes; + + if (step_size == 512 && strength == 8) + return ECC_PARITY_BCH8_512B; + + ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8); + ecc_bytes = ALIGN(ecc_bytes, 2); + + return ecc_bytes; +} + +static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) +{ + return container_of(nand, struct meson_nfc_nand_chip, nand); +} + +static void meson_nfc_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + struct meson_nfc *nfc = nand_get_controller_data(nand); + + nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0; +} + +static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time) +{ + writel(NFC_CMD_MAKE_IDLE(nfc->param.chip_select, time), + nfc->reg_base + NFC_REG_CMD); +} + +static void meson_nfc_cmd_seed(const struct meson_nfc *nfc, u32 seed) +{ + writel(NFC_CMD_SEED | (NFC_SEED_OFFSET + (seed & NFC_SEED_MASK)), + nfc->reg_base + NFC_REG_CMD); +} + +static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir, + int scrambler) +{ + struct mtd_info *mtd = nand_to_mtd(nand); + const struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + u32 bch = meson_chip->bch_mode, cmd; + int len = mtd->writesize, pagesize, pages; + + pagesize = nand->ecc.size; + + if (raw) { + len = mtd->writesize + mtd->oobsize; + cmd = len | scrambler | DMA_DIR(dir); + writel(cmd, nfc->reg_base + NFC_REG_CMD); + return; + } + + pages = len / nand->ecc.size; + + cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch, + NFC_CMD_SHORTMODE_DISABLE, pagesize, pages); + + writel(cmd, nfc->reg_base + NFC_REG_CMD); +} + +static void meson_nfc_drain_cmd(struct meson_nfc *nfc) +{ + /* + * Insert two commands to make sure all valid commands are finished. + * + * The Nand flash controller is designed as two stages pipleline - + * a) fetch and b) execute. + * There might be cases when the driver see command queue is empty, + * but the Nand flash controller still has two commands buffered, + * one is fetched into NFC request queue (ready to run), and another + * is actively executing. So pushing 2 "IDLE" commands guarantees that + * the pipeline is emptied. + */ + meson_nfc_cmd_idle(nfc, 0); + meson_nfc_cmd_idle(nfc, 0); +} + +static int meson_nfc_wait_cmd_finish(const struct meson_nfc *nfc, + unsigned int timeout_us) +{ + u32 cmd_size = 0; + + /* wait cmd fifo is empty */ + return readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size, + !NFC_CMD_GET_SIZE(cmd_size), + timeout_us); +} + +static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc) +{ + meson_nfc_drain_cmd(nfc); + + return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT_US); +} + +static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i) +{ + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + int len; + + len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i; + + return meson_chip->data_buf + len; +} + +static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i) +{ + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + int len, temp; + + temp = nand->ecc.size + nand->ecc.bytes; + len = (temp + 2) * i; + + return meson_chip->data_buf + len; +} + +static void meson_nfc_get_data_oob(struct nand_chip *nand, + u8 *buf, u8 *oobbuf) +{ + u8 *dsrc, *osrc; + int i, oob_len; + + oob_len = nand->ecc.bytes + 2; + for (i = 0; i < nand->ecc.steps; i++) { + if (buf) { + dsrc = meson_nfc_data_ptr(nand, i); + memcpy(buf, dsrc, nand->ecc.size); + buf += nand->ecc.size; + } + + if (oobbuf) { + osrc = meson_nfc_oob_ptr(nand, i); + memcpy(oobbuf, osrc, oob_len); + oobbuf += oob_len; + } + } +} + +static void meson_nfc_set_data_oob(struct nand_chip *nand, + const u8 *buf, u8 *oobbuf) +{ + int i, oob_len; + + oob_len = nand->ecc.bytes + 2; + for (i = 0; i < nand->ecc.steps; i++) { + u8 *osrc; + + if (buf) { + u8 *dsrc; + + dsrc = meson_nfc_data_ptr(nand, i); + memcpy(dsrc, buf, nand->ecc.size); + buf += nand->ecc.size; + } + + osrc = meson_nfc_oob_ptr(nand, i); + memcpy(osrc, oobbuf, oob_len); + oobbuf += oob_len; + } +} + +static void meson_nfc_set_user_byte(struct nand_chip *nand, const u8 *oob_buf) +{ + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + int i, count; + + for (i = 0, count = 0; i < nand->ecc.steps; i++, count += (2 + nand->ecc.bytes)) { + __le64 *info = &meson_chip->info_buf[i]; + + *info |= oob_buf[count]; + *info |= oob_buf[count + 1] << 8; + } +} + +static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf) +{ + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + int i, count; + + for (i = 0, count = 0; i < nand->ecc.steps; i++, count += (2 + nand->ecc.bytes)) { + const __le64 *info = &meson_chip->info_buf[i]; + + oob_buf[count] = *info; + oob_buf[count + 1] = *info >> 8; + } +} + +static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips, + u64 *correct_bitmap) +{ + struct mtd_info *mtd = nand_to_mtd(nand); + int ret = 0, i; + + for (i = 0; i < nand->ecc.steps; i++) { + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + const __le64 *info = &meson_chip->info_buf[i]; + + if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) { + mtd->ecc_stats.corrected += ECC_ERR_CNT(*info); + *bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info)); + *correct_bitmap |= BIT_ULL(i); + continue; + } + + if ((nand->options & NAND_NEED_SCRAMBLING) && + ECC_ZERO_CNT(*info) < nand->ecc.strength) { + mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info); + *bitflips = max_t(u32, *bitflips, + ECC_ZERO_CNT(*info)); + ret = ECC_CHECK_RETURN_FF; + } else { + ret = -EBADMSG; + } + } + + return ret; +} + +static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, void *databuf, + int datalen, void *infobuf, int infolen, + enum dma_data_direction dir) +{ + struct meson_nfc *nfc = nand_get_controller_data(nand); + int ret; + u32 cmd; + + nfc->daddr = dma_map_single(databuf, datalen, DMA_BIDIRECTIONAL); + ret = dma_mapping_error(nfc->dev, nfc->daddr); + if (ret) + return ret; + + cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr); + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr); + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + if (infobuf) { + nfc->iaddr = dma_map_single(infobuf, infolen, + DMA_BIDIRECTIONAL); + ret = dma_mapping_error(nfc->dev, nfc->iaddr); + if (ret) { + dma_unmap_single(nfc->daddr, datalen, dir); + return ret; + } + + nfc->info_bytes = infolen; + cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr); + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr); + writel(cmd, nfc->reg_base + NFC_REG_CMD); + } + + return 0; +} + +static void meson_nfc_dma_buffer_release(struct nand_chip *nand, + int datalen, int infolen, + enum dma_data_direction dir) +{ + struct meson_nfc *nfc = nand_get_controller_data(nand); + + dma_unmap_single(nfc->daddr, datalen, dir); + + if (infolen) { + dma_unmap_single(nfc->iaddr, infolen, dir); + nfc->info_bytes = 0; + } +} + +static void meson_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int size) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc *nfc = nand_get_controller_data(nand); + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + u8 *dma_buf; + int ret; + u32 cmd; + + if ((uintptr_t)buf % DMA_ADDR_ALIGN) { + unsigned long tmp_addr; + + dma_buf = dma_alloc_coherent(size, &tmp_addr); + if (!dma_buf) + return; + } else { + dma_buf = buf; + } + + ret = meson_nfc_dma_buffer_setup(nand, dma_buf, size, meson_chip->info_buf, + PER_INFO_BYTE, DMA_FROM_DEVICE); + if (ret) { + pr_err("Failed to setup DMA buffer %p/%p\n", dma_buf, + meson_chip->info_buf); + return; + } + + cmd = NFC_CMD_N2M | size; + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + meson_nfc_drain_cmd(nfc); + meson_nfc_wait_cmd_finish(nfc, CMD_DRAIN_TIMEOUT_US); + meson_nfc_dma_buffer_release(nand, size, PER_INFO_BYTE, DMA_FROM_DEVICE); + + if (buf != dma_buf) { + memcpy(buf, dma_buf, size); + dma_free_coherent(dma_buf); + } +} + +static void meson_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int size) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc *nfc = nand_get_controller_data(nand); + u8 *dma_buf; + int ret; + u32 cmd; + + if ((uintptr_t)buf % DMA_ADDR_ALIGN) { + unsigned long tmp_addr; + + dma_buf = dma_alloc_coherent(size, &tmp_addr); + if (!dma_buf) + return; + + memcpy(dma_buf, buf, size); + } else { + dma_buf = (u8 *)buf; + } + + ret = meson_nfc_dma_buffer_setup(nand, (void *)dma_buf, size, NULL, + 0, DMA_TO_DEVICE); + if (ret) { + pr_err("Failed to setup DMA buffer %p\n", dma_buf); + return; + } + + cmd = NFC_CMD_M2N | size; + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + meson_nfc_drain_cmd(nfc); + meson_nfc_wait_cmd_finish(nfc, CMD_DRAIN_TIMEOUT_US); + meson_nfc_dma_buffer_release(nand, size, 0, DMA_TO_DEVICE); + + if (buf != dma_buf) + dma_free_coherent(dma_buf); +} + +static int meson_nfc_write_page_sub(struct nand_chip *nand, + int page, bool raw) +{ + const struct mtd_info *mtd = nand_to_mtd(nand); + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + struct meson_nfc *nfc = nand_get_controller_data(nand); + int data_len, info_len; + int ret; + u32 cmd; + + data_len = mtd->writesize + mtd->oobsize; + info_len = nand->ecc.steps * PER_INFO_BYTE; + + ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, + data_len, meson_chip->info_buf, + info_len, DMA_TO_DEVICE); + if (ret) { + pr_err("Failed to setup DMA buffer %p/%p\n", + meson_chip->data_buf, meson_chip->info_buf); + return ret; + } + + if (nand->options & NAND_NEED_SCRAMBLING) { + meson_nfc_cmd_seed(nfc, page); + meson_nfc_cmd_access(nand, raw, DIRWRITE, + NFC_CMD_SCRAMBLER_ENABLE); + } else { + meson_nfc_cmd_access(nand, raw, DIRWRITE, + NFC_CMD_SCRAMBLER_DISABLE); + } + + cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG; + writel(cmd, nfc->reg_base + NFC_REG_CMD); + + meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE); + + return 0; +} + +static int meson_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + meson_nfc_set_data_oob(chip, buf, oob_required ? chip->oob_poi : NULL); + + return meson_nfc_write_page_sub(chip, page, true); +} + +static int meson_nfc_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, int page) +{ + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(chip); + + if (buf) + memcpy(meson_chip->data_buf, buf, mtd->writesize); + + memset(meson_chip->info_buf, 0, chip->ecc.steps * PER_INFO_BYTE); + + if (oob_required) + meson_nfc_set_user_byte(chip, chip->oob_poi); + + return meson_nfc_write_page_sub(chip, page, false); +} + +static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc, + struct nand_chip *nand, bool raw) +{ + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + __le64 *info; + u32 neccpages; + int ret; + + neccpages = raw ? 1 : nand->ecc.steps; + info = &meson_chip->info_buf[neccpages - 1]; + do { + udelay(ECC_POLL_TIMEOUT_US); + /* info is updated by nfc dma engine*/ + rmb(); + invalidate_dcache_range(nfc->iaddr, nfc->iaddr + nfc->info_bytes); + ret = *info & ECC_COMPLETE; + } while (!ret); +} + +static int meson_nfc_read_page_sub(struct nand_chip *nand, + int page, bool raw) +{ + struct mtd_info *mtd = nand_to_mtd(nand); + struct meson_nfc *nfc = nand_get_controller_data(nand); + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + u32 data_len, info_len; + int ret; + + data_len = mtd->writesize + mtd->oobsize; + info_len = nand->ecc.steps * PER_INFO_BYTE; + + ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf, data_len, + meson_chip->info_buf, info_len, + DMA_FROM_DEVICE); + if (ret) + return ret; + + if (nand->options & NAND_NEED_SCRAMBLING) { + meson_nfc_cmd_seed(nfc, page); + meson_nfc_cmd_access(nand, raw, DIRREAD, + NFC_CMD_SCRAMBLER_ENABLE); + } else { + meson_nfc_cmd_access(nand, raw, DIRREAD, + NFC_CMD_SCRAMBLER_DISABLE); + } + + meson_nfc_wait_dma_finish(nfc); + meson_nfc_check_ecc_pages_valid(nfc, nand, raw); + + meson_nfc_dma_buffer_release(nand, data_len, info_len, + DMA_FROM_DEVICE); + + return 0; +} + +static int meson_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + int ret; + + ret = meson_nfc_read_page_sub(chip, page, true); + if (ret) + return ret; + + meson_nfc_get_data_oob(chip, buf, oob_required ? chip->oob_poi : NULL); + + return 0; +} + +static int meson_nfc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(chip); + u64 correct_bitmap = 0; + u32 bitflips = 0; + int ret; + + ret = meson_nfc_read_page_sub(chip, page, false); + if (ret) + return ret; + + if (oob_required) + meson_nfc_get_user_byte(chip, chip->oob_poi); + + ret = meson_nfc_ecc_correct(chip, &bitflips, &correct_bitmap); + + if (ret == ECC_CHECK_RETURN_FF) { + if (buf) + memset(buf, 0xff, mtd->writesize); + + if (oob_required) + memset(chip->oob_poi, 0xff, mtd->oobsize); + } else if (ret < 0) { + struct nand_ecc_ctrl *ecc; + int i; + + if ((chip->options & NAND_NEED_SCRAMBLING) || !buf) { + mtd->ecc_stats.failed++; + return bitflips; + } + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + ret = meson_nfc_read_page_raw(mtd, chip, buf, 1, page); + if (ret) + return ret; + + ecc = &chip->ecc; + + for (i = 0; i < chip->ecc.steps ; i++) { + u8 *data = buf + i * ecc->size; + u8 *oob = chip->oob_poi + i * (ecc->bytes + 2); + + if (correct_bitmap & BIT_ULL(i)) + continue; + + ret = nand_check_erased_ecc_chunk(data, ecc->size, + oob, ecc->bytes + 2, + NULL, 0, + ecc->strength); + if (ret < 0) { + mtd->ecc_stats.failed++; + } else { + mtd->ecc_stats.corrected += ret; + bitflips = max_t(u32, bitflips, ret); + } + } + } else if (buf && buf != meson_chip->data_buf) { + memcpy(buf, meson_chip->data_buf, mtd->writesize); + } + + return bitflips; +} + +static int meson_nfc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int ret; + + ret = nand_read_page_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + return meson_nfc_read_page_raw(mtd, chip, NULL, 1, page); +} + +static int meson_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int ret; + + ret = nand_read_page_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + return meson_nfc_read_page_hwecc(mtd, chip, NULL, 1, page); +} + +static int meson_nfc_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int ret; + + ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + ret = meson_nfc_write_page_raw(mtd, chip, NULL, 1, page); + if (ret) + return ret; + + return nand_prog_page_end_op(chip); +} + +static int meson_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int ret; + + ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); + if (ret) + return ret; + + ret = meson_nfc_write_page_hwecc(mtd, chip, NULL, 1, page); + if (ret) + return ret; + + return nand_prog_page_end_op(chip); +} + +static void meson_nfc_nand_cmd_function(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + + chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + + if (column != -1 || page_addr != -1) { + int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (chip->options & NAND_BUSWIDTH_16 && + !nand_opcode_8bits(command)) + column >>= 1; + + chip->cmd_ctrl(mtd, column, ctrl); + ctrl &= ~NAND_CTRL_CHANGE; + /* Only output a single addr cycle for 8bits + * opcodes. + */ + if (!nand_opcode_8bits(command)) + chip->cmd_ctrl(mtd, column >> 8, ctrl); + } + + if (page_addr != -1) { + chip->cmd_ctrl(mtd, page_addr, ctrl); + chip->cmd_ctrl(mtd, page_addr >> 8, NAND_NCE | + NAND_ALE); + /* One more address cycle for devices > 128MiB */ + if (chip->chipsize > SZ_128M) + chip->cmd_ctrl(mtd, page_addr >> 16, + NAND_NCE | NAND_ALE); + } + + switch (command) { + case NAND_CMD_READ0: + chip->cmd_ctrl(mtd, NAND_CMD_READSTART, + NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + fallthrough; + case NAND_CMD_PARAM: + nand_wait_ready(mtd); + nand_exit_status_op(chip); + } + } +} + +static void meson_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc *nfc = nand_get_controller_data(nand); + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + cmd = NFC_CMD_MAKE_CLE(nfc->param.chip_select, cmd); + else + cmd = NFC_CMD_MAKE_ALE(nfc->param.chip_select, cmd); + + writel(cmd, nfc->reg_base + NFC_REG_CMD); +} + +static void meson_nfc_wait_cmd_fifo(struct meson_nfc *nfc) +{ + while ((NFC_GET_CMD(nfc) >> 22) & GENMASK(4, 0)) + ; +} + +static u8 meson_nfc_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc *nfc = nand_get_controller_data(nand); + + writel(NFC_CMD_MAKE_DRD(nfc->param.chip_select, 0), nfc->reg_base + NFC_REG_CMD); + + meson_nfc_cmd_idle(nfc, NAND_TWB_TIME_CYCLE); + meson_nfc_cmd_idle(nfc, 0); + meson_nfc_cmd_idle(nfc, 0); + + meson_nfc_wait_cmd_fifo(nfc); + + return readl(nfc->reg_base + NFC_REG_BUF); +} + +static void meson_nfc_nand_write_byte(struct mtd_info *mtd, u8 val) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct meson_nfc *nfc = nand_get_controller_data(nand); + + meson_nfc_cmd_idle(nfc, NAND_TWB_TIME_CYCLE); + + writel(NFC_CMD_MAKE_DWR(nfc->param.chip_select, val), nfc->reg_base + NFC_REG_CMD); + + meson_nfc_cmd_idle(nfc, NAND_TWB_TIME_CYCLE); + meson_nfc_cmd_idle(nfc, 0); + meson_nfc_cmd_idle(nfc, 0); + + meson_nfc_wait_cmd_fifo(nfc); +} + +static int meson_nfc_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + unsigned int time_out_cnt = 0; + + chip->select_chip(mtd, 0); + + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + + do { + int status; + + status = (int)chip->read_byte(mtd); + if (status & NAND_STATUS_READY) + break; + } while (time_out_cnt++ < NFC_DEV_READY_TICK_MAX); + + return time_out_cnt != NFC_DEV_READY_TICK_MAX; +} + +static int meson_chip_buffer_init(struct nand_chip *nand) +{ + const struct mtd_info *mtd = nand_to_mtd(nand); + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + u32 page_bytes, info_bytes, nsectors; + unsigned long tmp_addr; + + nsectors = mtd->writesize / nand->ecc.size; + + page_bytes = mtd->writesize + mtd->oobsize; + info_bytes = nsectors * PER_INFO_BYTE; + + meson_chip->data_buf = dma_alloc_coherent(page_bytes, &tmp_addr); + if (!meson_chip->data_buf) + return -ENOMEM; + + meson_chip->info_buf = dma_alloc_coherent(info_bytes, &tmp_addr); + if (!meson_chip->info_buf) { + dma_free_coherent(meson_chip->data_buf); + return -ENOMEM; + } + + return 0; +} + +static const int axg_stepinfo_strengths[] = { 8 }; +static const struct nand_ecc_step_info axg_stepinfo_1024 = { + .stepsize = 1024, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) +}; + +static const struct nand_ecc_step_info axg_stepinfo_512 = { + .stepsize = 512, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) +}; + +static const struct nand_ecc_step_info axg_stepinfo[] = { axg_stepinfo_1024, axg_stepinfo_512 }; + +static const struct nand_ecc_caps meson_axg_ecc_caps = { + .stepinfos = axg_stepinfo, + .nstepinfos = ARRAY_SIZE(axg_stepinfo), + .calc_ecc_bytes = meson_nand_calc_ecc_bytes, +}; + +/* + * OOB layout: + * + * For ECC with 512 bytes step size: + * 0x00: AA AA BB BB BB BB BB BB BB BB BB BB BB BB BB BB + * 0x10: AA AA CC CC CC CC CC CC CC CC CC CC CC CC CC CC + * 0x20: + * 0x30: + * + * For ECC with 1024 bytes step size: + * 0x00: AA AA BB BB BB BB BB BB BB BB BB BB BB BB BB BB + * 0x10: AA AA CC CC CC CC CC CC CC CC CC CC CC CC CC CC + * 0x20: AA AA DD DD DD DD DD DD DD DD DD DD DD DD DD DD + * 0x30: AA AA EE EE EE EE EE EE EE EE EE EE EE EE EE EE + * + * AA - user bytes. + * BB, CC, DD, EE - ECC code bytes for each step. + */ +static struct nand_ecclayout nand_oob; + +static void meson_nfc_init_nand_oob(struct nand_chip *nand) +{ + int section_size = 2 + nand->ecc.bytes; + int i; + int k; + + nand_oob.eccbytes = nand->ecc.steps * nand->ecc.bytes; + k = 0; + + for (i = 0; i < nand->ecc.steps; i++) { + int j; + + for (j = 0; j < nand->ecc.bytes; j++) + nand_oob.eccpos[k++] = (i * section_size) + 2 + j; + + nand_oob.oobfree[i].offset = (i * section_size); + nand_oob.oobfree[i].length = 2; + } + + nand_oob.oobavail = 2 * nand->ecc.steps; + nand->ecc.layout = &nand_oob; +} + +static int meson_nfc_init_ecc(struct nand_chip *nand, ofnode node) +{ + const struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + int i; + + ret = nand_check_ecc_caps(nand, &meson_axg_ecc_caps, mtd->oobsize - 2); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) { + if (meson_ecc[i].strength == nand->ecc.strength && + meson_ecc[i].size == nand->ecc.size) { + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); + + nand->ecc.steps = mtd->writesize / nand->ecc.size; + meson_chip->bch_mode = meson_ecc[i].bch; + + meson_nfc_init_nand_oob(nand); + + return 0; + } + } + + return -EINVAL; +} + +static int meson_nfc_nand_chip_init(struct udevice *dev, struct meson_nfc *nfc, + ofnode node) +{ + struct meson_nfc_nand_chip *meson_chip; + struct nand_chip *nand; + struct mtd_info *mtd; + u32 cs[MAX_CE_NUM]; + u32 nsels; + int ret; + int i; + + if (!ofnode_get_property(node, "reg", &nsels)) { + dev_err(dev, "\"reg\" property is not found\n"); + return -ENODEV; + } + + nsels /= sizeof(u32); + if (nsels >= MAX_CE_NUM) { + dev_err(dev, "invalid size of CS array, max is %d\n", + MAX_CE_NUM); + return -EINVAL; + } + + ret = ofnode_read_u32_array(node, "reg", cs, nsels); + if (ret < 0) { + dev_err(dev, "failed to read \"reg\" property\n"); + return ret; + } + + for (i = 0; i < nsels; i++) { + if (test_and_set_bit(cs[i], &nfc->assigned_cs)) { + dev_err(dev, "CS %d already assigned\n", cs[i]); + return -EINVAL; + } + } + + meson_chip = malloc(sizeof(*meson_chip) + nsels * sizeof(meson_chip->sels[0])); + if (!meson_chip) { + dev_err(dev, "failed to allocate memory for chip\n"); + return -ENOMEM; + } + + meson_chip->nsels = nsels; + nand = &meson_chip->nand; + + nand->flash_node = node; + nand_set_controller_data(nand, nfc); + /* Set the driver entry points for MTD */ + nand->cmdfunc = meson_nfc_nand_cmd_function; + nand->cmd_ctrl = meson_nfc_cmd_ctrl; + nand->select_chip = meson_nfc_nand_select_chip; + nand->read_byte = meson_nfc_nand_read_byte; + nand->write_byte = meson_nfc_nand_write_byte; + nand->dev_ready = meson_nfc_dev_ready; + + /* Buffer read/write routines */ + nand->read_buf = meson_nfc_read_buf; + nand->write_buf = meson_nfc_write_buf; + nand->options |= NAND_NO_SUBPAGE_WRITE; + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.hwctl = NULL; + nand->ecc.read_page = meson_nfc_read_page_hwecc; + nand->ecc.write_page = meson_nfc_write_page_hwecc; + nand->ecc.read_page_raw = meson_nfc_read_page_raw; + nand->ecc.write_page_raw = meson_nfc_write_page_raw; + + nand->ecc.read_oob = meson_nfc_read_oob; + nand->ecc.write_oob = meson_nfc_write_oob; + nand->ecc.read_oob_raw = meson_nfc_read_oob_raw; + nand->ecc.write_oob_raw = meson_nfc_write_oob_raw; + + nand->ecc.algo = NAND_ECC_BCH; + + mtd = nand_to_mtd(nand); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(dev, "'nand_scan_ident()' failed: %d\n", ret); + goto err_chip_free; + } + + ret = meson_nfc_init_ecc(nand, node); + if (ret) { + dev_err(dev, "failed to init ECC settings: %d\n", ret); + goto err_chip_free; + } + + ret = meson_chip_buffer_init(nand); + if (ret) { + dev_err(dev, "failed to init DMA buffers: %d\n", ret); + goto err_chip_free; + } + + /* 'nand_scan_tail()' needs ECC parameters to be already + * set and correct. + */ + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(dev, "'nand_scan_tail()' failed: %d\n", ret); + goto err_chip_buf_free; + } + + ret = nand_register(0, mtd); + if (ret) { + dev_err(dev, "'nand_register()' failed: %d\n", ret); + goto err_chip_buf_free; + } + + list_add_tail(&meson_chip->node, &nfc->chips); + + return 0; + +err_chip_buf_free: + dma_free_coherent(meson_chip->info_buf); + dma_free_coherent(meson_chip->data_buf); + +err_chip_free: + free(meson_chip); + + return ret; +} + +static int meson_nfc_nand_chips_init(struct udevice *dev, + struct meson_nfc *nfc) +{ + ofnode parent = dev_ofnode(dev); + ofnode node; + + ofnode_for_each_subnode(node, parent) { + int ret = meson_nfc_nand_chip_init(dev, nfc, node); + + if (ret) + return ret; + } + + return 0; +} + +static void meson_nfc_clk_init(struct meson_nfc *nfc) +{ + u32 bus_cycle = NFC_DEFAULT_BUS_CYCLE; + u32 bus_timing = NFC_DEFAULT_BUS_TIMING; + u32 bus_cfg_val; + + writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_ENABLE_VALUE, nfc->reg_clk); + writel(0, nfc->reg_base + NFC_REG_CFG); + + bus_cfg_val = (((bus_cycle - 1) & 31) | ((bus_timing & 31) << 5)); + writel(bus_cfg_val, nfc->reg_base + NFC_REG_CFG); + writel(BIT(31), nfc->reg_base + NFC_REG_CMD); +} + +static int meson_probe(struct udevice *dev) +{ + struct meson_nfc *nfc = dev_get_priv(dev); + void *addr; + int ret; + + addr = dev_read_addr_ptr(dev); + if (!addr) { + dev_err(dev, "base register address not found\n"); + return -EINVAL; + } + + nfc->reg_base = addr; + + addr = dev_read_addr_index_ptr(dev, 1); + if (!addr) { + dev_err(dev, "clk register address not found\n"); + return -EINVAL; + } + + nfc->reg_clk = addr; + nfc->dev = dev; + + meson_nfc_clk_init(nfc); + + ret = meson_nfc_nand_chips_init(dev, nfc); + if (ret) { + dev_err(nfc->dev, "failed to init chips\n"); + return ret; + } + + return 0; +} + +static const struct udevice_id meson_nand_dt_ids[] = { + {.compatible = "amlogic,meson-axg-nfc",}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_nand) = { + .name = "meson_nand", + .id = UCLASS_MTD, + .of_match = meson_nand_dt_ids, + .probe = meson_probe, + .priv_auto = sizeof(struct meson_nfc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(meson_nand), &dev); + + if (ret && ret != -ENODEV) + pr_err("Failed to initialize: %d\n", ret); +} diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c40a0f23d7b..688d17ba3c2 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4118,7 +4118,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) */ void nand_decode_ext_id(struct nand_chip *chip) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); @@ -4185,7 +4185,7 @@ static int nand_manufacturer_init(struct nand_chip *chip) */ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4265,7 +4265,7 @@ static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) int nand_detect(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) { - struct mtd_info *mtd = &chip->mtd; + struct mtd_info *mtd = nand_to_mtd(chip); const struct nand_manufacturer *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index f172f4787f8..65b836b34ca 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o -spinand-objs += toshiba.o winbond.o +spinand-objs += toshiba.o winbond.o xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8ca33459f96..62c28aa422d 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -829,6 +829,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, &esmt_c8_spinand_manufacturer, + &xtx_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c new file mode 100644 index 00000000000..aee1849a71f --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: + * Felix Matouschek <felix@matouschek.org> + */ + +#include <linux/bitfield.h> +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_XTX 0x0B + +#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2) +#define XT26G0XA_STATUS_ECC_NO_DETECTED (0 << 2) +#define XT26G0XA_STATUS_ECC_8_CORRECTED (3 << 4) +#define XT26G0XA_STATUS_ECC_UNCOR_ERROR (2 << 4) + +#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6) +#define XT26XXXD_STATUS_ECC_NO_DETECTED (0) +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1) +#define XT26XXXD_STATUS_ECC_8_CORRECTED (3) +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 48; + region->length = 16; + + return 0; +} + +static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 1; + region->length = 47; + + return 0; +} + +static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = { + .ecc = xt26g0xa_ooblayout_ecc, + .rfree = xt26g0xa_ooblayout_free, +}; + +static int xt26g0xa_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + status = status & XT26G0XA_STATUS_ECC_MASK; + + switch (status) { + case XT26G0XA_STATUS_ECC_NO_DETECTED: + return 0; + case XT26G0XA_STATUS_ECC_8_CORRECTED: + return 8; + case XT26G0XA_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + default: + break; + } + + /* At this point values greater than (2 << 4) are invalid */ + if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR) + return -EINVAL; + + /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ + return status >> 2; +} + +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = { + .ecc = xt26xxxd_ooblayout_ecc, + .rfree = xt26xxxd_ooblayout_free, +}; + +static int xt26xxxd_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (FIELD_GET(STATUS_ECC_MASK, status)) { + case XT26XXXD_STATUS_ECC_NO_DETECTED: + return 0; + case XT26XXXD_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + case XT26XXXD_STATUS_ECC_1_7_CORRECTED: + return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status); + case XT26XXXD_STATUS_ECC_8_CORRECTED: + return 8; + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info xtx_spinand_table[] = { + SPINAND_INFO("XT26G01A", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g0xa_ooblayout, + xt26g0xa_ecc_get_status)), + SPINAND_INFO("XT26G02A", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g0xa_ooblayout, + xt26g0xa_ecc_get_status)), + SPINAND_INFO("XT26G04A", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3), + NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g0xa_ooblayout, + xt26g0xa_ecc_get_status)), + SPINAND_INFO("XT26G01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G11D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G12D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), +}; + +static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer xtx_spinand_manufacturer = { + .id = SPINAND_MFR_XTX, + .name = "XTX", + .chips = xtx_spinand_table, + .nchips = ARRAY_SIZE(xtx_spinand_table), + .ops = &xtx_spinand_manuf_ops, +}; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c222197b114..4c1642b29a8 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -352,6 +352,11 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, (phydev->duplex) ? "full" : "half", (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +#ifdef CONFIG_ARCH_NPCM8XX + /* Pass all Multicast Frames */ + setbits_le32(&mac_p->framefilt, BIT(4)); + +#endif return 0; } @@ -554,6 +559,11 @@ static int _dw_free_pkt(struct dw_eth_dev *priv) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + ulong data_start = desc_p->dmamac_addr; + ulong data_end = data_start + roundup(CFG_ETH_BUFSIZE, ARCH_DMA_MINALIGN); + + /* Invalidate the descriptor buffer data */ + invalidate_dcache_range(data_start, data_end); /* * Make the current descriptor valid again and go to diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9b3bce1dc87..67d80d987ff 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -159,7 +159,7 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = eqos_mdio_wait_idle(eqos); if (ret) { - pr_err("MDIO not idle at entry"); + pr_err("MDIO not idle at entry\n"); return ret; } @@ -179,7 +179,7 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = eqos_mdio_wait_idle(eqos); if (ret) { - pr_err("MDIO read didn't complete"); + pr_err("MDIO read didn't complete\n"); return ret; } @@ -203,7 +203,7 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = eqos_mdio_wait_idle(eqos); if (ret) { - pr_err("MDIO not idle at entry"); + pr_err("MDIO not idle at entry\n"); return ret; } @@ -225,7 +225,7 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, ret = eqos_mdio_wait_idle(eqos); if (ret) { - pr_err("MDIO read didn't complete"); + pr_err("MDIO read didn't complete\n"); return ret; } @@ -242,37 +242,37 @@ static int eqos_start_clks_tegra186(struct udevice *dev) ret = clk_enable(&eqos->clk_slave_bus); if (ret < 0) { - pr_err("clk_enable(clk_slave_bus) failed: %d", ret); + pr_err("clk_enable(clk_slave_bus) failed: %d\n", ret); goto err; } ret = clk_enable(&eqos->clk_master_bus); if (ret < 0) { - pr_err("clk_enable(clk_master_bus) failed: %d", ret); + pr_err("clk_enable(clk_master_bus) failed: %d\n", ret); goto err_disable_clk_slave_bus; } ret = clk_enable(&eqos->clk_rx); if (ret < 0) { - pr_err("clk_enable(clk_rx) failed: %d", ret); + pr_err("clk_enable(clk_rx) failed: %d\n", ret); goto err_disable_clk_master_bus; } ret = clk_enable(&eqos->clk_ptp_ref); if (ret < 0) { - pr_err("clk_enable(clk_ptp_ref) failed: %d", ret); + pr_err("clk_enable(clk_ptp_ref) failed: %d\n", ret); goto err_disable_clk_rx; } ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); if (ret < 0) { - pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret); + pr_err("clk_set_rate(clk_ptp_ref) failed: %d\n", ret); goto err_disable_clk_ptp_ref; } ret = clk_enable(&eqos->clk_tx); if (ret < 0) { - pr_err("clk_enable(clk_tx) failed: %d", ret); + pr_err("clk_enable(clk_tx) failed: %d\n", ret); goto err_disable_clk_ptp_ref; } #endif @@ -305,26 +305,26 @@ static int eqos_start_clks_stm32(struct udevice *dev) ret = clk_enable(&eqos->clk_master_bus); if (ret < 0) { - pr_err("clk_enable(clk_master_bus) failed: %d", ret); + pr_err("clk_enable(clk_master_bus) failed: %d\n", ret); goto err; } ret = clk_enable(&eqos->clk_rx); if (ret < 0) { - pr_err("clk_enable(clk_rx) failed: %d", ret); + pr_err("clk_enable(clk_rx) failed: %d\n", ret); goto err_disable_clk_master_bus; } ret = clk_enable(&eqos->clk_tx); if (ret < 0) { - pr_err("clk_enable(clk_tx) failed: %d", ret); + pr_err("clk_enable(clk_tx) failed: %d\n", ret); goto err_disable_clk_rx; } if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { ret = clk_enable(&eqos->clk_ck); if (ret < 0) { - pr_err("clk_enable(clk_ck) failed: %d", ret); + pr_err("clk_enable(clk_ck) failed: %d\n", ret); goto err_disable_clk_tx; } eqos->clk_ck_enabled = true; @@ -390,7 +390,7 @@ static int eqos_start_resets_tegra186(struct udevice *dev) ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); if (ret < 0) { - pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); + pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d\n", ret); return ret; } @@ -398,13 +398,13 @@ static int eqos_start_resets_tegra186(struct udevice *dev) ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); if (ret < 0) { - pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d\n", ret); return ret; } ret = reset_assert(&eqos->reset_ctl); if (ret < 0) { - pr_err("reset_assert() failed: %d", ret); + pr_err("reset_assert() failed: %d\n", ret); return ret; } @@ -412,7 +412,7 @@ static int eqos_start_resets_tegra186(struct udevice *dev) ret = reset_deassert(&eqos->reset_ctl); if (ret < 0) { - pr_err("reset_deassert() failed: %d", ret); + pr_err("reset_deassert() failed: %d\n", ret); return ret; } @@ -448,14 +448,14 @@ static int eqos_calibrate_pads_tegra186(struct udevice *dev) ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); if (ret) { - pr_err("calibrate didn't start"); + pr_err("calibrate didn't start\n"); goto failed; } ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); if (ret) { - pr_err("calibrate didn't finish"); + pr_err("calibrate didn't finish\n"); goto failed; } @@ -586,13 +586,13 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) rate = 2.5 * 1000 * 1000; break; default: - pr_err("invalid speed %d", eqos->phy->speed); + pr_err("invalid speed %d\n", eqos->phy->speed); return -EINVAL; } ret = clk_set_rate(&eqos->clk_tx, rate); if (ret < 0) { - pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); + pr_err("clk_set_rate(tx_clk, %lu) failed: %d\n", rate, ret); return ret; } #endif @@ -613,7 +613,7 @@ static int eqos_adjust_link(struct udevice *dev) else ret = eqos_set_half_duplex(dev); if (ret < 0) { - pr_err("eqos_set_*_duplex() failed: %d", ret); + pr_err("eqos_set_*_duplex() failed: %d\n", ret); return ret; } @@ -631,32 +631,32 @@ static int eqos_adjust_link(struct udevice *dev) ret = eqos_set_mii_speed_10(dev); break; default: - pr_err("invalid speed %d", eqos->phy->speed); + pr_err("invalid speed %d\n", eqos->phy->speed); return -EINVAL; } if (ret < 0) { - pr_err("eqos_set_*mii_speed*() failed: %d", ret); + pr_err("eqos_set_*mii_speed*() failed: %d\n", ret); return ret; } if (en_calibration) { ret = eqos->config->ops->eqos_calibrate_pads(dev); if (ret < 0) { - pr_err("eqos_calibrate_pads() failed: %d", + pr_err("eqos_calibrate_pads() failed: %d\n", ret); return ret; } } else { ret = eqos->config->ops->eqos_disable_calibration(dev); if (ret < 0) { - pr_err("eqos_disable_calibration() failed: %d", + pr_err("eqos_disable_calibration() failed: %d\n", ret); return ret; } } ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); if (ret < 0) { - pr_err("eqos_set_tx_clk_speed() failed: %d", ret); + pr_err("eqos_set_tx_clk_speed() failed: %d\n", ret); return ret; } @@ -755,7 +755,7 @@ static int eqos_start(struct udevice *dev) ret = eqos->config->ops->eqos_start_resets(dev); if (ret < 0) { - pr_err("eqos_start_resets() failed: %d", ret); + pr_err("eqos_start_resets() failed: %d\n", ret); goto err; } @@ -773,13 +773,13 @@ static int eqos_start(struct udevice *dev) EQOS_DMA_MODE_SWR, false, eqos->config->swr_wait, false); if (ret) { - pr_err("EQOS_DMA_MODE_SWR stuck"); + pr_err("EQOS_DMA_MODE_SWR stuck\n"); goto err_stop_resets; } ret = eqos->config->ops->eqos_calibrate_pads(dev); if (ret < 0) { - pr_err("eqos_calibrate_pads() failed: %d", ret); + pr_err("eqos_calibrate_pads() failed: %d\n", ret); goto err_stop_resets; } @@ -812,7 +812,7 @@ static int eqos_start(struct udevice *dev) } if (!eqos->phy) { - pr_err("phy_connect() failed"); + pr_err("phy_connect() failed\n"); ret = -ENODEV; goto err_stop_resets; } @@ -820,7 +820,7 @@ static int eqos_start(struct udevice *dev) if (eqos->max_speed) { ret = phy_set_supported(eqos->phy, eqos->max_speed); if (ret) { - pr_err("phy_set_supported() failed: %d", ret); + pr_err("phy_set_supported() failed: %d\n", ret); goto err_shutdown_phy; } } @@ -828,26 +828,26 @@ static int eqos_start(struct udevice *dev) eqos->phy->node = eqos->phy_of_node; ret = phy_config(eqos->phy); if (ret < 0) { - pr_err("phy_config() failed: %d", ret); + pr_err("phy_config() failed: %d\n", ret); goto err_shutdown_phy; } } ret = phy_startup(eqos->phy); if (ret < 0) { - pr_err("phy_startup() failed: %d", ret); + pr_err("phy_startup() failed: %d\n", ret); goto err_shutdown_phy; } if (!eqos->phy->link) { - pr_err("No link"); + pr_err("No link\n"); ret = -EAGAIN; goto err_shutdown_phy; } ret = eqos_adjust_link(dev); if (ret < 0) { - pr_err("eqos_adjust_link() failed: %d", ret); + pr_err("eqos_adjust_link() failed: %d\n", ret); goto err_shutdown_phy; } @@ -1090,7 +1090,7 @@ err_shutdown_phy: err_stop_resets: eqos->config->ops->eqos_stop_resets(dev); err: - pr_err("FAILED: %d", ret); + pr_err("FAILED: %d\n", ret); return ret; } @@ -1217,7 +1217,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) struct eqos_priv *eqos = dev_get_priv(dev); u32 idx, idx_mask = eqos->desc_per_cacheline - 1; uchar *packet_expected; - struct eqos_desc *rx_desc; + struct eqos_desc *rx_desc = NULL; debug("%s(packet=%p, length=%d)\n", __func__, packet, length); @@ -1361,7 +1361,7 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); if (ret) { - pr_err("reset_get_by_name(rst) failed: %d", ret); + pr_err("reset_get_by_name(rst) failed: %d\n", ret); return ret; } @@ -1369,37 +1369,37 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) &eqos->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret) { - pr_err("gpio_request_by_name(phy reset) failed: %d", ret); + pr_err("gpio_request_by_name(phy reset) failed: %d\n", ret); goto err_free_reset_eqos; } ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); if (ret) { - pr_err("clk_get_by_name(slave_bus) failed: %d", ret); + pr_err("clk_get_by_name(slave_bus) failed: %d\n", ret); goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); if (ret) { - pr_err("clk_get_by_name(master_bus) failed: %d", ret); + pr_err("clk_get_by_name(master_bus) failed: %d\n", ret); goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); if (ret) { - pr_err("clk_get_by_name(rx) failed: %d", ret); + pr_err("clk_get_by_name(rx) failed: %d\n", ret); goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); if (ret) { - pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); + pr_err("clk_get_by_name(ptp_ref) failed: %d\n", ret); goto err_free_gpio_phy_reset; } ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); if (ret) { - pr_err("clk_get_by_name(tx) failed: %d", ret); + pr_err("clk_get_by_name(tx) failed: %d\n", ret); goto err_free_gpio_phy_reset; } @@ -1436,19 +1436,19 @@ static int eqos_probe_resources_stm32(struct udevice *dev) ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); if (ret) { - pr_err("clk_get_by_name(master_bus) failed: %d", ret); + pr_err("clk_get_by_name(master_bus) failed: %d\n", ret); goto err_probe; } ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); if (ret) { - pr_err("clk_get_by_name(rx) failed: %d", ret); + pr_err("clk_get_by_name(rx) failed: %d\n", ret); goto err_probe; } ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); if (ret) { - pr_err("clk_get_by_name(tx) failed: %d", ret); + pr_err("clk_get_by_name(tx) failed: %d\n", ret); goto err_probe; } @@ -1502,7 +1502,7 @@ static int eqos_probe(struct udevice *dev) eqos->regs = dev_read_addr(dev); if (eqos->regs == FDT_ADDR_T_NONE) { - pr_err("dev_read_addr() failed"); + pr_err("dev_read_addr() failed\n"); return -ENODEV; } eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); @@ -1514,19 +1514,19 @@ static int eqos_probe(struct udevice *dev) ret = eqos_probe_resources_core(dev); if (ret < 0) { - pr_err("eqos_probe_resources_core() failed: %d", ret); + pr_err("eqos_probe_resources_core() failed: %d\n", ret); return ret; } ret = eqos->config->ops->eqos_probe_resources(dev); if (ret < 0) { - pr_err("eqos_probe_resources() failed: %d", ret); + pr_err("eqos_probe_resources() failed: %d\n", ret); goto err_remove_resources_core; } ret = eqos->config->ops->eqos_start_clks(dev); if (ret < 0) { - pr_err("eqos_start_clks() failed: %d", ret); + pr_err("eqos_start_clks() failed: %d\n", ret); goto err_remove_resources_tegra; } @@ -1536,7 +1536,7 @@ static int eqos_probe(struct udevice *dev) if (!eqos->mii) { eqos->mii = mdio_alloc(); if (!eqos->mii) { - pr_err("mdio_alloc() failed"); + pr_err("mdio_alloc() failed\n"); ret = -ENOMEM; goto err_stop_clks; } @@ -1547,7 +1547,7 @@ static int eqos_probe(struct udevice *dev) ret = mdio_register(eqos->mii); if (ret < 0) { - pr_err("mdio_register() failed: %d", ret); + pr_err("mdio_register() failed: %d\n", ret); goto err_free_mdio; } } diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 72eccc99e5f..ddfa95a0b7e 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -57,3 +57,16 @@ config MDIO_TI_CPSW help This driver supports the TI CPSW MDIO interface found in various TI SoCs. + +config TI_ICSSG_PRUETH + bool "TI Gigabit PRU Ethernet driver" + depends on ARCH_K3 + imply DM_MDIO + imply MISC_INIT_R + imply MISC + imply MDIO_TI_CPSW + select PHYLIB + select FS_LOADER + help + Support Gigabit Ethernet ports over the ICSSG PRU Subsystem + This subsystem is available starting with the AM65 platform. diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index 30c4c4b6d5a..b2b3aa3b180 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o obj-$(CONFIG_MDIO_TI_CPSW) += cpsw_mdio.o +obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg_prueth.o icssg_classifier.o icssg_config.o icssg_queues.o diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index d68ed671836..b151e25d6a4 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -664,7 +664,7 @@ static int am65_cpsw_port_probe(struct udevice *dev) struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common; - char portname[15]; + char portname[32]; int ret; priv->dev = dev; @@ -672,7 +672,7 @@ static int am65_cpsw_port_probe(struct udevice *dev) cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common; - sprintf(portname, "%s%s", dev->parent->name, dev->name); + snprintf(portname, sizeof(portname), "%s%s", dev->parent->name, dev->name); device_set_name(dev, portname); ret = am65_cpsw_ofdata_parse_phy(dev); diff --git a/drivers/net/ti/icss_mii_rt.h b/drivers/net/ti/icss_mii_rt.h new file mode 100644 index 00000000000..fd95d4d7c1f --- /dev/null +++ b/drivers/net/ti/icss_mii_rt.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* PRU-ICSS MII_RT register definitions + * + * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com + */ + +#ifndef __NET_PRUSS_MII_RT_H__ +#define __NET_PRUSS_MII_RT_H__ + +#include <regmap.h> + +/* PRUSS_MII_RT Registers */ +#define PRUSS_MII_RT_RXCFG0 0x0 +#define PRUSS_MII_RT_RXCFG1 0x4 +#define PRUSS_MII_RT_TXCFG0 0x10 +#define PRUSS_MII_RT_TXCFG1 0x14 +#define PRUSS_MII_RT_TX_CRC0 0x20 +#define PRUSS_MII_RT_TX_CRC1 0x24 +#define PRUSS_MII_RT_TX_IPG0 0x30 +#define PRUSS_MII_RT_TX_IPG1 0x34 +#define PRUSS_MII_RT_PRS0 0x38 +#define PRUSS_MII_RT_PRS1 0x3c +#define PRUSS_MII_RT_RX_FRMS0 0x40 +#define PRUSS_MII_RT_RX_FRMS1 0x44 +#define PRUSS_MII_RT_RX_PCNT0 0x48 +#define PRUSS_MII_RT_RX_PCNT1 0x4c +#define PRUSS_MII_RT_RX_ERR0 0x50 +#define PRUSS_MII_RT_RX_ERR1 0x54 + +/* PRUSS_MII_RT_RXCFG0/1 bits */ +#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0) +#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS BIT(1) +#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2) +#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3) +#define PRUSS_MII_RT_RXCFG_RX_L2_EN BIT(4) +#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAP BIT(5) +#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6) +#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9) + +/* PRUSS_MII_RT_TXCFG0/1 bits */ +#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0) +#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE BIT(1) +#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2) +#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAP BIT(3) +#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCE BIT(9) +#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10) +#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11) +#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */ + +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT 16 +#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16) + +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28 +#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28) + +/* PRUSS_MII_RT_TX_IPG0/1 bits */ +#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0 +#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0) + +/* PRUSS_MII_RT_PRS0/1 bits */ +#define PRUSS_MII_RT_PRS_COL BIT(0) +#define PRUSS_MII_RT_PRS_CRS BIT(1) + +/* PRUSS_MII_RT_RX_FRMS0/1 bits */ +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0 +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0) + +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16 +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16) + +/* Min/Max in MII_RT_RX_FRMS */ +/* For EMAC and Switch */ +#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64) + +/* for HSR and PRP */ +#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \ + ICSS_LRE_TAG_RCT_SIZE) +/* PRUSS_MII_RT_RX_PCNT0/1 bits */ +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT 0 +#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0) + +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT 4 +#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4) + +/* PRUSS_MII_RT_RX_ERR0/1 bits */ +#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0) +#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1) +#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERR BIT(2) +#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERR BIT(3) + +#define ICSSG_CFG_OFFSET 0 +#define RGMII_CFG_OFFSET 4 + +/* Constant to choose between MII0 and MII1 */ +#define ICSS_MII0 0 +#define ICSS_MII1 1 + +/* ICSSG_CFG Register bits */ +#define ICSSG_CFG_SGMII_MODE BIT(16) +#define ICSSG_CFG_TX_PRU_EN BIT(11) +#define ICSSG_CFG_RX_SFD_TX_SOF_EN BIT(10) +#define ICSSG_CFG_RTU_PRU_PSI_SHARE_EN BIT(9) +#define ICSSG_CFG_IEP1_TX_EN BIT(8) +#define ICSSG_CFG_MII1_MODE GENMASK(6, 5) +#define ICSSG_CFG_MII1_MODE_SHIFT 5 +#define ICSSG_CFG_MII0_MODE GENMASK(4, 3) +#define ICSSG_CFG_MII0_MODE_SHIFT 3 +#define ICSSG_CFG_RX_L2_G_EN BIT(2) +#define ICSSG_CFG_TX_L2_EN BIT(1) +#define ICSSG_CFG_TX_L1_EN BIT(0) + +enum mii_mode { MII_MODE_MII = 0, MII_MODE_RGMII, MII_MODE_SGMII }; + +/* RGMII CFG Register bits */ +#define RGMII_CFG_INBAND_EN_MII0 BIT(16) +#define RGMII_CFG_GIG_EN_MII0 BIT(17) +#define RGMII_CFG_INBAND_EN_MII1 BIT(20) +#define RGMII_CFG_GIG_EN_MII1 BIT(21) +#define RGMII_CFG_FULL_DUPLEX_MII0 BIT(18) +#define RGMII_CFG_FULL_DUPLEX_MII1 BIT(22) +#define RGMII_CFG_SPEED_MII0 GENMASK(2, 1) +#define RGMII_CFG_SPEED_MII1 GENMASK(6, 5) +#define RGMII_CFG_SPEED_MII0_SHIFT 1 +#define RGMII_CFG_SPEED_MII1_SHIFT 5 +#define RGMII_CFG_FULLDUPLEX_MII0 BIT(3) +#define RGMII_CFG_FULLDUPLEX_MII1 BIT(7) +#define RGMII_CFG_FULLDUPLEX_MII0_SHIFT 3 +#define RGMII_CFG_FULLDUPLEX_MII1_SHIFT 7 +#define RGMII_CFG_SPEED_10M 0 +#define RGMII_CFG_SPEED_100M 1 +#define RGMII_CFG_SPEED_1G 2 + +static inline void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg) +{ + u32 val; + + if (mii == ICSS_MII0) { + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg); + } else { + /* Errata workaround: IEP1 is not read by h/w unless IEP0 is written */ + regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val); + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg); + regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val); + } +} + +static inline void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed, + bool full_duplex, int slice, struct prueth_priv *priv) +{ + u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0; + u32 inband_en_mask, inband_val = 0; + + gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 : + RGMII_CFG_GIG_EN_MII1; + if (speed == SPEED_1000) + gig_val = gig_en_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); + + inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 : + RGMII_CFG_INBAND_EN_MII1; + if (speed == SPEED_10 && phy_interface_is_rgmii(priv->phydev)) + inband_val = inband_en_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); + + full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 : + RGMII_CFG_FULL_DUPLEX_MII1; + if (full_duplex) + full_duplex_val = full_duplex_mask; + regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, + full_duplex_val); +} + +static inline void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, int phy_if) +{ + u32 val, mask, shift; + + mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE; + shift = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT; + + val = MII_MODE_RGMII; + if (phy_if == PHY_INTERFACE_MODE_MII) + val = MII_MODE_MII; + + val <<= shift; + regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); + regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); +} + +#endif /* __NET_PRUSS_MII_RT_H__ */ diff --git a/drivers/net/ti/icssg_classifier.c b/drivers/net/ti/icssg_classifier.c new file mode 100644 index 00000000000..e510a1cd3e5 --- /dev/null +++ b/drivers/net/ti/icssg_classifier.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Texas Instruments ICSSG Ethernet Driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include <dm/ofnode.h> +#include <regmap.h> + +#define ICSSG_NUM_CLASSIFIERS 16 +#define ICSSG_NUM_FT1_SLOTS 8 +#define ICSSG_NUM_FT3_SLOTS 16 + +#define ICSSG_NUM_CLASSIFIERS_IN_USE 1 + +/* Filter 1 - FT1 */ +#define FT1_NUM_SLOTS 8 +#define FT1_SLOT_SIZE 0x10 /* bytes */ + +/* offsets from FT1 slot base i.e. slot 1 start */ +#define FT1_DA0 0x0 +#define FT1_DA1 0x4 +#define FT1_DA0_MASK 0x8 +#define FT1_DA1_MASK 0xc + +#define FT1_N_REG(slize, n, reg) (offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg)) + +#define FT1_LEN_MASK GENMASK(19, 16) +#define FT1_LEN_SHIFT 16 +#define FT1_LEN(len) (((len) << FT1_LEN_SHIFT) & FT1_LEN_MASK) + +#define FT1_START_MASK GENMASK(14, 0) +#define FT1_START(start) ((start) & FT1_START_MASK) + +#define FT1_MATCH_SLOT(n) (GENMASK(23, 16) & (BIT(n) << 16)) + +enum ft1_cfg_type { + FT1_CFG_TYPE_DISABLED = 0, + FT1_CFG_TYPE_EQ, + FT1_CFG_TYPE_GT, + FT1_CFG_TYPE_LT, +}; + +#define FT1_CFG_SHIFT(n) (2 * (n)) +#define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) + +/* Filter 3 - FT3 */ +#define FT3_NUM_SLOTS 16 +#define FT3_SLOT_SIZE 0x20 /* bytes */ + +/* offsets from FT3 slot n's base */ +#define FT3_START 0 +#define FT3_START_AUTO 0x4 +#define FT3_START_OFFSET 0x8 +#define FT3_JUMP_OFFSET 0xc +#define FT3_LEN 0x10 +#define FT3_CFG 0x14 +#define FT3_T 0x18 +#define FT3_T_MASK 0x1c + +#define FT3_N_REG(slize, n, reg) \ + (offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg)) + +/* offsets from rx_class n's base */ +#define RX_CLASS_AND_EN 0 +#define RX_CLASS_OR_EN 0x4 + +#define RX_CLASS_NUM_SLOTS 16 +#define RX_CLASS_EN_SIZE 0x8 /* bytes */ + +#define RX_CLASS_N_REG(slice, n, reg) \ + (offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg)) + +/* RX Class Gates */ +#define RX_CLASS_GATES_SIZE 0x4 /* bytes */ + +#define RX_CLASS_GATES_N_REG(slice, n) \ + (offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n)) + +#define RX_CLASS_GATES_ALLOW_MASK BIT(6) +#define RX_CLASS_GATES_RAW_MASK BIT(5) +#define RX_CLASS_GATES_PHASE_MASK BIT(4) + +/* RX Class traffic data matching bits */ +#define RX_CLASS_FT_UC BIT(31) +#define RX_CLASS_FT_MC BIT(30) +#define RX_CLASS_FT_BC BIT(29) +#define RX_CLASS_FT_FW BIT(28) +#define RX_CLASS_FT_RCV BIT(27) +#define RX_CLASS_FT_VLAN BIT(26) +#define RX_CLASS_FT_DA_P BIT(25) +#define RX_CLASS_FT_DA_I BIT(24) +#define RX_CLASS_FT_FT1_MATCH_MASK GENMASK(23, 16) +#define RX_CLASS_FT_FT1_MATCH_SHIFT 16 +#define RX_CLASS_FT_FT3_MATCH_MASK GENMASK(15, 0) +#define RX_CLASS_FT_FT3_MATCH_SHIFT 0 + +#define RX_CLASS_FT_FT1_MATCH(slot) \ + ((BIT(slot) << RX_CLASS_FT_FT1_MATCH_SHIFT) & \ + RX_CLASS_FT_FT1_MATCH_MASK) + +enum rx_class_sel_type { + RX_CLASS_SEL_TYPE_OR = 0, + RX_CLASS_SEL_TYPE_AND = 1, + RX_CLASS_SEL_TYPE_OR_AND_AND = 2, + RX_CLASS_SEL_TYPE_OR_OR_AND = 3, +}; + +#define FT1_CFG_SHIFT(n) (2 * (n)) +#define FT1_CFG_MASK(n) (0x3 << FT1_CFG_SHIFT((n))) + +#define RX_CLASS_SEL_SHIFT(n) (2 * (n)) +#define RX_CLASS_SEL_MASK(n) (0x3 << RX_CLASS_SEL_SHIFT((n))) + +#define ICSSG_CFG_OFFSET 0 +#define MAC_INTERFACE_0 0x18 +#define MAC_INTERFACE_1 0x1c + +#define ICSSG_CFG_RX_L2_G_EN BIT(2) + +/* these are register offsets per PRU */ +struct miig_rt_offsets { + u32 mac0; + u32 mac1; + u32 ft1_start_len; + u32 ft1_cfg; + u32 ft1_slot_base; + u32 ft3_slot_base; + u32 ft3_p_base; + u32 ft_rx_ptr; + u32 rx_class_base; + u32 rx_class_cfg1; + u32 rx_class_cfg2; + u32 rx_class_gates_base; + u32 rx_green; + u32 rx_rate_cfg_base; + u32 rx_rate_src_sel0; + u32 rx_rate_src_sel1; + u32 tx_rate_cfg_base; + u32 stat_base; + u32 tx_hsr_tag; + u32 tx_hsr_seq; + u32 tx_vlan_type; + u32 tx_vlan_ins; +}; + +static struct miig_rt_offsets offs[] = { + /* PRU0 */ + { + 0x8, + 0xc, + 0x80, + 0x84, + 0x88, + 0x108, + 0x308, + 0x408, + 0x40c, + 0x48c, + 0x490, + 0x494, + 0x4d4, + 0x4e4, + 0x504, + 0x508, + 0x50c, + 0x54c, + 0x63c, + 0x640, + 0x644, + 0x648, + }, + /* PRU1 */ + { + 0x10, + 0x14, + 0x64c, + 0x650, + 0x654, + 0x6d4, + 0x8d4, + 0x9d4, + 0x9d8, + 0xa58, + 0xa5c, + 0xa60, + 0xaa0, + 0xab0, + 0xad0, + 0xad4, + 0xad8, + 0xb18, + 0xc08, + 0xc0c, + 0xc10, + 0xc14, + }, +}; + +static inline u32 addr_to_da0(const u8 *addr) +{ + return (u32)(addr[0] | addr[1] << 8 | + addr[2] << 16 | addr[3] << 24); +}; + +static inline u32 addr_to_da1(const u8 *addr) +{ + return (u32)(addr[4] | addr[5] << 8); +}; + +static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice, + u16 start, u8 len) +{ + u32 offset, val; + + offset = offs[slice].ft1_start_len; + val = FT1_LEN(len) | FT1_START(start); + regmap_write(miig_rt, offset, val); +} + +static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice, + int n, const u8 *addr) +{ + u32 offset; + + offset = FT1_N_REG(slice, n, FT1_DA0); + regmap_write(miig_rt, offset, addr_to_da0(addr)); + offset = FT1_N_REG(slice, n, FT1_DA1); + regmap_write(miig_rt, offset, addr_to_da1(addr)); +} + +static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice, + int n, const u8 *addr) +{ + u32 offset; + + offset = FT1_N_REG(slice, n, FT1_DA0_MASK); + regmap_write(miig_rt, offset, addr_to_da0(addr)); + offset = FT1_N_REG(slice, n, FT1_DA1_MASK); + regmap_write(miig_rt, offset, addr_to_da1(addr)); +} + +static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n, + enum ft1_cfg_type type) +{ + u32 offset; + + offset = offs[slice].ft1_cfg; + regmap_update_bits(miig_rt, offset, FT1_CFG_MASK(n), + type << FT1_CFG_SHIFT(n)); +} + +static void rx_class_sel_set_type(struct regmap *miig_rt, int slice, int n, + enum rx_class_sel_type type) +{ + u32 offset; + + offset = offs[slice].rx_class_cfg1; + regmap_update_bits(miig_rt, offset, RX_CLASS_SEL_MASK(n), + type << RX_CLASS_SEL_SHIFT(n)); +} + +static void rx_class_set_and(struct regmap *miig_rt, int slice, int n, + u32 data) +{ + u32 offset; + + offset = RX_CLASS_N_REG(slice, n, RX_CLASS_AND_EN); + regmap_write(miig_rt, offset, data); +} + +static void rx_class_set_or(struct regmap *miig_rt, int slice, int n, + u32 data) +{ + u32 offset; + + offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN); + regmap_write(miig_rt, offset, data); +} + +void icssg_class_set_host_mac_addr(struct regmap *miig_rt, u8 *mac) +{ + regmap_write(miig_rt, MAC_INTERFACE_0, addr_to_da0(mac)); + regmap_write(miig_rt, MAC_INTERFACE_1, addr_to_da1(mac)); +} + +void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac) +{ + regmap_write(miig_rt, offs[slice].mac0, addr_to_da0(mac)); + regmap_write(miig_rt, offs[slice].mac1, addr_to_da1(mac)); +} + +void icssg_class_disable_n(struct regmap *miig_rt, int slice, int n) +{ + u32 data, offset; + + /* AND_EN = 0 */ + rx_class_set_and(miig_rt, slice, n, 0); + /* OR_EN = 0 */ + rx_class_set_or(miig_rt, slice, n, 0); + + /* set CFG1 to OR */ + rx_class_sel_set_type(miig_rt, slice, n, RX_CLASS_SEL_TYPE_OR); + + /* configure gate */ + offset = RX_CLASS_GATES_N_REG(slice, n); + regmap_read(miig_rt, offset, &data); + /* clear class_raw so we go through filters */ + data &= ~RX_CLASS_GATES_RAW_MASK; + /* set allow and phase mask */ + data |= RX_CLASS_GATES_ALLOW_MASK | RX_CLASS_GATES_PHASE_MASK; + regmap_write(miig_rt, offset, data); +} + +/* disable all RX traffic */ +void icssg_class_disable(struct regmap *miig_rt, int slice) +{ + int n; + + /* Enable RX_L2_G */ + regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, ICSSG_CFG_RX_L2_G_EN, + ICSSG_CFG_RX_L2_G_EN); + + for (n = 0; n < ICSSG_NUM_CLASSIFIERS; n++) + icssg_class_disable_n(miig_rt, slice, n); + + /* FT1 Disabled */ + for (n = 0; n < ICSSG_NUM_FT1_SLOTS; n++) { + u8 addr[] = { 0, 0, 0, 0, 0, 0, }; + + rx_class_ft1_cfg_set_type(miig_rt, slice, n, + FT1_CFG_TYPE_DISABLED); + rx_class_ft1_set_da(miig_rt, slice, n, addr); + rx_class_ft1_set_da_mask(miig_rt, slice, n, addr); + } + + /* clear CFG2 */ + regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); +} + +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti) +{ + u32 data; + + /* defaults */ + icssg_class_disable(miig_rt, slice); + + /* Setup Classifier */ + /* match on Broadcast or MAC_PRU address */ + data = RX_CLASS_FT_BC | RX_CLASS_FT_DA_P; + + /* multicast? */ + if (allmulti) + data |= RX_CLASS_FT_MC; + + rx_class_set_or(miig_rt, slice, 0, data); + + /* set CFG1 for OR_OR_AND for classifier */ + rx_class_sel_set_type(miig_rt, slice, 0, + RX_CLASS_SEL_TYPE_OR_OR_AND); + + /* clear CFG2 */ + regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); +} + +/* required for SR2 for SAV check */ +void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr) +{ + u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, }; + + rx_class_ft1_set_start_len(miig_rt, slice, 6, 6); + rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr); + rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr); + rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ); +} diff --git a/drivers/net/ti/icssg_config.c b/drivers/net/ti/icssg_config.c new file mode 100644 index 00000000000..5f132d0525c --- /dev/null +++ b/drivers/net/ti/icssg_config.c @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: GPL-2.0 +/* ICSSG Ethernet driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <phy.h> +#include "icssg_prueth.h" +#include "icssg_switch_map.h" +#include "icss_mii_rt.h" +#include <dm/device_compat.h> +#include <linux/iopoll.h> + +/* TX IPG Values to be set for 100M and 1G link speeds. These values are + * in ocp_clk cycles. So need change if ocp_clk is changed for a specific + * h/w design. + */ + +/* SR2.0 IPG is in rgmii_clk (125MHz) clock cycles + 1 */ +#define MII_RT_TX_IPG_100M 0x17 +#define MII_RT_TX_IPG_1G 0xb + +#define ICSSG_QUEUES_MAX 64 +#define ICSSG_QUEUE_OFFSET 0xd00 +#define ICSSG_QUEUE_PEEK_OFFSET 0xe00 +#define ICSSG_QUEUE_CNT_OFFSET 0xe40 +#define ICSSG_QUEUE_RESET_OFFSET 0xf40 + +#define ICSSG_NUM_TX_QUEUES 8 + +#define RECYCLE_Q_SLICE0 16 +#define RECYCLE_Q_SLICE1 17 + +#define ICSSG_NUM_OTHER_QUEUES 5 /* port, host and special queues */ + +#define PORT_HI_Q_SLICE0 32 +#define PORT_LO_Q_SLICE0 33 +#define HOST_HI_Q_SLICE0 34 +#define HOST_LO_Q_SLICE0 35 +#define HOST_SPL_Q_SLICE0 40 /* Special Queue */ + +#define PORT_HI_Q_SLICE1 36 +#define PORT_LO_Q_SLICE1 37 +#define HOST_HI_Q_SLICE1 38 +#define HOST_LO_Q_SLICE1 39 +#define HOST_SPL_Q_SLICE1 41 /* Special Queue */ + +#define MII_RXCFG_DEFAULT (PRUSS_MII_RT_RXCFG_RX_ENABLE | \ + PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS | \ + PRUSS_MII_RT_RXCFG_RX_L2_EN | \ + PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS) + +#define MII_TXCFG_DEFAULT (PRUSS_MII_RT_TXCFG_TX_ENABLE | \ + PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE | \ + PRUSS_MII_RT_TXCFG_TX_32_MODE_EN | \ + PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN) + +#define ICSSG_CFG_DEFAULT (ICSSG_CFG_TX_L1_EN | \ + ICSSG_CFG_TX_L2_EN | ICSSG_CFG_RX_L2_G_EN | \ + ICSSG_CFG_TX_PRU_EN | /* SR2.0 only */ \ + ICSSG_CFG_SGMII_MODE) + +#define FDB_GEN_CFG1 0x60 +#define SMEM_VLAN_OFFSET 8 +#define SMEM_VLAN_OFFSET_MASK GENMASK(25, 8) + +#define FDB_GEN_CFG2 0x64 +#define FDB_VLAN_EN BIT(6) +#define FDB_HOST_EN BIT(2) +#define FDB_PRU1_EN BIT(1) +#define FDB_PRU0_EN BIT(0) +#define FDB_EN_ALL (FDB_PRU0_EN | FDB_PRU1_EN | \ + FDB_HOST_EN | FDB_VLAN_EN) + +struct map { + int queue; + u32 pd_addr_start; + u32 flags; + bool special; +}; + +struct map hwq_map[2][ICSSG_NUM_OTHER_QUEUES] = { + { + { PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 }, + { PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 }, + { HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 }, + { HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 }, + { HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 }, + }, + { + { PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 }, + { PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 }, + { HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 }, + { HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 }, + { HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 }, + }, +}; + +static void icssg_config_mii_init(struct prueth_priv *priv, int slice) +{ + struct prueth *prueth = priv->prueth; + struct regmap *mii_rt = prueth->mii_rt; + u32 txcfg_reg, pcnt_reg; + u32 txcfg; + + txcfg_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_TXCFG0 : + PRUSS_MII_RT_TXCFG1; + pcnt_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_RX_PCNT0 : + PRUSS_MII_RT_RX_PCNT1; + + txcfg = MII_TXCFG_DEFAULT; + + if (prueth->phy_interface == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0) + txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL; + else if (prueth->phy_interface != PHY_INTERFACE_MODE_MII && slice == ICSS_MII1) + txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL; + + regmap_write(mii_rt, txcfg_reg, txcfg); + regmap_write(mii_rt, pcnt_reg, 0x1); +} + +static void icssg_miig_queues_init(struct prueth_priv *priv, int slice) +{ + struct prueth *prueth = priv->prueth; + void __iomem *smem = (void __iomem *)prueth->shram.pa; + struct regmap *miig_rt = prueth->miig_rt; + int queue = 0, i, j; + u8 pd[ICSSG_SPECIAL_PD_SIZE]; + u32 *pdword; + + /* reset hwqueues */ + if (slice) + queue = ICSSG_NUM_TX_QUEUES; + + for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) { + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); + queue++; + } + + queue = slice ? RECYCLE_Q_SLICE1 : RECYCLE_Q_SLICE0; + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); + + for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) { + regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, + hwq_map[slice][i].queue); + } + + /* initialize packet descriptors in SMEM */ + /* push pakcet descriptors to hwqueues */ + + pdword = (u32 *)pd; + for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) { + struct map *mp; + int pd_size, num_pds; + u32 pdaddr; + + mp = &hwq_map[slice][j]; + if (mp->special) { + pd_size = ICSSG_SPECIAL_PD_SIZE; + num_pds = ICSSG_NUM_SPECIAL_PDS; + } else { + pd_size = ICSSG_NORMAL_PD_SIZE; + num_pds = ICSSG_NUM_NORMAL_PDS; + } + + for (i = 0; i < num_pds; i++) { + memset(pd, 0, pd_size); + + pdword[0] &= cpu_to_le32(ICSSG_FLAG_MASK); + pdword[0] |= cpu_to_le32(mp->flags); + pdaddr = mp->pd_addr_start + i * pd_size; + + memcpy_toio(smem + pdaddr, pd, pd_size); + queue = mp->queue; + regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, + pdaddr); + } + } +} + +void icssg_config_ipg(struct prueth_priv *priv, int speed, int mii) +{ + struct prueth *prueth = priv->prueth; + + switch (speed) { + case SPEED_1000: + icssg_mii_update_ipg(prueth->mii_rt, mii, MII_RT_TX_IPG_1G); + break; + case SPEED_100: + icssg_mii_update_ipg(prueth->mii_rt, mii, MII_RT_TX_IPG_100M); + break; + default: + /* Other links speeds not supported */ + pr_err("Unsupported link speed\n"); + return; + } +} + +static void emac_r30_cmd_init(struct prueth_priv *priv) +{ + struct prueth *prueth = priv->prueth; + struct icssg_r30_cmd *p; + int i; + + p = (struct icssg_r30_cmd *)(prueth->dram[priv->port_id].pa + MGR_R30_CMD_OFFSET); + + for (i = 0; i < 4; i++) + writel(EMAC_NONE, &p->cmd[i]); +} + +static int emac_r30_is_done(struct prueth_priv *priv) +{ + struct prueth *prueth = priv->prueth; + const struct icssg_r30_cmd *p; + int i; + u32 cmd; + + p = (const struct icssg_r30_cmd *)(prueth->dram[priv->port_id].pa + MGR_R30_CMD_OFFSET); + + for (i = 0; i < 4; i++) { + cmd = readl(&p->cmd[i]); + if (cmd != EMAC_NONE) + return 0; + } + + return 1; +} + +static int prueth_emac_buffer_setup(struct prueth_priv *priv) +{ + struct prueth *prueth = priv->prueth; + struct icssg_buffer_pool_cfg *bpool_cfg; + struct icssg_rxq_ctx *rxq_ctx; + int slice = priv->port_id; + u32 addr; + int i; + + /* Layout to have 64KB aligned buffer pool + * |BPOOL0|BPOOL1|RX_CTX0|RX_CTX1| + */ + + addr = lower_32_bits(prueth->sram_pa); + if (slice) + addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE; + + if (addr % SZ_64K) { + dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n"); + return -EINVAL; + } + + bpool_cfg = (struct icssg_buffer_pool_cfg *)(prueth->dram[priv->port_id].pa + BUFFER_POOL_0_ADDR_OFFSET); + /* workaround for f/w bug. bpool 0 needs to be initilalized */ + bpool_cfg[0].addr = cpu_to_le32(addr); + bpool_cfg[0].len = 0; + + for (i = PRUETH_EMAC_BUF_POOL_START; + i < (PRUETH_EMAC_BUF_POOL_START + PRUETH_NUM_BUF_POOLS); + i++) { + bpool_cfg[i].addr = cpu_to_le32(addr); + bpool_cfg[i].len = cpu_to_le32(PRUETH_EMAC_BUF_POOL_SIZE); + addr += PRUETH_EMAC_BUF_POOL_SIZE; + } + + if (!slice) + addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE; + else + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE * 2; + + rxq_ctx = (struct icssg_rxq_ctx *)(prueth->dram[priv->port_id].pa + HOST_RX_Q_PRE_CONTEXT_OFFSET); + + for (i = 0; i < 3; i++) + rxq_ctx->start[i] = cpu_to_le32(addr); + + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE; + rxq_ctx->end = cpu_to_le32(addr); + + /* Express RX buffer queue */ + rxq_ctx = (struct icssg_rxq_ctx *)(prueth->dram[priv->port_id].pa + HOST_RX_Q_EXP_CONTEXT_OFFSET); + for (i = 0; i < 3; i++) + rxq_ctx->start[i] = cpu_to_le32(addr); + + addr += PRUETH_EMAC_RX_CTX_BUF_SIZE; + rxq_ctx->end = cpu_to_le32(addr); + + return 0; +} + +static void icssg_init_emac_mode(struct prueth *prueth) +{ + u8 mac[6] = { 0 }; + + regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, 0); + regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0); + /* Clear host MAC address */ + icssg_class_set_host_mac_addr(prueth->miig_rt, mac); +} + +int icssg_config(struct prueth_priv *priv) +{ + struct prueth *prueth = priv->prueth; + void *config = (void *)(prueth->dram[priv->port_id].pa + ICSSG_CONFIG_OFFSET); + u8 *cfg_byte_ptr = config; + struct icssg_flow_cfg *flow_cfg; + u32 mask; + int ret; + + int slice = priv->port_id; + + icssg_init_emac_mode(prueth); + + memset_io(config, 0, TAS_GATE_MASK_LIST0); + icssg_miig_queues_init(priv, slice); + + prueth->speed = SPEED_1000; + prueth->duplex = DUPLEX_FULL; + if (!phy_interface_is_rgmii(priv->phydev)) { + prueth->speed = SPEED_100; + prueth->duplex = DUPLEX_FULL; + } + + regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, + ICSSG_CFG_DEFAULT, ICSSG_CFG_DEFAULT); + icssg_miig_set_interface_mode(prueth->miig_rt, ICSS_MII0, prueth->phy_interface); + icssg_miig_set_interface_mode(prueth->miig_rt, ICSS_MII1, prueth->phy_interface); + icssg_config_mii_init(priv, slice); + + icssg_config_ipg(priv, SPEED_1000, slice); + icssg_update_rgmii_cfg(prueth->miig_rt, SPEED_1000, true, slice, priv); + + /* set GPI mode */ + pruss_cfg_gpimode(prueth->pruss, slice, PRUSS_GPI_MODE_MII); + + /* enable XFR shift for PRU and RTU */ + mask = PRUSS_SPP_XFER_SHIFT_EN | PRUSS_SPP_RTU_XFR_SHIFT_EN; + pruss_cfg_update(prueth->pruss, PRUSS_CFG_SPP, mask, mask); + + flow_cfg = config + PSI_L_REGULAR_FLOW_ID_BASE_OFFSET; + flow_cfg->rx_base_flow = prueth->dma_rx.id; + flow_cfg->mgm_base_flow = 0; + *(cfg_byte_ptr + SPL_PKT_DEFAULT_PRIORITY) = 0; + *(cfg_byte_ptr + QUEUE_NUM_UNTAGGED) = 0x0; + + ret = prueth_emac_buffer_setup(priv); + + if (ret) + return ret; + + emac_r30_cmd_init(priv); + return 0; +} + +/* commands to program ICSSG R30 registers */ +static struct icssg_r30_cmd emac_r32_bitmask[] = { + {{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}}, /* EMAC_PORT_DISABLE */ + {{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}}, /* EMAC_PORT_BLOCK */ + {{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}}, /* EMAC_PORT_FORWARD */ + {{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}}, /* EMAC_PORT_FORWARD_WO_LEARNING */ + {{0xffff0001, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT ALL */ + {{0xfffe0002, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT TAGGED */ + {{0xfffc0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT UNTAGGED and PRIO */ + {{EMAC_NONE, 0xffff0020, EMAC_NONE, EMAC_NONE}}, /* TAS Trigger List change */ + {{EMAC_NONE, 0xdfff1000, EMAC_NONE, EMAC_NONE}}, /* TAS set state ENABLE*/ + {{EMAC_NONE, 0xefff2000, EMAC_NONE, EMAC_NONE}}, /* TAS set state RESET*/ + {{EMAC_NONE, 0xcfff0000, EMAC_NONE, EMAC_NONE}}, /* TAS set state DISABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xffff0400, EMAC_NONE}}, /* UC flooding ENABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xfbff0000, EMAC_NONE}}, /* UC flooding DISABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xffff0800, EMAC_NONE}}, /* MC flooding ENABLE*/ + {{EMAC_NONE, EMAC_NONE, 0xf7ff0000, EMAC_NONE}}, /* MC flooding DISABLE*/ + {{EMAC_NONE, 0xffff4000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx ENABLE*/ + {{EMAC_NONE, 0xbfff0000, EMAC_NONE, EMAC_NONE}} /* Preemption on Tx DISABLE*/ +}; + +int emac_set_port_state(struct prueth_priv *priv, + enum icssg_port_state_cmd cmd) +{ + struct prueth *prueth = priv->prueth; + struct icssg_r30_cmd *p; + int ret = -ETIMEDOUT; + int timeout = 10; + int i; + + p = (struct icssg_r30_cmd *)(prueth->dram[priv->port_id].pa + MGR_R30_CMD_OFFSET); + + if (cmd >= ICSSG_EMAC_PORT_MAX_COMMANDS) { + dev_err(prueth->dev, "invalid port command\n"); + return -EINVAL; + } + + for (i = 0; i < 4; i++) + writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]); + + /* wait for done */ + while (timeout) { + if (emac_r30_is_done(priv)) { + ret = 0; + break; + } + + udelay(2000); + timeout--; + } + + if (ret == -ETIMEDOUT) + dev_err(prueth->dev, "timeout waiting for command done\n"); + + return ret; +} + +int icssg_send_fdb_msg(struct prueth_priv *priv, struct mgmt_cmd *cmd, + struct mgmt_cmd_rsp *rsp) +{ + struct prueth *prueth = priv->prueth; + int slice = priv->port_id; + int ret, addr; + + addr = icssg_queue_pop(prueth, slice == 0 ? + ICSSG_CMD_POP_SLICE0 : ICSSG_CMD_POP_SLICE1); + if (addr < 0) + return addr; + + /* First 4 bytes have FW owned buffer linking info which should + * not be touched + */ + memcpy_toio((void __iomem *)prueth->shram.pa + addr + 4, cmd, sizeof(*cmd)); + icssg_queue_push(prueth, slice == 0 ? + ICSSG_CMD_PUSH_SLICE0 : ICSSG_CMD_PUSH_SLICE1, addr); + ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0, + 2000, 20000000, prueth, slice == 0 ? + ICSSG_RSP_POP_SLICE0 : ICSSG_RSP_POP_SLICE1); + + if (ret) { + dev_err(prueth->dev, "Timedout sending HWQ message\n"); + return ret; + } + + memcpy_fromio(rsp, (void __iomem *)prueth->shram.pa + addr, sizeof(*rsp)); + /* Return buffer back for to pool */ + icssg_queue_push(prueth, slice == 0 ? + ICSSG_RSP_PUSH_SLICE0 : ICSSG_RSP_PUSH_SLICE1, addr); + + return 0; +} + +int emac_fdb_flow_id_updated(struct prueth_priv *priv) +{ + struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 }; + struct prueth *prueth = priv->prueth; + struct mgmt_cmd fdb_cmd = { 0 }; + int slice = priv->port_id; + int ret = 0; + + fdb_cmd.header = ICSSG_FW_MGMT_CMD_HEADER; + fdb_cmd.type = ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW; + fdb_cmd.seqnum = ++(prueth->icssg_hwcmdseq); + fdb_cmd.param = 0; + + fdb_cmd.param |= (slice << 4); + fdb_cmd.cmd_args[0] = 0; + + ret = icssg_send_fdb_msg(priv, &fdb_cmd, &fdb_cmd_rsp); + if (ret) + return ret; + + if (fdb_cmd.seqnum != fdb_cmd_rsp.seqnum) { + dev_err(prueth->dev, "seqnum doesn't match, cmd.seqnum %d != rsp.seqnum %d\n", + fdb_cmd.seqnum, fdb_cmd_rsp.seqnum); + return -EINVAL; + } + + if (fdb_cmd_rsp.status == 1) + return 0; + + return -EINVAL; +} diff --git a/drivers/net/ti/icssg_config.h b/drivers/net/ti/icssg_config.h new file mode 100644 index 00000000000..d388484c035 --- /dev/null +++ b/drivers/net/ti/icssg_config.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_CONFIG_H +#define __NET_TI_ICSSG_CONFIG_H + +struct icssg_buffer_pool_cfg { + __le32 addr; + __le32 len; +} __packed; + +struct icssg_flow_cfg { + __le16 rx_base_flow; + __le16 mgm_base_flow; +} __packed; + +/* Config area lies in shared RAM */ +#define ICSSG_CONFIG_OFFSET_SLICE0 0 +#define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 + +/* pstate speed/duplex command to set speed and duplex settings + * in firmware. + * Command format : 0x8102ssPN. ss - sequence number: currently not + * used by driver, P - port number: For switch, N - Speed/Duplex state + * - Possible values of N: + * 0x0 - 10Mbps/Half duplex ; + * 0x8 - 10Mbps/Full duplex ; + * 0x2 - 100Mbps/Half duplex; + * 0xa - 100Mbps/Full duplex; + * 0xc - 1Gbps/Full duplex; + * NOTE: The above are same as bits [3..1](slice 0) or bits [8..6](slice 1) of + * RGMII CFG register. So suggested to read the register to populate the command + * bits. + */ +#define ICSSG_PSTATE_SPEED_DUPLEX_CMD 0x81020000 +#define ICSSG_PSTATE_FULL_DUPLEX BIT(3) +#define ICSSG_PSTATE_SPEED_100 BIT(1) +#define ICSSG_PSTATE_SPEED_1000 BIT(2) + +/* Flow IDs used in config structure to firmware. Should match with + * flow_id in struct dma for rx channels. + */ +#define ICSSG_RX_CHAN_FLOW_ID 0 /* flow id for host port */ +#define ICSSG_RX_MGM_CHAN_FLOW_ID 1 /* flow id for command response */ + +/* Used to notify the FW of the current link speed */ +#define PORT_LINK_SPEED_OFFSET 0x00A8 + +#define FW_LINK_SPEED_1G (0x00) +#define FW_LINK_SPEED_100M (0x01) +#define FW_LINK_SPEED_10M (0x02) +#define FW_LINK_SPEED_HD (0x80) + +#define PRUETH_PKT_TYPE_CMD 0x10 +#define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ +#define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ +#define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ +#define PRUETH_RX_FLOW_DATA 0 /* FIXME: f/w bug to change to highest priority flow */ + +#define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K +#define PRUETH_EMAC_POOLS_PER_SLICE 24 +#define PRUETH_EMAC_BUF_POOL_START 8 +#define PRUETH_NUM_BUF_POOLS 8 +#define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ +#define MSMC_RAM_SIZE (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ + PRUETH_EMAC_RX_CTX_BUF_SIZE)) + +struct icssg_rxq_ctx { + __le32 start[3]; + __le32 end; +} __packed; + +/* Load time Fiwmware Configuration */ + +#define ICSSG_FW_MGMT_CMD_HEADER 0x81 +#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 +#define ICSSG_FW_MGMT_CMD_TYPE 0x04 +#define ICSSG_FW_MGMT_PKT 0x80000000 +#define ICSSG_FW_MGMT_FDB_CMD_TYPE_RX_FLOW 0x05 + +struct icssg_r30_cmd { + u32 cmd[4]; +} __packed; + +enum icssg_port_state_cmd { + ICSSG_EMAC_PORT_DISABLE = 0, + ICSSG_EMAC_PORT_BLOCK, + ICSSG_EMAC_PORT_FORWARD, + ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, + ICSSG_EMAC_PORT_ACCEPT_ALL, + ICSSG_EMAC_PORT_ACCEPT_TAGGED, + ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, + ICSSG_EMAC_PORT_TAS_TRIGGER, + ICSSG_EMAC_PORT_TAS_ENABLE, + ICSSG_EMAC_PORT_TAS_RESET, + ICSSG_EMAC_PORT_TAS_DISABLE, + ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, + ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, + ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, + ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, + ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, + ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, + ICSSG_EMAC_PORT_MAX_COMMANDS +}; + +#define EMAC_NONE 0xffff0000 +#define EMAC_PRU0_P_DI 0xffff0004 +#define EMAC_PRU1_P_DI 0xffff0040 +#define EMAC_TX_P_DI 0xffff0100 + +#define EMAC_PRU0_P_EN 0xfffb0000 +#define EMAC_PRU1_P_EN 0xffbf0000 +#define EMAC_TX_P_EN 0xfeff0000 + +#define EMAC_P_BLOCK 0xffff0040 +#define EMAC_TX_P_BLOCK 0xffff0200 +#define EMAC_P_UNBLOCK 0xffbf0000 +#define EMAC_TX_P_UNBLOCK 0xfdff0000 +#define EMAC_LEAN_EN 0xfff70000 +#define EMAC_LEAN_DI 0xffff0008 + +#define EMAC_ACCEPT_ALL 0xffff0001 +#define EMAC_ACCEPT_TAG 0xfffe0002 +#define EMAC_ACCEPT_PRIOR 0xfffc0000 + +/* Config area lies in DRAM */ +#define ICSSG_CONFIG_OFFSET 0x0 + +#define ICSSG_NUM_NORMAL_PDS 64 +#define ICSSG_NUM_SPECIAL_PDS 16 + +#define ICSSG_NORMAL_PD_SIZE 8 +#define ICSSG_SPECIAL_PD_SIZE 20 + +#define ICSSG_FLAG_MASK 0xff00ffff + +struct icssg_setclock_desc { + u8 request; + u8 restore; + u8 acknowledgment; + u8 cmp_status; + u32 margin; + u32 cyclecounter0_set; + u32 cyclecounter1_set; + u32 iepcount_set; + u32 rsvd1; + u32 rsvd2; + u32 CMP0_current; + u32 iepcount_current; + u32 difference; + u32 cyclecounter0_new; + u32 cyclecounter1_new; + u32 CMP0_new; +} __packed; + +struct mgmt_cmd { + u8 param; + u8 seqnum; + u8 type; + u8 header; + u32 cmd_args[3]; +} __packed; + +struct mgmt_cmd_rsp { + u32 reserved; + u8 status; + u8 seqnum; + u8 type; + u8 header; + u32 cmd_args[3]; +} __packed; + +#define ICSSG_CMD_POP_SLICE0 56 +#define ICSSG_CMD_POP_SLICE1 60 + +#define ICSSG_CMD_PUSH_SLICE0 57 +#define ICSSG_CMD_PUSH_SLICE1 61 + +#define ICSSG_RSP_POP_SLICE0 58 +#define ICSSG_RSP_POP_SLICE1 62 + +#define ICSSG_RSP_PUSH_SLICE0 56 +#define ICSSG_RSP_PUSH_SLICE1 60 + +#define ICSSG_TS_POP_SLICE0 59 +#define ICSSG_TS_POP_SLICE1 63 + +#define ICSSG_TS_PUSH_SLICE0 40 +#define ICSSG_TS_PUSH_SLICE1 41 + +#endif /* __NET_TI_ICSSG_CONFIG_H */ diff --git a/drivers/net/ti/icssg_prueth.c b/drivers/net/ti/icssg_prueth.c new file mode 100644 index 00000000000..2639f960631 --- /dev/null +++ b/drivers/net/ti/icssg_prueth.c @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments K3 AM65 PRU Ethernet Driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include <asm/io.h> +#include <asm/processor.h> +#include <clk.h> +#include <dm/lists.h> +#include <dm/device.h> +#include <dma-uclass.h> +#include <dm/of_access.h> +#include <dm/pinctrl.h> +#include <fs_loader.h> +#include <miiphy.h> +#include <net.h> +#include <phy.h> +#include <power-domain.h> +#include <linux/soc/ti/ti-udma.h> +#include <regmap.h> +#include <remoteproc.h> +#include <syscon.h> +#include <soc.h> +#include <linux/pruss_driver.h> +#include <dm/device_compat.h> + +#include "icssg_prueth.h" +#include "icss_mii_rt.h" + +#define ICSS_SLICE0 0 +#define ICSS_SLICE1 1 + +#ifdef PKTSIZE_ALIGN +#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN +#else +#define UDMA_RX_BUF_SIZE ALIGN(PKTSIZE, ARCH_DMA_MINALIGN) +#endif + +#ifdef PKTBUFSRX +#define UDMA_RX_DESC_NUM PKTBUFSRX +#else +#define UDMA_RX_DESC_NUM 4 +#endif + +/* Config region lies in shared RAM */ +#define ICSS_CONFIG_OFFSET_SLICE0 0 +#define ICSS_CONFIG_OFFSET_SLICE1 0x8000 + +/* Firmware flags */ +#define ICSS_SET_RUN_FLAG_VLAN_ENABLE BIT(0) /* switch only */ +#define ICSS_SET_RUN_FLAG_FLOOD_UNICAST BIT(1) /* switch only */ +#define ICSS_SET_RUN_FLAG_PROMISC BIT(2) /* MAC only */ +#define ICSS_SET_RUN_FLAG_MULTICAST_PROMISC BIT(3) /* MAC only */ + +/* CTRLMMR_ICSSG_RGMII_CTRL register bits */ +#define ICSSG_CTRL_RGMII_ID_MODE BIT(24) + +/* Management packet type */ +#define PRUETH_PKT_TYPE_CMD 0x10 + +/* Number of PRU Cores per Slice */ +#define ICSSG_NUM_PRU_CORES 3 + +static int icssg_gmii_select(struct prueth_priv *priv) +{ + struct phy_device *phydev = priv->phydev; + + if (phydev->interface != PHY_INTERFACE_MODE_MII && + phydev->interface < PHY_INTERFACE_MODE_RGMII && + phydev->interface > PHY_INTERFACE_MODE_RGMII_TXID) { + dev_err(priv->dev, "PHY mode unsupported %s\n", + phy_string_for_interface(phydev->interface)); + return -EINVAL; + } + + /* AM65 SR2.0 has TX Internal delay always enabled by hardware + * and it is not possible to disable TX Internal delay. The below + * switch case block describes how we handle different phy modes + * based on hardware restriction. + */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII_ID: + phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + phydev->interface = PHY_INTERFACE_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + dev_err(priv->dev, "RGMII mode without TX delay is not supported"); + return -EINVAL; + default: + break; + } + + return 0; +} + +static int icssg_phy_init(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct phy_device *phydev; + u32 supported = PHY_GBIT_FEATURES; + int ret; + + phydev = dm_eth_phy_connect(dev); + if (!phydev) { + dev_err(dev, "phy_connect() failed\n"); + return -ENODEV; + } + + /* disable unsupported features */ + supported &= ~(PHY_10BT_FEATURES | + SUPPORTED_100baseT_Half | + SUPPORTED_1000baseT_Half | + SUPPORTED_Pause | + SUPPORTED_Asym_Pause); + + phydev->supported &= supported; + phydev->advertising = phydev->supported; + priv->phydev = phydev; + + ret = icssg_gmii_select(priv); + if (ret) + goto out; + + ret = phy_config(phydev); + if (ret < 0) + dev_err(dev, "phy_config() failed: %d", ret); +out: + return ret; +} + +static void icssg_config_set_speed(struct prueth_priv *priv, int speed) +{ + struct prueth *prueth = priv->prueth; + u8 fw_speed; + + switch (speed) { + case SPEED_1000: + fw_speed = FW_LINK_SPEED_1G; + break; + case SPEED_100: + fw_speed = FW_LINK_SPEED_100M; + break; + case SPEED_10: + fw_speed = FW_LINK_SPEED_10M; + break; + default: + /* Other links speeds not supported */ + dev_err(priv->dev, "Unsupported link speed\n"); + return; + } + + writeb(fw_speed, prueth->dram[priv->port_id].pa + PORT_LINK_SPEED_OFFSET); +} + +static int icssg_update_link(struct prueth_priv *priv) +{ + struct phy_device *phy = priv->phydev; + struct prueth *prueth = priv->prueth; + bool gig_en = false, full_duplex = false; + + if (phy->link) { /* link up */ + if (phy->speed == SPEED_1000) + gig_en = true; + if (phy->duplex == DUPLEX_FULL) + full_duplex = true; + /* Set the RGMII cfg for gig en and full duplex */ + icssg_update_rgmii_cfg(prueth->miig_rt, phy->speed, full_duplex, + priv->port_id, priv); + /* update the Tx IPG based on 100M/1G speed */ + icssg_config_ipg(priv, phy->speed, priv->port_id); + + /* Send command to firmware to update Speed setting */ + icssg_config_set_speed(priv, phy->speed); + + /* Enable PORT FORWARDING */ + emac_set_port_state(priv, ICSSG_EMAC_PORT_FORWARD); + + printf("link up on port %d, speed %d, %s duplex\n", + priv->port_id, phy->speed, + (phy->duplex == DUPLEX_FULL) ? "full" : "half"); + } else { + emac_set_port_state(priv, ICSSG_EMAC_PORT_DISABLE); + printf("link down on port %d\n", priv->port_id); + } + + return phy->link; +} + +struct icssg_firmwares { + char *pru; + char *rtu; + char *txpru; +}; + +static struct icssg_firmwares icssg_emac_firmwares[] = { + { + .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + }, + { + .pru = "/lib/firmware/ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + .rtu = "/lib/firmware/ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + .txpru = "/lib/firmware/ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", + } +}; + +static int icssg_start_pru_cores(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + struct icssg_firmwares *firmwares; + struct udevice *rproc_dev = NULL; + int ret, slice; + u32 phandle; + u8 index; + + slice = priv->port_id; + index = slice * ICSSG_NUM_PRU_CORES; + firmwares = icssg_emac_firmwares; + + ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + return ret; + } + + prueth->pru_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].pru); + if (ret) + return ret; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); + return -EINVAL; + } + + ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index + 1, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + goto halt_pru; + } + + prueth->rtu_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].rtu); + if (ret) + goto halt_pru; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); + goto halt_pru; + } + + ofnode_read_u32_index(dev_ofnode(prueth->dev), "ti,prus", index + 2, &phandle); + ret = uclass_get_device_by_phandle_id(UCLASS_REMOTEPROC, phandle, &rproc_dev); + if (ret) { + dev_err(dev, "Unknown remote processor with phandle '0x%x' requested(%d)\n", + phandle, ret); + goto halt_rtu; + } + + prueth->txpru_core_id = dev_seq(rproc_dev); + ret = rproc_set_firmware(rproc_dev, firmwares[slice].txpru); + if (ret) + goto halt_rtu; + + ret = rproc_boot(rproc_dev); + if (ret) { + dev_err(dev, "failed to boot TXPRU%d: %d\n", slice, ret); + goto halt_rtu; + } + + return 0; + +halt_rtu: + rproc_stop(prueth->rtu_core_id); + +halt_pru: + rproc_stop(prueth->pru_core_id); + return ret; +} + +static int icssg_stop_pru_cores(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + + rproc_stop(prueth->pru_core_id); + rproc_stop(prueth->rtu_core_id); + rproc_stop(prueth->txpru_core_id); + + return 0; +} + +static int prueth_start(struct udevice *dev) +{ + struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; + struct eth_pdata *pdata = dev_get_plat(dev); + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + struct icssg_flow_cfg *flow_cfg; + u8 *hwaddr = pdata->enetaddr; + char chn_name[16]; + void *config; + int ret, i; + + icssg_class_set_mac_addr(prueth->miig_rt, priv->port_id, hwaddr); + icssg_ft1_set_mac_addr(prueth->miig_rt, priv->port_id, hwaddr); + icssg_class_default(prueth->miig_rt, priv->port_id, 0); + + /* Set Load time configuration */ + icssg_config(priv); + + ret = icssg_start_pru_cores(dev); + if (ret) + return ret; + + /* To differentiate channels for SLICE0 vs SLICE1 */ + snprintf(chn_name, sizeof(chn_name), "tx%d-0", priv->port_id); + + ret = dma_get_by_name(prueth->dev, chn_name, &prueth->dma_tx); + if (ret) + dev_err(dev, "TX dma get failed %d\n", ret); + + snprintf(chn_name, sizeof(chn_name), "rx%d", priv->port_id); + ret = dma_get_by_name(prueth->dev, chn_name, &prueth->dma_rx); + if (ret) + dev_err(dev, "RX dma get failed %d\n", ret); + + for (i = 0; i < UDMA_RX_DESC_NUM; i++) { + ret = dma_prepare_rcv_buf(&prueth->dma_rx, + net_rx_packets[i], + UDMA_RX_BUF_SIZE); + if (ret) + dev_err(dev, "RX dma add buf failed %d\n", ret); + } + + ret = dma_enable(&prueth->dma_tx); + if (ret) { + dev_err(dev, "TX dma_enable failed %d\n", ret); + goto tx_fail; + } + + ret = dma_enable(&prueth->dma_rx); + if (ret) { + dev_err(dev, "RX dma_enable failed %d\n", ret); + goto rx_fail; + } + + /* check if the rx_flow_id of dma_rx is as expected since + * driver hardcode that value in config struct to firmware + * in probe. Just add this sanity check to catch any change + * to rx channel assignment in the future. + */ + dma_get_cfg(&prueth->dma_rx, 0, (void **)&dma_rx_cfg_data); + config = (void *)(prueth->dram[priv->port_id].pa + ICSSG_CONFIG_OFFSET); + + flow_cfg = config + PSI_L_REGULAR_FLOW_ID_BASE_OFFSET; + writew(dma_rx_cfg_data->flow_id_base, &flow_cfg->rx_base_flow); + writew(0, &flow_cfg->mgm_base_flow); + + dev_info(dev, "K3 ICSSG: rflow_id_base: %u, chn_name = %s\n", + dma_rx_cfg_data->flow_id_base, chn_name); + + ret = emac_fdb_flow_id_updated(priv); + if (ret) { + dev_err(dev, "Failed to update Rx Flow ID %d", ret); + goto phy_fail; + } + + ret = phy_startup(priv->phydev); + if (ret) { + dev_err(dev, "phy_startup failed\n"); + goto phy_fail; + } + + ret = icssg_update_link(priv); + if (!ret) { + ret = -ENODEV; + goto phy_shut; + } + + return 0; + +phy_shut: + phy_shutdown(priv->phydev); +phy_fail: + dma_disable(&prueth->dma_rx); + dma_free(&prueth->dma_rx); +rx_fail: + dma_disable(&prueth->dma_tx); + dma_free(&prueth->dma_tx); + +tx_fail: + icssg_class_disable(prueth->miig_rt, priv->port_id); + + return ret; +} + +static int prueth_send(struct udevice *dev, void *packet, int length) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + int ret; + + ret = dma_send(&prueth->dma_tx, packet, length, NULL); + + return ret; +} + +static int prueth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + int ret; + + /* try to receive a new packet */ + ret = dma_receive(&prueth->dma_rx, (void **)packetp, NULL); + + return ret; +} + +static int prueth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + int ret = 0; + + if (length > 0) { + u32 pkt = prueth->rx_next % UDMA_RX_DESC_NUM; + + dev_dbg(dev, "%s length:%d pkt:%u\n", __func__, length, pkt); + + ret = dma_prepare_rcv_buf(&prueth->dma_rx, + net_rx_packets[pkt], + UDMA_RX_BUF_SIZE); + prueth->rx_next++; + } + + return ret; +} + +static void prueth_stop(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth = priv->prueth; + + phy_shutdown(priv->phydev); + + dma_disable(&prueth->dma_tx); + dma_disable(&prueth->dma_rx); + + icssg_stop_pru_cores(dev); + + dma_free(&prueth->dma_tx); + dma_free(&prueth->dma_rx); +} + +static const struct eth_ops prueth_ops = { + .start = prueth_start, + .send = prueth_send, + .recv = prueth_recv, + .free_pkt = prueth_free_pkt, + .stop = prueth_stop, +}; + +static int icssg_ofdata_parse_phy(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + + dev_read_u32(dev, "reg", &priv->port_id); + priv->phy_interface = dev_read_phy_mode(dev); + if (priv->phy_interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Invalid PHY mode '%s', port %u\n", + phy_string_for_interface(priv->phy_interface), + priv->port_id); + return -EINVAL; + } + + return 0; +} + +static int prueth_port_probe(struct udevice *dev) +{ + struct prueth_priv *priv = dev_get_priv(dev); + struct prueth *prueth; + char portname[15]; + int ret; + + priv->dev = dev; + prueth = dev_get_priv(dev->parent); + priv->prueth = prueth; + + sprintf(portname, "%s-%s", dev->parent->name, dev->name); + + device_set_name(dev, portname); + + ret = icssg_ofdata_parse_phy(dev); + if (ret) + goto out; + + ret = icssg_phy_init(dev); + if (ret) + goto out; + + ret = pruss_request_mem_region(prueth->pruss, + priv->port_id ? PRUSS_MEM_DRAM1 : PRUSS_MEM_DRAM0, + &prueth->dram[priv->port_id]); + if (ret) { + dev_err(dev, "could not request DRAM%d region\n", priv->port_id); + return ret; + } +out: + return ret; +} + +static int prueth_probe(struct udevice *dev) +{ + ofnode node, pruss_node, mdio_node, sram_node, curr_sram_node; + struct prueth *prueth = dev_get_priv(dev); + u32 phandle, err, sp, prev_end_addr; + struct udevice **prussdev = NULL; + ofnode eth_ports_node, eth_node; + struct udevice *port_dev; + int ret = 0; + + prueth->dev = dev; + + err = ofnode_read_u32(dev_ofnode(dev), "ti,prus", &phandle); + if (err) + return err; + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) + return -EINVAL; + + pruss_node = ofnode_get_parent(node); + ret = device_get_global_by_ofnode(pruss_node, prussdev); + if (ret) + dev_err(dev, "error getting the pruss dev\n"); + prueth->pruss = *prussdev; + + ret = pruss_request_mem_region(*prussdev, PRUSS_MEM_SHRD_RAM2, + &prueth->shram); + if (ret) + return ret; + + ret = pruss_request_tm_region(*prussdev, &prueth->tmaddr); + if (ret) + return ret; + + prueth->miig_rt = syscon_regmap_lookup_by_phandle(dev, "ti,mii-g-rt"); + if (!prueth->miig_rt) { + dev_err(dev, "couldn't get mii-g-rt syscon regmap\n"); + return -ENODEV; + } + + prueth->mii_rt = syscon_regmap_lookup_by_phandle(dev, "ti,mii-rt"); + if (!prueth->mii_rt) { + dev_err(dev, "couldn't get mii-rt syscon regmap\n"); + return -ENODEV; + } + + ret = ofnode_read_u32(dev_ofnode(dev), "sram", &sp); + if (ret) { + dev_err(dev, "sram node fetch failed %d\n", ret); + return ret; + } + + sram_node = ofnode_get_by_phandle(sp); + if (!ofnode_valid(sram_node)) + return -EINVAL; + + prev_end_addr = ofnode_get_addr(sram_node); + + ofnode_for_each_subnode(curr_sram_node, sram_node) { + u32 start_addr, size, end_addr, avail; + const char *name; + + name = ofnode_get_name(curr_sram_node); + start_addr = ofnode_get_addr(curr_sram_node); + size = ofnode_get_size(curr_sram_node); + end_addr = start_addr + size; + avail = start_addr - prev_end_addr; + + if (avail > MSMC_RAM_SIZE) + break; + + prev_end_addr = end_addr; + } + + prueth->sram_pa = prev_end_addr; + if (prueth->sram_pa % SZ_64K != 0) { + /* This is constraint for SR2.0 firmware */ + dev_err(dev, "sram address needs to be 64KB aligned\n"); + return -EINVAL; + } + dev_dbg(dev, "sram: addr %x size %x\n", prueth->sram_pa, MSMC_RAM_SIZE); + + mdio_node = ofnode_find_subnode(pruss_node, "mdio"); + prueth->mdio_base = ofnode_get_addr(mdio_node); + ofnode_read_u32(mdio_node, "bus_freq", &prueth->mdio_freq); + + ret = clk_get_by_name_nodev(mdio_node, "fck", &prueth->mdiofck); + if (ret) { + dev_err(dev, "failed to get clock %d\n", ret); + return ret; + } + + ret = clk_enable(&prueth->mdiofck); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + eth_ports_node = dev_read_subnode(dev, "ethernet-ports"); + if (!ofnode_valid(eth_ports_node)) + return -ENOENT; + + ofnode_for_each_subnode(eth_node, eth_ports_node) { + const char *node_name; + u32 port_id; + bool disabled; + + node_name = ofnode_get_name(eth_node); + disabled = !ofnode_is_enabled(eth_node); + ret = ofnode_read_u32(eth_node, "reg", &port_id); + if (ret) + dev_err(dev, "%s: error reading port_id (%d)\n", node_name, ret); + + if (port_id >= PRUETH_NUM_MACS) { + dev_err(dev, "%s: invalid port_id (%d)\n", node_name, port_id); + return -EINVAL; + } + + if (port_id < 0) + continue; + if (disabled) + continue; + + ret = device_bind_driver_to_node(dev, "prueth_port", + ofnode_get_name(eth_node), + eth_node, &port_dev); + if (ret) { + dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(eth_node)); + goto out; + } + } + + return 0; +out: + clk_disable(&prueth->mdiofck); + + return ret; +} + +static const struct udevice_id prueth_ids[] = { + { .compatible = "ti,am654-icssg-prueth" }, + { .compatible = "ti,am642-icssg-prueth" }, + { } +}; + +U_BOOT_DRIVER(prueth) = { + .name = "prueth", + .id = UCLASS_MISC, + .of_match = prueth_ids, + .probe = prueth_probe, + .priv_auto = sizeof(struct prueth), +}; + +U_BOOT_DRIVER(prueth_port) = { + .name = "prueth_port", + .id = UCLASS_ETH, + .probe = prueth_port_probe, + .ops = &prueth_ops, + .priv_auto = sizeof(struct prueth_priv), + .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/ti/icssg_prueth.h b/drivers/net/ti/icssg_prueth.h new file mode 100644 index 00000000000..c69cfd4f162 --- /dev/null +++ b/drivers/net/ti/icssg_prueth.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_PRUETH_H +#define __NET_TI_ICSSG_PRUETH_H + +#include <asm/io.h> +#include <clk.h> +#include <dm/lists.h> +#include <dm/ofnode.h> +#include <dm/device.h> +#include <dma-uclass.h> +#include <regmap.h> +#include <linux/sizes.h> +#include <linux/pruss_driver.h> +#include "icssg_config.h" +#include "icssg_switch_map.h" + +void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac); +void icssg_class_set_host_mac_addr(struct regmap *miig_rt, u8 *mac); +void icssg_class_disable(struct regmap *miig_rt, int slice); +void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti); +void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr); + +enum prueth_mac { + PRUETH_MAC0 = 0, + PRUETH_MAC1, + PRUETH_NUM_MACS, +}; + +enum prueth_port { + PRUETH_PORT_HOST = 0, /* host side port */ + PRUETH_PORT_MII0, /* physical port MII 0 */ + PRUETH_PORT_MII1, /* physical port MII 1 */ +}; + +struct prueth { + struct udevice *dev; + struct udevice *pruss; + struct regmap *miig_rt; + struct regmap *mii_rt; + fdt_addr_t mdio_base; + struct pruss_mem_region shram; + struct pruss_mem_region dram[PRUETH_NUM_MACS]; + phys_addr_t tmaddr; + struct mii_dev *bus; + u32 sram_pa; + ofnode eth_node[PRUETH_NUM_MACS]; + u32 mdio_freq; + int phy_interface; + struct clk mdiofck; + struct dma dma_tx; + struct dma dma_rx; + struct dma dma_rx_mgm; + u32 rx_next; + u32 rx_pend; + int slice; + bool mdio_manual_mode; + int speed; + int duplex; + u8 pru_core_id; + u8 rtu_core_id; + u8 txpru_core_id; + u8 icssg_hwcmdseq; +}; + +struct prueth_priv { + struct udevice *dev; + struct prueth *prueth; + u32 port_id; + struct phy_device *phydev; + bool has_phy; + ofnode phy_node; + u32 phy_addr; + int phy_interface; +}; + +/* config helpers */ +void icssg_config_ipg(struct prueth_priv *priv, int speed, int mii); +int icssg_config(struct prueth_priv *priv); +int emac_set_port_state(struct prueth_priv *priv, enum icssg_port_state_cmd cmd); + +/* Buffer queue helpers */ +int icssg_queue_pop(struct prueth *prueth, u8 queue); +void icssg_queue_push(struct prueth *prueth, int queue, u16 addr); +u32 icssg_queue_level(struct prueth *prueth, int queue); + +/* FDB helpers */ +int icssg_send_fdb_msg(struct prueth_priv *priv, struct mgmt_cmd *cmd, + struct mgmt_cmd_rsp *rsp); +int emac_fdb_flow_id_updated(struct prueth_priv *priv); + +#endif /* __NET_TI_ICSSG_PRUETH_H */ diff --git a/drivers/net/ti/icssg_queues.c b/drivers/net/ti/icssg_queues.c new file mode 100644 index 00000000000..fc4d33dbb25 --- /dev/null +++ b/drivers/net/ti/icssg_queues.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* ICSSG Buffer queue helpers + * + * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <dm/ofnode.h> +#include <regmap.h> +#include "icssg_prueth.h" + +#define ICSSG_QUEUES_MAX 64 +#define ICSSG_QUEUE_OFFSET 0xd00 +#define ICSSG_QUEUE_PEEK_OFFSET 0xe00 +#define ICSSG_QUEUE_CNT_OFFSET 0xe40 +#define ICSSG_QUEUE_RESET_OFFSET 0xf40 + +int icssg_queue_pop(struct prueth *prueth, u8 queue) +{ + u32 val, cnt; + + if (queue >= ICSSG_QUEUES_MAX) + return -EINVAL; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); + if (!cnt) + return -EINVAL; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); + + return val; +} + +void icssg_queue_push(struct prueth *prueth, int queue, u16 addr) +{ + if (queue >= ICSSG_QUEUES_MAX) + return; + + regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); +} + +u32 icssg_queue_level(struct prueth *prueth, int queue) +{ + u32 reg; + + if (queue >= ICSSG_QUEUES_MAX) + return 0; + + regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, ®); + + return reg; +} diff --git a/drivers/net/ti/icssg_switch_map.h b/drivers/net/ti/icssg_switch_map.h new file mode 100644 index 00000000000..b62c51407b8 --- /dev/null +++ b/drivers/net/ti/icssg_switch_map.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Texas Instruments ICSSG Ethernet driver + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __NET_TI_ICSSG_SWITCH_MAP_H +#define __NET_TI_ICSSG_SWITCH_MAP_H + +/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/ +#define FDB_AGEING_TIMEOUT_OFFSET 0x0014 + +/*default VLAN tag for Host Port*/ +#define HOST_PORT_DF_VLAN_OFFSET 0x001C + +/*Same as HOST_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P1 Port*/ +#define P1_PORT_DF_VLAN_OFFSET 0x0020 + +/*Same as P1_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET + +/*default VLAN tag for P2 Port*/ +#define P2_PORT_DF_VLAN_OFFSET 0x0024 + +/*Same as P2_PORT_DF_VLAN_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET + +/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/ +#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 + +/*VLAN-FID Table offset for EMAC*/ +#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_HI 0x2104 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC0_LO 0x2F6C + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_HI 0x3DD4 + +/*packet descriptor Q reserved memory*/ +#define PORT_DESC1_LO 0x4C3C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_HI 0x5AA4 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC0_LO 0x5F0C + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_HI 0x6374 + +/*packet descriptor Q reserved memory*/ +#define HOST_DESC1_LO 0x67DC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD0 0x7AAC + +/*special packet descriptor Q reserved memory*/ +#define HOST_SPPD1 0x7EAC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC + +/*IEP count hi roll over count*/ +#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 + +/*Set clock descriptor*/ +#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 + +/*_Small_Description_*/ +#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 + +/*Control variable to generate SYNC1*/ +#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C + +/*SystemTime Sync0 periodicity*/ +#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 + +/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454 + +/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/ +#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458 + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C + +/*Set clock operation done signal for next task*/ +#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 + +/*New list is copied at this time*/ +#define TAS_CONFIG_CHANGE_TIME 0x000C + +/*config change error counter*/ +#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014 + +/*TAS List update pending flag*/ +#define TAS_CONFIG_PENDING 0x0018 + +/*TAS list update trigger flag*/ +#define TAS_CONFIG_CHANGE 0x0019 + +/*List length for new TAS schedule*/ +#define TAS_ADMIN_LIST_LENGTH 0x001A + +/*Currently active TAS list index*/ +#define TAS_ACTIVE_LIST_INDEX 0x001B + +/*Cycle time for the new TAS schedule*/ +#define TAS_ADMIN_CYCLE_TIME 0x001C + +/*Cycle counts remaining till the TAS list update*/ +#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020 + +/*Base Flow ID for sending packets to Host for Slice0*/ +#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024 + +/*Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET + +/*Base Flow ID for sending mgmt and Tx TS to Host for Slice0*/ +#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026 + +/*Same as PSI_L_MGMT_FLOW_ID_OFFSET*/ +#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET + +/*Queue number for Special packets written here*/ +#define SPL_PKT_DEFAULT_PRIORITY 0x0028 + +/*Express Preemptible Queue Mask*/ +#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029 + +/*Port1/Port2 Default Queue number for untagged packets, only 1B is used*/ +#define QUEUE_NUM_UNTAGGED 0x002A + +/*Stores the table used for priority regeneration. 1B per PCP/Queue*/ +#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C + +/* For marking Packet as priority/express (this feature is disabled) or + * cut-through/S&F. + */ +#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034 + +/*Stores the table used for priority mapping. 1B per PCP/Queue*/ +#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C + +/*TAS gate mask for windows list0*/ +#define TAS_GATE_MASK_LIST0 0x0100 + +/*TAS gate mask for windows list1*/ +#define TAS_GATE_MASK_LIST1 0x0350 + +/*Memory to Enable/Disable Preemption on TX side*/ +#define PRE_EMPTION_ENABLE_TX 0x05A0 + +/*Active State of Preemption on TX side*/ +#define PRE_EMPTION_ACTIVE_TX 0x05A1 + +/*Memory to Enable/Disable Verify State Machine Preemption*/ +#define PRE_EMPTION_ENABLE_VERIFY 0x05A2 + +/*Verify Status of State Machine*/ +#define PRE_EMPTION_VERIFY_STATUS 0x05A3 + +/*Non Final Fragment Size supported by Link Partner*/ +#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4 + +/*Non Final Fragment Size supported by Firmware*/ +#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6 + +/*Time in ms the State machine waits for respond packet*/ +#define PRE_EMPTION_VERIFY_TIME 0x05A8 + +/*Memory used for R30 related management commands*/ +#define MGR_R30_CMD_OFFSET 0x05AC + +/*HW Buffer Pool0 base address*/ +#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC + +/*16B for Host Egress MSMC Q (Pre-emptible) context*/ +#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684 + +/*Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL*/ +#define FDB_CMD_BUFFER 0x0894 + +/*16B for Host Egress MSMC Q (Express) context*/ +#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940 + +/*Start of 32 bits PA_STAT counters*/ +#define PA_STAT_32b_START_OFFSET 0x0080 + +#endif +/* __NET_TI_ICSSG_SWITCH_MAP_H */ diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805a..b9fe608c279 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -12,6 +12,21 @@ config PHY_QCOM_IPQ4019_USB help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. +config PHY_QCOM_QUSB2 + tristate "Qualcomm USB QUSB2 PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. + +config PHY_QCOM_USB_SNPS_FEMTO_V2 + tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare Core 7nm + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. + config PHY_QCOM_USB_HS_28NM tristate "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 2113f178c0c..5f4db4a5378 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,4 +1,6 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o +obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c new file mode 100644 index 00000000000..c91ba18c4ab --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <dm.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <reset.h> +#include <clk.h> +#include <linux/delay.h> + +#include <dt-bindings/phy/phy-qcom-qusb2.h> + +#define QUSB2PHY_PLL 0x0 +#define QUSB2PHY_PLL_TEST 0x04 +#define CLK_REF_SEL BIT(7) + +#define QUSB2PHY_PLL_TUNE 0x08 +#define QUSB2PHY_PLL_USER_CTL1 0x0c +#define QUSB2PHY_PLL_USER_CTL2 0x10 +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c +#define QUSB2PHY_PLL_PWR_CTRL 0x18 + +/* QUSB2PHY_PLL_STATUS register bits */ +#define PLL_LOCKED BIT(5) + +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + +/* QUSB2PHY_PORT_POWERDOWN register bits */ +#define CLAMP_N_EN BIT(5) +#define FREEZIO_N BIT(1) +#define POWER_DOWN BIT(0) + +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + +#define QUSB2PHY_REFCLK_ENABLE BIT(0) + +#define PHY_CLK_SCHEME_SEL BIT(0) + +/* QUSB2PHY_INTR_CTRL register bits */ +#define DMSE_INTR_HIGH_SEL BIT(4) +#define DPSE_INTR_HIGH_SEL BIT(3) +#define CHG_DET_INTR_EN BIT(2) +#define DMSE_INTR_EN BIT(1) +#define DPSE_INTR_EN BIT(0) + +/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ +#define CORE_PLL_EN_FROM_RESET BIT(4) +#define CORE_RESET BIT(5) +#define CORE_RESET_MUX BIT(6) + +/* QUSB2PHY_IMP_CTRL1 register bits */ +#define IMP_RES_OFFSET_MASK GENMASK(5, 0) +#define IMP_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + +/* QUSB2PHY_PORT_TUNE1 register bits */ +#define HSTX_TRIM_MASK GENMASK(7, 4) +#define HSTX_TRIM_SHIFT 0x4 +#define PREEMPH_WIDTH_HALF_BIT BIT(2) +#define PREEMPHASIS_EN_MASK GENMASK(1, 0) +#define PREEMPHASIS_EN_SHIFT 0x0 + +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 +#define QUSB2PHY_PWR_CTRL2 0x214 +#define QUSB2PHY_IMP_CTRL1 0x220 +#define QUSB2PHY_IMP_CTRL2 0x224 +#define QUSB2PHY_CHG_CTRL2 0x23c + +struct qusb2_phy_init_tbl { + unsigned int offset; + unsigned int val; + /* + * register part of layout ? + * if yes, then offset gives index in the reg-layout + */ + int in_layout; +}; + +struct qusb2_phy_cfg { + const struct qusb2_phy_init_tbl *tbl; + /* number of entries in the table */ + unsigned int tbl_num; + /* offset to PHY_CLK_SCHEME register in TCSR map */ + unsigned int clk_scheme_offset; + + /* array of registers with different offsets */ + const unsigned int *regs; + unsigned int mask_core_ready; + unsigned int disable_ctrl; + unsigned int autoresume_en; + + /* true if PHY has PLL_TEST register to select clk_scheme */ + bool has_pll_test; + + /* true if TUNE1 register must be updated by fused value, else TUNE2 */ + bool update_tune1_with_efuse; + + /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ + bool has_pll_override; +}; + +/* set of registers with offsets different per-PHY */ +enum qusb2phy_reg_layout { + QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, + QUSB2PHY_PLL_STATUS, + QUSB2PHY_PORT_TUNE1, + QUSB2PHY_PORT_TUNE2, + QUSB2PHY_PORT_TUNE3, + QUSB2PHY_PORT_TUNE4, + QUSB2PHY_PORT_TUNE5, + QUSB2PHY_PORT_TEST1, + QUSB2PHY_PORT_TEST2, + QUSB2PHY_PORT_POWERDOWN, + QUSB2PHY_INTR_CTRL, +}; + +#define QUSB2_PHY_INIT_CFG(o, v) \ + { \ + .offset = o, .val = v, \ + } + +#define QUSB2_PHY_INIT_CFG_L(o, v) \ + { \ + .offset = o, .val = v, .in_layout = 1, \ + } + +static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + +static const unsigned int sm6115_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0xb8, [QUSB2PHY_PORT_TEST2] = 0x9c, + [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, +}; + +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + +static const unsigned int qusb2_v2_regs_layout[] = { + [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, + [QUSB2PHY_PLL_STATUS] = 0x1a0, + [QUSB2PHY_PORT_TUNE1] = 0x240, + [QUSB2PHY_PORT_TUNE2] = 0x244, + [QUSB2PHY_PORT_TUNE3] = 0x248, + [QUSB2PHY_PORT_TUNE4] = 0x24c, + [QUSB2PHY_PORT_TUNE5] = 0x250, + [QUSB2PHY_PORT_TEST1] = 0x254, + [QUSB2PHY_PORT_TEST2] = 0x258, + [QUSB2PHY_PORT_POWERDOWN] = 0x210, + [QUSB2PHY_INTR_CTRL] = 0x230, +}; + +static const struct qusb2_phy_cfg sm6115_phy_cfg = { + .tbl = sm6115_init_tbl, + .tbl_num = ARRAY_SIZE(sm6115_init_tbl), + .regs = sm6115_regs_layout, + + .has_pll_test = true, + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(3), +}; + +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, + .has_pll_override = true, + .autoresume_en = BIT(0), + .update_tune1_with_efuse = true, +}; + +/** + * struct qusb2_phy - structure holding qusb2 phy attributes + * + * @phy: generic phy + * @base: iomapped memory space for qubs2 phy + * + * @cfg_ahb_clk: AHB2PHY interface clock + * @phy_rst: phy reset control + * + * @cfg: phy config data + * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme + */ +struct qusb2_phy { + struct phy *phy; + void __iomem *base; + + struct clk cfg_ahb_clk; + struct reset_ctl phy_rst; + + const struct qusb2_phy_cfg *cfg; + bool has_se_clk_scheme; +}; + +static inline void qusb2_phy_configure(void __iomem *base, + const unsigned int *regs, + const struct qusb2_phy_init_tbl tbl[], + int num) +{ + int i; + + for (i = 0; i < num; i++) { + if (tbl[i].in_layout) + writel(tbl[i].val, base + regs[tbl[i].offset]); + else + writel(tbl[i].val, base + tbl[i].offset); + } +} + +static int qusb2phy_do_reset(struct qusb2_phy *qphy) +{ + int ret; + + ret = reset_assert(&qphy->phy_rst); + if (ret) + return ret; + + udelay(500); + + ret = reset_deassert(&qphy->phy_rst); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_power_on(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + const struct qusb2_phy_cfg *cfg = qphy->cfg; + int ret; + u32 val; + + ret = qusb2phy_do_reset(qphy); + if (ret) + return ret; + + /* Disable the PHY */ + setbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + if (cfg->has_pll_test) { + /* save reset value to override reference clock scheme later */ + val = readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num); + + /* Enable the PHY */ + clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN], + POWER_DOWN); + + /* Required to get phy pll lock successfully */ + udelay(150); + + if (cfg->has_pll_test) { + val |= CLK_REF_SEL; + + writel(val, qphy->base + QUSB2PHY_PLL_TEST); + + /* ensure above write is through */ + readl(qphy->base + QUSB2PHY_PLL_TEST); + } + + /* Required to get phy pll lock successfully */ + udelay(100); + + val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); + if (!(val & cfg->mask_core_ready)) { + pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val); + ret = -EBUSY; + return ret; + } + + return 0; +} + +static int qusb2phy_power_off(struct phy *phy) +{ + struct qusb2_phy *qphy = dev_get_priv(phy->dev); + + /* Disable the PHY */ + setbits_le32(qphy->base + qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], + qphy->cfg->disable_ctrl); + + reset_assert(&qphy->phy_rst); + + clk_disable(&qphy->cfg_ahb_clk); + + return 0; +} + +static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy) +{ + int ret; + + /* We ignore the ref clock as we currently lack a driver for rpmcc/rpmhcc where + * it usually comes from - we assume it's always on. + */ + ret = clk_get_by_name(dev, "cfg_ahb", &qphy->cfg_ahb_clk); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable(&qphy->cfg_ahb_clk); + if (ret) + return ret; + + return 0; +} + +static int qusb2phy_probe(struct udevice *dev) +{ + struct qusb2_phy *qphy = dev_get_priv(dev); + int ret; + + qphy->base = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + ret = qusb2phy_clk_init(dev, qphy); + if (ret) { + printf("%s: Couldn't get clocks: %d\n", __func__, ret); + return ret; + } + + ret = reset_get_by_index(dev, 0, &qphy->phy_rst); + if (ret) { + printf("%s: Couldn't get resets: %d\n", __func__, ret); + return ret; + } + + qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev); + if (!qphy->cfg) { + printf("%s: Couldn't get driver data\n", __func__); + return -EINVAL; + } + + debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg); + return 0; +} + +static struct phy_ops qusb2phy_ops = { + .power_on = qusb2phy_power_on, + .power_off = qusb2phy_power_off, +}; + +static const struct udevice_id qusb2phy_ids[] = { + { .compatible = "qcom,qusb2-phy" }, + { .compatible = "qcom,qcm2290-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,sm6115-qusb2-phy", + .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg }, + {} +}; + +U_BOOT_DRIVER(qcom_qusb2_phy) = { + .name = "qcom-qusb2-phy", + .id = UCLASS_PHY, + .of_match = qusb2phy_ids, + .ops = &qusb2phy_ops, + .probe = qusb2phy_probe, + .priv_auto = sizeof(struct qusb2_phy), +}; diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c new file mode 100644 index 00000000000..a1675b664e4 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org> + * + * Based on Linux driver + */ + +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <generic-phy.h> +#include <malloc.h> +#include <reset.h> + +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) +#define SLEEPM BIT(0) +#define OPMODE_MASK GENMASK(4, 3) +#define OPMODE_NORMAL (0x00) +#define OPMODE_NONDRIVING BIT(3) +#define TERMSEL BIT(5) + +#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) +#define POR BIT(1) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) +#define SIDDQ BIT(2) +#define RETENABLEN BIT(3) +#define FSEL_MASK GENMASK(6, 4) +#define FSEL_DEFAULT (0x3 << 4) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) +#define VREGBYPASS BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) +#define VBUSVLDEXT0 BIT(0) + +#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) +#define USB2_AUTO_RESUME BIT(0) +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define USB2_PHY_USB_PHY_CFG0 (0x94) +#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +struct qcom_snps_hsphy { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +/* + * We should just be able to use clrsetbits_le32() here, but this results + * in crashes on some boards. This is suspected to be because of some bus + * arbitration quirks with the PHY (i.e. it takes several bus clock cycles + * for the write to actually go through). The readl_relaxed() at the end will + * block until the write is completed (and all registers updated), and thus + * ensure that we don't access the PHY registers when they're in an + * undetermined state. + */ +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, + u32 mask, u32 val) +{ + u32 reg; + + reg = readl_relaxed(base + offset); + + reg &= ~mask; + reg |= val & mask; + writel_relaxed(reg, base + offset); + + /* Ensure above write is completed */ + readl_relaxed(base + offset); +} + +static int qcom_snps_hsphy_usb_init(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + POR); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + PLLBTUNE, PLLBTUNE); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTRL, + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, + VBUSVLDEXT0, VBUSVLDEXT0); + + qcom_snps_hsphy_write_mask(priv->base, + USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, + VREGBYPASS, VREGBYPASS); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL0, + SLEEPM, SLEEPM); + + qcom_snps_hsphy_write_mask( + priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR, + 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL, 0); + + qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + return 0; +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + int ret; + + clk_enable_bulk(&priv->clks); + + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + ret = qcom_snps_hsphy_usb_init(phy); + if (ret) + return ret; + + return 0; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev); + + reset_assert_bulk(&priv->resets); + clk_disable_bulk(&priv->clks); + + return 0; +} + +static int qcom_snps_hsphy_phy_probe(struct udevice *dev) +{ + struct qcom_snps_hsphy *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = clk_get_bulk(dev, &priv->clks); + if (ret < 0 && ret != -ENOENT) { + printf("%s: Failed to get clocks %d\n", __func__, ret); + return ret; + } + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) { + printf("failed to get resets, ret = %d\n", ret); + return ret; + } + + clk_enable_bulk(&priv->clks); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static struct phy_ops qcom_snps_hsphy_phy_ops = { + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, +}; + +static const struct udevice_id qcom_snps_hsphy_phy_ids[] = { + { .compatible = "qcom,sm8150-usb-hs-phy" }, + { .compatible = "qcom,usb-snps-hs-5nm-phy" }, + { .compatible = "qcom,usb-snps-hs-7nm-phy" }, + { .compatible = "qcom,usb-snps-femto-v2-phy" }, + {} +}; + +U_BOOT_DRIVER(qcom_usb_qcom_snps_hsphy) = { + .name = "qcom-snps-hsphy", + .id = UCLASS_PHY, + .of_match = qcom_snps_hsphy_phy_ids, + .ops = &qcom_snps_hsphy_phy_ops, + .probe = qcom_snps_hsphy_phy_probe, + .priv_auto = sizeof(struct qcom_snps_hsphy), +}; diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index db0e2124684..a9a00f4b081 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -49,7 +49,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev, } } -static unsigned int apq8016_get_function_mux(unsigned int selector) +static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index 880df8fe3c7..9697cb5beb7 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -44,7 +44,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev, } } -static unsigned int apq8096_get_function_mux(unsigned int selector) +static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 74c04ab87cd..44792303133 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -40,7 +40,8 @@ static const char *ipq4019_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int ipq4019_get_function_mux(unsigned int selector) +static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index ee0624df296..909e566acf5 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -83,14 +83,14 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, unsigned int func_selector) { struct msm_pinctrl_priv *priv = dev_get_priv(dev); + u32 func = priv->data->get_function_mux(pin_selector, func_selector); /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(&priv->data->pin_data, pin_selector)) return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, - priv->data->get_function_mux(func_selector) << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h index 07f2eae9bae..49b7bfbc001 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.h +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h @@ -18,7 +18,8 @@ struct msm_pinctrl_data { int functions_count; const char *(*get_function_name)(struct udevice *dev, unsigned int selector); - unsigned int (*get_function_mux)(unsigned int selector); + unsigned int (*get_function_mux)(unsigned int pin, + unsigned int selector); const char *(*get_pin_name)(struct udevice *dev, unsigned int selector); }; diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 3a2d4685997..4b7c670c90b 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -94,7 +94,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev, } } -static unsigned int qcs404_get_function_mux(unsigned int selector) +static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 76bd8c4ef41..459a4329ec8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -70,7 +70,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev, return pin_name; } -static unsigned int sdm845_get_function_mux(unsigned int selector) +static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) { return msm_pinctrl_functions[selector].val; } diff --git a/drivers/rtc/goldfish_rtc.c b/drivers/rtc/goldfish_rtc.c index 1ace9903858..3231eb0daf8 100644 --- a/drivers/rtc/goldfish_rtc.c +++ b/drivers/rtc/goldfish_rtc.c @@ -72,7 +72,7 @@ static int goldfish_rtc_set(struct udevice *dev, const struct rtc_time *time) return 0; } -int goldfish_rtc_probe(struct udevice *dev) +static int goldfish_rtc_probe(struct udevice *dev) { struct goldfish_rtc *priv = dev_get_priv(dev); fdt_addr_t addr; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index e5c3dcffc1c..5260474fb9a 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -603,7 +603,20 @@ U_BOOT_DRIVER(serial_msm_geni) = { .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops, - .flags = DM_FLAG_PRE_RELOC, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; + +static const struct udevice_id geniqup_ids[] = { + { .compatible = "qcom,geni-se-qup" }, + { } +}; + +U_BOOT_DRIVER(geni_se_qup) = { + .name = "geni-se-qup", + .id = UCLASS_NOP, + .of_match = geniqup_ids, + .bind = dm_scan_fdt_dev, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, }; #ifdef CONFIG_DEBUG_UART_MSM_GENI diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index b6197da97cc..35df413321f 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -23,7 +23,7 @@ #define ULITE_CONTROL_RST_TX 0x01 #define ULITE_CONTROL_RST_RX 0x02 -static bool little_endian; +static bool little_endian __section(".data"); struct uartlite { unsigned int rx_fifo; diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 786825d920c..d8b4f172a39 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -44,6 +44,7 @@ enum { ZYNQMP_VARIANT_DR = BIT(3), ZYNQMP_VARIANT_DR_SE = BIT(4), ZYNQMP_VARIANT_EG_SE = BIT(5), + ZYNQMP_VARIANT_TEG = BIT(6), }; struct zynqmp_device { @@ -75,6 +76,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, }, { + .id = 0x04718093, + .device = 3, + .variants = ZYNQMP_VARIANT_TEG, + }, + { .id = 0x04721093, .device = 4, .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG | @@ -299,6 +305,8 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, strlcat(priv->machine, "dr", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_TEG) { + strlcat(priv->machine, "teg", sizeof(priv->machine)); } return 0; diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c index 5fc05c46cb0..0de132633a8 100644 --- a/drivers/sysreset/sysreset-ti-sci.c +++ b/drivers/sysreset/sysreset-ti-sci.c @@ -60,15 +60,9 @@ static struct sysreset_ops ti_sci_sysreset_ops = { .request = ti_sci_sysreset_request, }; -static const struct udevice_id ti_sci_sysreset_of_match[] = { - { .compatible = "ti,sci-sysreset", }, - { /* sentinel */ }, -}; - U_BOOT_DRIVER(ti_sci_sysreset) = { .name = "ti-sci-sysreset", .id = UCLASS_SYSRESET, - .of_match = ti_sci_sysreset_of_match, .probe = ti_sci_sysreset_probe, .priv_auto = sizeof(struct ti_sci_sysreset_data), .ops = &ti_sci_sysreset_ops, diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6f319ba0d54..39c82521be1 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -180,6 +180,7 @@ config CONSOLE_ROTATION config CONSOLE_TRUETYPE bool "Support a console that uses TrueType fonts" + select X86_HARDFP if X86 help TrueTrype fonts can provide outline-drawing capability rather than needing to provide a bitmap for each font and size that is needed. diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index 362458aecd4..28665a32757 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -8,6 +8,7 @@ #include <dm.h> #include <log.h> #include <malloc.h> +#include <spl.h> #include <video.h> #include <video_console.h> @@ -802,6 +803,9 @@ static int truetype_entry_save(struct udevice *dev, struct abuf *buf) struct console_tt_store store; const uint size = sizeof(store); + if (spl_phase() <= PHASE_SPL) + return -ENOSYS; + /* * store the whole priv structure as it is simpler that picking out * what we need @@ -823,6 +827,9 @@ static int truetype_entry_restore(struct udevice *dev, struct abuf *buf) struct console_tt_priv *priv = dev_get_priv(dev); struct console_tt_store store; + if (spl_phase() <= PHASE_SPL) + return -ENOSYS; + memcpy(&store, abuf_data(buf), sizeof(store)); vc_priv->xcur_frac = store.cur.xpos_frac; @@ -847,6 +854,9 @@ static int truetype_set_cursor_visible(struct udevice *dev, bool visible, uint out, val; int ret; + if (spl_phase() <= PHASE_SPL) + return -ENOSYS; + if (!visible) return 0; diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 5f89f6a5219..5d06e51ff23 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -126,6 +126,7 @@ void vidconsole_set_cursor_pos(struct udevice *dev, int x, int y) priv->xcur_frac = VID_TO_POS(x); priv->xstart_frac = priv->xcur_frac; priv->ycur = y; + vidconsole_entry_start(dev); } /** @@ -135,8 +136,10 @@ void vidconsole_set_cursor_pos(struct udevice *dev, int x, int y) * @row: new row * @col: new column */ -static void set_cursor_position(struct vidconsole_priv *priv, int row, int col) +static void set_cursor_position(struct udevice *dev, int row, int col) { + struct vidconsole_priv *priv = dev_get_uclass_priv(dev); + /* * Ensure we stay in the bounds of the screen. */ @@ -145,9 +148,7 @@ static void set_cursor_position(struct vidconsole_priv *priv, int row, int col) if (col >= priv->cols) col = priv->cols - 1; - priv->ycur = row * priv->y_charsize; - priv->xcur_frac = priv->xstart_frac + - VID_TO_POS(col * priv->x_charsize); + vidconsole_position_cursor(dev, col, row); } /** @@ -194,7 +195,7 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) int row = priv->row_saved; int col = priv->col_saved; - set_cursor_position(priv, row, col); + set_cursor_position(dev, row, col); priv->escape = 0; return; } @@ -256,7 +257,7 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) if (row < 0) row = 0; /* Right and bottom overflows are handled in the callee. */ - set_cursor_position(priv, row, col); + set_cursor_position(dev, row, col); break; } case 'H': @@ -280,7 +281,7 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) if (col) --col; - set_cursor_position(priv, row, col); + set_cursor_position(dev, row, col); break; } diff --git a/env/Kconfig b/env/Kconfig index 7885c8bf831..1f8e90af55e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -472,7 +472,7 @@ config ENV_FAT_DEVICE_AND_PART string "Device and partition for where to store the environemt in FAT" depends on ENV_IS_IN_FAT default "0:1" if TI_COMMON_CMD_OPTIONS - default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL + default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET default ":auto" if ARCH_SUNXI default "0" if ARCH_AT91 help diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 365c5147c4b..2ff0dca2495 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -765,11 +765,6 @@ int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags) struct ext2_inode *first_inode = NULL; struct ext2_inode temp_inode; - if (*dirname != '/') { - printf("Please supply Absolute path\n"); - return -1; - } - /* TODO: input validation make equivalent to linux */ depth_dirname = zalloc(strlen(dirname) + 1); if (!depth_dirname) diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index 1a340b4764c..e80f797c8dc 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -430,7 +430,7 @@ int ext4fs_check_journal_state(int recovery_flag) printf("Recovery required\n"); } else { if (recovery_flag == RECOVER) - printf("File System is consistent\n"); + log_debug("File System is consistent\n"); goto end; } diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index ea4c5d4157c..d057f6b5a79 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -847,6 +847,7 @@ int ext4fs_write(const char *fname, const char *buffer, { int ret = 0; struct ext2_inode *file_inode = NULL; + struct ext2_inode *existing_file_inode = NULL; unsigned char *inode_buffer = NULL; int parent_inodeno; int inodeno; @@ -900,6 +901,15 @@ int ext4fs_write(const char *fname, const char *buffer, /* check if the filename is already present in root */ existing_file_inodeno = ext4fs_filename_unlink(filename); if (existing_file_inodeno != -1) { + existing_file_inode = (struct ext2_inode *)zalloc(fs->inodesz); + if (!existing_file_inode) + goto fail; + ret = ext4fs_iget(existing_file_inodeno, existing_file_inode); + if (ret) { + free(existing_file_inode); + goto fail; + } + ret = ext4fs_delete_file(existing_file_inodeno); fs->first_pass_bbmap = 0; fs->curr_blkno = 0; @@ -948,9 +958,15 @@ int ext4fs_write(const char *fname, const char *buffer, sizebytes = 0; } } else { - file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | S_IRGRP | - S_IROTH | S_IXGRP | S_IXOTH); + if (existing_file_inode) { + file_inode->mode = existing_file_inode->mode; + } else { + file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | S_IRGRP | + S_IROTH | S_IXGRP | S_IXOTH); + } } + if (existing_file_inode) + free(existing_file_inode); /* ToDo: Update correct time */ file_inode->mtime = cpu_to_le32(timestamp); file_inode->atime = cpu_to_le32(timestamp); diff --git a/include/bootm.h b/include/bootm.h index 9e0f8d60de0..6983375ff8b 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -273,21 +273,24 @@ int bootm_process_cmdline(char *buf, int maxlen, int flags); int bootm_process_cmdline_env(int flags); /** - * zboot_start() - Boot a zimage + * zboot_run() - Run through the various steps to boot a zimage * * Boot a zimage, given the component parts * * @addr: Address where the bzImage is moved before booting, either * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR - * @base: Pointer to the boot parameters, typically at address - * DEFAULT_SETUP_BASE + * @size: Size of bzImage, or 0 to detect this * @initrd: Address of the initial ramdisk, or 0 if none * @initrd_size: Size of the initial ramdisk, or 0 if none - * @cmdline: Command line to use for booting + * @base_addr: If non-zero, this indicates that the boot parameters have already + * been loaded by the caller to this address, so the load_zimage() call + * in zboot_load() will be skipped when booting + * @cmdline: If non-NULL, the environment variable containing the command line + * to use for booting * Return: -EFAULT on error (normally it does not return) */ -int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size, - ulong base, char *cmdline); +int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size, + ulong base, char *cmdline); /* * zimage_get_kernel_version() - Get the version string from a kernel @@ -314,7 +317,7 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); * bootm_boot_start() - Boot an image at the given address * * @addr: Image address - * @cmdline: Command line to set + * @cmdline: Command line to set, NULL for default */ int bootm_boot_start(ulong addr, const char *cmdline); diff --git a/include/configs/jethub.h b/include/configs/jethub.h index e22db4991de..2c44bfc853e 100644 --- a/include/configs/jethub.h +++ b/include/configs/jethub.h @@ -11,7 +11,7 @@ #if defined(CONFIG_MESON_AXG) #define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ "bootcmd_rescue=" \ - "if gpio input 10; then " \ + "if gpio input periphs-banks10; then " \ "run bootcmd_mmc0; " \ "run bootcmd_usb0;" \ "fi;\0" diff --git a/include/configs/meson64.h b/include/configs/meson64.h index efab9a624dc..65fa5f3d6dd 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -120,6 +120,12 @@ #include <config_distro_bootcmd.h> +#ifdef CONFIG_OF_UPSTREAM +#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ @@ -133,7 +139,7 @@ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "fdtfile=" FDTFILE_NAME "\0" \ "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x4000000 \0" \ BOOTENV #endif diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h deleted file mode 100644 index 25bb1fffa97..00000000000 --- a/include/dt-bindings/gpio/meson-axg-gpio.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H -#define _DT_BINDINGS_MESON_AXG_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define BOOT_0 11 -#define BOOT_1 12 -#define BOOT_2 13 -#define BOOT_3 14 -#define BOOT_4 15 -#define BOOT_5 16 -#define BOOT_6 17 -#define BOOT_7 18 -#define BOOT_8 19 -#define BOOT_9 20 -#define BOOT_10 21 -#define BOOT_11 22 -#define BOOT_12 23 -#define BOOT_13 24 -#define BOOT_14 25 -#define GPIOA_0 26 -#define GPIOA_1 27 -#define GPIOA_2 28 -#define GPIOA_3 29 -#define GPIOA_4 30 -#define GPIOA_5 31 -#define GPIOA_6 32 -#define GPIOA_7 33 -#define GPIOA_8 34 -#define GPIOA_9 35 -#define GPIOA_10 36 -#define GPIOA_11 37 -#define GPIOA_12 38 -#define GPIOA_13 39 -#define GPIOA_14 40 -#define GPIOA_15 41 -#define GPIOA_16 42 -#define GPIOA_17 43 -#define GPIOA_18 44 -#define GPIOA_19 45 -#define GPIOA_20 46 -#define GPIOX_0 47 -#define GPIOX_1 48 -#define GPIOX_2 49 -#define GPIOX_3 50 -#define GPIOX_4 51 -#define GPIOX_5 52 -#define GPIOX_6 53 -#define GPIOX_7 54 -#define GPIOX_8 55 -#define GPIOX_9 56 -#define GPIOX_10 57 -#define GPIOX_11 58 -#define GPIOX_12 59 -#define GPIOX_13 60 -#define GPIOX_14 61 -#define GPIOX_15 62 -#define GPIOX_16 63 -#define GPIOX_17 64 -#define GPIOX_18 65 -#define GPIOX_19 66 -#define GPIOX_20 67 -#define GPIOX_21 68 -#define GPIOX_22 69 -#define GPIOY_0 70 -#define GPIOY_1 71 -#define GPIOY_2 72 -#define GPIOY_3 73 -#define GPIOY_4 74 -#define GPIOY_5 75 -#define GPIOY_6 76 -#define GPIOY_7 77 -#define GPIOY_8 78 -#define GPIOY_9 79 -#define GPIOY_10 80 -#define GPIOY_11 81 -#define GPIOY_12 82 -#define GPIOY_13 83 -#define GPIOY_14 84 -#define GPIOY_15 85 - -#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h deleted file mode 100644 index f7bd69350d1..00000000000 --- a/include/dt-bindings/gpio/meson-g12a-gpio.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - */ - -#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H -#define _DT_BINDINGS_MESON_G12A_GPIO_H - -/* First GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOE_0 12 -#define GPIOE_1 13 -#define GPIOE_2 14 - -/* Second GPIO chip */ -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define BOOT_0 25 -#define BOOT_1 26 -#define BOOT_2 27 -#define BOOT_3 28 -#define BOOT_4 29 -#define BOOT_5 30 -#define BOOT_6 31 -#define BOOT_7 32 -#define BOOT_8 33 -#define BOOT_9 34 -#define BOOT_10 35 -#define BOOT_11 36 -#define BOOT_12 37 -#define BOOT_13 38 -#define BOOT_14 39 -#define BOOT_15 40 -#define GPIOC_0 41 -#define GPIOC_1 42 -#define GPIOC_2 43 -#define GPIOC_3 44 -#define GPIOC_4 45 -#define GPIOC_5 46 -#define GPIOC_6 47 -#define GPIOC_7 48 -#define GPIOA_0 49 -#define GPIOA_1 50 -#define GPIOA_2 51 -#define GPIOA_3 52 -#define GPIOA_4 53 -#define GPIOA_5 54 -#define GPIOA_6 55 -#define GPIOA_7 56 -#define GPIOA_8 57 -#define GPIOA_9 58 -#define GPIOA_10 59 -#define GPIOA_11 60 -#define GPIOA_12 61 -#define GPIOA_13 62 -#define GPIOA_14 63 -#define GPIOA_15 64 -#define GPIOX_0 65 -#define GPIOX_1 66 -#define GPIOX_2 67 -#define GPIOX_3 68 -#define GPIOX_4 69 -#define GPIOX_5 70 -#define GPIOX_6 71 -#define GPIOX_7 72 -#define GPIOX_8 73 -#define GPIOX_9 74 -#define GPIOX_10 75 -#define GPIOX_11 76 -#define GPIOX_12 77 -#define GPIOX_13 78 -#define GPIOX_14 79 -#define GPIOX_15 80 -#define GPIOX_16 81 -#define GPIOX_17 82 -#define GPIOX_18 83 -#define GPIOX_19 84 - -#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h deleted file mode 100644 index 489c75b2764..00000000000 --- a/include/dt-bindings/gpio/meson-gxbb-gpio.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXBB SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H -#define _DT_BINDINGS_MESON_GXBB_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_TEST_N 14 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define BOOT_0 20 -#define BOOT_1 21 -#define BOOT_2 22 -#define BOOT_3 23 -#define BOOT_4 24 -#define BOOT_5 25 -#define BOOT_6 26 -#define BOOT_7 27 -#define BOOT_8 28 -#define BOOT_9 29 -#define BOOT_10 30 -#define BOOT_11 31 -#define BOOT_12 32 -#define BOOT_13 33 -#define BOOT_14 34 -#define BOOT_15 35 -#define BOOT_16 36 -#define BOOT_17 37 -#define CARD_0 38 -#define CARD_1 39 -#define CARD_2 40 -#define CARD_3 41 -#define CARD_4 42 -#define CARD_5 43 -#define CARD_6 44 -#define GPIODV_0 45 -#define GPIODV_1 46 -#define GPIODV_2 47 -#define GPIODV_3 48 -#define GPIODV_4 49 -#define GPIODV_5 50 -#define GPIODV_6 51 -#define GPIODV_7 52 -#define GPIODV_8 53 -#define GPIODV_9 54 -#define GPIODV_10 55 -#define GPIODV_11 56 -#define GPIODV_12 57 -#define GPIODV_13 58 -#define GPIODV_14 59 -#define GPIODV_15 60 -#define GPIODV_16 61 -#define GPIODV_17 62 -#define GPIODV_18 63 -#define GPIODV_19 64 -#define GPIODV_20 65 -#define GPIODV_21 66 -#define GPIODV_22 67 -#define GPIODV_23 68 -#define GPIODV_24 69 -#define GPIODV_25 70 -#define GPIODV_26 71 -#define GPIODV_27 72 -#define GPIODV_28 73 -#define GPIODV_29 74 -#define GPIOY_0 75 -#define GPIOY_1 76 -#define GPIOY_2 77 -#define GPIOY_3 78 -#define GPIOY_4 79 -#define GPIOY_5 80 -#define GPIOY_6 81 -#define GPIOY_7 82 -#define GPIOY_8 83 -#define GPIOY_9 84 -#define GPIOY_10 85 -#define GPIOY_11 86 -#define GPIOY_12 87 -#define GPIOY_13 88 -#define GPIOY_14 89 -#define GPIOY_15 90 -#define GPIOY_16 91 -#define GPIOX_0 92 -#define GPIOX_1 93 -#define GPIOX_2 94 -#define GPIOX_3 95 -#define GPIOX_4 96 -#define GPIOX_5 97 -#define GPIOX_6 98 -#define GPIOX_7 99 -#define GPIOX_8 100 -#define GPIOX_9 101 -#define GPIOX_10 102 -#define GPIOX_11 103 -#define GPIOX_12 104 -#define GPIOX_13 105 -#define GPIOX_14 106 -#define GPIOX_15 107 -#define GPIOX_16 108 -#define GPIOX_17 109 -#define GPIOX_18 110 -#define GPIOX_19 111 -#define GPIOX_20 112 -#define GPIOX_21 113 -#define GPIOX_22 114 -#define GPIOCLK_0 115 -#define GPIOCLK_1 116 -#define GPIOCLK_2 117 -#define GPIOCLK_3 118 - -#endif diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h deleted file mode 100644 index 0a001ae4827..00000000000 --- a/include/dt-bindings/gpio/meson-gxl-gpio.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * GPIO definitions for Amlogic Meson GXL SoCs - * - * Copyright (C) 2016 Endless Mobile, Inc. - * Author: Carlo Caione <carlo@endlessm.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H -#define _DT_BINDINGS_MESON_GXL_GPIO_H - -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIO_TEST_N 10 - -#define GPIOZ_0 0 -#define GPIOZ_1 1 -#define GPIOZ_2 2 -#define GPIOZ_3 3 -#define GPIOZ_4 4 -#define GPIOZ_5 5 -#define GPIOZ_6 6 -#define GPIOZ_7 7 -#define GPIOZ_8 8 -#define GPIOZ_9 9 -#define GPIOZ_10 10 -#define GPIOZ_11 11 -#define GPIOZ_12 12 -#define GPIOZ_13 13 -#define GPIOZ_14 14 -#define GPIOZ_15 15 -#define GPIOH_0 16 -#define GPIOH_1 17 -#define GPIOH_2 18 -#define GPIOH_3 19 -#define GPIOH_4 20 -#define GPIOH_5 21 -#define GPIOH_6 22 -#define GPIOH_7 23 -#define GPIOH_8 24 -#define GPIOH_9 25 -#define BOOT_0 26 -#define BOOT_1 27 -#define BOOT_2 28 -#define BOOT_3 29 -#define BOOT_4 30 -#define BOOT_5 31 -#define BOOT_6 32 -#define BOOT_7 33 -#define BOOT_8 34 -#define BOOT_9 35 -#define BOOT_10 36 -#define BOOT_11 37 -#define BOOT_12 38 -#define BOOT_13 39 -#define BOOT_14 40 -#define BOOT_15 41 -#define CARD_0 42 -#define CARD_1 43 -#define CARD_2 44 -#define CARD_3 45 -#define CARD_4 46 -#define CARD_5 47 -#define CARD_6 48 -#define GPIODV_0 49 -#define GPIODV_1 50 -#define GPIODV_2 51 -#define GPIODV_3 52 -#define GPIODV_4 53 -#define GPIODV_5 54 -#define GPIODV_6 55 -#define GPIODV_7 56 -#define GPIODV_8 57 -#define GPIODV_9 58 -#define GPIODV_10 59 -#define GPIODV_11 60 -#define GPIODV_12 61 -#define GPIODV_13 62 -#define GPIODV_14 63 -#define GPIODV_15 64 -#define GPIODV_16 65 -#define GPIODV_17 66 -#define GPIODV_18 67 -#define GPIODV_19 68 -#define GPIODV_20 69 -#define GPIODV_21 70 -#define GPIODV_22 71 -#define GPIODV_23 72 -#define GPIODV_24 73 -#define GPIODV_25 74 -#define GPIODV_26 75 -#define GPIODV_27 76 -#define GPIODV_28 77 -#define GPIODV_29 78 -#define GPIOX_0 79 -#define GPIOX_1 80 -#define GPIOX_2 81 -#define GPIOX_3 82 -#define GPIOX_4 83 -#define GPIOX_5 84 -#define GPIOX_6 85 -#define GPIOX_7 86 -#define GPIOX_8 87 -#define GPIOX_9 88 -#define GPIOX_10 89 -#define GPIOX_11 90 -#define GPIOX_12 91 -#define GPIOX_13 92 -#define GPIOX_14 93 -#define GPIOX_15 94 -#define GPIOX_16 95 -#define GPIOX_17 96 -#define GPIOX_18 97 -#define GPIOCLK_0 98 -#define GPIOCLK_1 99 - -#endif diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h deleted file mode 100644 index e5243884b24..00000000000 --- a/include/dt-bindings/power/meson-axg-power.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2020 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_AXG_POWER_H -#define _DT_BINDINGS_MESON_AXG_POWER_H - -#define PWRC_AXG_VPU_ID 0 -#define PWRC_AXG_ETHERNET_MEM_ID 1 -#define PWRC_AXG_AUDIO_ID 2 - -#endif diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h deleted file mode 100644 index bb5e67a842d..00000000000 --- a/include/dt-bindings/power/meson-g12a-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_G12A_POWER_H -#define _DT_BINDINGS_MESON_G12A_POWER_H - -#define PWRC_G12A_VPU_ID 0 -#define PWRC_G12A_ETH_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h deleted file mode 100644 index 1262dac696c..00000000000 --- a/include/dt-bindings/power/meson-gxbb-power.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H -#define _DT_BINDINGS_MESON_GXBB_POWER_H - -#define PWRC_GXBB_VPU_ID 0 -#define PWRC_GXBB_ETHERNET_MEM_ID 1 - -#endif diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h deleted file mode 100644 index a020ab00c13..00000000000 --- a/include/dt-bindings/power/meson-sm1-power.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_MESON_SM1_POWER_H -#define _DT_BINDINGS_MESON_SM1_POWER_H - -#define PWRC_SM1_VPU_ID 0 -#define PWRC_SM1_NNA_ID 1 -#define PWRC_SM1_USB_ID 2 -#define PWRC_SM1_PCIE_ID 3 -#define PWRC_SM1_GE2D_ID 4 -#define PWRC_SM1_AUDIO_ID 5 -#define PWRC_SM1_ETH_ID 6 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan <yixun.lan@amlogic.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7a..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 6d487c5eba2..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75-77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index 883bfd3bcba..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -#define RESET_ACODEC 61 -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h deleted file mode 100644 index 1051b8af298..00000000000 --- a/include/dt-bindings/sound/meson-aiu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_AIU_H -#define __DT_MESON_AIU_H - -#define AIU_CPU 0 -#define AIU_HDMI 1 -#define AIU_ACODEC 2 - -#define CPU_I2S_FIFO 0 -#define CPU_SPDIF_FIFO 1 -#define CPU_I2S_ENCODER 2 -#define CPU_SPDIF_ENCODER 3 - -#define CTRL_I2S 0 -#define CTRL_PCM 1 -#define CTRL_OUT 2 - -#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h deleted file mode 100644 index 69d7a75592a..00000000000 --- a/include/dt-bindings/sound/meson-g12a-toacodec.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOACODEC_H -#define __DT_MESON_G12A_TOACODEC_H - -#define TOACODEC_IN_A 0 -#define TOACODEC_IN_B 1 -#define TOACODEC_IN_C 2 -#define TOACODEC_OUT 3 - -#endif /* __DT_MESON_G12A_TOACODEC_H */ diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h deleted file mode 100644 index c5e1f48d30d..00000000000 --- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_MESON_G12A_TOHDMITX_H -#define __DT_MESON_G12A_TOHDMITX_H - -#define TOHDMITX_I2S_IN_A 0 -#define TOHDMITX_I2S_IN_B 1 -#define TOHDMITX_I2S_IN_C 2 -#define TOHDMITX_I2S_OUT 3 -#define TOHDMITX_SPDIF_IN_A 4 -#define TOHDMITX_SPDIF_IN_B 5 -#define TOHDMITX_SPDIF_OUT 6 - -#endif /* __DT_MESON_G12A_TOHDMITX_H */ diff --git a/include/efi.h b/include/efi.h index f0e5faa7549..c3c4b93f860 100644 --- a/include/efi.h +++ b/include/efi.h @@ -492,13 +492,14 @@ extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[]; /* * Variable Attributes */ -#define EFI_VARIABLE_NON_VOLATILE 0x0000000000000001 -#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002 -#define EFI_VARIABLE_RUNTIME_ACCESS 0x0000000000000004 -#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008 -#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010 -#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020 -#define EFI_VARIABLE_APPEND_WRITE 0x0000000000000040 +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008 +#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010 +#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020 +#define EFI_VARIABLE_APPEND_WRITE 0x00000040 +#define EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS 0x00000080 #define EFI_VARIABLE_MASK (EFI_VARIABLE_NON_VOLATILE | \ EFI_VARIABLE_BOOTSERVICE_ACCESS | \ @@ -506,7 +507,8 @@ extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[]; EFI_VARIABLE_HARDWARE_ERROR_RECORD | \ EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \ EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \ - EFI_VARIABLE_APPEND_WRITE) + EFI_VARIABLE_APPEND_WRITE | \ + EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS) /** * efi_get_priv() - Get access to the EFI-private information diff --git a/include/efi_loader.h b/include/efi_loader.h index 7daca0afba2..bb51c028177 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -345,9 +345,6 @@ extern const efi_guid_t smbios3_guid; extern const efi_guid_t efi_guid_text_input_protocol; extern const efi_guid_t efi_guid_text_output_protocol; -extern char __efi_runtime_start[], __efi_runtime_stop[]; -extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; - /** * struct efi_open_protocol_info_item - open protocol info item * diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index b21c5cb3dd6..a75b5a35b6e 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -150,16 +150,14 @@ struct efi_tcg2_final_events_table { * the variable. * @variable_data_length: The size of the variable data. * @unicode_name: The CHAR16 unicode name of the variable - * without NULL-terminator. - * @variable_data: The data parameter of the efi variable - * in the GetVariable() API. + * without NULL-terminator followed by data. */ struct efi_tcg2_uefi_variable_data { efi_guid_t variable_name; u64 unicode_name_length; u64 variable_data_length; - u16 unicode_name[1]; - u8 variable_data[1]; + u16 unicode_name[]; + // u8 variable_data[]; }; /** diff --git a/include/efi_variable.h b/include/efi_variable.h index 805e6c5f1e0..42a2b7c52be 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -8,7 +8,7 @@ #include <linux/bitops.h> -#define EFI_VARIABLE_READ_ONLY BIT(31) +#define EFI_VARIABLE_READ_ONLY 0x80000000 enum efi_auth_var_type { EFI_AUTH_VAR_NONE = 0, diff --git a/include/fastboot-internal.h b/include/fastboot-internal.h index 610d4f91414..e59c187c05c 100644 --- a/include/fastboot-internal.h +++ b/include/fastboot-internal.h @@ -6,7 +6,7 @@ /** * fastboot_buf_addr - base address of the fastboot download buffer */ -extern void *fastboot_buf_addr; +extern ulong fastboot_buf_addr; /** * fastboot_buf_size - size of the fastboot download buffer diff --git a/include/fastboot.h b/include/fastboot.h index 1e7920eb913..c75184cc912 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -114,13 +114,13 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason); */ void fastboot_set_progress_callback(void (*progress)(const char *msg)); -/* +/** * fastboot_init() - initialise new fastboot protocol session * - * @buf_addr: Pointer to download buffer, or NULL for default + * @buf_addr: Address of download buffer, or 0 for default * @buf_size: Size of download buffer, or zero for default */ -void fastboot_init(void *buf_addr, u32 buf_size); +void fastboot_init(ulong buf_addr, u32 buf_size); /** * fastboot_boot() - Execute fastboot boot command diff --git a/include/host_arch.h b/include/host_arch.h index 169d4945136..261194bd7c6 100644 --- a/include/host_arch.h +++ b/include/host_arch.h @@ -16,6 +16,8 @@ export HOST_ARCH_X86=0x0386 export HOST_ARCH_X86_64=0x8664 #endif +#include <version.h> + #define HOST_ARCH_AARCH64 0xaa64 #define HOST_ARCH_ARM 0x00a7 #define HOST_ARCH_RISCV32 0x5032 diff --git a/include/image.h b/include/image.h index 21de70f0c9e..acffd17e0df 100644 --- a/include/image.h +++ b/include/image.h @@ -946,7 +946,7 @@ static inline void image_set_name(struct legacy_img_hdr *hdr, const char *name) int image_check_hcrc(const struct legacy_img_hdr *hdr); int image_check_dcrc(const struct legacy_img_hdr *hdr); #ifndef USE_HOSTCC -ulong env_get_bootm_low(void); +phys_addr_t env_get_bootm_low(void); phys_size_t env_get_bootm_size(void); phys_size_t env_get_bootm_mapsize(void); #endif diff --git a/include/imx_container.h b/include/imx_container.h index 54cd684e35d..691c764b3e5 100644 --- a/include/imx_container.h +++ b/include/imx_container.h @@ -50,10 +50,10 @@ struct signature_block_hdr { u8 length_lsb; u8 length_msb; u8 tag; - u16 srk_table_offset; u16 cert_offset; - u16 blob_offset; + u16 srk_table_offset; u16 signature_offset; + u16 blob_offset; u32 reserved; } __packed; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index fb002ae6411..4abaf4734cf 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -249,6 +249,13 @@ enum nand_ecc_algo { */ #define NAND_USE_BOUNCE_BUFFER 0x00100000 +/* + * Do not try to tweak the timings at runtime. This is needed when the + * controller initializes the timings on itself or when it relies on + * configuration done by the bootloader. + */ +#define NAND_KEEP_TIMINGS 0x00800000 + /* Options set by nand scan */ /* bbt has already been read */ #define NAND_BBT_SCANNED 0x40000000 diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6f479fa5adc..13b5a52f8b9 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -251,6 +251,7 @@ extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants diff --git a/include/mcheck.h b/include/mcheck.h new file mode 100644 index 00000000000..bd506ae6291 --- /dev/null +++ b/include/mcheck.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.1+ */ +/* + * Copyright (C) 1996-2024 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * <https://www.gnu.org/licenses/>. + */ +#ifndef _MCHECK_H +#define _MCHECK_H 1 + +/* + * Return values for `mprobe': these are the kinds of inconsistencies that + * `mcheck' enables detection of. + */ +enum mcheck_status { + MCHECK_DISABLED = -1, /* Consistency checking is not turned on. */ + MCHECK_OK, /* Block is fine. */ + MCHECK_FREE, /* Block freed twice. */ + MCHECK_HEAD, /* Memory before the block was clobbered. */ + MCHECK_TAIL /* Memory after the block was clobbered. */ +}; + +typedef void (*mcheck_abortfunc_t)(enum mcheck_status, const void *p); + +int mcheck(mcheck_abortfunc_t func); + +/* + * Similar to `mcheck' but performs checks for all block whenever one of + * the memory handling functions is called. This can be very slow. + */ +int mcheck_pedantic(mcheck_abortfunc_t f); + +/* Force check of all blocks now. */ +void mcheck_check_all(void); + +/* + * Check for aberrations in a particular malloc'd block. These are the + * same checks that `mcheck' does, when you free or reallocate a block. + */ +enum mcheck_status mprobe(void *__ptr); + +#endif diff --git a/include/turris-omnia-mcu-interface.h b/include/turris-omnia-mcu-interface.h new file mode 100644 index 00000000000..3c4638f7329 --- /dev/null +++ b/include/turris-omnia-mcu-interface.h @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * CZ.NIC's Turris Omnia MCU I2C interface commands definitions + * + * 2023 by Marek Behún <kabel@kernel.org> + */ + +#ifndef __TURRIS_OMNIA_MCU_INTERFACE_H +#define __TURRIS_OMNIA_MCU_INTERFACE_H + +#include <linux/bitops.h> + +enum omnia_commands_e { + CMD_GET_STATUS_WORD = 0x01, /* slave sends status word back */ + CMD_GENERAL_CONTROL = 0x02, + CMD_LED_MODE = 0x03, /* default/user */ + CMD_LED_STATE = 0x04, /* LED on/off */ + CMD_LED_COLOR = 0x05, /* LED number + RED + GREEN + BLUE */ + CMD_USER_VOLTAGE = 0x06, + CMD_SET_BRIGHTNESS = 0x07, + CMD_GET_BRIGHTNESS = 0x08, + CMD_GET_RESET = 0x09, + CMD_GET_FW_VERSION_APP = 0x0A, /* 20B git hash number */ + CMD_SET_WATCHDOG_STATE = 0x0B, /* 0 - disable + * 1 - enable / ping + * after boot watchdog is started + * with 2 minutes timeout + */ + + /* CMD_WATCHDOG_STATUS = 0x0C, not implemented anymore */ + + CMD_GET_WATCHDOG_STATE = 0x0D, + CMD_GET_FW_VERSION_BOOT = 0x0E, /* 20B git hash number */ + CMD_GET_FW_CHECKSUM = 0x0F, /* 4B length, 4B checksum */ + + /* available if FEATURES_SUPPORTED bit set in status word */ + CMD_GET_FEATURES = 0x10, + + /* available if EXT_CMD bit set in features */ + CMD_GET_EXT_STATUS_DWORD = 0x11, + CMD_EXT_CONTROL = 0x12, + CMD_GET_EXT_CONTROL_STATUS = 0x13, + + /* available if NEW_INT_API bit set in features */ + CMD_GET_INT_AND_CLEAR = 0x14, + CMD_GET_INT_MASK = 0x15, + CMD_SET_INT_MASK = 0x16, + + /* available if FLASHING bit set in features */ + CMD_FLASH = 0x19, + + /* available if WDT_PING bit set in features */ + CMD_SET_WDT_TIMEOUT = 0x20, + CMD_GET_WDT_TIMELEFT = 0x21, + + /* available if POWEROFF_WAKEUP bit set in features */ + CMD_SET_WAKEUP = 0x22, + CMD_GET_UPTIME_AND_WAKEUP = 0x23, + CMD_POWER_OFF = 0x24, + + /* available if USB_OVC_PROT_SETTING bit set in features */ + CMD_SET_USB_OVC_PROT = 0x25, + CMD_GET_USB_OVC_PROT = 0x26, + + /* available if TRNG bit set in features */ + CMD_TRNG_COLLECT_ENTROPY = 0x28, + + /* available if CRYPTO bit set in features */ + CMD_CRYPTO_GET_PUBLIC_KEY = 0x29, + CMD_CRYPTO_SIGN_MESSAGE = 0x2A, + CMD_CRYPTO_COLLECT_SIGNATURE = 0x2B, + + /* available if BOARD_INFO it set in features */ + CMD_BOARD_INFO_GET = 0x2C, + CMD_BOARD_INFO_BURN = 0x2D, + + /* available only at address 0x2b (led-controller) */ + /* available only if LED_GAMMA_CORRECTION bit set in features */ + CMD_SET_GAMMA_CORRECTION = 0x30, + CMD_GET_GAMMA_CORRECTION = 0x31, + + /* available only at address 0x2b (led-controller) */ + /* available only if PER_LED_CORRECTION bit set in features */ + /* available only if FROM_BIT_16_INVALID bit NOT set in features */ + CMD_SET_LED_CORRECTIONS = 0x32, + CMD_GET_LED_CORRECTIONS = 0x33, +}; + +enum omnia_flashing_commands_e { + FLASH_CMD_UNLOCK = 0x01, + FLASH_CMD_SIZE_AND_CSUM = 0x02, + FLASH_CMD_PROGRAM = 0x03, + FLASH_CMD_RESET = 0x04, +}; + +enum omnia_sts_word_e { + STS_MCU_TYPE_MASK = GENMASK(1, 0), + STS_MCU_TYPE_STM32 = 0 << 0, + STS_MCU_TYPE_GD32 = 1 << 0, + STS_MCU_TYPE_MKL = 2 << 0, + STS_FEATURES_SUPPORTED = BIT(2), + STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3), + STS_CARD_DET = BIT(4), + STS_MSATA_IND = BIT(5), + STS_USB30_OVC = BIT(6), + STS_USB31_OVC = BIT(7), + STS_USB30_PWRON = BIT(8), + STS_USB31_PWRON = BIT(9), + STS_ENABLE_4V5 = BIT(10), + STS_BUTTON_MODE = BIT(11), + STS_BUTTON_PRESSED = BIT(12), + STS_BUTTON_COUNTER_MASK = GENMASK(15, 13) +}; + +enum omnia_ctl_byte_e { + CTL_LIGHT_RST = BIT(0), + CTL_HARD_RST = BIT(1), + /* BIT(2) is currently reserved */ + CTL_USB30_PWRON = BIT(3), + CTL_USB31_PWRON = BIT(4), + CTL_ENABLE_4V5 = BIT(5), + CTL_BUTTON_MODE = BIT(6), + CTL_BOOTLOADER = BIT(7) +}; + +enum omnia_features_e { + FEAT_PERIPH_MCU = BIT(0), + FEAT_EXT_CMDS = BIT(1), + FEAT_WDT_PING = BIT(2), + FEAT_LED_STATE_EXT_MASK = GENMASK(4, 3), + FEAT_LED_STATE_EXT = 1 << 3, + FEAT_LED_STATE_EXT_V32 = 2 << 3, + FEAT_LED_GAMMA_CORRECTION = BIT(5), + FEAT_NEW_INT_API = BIT(6), + FEAT_BOOTLOADER = BIT(7), + FEAT_FLASHING = BIT(8), + FEAT_NEW_MESSAGE_API = BIT(9), + FEAT_BRIGHTNESS_INT = BIT(10), + FEAT_POWEROFF_WAKEUP = BIT(11), + FEAT_CAN_OLD_MESSAGE_API = BIT(12), + FEAT_TRNG = BIT(13), + FEAT_CRYPTO = BIT(14), + FEAT_BOARD_INFO = BIT(15), + + /* + * Orginally the features command replied only 16 bits. If more were + * read, either the I2C transaction failed or 0xff bytes were sent. + * Therefore to consider bits 16 - 31 valid, one bit (20) was reserved + * to be zero. + */ + + /* Bits 16 - 19 correspond to bits 0 - 3 of status word */ + FEAT_MCU_TYPE_MASK = GENMASK(17, 16), + FEAT_MCU_TYPE_STM32 = 0 << 16, + FEAT_MCU_TYPE_GD32 = 1 << 16, + FEAT_MCU_TYPE_MKL = 2 << 16, + FEAT_FEATURES_SUPPORTED = BIT(18), + FEAT_USER_REGULATOR_NOT_SUPPORTED = BIT(19), + + /* must not be set */ + FEAT_FROM_BIT_16_INVALID = BIT(20), + + FEAT_PER_LED_CORRECTION = BIT(21), + FEAT_USB_OVC_PROT_SETTING = BIT(22), +}; + +enum omnia_ext_sts_dword_e { + EXT_STS_SFP_nDET = BIT(0), + EXT_STS_LED_STATES_MASK = GENMASK(31, 12), + EXT_STS_WLAN0_MSATA_LED = BIT(12), + EXT_STS_WLAN1_LED = BIT(13), + EXT_STS_WLAN2_LED = BIT(14), + EXT_STS_WPAN0_LED = BIT(15), + EXT_STS_WPAN1_LED = BIT(16), + EXT_STS_WPAN2_LED = BIT(17), + EXT_STS_WAN_LED0 = BIT(18), + EXT_STS_WAN_LED1 = BIT(19), + EXT_STS_LAN0_LED0 = BIT(20), + EXT_STS_LAN0_LED1 = BIT(21), + EXT_STS_LAN1_LED0 = BIT(22), + EXT_STS_LAN1_LED1 = BIT(23), + EXT_STS_LAN2_LED0 = BIT(24), + EXT_STS_LAN2_LED1 = BIT(25), + EXT_STS_LAN3_LED0 = BIT(26), + EXT_STS_LAN3_LED1 = BIT(27), + EXT_STS_LAN4_LED0 = BIT(28), + EXT_STS_LAN4_LED1 = BIT(29), + EXT_STS_LAN5_LED0 = BIT(30), + EXT_STS_LAN5_LED1 = BIT(31), +}; + +enum omnia_ext_ctl_e { + EXT_CTL_nRES_MMC = BIT(0), + EXT_CTL_nRES_LAN = BIT(1), + EXT_CTL_nRES_PHY = BIT(2), + EXT_CTL_nPERST0 = BIT(3), + EXT_CTL_nPERST1 = BIT(4), + EXT_CTL_nPERST2 = BIT(5), + EXT_CTL_PHY_SFP = BIT(6), + EXT_CTL_PHY_SFP_AUTO = BIT(7), + EXT_CTL_nVHV_CTRL = BIT(8), +}; + +enum omnia_int_e { + INT_CARD_DET = BIT(0), + INT_MSATA_IND = BIT(1), + INT_USB30_OVC = BIT(2), + INT_USB31_OVC = BIT(3), + INT_BUTTON_PRESSED = BIT(4), + INT_SFP_nDET = BIT(5), + INT_BRIGHTNESS_CHANGED = BIT(6), + INT_TRNG = BIT(7), + INT_MESSAGE_SIGNED = BIT(8), + + INT_LED_STATES_MASK = GENMASK(31, 12), + INT_WLAN0_MSATA_LED = BIT(12), + INT_WLAN1_LED = BIT(13), + INT_WLAN2_LED = BIT(14), + INT_WPAN0_LED = BIT(15), + INT_WPAN1_LED = BIT(16), + INT_WPAN2_LED = BIT(17), + INT_WAN_LED0 = BIT(18), + INT_WAN_LED1 = BIT(19), + INT_LAN0_LED0 = BIT(20), + INT_LAN0_LED1 = BIT(21), + INT_LAN1_LED0 = BIT(22), + INT_LAN1_LED1 = BIT(23), + INT_LAN2_LED0 = BIT(24), + INT_LAN2_LED1 = BIT(25), + INT_LAN3_LED0 = BIT(26), + INT_LAN3_LED1 = BIT(27), + INT_LAN4_LED0 = BIT(28), + INT_LAN4_LED1 = BIT(29), + INT_LAN5_LED0 = BIT(30), + INT_LAN5_LED1 = BIT(31), +}; + +enum omnia_cmd_poweroff_e { + CMD_POWER_OFF_POWERON_BUTTON = BIT(0), + CMD_POWER_OFF_MAGIC = 0xdead, +}; + +enum cmd_usb_ovc_prot_e { + CMD_xET_USB_OVC_PROT_PORT_MASK = GENMASK(3, 0), + CMD_xET_USB_OVC_PROT_ENABLE = BIT(4), +}; + +#endif /* __TURRIS_OMNIA_MCU_INTERFACE_H */ diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h index a33cc8780d3..ee19f460958 100644 --- a/include/u-boot/zlib.h +++ b/include/u-boot/zlib.h @@ -49,9 +49,6 @@ extern "C" { #endif -#define ZLIB_VERSION "1.2.3" -#define ZLIB_VERNUM 0x1230 - /* #include "zconf.h" */ /* included directly here */ /* zconf.h -- configuration of the zlib compression library * Copyright (C) 1995-2005 Jean-loup Gailly. @@ -484,7 +481,6 @@ typedef gz_header FAR *gz_headerp; #define Z_DATA_ERROR (-3) #define Z_MEM_ERROR (-4) #define Z_BUF_ERROR (-5) -#define Z_VERSION_ERROR (-6) /* Return codes for the compression/decompression functions. Negative * values are errors, positive values are used for special but normal events. */ @@ -523,11 +519,11 @@ typedef gz_header FAR *gz_headerp; ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level, - const char *version, int stream_size)); + int stream_size)); ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method, int windowBits, int memLevel, - int strategy, const char *version, + int strategy, int stream_size)); ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm)); ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm, @@ -553,7 +549,7 @@ ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest, ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, - const char *version, int stream_size)); + int stream_size)); ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush)); /* inflate decompresses as much data as possible, and stops when the input @@ -743,11 +739,11 @@ ZEXTERN int ZEXPORT uncompress2 OF((Bytef *dest, uLongf *destLen, */ ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits, - const char *version, int stream_size)); + int stream_size)); #define inflateInit(strm) \ - inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream)) + inflateInit_((strm), sizeof(z_stream)) #define inflateInit2(strm, windowBits) \ - inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream)) + inflateInit2_((strm), (windowBits), sizeof(z_stream)) #if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL) struct internal_state {int dummy;}; /* hack for buggy compilers */ diff --git a/lib/Kconfig b/lib/Kconfig index 37ac14f7bab..efb77978a65 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -348,7 +348,7 @@ config TRACE Enables function tracing within U-Boot. This allows recording of call traces including timing information. The command can write data to memory for exporting for analysis (e.g. using bootchart). - See doc/README.trace for full details. + See doc/develop/trace.rst for full details. config TRACE_BUFFER_SIZE hex "Size of trace buffer in U-Boot" diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index a7c3e05c13a..e13a6f9f4c3 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -44,7 +44,6 @@ config EFI_BINARY_EXEC config EFI_BOOTMGR bool "UEFI Boot Manager" default y - select BOOTMETH_GLOBAL if BOOTSTD help Select this option if you want to select the UEFI binary to be booted via UEFI variables Boot####, BootOrder, and BootNext. You should also diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index fcb0af7e7d6..034e366967f 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -6,8 +6,7 @@ # This file only gets included with CONFIG_EFI_LOADER set, so all # object inclusion implicitly depends on it -asflags-y += -DHOST_ARCH="$(HOST_ARCH)" -I. -ccflags-y += -DHOST_ARCH="$(HOST_ARCH)" +asflags-y += -I. CFLAGS_efi_boottime.o += \ -DFW_VERSION="0x$(VERSION)" \ @@ -72,11 +71,11 @@ obj-y += efi_string.o obj-$(CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2) += efi_unicode_collation.o obj-y += efi_var_common.o obj-y += efi_var_mem.o -obj-y += efi_var_file.o ifeq ($(CONFIG_EFI_MM_COMM_TEE),y) obj-y += efi_variable_tee.o else obj-y += efi_variable.o +obj-y += efi_var_file.o obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o endif obj-y += efi_watchdog.o diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index 67bbd2a01c0..67bd7f8ca24 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -41,7 +41,7 @@ efi_status_t efi_acpi_register(void) } addr = gd_acpi_start(); - printf("EFI using ACPI tables at %lx\n", addr); + log_debug("EFI using ACPI tables at %lx\n", addr); /* And expose them to our EFI payload */ return efi_install_configuration_table(&acpi_guid, diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index edfad2d95a1..12cf23fa3fa 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -15,6 +15,7 @@ #include <watchdog.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <asm/sections.h> #include <linux/list_sort.h> #include <linux/sizes.h> @@ -933,8 +934,8 @@ static void add_u_boot_and_runtime(void) * Add Runtime Services. We mark surrounding boottime code as runtime as * well to fulfill the runtime alignment constraints but avoid padding. */ - runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask; - runtime_end = (ulong)&__efi_runtime_stop; + runtime_start = (uintptr_t)__efi_runtime_start & ~runtime_mask; + runtime_end = (uintptr_t)__efi_runtime_stop; runtime_end = (runtime_end + runtime_mask) & ~runtime_mask; runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT; efi_add_memory_map_pg(runtime_start, runtime_pages, diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 9185f1894c4..a61c9a77b13 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -669,14 +669,14 @@ static __efi_runtime void efi_relocate_runtime_table(ulong offset) void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) { #ifdef IS_RELA - struct elf_rela *rel = (void*)&__efi_runtime_rel_start; + struct elf_rela *rel = (void *)__efi_runtime_rel_start; #else - struct elf_rel *rel = (void*)&__efi_runtime_rel_start; + struct elf_rel *rel = (void *)__efi_runtime_rel_start; static ulong lastoff = CONFIG_TEXT_BASE; #endif debug("%s: Relocating to offset=%lx\n", __func__, offset); - for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) { + for (; (uintptr_t)rel < (uintptr_t)__efi_runtime_rel_stop; rel++) { ulong base = CONFIG_TEXT_BASE; ulong *p; ulong newaddr; diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index d528747f3fb..aa8feffd3ec 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -9,6 +9,7 @@ #include <efi_loader.h> #include <efi_variable.h> #include <stdlib.h> +#include <u-boot/crc.h> enum efi_secure_mode { EFI_MODE_SETUP, @@ -99,7 +100,7 @@ efi_status_t EFIAPI efi_set_variable(u16 *variable_name, data_size, data); /* Make sure that the EFI_VARIABLE_READ_ONLY flag is not set */ - if (attributes & ~(u32)EFI_VARIABLE_MASK) + if (attributes & ~EFI_VARIABLE_MASK) ret = EFI_INVALID_PARAMETER; else ret = efi_set_variable_int(variable_name, vendor, attributes, @@ -416,3 +417,76 @@ void *efi_get_var(const u16 *name, const efi_guid_t *vendor, efi_uintn_t *size) return buf; } + +/** + * efi_var_collect() - Copy EFI variables mstching attributes mask + * + * @bufp: buffer containing variable collection + * @lenp: buffer length + * @attr_mask: mask of matched attributes + * + * Return: Status code + */ +efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, + u32 check_attr_mask) +{ + size_t len = EFI_VAR_BUF_SIZE; + struct efi_var_file *buf; + struct efi_var_entry *var, *old_var; + size_t old_var_name_length = 2; + + *bufp = NULL; /* Avoid double free() */ + buf = calloc(1, len); + if (!buf) + return EFI_OUT_OF_RESOURCES; + var = buf->var; + old_var = var; + for (;;) { + efi_uintn_t data_length, var_name_length; + u8 *data; + efi_status_t ret; + + if ((uintptr_t)buf + len <= + (uintptr_t)var->name + old_var_name_length) + return EFI_BUFFER_TOO_SMALL; + + var_name_length = (uintptr_t)buf + len - (uintptr_t)var->name; + memcpy(var->name, old_var->name, old_var_name_length); + guidcpy(&var->guid, &old_var->guid); + ret = efi_get_next_variable_name_int( + &var_name_length, var->name, &var->guid); + if (ret == EFI_NOT_FOUND) + break; + if (ret != EFI_SUCCESS) { + free(buf); + return ret; + } + old_var_name_length = var_name_length; + old_var = var; + + data = (u8 *)var->name + old_var_name_length; + data_length = (uintptr_t)buf + len - (uintptr_t)data; + ret = efi_get_variable_int(var->name, &var->guid, + &var->attr, &data_length, data, + &var->time); + if (ret != EFI_SUCCESS) { + free(buf); + return ret; + } + if ((var->attr & check_attr_mask) == check_attr_mask) { + var->length = data_length; + var = (struct efi_var_entry *)ALIGN((uintptr_t)data + data_length, 8); + } + } + + buf->reserved = 0; + buf->magic = EFI_VAR_FILE_MAGIC; + len = (uintptr_t)var - (uintptr_t)buf; + buf->crc32 = crc32(0, (u8 *)buf->var, + len - sizeof(struct efi_var_file)); + buf->length = len; + *bufp = buf; + *lenp = len; + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index 532b6b40eef..413e1794e88 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -52,70 +52,6 @@ static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void) return EFI_SUCCESS; } -efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, - u32 check_attr_mask) -{ - size_t len = EFI_VAR_BUF_SIZE; - struct efi_var_file *buf; - struct efi_var_entry *var, *old_var; - size_t old_var_name_length = 2; - - *bufp = NULL; /* Avoid double free() */ - buf = calloc(1, len); - if (!buf) - return EFI_OUT_OF_RESOURCES; - var = buf->var; - old_var = var; - for (;;) { - efi_uintn_t data_length, var_name_length; - u8 *data; - efi_status_t ret; - - if ((uintptr_t)buf + len <= - (uintptr_t)var->name + old_var_name_length) - return EFI_BUFFER_TOO_SMALL; - - var_name_length = (uintptr_t)buf + len - (uintptr_t)var->name; - memcpy(var->name, old_var->name, old_var_name_length); - guidcpy(&var->guid, &old_var->guid); - ret = efi_get_next_variable_name_int( - &var_name_length, var->name, &var->guid); - if (ret == EFI_NOT_FOUND) - break; - if (ret != EFI_SUCCESS) { - free(buf); - return ret; - } - old_var_name_length = var_name_length; - old_var = var; - - data = (u8 *)var->name + old_var_name_length; - data_length = (uintptr_t)buf + len - (uintptr_t)data; - ret = efi_get_variable_int(var->name, &var->guid, - &var->attr, &data_length, data, - &var->time); - if (ret != EFI_SUCCESS) { - free(buf); - return ret; - } - if ((var->attr & check_attr_mask) == check_attr_mask) { - var->length = data_length; - var = (struct efi_var_entry *)ALIGN((uintptr_t)data + data_length, 8); - } - } - - buf->reserved = 0; - buf->magic = EFI_VAR_FILE_MAGIC; - len = (uintptr_t)var - (uintptr_t)buf; - buf->crc32 = crc32(0, (u8 *)buf->var, - len - sizeof(struct efi_var_file)); - buf->length = len; - *bufp = buf; - *lenp = len; - - return EFI_SUCCESS; -} - /** * efi_var_to_file() - save non-volatile variables as file * diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 40f7a0fb10d..e6c1219a11c 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -163,6 +163,7 @@ static efi_status_t efi_variable_authenticate(const u16 *variable, break; default: /* TODO: support private authenticated variables */ + ret = EFI_UNSUPPORTED; goto err; } @@ -235,8 +236,12 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (data_size && !data) return EFI_INVALID_PARAMETER; - /* EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated */ - if (attributes & EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS) + /* + * EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated. + * We don't support EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS. + */ + if (attributes & (EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \ + EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS)) return EFI_UNSUPPORTED; /* Make sure if runtime bit is set, boot service bit is set also */ @@ -259,7 +264,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, /* check if a variable exists */ var = efi_var_mem_find(vendor, variable_name, NULL); append = !!(attributes & EFI_VARIABLE_APPEND_WRITE); - attributes &= ~(u32)EFI_VARIABLE_APPEND_WRITE; + attributes &= ~EFI_VARIABLE_APPEND_WRITE; delete = !append && (!data_size || !attributes); /* check attributes */ @@ -276,17 +281,27 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, /* attributes won't be changed */ if (!delete && ((ro_check && var->attr != attributes) || - (!ro_check && ((var->attr & ~(u32)EFI_VARIABLE_READ_ONLY) - != (attributes & ~(u32)EFI_VARIABLE_READ_ONLY))))) { + (!ro_check && ((var->attr & ~EFI_VARIABLE_READ_ONLY) + != (attributes & ~EFI_VARIABLE_READ_ONLY))))) { return EFI_INVALID_PARAMETER; } time = var->time; } else { - if (delete || append) - /* - * Trying to delete or to update a non-existent - * variable. - */ + /* + * UEFI specification does not clearly describe the expected + * behavior of append write with data size 0, we follow + * the EDK II reference implementation. + */ + if (append && !data_size) + return EFI_SUCCESS; + + /* + * EFI_VARIABLE_APPEND_WRITE to non-existent variable is accepted + * and new variable is created in EDK II reference implementation. + * We follow it and only check the deletion here. + */ + if (delete) + /* Trying to delete a non-existent variable. */ return EFI_NOT_FOUND; } @@ -329,7 +344,11 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, /* EFI_NOT_FOUND has been handled before */ attributes = var->attr; ret = EFI_SUCCESS; - } else if (append) { + } else if (append && var) { + /* + * data is appended if EFI_VARIABLE_APPEND_WRITE is set and + * variable exists. + */ u16 *old_data = var->name; for (; *old_data; ++old_data) @@ -342,11 +361,12 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, ret = efi_var_mem_ins(variable_name, vendor, attributes, data_size, data, 0, NULL, time); } - efi_var_mem_del(var); if (ret != EFI_SUCCESS) return ret; + efi_var_mem_del(var); + if (var_type == EFI_AUTH_VAR_PK) ret = efi_init_secure_state(); else @@ -384,7 +404,7 @@ efi_status_t efi_query_variable_info_int(u32 attributes, EFI_VARIABLE_RUNTIME_ACCESS) return EFI_INVALID_PARAMETER; - if (attributes & ~(u32)EFI_VARIABLE_MASK) + if (attributes & ~EFI_VARIABLE_MASK) return EFI_INVALID_PARAMETER; *maximum_variable_storage_size = EFI_VAR_BUF_SIZE - diff --git a/lib/efi_selftest/efi_selftest_variables.c b/lib/efi_selftest/efi_selftest_variables.c index c7a3fdbaa67..39ad03a090d 100644 --- a/lib/efi_selftest/efi_selftest_variables.c +++ b/lib/efi_selftest/efi_selftest_variables.c @@ -131,13 +131,57 @@ static int execute(void) (unsigned int)len); if (memcmp(data, v, len)) efi_st_todo("GetVariable returned wrong value\n"); - /* Append variable 2 */ + + /* Append variable 2, write to non-existent variable with datasize=0 */ + ret = runtime->set_variable(u"efi_none", &guid_vendor1, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_APPEND_WRITE, + 0, v); + if (ret != EFI_SUCCESS) { + efi_st_error( + "SetVariable(APPEND_WRITE) with size 0 to non-existent variable returns wrong code\n"); + return EFI_ST_FAILURE; + } + len = EFI_ST_MAX_DATA_SIZE; + ret = runtime->get_variable(u"efi_none", &guid_vendor1, + &attr, &len, data); + if (ret != EFI_NOT_FOUND) { + efi_st_error("Variable must not be created\n"); + return EFI_ST_FAILURE; + } + /* Append variable 2, write to non-existent variable with valid data size*/ ret = runtime->set_variable(u"efi_none", &guid_vendor1, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_APPEND_WRITE, 15, v); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable(APPEND_WRITE) with valid size and data to non-existent variable must be succcessful\n"); + return EFI_ST_FAILURE; + } + len = EFI_ST_MAX_DATA_SIZE; + ret = runtime->get_variable(u"efi_none", &guid_vendor1, + &attr, &len, data); + if (ret != EFI_SUCCESS) { + efi_st_error("GetVariable failed\n"); + return EFI_ST_FAILURE; + } + if (len != 15) + efi_st_todo("GetVariable returned wrong length %u\n", + (unsigned int)len); + if (memcmp(data, v, len)) + efi_st_todo("GetVariable returned wrong value\n"); + /* Delete variable efi_none */ + ret = runtime->set_variable(u"efi_none", &guid_vendor1, + 0, 0, NULL); + if (ret != EFI_SUCCESS) { + efi_st_error("SetVariable failed\n"); + return EFI_ST_FAILURE; + } + len = EFI_ST_MAX_DATA_SIZE; + ret = runtime->get_variable(u"efi_none", &guid_vendor1, + &attr, &len, data); if (ret != EFI_NOT_FOUND) { - efi_st_error("SetVariable(APPEND_WRITE) with size 0 to non-existent variable returns wrong code\n"); + efi_st_error("Variable was not deleted\n"); return EFI_ST_FAILURE; } /* Enumerate variables */ diff --git a/lib/gzip.c b/lib/gzip.c index 5d9c19598d5..a9a3df524de 100644 --- a/lib/gzip.c +++ b/lib/gzip.c @@ -67,7 +67,7 @@ int zzip(void *dst, unsigned long *lenp, unsigned char *src, r = deflateInit2_(&s, Z_BEST_SPEED, Z_DEFLATED, window, DEF_MEM_LEVEL, Z_DEFAULT_STRATEGY, - ZLIB_VERSION, sizeof(z_stream)); + sizeof(z_stream)); if (r != Z_OK) { printf ("Error: deflateInit2_() returned %d\n", r); return -1; diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 1007b6979a4..d3b4f71d6be 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -342,7 +342,7 @@ static int rsa_verify_key(struct image_sign_info *info, return -EINVAL; } - debug("Checksum algorithm: %s", checksum->name); + debug("Checksum algorithm: %s\n", checksum->name); /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { @@ -444,13 +444,13 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, const char *algo; if (node < 0) { - debug("%s: Skipping invalid node", __func__); + debug("%s: Skipping invalid node\n", __func__); return -EBADF; } algo = fdt_getprop(blob, node, "algo", NULL); if (strcmp(info->name, algo)) { - debug("%s: Wrong algo: have %s, expected %s", __func__, + debug("%s: Wrong algo: have %s, expected %s\n", __func__, info->name, algo); return -EFAULT; } @@ -470,7 +470,7 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, prop.rr = fdt_getprop(blob, node, "rsa,r-squared", NULL); if (!prop.num_bits || !prop.modulus || !prop.rr) { - debug("%s: Missing RSA key info", __func__); + debug("%s: Missing RSA key info\n", __func__); return -EFAULT; } diff --git a/lib/zlib/deflate.c b/lib/zlib/deflate.c index 4549f4dc12a..7e1ed4f9b20 100644 --- a/lib/zlib/deflate.c +++ b/lib/zlib/deflate.c @@ -196,37 +196,30 @@ struct static_tree_desc_s {int dummy;}; /* for buggy compilers */ zmemzero((Bytef *)s->head, (unsigned)(s->hash_size-1)*sizeof(*s->head)); /* ========================================================================= */ -int ZEXPORT deflateInit_(strm, level, version, stream_size) +int ZEXPORT deflateInit_(strm, level, stream_size) z_streamp strm; int level; - const char *version; int stream_size; { return deflateInit2_(strm, level, Z_DEFLATED, MAX_WBITS, DEF_MEM_LEVEL, - Z_DEFAULT_STRATEGY, version, stream_size); + Z_DEFAULT_STRATEGY, stream_size); /* To do: ignore strm->next_in if we use it as window */ } /* ========================================================================= */ int ZEXPORT deflateInit2_(strm, level, method, windowBits, memLevel, strategy, - version, stream_size) + stream_size) z_streamp strm; int level; int method; int windowBits; int memLevel; int strategy; - const char *version; int stream_size; { deflate_state *s; int wrap = 1; - static const char my_version[] = ZLIB_VERSION; - if (version == Z_NULL || version[0] != my_version[0] || - stream_size != sizeof(z_stream)) { - return Z_VERSION_ERROR; - } if (strm == Z_NULL) return Z_STREAM_ERROR; strm->msg = Z_NULL; diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index e3c7f3b892b..5e2a65ad4d2 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c @@ -1,5 +1,5 @@ /* inffast.c -- fast decoding - * Copyright (C) 1995-2004 Mark Adler + * Copyright (C) 1995-2008, 2010, 2013 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -12,25 +12,6 @@ #ifndef ASMINF -/* Allow machine dependent optimization for post-increment or pre-increment. - Based on testing to date, - Pre-increment preferred for: - - PowerPC G3 (Adler) - - MIPS R5000 (Randers-Pehrson) - Post-increment preferred for: - - none - No measurable difference: - - Pentium III (Anderson) - - M68060 (Nikl) - */ -#ifdef POSTINC -# define OFF 0 -# define PUP(a) *(a)++ -#else -# define OFF 1 -# define PUP(a) *++(a) -#endif - /* Decode literal, length, and distance codes and write out the resulting literal and match bytes until either not enough input or output is @@ -66,12 +47,13 @@ requires strm->avail_out >= 258 for each loop to avoid checking for output space. */ -void inflate_fast(z_streamp strm, unsigned start) -/* start: inflate()'s starting value for strm->avail_out */ +void ZLIB_INTERNAL inflate_fast(strm, start) +z_streamp strm; +unsigned start; /* inflate()'s starting value for strm->avail_out */ { struct inflate_state FAR *state; - unsigned char FAR *in; /* local strm->next_in */ - unsigned char FAR *last; /* while in < last, enough input available */ + z_const unsigned char FAR *in; /* local strm->next_in */ + z_const unsigned char FAR *last; /* have enough input while in < last */ unsigned char FAR *out; /* local strm->next_out */ unsigned char FAR *beg; /* inflate()'s initial strm->next_out */ unsigned char FAR *end; /* while out < end, enough space available */ @@ -80,7 +62,7 @@ void inflate_fast(z_streamp strm, unsigned start) #endif unsigned wsize; /* window size or zero if not using window */ unsigned whave; /* valid bytes in the window */ - unsigned write; /* window write index */ + unsigned wnext; /* window write index */ unsigned char FAR *window; /* allocated sliding window, if wsize != 0 */ unsigned long hold; /* local strm->hold */ unsigned bits; /* local strm->bits */ @@ -88,7 +70,7 @@ void inflate_fast(z_streamp strm, unsigned start) code const FAR *dcode; /* local strm->distcode */ unsigned lmask; /* mask for first level of length codes */ unsigned dmask; /* mask for first level of distance codes */ - code this; /* retrieved table entry */ + code here; /* retrieved table entry */ unsigned op; /* code bits, operation, extra bits, or */ /* window position, window bytes to copy */ unsigned len; /* match length, unused bytes */ @@ -97,7 +79,7 @@ void inflate_fast(z_streamp strm, unsigned start) /* copy state to local variables */ state = (struct inflate_state FAR *)strm->state; - in = strm->next_in - OFF; + in = strm->next_in; last = in + (strm->avail_in - 5); if (in > last && strm->avail_in > 5) { /* @@ -107,7 +89,7 @@ void inflate_fast(z_streamp strm, unsigned start) strm->avail_in = 0xffffffff - (uintptr_t)in; last = in + (strm->avail_in - 5); } - out = strm->next_out - OFF; + out = strm->next_out; beg = out - (start - strm->avail_out); end = out + (strm->avail_out - 257); #ifdef INFLATE_STRICT @@ -115,7 +97,7 @@ void inflate_fast(z_streamp strm, unsigned start) #endif wsize = state->wsize; whave = state->whave; - write = state->write; + wnext = state->wnext; window = state->window; hold = state->hold; bits = state->bits; @@ -128,29 +110,29 @@ void inflate_fast(z_streamp strm, unsigned start) input data or output space */ do { if (bits < 15) { - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; } - this = lcode[hold & lmask]; + here = lcode[hold & lmask]; dolen: - op = (unsigned)(this.bits); + op = (unsigned)(here.bits); hold >>= op; bits -= op; - op = (unsigned)(this.op); + op = (unsigned)(here.op); if (op == 0) { /* literal */ - Tracevv((stderr, this.val >= 0x20 && this.val < 0x7f ? + Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ? "inflate: literal '%c'\n" : - "inflate: literal 0x%02x\n", this.val)); - PUP(out) = (unsigned char)(this.val); + "inflate: literal 0x%02x\n", here.val)); + *out++ = (unsigned char)(here.val); } else if (op & 16) { /* length base */ - len = (unsigned)(this.val); + len = (unsigned)(here.val); op &= 15; /* number of extra bits */ if (op) { if (bits < op) { - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; } len += (unsigned)hold & ((1U << op) - 1); @@ -159,25 +141,25 @@ void inflate_fast(z_streamp strm, unsigned start) } Tracevv((stderr, "inflate: length %u\n", len)); if (bits < 15) { - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; } - this = dcode[hold & dmask]; + here = dcode[hold & dmask]; dodist: - op = (unsigned)(this.bits); + op = (unsigned)(here.bits); hold >>= op; bits -= op; - op = (unsigned)(this.op); + op = (unsigned)(here.op); if (op & 16) { /* distance base */ - dist = (unsigned)(this.val); + dist = (unsigned)(here.val); op &= 15; /* number of extra bits */ if (bits < op) { - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; if (bits < op) { - hold += (unsigned long)(PUP(in)) << bits; + hold += (unsigned long)(*in++) << bits; bits += 8; } } @@ -196,108 +178,80 @@ void inflate_fast(z_streamp strm, unsigned start) if (dist > op) { /* see if copy from window */ op = dist - op; /* distance back in window */ if (op > whave) { - strm->msg = (char *)"invalid distance too far back"; + strm->msg = + (char *)"invalid distance too far back"; state->mode = BAD; break; } - from = window - OFF; - if (write == 0) { /* very common case */ + from = window; + if (wnext == 0) { /* very common case */ from += wsize - op; if (op < len) { /* some from window */ len -= op; do { - PUP(out) = PUP(from); + *out++ = *from++; } while (--op); from = out - dist; /* rest from output */ } } - else if (write < op) { /* wrap around window */ - from += wsize + write - op; - op -= write; + else if (wnext < op) { /* wrap around window */ + from += wsize + wnext - op; + op -= wnext; if (op < len) { /* some from end of window */ len -= op; do { - PUP(out) = PUP(from); + *out++ = *from++; } while (--op); - from = window - OFF; - if (write < len) { /* some from start of window */ - op = write; + from = window; + if (wnext < len) { /* some from start of window */ + op = wnext; len -= op; do { - PUP(out) = PUP(from); + *out++ = *from++; } while (--op); from = out - dist; /* rest from output */ } } } else { /* contiguous in window */ - from += write - op; + from += wnext - op; if (op < len) { /* some from window */ len -= op; do { - PUP(out) = PUP(from); + *out++ = *from++; } while (--op); from = out - dist; /* rest from output */ } } while (len > 2) { - PUP(out) = PUP(from); - PUP(out) = PUP(from); - PUP(out) = PUP(from); + *out++ = *from++; + *out++ = *from++; + *out++ = *from++; len -= 3; } if (len) { - PUP(out) = PUP(from); + *out++ = *from++; if (len > 1) - PUP(out) = PUP(from); + *out++ = *from++; } } else { - unsigned short *sout; - unsigned long loops; - from = out - dist; /* copy direct from output */ - /* minimum length is three */ - /* Align out addr */ - if (!((long)(out - 1 + OFF) & 1)) { - PUP(out) = PUP(from); - len--; - } - sout = (unsigned short *)(out - OFF); - if (dist > 2 ) { - unsigned short *sfrom; - - sfrom = (unsigned short *)(from - OFF); - loops = len >> 1; - do - PUP(sout) = get_unaligned(++sfrom); - while (--loops); - out = (unsigned char *)sout + OFF; - from = (unsigned char *)sfrom + OFF; - } else { /* dist == 1 or dist == 2 */ - unsigned short pat16; - - pat16 = *(sout-2+2*OFF); - if (dist == 1) -#if defined(__BIG_ENDIAN) - pat16 = (pat16 & 0xff) | ((pat16 & 0xff ) << 8); -#elif defined(__LITTLE_ENDIAN) - pat16 = (pat16 & 0xff00) | ((pat16 & 0xff00 ) >> 8); -#else -#error __BIG_ENDIAN nor __LITTLE_ENDIAN is defined -#endif - loops = len >> 1; - do - PUP(sout) = pat16; - while (--loops); - out = (unsigned char *)sout + OFF; - } - if (len & 1) - PUP(out) = PUP(from); + do { /* minimum length is three */ + *out++ = *from++; + *out++ = *from++; + *out++ = *from++; + len -= 3; + } while (len > 2); + if (len) { + *out++ = *from++; + if (len > 1) + *out++ = *from++; + } } } else if ((op & 64) == 0) { /* 2nd level distance code */ - this = dcode[this.val + (hold & ((1U << op) - 1))]; + here = dcode[here.val + (hold & ((1U << op) - 1))]; goto dodist; } else { @@ -307,7 +261,7 @@ void inflate_fast(z_streamp strm, unsigned start) } } else if ((op & 64) == 0) { /* 2nd level length code */ - this = lcode[this.val + (hold & ((1U << op) - 1))]; + here = lcode[here.val + (hold & ((1U << op) - 1))]; goto dolen; } else if (op & 32) { /* end-of-block */ @@ -329,8 +283,8 @@ void inflate_fast(z_streamp strm, unsigned start) hold &= (1U << bits) - 1; /* update state and return */ - strm->next_in = in + OFF; - strm->next_out = out + OFF; + strm->next_in = in; + strm->next_out = out; strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last)); strm->avail_out = (unsigned)(out < end ? 257 + (end - out) : 257 - (out - end)); @@ -343,7 +297,7 @@ void inflate_fast(z_streamp strm, unsigned start) inflate_fast() speedups that turned out slower (on a PowerPC G3 750CXe): - Using bit fields for code structure - Different op definition to avoid & for extra bits (do & for table bits) - - Three separate decoding do-loops for direct, window, and write == 0 + - Three separate decoding do-loops for direct, window, and wnext == 0 - Special case for distance > 1 copies to do overlapped load and store copy - Explicit branch predictions (based on measured branch probabilities) - Deferring match copy and interspersed it with decoding subsequent codes diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index 8f767b7b9d2..f7e81fc8b2a 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -21,7 +21,7 @@ int ZEXPORT inflateReset(z_streamp strm) state->head = Z_NULL; state->wsize = 0; state->whave = 0; - state->write = 0; + state->wnext = 0; state->hold = 0; state->bits = 0; state->lencode = state->distcode = state->next = state->codes; @@ -30,14 +30,11 @@ int ZEXPORT inflateReset(z_streamp strm) return Z_OK; } -int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, const char *version, +int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, int stream_size) { struct inflate_state FAR *state; - if (version == Z_NULL || version[0] != ZLIB_VERSION[0] || - stream_size != (int)(sizeof(z_stream))) - return Z_VERSION_ERROR; if (strm == Z_NULL) return Z_STREAM_ERROR; strm->msg = Z_NULL; /* in case we return an error */ if (strm->zalloc == (alloc_func)0) { @@ -70,9 +67,9 @@ int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, const char *version, return inflateReset(strm); } -int ZEXPORT inflateInit_(z_streamp strm, const char *version, int stream_size) +int ZEXPORT inflateInit_(z_streamp strm, int stream_size) { - return inflateInit2_(strm, DEF_WBITS, version, stream_size); + return inflateInit2_(strm, DEF_WBITS, stream_size); } local void fixedtables(struct inflate_state FAR *state) @@ -115,7 +112,7 @@ local int updatewindow(z_streamp strm, unsigned out) /* if window not in use yet, initialize */ if (state->wsize == 0) { state->wsize = 1U << state->wbits; - state->write = 0; + state->wnext = 0; state->whave = 0; } @@ -123,22 +120,22 @@ local int updatewindow(z_streamp strm, unsigned out) copy = out - strm->avail_out; if (copy >= state->wsize) { zmemcpy(state->window, strm->next_out - state->wsize, state->wsize); - state->write = 0; + state->wnext = 0; state->whave = state->wsize; } else { - dist = state->wsize - state->write; + dist = state->wsize - state->wnext; if (dist > copy) dist = copy; - zmemcpy(state->window + state->write, strm->next_out - copy, dist); + zmemcpy(state->window + state->wnext, strm->next_out - copy, dist); copy -= dist; if (copy) { zmemcpy(state->window, strm->next_out - copy, copy); - state->write = copy; + state->wnext = copy; state->whave = state->wsize; } else { - state->write += dist; - if (state->write == state->wsize) state->write = 0; + state->wnext += dist; + if (state->wnext == state->wsize) state->wnext = 0; if (state->whave < state->wsize) state->whave += dist; } } @@ -823,12 +820,12 @@ int ZEXPORT inflate(z_streamp strm, int flush) copy = out - left; if (state->offset > copy) { /* copy from window */ copy = state->offset - copy; - if (copy > state->write) { - copy -= state->write; + if (copy > state->wnext) { + copy -= state->wnext; from = state->window + (state->wsize - copy); } else - from = state->window + (state->write - copy); + from = state->window + (state->wnext - copy); if (copy > state->length) copy = state->length; } else { /* copy from output */ diff --git a/lib/zlib/inflate.h b/lib/zlib/inflate.h index 07bd3e78a7c..2657d611cda 100644 --- a/lib/zlib/inflate.h +++ b/lib/zlib/inflate.h @@ -88,7 +88,7 @@ struct inflate_state { unsigned wbits; /* log base 2 of requested window size */ unsigned wsize; /* window size or zero if not using window */ unsigned whave; /* valid bytes in the window */ - unsigned write; /* window write index */ + unsigned wnext; /* window write index */ unsigned char FAR *window; /* allocated sliding window, if needed */ /* bit accumulator */ unsigned long hold; /* input bit accumulator */ diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index 609aac55ce1..ec21b458fcc 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -21,7 +21,6 @@ const char * const z_errmsg[10] = { "data error", /* Z_DATA_ERROR (-3) */ "insufficient memory", /* Z_MEM_ERROR (-4) */ "buffer error", /* Z_BUF_ERROR (-5) */ -"incompatible version",/* Z_VERSION_ERROR (-6) */ ""}; #ifdef DEBUG diff --git a/net/nfs.c b/net/nfs.c index 7a8887ef236..c18282448cc 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -57,7 +57,8 @@ static int nfs_offset = -1; static int nfs_len; static const ulong nfs_timeout = CONFIG_NFS_TIMEOUT; -static char dirfh[NFS_FHSIZE]; /* NFSv2 / NFSv3 file handle of directory */ +static char dirfh[NFS3_FHSIZE]; /* NFSv2 / NFSv3 file handle of directory */ +static unsigned int dirfh3_length; /* (variable) length of dirfh when NFSv3 */ static char filefh[NFS3_FHSIZE]; /* NFSv2 / NFSv3 file handle */ static unsigned int filefh3_length; /* (variable) length of filefh when NFSv3 */ @@ -377,9 +378,9 @@ static void nfs_lookup_req(char *fname) rpc_req(PROG_NFS, NFS_LOOKUP, data, len); } else { /* NFS_V3 */ - *p++ = htonl(NFS_FHSIZE); /* Dir handle length */ - memcpy(p, dirfh, NFS_FHSIZE); - p += (NFS_FHSIZE / 4); + *p++ = htonl(dirfh3_length); /* Dir handle length */ + memcpy(p, dirfh, dirfh3_length); + p += (dirfh3_length / 4); *p++ = htonl(fnamelen); if (fnamelen & 3) *(p + fnamelen / 4) = 0; @@ -565,7 +566,14 @@ static int nfs_mount_reply(uchar *pkt, unsigned len) fs_mounted = 1; /* NFSv2 and NFSv3 use same structure */ - memcpy(dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + if (choosen_nfs_version != NFS_V3) { + memcpy(dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + } else { + dirfh3_length = ntohl(rpc_pkt.u.reply.data[1]); + if (dirfh3_length > NFS3_FHSIZE) + dirfh3_length = NFS3_FHSIZE; + memcpy(dirfh, rpc_pkt.u.reply.data + 2, dirfh3_length); + } return 0; } diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index d074ba23500..1868f1beef6 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -381,6 +381,11 @@ $(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin $(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ endif +$(obj)/u-boot-spl.ldr: $(obj)/u-boot-spl + $(CREATE_LDR_ENV) + $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) + $(BOARD_SIZE_CHECK) + quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ @@ -575,7 +580,7 @@ endif SPL_OF_LIST_TARGETS = $(patsubst %,dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST))) SHRUNK_ARCH_DTB = $(addprefix $(obj)/,$(SPL_OF_LIST_TARGETS)) -$(dir $(SHRUNK_ARCH_DTB)): +$(sort $(dir $(SHRUNK_ARCH_DTB))): $(shell [ -d $@ ] || mkdir -p $@) .SECONDEXPANSION: diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 4845b7121c8..674d4c05f83 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -13,6 +13,7 @@ #include <bootstd.h> #include <cli.h> #include <dm.h> +#include <efi_default_filename.h> #include <expo.h> #ifdef CONFIG_SANDBOX #include <asm/test.h> @@ -179,7 +180,8 @@ static int bootflow_cmd_scan_e(struct unit_test_state *uts) ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole "); ut_assert_nextline(" ** No partition found, err=-2: No such file or directory"); ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); - ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 efi/boot/bootsbox.efi"); + ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 /EFI/BOOT/" + BOOTEFI_NAME); ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':"); ut_assert_skip_to_line( @@ -377,7 +379,7 @@ static int bootflow_system(struct unit_test_state *uts) if (!IS_ENABLED(CONFIG_EFI_BOOTMGR)) return -EAGAIN; ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd)); - ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr), + ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_3efi_mgr), "efi_mgr", 0, ofnode_null(), &dev)); ut_assertok(device_probe(dev)); sandbox_set_fake_efi_mgr_dev(dev, true); diff --git a/test/py/test.py b/test/py/test.py index 95859a66e29..7c477903d6b 100755 --- a/test/py/test.py +++ b/test/py/test.py @@ -11,7 +11,6 @@ import os import os.path import sys import pytest -from pkg_resources import load_entry_point if __name__ == '__main__': # argv; py.test test_directory_name user-supplied-arguments diff --git a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts index e8a18585092..1a62c260474 100644 --- a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts +++ b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts @@ -55,42 +55,6 @@ }; capsule1 { - filename = "Test01"; - efi-capsule { - image-index = <0x1>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule2 { - filename = "Test02"; - efi-capsule { - image-index = <0x2>; - image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; - - text { - text = "u-boot-env:New"; - }; - }; - }; - - capsule3 { - filename = "Test03"; - efi-capsule { - image-index = <0x1>; - image-guid = SANDBOX_INCORRECT_GUID; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule4 { filename = "Test04"; efi-capsule { image-index = <0x1>; @@ -102,7 +66,7 @@ }; }; - capsule5 { + capsule2 { filename = "Test05"; efi-capsule { image-index = <0x1>; @@ -114,46 +78,7 @@ }; }; - capsule6 { - filename = "Test101"; - efi-capsule { - image-index = <0x1>; - fw-version = <0x5>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule7 { - filename = "Test102"; - efi-capsule { - image-index = <0x2>; - fw-version = <0xa>; - image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; - - text { - text = "u-boot-env:New"; - }; - }; - }; - - capsule8 { - filename = "Test103"; - efi-capsule { - image-index = <0x1>; - fw-version = <0x2>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule9 { + capsule3 { filename = "Test104"; efi-capsule { image-index = <0x1>; @@ -166,7 +91,7 @@ }; }; - capsule10 { + capsule4 { filename = "Test105"; efi-capsule { image-index = <0x1>; @@ -179,37 +104,7 @@ }; }; - capsule11 { - filename = "Test11"; - efi-capsule { - image-index = <0x1>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - private-key = CAPSULE_PRIV_KEY; - public-key-cert = CAPSULE_PUB_KEY; - monotonic-count = <0x1>; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule12 { - filename = "Test12"; - efi-capsule { - image-index = <0x1>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - private-key = CAPSULE_INVAL_KEY; - public-key-cert = CAPSULE_INVAL_PUB_KEY; - monotonic-count = <0x1>; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule13 { + capsule5 { filename = "Test13"; efi-capsule { image-index = <0x1>; @@ -224,7 +119,7 @@ }; }; - capsule14 { + capsule6 { filename = "Test14"; efi-capsule { image-index = <0x1>; @@ -239,55 +134,7 @@ }; }; - capsule15 { - filename = "Test111"; - efi-capsule { - image-index = <0x1>; - fw-version = <0x5>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - private-key = CAPSULE_PRIV_KEY; - public-key-cert = CAPSULE_PUB_KEY; - monotonic-count = <0x1>; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule16 { - filename = "Test112"; - efi-capsule { - image-index = <0x2>; - fw-version = <0xa>; - image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID; - private-key = CAPSULE_PRIV_KEY; - public-key-cert = CAPSULE_PUB_KEY; - monotonic-count = <0x1>; - - text { - text = "u-boot-env:New"; - }; - }; - }; - - capsule17 { - filename = "Test113"; - efi-capsule { - image-index = <0x1>; - fw-version = <0x2>; - image-guid = SANDBOX_UBOOT_IMAGE_GUID; - private-key = CAPSULE_PRIV_KEY; - public-key-cert = CAPSULE_PUB_KEY; - monotonic-count = <0x1>; - - text { - text = "u-boot:New"; - }; - }; - }; - - capsule18 { + capsule7 { filename = "Test114"; efi-capsule { image-index = <0x1>; @@ -303,7 +150,7 @@ }; }; - capsule19 { + capsule8 { filename = "Test115"; efi-capsule { image-index = <0x1>; diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index dd41da9284e..80b12977d6f 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -85,6 +85,7 @@ def efi_capsule_data(request, u_boot_config): check_call('cd %s; ' './tools/binman/binman --toolpath %s/tools build -u -d %s/capsule_binman.dtb -O %s -m --allow-missing -I %s -I ./board/sandbox -I ./arch/sandbox/dts' % (u_boot_config.source_dir, u_boot_config.build_dir, data_dir, data_dir, data_dir), shell=True) + check_call('cp %s/Test* %s' % (u_boot_config.build_dir, data_dir), shell=True) os.environ['PYTHONPATH'] = pythonpath # Create a disk image with EFI system partition diff --git a/test/py/tests/test_scsi.py b/test/py/tests/test_scsi.py index be2e283e7d2..445693cafd7 100644 --- a/test/py/tests/test_scsi.py +++ b/test/py/tests/test_scsi.py @@ -87,6 +87,6 @@ def test_scsi_dev(u_boot_console): def test_scsi_part(u_boot_console): test_scsi_dev(u_boot_console) output = u_boot_console.run_command('scsi part') - assert 'Partition Map for SCSI device' in output + assert 'Partition Map for scsi device' in output output = u_boot_console.run_command('echo $?') assert output.endswith('0') diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py index fe81a1f51b1..c6df64c5316 100644 --- a/tools/binman/btool/openssl.py +++ b/tools/binman/btool/openssl.py @@ -283,6 +283,7 @@ emailAddress = {req_dist_name_dict['emailAddress']} basicConstraints = CA:true 1.3.6.1.4.1.294.1.3=ASN1:SEQUENCE:swrv 1.3.6.1.4.1.294.1.9=ASN1:SEQUENCE:ext_boot_info +1.3.6.1.4.1.294.1.8=ASN1:SEQUENCE:debug [swrv] swrv=INTEGER:{sw_rev} @@ -323,6 +324,12 @@ compSize = INTEGER:{imagesize_sysfw_data} shaType = OID:{sha_type} shaValue = FORMAT:HEX,OCT:{hashval_sysfw_data} +[ debug ] +debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 +debugType = INTEGER:4 +coreDbgEn = INTEGER:0 +coreDbgSecEn = INTEGER:0 + {sysfw_inner_cert_ext_boot_block} {dm_data_ext_boot_block} diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py index 2c3bb8f7b56..c10d66edcb1 100644 --- a/tools/binman/etype/ti_board_config.py +++ b/tools/binman/etype/ti_board_config.py @@ -248,7 +248,7 @@ class Entry_ti_board_config(Entry_section): yaml_config = config.YamlLintConfig("extends: default") for p in yamllint.linter.run(open(self._config_file, "r"), yaml_config): - self.Raise(f"Yamllint error: {p.line}: {p.rule}") + self.Raise(f"Yamllint error: Line {p.line} in {self._config_file}: {p.rule}") try: validate(self.file_yaml, self.schema_yaml) except Exception as e: diff --git a/tools/fit_image.c b/tools/fit_image.c index beef1fa86e2..0fccfbb4ebd 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -137,7 +137,7 @@ static int fdt_property_file(struct image_tool_params *params, int ret; int fd; - fd = open(fname, O_RDWR | O_BINARY); + fd = open(fname, O_RDONLY | O_BINARY); if (fd < 0) { fprintf(stderr, "%s: Can't open %s: %s\n", params->cmdname, fname, strerror(errno)); diff --git a/tools/image-host.c b/tools/image-host.c index b2a0f2e6d16..7bfc0cb6b18 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -346,17 +346,17 @@ static int fit_image_read_key_iv_data(const char *keydir, const char *key_iv_nam unsigned char *key_iv_data, int expected_size) { char filename[PATH_MAX]; - int ret = -1; + int ret; ret = snprintf(filename, sizeof(filename), "%s/%s%s", keydir, key_iv_name, ".bin"); if (ret >= sizeof(filename)) { - printf("Can't format the key or IV filename when setting up the cipher: insufficient buffer space\n"); - ret = -1; + fprintf(stderr, "Can't format the key or IV filename when setting up the cipher: insufficient buffer space\n"); + return -1; } if (ret < 0) { - printf("Can't format the key or IV filename when setting up the cipher: snprintf error\n"); - ret = -1; + fprintf(stderr, "Can't format the key or IV filename when setting up the cipher: snprintf error\n"); + return -1; } ret = fit_image_read_data(filename, key_iv_data, expected_size); diff --git a/tools/proftool.c b/tools/proftool.c index fca45e4a5af..c2e38099354 100644 --- a/tools/proftool.c +++ b/tools/proftool.c @@ -290,7 +290,7 @@ static void usage(void) "Options:\n" " -c <cfg>\tSpecify config file\n" " -f <subtype>\tSpecify output subtype\n" - " -m <map>\tSpecify Systen.map file\n" + " -m <map>\tSpecify System.map file\n" " -o <fname>\tSpecify output file\n" " -t <fname>\tSpecify trace data file (from U-Boot 'trace calls')\n" " -v <0-4>\tSpecify verbosity\n" @@ -306,7 +306,7 @@ static void usage(void) } /** - * h_cmp_offset - bsearch() function to compare two functions bny their offset + * h_cmp_offset - bsearch() function to compare two functions by their offset * * @v1: Pointer to first function (struct func_info) * @v2: Pointer to second function (struct func_info) @@ -431,7 +431,7 @@ static struct func_info *find_func_by_offset(uint offset) static struct func_info *find_caller_by_offset(uint offset) { int low; /* least function that could be a match */ - int high; /* greated function that could be a match */ + int high; /* greatest function that could be a match */ struct func_info key; low = 0; @@ -1352,7 +1352,7 @@ static int write_pages(struct twriter *tw, enum out_format_t out_format, } if (!(func->flags & FUNCF_TRACE)) { - debug("Funcion '%s' is excluded from trace\n", + debug("Function '%s' is excluded from trace\n", func->name); skip_count++; continue; @@ -1781,7 +1781,8 @@ static int make_flame_tree(enum out_format_t out_format, * * This works by maintaining a string shared across all recursive calls. The * function name for this node is added to the existing string, to make up the - * full call-stack description. For example, on entry, @str might contain: + * full call-stack description. For example, on entry, @str_buf->data might + * contain: * * "initf_bootstage;bootstage_mark_name" * ^ @base @@ -1795,18 +1796,18 @@ static int make_flame_tree(enum out_format_t out_format, * @fout: Output file * @out_format: Output format to use * @node: Node to output (pass the whole tree at first) - * @str: String to use to build the output line (e.g. 500 charas long) - * @maxlen: Maximum length of string + * @str_buf: String buffer to use to build the output line * @base: Current base position in the string * @treep: Returns the resulting flamegraph tree * Returns 0 if OK, -1 on error */ static int output_tree(FILE *fout, enum out_format_t out_format, - const struct flame_node *node, char *str, int maxlen, + const struct flame_node *node, struct abuf *str_buf, int base) { const struct flame_node *child; int pos; + char *str = abuf_data(str_buf); if (node->count) { if (out_format == OUT_FMT_FLAMEGRAPH_CALLS) { @@ -1832,18 +1833,29 @@ static int output_tree(FILE *fout, enum out_format_t out_format, if (pos) str[pos++] = ';'; list_for_each_entry(child, &node->child_head, sibling_node) { - int len; + int len, needed; len = strlen(child->func->name); - if (pos + len + 1 >= maxlen) { - fprintf(stderr, "String too short (%d chars)\n", - maxlen); - return -1; + needed = pos + len + 1; + if (needed > abuf_size(str_buf)) { + /* + * We need to re-allocate the string buffer; increase + * its size by multiples of 500 characters. + */ + needed = 500 * ((needed / 500) + 1); + if (!abuf_realloc(str_buf, needed)) + return -1; + str = abuf_data(str_buf); + memset(str + pos, 0, abuf_size(str_buf) - pos); } strcpy(str + pos, child->func->name); - if (output_tree(fout, out_format, child, str, maxlen, - pos + len)) + if (output_tree(fout, out_format, child, str_buf, pos + len)) return -1; + /* + * Update our pointer as the string buffer might have been + * re-allocated. + */ + str = abuf_data(str_buf); } return 0; @@ -1859,16 +1871,24 @@ static int output_tree(FILE *fout, enum out_format_t out_format, static int make_flamegraph(FILE *fout, enum out_format_t out_format) { struct flame_node *tree; - char str[500]; + struct abuf str_buf; + char *str; + int ret = 0; if (make_flame_tree(out_format, &tree)) return -1; - *str = '\0'; - if (output_tree(fout, out_format, tree, str, sizeof(str), 0)) + abuf_init(&str_buf); + if (!abuf_realloc(&str_buf, 500)) return -1; - return 0; + str = abuf_data(&str_buf); + memset(str, 0, abuf_size(&str_buf)); + if (output_tree(fout, out_format, tree, &str_buf, 0)) + ret = -1; + + abuf_uninit(&str_buf); + return ret; } /** |