diff options
53 files changed, 1909 insertions, 2140 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 043d963f634..a8f770b57b0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,12 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_BANANAPI_F3 + bool "Support BananaPi F3 Board" + +config TARGET_LICHEERV_NANO + bool "Support LicheeRV Nano Board" + config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -92,6 +98,8 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" +source "board/sophgo/licheerv_nano/Kconfig" +source "board/spacemit/bananapi-f3/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" @@ -104,6 +112,7 @@ source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/ast2700/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" +source "arch/riscv/cpu/k1/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index e5549a01b83..fa47e55226e 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -16,16 +16,17 @@ config STARFIVE_JH7110 select SYS_CACHE_SHIFT_6 select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 + imply SMP + imply SPL_RISCV_ACLINT + imply SIFIVE_CACHE + imply SPL_SYS_MALLOC_CLEAR_ON_INIT + imply SPL_LOAD_FIT + imply SPL_CPU + imply SPL_OPENSBI + imply OF_UPSTREAM + imply SIFIVE_CCACHE imply MMC imply MMC_BROKEN_CD imply MMC_SPI - imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CACHE - imply SIFIVE_CCACHE - imply SMP imply SPI - imply SPL_CPU - imply SPL_LOAD_FIT - imply SPL_OPENSBI - imply SPL_RISCV_ACLINT - imply SPL_SYS_MALLOC_CLEAR_ON_INIT + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig new file mode 100644 index 00000000000..d9cd8dce964 --- /dev/null +++ b/arch/riscv/cpu/k1/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024, Kongyang Liu <seashell11234455@gmail.com> + +config SPACEMIT_K1 + bool + select BINMAN + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/k1/Makefile b/arch/riscv/cpu/k1/Makefile new file mode 100644 index 00000000000..bad4f4cf46f --- /dev/null +++ b/arch/riscv/cpu/k1/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/k1/cpu.c b/arch/riscv/cpu/k1/cpu.c new file mode 100644 index 00000000000..41a4a1b95e6 --- /dev/null +++ b/arch/riscv/cpu/k1/cpu.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int cleanup_before_linux(void) +{ + return 0; +} diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c new file mode 100644 index 00000000000..c477c15cbfb --- /dev/null +++ b/arch/riscv/cpu/k1/dram.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +#include <asm/global_data.h> +#include <config.h> +#include <fdt_support.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_base = CFG_SYS_SDRAM_BASE; + /* TODO get ram size from ddr controller */ + gd->ram_size = SZ_4G; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + + if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = 0x100000000; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + if (gd->ram_size > SZ_2G) + return SZ_2G; + + return gd->ram_size; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + start[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + + return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +} diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index de356584bf1..b64fc0daf3c 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,13 +1,15 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb +dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 00000000000..7871294e90d --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ { + aliases { + spi0 = &qspi; + }; + + chosen { + bootph-pre-ram; + }; + + firmware { + spi0 = &qspi; + bootph-pre-ram; + }; + + config { + bootph-pre-ram; + u-boot,spl-payload-offset = <0x100000>; + }; + + memory@40000000 { + bootph-pre-ram; + }; +}; + +&uart0 { + bootph-pre-ram; + reg-offset = <0>; + current-speed = <115200>; + clock-frequency = <24000000>; +}; + +&mmc0 { + bootph-pre-ram; +}; + +&mmc1 { + bootph-pre-ram; +}; + +&qspi { + bootph-pre-ram; + + flash@0 { + bootph-pre-ram; + cdns,read-delay = <2>; + spi-max-frequency = <100000000>; + }; +}; + +&syscrg { + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>; +}; + +&sysgpio { + bootph-pre-ram; +}; + +&mmc0_pins { + bootph-pre-ram; + rst-pins { + bootph-pre-ram; + }; +}; + +&mmc1_pins { + bootph-pre-ram; + clk-pins { + bootph-pre-ram; + }; + + mmc-pins { + bootph-pre-ram; + }; +}; + +&i2c5_pins { + bootph-pre-ram; + i2c-pins { + bootph-pre-ram; + }; +}; + +&i2c5 { + bootph-pre-ram; + eeprom@50 { + bootph-pre-ram; + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&binman { + itb { + fit { + images { + fdt-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb"; + }; + }; + + fdt-jh7110-pine64-star64 { + description = "jh7110-pine64-star64"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb"; + }; + }; + + fdt-jh7110-starfive-visionfive-2-v1.2a { + description = "jh7110-starfive-visionfive-2-v1.2a"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; + }; + }; + + fdt-jh7110-starfive-visionfive-2-v1.3b { + description = "jh7110-starfive-visionfive-2-v1.3b"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; + }; + }; + }; + + configurations { + conf-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-milkv-mars"; + }; + + conf-jh7110-pine64-star64 { + description = "jh7110-pine64-star64"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-pine64-star64"; + }; + + conf-jh7110-starfive-visionfive-2-v1.2a { + description = "jh7110-starfive-visionfive-2-v1.2a"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a"; + }; + + conf-jh7110-starfive-visionfive-2-v1.3b { + description = "jh7110-starfive-visionfive-2-v1.3b"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b"; + }; + }; + }; + }; + + spl-img { + filename = "spl/u-boot-spl.bin.normal.out"; + + mkimage { + args = "-T sfspl"; + + u-boot-spl { + }; + }; + }; +}; diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi new file mode 100644 index 00000000000..9df1e5db553 --- /dev/null +++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi new file mode 100644 index 00000000000..9df1e5db553 --- /dev/null +++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi deleted file mode 100644 index 3012466b305..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "binman.dtsi" -#include "jh7110-u-boot.dtsi" -/ { - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - config { - bootph-pre-ram; - u-boot,spl-payload-offset = <0x100000>; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - - nor-flash@0 { - bootph-pre-ram; - }; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - mmc0-pins-rest { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - mmc1-pins0 { - bootph-pre-ram; - }; - - mmc1-pins1 { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - }; -}; - -&binman { - itb { - fit { - images { - fdt-1 { - description = "NAME"; - load = <0x40400000>; - compression = "none"; - - uboot_fdt_blob: blob-ext { - filename = "u-boot.dtb"; - }; - }; - }; - - configurations { - conf-1 { - fdt = "fdt-1"; - }; - }; - }; - }; - - spl-img { - filename = "spl/u-boot-spl.bin.normal.out"; - - mkimage { - args = "-T sfspl"; - - u-boot-spl { - }; - }; - }; -}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi new file mode 100644 index 00000000000..9df1e5db553 --- /dev/null +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi new file mode 100644 index 00000000000..e6bc6630dcd --- /dev/null +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts deleted file mode 100644 index 288ea394939..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include "jh7110-starfive-visionfive-2.dtsi" - -/ { - compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; -}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi deleted file mode 100644 index e11babc1cde..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; - -#include "jh7110.dtsi" -#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> -#include <dt-bindings/gpio/gpio.h> -/ { - aliases { - serial0 = &uart0; - spi0 = &qspi; - mmc0 = &mmc0; - mmc1 = &mmc1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - timebase-frequency = <4000000>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x2 0x0>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&rtc_osc { - clock-frequency = <32768>; -}; - -&gmac0_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac0_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&gmac1_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac1_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&i2stx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2stx_lrck_ext { - clock-frequency = <192000>; -}; - -&i2srx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2srx_lrck_ext { - clock-frequency = <192000>; -}; - -&tdm_ext { - clock-frequency = <49152000>; -}; - -&mclk_ext { - clock-frequency = <12288000>; -}; - -&uart0 { - reg-offset = <0>; - current-speed = <115200>; - clock-frequency = <24000000>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - status = "okay"; - - pmic@36 { - compatible = "x-powers,axp15060"; - reg = <0x36>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c6 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - status = "okay"; -}; - -&sysgpio { - status = "okay"; - uart0_pins: uart0-0 { - tx-pins { - pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, - GPOEN_ENABLE, - GPI_NONE)>; - bias-disable; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pinmux = <GPIOMUX(6, GPOUT_LOW, - GPOEN_DISABLE, - GPI_SYS_UART0_RX)>; - bias-disable; /* external pull-up */ - drive-strength = <2>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; - - i2c0_pins: i2c0-0 { - i2c-pins { - pinmux = <GPIOMUX(57, GPOUT_LOW, - GPOEN_SYS_I2C0_CLK, - GPI_SYS_I2C0_CLK)>, - <GPIOMUX(58, GPOUT_LOW, - GPOEN_SYS_I2C0_DATA, - GPI_SYS_I2C0_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c2_pins: i2c2-0 { - i2c-pins { - pinmux = <GPIOMUX(3, GPOUT_LOW, - GPOEN_SYS_I2C2_CLK, - GPI_SYS_I2C2_CLK)>, - <GPIOMUX(2, GPOUT_LOW, - GPOEN_SYS_I2C2_DATA, - GPI_SYS_I2C2_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c5_pins: i2c5-0 { - i2c-pins { - pinmux = <GPIOMUX(19, GPOUT_LOW, - GPOEN_SYS_I2C5_CLK, - GPI_SYS_I2C5_CLK)>, - <GPIOMUX(20, GPOUT_LOW, - GPOEN_SYS_I2C5_DATA, - GPI_SYS_I2C5_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c6_pins: i2c6-0 { - i2c-pins { - pinmux = <GPIOMUX(16, GPOUT_LOW, - GPOEN_SYS_I2C6_CLK, - GPI_SYS_I2C6_CLK)>, - <GPIOMUX(17, GPOUT_LOW, - GPOEN_SYS_I2C6_DATA, - GPI_SYS_I2C6_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - mmc0_pins: mmc0-pins { - mmc0-pins-rest { - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, - GPOEN_ENABLE, GPI_NONE)>; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mmc1_pins: mmc1-pins { - mmc1-pins0 { - pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, - GPOEN_ENABLE, GPI_NONE)>; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mmc1-pins1 { - pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, - GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>, - <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, - GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>, - <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, - GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>, - <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, - GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>, - <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, - GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>; - bias-pull-up; - drive-strength = <12>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&mmc0 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - cap-mmc-hw-reset; - post-power-on-delay-ms = <200>; - status = "okay"; - -}; - -&mmc1 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - no-sdio; - no-mmc; - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; - cap-sd-highspeed; - post-power-on-delay-ms = <200>; - status = "okay"; -}; - -&qspi { - spi-max-frequency = <250000000>; - status = "okay"; - - nor-flash@0 { - compatible = "jedec,spi-nor"; - reg=<0>; - spi-max-frequency = <100000000>; - cdns,tshsl-ns = <1>; - cdns,tsd2d-ns = <1>; - cdns,tchsh-ns = <1>; - cdns,tslch-ns = <1>; - }; -}; - -&pcie0 { - reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie1 { - reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&aoncrg { - assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; - assigned-clock-parents = <&osc>; - assigned-clock-rates = <0>; -}; - -&gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&gmac1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy1: ethernet-phy@1 { - reg = <0>; - }; - }; -}; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7296f..ce7d9e16961 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; }; + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + soc { bootph-pre-ram; @@ -62,7 +71,7 @@ <&syscrg JH7110_SYSRST_DDR_OSC>, <&syscrg JH7110_SYSRST_DDR_APB>; reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll1_out"; clock-frequency = <2133>; }; @@ -73,10 +82,22 @@ bootph-pre-ram; }; +&gmac0_rgmii_rxin { + bootph-pre-ram; +}; + &gmac0_rmii_refin { bootph-pre-ram; }; +&gmac1_rgmii_rxin { + bootph-pre-ram; +}; + +&gmac1_rmii_refin { + bootph-pre-ram; +}; + &aoncrg { bootph-pre-ram; }; @@ -92,7 +113,3 @@ &sys_syscon { bootph-pre-ram; }; - -&S7_0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi deleted file mode 100644 index 2cdc683d49b..00000000000 --- a/arch/riscv/dts/jh7110.dtsi +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include <dt-bindings/clock/starfive,jh7110-crg.h> -#include <dt-bindings/reset/starfive,jh7110-crg.h> - -/ { - compatible = "starfive,jh7110"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - S7_0: cpu@0 { - compatible = "sifive,s7", "riscv"; - reg = <0>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - riscv,isa = "rv64imac_zba_zbb"; - status = "disabled"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_1: cpu@1 { - compatible = "sifive,u74-mc", "riscv"; - reg = <1>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_2: cpu@2 { - compatible = "sifive,u74-mc", "riscv"; - reg = <2>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_3: cpu@3 { - compatible = "sifive,u74-mc", "riscv"; - reg = <3>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_4: cpu@4 { - compatible = "sifive,u74-mc", "riscv"; - reg = <4>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&S7_0>; - }; - - core1 { - cpu = <&U74_1>; - }; - - core2 { - cpu = <&U74_2>; - }; - - core3 { - cpu = <&U74_3>; - }; - - core4 { - cpu = <&U74_4>; - }; - }; - }; - }; - - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc"; - #clock-cells = <0>; - }; - - rtc_osc: rtc-oscillator { - compatible = "fixed-clock"; - clock-output-names = "rtc_osc"; - #clock-cells = <0>; - }; - - gmac0_rmii_refin: gmac0-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rmii_refin"; - #clock-cells = <0>; - }; - - gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rgmii_rxin"; - #clock-cells = <0>; - }; - - gmac1_rmii_refin: gmac1-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rmii_refin"; - #clock-cells = <0>; - }; - - gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rgmii_rxin"; - #clock-cells = <0>; - }; - - i2stx_bclk_ext: i2stx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_bclk_ext"; - #clock-cells = <0>; - }; - - i2stx_lrck_ext: i2stx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_lrck_ext"; - #clock-cells = <0>; - }; - - i2srx_bclk_ext: i2srx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_bclk_ext"; - #clock-cells = <0>; - }; - - i2srx_lrck_ext: i2srx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_lrck_ext"; - #clock-cells = <0>; - }; - - tdm_ext: tdm-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; - #clock-cells = <0>; - }; - - mclk_ext: mclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "mclk_ext"; - #clock-cells = <0>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,lpi_en; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <4>; - snps,blen = <256 128 64 32 0 0 0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clint: timer@2000000 { - compatible = "starfive,jh7110-clint", "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>; - }; - - plic: interrupt-controller@c000000 { - compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <0>; - riscv,ndev = <136>; - }; - - ccache: cache-controller@2010000 { - compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; - reg = <0x0 0x2010000 0x0 0x4000>; - interrupts = <1>, <3>, <4>, <2>; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - }; - - uart0: serial@10000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, - <&syscrg JH7110_SYSCLK_UART0_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART0_APB>, - <&syscrg JH7110_SYSRST_UART0_CORE>; - interrupts = <32>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@10010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, - <&syscrg JH7110_SYSCLK_UART1_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART1_APB>, - <&syscrg JH7110_SYSRST_UART1_CORE>; - interrupts = <33>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@10020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, - <&syscrg JH7110_SYSCLK_UART2_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART2_APB>, - <&syscrg JH7110_SYSRST_UART2_CORE>; - interrupts = <34>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@10030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C0_APB>; - interrupts = <35>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@10040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C1_APB>; - interrupts = <36>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@10050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C2_APB>; - interrupts = <37>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - stgcrg: clock-controller@10230000 { - compatible = "starfive,jh7110-stgcrg"; - reg = <0x0 0x10230000 0x0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - stg_syscon: stg_syscon@10240000 { - compatible = "starfive,jh7110-stg-syscon","syscon"; - reg = <0x0 0x10240000 0x0 0x1000>; - }; - - uart3: serial@12000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, - <&syscrg JH7110_SYSCLK_UART3_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART3_APB>, - <&syscrg JH7110_SYSRST_UART3_CORE>; - interrupts = <45>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@12010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, - <&syscrg JH7110_SYSCLK_UART4_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART4_APB>, - <&syscrg JH7110_SYSRST_UART4_CORE>; - interrupts = <46>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@12020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, - <&syscrg JH7110_SYSCLK_UART5_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART5_APB>, - <&syscrg JH7110_SYSRST_UART5_CORE>; - interrupts = <47>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c3: i2c@12030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C3_APB>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@12040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C4_APB>; - interrupts = <49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@12050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C5_APB>; - interrupts = <50>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@12060000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12060000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C6_APB>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - power-controller@17030000 { - compatible = "starfive,jh7110-pmu"; - reg = <0x0 0x17030000 0x0 0x10000>; - interrupts = <111>; - }; - - qspi: spi@13010000 { - compatible = "cdns,qspi-nor"; - reg = <0x0 0x13010000 0x0 0x10000 - 0x0 0x21000000 0x0 0x400000>; - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; - clock-names = "clk_ref"; - resets = <&syscrg JH7110_SYSRST_QSPI_APB>, - <&syscrg JH7110_SYSRST_QSPI_AHB>, - <&syscrg JH7110_SYSRST_QSPI_REF>; - reset-names = "rst_apb", "rst_ahb", "rst_ref"; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - syscrg: clock-controller@13020000 { - compatible = "starfive,jh7110-syscrg"; - reg = <0x0 0x13020000 0x0 0x10000>; - clocks = <&osc>, <&gmac1_rmii_refin>, - <&gmac1_rgmii_rxin>, - <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, - <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>, - <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL1_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>; - clock-names = "osc", "gmac1_rmii_refin", - "gmac1_rgmii_rxin", - "i2stx_bclk_ext", "i2stx_lrck_ext", - "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext", - "pll0_out", "pll1_out", "pll2_out"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sys_syscon: sys_syscon@13030000 { - compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; - reg = <0x0 0x13030000 0x0 0x1000>; - - pllclk: clock-controller { - compatible = "starfive,jh7110-pll"; - clocks = <&osc>; - #clock-cells = <1>; - }; - }; - - sysgpio: pinctrl@13040000 { - compatible = "starfive,jh7110-sys-pinctrl"; - reg = <0x0 0x13040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; - resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; - interrupts = <86>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - watchdog@13070000 { - compatible = "starfive,jh7110-wdt"; - reg = <0x0 0x13070000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, - <&syscrg JH7110_SYSCLK_WDT_CORE>; - clock-names = "apb", "core"; - resets = <&syscrg JH7110_SYSRST_WDT_APB>, - <&syscrg JH7110_SYSRST_WDT_CORE>; - }; - - mmc0: mmc@16010000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, - <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; - reset-names = "reset"; - interrupts = <74>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; - status = "disabled"; - }; - - mmc1: mmc@16020000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, - <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; - reset-names = "reset"; - interrupts = <75>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; - status = "disabled"; - }; - - gmac0: ethernet@16030000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16030000 0x0 0x10000>; - clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, - <&aoncrg JH7110_AONCLK_GMAC0_AHB>, - <&syscrg JH7110_SYSCLK_GMAC0_PTP>, - <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, - <&aoncrg JH7110_AONRST_GMAC0_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <7>, <6>, <5>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&aon_syscon 0xc 0x12>; - status = "disabled"; - }; - - gmac1: ethernet@16040000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, - <&syscrg JH7110_SYSCLK_GMAC1_AHB>, - <&syscrg JH7110_SYSCLK_GMAC1_PTP>, - <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, - <&syscrg JH7110_SYSRST_GMAC1_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <78>, <77>, <76>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&sys_syscon 0x90 0x2>; - status = "disabled"; - }; - - rng: rng@1600c000 { - compatible = "starfive,jh7110-trng"; - reg = <0x0 0x1600C000 0x0 0x4000>; - clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, - <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; - clock-names = "hclk", "ahb"; - resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; - interrupts = <30>; - }; - - aoncrg: clock-controller@17000000 { - compatible = "starfive,jh7110-aoncrg"; - reg = <0x0 0x17000000 0x0 0x10000>; - clocks = <&osc>, <&rtc_osc>, - <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, - <&syscrg JH7110_SYSCLK_STG_AXIAHB>, - <&syscrg JH7110_SYSCLK_APB_BUS>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; - clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", - "gmac0_rgmii_rxin", "stg_axiahb", - "apb_bus", "gmac0_gtxclk"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - aon_syscon: aon_syscon@17010000 { - compatible = "starfive,jh7110-aon-syscon","syscon"; - reg = <0x0 0x17010000 0x0 0x1000>; - }; - - aongpio: pinctrl@17020000 { - compatible = "starfive,jh7110-aon-pinctrl"; - reg = <0x0 0x17020000 0x0 0x10000>; - resets = <&aoncrg JH7110_AONRST_IOMUX>; - interrupts = <85>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcie0: pcie@2b000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2b000000 0x0 0x1000000 - 0x9 0x40000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, - <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; - interrupts = <56>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_TL>, - <&stgcrg JH7110_STGCLK_PCIE0_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV>, - <&stgcrg JH7110_STGRST_PCIE0_BRG>, - <&stgcrg JH7110_STGRST_PCIE0_CORE>, - <&stgcrg JH7110_STGRST_PCIE0_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - - pcie1: pcie@2c000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2c000000 0x0 0x1000000 - 0x9 0xc0000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, - <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; - interrupts = <57>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_TL>, - <&stgcrg JH7110_STGCLK_PCIE1_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV>, - <&stgcrg JH7110_STGRST_PCIE1_BRG>, - <&stgcrg JH7110_STGRST_PCIE1_CORE>, - <&stgcrg JH7110_STGRST_PCIE1_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - }; -}; diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts new file mode 100644 index 00000000000..d2486f70906 --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> + */ + +#include "k1.dtsi" +#include "binman.dtsi" + +/ { + model = "Banana Pi BPI-F3"; + compatible = "bananapi,bpi-f3", "spacemit,k1"; + + chosen { + stdout-path = "serial0"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi new file mode 100644 index 00000000000..514be453dba --- /dev/null +++ b/arch/riscv/dts/k1.dtsi @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> + */ + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K1"; + compatible = "spacemit,k1"; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + + cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster0_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <128>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <128>; + next-level-cache = <&cluster1_l2_cache>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cluster0_l2_cache: l2-cache0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + + cluster1_l2_cache: l2-cache1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <512>; + cache-unified; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + interrupts = <42>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + interrupts = <44>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + interrupts = <45>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xe0000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + riscv,ndev = <159>; + }; + + clint: timer@e4000000 { + compatible = "spacemit,k1-clint", "sifive,clint0"; + reg = <0x0 0xe4000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + sec_uart1: serial@f0612000 { + compatible = "spacemit,k1-uart", "snps,dw-apb-uart"; + reg = <0x0 0xf0612000 0x0 0x100>; + interrupts = <43>; + clock-frequency = <14857000>; + reg-shift = <2>; + reg-io-width = <4>; + status = "reserved"; /* for TEE usage */ + }; + }; +};
\ No newline at end of file diff --git a/arch/riscv/dts/sg2002-licheerv-nano-b.dts b/arch/riscv/dts/sg2002-licheerv-nano-b.dts new file mode 100644 index 00000000000..9871a75836c --- /dev/null +++ b/arch/riscv/dts/sg2002-licheerv-nano-b.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com> + */ + +/dts-v1/; + +#include "sg2002.dtsi" + +/ { + model = "LicheeRV Nano B"; + compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/dts/sg2002.dtsi b/arch/riscv/dts/sg2002.dtsi new file mode 100644 index 00000000000..0f97000fa8b --- /dev/null +++ b/arch/riscv/dts/sg2002.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com> + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "cv18xx.dtsi" + +/ { + compatible = "sophgo,sg2002"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&plic { + compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-plic", "thead,c900-plic"; +}; + +&clint { + compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-clint", "thead,c900-clint"; +}; + +&clk { + compatible = "sophgo,sg2002-clk", "sophgo,cv1800-clk"; +}; + +&sdhci0 { + compatible = "sophgo,sg2002-dwcmshc", "sophgo,cv1800b-dwcmshc"; +}; diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index dc00e3dfa02..86a81bdcf77 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -32,3 +32,21 @@ &uart_sclk { clock-frequency = <100000000>; }; + +&emmc { + bus-width = <8>; + max-frequency = <198000000>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + max-frequency = <198000000>; + status = "okay"; +}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index f7bfa422439..cbe3481fadd 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -134,6 +134,13 @@ #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -173,6 +180,33 @@ status = "disabled"; }; + emmc: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + + sdio0: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + + sdio1: mmc@ffe70a0000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe70a0000 0x0 0x10000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + uart1: serial@ffe7f00000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f00000 0x0 0x100>; diff --git a/board/sophgo/licheerv_nano/Kconfig b/board/sophgo/licheerv_nano/Kconfig new file mode 100644 index 00000000000..660d3c5d095 --- /dev/null +++ b/board/sophgo/licheerv_nano/Kconfig @@ -0,0 +1,28 @@ +if TARGET_LICHEERV_NANO + +config SYS_BOARD + default "licheerv_nano" + +config SYS_VENDOR + default "sophgo" + +config SYS_CPU + default "cv1800b" + +config SYS_CONFIG_NAME + default "licheerv_nano" + +config TEXT_BASE + default 0x80200000 + +config ENV_SIZE + default 0x20000 + +config ENV_SECT_SIZE + default 0x40000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOPHGO_CV1800B + +endif diff --git a/board/sophgo/licheerv_nano/MAINTAINERS b/board/sophgo/licheerv_nano/MAINTAINERS new file mode 100644 index 00000000000..c56060db081 --- /dev/null +++ b/board/sophgo/licheerv_nano/MAINTAINERS @@ -0,0 +1,5 @@ +LicheeRV Nano +M: Thomas Bonnefille <thomas.bonnefille@bootlin.com> +S: Maintained +F: board/sophgo/licheerv_nano/ +F: configs/sipeed_licheerv_nano_defconfig diff --git a/board/sophgo/licheerv_nano/Makefile b/board/sophgo/licheerv_nano/Makefile new file mode 100644 index 00000000000..59fcd5bfba9 --- /dev/null +++ b/board/sophgo/licheerv_nano/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y += board.o diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c new file mode 100644 index 00000000000..eaa47be1739 --- /dev/null +++ b/board/sophgo/licheerv_nano/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/bananapi-f3/Kconfig new file mode 100644 index 00000000000..f89fa9af2c7 --- /dev/null +++ b/board/spacemit/bananapi-f3/Kconfig @@ -0,0 +1,25 @@ +if TARGET_BANANAPI_F3 + +config SYS_BOARD + default "bananapi-f3" + +config SYS_VENDOR + default "spacemit" + +config SYS_CPU + default "k1" + +config SYS_CONFIG_NAME + default "bananapi-f3" + +config TEXT_BASE + default 0x00200000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x00000000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SPACEMIT_K1 + +endif diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS new file mode 100644 index 00000000000..131bad03181 --- /dev/null +++ b/board/spacemit/bananapi-f3/MAINTAINERS @@ -0,0 +1,6 @@ +BananaPi F3 +M: Huan Zhou <pericycle.cc@@gmail.com> +S: Maintained +F: board/spacemit/bananapi-f3/ +F: configs/bananapi-f3_defconfig +F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile new file mode 100644 index 00000000000..2168698402b --- /dev/null +++ b/board/spacemit/bananapi-f3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + +obj-y := board.o diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c new file mode 100644 index 00000000000..2631cdd49e0 --- /dev/null +++ b/board/spacemit/bananapi-f3/board.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3fd535e7cfc..22afd76c6b9 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -20,364 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; #define JH7110_CLK_CPU_ROOT_SHIFT 24 #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24) -struct starfive_vf2_pro { - const char *path; - const char *name; - const char *value; -}; - -static const struct starfive_vf2_pro milk_v_mars[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1500"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "tx-internal-delay-ps", "1500"}, -}; - -static const struct starfive_vf2_pro starfive_vera[] = { - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", - "1900"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", - "1350"} -}; - -static const struct starfive_vf2_pro starfive_verb[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1500"}, - - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-adj-enabled", NULL}, - { "/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "rx-internal-delay-ps", "0"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "tx-internal-delay-ps", "0"}, -}; - -static const struct starfive_vf2_pro star64_pine64[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-10-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1900"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "tx-internal-delay-ps", "1500"}, - - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-10-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-clk-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "rx-internal-delay-ps", "0"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "tx-internal-delay-ps", "300"}, -}; - -void spl_fdt_fixup_mars(void *fdt) -{ - static const char compat[] = "milkv,mars\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "Milk-V Mars"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), - "status", "disabled"); - - for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) { - offset = fdt_path_offset(fdt, milk_v_mars[i].path); - - if (milk_v_mars[i].value) - ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name, - dectoul(milk_v_mars[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name); - break; - } - } -} - -void spl_fdt_fixup_mars_cm(void *fdt) -{ - const char *compat; - const char *model; - int compat_size; - - spl_fdt_fixup_mars(fdt); - - if (!get_mmc_size_from_eeprom()) { - int offset; - static const char - compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110"; - - model = "Milk-V Mars CM Lite"; - compat = compat_cm_lite; - compat_size = sizeof(compat_cm_lite); - - offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); - /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ - fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); - } else { - static const char - compat_cm[] = "milkv,mars-cm\0starfive,jh7110"; - - model = "Milk-V Mars CM"; - compat = compat_cm; - compat_size = sizeof(compat_cm); - } - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), - "compatible", compat, compat_size); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); -} - -void spl_fdt_fixup_version_a(void *fdt) -{ - static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "StarFive VisionFive 2 v1.2A"); - - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX); - - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), - "phy-mode", "rmii"); - - for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) { - offset = fdt_path_offset(fdt, starfive_vera[i].path); - - if (starfive_vera[i].value) - ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name, - dectoul(starfive_vera[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name); - break; - } - } -} - -void spl_fdt_fixup_version_b(void *fdt) -{ - static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "StarFive VisionFive 2 v1.3B"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { - offset = fdt_path_offset(fdt, starfive_verb[i].path); - - if (starfive_verb[i].value) - ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, - dectoul(starfive_verb[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); - break; - } - } -} - -void spl_fdt_fixup_star64(void *fdt) -{ - static const char compat[] = "pine64,star64\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "Pine64 Star64"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { - offset = fdt_path_offset(fdt, star64_pine64[i].path); - - if (star64_pine64[i].value) - ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, - dectoul(star64_pine64[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); - break; - } - } -} - void spl_perform_fixups(struct spl_image_info *spl_image) { - u8 version; - const char *product_id; - - product_id = get_product_id_from_eeprom(); - if (!product_id) { - pr_err("Can't read EEPROM\n"); - return; - } - if (!strncmp(product_id, "MARC", 4)) { - spl_fdt_fixup_mars_cm(spl_image->fdt_addr); - } else if (!strncmp(product_id, "MARS", 4)) { - spl_fdt_fixup_mars(spl_image->fdt_addr); - } else if (!strncmp(product_id, "VF7110", 6)) { - version = get_pcb_revision_from_eeprom(); - switch (version) { - case 'a': - case 'A': - spl_fdt_fixup_version_a(spl_image->fdt_addr); - break; - - case 'b': - case 'B': - default: - spl_fdt_fixup_version_b(spl_image->fdt_addr); - break; - }; - } else if (!strncmp(product_id, "STAR64", 6)) { - spl_fdt_fixup_star64(spl_image->fdt_addr); - } else { - pr_err("Unknown product %s\n", product_id); - }; - /* Update the memory size which read from eeprom or DT */ fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } @@ -466,10 +110,39 @@ void board_init_f(ulong dummy) } } -#if CONFIG_IS_ENABLED(SPL_LOAD_FIT) +#if CONFIG_IS_ENABLED(LOAD_FIT) int board_fit_config_name_match(const char *name) { - /* boot using first FIT config */ - return 0; + const char *product_id; + u8 version; + + product_id = get_product_id_from_eeprom(); + + if (!strncmp(product_id, "VF7110", 6)) { + version = get_pcb_revision_from_eeprom(); + if ((version == 'b' || version == 'B') && + !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b")) + return 0; + + if ((version == 'a' || version == 'A') && + !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a")) + return 0; + } else if (!strncmp(product_id, "MARS", 4) && + !strcmp(name, "jh7110-milkv-mars")) { + return 0; + } else if (!strncmp(product_id, "MARC", 4)) { + if (!get_mmc_size_from_eeprom()) { + if (!strcmp(name, "jh7110-milkv-mars-cm-lite")) + return 0; + } else { + if (!strcmp(name, "jh7110-milkv-mars-cm")) + return 0; + } + } else if (!strncmp(product_id, "STAR64", 6) && + !strcmp(name, "jh7110-pine64-star64")) { + return 0; + } + + return -EINVAL; } #endif diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 240543c9c7e..4e56d9909c8 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -751,6 +751,7 @@ config SPL_FS_LOAD_PAYLOAD_NAME depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING default "tispl.bin" if SYS_K3_SPL_ATF default "u-boot.itb" if SPL_LOAD_FIT + default "linux.itb" if SPL_LOAD_FIT_OPENSBI_OS_BOOT default "u-boot.img" help Filename to read to load U-Boot when reading from filesystem. diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig new file mode 100644 index 00000000000..63636202087 --- /dev/null +++ b/configs/bananapi-f3_defconfig @@ -0,0 +1,20 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" +CONFIG_SYS_LOAD_ADDR=0x200000 +CONFIG_TARGET_BANANAPI_F3=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0xa000000 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_HUSH_PARSER=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig new file mode 100644 index 00000000000..14fefa968c6 --- /dev/null +++ b/configs/sipeed_licheerv_nano_defconfig @@ -0,0 +1,47 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x820000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 +CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b" +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_IDENT_STRING="licheerv_nano" +CONFIG_TARGET_LICHEERV_NANO=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_BOOTSTD_FULL=y +# CONFIG_BOOTMETH_EFI_BOOTMGR is not set +CONFIG_SD_BOOT=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=544 +CONFIG_SYS_PROMPT="licheerv_nano# " +# CONFIG_CMD_BOOTDEV is not set +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +# CONFIG_CMD_MII is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_SOPHGO_CV1800B=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CV1800B_SPIF=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CV1800B=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 20f89ae6796..96056c50c84 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xf0000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" +CONFIG_DEFAULT_DEVICE_TREE="starfive/jh7110-starfive-visionfive-2-v1.3b" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y @@ -79,6 +79,8 @@ CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y +CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 3b6ff62ee12..d13c97463a8 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_MMC_SPEED_MODE_SET=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set @@ -66,7 +68,14 @@ CONFIG_NO_NET=y CONFIG_DWAPB_GPIO=y # CONFIG_I2C is not set # CONFIG_INPUT is not set -# CONFIG_DM_MMC is not set +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_SNPS=y # CONFIG_MTD is not set # CONFIG_POWER is not set CONFIG_SYS_NS16550=y diff --git a/doc/board/index.rst b/doc/board/index.rst index b54c1748d57..b1c470eb2cb 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -55,6 +55,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst index e097afdac64..26dba4a4851 100644 --- a/doc/board/sophgo/index.rst +++ b/doc/board/sophgo/index.rst @@ -6,3 +6,4 @@ Sophgo :maxdepth: 1 milkv_duo + licheerv_nano diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst new file mode 100644 index 00000000000..a75c6a37dc5 --- /dev/null +++ b/doc/board/sophgo/licheerv_nano.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LicheeRV Nano +============= + +SG2002 RISC-V SoC +----------------- +The SG2002 is a high-performance, low-power 64-bit RISC-V/ARM SoC from Sophgo. + +Mainline support +---------------- +The support for following drivers are already enabled: +1. ns16550 UART Driver. +2. Synopsys Designware MSHC Driver + +Building +~~~~~~~~ +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix> + cd <U-Boot-dir> + make sipeed_licheerv_nano_defconfig + make + +This will generate u-boot.bin + +Booting +~~~~~~~ +Currently, we rely on vendor FSBL (First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +To run u-boot.bin on top of FSBL, follow these steps: + +1. Use mainline OpenSBI with a newer version than 1.5 to generate fw_dynamic. + +2. Generate a compatible u-boot.bin using U-Boot with the LicheeRV Nano default + configuration. + +3. Use the vendor-provided tool [1] to create a unified fip.bin file containing + FSBL, OpenSBI, and U-Boot. + Note that you will have to use the file cv181x.bin as the FSBL. + +2. Place the generated fip.bin file into the FAT partition of the SD card. + +3. Insert the SD card into the board and power it on. + +The board will automatically execute the FSBL from the fip.bin file. +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke +U-Boot. + +[1]: https://github.com/sophgo/fiptool + + +Sample boot log from LicheeRV Nano board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + U-Boot 2024.10 (Oct 24 2024 - 15:00:20 +0200)licheerv_nano + + DRAM: 256 MiB + Core: 19 devices, 11 uclasses, devicetree: separate + MMC: mmc@4310000: 0 + Loading Environment from nowhere... OK + In: serial@4140000 + Out: serial@4140000 + Err: serial@4140000 + Net: No ethernet found. + Hit any key to stop autoboot: 0 + licheerv_nano# diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 00000000000..f2220950a3a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,106 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Banana Pi BPI-F3 +================ + +Building +~~~~~~~~ +1. Install the SpacemiT riscv cross compile toolchain_, or skip it if riscv toolchain is installed. + +.. _toolchain: https://archive.spacemit.com/toolchain/ + +2. Setup cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu-> + +3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below: + +.. code-block:: console + + git clone https://github.com/cyyself/opensbi -b k1-opensbi + cd opensbi + make PLATFORM=generic + +4. Then build U-Boot as following: + +.. code-block:: console + + cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin + +This will generate u-boot.itb + +Burning +~~~~~~~ +Actually, we can replace the uboot partition of Bianbu Linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card, +and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch. +Or use fastboot: +Collect FSBL.bin, u-boot.itb, partition_2M.json, bootinfo_spinor.bin +u-boot-env-default.bin, fw_dynamic.itb from vendor SDK + +.. code-block:: console + + fastboot stage FSBL.bin + fastboot continue + fastboot stage u-boot.itb-vendor # the itb from vendor uboot + fastboot continue + + fastboot flash mtd partition_2M.json + fastboot flash bootinfo bootinfo_spinor.bin + fastboot flash fsbl FSBL.bin + fastboot flash env u-boot-env-default.bin + fastboot flash opensbi fw_dynamic.itb + + fastboot flash uboot u-boot.itb-mainline # the itb from mainline uboot + +.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout + +Booting +~~~~~~~ +Sample boot log from Banana Pi BPI-F3 board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + try sd... + bm:3 + j... + + U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK + + + U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800) + + DRAM: 4 GiB + Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + => + diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 00000000000..e7d3d94e459 --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT +======== +.. toctree:: + :maxdepth: 1 + + bananapi-f3 + diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 6d2bfb3ecb7..f8af17227c5 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev) if (sysreg == FDT_ADDR_T_NONE) return -EINVAL; - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT), starfive_jh7110_pll("pll0_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll0)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT), starfive_jh7110_pll("pll1_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll1)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT), starfive_jh7110_pll("pll2_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll2)); diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75d7ba..6387e949d50 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB), starfive_clk_gate(priv->reg, "usb_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB), + OFFSET(JH7110_STGCLK_USB0_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB), starfive_clk_gate(priv->reg, "usb_utmi_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_UTMI_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI), + OFFSET(JH7110_STGCLK_USB0_UTMI_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI), starfive_clk_gate(priv->reg, "usb_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_USB_AXI))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM), + OFFSET(JH7110_STGCLK_USB0_AXI))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM), starfive_clk_gate_divider(priv->reg, "usb_lpm", "oscillator", - OFFSET(JH7110_STGCLK_USB_LPM), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB), + OFFSET(JH7110_STGCLK_USB0_LPM), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB), starfive_clk_gate_divider(priv->reg, "usb_stb", "oscillator", - OFFSET(JH7110_STGCLK_USB_STB), 3)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125), + OFFSET(JH7110_STGCLK_USB0_STB), 3)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125), starfive_clk_gate(priv->reg, "usb_app_125", "usb_125m", - OFFSET(JH7110_STGCLK_USB_APP_125))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK), + OFFSET(JH7110_STGCLK_USB0_APP_125))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK), starfive_clk_divider(priv->reg, "usb_refclk", "oscillator", - OFFSET(JH7110_STGCLK_USB_REFCLK), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI), + OFFSET(JH7110_STGCLK_USB0_REFCLK), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0), starfive_clk_gate(priv->reg, "pcie0_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE0_AXI))); + OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB), starfive_clk_gate(priv->reg, "pcie0_apb", "apb_bus", @@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE0_TL))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0), starfive_clk_gate(priv->reg, "pcie1_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE1_AXI))); + OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB), starfive_clk_gate(priv->reg, "pcie1_apb", "apb_bus", @@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev) OFFSET(JH7110_STGCLK_PCIE1_TL))); /* Security clocks */ - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB), starfive_clk_gate(priv->reg, "sec_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_HCLK))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + OFFSET(JH7110_STGCLK_SEC_AHB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB), starfive_clk_gate(priv->reg, "sec_misc_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + OFFSET(JH7110_STGCLK_SEC_MISC_AHB))); return 0; } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 38817622fca..f4fdf15242c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -732,6 +732,18 @@ config MMC_SDHCI_S5P If unsure, say N. +config MMC_SDHCI_SNPS + bool "Synopsys DesignWare SDHCI controller" + depends on MMC_SDHCI + depends on DM_MMC + help + Support for DesignWare SDHCI host controller on Alibaba TH1520 SoC. + This is a highly configurable and programmable, high performance + Mobile Storage Host Controller (MSHC) with AXI as the bus interface + for data transfer. + + If unsure, say N. + config MMC_SDHCI_STI bool "SDHCI support for STMicroelectronics SoC" depends on MMC_SDHCI && OF_CONTROL diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 868f3090ff2..90e76f90769 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_NPCM) += npcm_sdhci.o obj-$(CONFIG_MMC_SDHCI_PIC32) += pic32_sdhci.o obj-$(CONFIG_MMC_SDHCI_ROCKCHIP) += rockchip_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o +obj-$(CONFIG_MMC_SDHCI_SNPS) += snps_sdhci.o obj-$(CONFIG_MMC_SDHCI_STI) += sti_sdhci.o obj-$(CONFIG_MMC_SDHCI_TANGIER) += tangier_sdhci.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 47ab5654bd6..92880e0ed87 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -186,6 +186,7 @@ static int snps_dwmmc_bind(struct udevice *dev) static const struct udevice_id snps_dwmmc_ids[] = { { .compatible = "snps,dw-mshc" }, + { .compatible = "starfive,jh7110-mmc" }, { } }; diff --git a/drivers/mmc/snps_sdhci.c b/drivers/mmc/snps_sdhci.c new file mode 100644 index 00000000000..f5ede38c3c1 --- /dev/null +++ b/drivers/mmc/snps_sdhci.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Maksim Kiselev <bigunclemax@gmail.com> + */ + +#include <clk.h> +#include <dm.h> +#include <linux/bitfield.h> +#include <sdhci.h> + +/* DWCMSHC specific Mode Select value */ +#define DWCMSHC_CTRL_HS400 0x7 +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 +#define SDHCI_TUNING_LOOP_COUNT 128 + +/* PHY register area pointer */ +#define DWC_MSHC_PTR_PHY_R 0x300 + +/* PHY general configuration */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ + +/* PHY command/response pad settings */ +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) + +/* PHY data pad settings */ +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) + +/* PHY clock pad settings */ +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) + +/* PHY strobe pad settings */ +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) + +/* PHY reset pad settings */ +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) + +/* Bitfields are common for all pad settings */ +#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ +#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ + +#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ +#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ +#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ + +#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ +#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ +#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ + +/* PHY CLK delay line settings */ +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ + +/* PHY CLK delay line delay code */ +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ +#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ +#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ + +/* PHY drift_cclk_rx delay line configuration setting */ +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ +#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ + +/* PHY DLL control settings */ +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ +#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ + +/* PHY DLL configuration register 1 */ +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ +#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ +#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ + +/* PHY DLL configuration register 2 */ +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ + +/* PHY DLL master and slave delay line configuration settings */ +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ +#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ + +/* Vendor specific Registers */ +#define P_VENDOR_SPECIFIC_AREA 0x500 + +#define DWCMSHC_EMMC_CONTROL 0x2c +#define DWCMSHC_CARD_IS_EMMC BIT(0) +#define DWCMSHC_ENHANCED_STROBE BIT(8) +#define DWCMSHC_EMMC_ATCTRL 0x40 +/* Tuning and auto-tuning fields in AT_CTRL_R control register */ +#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ +#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ +#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ +#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ +#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ +#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ +#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ +#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ +#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ +#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ +#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ +#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ +#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ + +#define FLAG_IO_FIXED_1V8 BIT(0) + +#define BOUNDARY_OK(addr, len) \ + (((addr) | (SZ_128M - 1)) == (((addr) + (len) - 1) | (SZ_128M - 1))) + +struct snps_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; + u16 delay_line; + u16 flags; +}; + +/* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. + */ +void snps_sdhci_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, bool end) +{ + int tmplen, offset; + + if (likely(!len || BOUNDARY_OK(addr, len))) { + sdhci_adma_write_desc(host, desc, addr, len, end); + return; + } + + offset = addr & (SZ_128M - 1); + tmplen = SZ_128M - offset; + sdhci_adma_write_desc(host, desc, addr, tmplen, false); + + addr += tmplen; + len -= tmplen; + sdhci_adma_write_desc(host, desc, addr, len, end); +} + +static void snps_sdhci_set_phy(struct sdhci_host *host) +{ + struct snps_sdhci_plat *plat = dev_get_plat(host->mmc->dev); + u32 rxsel = PHY_PAD_RXSEL_3V3; + u32 val; + + if (plat->flags & FLAG_IO_FIXED_1V8 || + host->mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + rxsel = PHY_PAD_RXSEL_1V8; + + /* deassert phy reset & set tx drive strength */ + val = PHY_CNFG_RSTN_DEASSERT; + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, plat->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val = rxsel; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = rxsel; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + if (plat->flags & FLAG_IO_FIXED_1V8 || + host->mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL); + + sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R); + } + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); + + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | + PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); +} + +static int snps_sdhci_set_ios_post(struct sdhci_host *host) +{ + struct snps_sdhci_plat *plat = dev_get_plat(host->mmc->dev); + struct mmc *mmc = host->mmc; + u32 reg; + + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; + + switch (mmc->selected_mode) { + case UHS_SDR50: + case MMC_HS_52: + reg |= SDHCI_CTRL_UHS_SDR50; + break; + case UHS_DDR50: + case MMC_DDR_52: + reg |= SDHCI_CTRL_UHS_DDR50; + break; + case UHS_SDR104: + case MMC_HS_200: + reg |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_HS_400: + case MMC_HS_400_ES: + reg |= DWCMSHC_CTRL_HS400; + break; + default: + reg |= SDHCI_CTRL_UHS_SDR12; + } + + if ((plat->flags & FLAG_IO_FIXED_1V8) || + mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + reg |= SDHCI_CTRL_VDD_180; + else + reg &= ~SDHCI_CTRL_VDD_180; + + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); + + reg = sdhci_readw(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_CONTROL); + + if (IS_MMC(mmc)) + reg |= DWCMSHC_CARD_IS_EMMC; + else + reg &= ~DWCMSHC_CARD_IS_EMMC; + + if (mmc->selected_mode == MMC_HS_400_ES) + reg |= DWCMSHC_ENHANCED_STROBE; + else + reg &= ~DWCMSHC_ENHANCED_STROBE; + + sdhci_writeb(host, reg, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_CONTROL); + + if (mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == MMC_HS_400_ES) + plat->delay_line = PHY_SDCLKDL_DC_HS400; + else + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + + snps_sdhci_set_phy(host); + + return 0; +} + +static int snps_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) +{ + struct sdhci_host *host = dev_get_priv(mmc->dev); + char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + struct mmc_cmd cmd; + u32 ctrl, blk_size, val; + int ret; + + sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), + PHY_ATDL_CNFG_R); + val = sdhci_readl(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + + /* + * configure tuning settings: + * - center phase select code driven in block gap interval + * - disable reporting of framing errors + * - disable software managed tuning + * - disable user selection of sampling window edges, + * instead tuning calculated edges are used + */ + val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | + FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); + + /* + * configure tuning settings: + * - enable auto-tuning + * - enable sampling window threshold + * - stop clocks during phase code change + * - set max latency in cycles between tx and rx clocks + * - set max latency in cycles to switch output phase + * - set max sampling window threshold value + */ + val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; + val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); + + sdhci_writel(host, val, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + val = sdhci_readl(host, P_VENDOR_SPECIFIC_AREA + DWCMSHC_EMMC_ATCTRL); + + /* perform tuning */ + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl |= SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64); + if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8) + blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128); + sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE); + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); + + cmd.cmdidx = opcode; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + + do { + ret = mmc_send_cmd(mmc, &cmd, NULL); + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ret || tuning_loop_counter-- == 0) + break; + + } while (ctrl & SDHCI_CTRL_EXEC_TUNING); + + if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) { + if (!ret) + ret = -EIO; + printf("%s: Tuning failed: %d\n", __func__, ret); + + ctrl &= ~SDHCI_CTRL_TUNED_CLK; + ctrl &= ~SDHCI_CTRL_EXEC_TUNING; + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + + return ret; +} + +static int snps_sdhci_set_enhanced_strobe(struct sdhci_host *host) +{ + return 0; +} + +static const struct sdhci_ops snps_sdhci_ops = { + .set_ios_post = snps_sdhci_set_ios_post, + .platform_execute_tuning = snps_sdhci_execute_tuning, + .set_enhanced_strobe = snps_sdhci_set_enhanced_strobe, +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA_HELPERS) + .adma_write_desc = snps_sdhci_adma_write_desc, +#endif +}; + +static int snps_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct snps_sdhci_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + struct sdhci_host *host = dev_get_priv(dev); + struct clk clk; + int ret; + + plat->delay_line = PHY_SDCLKDL_DC_DEFAULT; + + ret = clk_get_by_name(dev, "core", &clk); + if (ret) + return ret; + + ret = clk_prepare_enable(&clk); + if (ret) + return ret; + + host->max_clk = clk_get_rate(&clk); + + host->ops = &snps_sdhci_ops; + + host->mmc = &plat->mmc; + host->mmc->priv = host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ); + if (ret) + return ret; + + if ((dev_read_bool(dev, "mmc-ddr-1_8v")) || + (dev_read_bool(dev, "mmc-hs200-1_8v")) || + (dev_read_bool(dev, "mmc-hs400-1_8v"))) + plat->flags |= FLAG_IO_FIXED_1V8; + else + plat->flags &= ~FLAG_IO_FIXED_1V8; + + return sdhci_probe(dev); +} + +static int snps_sdhci_of_to_plat(struct udevice *dev) +{ + struct snps_sdhci_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + host->name = dev->name; + host->ioaddr = dev_read_addr_ptr(dev); + + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret; + + return 0; +} + +static int snps_sdhci_bind(struct udevice *dev) +{ + struct snps_sdhci_plat *plat = dev_get_plat(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id snps_sdhci_ids[] = { + { .compatible = "thead,th1520-dwcmshc" } +}; + +U_BOOT_DRIVER(snps_sdhci_drv) = { + .name = "snps_sdhci", + .id = UCLASS_MMC, + .of_match = snps_sdhci_ids, + .of_to_plat = snps_sdhci_of_to_plat, + .ops = &sdhci_ops, + .bind = snps_sdhci_bind, + .probe = snps_sdhci_probe, + .priv_auto = sizeof(struct sdhci_host), + .plat_auto = sizeof(struct snps_sdhci_plat), +}; diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 569fbfd35c8..51aca7359ff 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -25,13 +25,19 @@ #include "pcie_plda_common.h" /* system control */ -#define STG_SYSCON_K_RP_NEP_MASK BIT(8) +#define STG_SYSCON_PCIE0_BASE 0x48 +#define STG_SYSCON_PCIE1_BASE 0x1f8 + +#define STG_SYSCON_AR_OFFSET 0x78 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 +#define STG_SYSCON_AW_OFFSET 0x7c #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) #define STG_SYSCON_CLKREQ_MASK BIT(22) #define STG_SYSCON_CKREF_SRC_SHIFT 18 #define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) +#define STG_SYSCON_RP_NEP_OFFSET 0xe8 +#define STG_SYSCON_K_RP_NEP_MASK BIT(8) DECLARE_GLOBAL_DATA_PTR; @@ -41,9 +47,7 @@ struct starfive_pcie { struct reset_ctl_bulk rsts; struct gpio_desc reset_gpio; struct regmap *regmap; - u32 stg_arfun; - u32 stg_awfun; - u32 stg_rp_nep; + unsigned int stg_pcie_base; }; static int starfive_pcie_atr_init(struct starfive_pcie *priv) @@ -92,7 +96,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) struct starfive_pcie *priv = dev_get_priv(dev); struct udevice *syscon; struct ofnode_phandle_args syscfg_phandle; - u32 cells[4]; int ret; /* get corresponding syscon phandle */ @@ -117,20 +120,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) return -ENODEV; } - /* get syscon register offset */ - ret = dev_read_u32_array(dev, "starfive,stg-syscon", - cells, ARRAY_SIZE(cells)); - if (ret) { - dev_err(dev, "Get syscon register err %d\n", ret); - return -EINVAL; - } - - dev_dbg(dev, "Get syscon values: %x, %x, %x\n", - cells[1], cells[2], cells[3]); - priv->stg_arfun = cells[1]; - priv->stg_awfun = cells[2]; - priv->stg_rp_nep = cells[3]; - return 0; } @@ -138,8 +127,9 @@ static int starfive_pcie_parse_dt(struct udevice *dev) { struct starfive_pcie *priv = dev_get_priv(dev); int ret; + u32 domain_nr; - priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg"); + priv->plda.reg_base = (void *)dev_read_addr_name(dev, "apb"); if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required reg address range\n"); return -EINVAL; @@ -147,7 +137,7 @@ static int starfive_pcie_parse_dt(struct udevice *dev) priv->plda.cfg_base = (void *)dev_read_addr_size_name(dev, - "config", + "cfg", &priv->plda.cfg_size); if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required config address range"); @@ -172,7 +162,18 @@ static int starfive_pcie_parse_dt(struct udevice *dev) return ret; } - ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + ret = dev_read_u32(dev, "linux,pci-domain", &domain_nr); + if (ret) { + dev_err(dev, "Can't get pci domain: %d\n", ret); + return ret; + } + + if (domain_nr == 0) + priv->stg_pcie_base = STG_SYSCON_PCIE0_BASE; + else + priv->stg_pcie_base = STG_SYSCON_PCIE1_BASE; + + ret = gpio_request_by_name(dev, "perst-gpios", 0, &priv->reset_gpio, GPIOD_IS_OUT); if (ret) { dev_err(dev, "Can't get reset-gpio: %d\n", ret); @@ -208,12 +209,12 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, (i << PLDA_PHY_FUNC_SHIFT) << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, i << PLDA_PHY_FUNC_SHIFT); @@ -222,11 +223,11 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions */ regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, 0); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, 0); @@ -273,17 +274,17 @@ static int starfive_pcie_probe(struct udevice *dev) return ret; regmap_update_bits(priv->regmap, - priv->stg_rp_nep, + priv->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, STG_SYSCON_K_RP_NEP_MASK, STG_SYSCON_K_RP_NEP_MASK); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CKREF_SRC_MASK, 2 << STG_SYSCON_CKREF_SRC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CLKREQ_MASK, STG_SYSCON_CLKREQ_MASK); diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h new file mode 100644 index 00000000000..97cf4d72df0 --- /dev/null +++ b/include/configs/bananapi-f3.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/licheerv_nano.h b/include/configs/licheerv_nano.h new file mode 100644 index 00000000000..2ea7943f66f --- /dev/null +++ b/include/configs/licheerv_nano.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Thomas Bonnefille <thomas.bonnefille@bootlin.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_bootcmd.h> + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#define CFG_EXTRA_ENV_SETTINGS "consoledev=ttyS0\0" \ + "baudrate=115200\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "scriptaddr=0x80c00000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff4..00000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da7..00000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ |