diff options
422 files changed, 14671 insertions, 10502 deletions
diff --git a/.gitignore b/.gitignore index 2e6fde8161b..d91e91b1e65 100644 --- a/.gitignore +++ b/.gitignore @@ -75,10 +75,5 @@ cscope.* /ctags /etags -# OneNAND IPL files -/onenand_ipl/onenand-ipl* -/onenand_ipl/board/*/onenand* -/onenand_ipl/board/*/*.S - # spl ais files /spl/*.ais diff --git a/MAINTAINERS b/MAINTAINERS index 4aabcffefff..aa54fe11ee5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -777,10 +777,6 @@ Nagendra T S <nagendra@mistralsolutions.com> am3517_crane ARM ARMV7 (AM35x SoC) -Kyungmin Park <kyungmin.park@samsung.com> - - apollon ARM1136EJS - Sandeep Paulraj <s-paulraj@ti.com> davinci_dm355evm ARM926EJS @@ -1112,6 +1108,7 @@ Wolfgang Wegner <w.wegner@astro-kom.de> Andreas Bießmann <andreas.devel@googlemail.com> grasshopper AT32AP7000 + atngw100mkii AT32AP7000 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> @@ -334,18 +334,27 @@ LIST_ppc=" \ LIST_SA="$(boards_by_cpu sa1100)" ######################################################################### +## ARM7 Systems +######################################################################### + +LIST_ARM7="$(boards_by_cpu arm720t)" + +######################################################################### ## ARM9 Systems ######################################################################### LIST_ARM9="$(boards_by_cpu arm920t) \ $(boards_by_cpu arm926ejs) \ $(boards_by_cpu arm925t) \ + $(boards_by_cpu arm946es) \ " ######################################################################### ## ARM11 Systems ######################################################################### -LIST_ARM11="$(boards_by_cpu arm1136)" +LIST_ARM11="$(boards_by_cpu arm1136) \ + $(boards_by_cpu arm1176) \ +" ######################################################################### ## ARMV7 Systems @@ -371,16 +380,7 @@ LIST_ixp="$(boards_by_cpu ixp)" ## ARM groups ######################################################################### -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM9} \ - ${LIST_ARM10} \ - ${LIST_ARM11} \ - ${LIST_ARMV7} \ - ${LIST_at91} \ - ${LIST_pxa} \ - ${LIST_ixp} \ -" +LIST_arm="$(boards_by_arch arm)" ######################################################################### ## MIPS Systems (default = big endian) @@ -388,6 +388,9 @@ LIST_arm=" \ LIST_mips4kc=" \ incaip \ + incaip_100MHz \ + incaip_133MHz \ + incaip_150MHz \ qemu_mips \ vct_platinum \ vct_platinum_small \ @@ -461,14 +464,7 @@ LIST_microblaze="$(boards_by_arch microblaze)" ## ColdFire Systems ######################################################################### -LIST_m68k="$(boards_by_arch m68k) - EB+MCF-EV123 \ - EB+MCF-EV123_internal \ - M52277EVB \ - M5235EVB \ - M54451EVB \ - M54455EVB \ -" +LIST_m68k="$(boards_by_arch m68k)" LIST_coldfire=${LIST_m68k} ######################################################################### @@ -22,9 +22,9 @@ # VERSION = 2012 -PATCHLEVEL = 07 +PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -242,9 +242,15 @@ LIBS-y += arch/arm/cpu/ixp/npe/libnpe.o endif LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o -LIBS-y += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \ - fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \ - fs/ubifs/libubifs.o fs/zfs/libzfs.o +LIBS-y += fs/cramfs/libcramfs.o \ + fs/ext4/libext4fs.o \ + fs/fat/libfat.o \ + fs/fdos/libfdos.o \ + fs/jffs2/libjffs2.o \ + fs/reiserfs/libreiserfs.o \ + fs/ubifs/libubifs.o \ + fs/yaffs2/libyaffs2.o \ + fs/zfs/libzfs.o LIBS-y += net/libnet.o LIBS-y += disk/libdisk.o LIBS-y += drivers/bios_emulator/libatibiosemu.o @@ -307,11 +313,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifeq ($(SOC),mx5) -LIBS-y += $(CPUDIR)/imx-common/libimx-common.o -endif -ifeq ($(SOC),mx6) -LIBS-y += $(CPUDIR)/imx-common/libimx-common.o +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) +LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif ifeq ($(SOC),s5pc1xx) @@ -378,7 +381,6 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin -ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin @@ -436,6 +438,11 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +$(obj)u-boot.pbl: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ + -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ + -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -550,12 +557,6 @@ nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin -onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all - -$(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin - cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin - $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all @@ -777,6 +778,7 @@ clean: $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ $(obj)tools/mk{smdk5250,}spl \ + $(obj)tools/mxsboot \ $(obj)tools/ncb $(obj)tools/ubsha1 @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ $(obj)board/matrix_vision/*/bootscript.img \ @@ -790,9 +792,7 @@ clean: @rm -f $(obj)include/generated/asm-offsets.h @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map} - @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} @rm -f $(ONENAND_BIN) - @rm -f $(obj)onenand_ipl/u-boot.lds @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map} @rm -f $(obj)MLO @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) @@ -813,6 +813,7 @@ clobber: tidy $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais @@ -825,7 +826,6 @@ clobber: tidy @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f - @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f @rm -f $(obj)dts/*.tmp @rm -f $(obj)spl/u-boot-spl{,-pad}.ais @@ -383,6 +383,31 @@ The following options need to be configured: symbol should be set to the TLB1 entry to be used for this purpose. + CONFIG_SYS_FSL_ERRATUM_A004510 + + Enables a workaround for erratum A004510. If set, + then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and + CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. + + CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional) + + Defines one or two SoC revisions (low 8 bits of SVR) + for which the A004510 workaround should be applied. + + The rest of SVR is either not relevant to the decision + of whether the erratum is present (e.g. p2040 versus + p2041) or is implied by the build target, which controls + whether CONFIG_SYS_FSL_ERRATUM_A004510 is set. + + See Freescale App Note 4493 for more information about + this erratum. + + CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY + + This is the value to write into CCSR offset 0x18600 + according to the A004510 workaround. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@ -3100,12 +3125,12 @@ to save the current settings. These two #defines specify the address and size of the environment area within the remote memory space. The local device can get the environment from remote memory - space by SRIO or other links. + space by SRIO or PCIE links. BE CAREFUL! For some special cases, the local device can not use "saveenv" command. For example, the local device will get the -environment stored in a remote NOR flash by SRIO link, but it can -not erase, write this NOR flash by SRIO interface. +environment stored in a remote NOR flash by SRIO or PCIE link, +but it can not erase, write this NOR flash by SRIO or PCIE interface. - CONFIG_ENV_IS_IN_NAND: @@ -3553,9 +3578,9 @@ within that device. - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which - can be mapped from slave TLB->slave LAW->slave SRIO outbound window - ->master inbound window->master LAW->the ucode address in master's - NOR flash. + can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound + window->master inbound window->master LAW->the ucode address in + master's memory space. Building the Software: ====================== diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8873fb719d9..93f429cc52e 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/io.h> @@ -30,16 +31,17 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); - u32 mfn = GET_PLL_MFN(reg); + s32 mfn = GET_PLL_MFN(reg); u32 mfd = GET_PLL_MFD(reg); u32 pd = GET_PLL_PD(reg); mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / - (mfd * pd)) << 10; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 mx31_get_mpl_dpdgck_clk(void) @@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void) u32 infreq; if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) - infreq = CONFIG_MX31_CLK32 * 1024; + infreq = MXC_CLK32 * 1024; else - infreq = CONFIG_MX31_HCLK_FREQ; + infreq = MXC_HCLK; return mx31_decode_pll(readl(CCM_MPCTL), infreq); } diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 72081a8bde2..36266da5aa8 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #include <div64.h> #include <watchdog.h> #include <asm/io.h> @@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX31_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX31_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX31_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \ - / CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -128,7 +128,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -159,7 +159,7 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return CONFIG_MX31_CLK32; + return MXC_CLK32; } void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d435e8af69a..ef65176eed2 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 get_mcu_main_clk(void) @@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void) struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); - fi *= - decode_pll(readl(&ccm->mpctl), - CONFIG_MX35_HCLK_FREQ); + fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); return fi / (arm_div * fd); } @@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -193,25 +191,20 @@ u32 imx_get_uartclk(void) (struct ccm_regs *)IMX_CCM_BASE; u32 pdr4 = readl(&ccm->pdr4); - if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) freq = get_mcu_main_clk(); - } else { - freq = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + else + freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK); + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; } unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; - if (reg4 & 0x200) { + usb_podf = (reg4 >> 22) & 0x3F; + if (reg4 & 0x200) pll = get_mcu_main_clk(); - } else { - pll = decode_pll(readl(&ccm->ppctl), - CONFIG_MX35_HCLK_FREQ); - } + else + pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK); - ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; pdf = mpdr2 & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case SSI2_BAUD: @@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (mpdr2 >> 8) & 0x3F; clk_sel = mpdr2 & (1 << 6); ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) pdf = (pre_pdf >> 22) & 0x3F; pre_pdf = (pre_pdf >> 28) & 0x7; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; pre_pdf = (mpdr3 >> 29) & 0x7; pdf = (mpdr3 >> 23) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : - decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / ((pre_pdf + 1) * (pdf + 1)); break; default: diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 04937a1dfeb..9680b7fde7b 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -27,6 +27,7 @@ #include <asm/io.h> #include <div64.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR; /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ #define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ -#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) - +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ_HZ); + do_div(tick, MXC_CLK32); return tick; } -static inline unsigned long long us_to_tick(unsigned long long usec) +static inline unsigned long long us_to_tick(unsigned long long us) { - usec *= TIMER_FREQ_HZ; - do_div(usec, 1000000); + us = us * MXC_CLK32 + 999999; + do_div(us, 1000000); - return usec; + return us; } +/* + * nothing really to do with interrupts, just starts up a counter. + * The 32KHz 32-bit timer overruns in 134217 seconds + */ int timer_init(void) { int i; struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR; /* setup GP Timer 1 */ writel(GPTCR_SWR, &gpt->ctrl); - for (i = 0; i < 100; i++) - writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(0, &gpt->pre); - /* Freerun Mode, PERCLK1 input */ - writel(readl(&gpt->ctrl) | - GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1); + + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + writel(0, &gpt->pre); /* prescaler = 1 */ + /* Freerun Mode, 32KHz input */ + writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + &gpt->ctrl); + writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl); return 0; } @@ -101,7 +111,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -132,5 +142,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return TIMER_FREQ_HZ; + return MXC_CLK32; } diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 4ea6d6b89ff..95da6a822a1 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := reset.o timer.o +COBJS := init.o reset.o timer.o SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/cpu/arm1176/bcm2835/init.c new file mode 100644 index 00000000000..e90d3bba1f9 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/init.c @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> + +int arch_cpu_init(void) +{ + icache_enable(); + + return 0; +} diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index 532a90b546f..c0fd114e163 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -65,10 +65,3 @@ static void cache_flush (void) /* mem barrier to sync things */ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); } - -int arch_cpu_init(void) -{ - icache_enable(); - - return 0; -} diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c index 6d4d66bced0..ddf8d979f44 100644 --- a/arch/arm/cpu/arm720t/tegra20/cpu.c +++ b/arch/arm/cpu/arm720t/tegra20/cpu.c @@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable) static int is_cpu_powered(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; } static void remove_cpu_io_clamps(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; /* Remove the clamps on the CPU I/O signals */ @@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void) static void powerup_cpu(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; int timeout = IO_STABILIZATION_DELAY; @@ -157,7 +157,7 @@ static void powerup_cpu(void) static void enable_cpu_power_rail(void) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_cntrl); diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a412a8fe204..90e584ac585 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) static ulong imx_get_mpllclk(void) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - ulong fref = 24000000; + ulong fref = MXC_HCLK; return imx_decode_pll(readl(&ccm->mpctl), fref); } diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 1cfd02b2306..4dc4041c08d 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -40,6 +40,7 @@ #include <div64.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR; static inline unsigned long long tick_to_time(unsigned long long tick) { tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX25_CLK32); + do_div(tick, MXC_CLK32); return tick; } static inline unsigned long long time_to_tick(unsigned long long time) { - time *= CONFIG_MX25_CLK32; + time *= MXC_CLK32; do_div(time, CONFIG_SYS_HZ); return time; } static inline unsigned long long us_to_tick(unsigned long long us) { - us = us * CONFIG_MX25_CLK32 + 999999; + us = us * MXC_CLK32 + 999999; do_div(us, 1000000); return us; } #else /* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX25_CLK32) +#define TICK_PER_TIME ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / MXC_CLK32) static inline unsigned long long tick_to_time(unsigned long long tick) { @@ -144,7 +144,7 @@ ulong get_timer_masked(void) { /* * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in * 5 * 10^6 days - long enough. */ @@ -177,6 +177,6 @@ ulong get_tbclk(void) { ulong tbclk; - tbclk = CONFIG_MX25_CLK32; + tbclk = MXC_CLK32; return tbclk; } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index ddafddbf2b4..ad66c57c5d3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -38,12 +38,14 @@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ -#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 void early_delay(int delay) { - uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + struct mxs_digctl_regs *digctl_regs = + (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + + uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); st += delay; - while (st > readl(HW_DIGCTRL_MICROSECONDS)) + while (st > readl(&digctl_regs->hw_digctl_microseconds)) ; } diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 792b11dfc51..c3948d38f08 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -292,7 +292,9 @@ int arch_misc_init(void) writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00); writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); + writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c); /* initialize timer */ timer_init_r(); diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index b387ac27ec8..ecc26717cda 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -37,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; static const struct gpio_bank gpio_bank_am33xx[4] = { @@ -119,22 +118,6 @@ static int read_eeprom(void) #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif -#ifdef CONFIG_SPL_BUILD -/* Initialize timer */ -static void init_timer(void) -{ - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); - - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); -} -#endif - /* * Determine what type of DDR we have. */ @@ -183,9 +166,6 @@ void s_init(void) regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); - /* Initialize the Timer */ - init_timer(); - preloader_console_init(); /* Initalize the board header */ diff --git a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c index 75cadb03ec7..925f8414c4d 100644 --- a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c +++ b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c @@ -46,7 +46,7 @@ static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; puts("Entering RCM...\n"); udelay(50000); diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 178bb130c28..cac0918ff31 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -137,24 +137,29 @@ static const u8 utmip_elastic_limit = 16; /* UTMIP High Speed Sync Start Delay */ static const u8 utmip_hs_sync_start_delay = 9; -/* Put the port into host mode (this only works for OTG ports) */ +/* Put the port into host mode */ static void set_host_mode(struct fdt_usb *config) { - if (config->dr_mode == DR_MODE_OTG) { - /* Check whether remote host from USB1 is driving VBus */ - if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) - return; - - /* - * If not driving, we set the GPIO to enable VBUS. We assume - * that the pinmux is set up correctly for this. - */ - if (fdt_gpio_isvalid(&config->vbus_gpio)) { - fdtdec_setup_gpio(&config->vbus_gpio); - gpio_direction_output(config->vbus_gpio.gpio, 1); - debug("set_host_mode: GPIO %d high\n", - config->vbus_gpio.gpio); - } + /* + * If we are an OTG port, check if remote host is driving VBus and + * bail out in this case. + */ + if (config->dr_mode == DR_MODE_OTG && + (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + 0 : 1); + debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio, + (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ? + "low" : "high"); } } diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 43c96c68643..9e91e5cb8ca 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -33,7 +33,7 @@ LIB = $(obj)lib$(SOC)-common.o SOBJS += lowlevel_init.o COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o -COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o +COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 00588dae527..c0ca6eb379e 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -32,7 +32,7 @@ int tegra_get_chip_type(void) { struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; uint tegra_sku_id, rev; /* @@ -40,7 +40,7 @@ int tegra_get_chip_type(void) * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30 */ - gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; tegra_sku_id = readl(&fuse->sku_info) & 0xff; @@ -101,7 +101,7 @@ static u32 get_odmdata(void) static void init_pmc_scratch(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 odmdata; int i; diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c index 598023aba9a..8a8d3384ac4 100644 --- a/arch/arm/cpu/tegra20-common/board.c +++ b/arch/arm/cpu/tegra20-common/board.c @@ -47,7 +47,7 @@ enum { unsigned int query_sdram_size(void) { - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; reg = readl(&pmc->pmc_scratch20); @@ -81,11 +81,11 @@ int checkboard(void) #endif /* CONFIG_DISPLAY_BOARDINFO */ static int uart_configs[] = { -#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB) +#if defined(CONFIG_TEGRA_UARTA_UAA_UAB) FUNCMUX_UART1_UAA_UAB, -#elif defined(CONFIG_TEGRA20_UARTA_GPU) +#elif defined(CONFIG_TEGRA_UARTA_GPU) FUNCMUX_UART1_GPU, -#elif defined(CONFIG_TEGRA20_UARTA_SDIO1) +#elif defined(CONFIG_TEGRA_UARTA_SDIO1) FUNCMUX_UART1_SDIO1, #else FUNCMUX_UART1_IRRX_IRTX, @@ -125,13 +125,13 @@ void board_init_uart_f(void) { int uart_ids = 0; /* bit mask of which UART ids to enable */ -#ifdef CONFIG_TEGRA20_ENABLE_UARTA +#ifdef CONFIG_TEGRA_ENABLE_UARTA uart_ids |= UARTA; #endif -#ifdef CONFIG_TEGRA20_ENABLE_UARTB +#ifdef CONFIG_TEGRA_ENABLE_UARTB uart_ids |= UARTB; #endif -#ifdef CONFIG_TEGRA20_ENABLE_UARTD +#ifdef CONFIG_TEGRA_ENABLE_UARTD uart_ids |= UARTD; #endif setup_uarts(uart_ids); diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index 8cfed645ce9..b2129adf2fe 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_NDFLASH: + if (config == FUNCMUX_NDFLASH_ATC) { + pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND); + pinmux_tristate_disable(PINGRP_ATC); + } + break; + default: debug("%s: invalid periph_id %d", __func__, id); return -1; diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 809ea0133eb..6ce995ef029 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0" +#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" #endif /* @@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void) u32 ram_code; struct sdram_params sdram; struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob); union scratch2_reg scratch2; union scratch4_reg scratch4; @@ -205,7 +205,7 @@ static u32 get_major_version(void) { u32 major_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT; @@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse) static int ap20_is_odm_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (!is_failure_analysis_mode(fuse) && is_odm_production_mode_fuse_set(fuse)) @@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void) static int ap20_is_production_mode(void) { - struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; if (get_major_version() == 0) return 1; @@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void) { u32 chip_id; struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE; + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index cd01908a462..80a5a15decf 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -38,7 +38,7 @@ void wb_start(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index f95be581350..d936b1e7e6a 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -204,4 +204,11 @@ compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x0078>; }; + + nand: nand-controller@70008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + }; }; diff --git a/arch/arm/cpu/armv7/imx-common/Makefile b/arch/arm/imx-common/Makefile index 16fba8da938..b3e608e9db0 100644 --- a/arch/arm/cpu/armv7/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o +ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) COBJS-y = iomux-v3.o timer.o cpu.o speed.o -COBJS-$(CONFIG_I2C_MXC) += i2c.o +COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o +endif COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o COBJS := $(sort $(COBJS-y)) diff --git a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c index 02fe72ed7fa..02fe72ed7fa 100644 --- a/arch/arm/cpu/armv7/imx-common/cmd_bmode.c +++ b/arch/arm/imx-common/cmd_bmode.c diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index fa1d4680416..fa1d4680416 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c b/arch/arm/imx-common/i2c-mxv7.c index da2b26f43f4..da2b26f43f4 100644 --- a/arch/arm/cpu/armv7/imx-common/i2c.c +++ b/arch/arm/imx-common/i2c-mxv7.c diff --git a/arch/arm/cpu/armv7/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index da093fbe148..da093fbe148 100644 --- a/arch/arm/cpu/armv7/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/imx-common/speed.c index 80989c49837..80989c49837 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/imx-common/speed.c diff --git a/arch/arm/cpu/armv7/imx-common/timer.c b/arch/arm/imx-common/timer.c index e2725e1a64b..e2725e1a64b 100644 --- a/arch/arm/cpu/armv7/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 0f701c90120..afdfcf049d1 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h index c79bed7ed9d..113f258756c 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-kirkwood/spi.h @@ -49,6 +49,7 @@ struct kwspi_registers { #define MISO_MPP11 (1 << 2) #define KWSPI_CLKPRESCL_MASK 0x1f +#define KWSPI_CLKPRESCL_MIN 0x12 #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h index 0f47eaf053c..a313b806119 100644 --- a/arch/arm/include/asm/arch-mx25/clock.h +++ b/arch/arm/include/asm/arch-mx25/clock.h @@ -26,6 +26,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX25_HCLK_FREQ +#define MXC_HCLK CONFIG_MX25_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX25_CLK32 +#define MXC_CLK32 CONFIG_MX25_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_CSI_CLK, MXC_EPIT_CLK, diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 852c19c1a74..9468b45feb0 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX31_HCLK_FREQ +#define MXC_HCLK CONFIG_MX31_HCLK_FREQ +#else +#define MXC_HCLK 26000000 +#endif + +#ifdef CONFIG_MX31_CLK32 +#define MXC_CLK32 CONFIG_MX31_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_IPG_CLK, diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h index e94f1244792..eb7458a338d 100644 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -24,6 +24,20 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#include <common.h> + +#ifdef CONFIG_MX35_HCLK_FREQ +#define MXC_HCLK CONFIG_MX35_HCLK_FREQ +#else +#define MXC_HCLK 24000000 +#endif + +#ifdef CONFIG_MX35_CLK32 +#define MXC_CLK32 CONFIG_MX35_CLK32 +#else +#define MXC_CLK32 32768 +#endif + enum mxc_clock { MXC_ARM_CLK, MXC_AHB_CLK, diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h index 7a2d1bbbf10..3fcde0ba525 100644 --- a/arch/arm/include/asm/arch-mx35/crm_regs.h +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -32,8 +32,8 @@ #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 21 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_UPE (1 << 9) @@ -47,7 +47,7 @@ #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) #define MXC_CCM_PDR0_AUTO_CON 0x1 @@ -62,10 +62,8 @@ #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 -#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR2_CSI_M_U (1 << 7) @@ -78,35 +76,23 @@ #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 -#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 15) -#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 -#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 -#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 -#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) -#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 -#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 -#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) #define MXC_CCM_PDR4_USB_M_U (1 << 9) /* Bit definitions for RCSR */ @@ -144,6 +130,12 @@ #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) /* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + #define MXC_CCM_CGR0_ASRC_OFFSET 0 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) #define MXC_CCM_CGR0_ATA_OFFSET 2 @@ -251,10 +243,8 @@ #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 #define MXC_CCM_COSR_CLKOEN (1 << 5) #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) -#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 -#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) -#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index a1255f9bd51..d23abd764a6 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -34,21 +34,21 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) @@ -63,55 +63,55 @@ #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h index 60324196414..d8d5647e806 100644 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h @@ -228,16 +228,6 @@ #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) #endif /* endif CONFIG_2420H4 */ -#if defined(CONFIG_APOLLON) -#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ -#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ -#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ -#define APOLLON_CS3_BASE 0x18000000 /* NOR */ - -#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) -#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) -#endif /* endif CONFIG_APOLLON */ - /* Common */ #define LOW_LEVEL_SRAM_STACK 0x4020FFFC diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index a830c43de20..54add4b4562 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -142,7 +142,6 @@ struct venc_regs { }; /* Few Register Offsets */ -#define FRAME_MODE_SHIFT 1 #define TFTSTN_SHIFT 3 #define DATALINES_SHIFT 8 @@ -182,6 +181,16 @@ struct panel_config { void *frame_buffer; }; +#define DSS_HBP(bp) (((bp) - 1) << 20) +#define DSS_HFP(fp) (((fp) - 1) << 8) +#define DSS_HSW(sw) ((sw) - 1) +#define DSS_VBP(bp) ((bp) << 20) +#define DSS_VFP(fp) ((fp) << 8) +#define DSS_VSW(sw) ((sw) - 1) + +#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) +#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) + /* Generic DSS Functions */ void omap3_dss_venc_config(const struct venc_regs *venc_cfg, u32 height, u32 width); diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 71f183de8d1..6e92b23da0f 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -451,6 +451,11 @@ #define CONTROL_PADCONF_GPIO128 0x0A58 #define CONTROL_PADCONF_GPIO129 0x0A5A +/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration + * of the extended drain cells */ +#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) +#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) + #define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index a8c4c60c8c9..3a0bfbf0c61 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -138,6 +138,7 @@ struct watchdog { #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) #define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) /* MUSB base */ #define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h index a91b4c2f31b..02ee2f88a1b 100644 --- a/arch/arm/include/asm/arch-omap4/i2c.h +++ b/arch/arm/include/asm/arch-omap4/i2c.h @@ -23,7 +23,7 @@ #ifndef _OMAP4_I2C_H_ #define _OMAP4_I2C_H_ -#define I2C_BUS_MAX 3 +#define I2C_BUS_MAX 4 #define I2C_DEFAULT_BASE I2C_BASE1 struct i2c { diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index 0f701c90120..afdfcf049d1 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h index c84d22f97bd..70d94c50417 100644 --- a/arch/arm/include/asm/arch-tegra20/ap20.h +++ b/arch/arm/include/asm/arch-tegra20/ap20.h @@ -95,9 +95,6 @@ #define HALT_COP_EVENT_IRQ_1 (1 << 11) #define HALT_COP_EVENT_FIQ_1 (1 << 9) -/* Start up the tegra20 SOC */ -void tegra20_start(void); - /* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index 258f7b641a6..bd511db8532 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -57,6 +57,9 @@ enum { /* Serial Flash configs */ FUNCMUX_SPI1_GMC_GMD = 0, + + /* NAND flags */ + FUNCMUX_NDFLASH_ATC = 0, }; /** diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h index 916a353a97d..5c95047998c 100644 --- a/arch/arm/include/asm/arch-tegra20/mmc.h +++ b/arch/arm/include/asm/arch-tegra20/mmc.h @@ -19,9 +19,9 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA20_MMC_H_ -#define _TEGRA20_MMC_H_ +#ifndef _TEGRA_MMC_H_ +#define _TEGRA_MMC_H_ -int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); +int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); -#endif /* TEGRA20_MMC_H_ */ +#endif /* _TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra20/sys_proto.h index 643d5424b84..919aec7f74c 100644 --- a/arch/arm/include/asm/arch-tegra20/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra20/sys_proto.h @@ -24,12 +24,12 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -struct tegra20_sysinfo { +struct tegra_sysinfo { char *board_string; }; void invalidate_dcache(void); -extern const struct tegra20_sysinfo sysinfo; +extern const struct tegra_sysinfo sysinfo; #endif diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h index 6750754bae1..c9485a1c844 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20.h @@ -33,21 +33,22 @@ #define NV_PA_GPIO_BASE 0x6000D000 #define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 -#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) +#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) +#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) +#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) +#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) +#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #define NV_PA_CSITE_BASE 0x70040000 #define TEGRA_USB1_BASE 0xC5000000 #define TEGRA_USB3_BASE 0xC5008000 #define TEGRA_USB_ADDR_MASK 0xFFFFC000 -#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE +#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) #define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) @@ -85,7 +86,7 @@ enum { }; #else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL TEGRA20_PMC_BASE +#define PRM_RSTCTRL NV_PA_PMC_BASE #endif #endif /* TEGRA20_H */ diff --git a/drivers/mmc/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h index b1f25641978..dd746cae0d0 100644 --- a/drivers/mmc/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h @@ -22,13 +22,13 @@ #ifndef __TEGRA_MMC_H_ #define __TEGRA_MMC_H_ -#define TEGRA20_SDMMC1_BASE 0xC8000000 -#define TEGRA20_SDMMC2_BASE 0xC8000200 -#define TEGRA20_SDMMC3_BASE 0xC8000400 -#define TEGRA20_SDMMC4_BASE 0xC8000600 +#define TEGRA_SDMMC1_BASE 0xC8000000 +#define TEGRA_SDMMC2_BASE 0xC8000200 +#define TEGRA_SDMMC3_BASE 0xC8000400 +#define TEGRA_SDMMC4_BASE 0xC8000600 #ifndef __ASSEMBLY__ -struct tegra20_mmc { +struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ @@ -118,7 +118,7 @@ struct tegra20_mmc { #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) struct mmc_host { - struct tegra20_mmc *reg; + struct tegra_mmc *reg; unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ unsigned int base; /* Base address, SDMMC1/2/3/4 */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra_spi.h index 8978beacc5d..d53a93ff53a 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h +++ b/arch/arm/include/asm/arch-tegra20/tegra_spi.h @@ -70,6 +70,6 @@ struct spi_tegra { #define SPI_STAT_CUR_BLKCNT (1 << 15) #define SPI_TIMEOUT 1000 -#define TEGRA20_SPI_MAX_FREQ 52000000 +#define TEGRA_SPI_MAX_FREQ 52000000 #endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h index 43f7ab4efa6..fdb99a73eeb 100644 --- a/arch/arm/include/asm/arch-tegra20/timer.h +++ b/arch/arm/include/asm/arch-tegra20/timer.h @@ -21,8 +21,8 @@ /* Tegra20 timer functions */ -#ifndef _TEGRA20_TIMER_H -#define _TEGRA20_TIMER_H +#ifndef _TEGRA_TIMER_H +#define _TEGRA_TIMER_H /* returns the current monotonic timer value in microseconds */ unsigned long timer_get_us(void); diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f1951e883e1..109a1ac7528 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -241,6 +241,9 @@ init_fnc_t *init_sequence[] = { fdtdec_check_fdt, #endif timer_init, /* initialize timer */ +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init, +#endif #ifdef CONFIG_FSL_ESDHC get_clocks, #endif diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c index 09ef1d2cfd4..3a0ab9746b4 100644 --- a/arch/m68k/cpu/mcf5227x/cpu.c +++ b/arch/m68k/cpu/mcf5227x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -30,14 +30,15 @@ #include <command.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -45,14 +46,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x6c: id = 52277; diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c index beb78f58393..e23b20df916 100644 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #include <asm/rtc.h> /* @@ -40,70 +41,70 @@ */ void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + pll_t *pll = (pll_t *)MMAP_PLL; #if !defined(CONFIG_CF_SBF) /* Workaround, must place before fbcs */ - pll->psr = 0x12; - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; - scm1->pacri = 0; + out_be32(&pll->psr, 0x12); + + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); + out_be32(&scm1->pacri, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #endif /* CONFIG_CF_SBF */ #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; + out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); #endif icache_enable(); @@ -115,11 +116,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *)&rtc->extended; - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); #endif return (0); @@ -127,27 +128,27 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); - gpio->par_uart |= - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + clrbits_be16(&gpio->par_uart, + ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: - gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); - gpio->par_uart |= - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + clrbits_be16(&gpio->par_uart, + ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); break; case 2: - gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); - gpio->par_dspi = - (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); + clrbits_8(&gpio->par_dspi, + ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); break; } } @@ -155,32 +156,32 @@ void uart_port_conf(int port) #ifdef CONFIG_CF_DSPI void cfspi_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_dspi = - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); } int cfspi_claim_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) return -1; /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; - gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); break; } @@ -189,17 +190,18 @@ int cfspi_claim_bus(uint bus, uint cs) void cfspi_release_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + /* Clear FIFO */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); break; } } diff --git a/arch/m68k/cpu/mcf5227x/interrupts.c b/arch/m68k/cpu/mcf5227x/interrupts.c index 85828a67b5f..a2cf51933ae 100644 --- a/arch/m68k/cpu/mcf5227x/interrupts.c +++ b/arch/m68k/cpu/mcf5227x/interrupts.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,14 +28,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -44,9 +45,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c index 7e385d39980..b94a9eda482 100644 --- a/arch/m68k/cpu/mcf5227x/speed.c +++ b/arch/m68k/cpu/mcf5227x/speed.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; void clock_enter_limp(int lpdiv) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + ccm_t *ccm = (ccm_t *)MMAP_CCM; int i, j; /* Check bounds of divider */ @@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv) for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; /* Apply the divider to the system clock */ - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); /* Enable Limp Mode */ - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); } /* @@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv) */ void clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; /* Exit Limp mode */ - ccm->misccr &= ~CCM_MISCCR_LIMP; + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for the PLL to lock */ - while (!(pll->psr & PLL_PSR_LOCK)) ; + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) + ; } /* @@ -85,12 +87,12 @@ void clock_exit_limp(void) int get_clocks(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; int vco, temp, pcrvalue, pfdr; u8 bootmode; - pcrvalue = pll->pcr & 0xFF0F0FFF; + pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; pfdr = pcrvalue >> 24; if (pfdr == 0x1E) @@ -102,32 +104,32 @@ int get_clocks(void) if (bootmode == 0) { /* Normal mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* Default value */ - pcrvalue = (pll->pcr & 0x00FFFFFF); + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); pcrvalue |= 0x1E << 24; - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); vco = - ((pll->pcr & 0xFF000000) >> 24) * + ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 3) { /* serial mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; /* Vco clock */ } - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; gd->flb_clk = vco / temp; /* flexbus clock */ gd->bus_clk = gd->flb_clk; } diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index 2376f970da7..a3f568403cd 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,28 +31,29 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; - ccm->rcr = CCM_RCR_SOFTRST; + out_8(&ccm->rcr, CCM_RCR_SOFTRST); /* we don't return! */ return 0; -}; +} int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x31: id = 5235; @@ -76,19 +77,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->sr = 0x5555; /* Count register */ + /* Count register */ + out_be16(&wdp->sr, 0x5555); asm("nop"); - wdp->sr = 0xAAAA; /* Count register */ + out_be16(&wdp->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + /* halted watchdog timer */ + setbits_be16(&wdp->cr, WTM_WCR_HALTED); puts("WATCHDOG:disabled\n"); return (0); @@ -96,15 +99,15 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); u32 wdog_module = 0; /* set timeout and enable watchdog */ wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); - wdp->mr = wdog_module; + out_be16(&wdp->mr, wdog_module); - wdp->cr = WTM_WCR_EN; + out_be16(&wdp->cr, WTM_WCR_EN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 0f299f0c3c5..d1c0b401c1e 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,74 +45,74 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; - volatile scm_t *scm = (scm_t *) MMAP_SCM; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + wdog_t *wdog = (wdog_t *) MMAP_WDOG; + scm_t *scm = (scm_t *) MMAP_SCM; /* watchdog is enabled by default - disable the watchdog */ #ifndef CONFIG_WATCHDOG - wdog->cr = 0; + out_be16(&wdog->cr, 0); #endif - scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ - gpio->par_cs = 0; + out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS6; - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); + out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS7; - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); + out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif #ifdef CONFIG_FSL_I2C @@ -132,29 +133,33 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); - gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); break; case 1: - gpio->par_uart &= - ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); - gpio->par_uart |= - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); - gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); - gpio->feci2c |= - (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); #endif break; } @@ -163,15 +168,16 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | - GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_FECEMDC | + GPIO_PAR_FECI2C_EMDIO_FECEMDIO); } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_MASK | + GPIO_PAR_FECI2C_EMDIO_MASK); } return 0; diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index db5ccdf6d3e..76115a40131 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,13 +25,14 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrl0 |= 0x1; + setbits_be32(&intp->imrl0, 0x1); enable_interrupts(); return 0; @@ -40,10 +41,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrl0 &= ~INTC_IPRL_INT0; - intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrl0, INTC_IPRL_INT0); + clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index 6096ba41444..e2a6ae3a58f 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; /* @@ -36,11 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks(void) { - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + pll_t *pll = (pll_t *)(MMAP_PLL); - pll->syncr = PLL_SYNCR_MFD(1); + out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); - while (!(pll->synsr & PLL_SYNSR_LOCK)); + while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) + ; gd->bus_clk = CONFIG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 571d078f896..7c6100c5287 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -9,6 +9,8 @@ * MCF5275 additions * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,6 +34,7 @@ #include <watchdog.h> #include <command.h> #include <asm/immap.h> +#include <asm/io.h> #include <netdev.h> #include "cpu.h" @@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_M5208 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); - rcm->rcr = RCM_RCR_SOFTRST; + out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -65,18 +68,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->sr = 0x5555; - wdt->sr = 0xAAAA; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->sr = 0x5555; /* reset watchdog counter */ - wdt->sr = 0xAAAA; - wdt->cr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); + /* disable watchdog timer */ + out_be16(&wdt->cr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -84,15 +90,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->cr = 0; /* disable watchdog */ + /* disable watchdog */ + out_be16(&wdt->cr, 0); /* set timeout and enable watchdog */ - wdt->mr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->sr = 0x5555; /* reset watchdog counter */ - wdt->sr = 0xAAAA; + out_be16(&wdt->mr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); puts("WATCHDOG:enabled\n"); return (0); @@ -178,13 +187,13 @@ int watchdog_init(void) #ifdef CONFIG_M5272 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->wdog_wrrr = 0; + out_be16(&wdp->wdog_wrrr, 0); udelay(1000); /* enable watchdog, set timeout to 0 and wait */ - wdp->wdog_wrrr = 1; + out_be16(&wdp->wdog_wrrr, 1); while (1) ; /* we don't return! */ @@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); + sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; char *suf; puts("CPU: "); - msk = (sysctrl->sc_dir > 28) & 0xf; + msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; switch (msk) { case 0x2: suf = "1K75N"; @@ -221,17 +230,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wdog_wcr = 0; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->wdog_wcr, 0); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wdog_wcr = 0; /* reset watchdog counter */ - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ - wdt->wdog_wrrr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->wdog_wcr, 0); + /* disable watchdog interrupt */ + out_be16(&wdt->wdog_wirr, 0); + /* disable watchdog timer */ + out_be16(&wdt->wdog_wrrr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -239,14 +252,17 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + /* disable watchdog interrupt */ + out_be16(&wdt->wdog_wirr, 0); /* set timeout and enable watchdog */ - wdt->wdog_wrrr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->wdog_wcr = 0; /* reset watchdog counter */ + out_be16(&wdt->wdog_wrrr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->wdog_wcr, 0); puts("WATCHDOG:enabled\n"); return (0); @@ -258,11 +274,11 @@ int watchdog_init(void) #ifdef CONFIG_M5275 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); - rcm->rcr = RCM_RCR_SOFTRST; + out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -282,18 +298,22 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wsr = 0x5555; - wdt->wsr = 0xAAAA; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; - wdt->wcr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); + + /* disable watchdog timer */ + out_be16(&wdt->wcr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -301,15 +321,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wcr = 0; /* disable watchdog */ + /* disable watchdog */ + out_be16(&wdt->wcr, 0); /* set timeout and enable watchdog */ - wdt->wmr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; + out_be16(&wdt->wmr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index a98a9262ebf..5d0e9f06f37 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -8,7 +8,7 @@ * (c) Copyright 2010 * Arcturus Networks Inc. <www.arcturusnetworks.com> * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * Hayden Fraser (Hayden.Fraser@freescale.com) * @@ -37,6 +37,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -48,57 +49,57 @@ /* Only 5272 Flexbus chipselect is different from the rest */ void init_fbcs(void) { - volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); + fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ && defined(CONFIG_SYS_CS6_CTRL)) - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; + out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ && defined(CONFIG_SYS_CS7_CTRL)) - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; + out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif } #endif @@ -106,22 +107,22 @@ void init_fbcs(void) #if defined(CONFIG_M5208) void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; #ifndef CONFIG_WATCHDOG - volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG; + wdog_t *wdg = (wdog_t *) MMAP_WDOG; /* Disable the watchdog if we aren't using it */ - wdg->cr = 0; + out_be16(&wdg->cr, 0); #endif - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); /* FlexBus Chipselect */ init_fbcs(); @@ -137,36 +138,36 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= GPIO_PAR_UART0_UNMASK; - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); + setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: - gpio->par_uart &= GPIO_PAR_UART0_UNMASK; - gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); + clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); + setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_timer &= - (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK); - gpio->par_timer |= - (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); + clrbits_8(&gpio->par_feci2c, + ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); + clrbits_8(&gpio->par_feci2c, + ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif break; } @@ -175,17 +176,17 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_fec |= - GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); } else { - gpio->par_fec &= - (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK; + clrbits_8(&gpio->par_fec, + ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); } return 0; } @@ -249,17 +250,17 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile u32 *par = (u32 *) MMAP_PAR; + u32 *par = (u32 *) MMAP_PAR; /* Setup Ports: */ switch (port) { case 1: - *par &= 0xFFE7FFFF; - *par |= 0x00180000; + clrbits_be32(par, 0x00180000); + setbits_be32(par, 0x00180000); break; case 2: - *par &= 0xFFFFFFFC; - *par &= 0x00000003; + clrbits_be32(par, 0x00000003); + clrbits_be32(par, 0xFFFFFFFC); break; } } @@ -332,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif /* CONFIG_CMD_NET */ -#endif + +#if defined(CONFIG_CF_QSPI) + +/* Configure PIOs for SIN, SOUT, and SCK */ +void cfspi_port_conf(void) +{ + mbar_writeByte(MCF_GPIO_PAR_QSPI, + MCF_GPIO_PAR_QSPI_SIN_SIN | + MCF_GPIO_PAR_QSPI_SOUT_SOUT | + MCF_GPIO_PAR_QSPI_SCK_SCK); +} +#endif /* CONFIG_CF_QSPI */ + +#endif /* CONFIG_M5271 */ #if defined(CONFIG_M5272) /* @@ -348,59 +362,59 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); - volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); - volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); + sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + gpio_t *gpio = (gpio_t *) (MMAP_GPIO); + csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - sysctrl->sc_scr = CONFIG_SYS_SCR; - sysctrl->sc_spr = CONFIG_SYS_SPR; + out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); /* Setup Ports: */ - gpio->gpio_pacnt = CONFIG_SYS_PACNT; - gpio->gpio_paddr = CONFIG_SYS_PADDR; - gpio->gpio_padat = CONFIG_SYS_PADAT; - gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; - gpio->gpio_pbddr = CONFIG_SYS_PBDDR; - gpio->gpio_pbdat = CONFIG_SYS_PBDAT; - gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; + out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); /* Memory Controller: */ - csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; - csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; + out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); + out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; - csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; + out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); + out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); #endif #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; - csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; + out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); + out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); #endif #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; - csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; + out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); + out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); #endif #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) - csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; - csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; + out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); + out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); #endif #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) - csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; - csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; + out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); + out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); #endif #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) - csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; - csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; + out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); + out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); #endif #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) - csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; - csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; + out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); + out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); #endif #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ @@ -420,17 +434,21 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); - gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); + clrbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); + setbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); break; case 1: - gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); - gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); + clrbits_be32(&gpio->gpio_pdcnt, + GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); + setbits_be32(&gpio->gpio_pdcnt, + GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); break; } } @@ -438,13 +456,14 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | - GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | - GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | - GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + setbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | + GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | + GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | + GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); } else { } return 0; @@ -469,11 +488,11 @@ void cpu_init_f(void) */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); - volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); + wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); + gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); /* Kill watchdog so we can initialize the PLL */ - wdog_reg->wcr = 0; + out_be16(&wdog_reg->wcr, 0); /* FlexBus Chipselect */ init_fbcs(); @@ -498,21 +517,21 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~UART0_ENABLE_MASK; - gpio->par_uart |= UART0_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); break; case 1: - gpio->par_uart &= ~UART1_ENABLE_MASK; - gpio->par_uart |= UART1_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); break; case 2: - gpio->par_uart &= ~UART2_ENABLE_MASK; - gpio->par_uart |= UART2_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); break; } } @@ -521,24 +540,24 @@ void uart_port_conf(int port) int fecpin_setclear(struct eth_device *dev, int setclear) { struct fec_info_s *info = (struct fec_info_s *) dev->priv; - volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; + gpio_t *gpio = (gpio_t *)MMAP_GPIO; if (setclear) { /* Enable Ethernet pins */ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c |= 0x0F00; - gpio->par_fec0hl |= 0xC0; + setbits_be16(&gpio->par_feci2c, 0x0f00); + setbits_8(&gpio->par_fec0hl, 0xc0); } else { - gpio->par_feci2c |= 0x00A0; - gpio->par_fec1hl |= 0xC0; + setbits_be16(&gpio->par_feci2c, 0x00a0); + setbits_8(&gpio->par_fec1hl, 0xc0); } } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c &= ~0x0F00; - gpio->par_fec0hl &= ~0xC0; + clrbits_be16(&gpio->par_feci2c, 0x0f00); + clrbits_8(&gpio->par_fec0hl, 0xc0); } else { - gpio->par_feci2c &= ~0x00A0; - gpio->par_fec1hl &= ~0xC0; + clrbits_be16(&gpio->par_feci2c, 0x00a0); + clrbits_8(&gpio->par_fec1hl, 0xc0); } } diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index dff8c6aa882..915eb702334 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,20 +28,22 @@ #include <watchdog.h> #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> #ifdef CONFIG_M5272 int interrupt_init(void) { - volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); + intctrl_t *intp = (intctrl_t *) (MMAP_INTC); /* disable all external interrupts */ - intp->int_icr1 = 0x88888888; - intp->int_icr2 = 0x88888888; - intp->int_icr3 = 0x88888888; - intp->int_icr4 = 0x88888888; - intp->int_pitr = 0x00000000; + out_be32(&intp->int_icr1, 0x88888888); + out_be32(&intp->int_icr2, 0x88888888); + out_be32(&intp->int_icr3, 0x88888888); + out_be32(&intp->int_icr4, 0x88888888); + out_be32(&intp->int_pitr, 0x00000000); + /* initialize vector register */ - intp->int_pivr = 0x40; + out_8(&intp->int_pivr, 0x40); enable_interrupts(); @@ -51,10 +53,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); + intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); - intp->int_icr1 &= ~INT_ICR1_TMR3MASK; - intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI; + clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); + setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ @@ -63,14 +65,14 @@ void dtimer_intr_setup(void) defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ #if defined(CONFIG_M5208) - intp->imrl0 = 0xFFFFFFFF; - intp->imrh0 = 0xFFFFFFFF; + out_be32(&intp->imrl0, 0xffffffff); + out_be32(&intp->imrh0, 0xffffffff); #else - intp->imrl0 |= 0x1; + setbits_be32(&intp->imrl0, 0x1); #endif enable_interrupts(); @@ -80,11 +82,11 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrl0 &= 0xFFFFFFFE; - intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrl0, 0x00000001); + clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index b485e1cccc1..70abed25c41 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks (void) { #if defined(CONFIG_M5208) - volatile pll_t *pll = (pll_t *) MMAP_PLL; + pll_t *pll = (pll_t *) MMAP_PLL; - pll->odr = CONFIG_SYS_PLL_ODR; - pll->fdr = CONFIG_SYS_PLL_FDR; + out_8(&pll->odr, CONFIG_SYS_PLL_ODR); + out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); #endif #if defined(CONFIG_M5249) || defined(CONFIG_M5253) @@ -70,14 +71,14 @@ int get_clocks (void) #endif /* CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5275) - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + pll_t *pll = (pll_t *)(MMAP_PLL); /* Setup PLL */ - pll->syncr = 0x01080000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) + out_be32(&pll->syncr, 0x01080000); + while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) ; - pll->syncr = 0x01000000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) + out_be32(&pll->syncr, 0x01000000); + while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) ; #endif diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 3346784c881..4f160a664e8 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,15 +31,16 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { #ifdef CONFIG_MCF5301x case 0x78: @@ -115,18 +116,20 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->sr = 0x5555; /* Count register */ - wdp->sr = 0xAAAA; /* Count register */ + /* Count register */ + out_be16(&wdp->sr, 0x5555); + out_be16(&wdp->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + /* halted watchdog timer */ + setbits_be16(&wdp->cr, WTM_WCR_HALTED); puts("WATCHDOG:disabled\n"); return (0); @@ -134,18 +137,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); u32 wdog_module = 0; /* set timeout and enable watchdog */ wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 - wdp->mr = (wdog_module / 8192); + out_be16(&wdp->mr, wdog_module / 8192); #else - wdp->mr = (wdog_module / 4096); + out_be16(&wdp->mr, wdog_module / 4096); #endif - wdp->cr = WTM_WCR_EN; + out_be16(&wdp->cr, WTM_WCR_EN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 6f551b60c92..f571fadc35a 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -38,72 +39,68 @@ #ifdef CONFIG_MCF5301x void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - - /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG - /*wdog->cr = 0; */ -#endif - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - gpio->par_cs |= GPIO_PAR_CS0_CS0; - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS1_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; + out_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); #endif icache_enable(); @@ -113,21 +110,21 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFFEC - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; #endif #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; + rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *) &rtc->extended; - rtcex->gocu = CONFIG_SYS_RTC_CNT; - rtcex->gocl = CONFIG_SYS_RTC_SETUP; + out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); #endif #ifdef CONFIG_MCFFEC if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) - ccm->misccr |= CCM_MISCCR_FECM; + setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); else - ccm->misccr &= ~CCM_MISCCR_FECM; + clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); #endif return (0); @@ -135,41 +132,52 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_ALT1_GPIO - gpio->par_simp1h &= - ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | - GPIO_PAR_SIMP1H_VEN1_UNMASK); - gpio->par_simp1h |= - (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); + clrbits_8(&gpio->par_simp1h, + GPIO_PAR_SIMP1H_DATA1_UNMASK | + GPIO_PAR_SIMP1H_VEN1_UNMASK); + setbits_8(&gpio->par_simp1h, + GPIO_PAR_SIMP1H_DATA1_U1TXD | + GPIO_PAR_SIMP1H_VEN1_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) - gpio->par_ssih &= - ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); - gpio->par_ssih |= - (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); + clrbits_8(&gpio->par_ssih, + GPIO_PAR_SSIH_RXD_UNMASK | + GPIO_PAR_SSIH_TXD_UNMASK); + setbits_8(&gpio->par_ssih, + GPIO_PAR_SSIH_RXD_U1RXD | + GPIO_PAR_SSIH_TXD_U1TXD); #endif break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U2TXD | + GPIO_PAR_UART_U2RXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->par_dspih &= - ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); - gpio->par_dspih |= - (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); + clrbits_8(&gpio->par_dspih, + GPIO_PAR_DSPIH_SIN_UNMASK | + GPIO_PAR_DSPIH_SOUT_UNMASK); + setbits_8(&gpio->par_dspih, + GPIO_PAR_DSPIH_SIN_U2RXD | + GPIO_PAR_DSPIH_SOUT_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_UNMASK | + GPIO_PAR_FECI2C_SCL_UNMASK); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_U2TXD | + GPIO_PAR_FECI2C_SCL_U2RXD); #endif break; } @@ -178,30 +186,30 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_s *info = (struct fec_info_s *)dev->priv; if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec |= - GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); } else { - gpio->par_fec |= - GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); } } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec &= - ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); } else { - gpio->par_fec &= - ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); } } return 0; @@ -212,80 +220,81 @@ int fecpin_setclear(struct eth_device *dev, int setclear) #ifdef CONFIG_MCF532x void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + wdog_t *wdog = (wdog_t *) MMAP_WDOG; /* watchdog is enabled by default - disable the watchdog */ #ifndef CONFIG_WATCHDOG - wdog->cr = 0; + out_be16(&wdog->cr, 0); #endif - scm1->mpr0 = 0x77777777; - scm2->pacra = 0; - scm2->pacrb = 0; - scm2->pacrc = 0; - scm2->pacrd = 0; - scm2->pacre = 0; - scm2->pacrf = 0; - scm2->pacrg = 0; - scm1->pacrh = 0; + out_be32(&scm1->mpr0, 0x77777777); + out_be32(&scm2->pacra, 0); + out_be32(&scm2->pacrb, 0); + out_be32(&scm2->pacrc, 0); + out_be32(&scm2->pacrd, 0); + out_be32(&scm2->pacre, 0); + out_be32(&scm2->pacrf, 0); + out_be32(&scm2->pacrg, 0); + out_be32(&scm1->pacrh, 0); /* Port configuration */ - gpio->par_cs = 0; + out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - gpio->par_cs |= GPIO_PAR_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS2); + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS3); + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; + out_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); #endif icache_enable(); @@ -301,30 +310,35 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); - gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); break; case 1: - gpio->par_uart &= - ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); - gpio->par_uart |= - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); break; case 2: #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_timer &= 0x0F; - gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + clrbits_8(&gpio->par_timer, 0xf0); + setbits_8(&gpio->par_timer, + GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_feci2c &= 0xFF00; - gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); + clrbits_8(&gpio->par_feci2c, 0x00ff); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) - gpio->par_ssi &= 0xF0FF; - gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); + clrbits_be16(&gpio->par_ssi, 0x0f00); + setbits_be16(&gpio->par_ssi, + GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); #endif break; } @@ -333,16 +347,18 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); } return 0; } diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index d6c82054549..d1ea2ff5a79 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -41,9 +42,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index 5a29e2567a8..cfdcc8b8077 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -65,13 +66,13 @@ DECLARE_GLOBAL_DATA_PTR; /* Get the value of the current system clock */ int get_sys_clock(void) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); + pll_t *pll = (pll_t *)(MMAP_PLL); int divider; /* Test to see if device is in LIMP mode */ - if (ccm->misccr & CCM_MISCCR_LIMP) { - divider = ccm->cdr & CCM_CDR_LPDIV(0xF); + if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { + divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); #ifdef CONFIG_MCF5301x return (FREF / (3 * (1 << divider))); #endif @@ -80,14 +81,14 @@ int get_sys_clock(void) #endif } else { #ifdef CONFIG_MCF5301x - u32 pfdr = (pll->pcr & 0x3F) + 1; - u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); - u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; + u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; + u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); + u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; return (((FREF * pfdr) / refdiv) / busdiv); #endif #ifdef CONFIG_MCF532x - return ((FREF * pll->pfdr) / (BUSDIV * 4)); + return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); #endif } } @@ -103,7 +104,7 @@ int get_sys_clock(void) */ int clock_limp(int div) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); u32 temp; /* Check bounds of divider */ @@ -113,12 +114,12 @@ int clock_limp(int div) div = MAX_LPD; /* Save of the current value of the SSIDIV so we don't overwrite the value */ - temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); + temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); /* Apply the divider to the system clock */ - ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); return (FREF / (3 * (1 << div))); } @@ -126,14 +127,15 @@ int clock_limp(int div) /* Exit low power LIMP mode */ int clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); int fout; /* Exit LIMP mode */ - ccm->misccr &= (~CCM_MISCCR_LIMP); + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for PLL to lock */ - while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) + ; fout = get_sys_clock(); @@ -153,10 +155,10 @@ int clock_exit_limp(void) int clock_pll(int fsys, int flags) { #ifdef CONFIG_MCF532x - volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); + u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80); #endif - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + pll_t *pll = (pll_t *)(MMAP_PLL); int fref, temp, fout, mfd; u32 i; @@ -165,13 +167,13 @@ int clock_pll(int fsys, int flags) if (fsys == 0) { /* Return current PLL output */ #ifdef CONFIG_MCF5301x - u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; - mfd = (pll->pcr & 0x3F) + 1; + u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; + mfd = (in_be32(&pll->pcr) & 0x3F) + 1; return (fref * mfd) / busdiv; #endif #ifdef CONFIG_MCF532x - mfd = pll->pfdr; + mfd = in_8(&pll->pfdr); return (fref * mfd / (BUSDIV * 4)); #endif @@ -211,8 +213,8 @@ int clock_pll(int fsys, int flags) * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL. */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl &= ~SDRAMC_SDCR_CKE; + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) + clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); /* * Initialize the PLL to generate the new system clock frequency. @@ -223,35 +225,36 @@ int clock_pll(int fsys, int flags) clock_limp(DEFAULT_LPD); #ifdef CONFIG_MCF5301x - pll->pdr = - PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | - PLL_PDR_OUTDIV2(BUSDIV - 1) | - PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | - PLL_PDR_OUTDIV4(USBDIV - 1); - - pll->pcr &= PLL_PCR_FBDIV_UNMASK; - pll->pcr |= PLL_PCR_FBDIV(mfd - 1); + out_be32(&pll->pdr, + PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | + PLL_PDR_OUTDIV2(BUSDIV - 1) | + PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | + PLL_PDR_OUTDIV4(USBDIV - 1)); + + clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK); + setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1)); #endif #ifdef CONFIG_MCF532x /* Reprogram PLL for desired fsys */ - pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + out_8(&pll->podr, + PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); - pll->pfdr = mfd; + out_8(&pll->pfdr, mfd); #endif /* Exit LIMP mode */ clock_exit_limp(); /* Return the SDRAM to normal operation if it is in use. */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl |= SDRAMC_SDCR_CKE; + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) + setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); #ifdef CONFIG_MCF532x /* * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - *sdram_workaround = CONFIG_SYS_SDRAM_BASE; + out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index 323a54eab47..adfc708c359 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,14 +31,15 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x48: id = 54455; diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index fdcd18585d9..3f9209ff196 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -30,6 +30,7 @@ #include <asm/immap.h> #include <asm/processor.h> #include <asm/rtc.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -46,64 +47,64 @@ */ void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); /* FlexBus */ - gpio->par_be = - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | - GPIO_PAR_BE_BE0_BE0; - gpio->par_fbctl = - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | - GPIO_PAR_FBCTL_TS_TS; + out_8(&gpio->par_be, + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | + GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); + out_8(&gpio->par_fbctl, + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | + GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); #if !defined(CONFIG_CF_SBF) #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif /* @@ -115,7 +116,8 @@ void cpu_init_f(void) setvbr(CONFIG_SYS_CS0_BASE); #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; + out_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); #endif icache_enable(); @@ -127,11 +129,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *)&rtc->extended; - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); #endif return (0); @@ -139,40 +141,40 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= - ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - gpio->par_uart |= - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_PRI_GPIO - gpio->par_uart &= - ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - gpio->par_uart |= - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) - gpio->par_ssi &= - (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); - gpio->par_ssi |= - (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); + clrbits_be16(&gpio->par_ssi, + ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); + setbits_be16(&gpio->par_ssi, + GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); #endif break; case 2: #if defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->par_timer &= - (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); - gpio->par_timer |= - (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_timer &= - (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); - gpio->par_timer |= - (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); #endif break; } @@ -181,43 +183,43 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_s *info = (struct fec_info_s *)dev->priv; if (setclear) { #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | - GPIO_PAR_FECI2C_MDIO0_MDIO0); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | + GPIO_PAR_FECI2C_MDIO0_MDIO0); else - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC1_MDC1 | - GPIO_PAR_FECI2C_MDIO1_MDIO1); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC1_MDC1 | + GPIO_PAR_FECI2C_MDIO1_MDIO1); #else - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); #endif if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); else - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + clrbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { #ifdef CONFIG_SYS_FEC_FULL_MII - gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); #else - gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); #endif } else { #ifdef CONFIG_SYS_FEC_FULL_MII - gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); #else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); #endif } } @@ -228,43 +230,45 @@ int fecpin_setclear(struct eth_device *dev, int setclear) #ifdef CONFIG_CF_DSPI void cfspi_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | + GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); } int cfspi_claim_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) return -1; /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); break; case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); break; case 3: - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; - gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3; + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); break; case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } @@ -273,26 +277,27 @@ int cfspi_claim_bus(uint bus, uint cs) void cfspi_release_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + /* Clear FIFO */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); break; case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); break; case 3: - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); break; case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } } diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index 85828a67b5f..a2cf51933ae 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,14 +28,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -44,9 +45,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c index 7f9784c3cbd..c32fcee7f99 100644 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ b/arch/m68k/cpu/mcf5445x/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -60,78 +60,82 @@ PCI_OP(write, dword, u32, out_le32, 0) void pci_mcf5445x_init(struct pci_controller *hose) { - volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; - volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pci_t *pci = (pci_t *)MMAP_PCI; + pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; u32 barEn = 0; - pciarb->acr = 0x001F001F; + out_be32(&pciarb->acr, 0x001f001f); /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, PCIREQ2, PCIGNT2 */ - gpio->par_pci = - GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | - GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | - GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + out_be16(&gpio->par_pci, + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | + GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 | + GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0); /* Assert reset bit */ - pci->gscr |= PCI_GSCR_PR; + setbits_be32(&pci->gscr, PCI_GSCR_PR); - pci->tcr1 |= PCI_TCR1_P; + setbits_be32(&pci->tcr1, PCI_TCR1_P); /* Initiator windows */ - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); + out_be32(&pci->iw0btar, + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); + out_be32(&pci->iw1btar, + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); + out_be32(&pci->iw2btar, + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - pci->iwcr = - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + out_be32(&pci->iwcr, + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - pci->icr = 0; + out_be32(&pci->icr, 0); /* Enable bus master and mem access */ - pci->scr = PCI_SCR_B | PCI_SCR_M; + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); /* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); - pci->cr2 = 0; + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); + out_be32(&pci->cr2, 0); #ifdef CONFIG_SYS_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); - pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); + out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); barEn |= PCI_TCR2_B0E; #endif #ifdef CONFIG_SYS_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); - pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); + out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); barEn |= PCI_TCR2_B1E; #endif #ifdef CONFIG_SYS_PCI_BAR2 - pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2); - pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN; + out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2)); + out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN); barEn |= PCI_TCR2_B2E; #endif #ifdef CONFIG_SYS_PCI_BAR3 - pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3); - pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN; + out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3)); + out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN); barEn |= PCI_TCR2_B3E; #endif #ifdef CONFIG_SYS_PCI_BAR4 - pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4); - pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN; + out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4)); + out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN); barEn |= PCI_TCR2_B4E; #endif #ifdef CONFIG_SYS_PCI_BAR5 - pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5); - pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN; + out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5)); + out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN); barEn |= PCI_TCR2_B5E; #endif - pci->tcr2 = barEn; + out_be32(&pci->tcr2, barEn); /* Deassert reset bit */ - pci->gscr &= ~PCI_GSCR_PR; + clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000); /* Enable PCI bus master support */ diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 9c0c07733b5..073b7efafb5 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; void clock_enter_limp(int lpdiv) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + ccm_t *ccm = (ccm_t *)MMAP_CCM; int i, j; /* Check bounds of divider */ @@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv) for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; /* Apply the divider to the system clock */ - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); /* Enable Limp Mode */ - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); } /* @@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv) */ void clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; /* Exit Limp mode */ - ccm->misccr &= ~CCM_MISCCR_LIMP; + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for the PLL to lock */ - while (!(pll->psr & PLL_PSR_LOCK)) ; + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) + ; } /* @@ -85,8 +87,8 @@ void clock_exit_limp(void) int get_clocks(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; int pllmult_pci[] = { 12, 6, 16, 8 }; int vco = 0, bPci, temp, fbtemp, pcrvalue; @@ -94,13 +96,13 @@ int get_clocks(void) u16 fbpll_mask; #ifdef CONFIG_M54455EVB - volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3); + u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3); #endif u8 bootmode; /* To determine PCI is present or not */ - if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || - ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { + if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || + ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { pPllmult = &pllmult_pci[0]; fbpll_mask = 3; /* 11b */ bPci = 1; @@ -114,7 +116,7 @@ int get_clocks(void) } #ifdef CONFIG_M54455EVB - bootmode = (*cpld & 0x03); + bootmode = (in_8(cpld) & 0x03); if (bootmode != 3) { /* Temporary read from CCR- fixed fb issue, must be the same clock @@ -122,11 +124,11 @@ int get_clocks(void) fbtemp = pPllmult[ccm->ccr & fbpll_mask]; /* Break down into small pieces, code still in flex bus */ - pcrvalue = pll->pcr & 0xFFFFF0FF; + pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; temp = fbtemp - 1; pcrvalue |= PLL_PCR_OUTDIV3(temp); - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); } #endif #ifdef CONFIG_M54451EVB @@ -137,9 +139,10 @@ int get_clocks(void) bootmode = 2; /* default value is 16 mul, set to 20 mul */ - pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000; - pll->pcr = pcrvalue; - while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK); + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; + out_be32(&pll->pcr, pcrvalue); + while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) + ; #endif #endif @@ -149,10 +152,10 @@ int get_clocks(void) if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* invaild range, re-set in PCR */ - int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; int i, j, bus; - j = (pll->pcr & 0xFF000000) >> 24; + j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; for (i = j; i < 0xFF; i++) { vco = i * CONFIG_SYS_INPUT_CLKSRC; if (vco >= CLOCK_PLL_FVCO_MIN) { @@ -163,47 +166,47 @@ int get_clocks(void) break; } } - pcrvalue = pll->pcr & 0x00FF00FF; + pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; fbtemp = ((i - 1) << 8) | ((i - 1) << 12); pcrvalue |= ((i << 24) | fbtemp); - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 2) { /* Normal mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* Default value */ - pcrvalue = (pll->pcr & 0x00FFFFFF); - pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; - pll->pcr = pcrvalue; - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); + pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; + out_be32(&pll->pcr, pcrvalue); + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 3) { /* serial mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; /* Vco clock */ } - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; gd->bus_clk = vco / temp; /* bus clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; gd->flb_clk = vco / temp; /* FlexBus clock */ #ifdef CONFIG_PCI if (bPci) { - temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; gd->pci_clk = vco / temp; /* PCI clock */ } #endif diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c index 7590f2c1c72..157a8e41ac7 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,19 +31,20 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - gptmr->pre = 10; - gptmr->cnt = 1; + out_be16(&gptmr->pre, 10); + out_be16(&gptmr->cnt, 1); /* enable watchdog, set timeout to 0 and wait */ - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE); /* we don't return! */ return 1; @@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile siu_t *siu = (siu_t *) MMAP_SIU; + siu_t *siu = (siu_t *) MMAP_SIU; u16 id = 0; puts("CPU: "); - switch ((siu->jtagid & 0x000FF000) >> 12) { + switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) { case 0x0C: id = 5485; break; @@ -111,18 +112,18 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void hw_watchdog_reset(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - gptmr->ocpw = 0xa5; + out_8(&gptmr->ocpw, 0xa5); } int watchdog_disable(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - gptmr->mode = 0; - gptmr->ctrl = 0; + out_8(&gptmr->mode, 0); + out_8(&gptmr->ctrl, 0); puts("WATCHDOG:disabled\n"); @@ -131,14 +132,13 @@ int watchdog_disable(void) int watchdog_init(void) { + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT); + out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000); - gptmr->pre = CONFIG_WATCHDOG_TIMEOUT; - gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000; - - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c index 60c91267a72..4eb8a7c1826 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <MCD_dma.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,58 +45,59 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB; - xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2500; - xlbarb->busto = 0x3000; + out_be32(&xlbarb->adrto, 0x2000); + out_be32(&xlbarb->datto, 0x2500); + out_be32(&xlbarb->busto, 0x3000); - xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; + out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); /* Master Priority Enable */ - xlbarb->prien = 0xff; - xlbarb->pri = 0; + out_be32(&xlbarb->prien, 0xff); + out_be32(&xlbarb->pri, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; + out_be16(&gpio->par_feci2cirq, + GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); #endif icache_enable(); @@ -115,44 +117,44 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ switch (port) { case 0: - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; case 1: - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); break; case 2: - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); break; case 3: - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); break; } - *pscsicr &= 0xF8; + clrbits_8(pscsicr, 0x07); } #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; + setbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq |= 0x0FC0; + setbits_be16(&gpio->par_feci2cirq, 0x0fc0); } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; + clrbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq &= 0xF03F; + clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); } return 0; } diff --git a/arch/m68k/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c index 76be876aa0b..d215438014d 100644 --- a/arch/m68k/cpu/mcf547x_8x/interrupts.c +++ b/arch/m68k/cpu/mcf547x_8x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); @@ -42,9 +43,9 @@ int interrupt_init(void) #if defined(CONFIG_SLTTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c index f867dc12798..1a81e3f04d9 100644 --- a/arch/m68k/cpu/mcf547x_8x/pci.c +++ b/arch/m68k/cpu/mcf547x_8x/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, void pci_mcf547x_8x_init(struct pci_controller *hose) { - volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pci_t *pci = (pci_t *) MMAP_PCI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Port configuration */ - gpio->par_pcibg = - GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | - GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | - GPIO_PAR_PCIBG_PCIBG4(3); - gpio->par_pcibr = - GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | - GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | - GPIO_PAR_PCIBR_PCIBR4(3); + out_be16(&gpio->par_pcibg, + GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | + GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | + GPIO_PAR_PCIBG_PCIBG4(3)); + out_be16(&gpio->par_pcibr, + GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | + GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | + GPIO_PAR_PCIBR_PCIBR4(3)); /* Assert reset bit */ - pci->gscr |= PCI_GSCR_PR; + setbits_be32(&pci->gscr, PCI_GSCR_PR); - pci->tcr1 = PCI_TCR1_P; + out_be32(&pci->tcr1, PCI_TCR1_P); /* Initiator windows */ - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); + out_be32(&pci->iw0btar, + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); + out_be32(&pci->iw1btar, + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); + out_be32(&pci->iw2btar, + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - pci->iwcr = - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + out_be32(&pci->iwcr, + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - pci->icr = 0; + out_be32(&pci->icr, 0); /* Enable bus master and mem access */ - pci->scr = PCI_SCR_B | PCI_SCR_M; + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); /* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); - pci->cr2 = 0; + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); + out_be32(&pci->cr2, 0); #ifdef CONFIG_SYS_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); - pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); + out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); #endif #ifdef CONFIG_SYS_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); - pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); + out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); #endif /* Deassert reset bit */ - pci->gscr &= ~PCI_GSCR_PR; + clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000); /* Enable PCI bus master support */ diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c index ee2e35bd517..25dd2aed56f 100644 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ b/arch/m68k/cpu/mcf547x_8x/slicetimer.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ #include <asm/timer.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,31 +43,32 @@ extern void dtimer_intr_setup(void); void __udelay(unsigned long usec) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); u32 now, freq; /* 1 us period */ freq = CONFIG_SYS_TIMER_PRESCALER; - timerp->cr = 0; /* Disable */ - timerp->tcnt = usec * freq; - timerp->cr = SLT_CR_TEN; + /* Disable */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, usec * freq); + out_be32(&timerp->cr, SLT_CR_TEN); - now = timerp->cnt; + now = in_be32(&timerp->cnt); while (now != 0) - now = timerp->cnt; + now = in_be32(&timerp->cnt); - timerp->sr |= SLT_SR_ST; - timerp->cr = 0; + setbits_be32(&timerp->sr, SLT_SR_ST); + out_be32(&timerp->cr, 0); } void dtimer_interrupt(void *not_used) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); /* check for timer interrupt asserted */ if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { - timerp->sr |= SLT_SR_ST; + setbits_be32(&timerp->sr, SLT_SR_ST); timestamp++; return; } @@ -74,25 +76,27 @@ void dtimer_interrupt(void *not_used) int timer_init(void) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); timestamp = 0; - timerp->cr = 0; /* disable timer */ - timerp->tcnt = 0; - timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ + /* disable timer */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, 0); + /* clear status */ + out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST); /* initialize and enable timer interrupt */ irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); /* Interrupt every ms */ - timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER; + out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER); dtimer_intr_setup(); /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; + out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); return 0; } diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index ad971b4f31f..525d90ccb02 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -17,41 +17,36 @@ extern int test_and_change_bit(int nr, volatile void *addr); #ifdef __KERNEL__ -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) + +extern inline int test_bit(int nr, __const__ volatile void *addr) { - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; + __const__ unsigned int *p = (__const__ unsigned int *) addr; + + return (p[nr >> 5] & (1UL << (nr & 31))) != 0; } + +extern inline int test_and_set_bit(int nr, volatile void *vaddr) +{ + char retval; + + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; + __asm__ __volatile__ ("bset %2,(%4); sne %0" + : "=d" (retval), "=m" (*p) + : "di" (nr & 7), "m" (*p), "a" (p)); + + return retval; +} + #define __ffs(x) (ffs(x) - 1) -#define PLATFORM_FFS + +/* + * * hweightN: returns the hamming weight (i.e. the number + * * of bits set) of a N-bit word + * */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) #endif /* __KERNEL__ */ diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h index 51cbbd8b2b0..9a3078a14a9 100644 --- a/arch/m68k/include/asm/coldfire/flexbus.h +++ b/arch/m68k/include/asm/coldfire/flexbus.h @@ -29,7 +29,57 @@ /********************************************************************* * FlexBus Chip Selects (FBCS) *********************************************************************/ +#ifdef CONFIG_M5235 +typedef struct fbcs { + u16 csar0; /* Chip-select Address */ + u16 res1; + u32 csmr0; /* Chip-select Mask */ + u16 res2; + u16 cscr0; /* Chip-select Control */ + + u16 csar1; + u16 res3; + u32 csmr1; + u16 res4; + u16 cscr1; + + u16 csar2; + u16 res5; + u32 csmr2; + u16 res6; + u16 cscr2; + + u16 csar3; + u16 res7; + u32 csmr3; + u16 res8; + u16 cscr3; + + u16 csar4; + u16 res9; + u32 csmr4; + u16 res10; + u16 cscr4; + + u16 csar5; + u16 res11; + u32 csmr5; + u16 res12; + u16 cscr5; + u16 csar6; + u16 res13; + u32 csmr6; + u16 res14; + u16 cscr6; + + u16 csar7; + u16 res15; + u32 csmr7; + u16 res16; + u16 cscr7; +} fbcs_t; +#else typedef struct fbcs { u32 csar0; /* Chip-select Address */ u32 csmr0; /* Chip-select Mask */ @@ -56,6 +106,7 @@ typedef struct fbcs { u32 csmr7; u32 cscr7; } fbcs_t; +#endif #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) @@ -94,6 +145,22 @@ typedef struct fbcs { #endif #define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#ifdef CONFIG_M5235 +#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) +#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) +#define FBCS_CSCR_AA_ON (1 << 8) +#define FBCS_CSCR_AA_OFF (0 << 8) +#define FBCS_CSCR_PS_32 (0 << 6) +#define FBCS_CSCR_PS_16 (2 << 6) +#define FBCS_CSCR_PS_8 (1 << 6) +#define FBCS_CSCR_BEM_ON (1 << 5) +#define FBCS_CSCR_BEM_OFF (0 << 5) +#define FBCS_CSCR_BSTR_ON (1 << 4) +#define FBCS_CSCR_BSTR_OFF (0 << 4) +#define FBCS_CSCR_BSTW_ON (1 << 3) +#define FBCS_CSCR_BSTW_OFF (0 << 3) +#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) +#else #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) #define FBCS_CSCR_SWS_MASK (0x03FFFFFF) #define FBCS_CSCR_SWSEN (0x00800000) @@ -116,5 +183,6 @@ typedef struct fbcs { #define FBCS_CSCR_PS_16 (0x00000080) #define FBCS_CSCR_PS_8 (0x00000040) #define FBCS_CSCR_PS_32 (0x00000000) +#endif #endif /* __FLEXBUS_H */ diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h index 8bcd2e4db1a..9fd98f6c044 100644 --- a/arch/m68k/include/asm/coldfire/qspi.h +++ b/arch/m68k/include/asm/coldfire/qspi.h @@ -98,7 +98,7 @@ typedef struct qspi_ctrl { #define QSPI_QAR_RECV (0x0010) #define QSPI_QAR_CMD (0x0020) -/* DR */ +/* DR with RAM command word definitions */ #define QSPI_QDR_CONT (0x8000) #define QSPI_QDR_BITSE (0x4000) #define QSPI_QDR_DT (0x2000) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index d86eaf95eac..50ed74989d5 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -1,7 +1,7 @@ /* * IO header file * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -225,6 +225,42 @@ extern inline void out_be32(volatile unsigned *addr, int val) *addr = val; } +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + static inline void sync(void) { /* This sync function is for PowerPC or other architecture instruction diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index d25261bcd1b..b2bc05111d8 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -171,6 +171,32 @@ #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 +/* Bit definitions and macros for PAR_QSPI */ +#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F +#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0 +#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80 +#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF +#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20 +#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7 +#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18 +#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10 +#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB +#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04 +#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC +#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03 +#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02 +#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00 + +/* Bit definitions and macros for PAR_TIMER for QSPI */ +#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF +#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000 +#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F +#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040 + #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) #define MCF_SDRAMC_DCR 0x000040 diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index aca79e26197..b4935f0a56b 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -31,3 +31,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds + +CONFIG_ARCH_DEVICE_TREE := microblaze diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index ee67082188c..7f2ee64ca0a 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -32,15 +32,12 @@ #undef DEBUG_INT -extern void microblaze_disable_interrupts (void); -extern void microblaze_enable_interrupts (void); - -void enable_interrupts (void) +void enable_interrupts(void) { MSRSET(0x2); } -int disable_interrupts (void) +int disable_interrupts(void) { unsigned int msr; @@ -58,20 +55,21 @@ microblaze_intc_t *intc; /* default handler */ static void def_hdlr(void) { - puts ("def_hdlr\n"); + puts("def_hdlr\n"); } static void enable_one_interrupt(int irq) { int mask; int offset = 1; + offset <<= irq; mask = intc->ier; intc->ier = (mask | offset); #ifdef DEBUG_INT - printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask, + printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask, intc->ier); - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, + printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, intc->iar, intc->mer); #endif } @@ -80,25 +78,26 @@ static void disable_one_interrupt(int irq) { int mask; int offset = 1; + offset <<= irq; mask = intc->ier; intc->ier = (mask & ~offset); #ifdef DEBUG_INT - printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask, + printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask, intc->ier); - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, + printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, intc->iar, intc->mer); #endif } -/* adding new handler for interrupt */ -void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg) +int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg) { struct irq_action *act; + /* irq out of range */ if ((irq < 0) || (irq > irq_no)) { - puts ("IRQ out of range\n"); - return; + puts("IRQ out of range\n"); + return -1; } act = &vecs[irq]; if (hdlr) { /* enable */ @@ -106,11 +105,14 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg) act->arg = arg; act->count = 0; enable_one_interrupt (irq); - } else { /* disable */ - act->handler = (interrupt_handler_t *) def_hdlr; - act->arg = (void *)irq; - disable_one_interrupt (irq); + return 0; } + + /* Disable */ + act->handler = (interrupt_handler_t *) def_hdlr; + act->arg = (void *)irq; + disable_one_interrupt(irq); + return 1; } /* initialization interrupt controller - hardware */ @@ -122,7 +124,7 @@ static void intc_init(void) /* XIntc_Start - hw_interrupt enable and all interrupt enable */ intc->mer = 0x3; #ifdef DEBUG_INT - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, + printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, intc->iar, intc->mer); #endif } @@ -157,7 +159,7 @@ int interrupts_init(void) return 0; } -void interrupt_handler (void) +void interrupt_handler(void) { int irqs = intc->ivr; /* find active interrupt */ int mask = 1; diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8a2f634a99c..8564c4e30ab 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -149,7 +149,7 @@ clear_bss: cmp r6, r5, r4 /* check if we have reach the end */ bnei r6, 2b 3: /* jumping to board_init */ - brai board_init + brai board_init_f 1: bri 1b /* diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index cc6b897fbb5..1330401a934 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -27,42 +27,30 @@ #include <asm/microblaze_intc.h> volatile int timestamp = 0; +microblaze_timer_t *tmr; -#ifdef CONFIG_SYS_TIMER_0 ulong get_timer (ulong base) { - return (timestamp - base); + if (tmr) + return timestamp - base; + return timestamp++ - base; } -#else -ulong get_timer (ulong base) -{ - return (timestamp++ - base); -} -#endif -#ifdef CONFIG_SYS_TIMER_0 void __udelay(unsigned long usec) { - int i; + u32 i; - i = get_timer(0); - while ((get_timer(0) - i) < (usec / 1000)) - ; + if (tmr) { + i = get_timer(0); + while ((get_timer(0) - i) < (usec / 1000)) + ; + } else { + for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++) + ; + } } -#else -void __udelay(unsigned long usec) -{ - unsigned int i; - for (i = 0; i < (usec * CONFIG_XILINX_CLOCK_FREQ / 10000000); i++) - ; -} -#endif - -#ifdef CONFIG_SYS_TIMER_0 -microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); - -void timer_isr (void *arg) +static void timer_isr(void *arg) { timestamp++; tmr->control = tmr->control | TIMER_INTERRUPT; @@ -70,15 +58,30 @@ void timer_isr (void *arg) int timer_init (void) { - tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD; - tmr->control = TIMER_INTERRUPT | TIMER_RESET; - tmr->control = - TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT; - timestamp = 0; - install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr); + int irq = -1; + u32 preload = 0; + u32 ret = 0; + +#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) + preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ; + irq = CONFIG_SYS_TIMER_0_IRQ; + tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); +#endif + + if (tmr && preload && irq >= 0) { + tmr->loadreg = preload; + tmr->control = TIMER_INTERRUPT | TIMER_RESET; + tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\ + TIMER_RELOAD | TIMER_DOWN_COUNT; + timestamp = 0; + ret = install_interrupt_handler (irq, timer_isr, (void *)tmr); + if (ret) + tmr = NULL; + } + + /* No problem if timer is not found/initialized */ return 0; } -#endif /* * This function is derived from PowerPC code (read timebase as long long). diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index ee41145bb58..d033a2835b3 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -45,6 +45,7 @@ SECTIONS .data ALIGN(0x4): { __data_start = .; + dts/libdts.o (.data) *(.data) __data_end = .; } diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 0dc4ce9ee52..de3b8dbe927 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -41,6 +41,7 @@ typedef struct global_data { unsigned long precon_buf_idx; /* Pre-Console buffer index */ #endif unsigned long env_addr; /* Address of Environment struct */ + const void *fdt_blob; /* Our device tree, NULL if none */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ void **jt; /* jump table */ diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h index 6142b9c9952..e9640f54376 100644 --- a/arch/microblaze/include/asm/microblaze_intc.h +++ b/arch/microblaze/include/asm/microblaze_intc.h @@ -39,7 +39,16 @@ struct irq_action { int count; /* number of interrupt */ }; -void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, +/** + * Register and unregister interrupt handler rutines + * + * @param irq IRQ number + * @param hdlr Interrupt handler rutine + * @param arg Pointer to argument which is passed to int. handler rutine + * @return 0 if registration pass, 1 if unregistration pass, + * or an error code < 0 otherwise + */ +int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg); int interrupts_init(void); diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h index 844c8db1151..28e8b027cbd 100644 --- a/arch/microblaze/include/asm/microblaze_timer.h +++ b/arch/microblaze/include/asm/microblaze_timer.h @@ -39,3 +39,6 @@ typedef volatile struct microblaze_timer_t { int loadreg; /* load register TLR */ int counter; /* timer/counter register */ } microblaze_timer_t; + +int timer_init(void); + diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index 2295d0a460e..2c4d5ffc5cb 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h @@ -28,4 +28,7 @@ extern char __end[]; extern char __text_start[]; +/* Microblaze board initialization function */ +void board_init(void); + #endif /* __ASM_MICROBLAZE_PROCESSOR_H */ diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index b80250a6bc2..674b5731966 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -32,21 +32,13 @@ #include <stdio_dev.h> #include <serial.h> #include <net.h> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> +#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SYS_GPIO_0 -extern int gpio_init (void); -#endif -#ifdef CONFIG_SYS_TIMER_0 -extern int timer_init (void); -#endif -#ifdef CONFIG_SYS_FSL_2 -extern void fsl_init2 (void); -#endif - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -63,31 +55,26 @@ typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { env_init, +#ifdef CONFIG_OF_CONTROL + fdtdec_check_fdt, +#endif serial_init, console_init_f, -#ifdef CONFIG_SYS_GPIO_0 - gpio_init, -#endif interrupts_init, -#ifdef CONFIG_SYS_TIMER_0 timer_init, -#endif -#ifdef CONFIG_SYS_FSL_2 - fsl_init2, -#endif NULL, }; unsigned long monitor_flash_len; -void board_init (void) +void board_init_f(ulong not_used) { bd_t *bd; init_fnc_t **init_fnc_ptr; gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET); bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \ - GENERATED_BD_INFO_SIZE); - char *s; + __maybe_unused char *s; #if defined(CONFIG_CMD_FLASH) ulong flash_size = 0; #endif @@ -103,6 +90,17 @@ void board_init (void) monitor_flash_len = __end - __text_start; +#ifdef CONFIG_OF_EMBED + /* Get a pointer to the FDT */ + gd->fdt_blob = _binary_dt_dtb_start; +#elif defined CONFIG_OF_SEPARATE + /* FDT is at end of image */ + gd->fdt_blob = (void *)__end; +#endif + /* Allow the early environment to override the fdt address */ + gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, + (uintptr_t)gd->fdt_blob); + /* * The Malloc area is immediately below the monitor copy in DRAM * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off @@ -121,6 +119,15 @@ void board_init (void) } } +#ifdef CONFIG_OF_CONTROL + /* For now, put this check after the console is ready */ + if (fdtdec_prepare_fdt()) { + panic("** CONFIG_OF_CONTROL defined but no FDT - please see " + "doc/README.fdt-control"); + } else + printf("DTB: 0x%x\n", (u32)gd->fdt_blob); +#endif + puts ("SDRAM :\n"); printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF"); printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF"); @@ -129,9 +136,8 @@ void board_init (void) #if defined(CONFIG_CMD_FLASH) puts ("Flash: "); bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - if (0 < (flash_size = flash_init ())) { - bd->bi_flashsize = flash_size; - bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size; + flash_size = flash_init(); + if (bd->bi_flashstart && flash_size > 0) { # ifdef CONFIG_SYS_FLASH_CHECKSUM print_size (flash_size, ""); /* @@ -142,13 +148,16 @@ void board_init (void) s = getenv ("flashchecksum"); if (s && (*s == 'y')) { printf (" CRC: %08X", - crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) + crc32(0, (const u8 *)bd->bi_flashstart, + flash_size) ); } putc ('\n'); # else /* !CONFIG_SYS_FLASH_CHECKSUM */ print_size (flash_size, "\n"); # endif /* CONFIG_SYS_FLASH_CHECKSUM */ + bd->bi_flashsize = flash_size; + bd->bi_flashoffset = bd->bi_flashstart + flash_size; } else { puts ("Flash init FAILED"); bd->bi_flashstart = 0; @@ -169,6 +178,8 @@ void board_init (void) /* Initialize the console (after the relocation and devices init) */ console_init_r(); + board_init(); + /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acdb17b..de9140b67b5 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,21 @@ CROSS_COMPILE ?= mips_4KC- -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +# Handle special prefix in ELDK 4.0 toolchain +ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ENDIANNESS := -EL +endif + +ifdef CONFIG_SYS_LITTLE_ENDIAN +ENDIANNESS := -EL +endif + +ifdef CONFIG_SYS_BIG_ENDIAN +ENDIANNESS := -EB +endif + +# Default to EB if no endianess is configured +ENDIANNESS ?= -EB PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ @@ -47,8 +61,8 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS) PLATFORM_CPPFLAGS += -msoft-float -PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index a1cd590a004..481e9844db2 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -29,21 +29,6 @@ # MIPSFLAGS := -march=mips32r2 -# Handle special prefix in ELDK 4.0 toolchain -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS := -EL -endif +PLATFORM_CPPFLAGS += $(MIPSFLAGS) -ifdef CONFIG_SYS_LITTLE_ENDIAN -ENDIANNESS := -EL -endif - -ifdef CONFIG_SYS_BIG_ENDIAN -ENDIANNESS := -EB -endif - -# Default to EB if no endianess is configured -ENDIANNESS ?= -EB - -PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANNESS) -PLATFORM_LDFLAGS += $(ENDIANNESS) +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index bce0c1bcb62..1536746c974 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -20,5 +20,6 @@ # MA 02111-1307 USA # -PLATFORM_CPPFLAGS += -march=mips32 -EL -PLATFORM_LDFLAGS += -EL +PLATFORM_CPPFLAGS += -march=mips32 + +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index e9763415979..ddcbfaa47c9 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -62,7 +62,7 @@ void __attribute__((weak)) _machine_restart(void) writew(100, &wdt->tdr); /* wdt_set_data(100) */ writew(0, &wdt->tcnt); /* wdt_set_count(0); */ - writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ + writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ while (1) diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c index de6f5daa35a..b6b3855ea19 100644 --- a/arch/mips/cpu/xburst/timer.c +++ b/arch/mips/cpu/xburst/timer.c @@ -34,13 +34,13 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; void reset_timer_masked(void) { /* reset time */ - gd->lastinc = readw(&tcu->tcnt0); + gd->lastinc = readl(&tcu->tcnt0); gd->tbl = 0; } ulong get_timer_masked(void) { - ulong now = readw(&tcu->tcnt0); + ulong now = readl(&tcu->tcnt0); if (gd->lastinc <= now) gd->tbl += now - gd->lastinc; /* normal mode */ @@ -83,11 +83,11 @@ void udelay_masked(unsigned long usec) int timer_init(void) { - writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); + writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); - writew(0, &tcu->tcnt0); - writew(0, &tcu->tdhr0); - writew(TIMER_FDATA, &tcu->tdfr0); + writel(0, &tcu->tcnt0); + writel(0, &tcu->tdhr0); + writel(TIMER_FDATA, &tcu->tdfr0); /* mask irqs */ writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr); diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 9244f3151a7..967e98a5261 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -25,6 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o +## Build a couple of necessary functions into a private libgcc +LIBGCC = $(obj)libgcc.o +GLSOBJS += ashldi3.o +GLSOBJS += ashrdi3.o +GLSOBJS += lshrdi3.o +LGOBJS := $(addprefix $(obj),$(GLSOBJS)) + SOBJS-y += COBJS-y += board.o @@ -37,9 +44,22 @@ endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +# Always build libmips.o +TARGETS := $(LIB) + +# Build private libgcc only when asked for +ifdef USE_PRIVATE_LIBGCC +TARGETS += $(LIBGCC) +endif + +all: $(TARGETS) + $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) + ######################################################################### # defines $(obj).depend target diff --git a/arch/mips/lib/ashldi3.c b/arch/mips/lib/ashldi3.c new file mode 100644 index 00000000000..9b50d866a01 --- /dev/null +++ b/arch/mips/lib/ashldi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} diff --git a/arch/mips/lib/ashrdi3.c b/arch/mips/lib/ashrdi3.c new file mode 100644 index 00000000000..f30359b73f0 --- /dev/null +++ b/arch/mips/lib/ashrdi3.c @@ -0,0 +1,27 @@ +#include "libgcc.h" + +long long __ashrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + /* w.s.high = 1..1 or 0..0 */ + w.s.high = + uu.s.high >> 31; + w.s.low = uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/mips/lib/libgcc.h b/arch/mips/lib/libgcc.h new file mode 100644 index 00000000000..05909d58e2f --- /dev/null +++ b/arch/mips/lib/libgcc.h @@ -0,0 +1,25 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { + int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { + int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff --git a/arch/mips/lib/lshrdi3.c b/arch/mips/lib/lshrdi3.c new file mode 100644 index 00000000000..bb340accba2 --- /dev/null +++ b/arch/mips/lib/lshrdi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 34f6c546984..33e93c88d72 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -55,8 +55,6 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1014) += ddr-gen3.o -COBJS-$(CONFIG_P1015) += ddr-gen3.o -COBJS-$(CONFIG_P1016) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o @@ -64,10 +62,8 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o -COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o @@ -80,10 +76,8 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o -COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -103,8 +97,6 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o COBJS-$(CONFIG_P1014) += p1010_serdes.o -COBJS-$(CONFIG_P1015) += p1021_serdes.o -COBJS-$(CONFIG_P1016) += p1021_serdes.o COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o @@ -114,10 +106,8 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o -COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 4e1a54ad0c5..e8989bdf459 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -27,6 +27,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + extern int enable_cpu_a011_workaround; +#endif __maybe_unused u32 svr = get_svr(); #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) @@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * The SVR has been checked by cpu_init_r(). */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + if (enable_cpu_a011_workaround) puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) @@ -120,6 +124,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG ETSEC129 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + puts("Work-around for Erratum A004510 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index c1815e8860d..5ddb29435c1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -117,6 +117,9 @@ int checkcpu (void) case PVR_VER_E5500: puts("E5500"); break; + case PVR_VER_E6500: + puts("E6500"); + break; default: puts("Unknown"); break; @@ -427,11 +430,21 @@ static void dump_spd_ddr_reg(void) case 0: ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; break; -#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR +#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; break; #endif +#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; + break; +#endif default: printf("%s unexpected controller number = %u\n", __func__, i); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index fc6c2877d25..afb56719da2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,6 +38,7 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <hwconfig.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -311,11 +312,41 @@ int cpu_init_r(void) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* + * CPU22 and NMG_CPU_A011 share the same workaround. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) + enable_cpu_a011_workaround = 0; + else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { flush_dcache(); mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); sync(); @@ -447,11 +478,18 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_SRIOBOOT_MASTER - srio_boot_master(); -#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF - srio_boot_master_release_slave(); -#endif +#ifdef CONFIG_FSL_CORENET + char *s = getenv("bootmaster"); + if (s) { + if (!strcmp(s, "SRIO1")) { + srio_boot_master(1); + srio_boot_master_release_slave(1); + } + if (!strcmp(s, "SRIO2")) { + srio_boot_master(2); + srio_boot_master_release_slave(2); + } + } #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 81961def1b7..ca4ed626457 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -32,9 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, case 0: ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; break; +#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; break; +#endif +#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; + break; +#endif default: printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); return; @@ -43,6 +55,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->eor, regs->ddr_eor); #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; cs_ea = regs->cs[i].bnds & 0xfff; @@ -115,8 +128,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); out_be32(&ddr->err_disable, regs->err_disable); out_be32(&ddr->err_int_en, regs->err_int_en); - for (i = 0; i < 32; i++) - out_be32(&ddr->debug[i], regs->debug[i]); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); + out_be32(&ddr->debug[i], regs->debug[i]); + } + } #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 out_be32(&ddr->debug[12], 0x00000015); @@ -128,6 +145,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); out_be32(&ddr->sdram_cfg, temp_sdram_cfg); #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + debug("Workaround for ERRATUM_DDR_A003\n"); if (regs->ddr_sdram_rcw_2 & 0x00f00000) { out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); out_be32(&ddr->debug[2], 0x00000400); @@ -209,6 +227,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, * This erratum does not affect DDR3 mode, only for DDR2 mode. */ #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 + debug("Workaround for ERRATUM_DDR_115\n"); if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ @@ -216,6 +235,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); /* * This is the combined workaround for DDR111 and DDR134 * following the published errata for MPC8572 diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 21c3ad49bfb..a0a9b4c5ae9 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -57,8 +57,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); + u32 phys_cpu_id = thread_to_core(*reg); + u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt64(val); if (*reg == id) { fdt_setprop_string(blob, off, "status", "okay"); @@ -534,7 +535,7 @@ void fdt_fixup_fman_firmware(void *blob) #define fdt_fixup_fman_firmware(x) #endif -#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060) +#if defined(CONFIG_PPC_P4080) static void fdt_fixup_usb(void *fdt) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 4b52dad56ce..2a680603697 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -46,8 +46,6 @@ static u32 serdes_prtcl_map; -#define HWCONFIG_BUFFER_SIZE 128 - #ifdef DEBUG static const char *serdes_prtcl_str[] = { [NONE] = "NA", @@ -68,6 +66,7 @@ static const char *serdes_prtcl_str[] = { [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", [XAUI_FM1] = "XAUI_FM1", [XAUI_FM2] = "XAUI_FM2", [AURORA] = "DEBUG", @@ -658,6 +657,7 @@ void fsl_serdes_init(void) case SGMII_FM2_DTSEC2: case SGMII_FM2_DTSEC3: case SGMII_FM2_DTSEC4: + case SGMII_FM2_DTSEC5: case XAUI_FM1: case XAUI_FM2: case SRIO1: @@ -717,6 +717,10 @@ void fsl_serdes_init(void) serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | FSL_CORENET_DEVDISR2_DTSEC2_4; break; + case SGMII_FM2_DTSEC5: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_5; + break; case XAUI_FM1: serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | FSL_CORENET_DEVDISR2_10GEC1; diff --git a/arch/powerpc/cpu/mpc85xx/p3060_ids.c b/arch/powerpc/cpu/mpc85xx/p3060_ids.c deleted file mode 100644 index d32142f6369..00000000000 --- a/arch/powerpc/cpu/mpc85xx/p3060_ids.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> - -#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { - /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO( 1, 2, 1, 0), - SET_QP_INFO( 3, 4, 2, 1), - SET_QP_INFO( 5, 6, 3, 2), - SET_QP_INFO( 7, 8, 4, 3), - SET_QP_INFO( 9, 10, 5, 4), - SET_QP_INFO(11, 12, 6, 5), - SET_QP_INFO(13, 14, 7, 6), - SET_QP_INFO(15, 16, 8, 7), - SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ - SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ -}; -#endif - -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 198), - SET_SRIO_LIODN_1(2, 199), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - -struct liodn_id_table liodn_tbl[] = { - SET_USB_LIODN(1, "fsl-usb2-mph", 127), - SET_USB_LIODN(2, "fsl-usb2-dr", 157), - - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - - SET_DMA_LIODN(1, 196), - SET_DMA_LIODN(2, 197), - - SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), - -#ifdef CONFIG_SYS_DPAA_QBMAN - SET_QMAN_LIODN(31), - SET_BMAN_LIODN(32), -#endif - SET_PME_LIODN(128), -}; -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); - -#ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 11), - SET_FMAN_RX_1G_LIODN(1, 1, 12), - SET_FMAN_RX_1G_LIODN(1, 2, 13), - SET_FMAN_RX_1G_LIODN(1, 3, 14), -}; -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); - -#if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(2, 0, 16), - SET_FMAN_RX_1G_LIODN(2, 1, 17), - SET_FMAN_RX_1G_LIODN(2, 2, 18), - SET_FMAN_RX_1G_LIODN(2, 3, 19), -}; -int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); -#endif -#endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 146, 154), - SET_SEC_JR_LIODN_ENTRY(1, 147, 155), - SET_SEC_JR_LIODN_ENTRY(2, 178, 186), - SET_SEC_JR_LIODN_ENTRY(3, 179, 187), - SET_SEC_RTIC_LIODN_ENTRY(a, 144), - SET_SEC_RTIC_LIODN_ENTRY(b, 145), - SET_SEC_RTIC_LIODN_ENTRY(c, 176), - SET_SEC_RTIC_LIODN_ENTRY(d, 177), - SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), - SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), - SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), - SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), - SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), -}; -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); - -struct liodn_id_table liodn_bases[] = { - [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), -#ifdef CONFIG_SYS_DPAA_FMAN - [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#if (CONFIG_SYS_NUM_FMAN == 2) - [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), -#endif -#endif -#ifdef CONFIG_SYS_DPAA_PME - [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), -#endif -}; diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c deleted file mode 100644 index e720dcf6bd3..00000000000 --- a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/fsl_serdes.h> -#include <asm/processor.h> -#include <asm/io.h> -#include "fsl_corenet_serdes.h" - -static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { - [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1, - SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, - NONE, NONE, AURORA, AURORA}, - [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3, - SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, - SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA}, - [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, - SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, - SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, - [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3, - SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, - [0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE, - AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, - SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3, - SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4}, -}; - -enum srds_prtcl serdes_get_prtcl(int cfg, int lane) -{ - if (!serdes_lane_enabled(lane)) - return NONE; - - return serdes_cfg_tbl[cfg][lane]; -} - -int is_serdes_prtcl_valid(u32 prtcl) -{ - int i; - - if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[prtcl][i] != NONE) - return 1; - } - - return 0; -} - -void soc_serdes_init(void) -{ - /* - * On the P3060 the devdisr2 register does not correctly reflect - * the state of the MACs based on the RCW fields. So disable the MACs - * based on the srds_prtcl and ec1, ec2, ec3 fields - */ - - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 devdisr2 = in_be32(&gur->devdisr2); - u32 rcwsr11 = in_be32(&gur->rcwsr[11]); - - /* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */ - - if (!is_serdes_configured(SGMII_FM1_DTSEC3)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3; - - if (!is_serdes_configured(SGMII_FM1_DTSEC4)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4; - - if (!is_serdes_configured(SGMII_FM2_DTSEC1)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1; - - if (!is_serdes_configured(SGMII_FM2_DTSEC2)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2; - - if (!is_serdes_configured(SGMII_FM2_DTSEC3)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3; - - if (!is_serdes_configured(SGMII_FM2_DTSEC4)) - devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4; - - if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == - FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) { - devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2; - } - - if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == - FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) { - devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1; - } - - out_be32(&gur->devdisr2, devdisr2); -} diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 1860684c11a..22e73e06610 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -74,6 +74,33 @@ __secondary_start_page: mtspr 977,r3 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xff + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + cmpw r3,r4 + beq 1f + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + cmpw r3,r4 + beq 1f +#endif + + /* Not a supported revision affected by erratum */ + b 2f + +1: /* Erratum says set bits 55:60 to 001001 */ + msync + isync + mfspr r3,976 + li r4,0x48 + rlwimi r3,r4,0,0x1f8 + mtspr 976,r3 + isync +2: +#endif + /* Enable branch prediction */ lis r3,BUCSR_ENABLE@h ori r3,r3,BUCSR_ENABLE@l @@ -128,7 +155,27 @@ __secondary_start_page: /* r10 has the base address for the entry */ mfspr r0,SPRN_PIR -#ifdef CONFIG_E500MC +#if defined(CONFIG_E6500) +/* + * PIR definition for E6500 + * 0-17 Reserved (logic 0s) + * 8-19 CHIP_ID, 2’b00 - SoC 1 + * all others - reserved + * 20-24 CLUSTER_ID 5’b00000 - CCM 1 + * all others - reserved + * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1 + * 2’b01 - cluster 2 + * 2’b10 - cluster 3 + * 2’b11 - cluster 4 + * 27-28 CORE_ID 2’b00 - core 0 + * 2’b01 - core 1 + * 2’b10 - core 2 + * 2’b11 - core 3 + * 29-31 THREAD_ID 3’b000 - thread 0 + * 3’b001 - thread 1 + */ + rlwinm r4,r0,29,25,31 +#elif defined(CONFIG_E500MC) rlwinm r4,r0,27,27,31 #else mr r4,r0 @@ -143,6 +190,25 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif +#ifdef CONFIG_E6500 + mfspr r0,SPRN_PIR + /* + * core 0 thread 0: pir reset value 0x00, new pir 0 + * core 0 thread 1: pir reset value 0x01, new pir 1 + * core 1 thread 0: pir reset value 0x08, new pir 2 + * core 1 thread 1: pir reset value 0x09, new pir 3 + * core 2 thread 0: pir reset value 0x10, new pir 4 + * core 2 thread 1: pir reset value 0x11, new pir 5 + * etc. + * + * Only thread 0 of each core will be running, updating PIR doesn't + * need to deal with the thread bits. + */ + rlwinm r4,r0,30,24,30 +#endif + + mtspr SPRN_PIR,r4 /* write to PIR register */ + #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* @@ -163,6 +229,12 @@ __secondary_start_page: cmpw r3,r5 bge 2f 1: +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + lis r3,toreset(enable_cpu_a011_workaround)@ha + lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) + cmpwi r3,0 + beq 2f +#endif mfspr r3,L1CSR2 oris r3,r3,(L1CSR2_DCWS)@h mtspr L1CSR2,r3 @@ -220,7 +292,7 @@ __secondary_start_page: /* setup the entry */ li r3,0 li r8,1 - stw r0,ENTRY_PIR(r10) + stw r4,ENTRY_PIR(r10) stw r3,ENTRY_ADDR_UPPER(r10) stw r8,ENTRY_ADDR_LOWER(r10) stw r3,ENTRY_R3_UPPER(r10) @@ -346,6 +418,15 @@ __bootpg_addr: __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 1 + /* Fill in the empty space. The actual reset vector is * the last word of the page */ __secondary_start_code_end: diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index ce475324550..abfeb268d4d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -186,8 +186,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_QE -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) sysInfo->freqQE = sysInfo->freqSystemBus; #else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6aabc30c283..9e04257d2ca 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -86,6 +86,35 @@ _start_e500: li r1,MSR_DE mtmsr r1 +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xff + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + cmpw r3,r4 + beq 1f + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + cmpw r3,r4 + beq 1f +#endif + + /* Not a supported revision affected by erratum */ + li r27,0 + b 2f + +1: li r27,1 /* Remember for later that we have the erratum */ + /* Erratum says set bits 55:60 to 001001 */ + msync + isync + mfspr r3,976 + li r4,0x48 + rlwimi r3,r4,0,0x1f8 + mtspr 976,r3 + isync +2: +#endif + #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later @@ -406,12 +435,11 @@ l2_disabled: * Search for the TLB that covers the code we're executing, and shrink it * so that it covers only this 4K page. That will ensure that any other * TLB we create won't interfere with it. We assume that the TLB exists, - * which is why we don't check the Valid bit of MAS1. + * which is why we don't check the Valid bit of MAS1. We also assume + * it is in TLB1. * * This is necessary, for example, when booting from the on-chip ROM, * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. - * If we don't shrink this TLB now, then we'll accidentally delete it - * in "purge_old_ccsr_tlb" below. */ bl nexti /* Find our address */ nexti: mflr r1 /* R1 = our PC */ @@ -421,11 +449,15 @@ nexti: mflr r1 /* R1 = our PC */ msync tlbsx 0, r1 /* This must succeed */ + mfspr r14, MAS0 /* Save ESEL for later */ + rlwinm r14, r14, 16, 0xfff + /* Set the size of the TLB to 4KB */ mfspr r3, MAS1 li r2, 0xF00 andc r3, r3, r2 /* Clear the TSIZE bits */ ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + oris r3, r3, MAS1_IPROT@h mtspr MAS1, r3 /* @@ -440,6 +472,14 @@ nexti: mflr r1 /* R1 = our PC */ mfspr r2, MAS2 andc r2, r2, r3 or r2, r2, r1 +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + cmpwi r27,0 + beq 1f + andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ + rlwinm r2, r2, 0, ~MAS2_I + ori r2, r2, MAS2_G +1: +#endif mtspr MAS2, r2 /* Set the EPN to our PC base address */ mfspr r2, MAS3 @@ -452,6 +492,39 @@ nexti: mflr r1 /* R1 = our PC */ tlbwe /* + * Clear out any other TLB entries that may exist, to avoid conflicts. + * Our TLB entry is in r14. + */ + li r0, TLBIVAX_ALL | TLBIVAX_TLB0 + tlbivax 0, r0 + tlbsync + + mfspr r4, SPRN_TLB1CFG + rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK + + li r3, 0 + mtspr MAS1, r3 +1: cmpw r3, r14 +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) + cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB + cror cr0*4+eq, cr0*4+eq, cr1*4+eq +#endif + rlwinm r5, r3, 16, MAS0_ESEL_MSK + addi r3, r3, 1 + beq 2f /* skip the entry we're executing from */ + + oris r5, r5, MAS0_TLBSEL(1)@h + mtspr MAS0, r5 + + isync + tlbwe + isync + msync + +2: cmpw r3, r4 + blt 1b + +/* * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default * location is not where we want it. This typically happens on a 36-bit * system, where we want to move CCSR to near the top of 36-bit address space. @@ -469,41 +542,15 @@ nexti: mflr r1 /* R1 = our PC */ #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." #endif -purge_old_ccsr_tlb: - lis r8, CONFIG_SYS_CCSRBAR@h - ori r8, r8, CONFIG_SYS_CCSRBAR@l - lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h - ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l - - /* - * In a multi-stage boot (e.g. NAND boot), a previous stage may have - * created a TLB for CCSR, which will interfere with our relocation - * code. Since we're going to create a new TLB for CCSR anyway, - * it should be safe to delete this old TLB here. We have to search - * for it, though. - */ - - li r1, 0 - mtspr MAS6, r1 /* Search the current address space and PID */ - isync - msync - tlbsx 0, r8 - mfspr r1, MAS1 - andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ - beq 1f /* Skip if no TLB found */ - - rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ - mtspr MAS1, r1 - isync - msync - tlbwe -1: - create_ccsr_new_tlb: /* * Create a TLB for the new location of CCSR. Register R8 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). */ + lis r8, CONFIG_SYS_CCSRBAR@h + ori r8, r8, CONFIG_SYS_CCSRBAR@l + lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h @@ -719,6 +766,253 @@ delete_temp_tlbs: tlbwe #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 +#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define LAW_SIZE_1M 0x13 +#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) + + cmpwi r27,0 + beq 9f + + /* + * Create a TLB entry for CCSR + * + * We're executing out of TLB1 entry in r14, and that's the only + * TLB entry that exists. To allocate some TLB entries for our + * own use, flip a bit high enough that we won't flip it again + * via incrementing. + */ + + xori r8, r14, 32 + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r8, 16, MAS0_ESEL_MSK + lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h + ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l + lis r7, CONFIG_SYS_CCSRBAR@h + ori r7, r7, CONFIG_SYS_CCSRBAR@l + ori r2, r7, MAS2_I|MAS2_G + lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r4 + isync + tlbwe + isync + msync + + /* Map DCSR temporarily to physical address zero */ + li r0, 0 + lis r3, DCSRBAR_LAWAR@h + ori r3, r3, DCSRBAR_LAWAR@l + + stw r0, 0xc00(r7) /* LAWBARH0 */ + stw r0, 0xc04(r7) /* LAWBARL0 */ + sync + stw r3, 0xc08(r7) /* LAWAR0 */ + + /* Read back from LAWAR to ensure the update is complete. */ + lwz r3, 0xc08(r7) /* LAWAR0 */ + isync + + /* Create a TLB entry for DCSR at zero */ + + addi r9, r8, 1 + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r9, 16, MAS0_ESEL_MSK + lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h + ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l + li r6, 0 /* DCSR effective address */ + ori r2, r6, MAS2_I|MAS2_G + li r3, MAS3_SW|MAS3_SR + li r4, 0 + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r4 + isync + tlbwe + isync + msync + + /* enable the timebase */ +#define CTBENR 0xe2084 + li r3, 1 + addis r4, r7, CTBENR@ha + stw r3, CTBENR@l(r4) + lwz r3, CTBENR@l(r4) + twi 0,r3,0 + isync + + .macro erratum_set_ccsr offset value + addis r3, r7, \offset@ha + lis r4, \value@h + addi r3, r3, \offset@l + ori r4, r4, \value@l + bl erratum_set_value + .endm + + .macro erratum_set_dcsr offset value + addis r3, r6, \offset@ha + lis r4, \value@h + addi r3, r3, \offset@l + ori r4, r4, \value@l + bl erratum_set_value + .endm + + erratum_set_dcsr 0xb0e08 0xe0201800 + erratum_set_dcsr 0xb0e18 0xe0201800 + erratum_set_dcsr 0xb0e38 0xe0400000 + erratum_set_dcsr 0xb0008 0x00900000 + erratum_set_dcsr 0xb0e40 0xe00a0000 + erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY + erratum_set_ccsr 0x10f00 0x415e5000 + erratum_set_ccsr 0x11f00 0x415e5000 + + /* Make temp mapping uncacheable again, if it was initially */ + bl 2f +2: mflr r3 + tlbsx 0, r3 + mfspr r4, MAS2 + rlwimi r4, r15, 0, MAS2_I + rlwimi r4, r15, 0, MAS2_G + mtspr MAS2, r4 + isync + tlbwe + isync + msync + + /* Clear the cache */ + lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + sync + isync + mtspr SPRN_L1CSR1,r3 + isync +2: sync + mfspr r4,SPRN_L1CSR1 + and. r4,r4,r3 + bne 2b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + sync + isync + mtspr SPRN_L1CSR1,r3 + isync +2: sync + mfspr r4,SPRN_L1CSR1 + and. r4,r4,r3 + beq 2b + + /* Remove temporary mappings */ + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r9, 16, MAS0_ESEL_MSK + li r3, 0 + mtspr MAS0, r0 + mtspr MAS1, r3 + isync + tlbwe + isync + msync + + li r3, 0 + stw r3, 0xc08(r7) /* LAWAR0 */ + lwz r3, 0xc08(r7) + isync + + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r8, 16, MAS0_ESEL_MSK + li r3, 0 + mtspr MAS0, r0 + mtspr MAS1, r3 + isync + tlbwe + isync + msync + + b 9f + + /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ +erratum_set_value: + /* Lock two cache lines into I-Cache */ + sync + mfspr r11, SPRN_L1CSR1 + rlwinm r11, r11, 0, ~L1CSR1_ICUL + sync + isync + mtspr SPRN_L1CSR1, r11 + isync + + mflr r12 + bl 5f +5: mflr r5 + addi r5, r5, 2f - 5b + icbtls 0, 0, r5 + addi r5, r5, 64 + + sync + mfspr r11, SPRN_L1CSR1 +3: andi. r11, r11, L1CSR1_ICUL + bne 3b + + icbtls 0, 0, r5 + addi r5, r5, 64 + + sync + mfspr r11, SPRN_L1CSR1 +3: andi. r11, r11, L1CSR1_ICUL + bne 3b + + b 2f + .align 6 + /* Inside a locked cacheline, wait a while, write, then wait a while */ +2: sync + + mfspr r5, SPRN_TBRL + addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ +4: mfspr r5, SPRN_TBRL + subf. r5, r5, r11 + bgt 4b + + stw r4, 0(r3) + + mfspr r5, SPRN_TBRL + addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ +4: mfspr r5, SPRN_TBRL + subf. r5, r5, r11 + bgt 4b + + sync + + /* + * Fill out the rest of this cache line and the next with nops, + * to ensure that nothing outside the locked area will be + * fetched due to a branch. + */ + .rept 19 + nop + .endr + + sync + mfspr r11, SPRN_L1CSR1 + rlwinm r11, r11, 0, ~L1CSR1_ICUL + sync + isync + mtspr SPRN_L1CSR1, r11 + isync + + mtlr r12 + blr + +9: +#endif + create_init_ram_area: lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l @@ -855,18 +1149,12 @@ version_string: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r1,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l - + lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ li r0,0 - stwu r0,-4(r1) - stwu r0,-4(r1) /* Terminate call chain */ - - stwu r1,-8(r1) /* Save back chain and move SP */ - lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0,RESET_VECTOR@l - stwu r1,-8(r1) /* Save back chain and move SP */ - stw r0,+12(r1) /* Save return addr (underflow vect) */ + stw r0,0(r3) /* Terminate Back Chain */ + stw r0,+4(r3) /* NULL return address. */ + mr r1,r3 /* Transfer to SP(r1) */ GET_GOT bl cpu_init_early_f diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index cbc674211aa..78a8f926b38 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -57,8 +57,6 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1015, P1015, 1), - CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), @@ -71,7 +69,6 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2040, P2040, 4), CPU_TYPE_ENTRY(P2041, P2041, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), - CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3), CPU_TYPE_ENTRY(P4040, P4040, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), CPU_TYPE_ENTRY(P5010, P5010, 1), @@ -85,7 +82,39 @@ struct cpu_type cpu_type_list [] = { #endif }; -struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +u32 compute_ppc_cpumask(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, mask = 0; + + do { + int j; + cluster = in_be32(&gur->tp_cluster[i++].lower); + for (j = 0; j < 4; j++) { + u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; + u32 type = in_be32(&gur->tp_ityp[idx]); + + if (type & TP_ITYP_AV) { + if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) + mask |= 1 << count; + } + count++; + } + } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + + return mask; +} +#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +/* + * Before chassis genenration 2, the cpumask should be hard-coded. + * In case of cpu type unknown or cpumask unset, use 1 as fail save. + */ +#define compute_ppc_cpumask() 1 +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + +struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); struct cpu_type *identify_cpu(u32 ver) { @@ -113,6 +142,9 @@ u32 cpu_mask() return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> MPC8xxx_PICFRR_NCPU_SHIFT) + 1; + if (cpu->num_cores == 0) + return compute_ppc_cpumask(); + return cpu->mask; } @@ -120,13 +152,14 @@ u32 cpu_mask() * Return the number of cores on this SOC. */ int cpu_numcores() { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; - /* better to query feature reporting register than just assume 1 */ - if (cpu == &cpu_type_unknown) - return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> - MPC8xxx_PICFRR_NCPU_SHIFT) + 1; + /* + * Report # of cores in terms of the cpu_mask if we haven't + * figured out how many there are yet + */ + if (cpu->num_cores == 0) + return hweight32(cpu_mask()); return cpu->num_cores; } @@ -138,9 +171,7 @@ int cpu_numcores() { */ int is_core_valid(unsigned int core) { - struct cpu_type *cpu = gd->cpu; - - return !!((1 << core) & cpu->mask); + return !!((1 << core) & cpu_mask()); } int probecpu (void) @@ -156,6 +187,19 @@ int probecpu (void) return 0; } +/* Once in memory, compute mask & # cores once and save them off */ +int fixup_cpu(void) +{ + struct cpu_type *cpu = gd->cpu; + + if (cpu->num_cores == 0) { + cpu->mask = cpu_mask(); + cpu->num_cores = cpu_numcores(); + } + + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 2067d53ad28..2592873c9f0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -151,8 +151,19 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, if (dimm_params[dimm_number].n_ranks > 0) { go_config = 1; /* These fields only available in CS0_CONFIG */ - intlv_en = popts->memctl_interleaving; - intlv_ctl = popts->memctl_interleaving_mode; + if (!popts->memctl_interleaving) + break; + switch (popts->memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + intlv_en = popts->memctl_interleaving; + intlv_ctl = popts->memctl_interleaving_mode; + break; + default: + break; + } } break; case 1: @@ -302,29 +313,41 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency) { + /* Extended precharge to activate interval (tRP) */ + unsigned int ext_pretoact = 0; /* Extended Activate to precharge interval (tRAS) */ unsigned int ext_acttopre = 0; - unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */ - unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ - unsigned int cntl_adj = 0; /* Control Adjust */ - - /* If the tRAS > 19 MCLK, we use the ext mode */ - if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) - ext_acttopre = 1; - + /* Extended activate to read/write interval (tRCD) */ + unsigned int ext_acttorw = 0; + /* Extended refresh recovery time (tRFC) */ + unsigned int ext_refrec; + /* Extended MCAS latency from READ cmd */ + unsigned int ext_caslat = 0; + /* Extended last data to precharge interval (tWR) */ + unsigned int ext_wrrec = 0; + /* Control Adjust */ + unsigned int cntl_adj = 0; + + ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4; + ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4; + ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4; + ext_caslat = (2 * cas_latency - 1) >> 4; ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; - - /* If the CAS latency more than 8, use the ext mode */ - if (cas_latency > 8) - ext_caslat = 1; + /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ + ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) + + (popts->OTF_burst_chop_en ? 2 : 0)) >> 4; ddr->timing_cfg_3 = (0 - | ((ext_acttopre & 0x1) << 24) - | ((ext_refrec & 0xF) << 16) - | ((ext_caslat & 0x1) << 12) + | ((ext_pretoact & 0x1) << 28) + | ((ext_acttopre & 0x2) << 24) + | ((ext_acttorw & 0x1) << 22) + | ((ext_refrec & 0x1F) << 16) + | ((ext_caslat & 0x3) << 12) + | ((ext_wrrec & 0x1) << 8) | ((cntl_adj & 0x7) << 0) ); debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); @@ -386,15 +409,16 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, * we need set extend bit for it at * TIMING_CFG_3[EXT_CASLAT] */ - if (cas_latency > 8) - cas_latency -= 8; caslat_ctrl = 2 * cas_latency - 1; #endif refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); - wrrec_mclk = wrrec_table[wrrec_mclk - 1]; + if (wrrec_mclk > 16) + printf("Error: WRREC doesn't support more than 16 clocks\n"); + else + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; if (popts->OTF_burst_chop_en) wrrec_mclk += 2; @@ -825,7 +849,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, /* Mode Register - MR0 */ unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ - unsigned int wr; /* Write Recovery */ + unsigned int wr = 0; /* Write Recovery */ unsigned int dll_rst; /* DLL Reset */ unsigned int mode; /* Normal=0 or Test=1 */ unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ @@ -885,24 +909,37 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, dll_on = 1; wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; - wr = wr_table[wr_mclk - 5]; + if (wr_mclk <= 16) { + wr = wr_table[wr_mclk - 5]; + } else { + printf("Error: unsupported write recovery for mode register " + "wr_mclk = %d\n", wr_mclk); + } dll_rst = 0; /* dll no reset */ mode = 0; /* normal mode */ /* look up table to get the cas latency bits */ - if (cas_latency >= 5 && cas_latency <= 11) { - unsigned char cas_latency_table[7] = { + if (cas_latency >= 5 && cas_latency <= 16) { + unsigned char cas_latency_table[] = { 0x2, /* 5 clocks */ 0x4, /* 6 clocks */ 0x6, /* 7 clocks */ 0x8, /* 8 clocks */ 0xa, /* 9 clocks */ 0xc, /* 10 clocks */ - 0xe /* 11 clocks */ + 0xe, /* 11 clocks */ + 0x1, /* 12 clocks */ + 0x3, /* 13 clocks */ + 0x5, /* 14 clocks */ + 0x7, /* 15 clocks */ + 0x9, /* 16 clocks */ }; caslat = cas_latency_table[cas_latency - 5]; + } else { + printf("Error: unsupported cas latency for mode register\n"); } + bt = 0; /* Nibble sequential */ switch (popts->burst_length) { @@ -930,6 +967,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, | ((mode & 0x1) << 7) | (((caslat >> 1) & 0x7) << 4) | ((bt & 0x1) << 3) + | ((caslat & 1) << 2) | ((bl & 0x3) << 0) ); @@ -1399,73 +1437,37 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Chip Select Memory Bounds (CSn_BNDS) */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - unsigned long long ea = 0, sa = 0; + unsigned long long ea, sa; unsigned int cs_per_dimm = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; unsigned int dimm_number = i / cs_per_dimm; unsigned long long rank_density - = dimm_params[dimm_number].rank_density; + = dimm_params[dimm_number].rank_density >> dbw_cap_adj; - if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) || - ((i == 2) && (popts->ba_intlv_ctl & 0x04)) || - ((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) { - /* - * Don't set up boundaries for unused CS - * cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3 - * cs2 for cs0_cs1_cs2_cs3 - * cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3 - * But we need to set the ODT_RD_CFG and - * ODT_WR_CFG for CS1_CONFIG here. - */ - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - continue; - } if (dimm_params[dimm_number].n_ranks == 0) { debug("Skipping setup of CS%u " "because n_ranks on DIMM %u is 0\n", i, dimm_number); continue; } - if (popts->memctl_interleaving && popts->ba_intlv_ctl) { - /* - * This works superbank 2CS - * There are 2 or more memory controllers configured - * identically, memory is interleaved between them, - * and each controller uses rank interleaving within - * itself. Therefore the starting and ending address - * on each controller is twice the amount present on - * each controller. If any CS is not included in the - * interleaving, the memory on that CS is not accssible - * and the total memory size is reduced. The CS is also - * disabled. - */ - unsigned long long ctlr_density = 0; + if (popts->memctl_interleaving) { switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + break; case FSL_DDR_CS0_CS1: case FSL_DDR_CS0_CS1_AND_CS2_CS3: - ctlr_density = dimm_params[0].rank_density * 2; if (i > 1) cs_en = 0; break; case FSL_DDR_CS2_CS3: - ctlr_density = dimm_params[0].rank_density; + default: if (i > 0) cs_en = 0; break; - case FSL_DDR_CS0_CS1_CS2_CS3: - /* - * The four CS interleaving should have been verified by - * populate_memctl_options() - */ - ctlr_density = dimm_params[0].rank_density * 4; - break; - default: - break; } - ea = (CONFIG_NUM_DDR_CONTROLLERS * - (ctlr_density >> dbw_cap_adj)) - 1; - } - else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) { + sa = common_dimm->base_address; + ea = common_dimm->total_mem - 1; + } else if (!popts->memctl_interleaving) { /* * If memory interleaving between controllers is NOT * enabled, the starting address for each memory @@ -1477,49 +1479,40 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, */ switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: - /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS - * needs to be set. - */ sa = common_dimm->base_address; - ea = sa + (4 * (rank_density >> dbw_cap_adj))-1; + ea = common_dimm->total_mem - 1; break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: - /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS - * and CS2_CNDS need to be set. - */ - if ((i == 2) && (dimm_number == 0)) { + if ((i >= 2) && (dimm_number == 0)) { sa = dimm_params[dimm_number].base_address + - 2 * (rank_density >> dbw_cap_adj); - ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1; + 2 * rank_density; + ea = sa + 2 * rank_density - 1; } else { sa = dimm_params[dimm_number].base_address; - ea = sa + (2 * (rank_density >> - dbw_cap_adj)) - 1; + ea = sa + 2 * rank_density - 1; } break; case FSL_DDR_CS0_CS1: - /* CS0+CS1 interleaving, CS0_CNDS needs - * to be set - */ if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { sa = dimm_params[dimm_number].base_address; - ea = sa + (rank_density >> dbw_cap_adj) - 1; - sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); - ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + ea = sa + rank_density - 1; + if (i != 1) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; } else { sa = 0; ea = 0; } if (i == 0) - ea += (rank_density >> dbw_cap_adj); + ea += rank_density; break; case FSL_DDR_CS2_CS3: - /* CS2+CS3 interleaving*/ if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { sa = dimm_params[dimm_number].base_address; - ea = sa + (rank_density >> dbw_cap_adj) - 1; - sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); - ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); + ea = sa + rank_density - 1; + if (i != 3) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; } else { sa = 0; ea = 0; @@ -1528,38 +1521,18 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ea += (rank_density >> dbw_cap_adj); break; default: /* No bank(chip-select) interleaving */ + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } break; } } - else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) { - /* - * Only the rank on CS0 of each memory controller may - * be used if memory controller interleaving is used - * without rank interleaving within each memory - * controller. However, the ending address programmed - * into each CS0 must be the sum of the amount of - * memory in the two CS0 ranks. - */ - if (i == 0) { - ea = (2 * (rank_density >> dbw_cap_adj)) - 1; - } - - } - else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) { - /* - * No rank interleaving and no memory controller - * interleaving. - */ - sa = dimm_params[dimm_number].base_address; - ea = sa + (rank_density >> dbw_cap_adj) - 1; - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); - ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj); - } else { - sa = 0; - ea = 0; - } - } sa >>= 24; ea >>= 24; @@ -1574,7 +1547,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_csn_config(dimm_number, i, ddr, popts, dimm_params); set_csn_config_2(i, ddr); } else - printf("CS%d is disabled.\n", i); + debug("CS%d is disabled.\n", i); } /* @@ -1590,7 +1563,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_0(ddr, popts); #endif - set_timing_cfg_3(ddr, common_dimm, cas_latency); + set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); set_timing_cfg_2(ddr, popts, common_dimm, cas_latency, additive_latency); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index d0a546610ee..3e7c269e402 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * calculate the organization and timing parameter @@ -90,6 +90,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, { unsigned int retval; unsigned int mtb_ps; + int ftb_10th_ps; int i; if (spd->mem_type) { @@ -197,6 +198,14 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->mtb_ps = mtb_ps; /* + * FTB - fine timebase + * use 1/10th of ps as our unit to avoid floating point + * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps + */ + ftb_10th_ps = + ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); + pdimm->ftb_10th_ps = ftb_10th_ps; + /* * sdram minimum cycle time * we assume the MTB is 0.125ns * eg: @@ -204,7 +213,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * =12 MTB (1.5ns) ->DDR3-1333 * =10 MTB (1.25ns) ->DDR3-1600 */ - pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps; + pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps + + (spd->fine_tCK_min * ftb_10th_ps) / 10; /* * CAS latency supported @@ -222,7 +232,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tAA_ps = spd->tAA_min * mtb_ps; + pdimm->tAA_ps = spd->tAA_min * mtb_ps + + (spd->fine_tAA_min * ftb_10th_ps) / 10; /* * min write recovery time @@ -239,7 +250,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25) */ - pdimm->tRCD_ps = spd->tRCD_min * mtb_ps; + pdimm->tRCD_ps = spd->tRCD_min * mtb_ps + + (spd->fine_tRCD_min * ftb_10th_ps) / 10; /* * min row active to row active delay time @@ -257,7 +269,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1333H 108 MTB (13.5ns) * DDR3-1600H 90 MTB (11.25ns) */ - pdimm->tRP_ps = spd->tRP_min * mtb_ps; + pdimm->tRP_ps = spd->tRP_min * mtb_ps + + (spd->fine_tRP_min * ftb_10th_ps) / 10; /* min active to precharge delay time * eg: tRAS_min = @@ -277,7 +290,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, * DDR3-1600H 370 MTB (46.25ns) */ pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb) - * mtb_ps; + * mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10; /* * min refresh recovery delay time * eg: tRFC_min = diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index 5b724371f60..f59d1051bfe 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -1047,7 +1047,7 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) /* General Section: Bytes 0-59 */ -#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, y); +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); #define PRINT_NNXXS(n0, n1, x0, x1, s) \ printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); @@ -1121,11 +1121,21 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) "therm_sensor SDRAM Thermal Sensor"); PRINT_NXS(33, spd->device_type, "device_type SDRAM Device Type"); - - printf("%-3d-%3d: ", 34, 59); /* Reserved, General Section */ - - for (i = 34; i <= 59; i++) - printf("%02x ", spd->res_34_59[i - 34]); + PRINT_NXS(34, spd->fine_tCK_min, + "fine_tCK_min Fine offset for tCKmin"); + PRINT_NXS(35, spd->fine_tAA_min, + "fine_tAA_min Fine offset for tAAmin"); + PRINT_NXS(36, spd->fine_tRCD_min, + "fine_tRCD_min Fine offset for tRCDmin"); + PRINT_NXS(37, spd->fine_tRP_min, + "fine_tRP_min Fine offset for tRPmin"); + PRINT_NXS(38, spd->fine_tRC_min, + "fine_tRC_min Fine offset for tRCmin"); + + printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ + + for (i = 39; i <= 59; i++) + printf("%02x ", spd->res_39_59[i - 39]); puts("\n"); @@ -1388,7 +1398,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) * No need to worry for buffer overflow here in * this function; readline() maxes out at CFG_CBSIZE */ - readline_into_buffer(prompt, buffer); + readline_into_buffer(prompt, buffer, 0); argc = parse_line(buffer, argv); if (argc == 0) continue; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 20c7db03ede..03a784cd479 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -27,8 +27,10 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, /* compute the common CAS latency supported between slots */ tmp = dimm_params[0].caslat_X; - for (i = 1; i < number_of_dimms; i++) - tmp &= dimm_params[i].caslat_X; + for (i = 1; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) + tmp &= dimm_params[i].caslat_X; + } common_caslat = tmp; /* compute the max tAAmin tCKmin between slots */ @@ -491,5 +493,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, */ outpdimm->additive_latency = additive_latency; + debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps); + debug("tRCD_ps = %u\n", outpdimm->tRCD_ps); + debug("tRP_ps = %u\n", outpdimm->tRP_ps); + debug("tRAS_ps = %u\n", outpdimm->tRAS_ps); + debug("tWR_ps = %u\n", outpdimm->tWR_ps); + debug("tWTR_ps = %u\n", outpdimm->tWTR_ps); + debug("tRFC_ps = %u\n", outpdimm->tRFC_ps); + debug("tRRD_ps = %u\n", outpdimm->tRRD_ps); + debug("tRC_ps = %u\n", outpdimm->tRC_ps); + return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index c2a03e334cf..b47268c20ea 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -15,13 +15,15 @@ #include <common.h> #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> #include "ddr.h" -extern void fsl_ddr_set_lawbar( +void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_set_intl3r(const unsigned int granule_size); /* processor specific function */ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, @@ -51,6 +53,22 @@ u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ }; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ + [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ +}; + #endif static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) @@ -156,12 +174,12 @@ const char * step_to_string(unsigned int step) { return step_string_tbl[s]; } -int step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[], - unsigned int *all_memctl_interleaving, - unsigned int *all_ctlr_rank_interleaving) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]) { int i, j; + unsigned long long total_mem, current_mem_base, total_ctlr_mem; + unsigned long long rank_density, ctlr_density = 0; /* * If a reduced data width is requested, but the SPD @@ -220,86 +238,108 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, "specified controller %u\n", i); return 1; } + debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); } - j = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - if (pinfo->memctl_opts[i].memctl_interleaving) - j++; - /* - * Not support less than all memory controllers interleaving - * if more than two controllers - */ - if (j == CONFIG_NUM_DDR_CONTROLLERS) - *all_memctl_interleaving = 1; - - /* Check that all controllers are rank interleaving. */ - j = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - if (pinfo->memctl_opts[i].ba_intlv_ctl) - j++; - /* - * All memory controllers must be populated to qualify for - * all controller rank interleaving - */ - if (j == CONFIG_NUM_DDR_CONTROLLERS) - *all_ctlr_rank_interleaving = 1; - - if (*all_memctl_interleaving) { - unsigned long long addr, total_mem_per_ctlr = 0; - /* - * If interleaving between memory controllers, - * make each controller start at a base address - * of 0. - * - * Also, if bank interleaving (chip select - * interleaving) is enabled on each memory - * controller, CS0 needs to be programmed to - * cover the entire memory range on that memory - * controller - * - * Bank interleaving also implies that each - * addressed chip select is identical in size. - */ - + current_mem_base = 0ull; + total_mem = 0; + if (pinfo->memctl_opts[0].memctl_interleaving) { + rank_density = pinfo->dimm_params[0][0].rank_density >> + dbw_cap_adj[0]; + switch (pinfo->memctl_opts[0].ba_intlv_ctl & + FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + ctlr_density = 4 * rank_density; + break; + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + ctlr_density = 2 * rank_density; + break; + case FSL_DDR_CS2_CS3: + default: + ctlr_density = rank_density; + break; + } + debug("rank density is 0x%llx, ctlr density is 0x%llx\n", + rank_density, ctlr_density); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - addr = 0; - pinfo->common_timing_params[i].base_address = 0ull; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned long long cap - = pinfo->dimm_params[i][j].capacity; - - pinfo->dimm_params[i][j].base_address = addr; - addr += cap >> dbw_cap_adj[i]; - total_mem_per_ctlr += cap >> dbw_cap_adj[i]; + if (pinfo->memctl_opts[i].memctl_interleaving) { + switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + total_ctlr_mem = 2 * ctlr_density; + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + total_ctlr_mem = 3 * ctlr_density; + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + total_ctlr_mem = 4 * ctlr_density; + break; + default: + panic("Unknown interleaving mode"); + } + pinfo->common_timing_params[i].base_address = + current_mem_base; + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem = current_mem_base + total_ctlr_mem; + debug("ctrl %d base 0x%llx\n", i, current_mem_base); + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + } else { + /* when 3rd controller not interleaved */ + current_mem_base = total_mem; + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned long long cap = + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; } } - pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr; } else { /* * Simple linear assignment if memory * controllers are not interleaved. */ - unsigned long long cur_memsize = 0; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - u64 total_mem_per_ctlr = 0; + total_ctlr_mem = 0; pinfo->common_timing_params[i].base_address = - cur_memsize; + current_mem_base; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { /* Compute DIMM base addresses. */ unsigned long long cap = - pinfo->dimm_params[i][j].capacity; + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; pinfo->dimm_params[i][j].base_address = - cur_memsize; - cur_memsize += cap >> dbw_cap_adj[i]; - total_mem_per_ctlr += cap >> dbw_cap_adj[i]; + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); pinfo->common_timing_params[i].total_mem = - total_mem_per_ctlr; + total_ctlr_mem; + total_mem += total_ctlr_mem; } } + debug("Total mem by %s is 0x%llx\n", __func__, total_mem); - return 0; + return total_mem; } unsigned long long @@ -307,8 +347,6 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only) { unsigned int i, j; - unsigned int all_controllers_memctl_interleaving = 0; - unsigned int all_controllers_rank_interleaving = 0; unsigned long long total_mem = 0; fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; @@ -345,9 +383,10 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, retval = compute_dimm_parameters(spd, pdimm, i); #ifdef CONFIG_SYS_DDR_RAW_TIMING - if (retval != 0) { - printf("SPD error! Trying fallback to " - "raw timing calculation\n"); + if (!i && !j && retval) { + printf("SPD error on controller %d! " + "Trying fallback to raw timing " + "calculation\n", i); fsl_ddr_get_dimm_params(pdimm, i, j); } #else @@ -407,17 +446,14 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); } - check_interleaving_options(pinfo); case STEP_ASSIGN_ADDRESSES: /* STEP 5: Assign addresses to chip selects */ - step_assign_addresses(pinfo, - dbw_capacity_adjust, - &all_controllers_memctl_interleaving, - &all_controllers_rank_interleaving); + check_interleaving_options(pinfo); + total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); case STEP_COMPUTE_REGS: /* STEP 6: compute controller register values */ - debug("FSL Memory ctrl cg register computation\n"); + debug("FSL Memory ctrl register computation\n"); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { if (timing_params[i].ndimms_present == 0) { memset(&ddr_reg[i], 0, @@ -437,21 +473,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, break; } - /* Compute the total amount of memory. */ - - /* - * If bank interleaving but NOT memory controller interleaving - * CS_BNDS describe the quantity of memory on each memory - * controller, so the total is the sum across. - */ - if (!all_controllers_memctl_interleaving - && all_controllers_rank_interleaving) { - total_mem = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - total_mem += timing_params[i].total_mem; - } - - } else { + { /* * Compute the amount of memory available just by * looking for the highest valid CSn_BNDS value. @@ -489,7 +511,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, phys_size_t fsl_ddr_sdram(void) { unsigned int i; - unsigned int memctl_interleaved; + unsigned int law_memctl = LAW_TRGT_IF_DDR_1; unsigned long long total_memory; fsl_ddr_info_t info; @@ -504,34 +526,6 @@ phys_size_t fsl_ddr_sdram(void) #endif total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); - /* Check for memory controller interleaving. */ - memctl_interleaved = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - memctl_interleaved += - info.memctl_opts[i].memctl_interleaving; - } - - if (memctl_interleaved) { - if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) { - debug("memctl interleaving\n"); - /* - * Change the meaning of memctl_interleaved - * to be "boolean". - */ - memctl_interleaved = 1; - } else { - printf("Warning: memctl interleaving not " - "properly configured on all controllers\n"); - memctl_interleaved = 0; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - info.memctl_opts[i].memctl_interleaving = 0; - debug("Recomputing with memctl_interleaving off.\n"); - total_memory = fsl_ddr_compute(&info, - STEP_ASSIGN_ADDRESSES, - 0); - } - } - /* Program configuration registers. */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { debug("Programming controller %u\n", i); @@ -544,24 +538,69 @@ phys_size_t fsl_ddr_sdram(void) fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i); } - if (memctl_interleaved) { - const unsigned int ctrl_num = 0; - - /* Only set LAWBAR1 if memory controller interleaving is on. */ - fsl_ddr_set_lawbar(&info.common_timing_params[0], - memctl_interleaved, ctrl_num); - } else { - /* - * Memory controller interleaving is NOT on; - * set each lawbar individually. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + /* program LAWs */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (info.memctl_opts[i].memctl_interleaving) { + switch (info.memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + if (i == 0) { + law_memctl = LAW_TRGT_IF_DDR_INTRLV; + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } else if (i == 2) { + law_memctl = LAW_TRGT_IF_DDR_INTLV_34; + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_123; + if (i == 0) { + fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode); + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; + if (i == 0) + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + /* place holder for future 4-way interleaving */ + break; + default: + break; + } + } else { + switch (i) { + case 0: + law_memctl = LAW_TRGT_IF_DDR_1; + break; + case 1: + law_memctl = LAW_TRGT_IF_DDR_2; + break; + case 2: + law_memctl = LAW_TRGT_IF_DDR_3; + break; + case 3: + law_memctl = LAW_TRGT_IF_DDR_4; + break; + default: + break; + } fsl_ddr_set_lawbar(&info.common_timing_params[i], - 0, i); + law_memctl, i); } } - debug("total_memory = %llu\n", total_memory); + debug("total_memory by %s = %llu\n", __func__, total_memory); #if !defined(CONFIG_PHYS_64BIT) /* Check for 4G or more. Bad. */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 00ec57be1ff..13e48252742 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -19,7 +19,6 @@ * This is pretty fragile on both the use of stack and if the buffer is big * enough. However we will get a warning from getenv_f for the later. */ -#define HWCONFIG_BUFFER_SIZE 128 /* Board-specific functions defined in each board's ddr.c */ extern void fsl_ddr_board_options(memctl_options_t *popts, @@ -790,46 +789,97 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * should be a subset of the requested configuration. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) { - if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0 for controller %d. Because only" - " rank on CS0 and ranks chip-select interleaved with CS0" - " are controller interleaved, force non memory " - "controller interleaving\n", ctrl_num); - popts->memctl_interleaving = 0; - } else { - popts->memctl_interleaving = 1; - /* - * test null first. if CONFIG_HWCONFIG is not defined - * hwconfig_arg_cmp returns non-zero - */ - if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "null", buf)) { - popts->memctl_interleaving = 0; - debug("memory controller interleaving disabled.\n"); - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "cacheline", buf)) - popts->memctl_interleaving_mode = - FSL_DDR_CACHE_LINE_INTERLEAVING; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "page", buf)) - popts->memctl_interleaving_mode = - FSL_DDR_PAGE_INTERLEAVING; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "bank", buf)) - popts->memctl_interleaving_mode = - FSL_DDR_BANK_INTERLEAVING; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "superbank", buf)) - popts->memctl_interleaving_mode = - FSL_DDR_SUPERBANK_INTERLEAVING; - else { - popts->memctl_interleaving = 0; - printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); - } - } + if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) + goto done; + + if (pdimm[0].n_ranks == 0) { + printf("There is no rank on CS0 for controller %d.\n", ctrl_num); + popts->memctl_interleaving = 0; + goto done; + } + popts->memctl_interleaving = 1; + /* + * test null first. if CONFIG_HWCONFIG is not defined + * hwconfig_arg_cmp returns non-zero + */ + if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "null", buf)) { + popts->memctl_interleaving = 0; + debug("memory controller interleaving disabled.\n"); + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "cacheline", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "page", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_PAGE_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "bank", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_BANK_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "superbank", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_SUPERBANK_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; +#if (CONFIG_NUM_DDR_CONTROLLERS == 3) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_1KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_1KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_4KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_4KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_8KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_8KB_INTERLEAVING; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 4) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_1KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_1KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_4KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_4KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_8KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_8KB_INTERLEAVING; +#endif + } else { + popts->memctl_interleaving = 0; + printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); } +done: #endif if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { @@ -859,20 +909,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1+CS2+CS3 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } if (pdimm[0].capacity != pdimm[1].capacity) { popts->ba_intlv_ctl = 0; printf("Not identical DIMM size for " "CS0+CS1+CS2+CS3 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } #endif break; @@ -881,7 +931,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " "CS0+CS1 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } break; case FSL_DDR_CS2_CS3: @@ -889,13 +939,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, if (pdimm[0].n_ranks < 4) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, force non-interleaving!\n", ctrl_num); + "on controller %d, interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) if (pdimm[1].n_ranks < 2) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, force non-interleaving!\n", ctrl_num); + "on controller %d, interleaving disabled!\n", ctrl_num); } #endif break; @@ -905,14 +955,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(CS) for CS0+CS1 and " "CS2+CS3 on controller %d, " - "force non-interleaving!\n", ctrl_num); + "interleaving disabled!\n", ctrl_num); } #endif break; @@ -954,33 +1004,73 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, void check_interleaving_options(fsl_ddr_info_t *pinfo) { - int i, j, check_n_ranks, intlv_fixed = 0; + int i, j, k, check_n_ranks, intlv_invalid = 0; + unsigned int check_intlv, check_n_row_addr, check_n_col_addr; unsigned long long check_rank_density; + struct dimm_params_s *dimm; /* * Check if all controllers are configured for memory * controller interleaving. Identical dimms are recommended. At least - * the size should be checked. + * the size, row and col address should be checked. */ j = 0; check_n_ranks = pinfo->dimm_params[0][0].n_ranks; check_rank_density = pinfo->dimm_params[0][0].rank_density; + check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; + check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; + check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if ((pinfo->memctl_opts[i].memctl_interleaving) && \ - (check_rank_density == pinfo->dimm_params[i][0].rank_density) && \ - (check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) { + dimm = &pinfo->dimm_params[i][0]; + if (!pinfo->memctl_opts[i].memctl_interleaving) { + continue; + } else if (((check_rank_density != dimm->rank_density) || + (check_n_ranks != dimm->n_ranks) || + (check_n_row_addr != dimm->n_row_addr) || + (check_n_col_addr != dimm->n_col_addr) || + (check_intlv != + pinfo->memctl_opts[i].memctl_interleaving_mode))){ + intlv_invalid = 1; + break; + } else { j++; } + } - if (j != CONFIG_NUM_DDR_CONTROLLERS) { + if (intlv_invalid) { for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - if (pinfo->memctl_opts[i].memctl_interleaving) { + pinfo->memctl_opts[i].memctl_interleaving = 0; + printf("Not all DIMMs are identical. " + "Memory controller interleaving disabled.\n"); + } else { + switch (check_intlv) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + if (3 == CONFIG_NUM_DDR_CONTROLLERS) + k = 2; + else + k = CONFIG_NUM_DDR_CONTROLLERS; + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + default: + k = CONFIG_NUM_DDR_CONTROLLERS; + break; + } + debug("%d of %d controllers are interleaving.\n", j, k); + if (j != k) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) pinfo->memctl_opts[i].memctl_interleaving = 0; - intlv_fixed = 1; - } - if (intlv_fixed) - printf("Not all DIMMs are identical in size. " - "Memory controller interleaving disabled.\n"); + printf("Not all controllers have compatible " + "interleaving mode. All disabled.\n"); + } } + debug("Checking interleaving options completed\n"); } int fsl_use_spd(void) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index eb6a17a8503..664ad09298f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -79,7 +79,7 @@ unsigned int mclk_to_picos(unsigned int mclk) void __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, + unsigned int law_memctl, unsigned int ctrl_num) { unsigned long long base = memctl_common_params->base_address; @@ -98,28 +98,13 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, if ((base + size) >= CONFIG_MAX_MEM_MAPPED) size = CONFIG_MAX_MEM_MAPPED - base; #endif - - if (ctrl_num == 0) { - /* - * Set up LAW for DDR controller 1 space. - */ - unsigned int lawbar1_target_id = memctl_interleaved - ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1; - - if (set_ddr_laws(base, size, lawbar1_target_id) < 0) { - printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__, - memctl_interleaved); - return ; - } - } else if (ctrl_num == 1) { - if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) { - printf("%s: ERROR (ctrl #1)\n", __func__); - return ; - } - } else { - printf("%s: unexpected DDR controller number (%u)\n", __func__, - ctrl_num); + if (set_ddr_laws(base, size, law_memctl) < 0) { + printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, + law_memctl); + return ; } + debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", + base, size, law_memctl); } __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void @@ -127,6 +112,15 @@ fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_set_intl3r(const unsigned int granule_size) +{ +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + *mcintl3r = 0x80000000 | (granule_size & 0x1f); + debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); +#endif +} + void board_add_ram_info(int use_default) { #if defined(CONFIG_MPC83xx) @@ -137,6 +131,9 @@ void board_add_ram_info(int use_default) #elif defined(CONFIG_MPC86xx) ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR); #endif +#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); +#endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) uint32_t cs0_config = in_be32(&ddr->cs0_config); #endif @@ -180,7 +177,29 @@ void board_add_ram_info(int use_default) else puts(", ECC off)"); -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if (CONFIG_NUM_DDR_CONTROLLERS == 3) +#ifdef CONFIG_E6500 + if (*mcintl3r & 0x80000000) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + switch (*mcintl3r & 0x1f) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + puts("3-way 1KB"); + break; + case FSL_DDR_3WAY_4KB_INTERLEAVING: + puts("3-way 4KB"); + break; + case FSL_DDR_3WAY_8KB_INTERLEAVING: + puts("3-way 8KB"); + break; + default: + puts("3-way UNKNOWN"); + break; + } + } +#endif +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) if (cs0_config & 0x20000000) { puts("\n"); puts(" DDR Controller Interleaving Mode: "); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 09810be7d30..32ab0509622 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -62,8 +62,9 @@ void ft_fixup_num_cores(void *blob) { off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + u32 phys_cpu_id = thread_to_core(*reg); - if (!is_core_valid(*reg) || is_core_disabled(*reg)) { + if (!is_core_valid(phys_cpu_id) || is_core_disabled(phys_cpu_id)) { int ph = fdt_get_phandle(blob, off); /* Delete the cpu node once there are no cpu handles */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 66824960d3f..56b319f5d4b 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -44,12 +44,18 @@ void init_early_memctl_regs(void) set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); #if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_SYS_CSPR0_EXT + set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); #endif #endif +#ifdef CONFIG_SYS_CSPR1_EXT + set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -61,6 +67,9 @@ void init_early_memctl_regs(void) set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); #endif +#ifdef CONFIG_SYS_CSPR2_EXT + set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -72,6 +81,9 @@ void init_early_memctl_regs(void) set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); #endif +#ifdef CONFIG_SYS_CSPR3_EXT + set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c7f394972bf..0cb65b32e48 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -95,126 +95,92 @@ void srio_init(void) } } -#ifdef CONFIG_SRIOBOOT_MASTER -void srio_boot_master(void) +#ifdef CONFIG_FSL_CORENET +void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; /* set port accept-all */ - out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + out_be32((void *)&srio->impl.port[port - 1].ptaacr, SRIO_PORT_ACCEPT_ALL); - debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", - CONFIG_SRIOBOOT_MASTER_PORT); + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port); /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, - (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, - CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); - /* configure inbound window for slave's ucode */ - debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + /* configure inbound window for slave's ucode and ENV */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, - (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, - CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar, - CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar, - CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, - SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); - - /* configure inbound window for slave's ENV */ - debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; " - "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", - CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, - CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, - CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar, - CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar, - CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar, + (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); + out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); + | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); } -#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF -void srio_boot_master_release_slave(void) +void srio_boot_master_release_slave(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; u32 escsr; debug("SRIOBOOT - MASTER: " "Check the port status and release slave core ...\n"); - escsr = in_be32((void *)&srio->lp_serial - .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr); + escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr); if (escsr & 0x2) { if (escsr & 0x10100) { debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", - CONFIG_SRIOBOOT_MASTER_PORT); + port); } else { debug("SRIOBOOT - MASTER: " - "Port [ %d ] is ready, now release slave's core ...\n", - CONFIG_SRIOBOOT_MASTER_PORT); + "Port [ %d ] is ready, now release slave's core ...\n", + port); /* * configure outbound window * with maintenance attribute to set slave's LCSBA1CSR */ - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowtar, 0); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowtear, 0); - if (CONFIG_SRIOBOOT_MASTER_PORT) - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + if (port - 1) + out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, CONFIG_SYS_SRIO2_MEM_PHYS >> 12); else - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, CONFIG_SYS_SRIO1_MEM_PHYS >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowar, SRIO_OB_ATMU_AR_MAINT | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); @@ -223,27 +189,22 @@ void srio_boot_master_release_slave(void) * configure outbound window * with R/W attribute to set slave's BRR */ - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowtar, SRIO_LCSBA1CSR >> 9); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowtear, 0); - if (CONFIG_SRIOBOOT_MASTER_PORT) - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + if (port - 1) + out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, (CONFIG_SYS_SRIO2_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); else - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, (CONFIG_SYS_SRIO1_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); - out_be32((void *)&srio->atmu - .port[CONFIG_SRIOBOOT_MASTER_PORT] + out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowar, SRIO_OB_ATMU_AR_RW | atmu_size_mask(SRIO_RW_WIN_SIZE)); @@ -252,7 +213,7 @@ void srio_boot_master_release_slave(void) * Set the LCSBA1CSR register in slave * by the maint-outbound window */ - if (CONFIG_SRIOBOOT_MASTER_PORT) { + if (port - 1) { out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); @@ -266,8 +227,8 @@ void srio_boot_master_release_slave(void) */ out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, - CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, + CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); } else { out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, @@ -282,15 +243,13 @@ void srio_boot_master_release_slave(void) */ out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, - CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, + CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); } debug("SRIOBOOT - MASTER: " "Release slave successfully! Now the slave should start up!\n"); } } else - debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", - CONFIG_SRIOBOOT_MASTER_PORT); + debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port); } #endif -#endif diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index d1386369395..67cea01aae8 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -29,6 +29,10 @@ #include <asm/config_mpc86xx.h> #endif +#ifndef HWCONFIG_BUFFER_SIZE + #define HWCONFIG_BUFFER_SIZE 256 +#endif + /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) # ifndef CONFIG_HARD_SPI diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b6c44bb11d1..aa27741a921 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -37,6 +37,7 @@ #if defined(CONFIG_MPC8536) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -54,12 +55,14 @@ #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 @@ -113,6 +116,7 @@ #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 @@ -191,33 +195,6 @@ #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -/* P1015 is single core version of P1024 */ -#elif defined(CONFIG_P1015) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 - -/* P1016 is single core version of P1025 */ -#elif defined(CONFIG_P1016) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_LAWS 12 -#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 -#define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM -#define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 - /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) #define CONFIG_MAX_CPUS 1 @@ -333,30 +310,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#elif defined(CONFIG_PPC_P2040) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P2041) +#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -380,6 +334,10 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_ERRATUM_A004510 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 +#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -399,47 +357,18 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_ERRATUM_A004510 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 +#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 -#elif defined(CONFIG_PPC_P3060) -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P4040) -#define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P4080) +#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -474,32 +403,11 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004510 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 +#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 -/* P5010 is single core version of P5020 */ -#elif defined(CONFIG_PPC_P5010) -#define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 - -#elif defined(CONFIG_PPC_P5020) +#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -521,6 +429,9 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_ERRATUM_A004510 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index 982b8094625..ffe4db8b8aa 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -43,6 +43,7 @@ typedef struct dimm_params_s { /* DIMM timing parameters */ unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ + unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 93639ba8516..e271342f089 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -76,6 +76,13 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_PAGE_INTERLEAVING 0x1 #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ @@ -88,6 +95,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index 7d95eb4416a..ba41b73cc03 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -783,12 +783,16 @@ extern void init_early_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) +#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) +#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ @@ -909,22 +913,24 @@ struct fsl_ifc_gpcm { */ struct fsl_ifc { u32 ifc_rev; - u32 res1[0x3]; + u32 res1[0x2]; struct { + u32 cspr_ext; u32 cspr; - u32 res2[0x2]; + u32 res2; } cspr_cs[FSL_IFC_BANK_COUNT]; - u32 res3[0x18]; + u32 res3[0x19]; struct { u32 amask; u32 res4[0x2]; } amask_cs[FSL_IFC_BANK_COUNT]; - u32 res5[0x18]; + u32 res5[0x17]; struct { + u32 csor_ext; u32 csor; - u32 res6[0x2]; + u32 res6; } csor_cs[FSL_IFC_BANK_COUNT]; - u32 res7[0x18]; + u32 res7[0x19]; struct { u32 ftim[4]; u32 res8[0x8]; diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 13caffd96e2..f9cec8ea441 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -60,14 +60,19 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_1 = 0x10, LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ + LAW_TRGT_IF_DDR_3 = 0x12, + LAW_TRGT_IF_DDR_4 = 0x13, LAW_TRGT_IF_DDR_INTRLV = 0x14, - + LAW_TRGT_IF_DDR_INTLV_34 = 0x15, + LAW_TRGT_IF_DDR_INTLV_123 = 0x17, + LAW_TRGT_IF_DDR_INTLV_1234 = 0x16, LAW_TRGT_IF_BMAN = 0x18, LAW_TRGT_IF_DCSR = 0x1d, LAW_TRGT_IF_LBC = 0x1f, LAW_TRGT_IF_QMAN = 0x3c, }; #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #else enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, @@ -86,6 +91,12 @@ enum law_trgt_if { LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ + /* place holder for 3-way and 4-way interleaving */ + LAW_TRGT_IF_DDR_3, + LAW_TRGT_IF_DDR_4, + LAW_TRGT_IF_DDR_INTLV_34, + LAW_TRGT_IF_DDR_INTLV_123, + LAW_TRGT_IF_DDR_INTLV_1234, }; #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 0f31af1db32..22525f11561 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -41,6 +41,7 @@ enum srds_prtcl { SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM2_DTSEC5, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index a905a266c4d..dfd8e08f3ed 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -55,10 +55,8 @@ enum atmu_size { #define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) extern void srio_init(void); -#ifdef CONFIG_SRIOBOOT_MASTER -extern void srio_boot_master(void); -#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF -extern void srio_boot_master_release_slave(void); -#endif +#ifdef CONFIG_FSL_CORENET +extern void srio_boot_master(int port); +extern void srio_boot_master_release_slave(int port); #endif #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 53d563ed0a0..7de33a7dded 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1729,6 +1729,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 +#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 #define FSL_CORENET_NUM_DEVDISR 2 u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ @@ -1758,13 +1759,14 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ -#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060) +#ifdef CONFIG_PPC_P4080 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ @@ -1772,7 +1774,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif -#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \ +#if defined(CONFIG_PPC_P2041) \ || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 @@ -1836,7 +1838,13 @@ typedef struct ccsr_gur { u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ u32 dcsrcr; /* DCSR Control register */ - u8 res32[1784]; + u8 res31a[56]; + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[16]; /* Core Cluster n Topology Register */ + u8 res32[1344]; u32 pmuxcr; /* Pin multiplexing control */ u8 res33[60]; u32 iovselsr; /* I/O voltage selection status */ @@ -1849,6 +1857,18 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_OTHER 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ + #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 #define FSL_CORENET_DCSR_SZ_4M 0x0 #define FSL_CORENET_DCSR_SZ_1G 0x3 @@ -1890,6 +1910,73 @@ typedef struct ccsr_clk { u8 res15[0x3dc]; } ccsr_clk_t; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +typedef struct ccsr_rcpm { + u8 res_00[12]; + u32 tph10sr0; /* Thread PH10 Status Register */ + u8 res_10[12]; + u32 tph10setr0; /* Thread PH10 Set Control Register */ + u8 res_20[12]; + u32 tph10clrr0; /* Thread PH10 Clear Control Register */ + u8 res_30[12]; + u32 tph10psr0; /* Thread PH10 Previous Status Register */ + u8 res_40[12]; + u32 twaitsr0; /* Thread Wait Status Register */ + u8 res_50[96]; + u32 pcph15sr; /* Physical Core PH15 Status Register */ + u32 pcph15setr; /* Physical Core PH15 Set Control Register */ + u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ + u32 pcph15psr; /* Physical Core PH15 Prev Status Register */ + u8 res_c0[16]; + u32 pcph20sr; /* Physical Core PH20 Status Register */ + u32 pcph20setr; /* Physical Core PH20 Set Control Register */ + u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ + u32 pcph20psr; /* Physical Core PH20 Prev Status Register */ + u32 pcpw20sr; /* Physical Core PW20 Status Register */ + u8 res_e0[12]; + u32 pcph30sr; /* Physical Core PH30 Status Register */ + u32 pcph30setr; /* Physical Core PH30 Set Control Register */ + u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ + u32 pcph30psr; /* Physical Core PH30 Prev Status Register */ + u8 res_100[32]; + u32 ippwrgatecr; /* IP Power Gating Control Register */ + u8 res_124[12]; + u32 powmgtcsr; /* Power Management Control & Status Reg */ + u8 res_134[12]; + u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ + u8 res_150[12]; + u32 tpmimr0; /* Thread PM Interrupt Mask Reg */ + u8 res_160[12]; + u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ + u8 res_170[12]; + u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ + u8 res_180[12]; + u32 tpmnmimr0; /* Thread PM NMI Mask Reg */ + u8 res_190[12]; + u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ + u32 pctbenr; /* Physical Core Time Base Enable Reg */ + u32 pctbclkselr; /* Physical Core Time Base Clock Select */ + u32 tbclkdivr; /* Time Base Clock Divider Register */ + u8 res_1ac[4]; + u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ + u32 clpcl10sr; /* Cluster PCL10 Status Register */ + u32 clpcl10setr; /* Cluster PCL30 Set Control Register */ + u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ + u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ + u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ + u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ + u32 cdpwroksetr; /* Core Domain Power OK Set Register */ + u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ + u32 cdpwrensr; /* Core Domain Power Enable Status Register */ + u32 cddslsr; /* Core Domain Deep Sleep Status Register */ + u8 res_1e8[8]; + u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ + u8 res_300[3568]; +} ccsr_rcpm_t; + +#define ctbenrl pctbenr + +#else typedef struct ccsr_rcpm { u8 res1[4]; u32 cdozsrl; /* Core Doze Status */ @@ -1926,6 +2013,7 @@ typedef struct ccsr_rcpm { u32 ctbhltcrl; /* Core Time Base Halt Control */ u8 res18[0xf68]; } ccsr_rcpm_t; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else typedef struct ccsr_gur { @@ -2259,8 +2347,7 @@ typedef struct ccsr_gur { u8 res11a[76]; par_io_t qe_par_io[7]; u8 res11b[1600]; -#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) u8 res11a[12]; u32 iovselsr; u8 res11b[60]; @@ -2534,6 +2621,7 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 @@ -2544,6 +2632,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 +#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 @@ -2652,6 +2741,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) #define CONFIG_SYS_IFC_ADDR \ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index ec0bfaee991..9e208618d94 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -162,7 +162,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) * is actually performed (i.e. the data has come back) before we start * executing any following instructions. */ -static inline u8 in_8(const volatile unsigned char __iomem *addr) +extern inline u8 in_8(const volatile unsigned char __iomem *addr) { u8 ret; @@ -173,7 +173,7 @@ static inline u8 in_8(const volatile unsigned char __iomem *addr) return ret; } -static inline void out_8(volatile unsigned char __iomem *addr, u8 val) +extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) { __asm__ __volatile__("sync;\n" "stb%U0%X0 %1,%0;\n" @@ -181,7 +181,7 @@ static inline void out_8(volatile unsigned char __iomem *addr, u8 val) : "r" (val)); } -static inline u16 in_le16(const volatile unsigned short __iomem *addr) +extern inline u16 in_le16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -192,7 +192,7 @@ static inline u16 in_le16(const volatile unsigned short __iomem *addr) return ret; } -static inline u16 in_be16(const volatile unsigned short __iomem *addr) +extern inline u16 in_be16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -202,18 +202,18 @@ static inline u16 in_be16(const volatile unsigned short __iomem *addr) return ret; } -static inline void out_le16(volatile unsigned short __iomem *addr, u16 val) +extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -static inline void out_be16(volatile unsigned short __iomem *addr, u16 val) +extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } -static inline u32 in_le32(const volatile unsigned __iomem *addr) +extern inline u32 in_le32(const volatile unsigned __iomem *addr) { u32 ret; @@ -224,7 +224,7 @@ static inline u32 in_le32(const volatile unsigned __iomem *addr) return ret; } -static inline u32 in_be32(const volatile unsigned __iomem *addr) +extern inline u32 in_be32(const volatile unsigned __iomem *addr) { u32 ret; @@ -234,13 +234,13 @@ static inline u32 in_be32(const volatile unsigned __iomem *addr) return ret; } -static inline void out_le32(volatile unsigned __iomem *addr, u32 val) +extern inline void out_le32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -static inline void out_be32(volatile unsigned __iomem *addr, u32 val) +extern inline void out_be32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 209103e3ce1..2e0e292da05 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -475,6 +475,10 @@ extern void print_bats(void); #define BOOKE_PAGESZ_256GB 14 #define BOOKE_PAGESZ_1TB 15 +#define TLBIVAX_ALL 4 +#define TLBIVAX_TLB0 0 +#define TLBIVAX_TLB1 8 + #ifdef CONFIG_E500 #ifndef __ASSEMBLY__ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index 3ffa30b9789..fe490bac05a 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -28,4 +28,10 @@ void cpu_mp_lmb_reserve(struct lmb *lmb); u32 determine_mp_bootpg(void); int is_core_disabled(int nr); +#ifdef CONFIG_E6500 +#define thread_to_core(x) (x >> 1) +#else +#define thread_to_core(x) (x) +#endif + #endif diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index dc009d66046..36695e2fb6d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -486,11 +486,13 @@ #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -513,6 +515,7 @@ #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define TLBnCFG_NENTRY_MASK 0x00000fff #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ @@ -948,6 +951,7 @@ #define PVR_VER_E500_V2 0x8021 #define PVR_VER_E500MC 0x8023 #define PVR_VER_E5500 0x8024 +#define PVR_VER_E6500 0x8040 #define PVR_86xx 0x80040000 @@ -1075,8 +1079,6 @@ #define SVR_P1012 0x80E501 #define SVR_P1013 0x80E700 #define SVR_P1014 0x80F101 -#define SVR_P1015 0x80E502 -#define SVR_P1016 0x80E503 #define SVR_P1017 0x80F700 #define SVR_P1020 0x80E400 #define SVR_P1021 0x80E401 @@ -1089,7 +1091,6 @@ #define SVR_P2040 0x821000 #define SVR_P2041 0x821001 #define SVR_P3041 0x821103 -#define SVR_P3060 0x820002 #define SVR_P4040 0x820100 #define SVR_P4080 0x820000 #define SVR_P5010 0x822100 @@ -1158,6 +1159,7 @@ struct cpu_type { }; struct cpu_type *identify_cpu(u32 ver); +int fixup_cpu(void); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index fea310eedd1..07feaf55fc2 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -345,6 +345,13 @@ ulong get_effective_memsize(void) #endif } +int __fixup_cpu(void) +{ + return 0; +} + +int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); + /* * This is the first part of the initialization sequence that is * implemented in C, but still running from ROM. @@ -521,9 +528,8 @@ void board_init_f(ulong bootflag) addr_sp -= 16; addr_sp &= ~0xF; s = (ulong *) addr_sp; - *s-- = 0; - *s-- = 0; - addr_sp = (ulong) s; + *s = 0; /* Terminate back chain */ + *++s = 0; /* NULL return address */ debug("Stack Pointer at: %08lx\n", addr_sp); /* @@ -647,6 +653,12 @@ void board_init_r(gd_t *id, ulong dest_addr) * We need to update it to point to the same CPU entry in RAM. */ gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE; + + /* + * If we didn't know the cpu mask & # cores, we can save them of + * now rather than 'computing' them constantly + */ + fixup_cpu(); #endif #ifdef CONFIG_SYS_EXTRA_ENV_RELOC diff --git a/arch/sparc/cpu/leon2/interrupts.c b/arch/sparc/cpu/leon2/interrupts.c index 5149550e8f7..f707efd259a 100644 --- a/arch/sparc/cpu/leon2/interrupts.c +++ b/arch/sparc/cpu/leon2/interrupts.c @@ -207,9 +207,9 @@ void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const a for (irq = 0; irq < NR_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { - printf("%02d %08lx %08lx %ld\n", irq, - (unsigned int)irq_handlers[irq].handler, - (unsigned int)irq_handlers[irq].arg, + printf("%02d %p %p %d\n", irq, + irq_handlers[irq].handler, + irq_handlers[irq].arg, irq_handlers[irq].count); } } diff --git a/arch/sparc/cpu/leon3/interrupts.c b/arch/sparc/cpu/leon3/interrupts.c index 4138f9b673d..4a3847de54c 100644 --- a/arch/sparc/cpu/leon3/interrupts.c +++ b/arch/sparc/cpu/leon3/interrupts.c @@ -209,9 +209,9 @@ void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const a for (irq = 0; irq < NR_IRQS; irq++) { if (irq_handlers[irq].handler != NULL) { - printf("%02d %08lx %08lx %ld\n", irq, - (unsigned int)irq_handlers[irq].handler, - (unsigned int)irq_handlers[irq].arg, + printf("%02d %p %p %d\n", irq, + irq_handlers[irq].handler, + irq_handlers[irq].arg, irq_handlers[irq].count); } } diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 7e48775dfe2..6f33666265e 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -166,7 +166,6 @@ char *str_init_seq_done = "\n\rInit sequence done...\r\n\r\n"; void board_init_f(ulong bootflag) { bd_t *bd; - unsigned char *s; init_fnc_t **init_fnc_ptr; int j; diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 776226fcb3b..e98244b5ed5 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -267,9 +267,9 @@ int drv_video_init(void) display_height = 256; printf("%ld x %ld pixel matrix\n", display_width, display_height); - /* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */ - csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) | - AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) | + /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */ + csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) | + AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) | AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 | AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN; writel(csr, &mc->smc.csr[2]); diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg index 3b9c53f57f2..55be3a3b32b 100644 --- a/board/Marvell/sheevaplug/kwbimage.cfg +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -21,8 +21,8 @@ # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, # MA 02110-1301 USA # -# Refer docs/README.kwimage for more details about how-to configure -# and create kirkwood boot image +# Refer to doc/README.kwbimage for more details about how-to +# configure and create kirkwood boot images. # # Boot Media configurations diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c deleted file mode 100644 index 76626f08181..00000000000 --- a/board/apollon/apollon.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics. - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <netdev.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/mem.h> -#include <asm/mach-types.h> - -void wait_for_command_complete(unsigned int wd_base); - -DECLARE_GLOBAL_DATA_PTR; - -#define write_config_reg(reg, value) \ -do { \ - writeb(value, reg); \ -} while (0) - -#define mask_config_reg(reg, mask) \ -do { \ - char value = readb(reg) & ~(mask); \ - writeb(value, reg); \ -} while (0) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRM, finish GPMC */ - - gd->bd->bi_arch_number = 919; - /* adress of boot parameters */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100); - - return 0; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with sram stack. - **********************************************************/ -void s_init(void) -{ - watchdog_init(); - set_muxconf_regs(); - delay(100); - - peripheral_enable(); - icache_enable(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - return (0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * The ROM takes care of the secure one. Of the 3 GP ones, - * 1 can reset us directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); - -#define MPU_WD_CLOCKED 1 -#if MPU_WD_CLOCKED - /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ - __raw_writel(WD_UNLOCK1, WD3_BASE + WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2, WD3_BASE + WSPR); - - __raw_writel(WD_UNLOCK1, WD4_BASE + WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); -#endif -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:board_eth_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - int cnt = 20; - - __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */ - - __raw_writew(0x0, LAN_RESET_REGISTER); - do { - __raw_writew(0x1, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto eth_reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); - - cnt = 20; - - do { - __raw_writew(0x0, LAN_RESET_REGISTER); - udelay(100); - if (cnt == 0) - goto eth_reset_err_out; - --cnt; - } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); - udelay(1000); - - mask_config_reg(ETH_CONTROL_REG, 0x01); - udelay(1000); - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -eth_reset_err_out: -#endif - return rc; -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - unsigned int size; - u32 mtype, btype; -#define NOT_EARLY 0 - - btype = get_board_type(); - mtype = get_mem_type(); - - display_board_info(btype); - - if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { - /* init other chip select */ - do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); - } - - size = get_sdr_cs_size(SDRC_CS0_OSET); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size; -#if CONFIG_NR_DRAM_BANKS > 1 - size = get_sdr_cs_size(SDRC_CS1_OSET); - - gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; - gd->bd->bi_dram[1].size = size; -#endif - - return 0; -} - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware - *********************************************************/ -void set_muxconf_regs(void) -{ - muxSetupSDRC(); - muxSetupGPMC(); - muxSetupUsb0(); /* USB Device */ - muxSetupUsbHost(); /* USB Host */ - muxSetupUART1(); - muxSetupLCD(); - muxSetupMMCSD(); - muxSetupTouchScreen(); -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void peripheral_enable(void) -{ - unsigned int v, if_clks = 0, func_clks = 0; - - /* Enable GP2 timer. */ - if_clks |= BIT4 | BIT3; - func_clks |= BIT4 | BIT3; - /* Sys_clk input OMAP2420_GPT2 */ - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CONFIG_SYS_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - /* Interface clocks on */ - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; - __raw_writel(v, CM_ICLKEN1_CORE); - /* Functional Clocks on */ - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif -} - -/**************************************** - * Routine: muxSetupUsb0 (ostboot) - * Description: Setup usb muxing - *****************************************/ -void muxSetupUsb0(void) -{ - mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f); - mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f); -} - -/**************************************** - * Routine: muxSetupUSBHost (ostboot) - * Description: Setup USB Host muxing - *****************************************/ -void muxSetupUsbHost(void) -{ - /* V19 */ - write_config_reg(CONTROL_PADCONF_USB1_RCV, 1); - /* W20 */ - write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1); - /* N14 */ - write_config_reg(CONTROL_PADCONF_GPIO69, 3); - /* P15 */ - write_config_reg(CONTROL_PADCONF_GPIO70, 3); - /* L18 */ - write_config_reg(CONTROL_PADCONF_GPIO102, 3); - /* L19 */ - write_config_reg(CONTROL_PADCONF_GPIO103, 3); - /* K15 */ - write_config_reg(CONTROL_PADCONF_GPIO104, 3); - /* K14 */ - write_config_reg(CONTROL_PADCONF_GPIO105, 3); -} - -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -void muxSetupUART1(void) -{ - /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); - /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); - /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_TX, 0); - /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_UART1_RX, 0); -} - -/**************************************** - * Routine: muxSetupLCD (ostboot) - * Description: Setup lcd muxing - *****************************************/ -void muxSetupLCD(void) -{ - /* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D0, 0); - /* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D1, 0); - /* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D2, 0); - /* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D3, 0); - /* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D4, 0); - /* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D5, 0); - /* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D6, 0); - /* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D7, 0); - /* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D8, 0); - /* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D9, 0); - /* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D10, 0); - /* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D11, 0); - /* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D12, 0); - /* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D13, 0); - /* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D14, 0); - /* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D15, 0); - /* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D16, 0); - /* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_D17, 0); - /* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0); - /* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0); - /* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0); - /* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0); -} - -/**************************************** - * Routine: muxSetupMMCSD (ostboot) - * Description: set up MMC muxing - *****************************************/ -void muxSetupMMCSD(void) -{ - /* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0); - /* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0); - /* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CMD, 0); - /* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0); - /* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0); - /* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0); - /* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0); - /* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0); - /* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0); - /* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0); - /* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0); - /* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0); -} - -/****************************************** - * Routine: muxSetupTouchScreen (ostboot) - * Description: Set up touch screen muxing - *******************************************/ -void muxSetupTouchScreen(void) -{ - /* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0); - /* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0); - /* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0); - /* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0); -#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1 - /* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */ - write_config_reg(CONTROL_PADCONF_GPIO85, 3); -} - -/*************************************************************** - * Routine: muxSetupGPMC (ostboot) - * Description: Configures balls which cam up in protected mode - ***************************************************************/ -void muxSetupGPMC(void) -{ - /* gpmc_io_dir, MCR */ - volatile unsigned int *MCR = (unsigned int *) 0x4800008C; - *MCR = 0x19000000; - - /* NOR FLASH CS0 */ - /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ - write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0); - /* MPDB(Multi Port Debug Port) CS1 */ - /* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0); - /* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0); - /* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0); - /* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0); - /* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0); - /* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0); - /* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */ - write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0); -} - -/**************************************************************** - * Routine: muxSetupSDRC (ostboot) - * Description: Configures balls which come up in protected mode - ****************************************************************/ -void muxSetupSDRC(void) -{ - /* It's set by IPL */ -} diff --git a/board/apollon/config.mk b/board/apollon/config.mk deleted file mode 100644 index 66005d4273a..00000000000 --- a/board/apollon/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2005-2007 -# Samsung Electronics -# -# Samsung December board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# December has 1 bank of 128MB mDDR-SDRAM on CS0 -# December has 1 bank of 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x83e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -#CONFIG_SYS_TEXT_BASE = 0x40270000 - -# Handy to get symbols to debug ROM version. -#CONFIG_SYS_TEXT_BASE = 0x0 -#CONFIG_SYS_TEXT_BASE = 0x08000000 diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S deleted file mode 100644 index f066fe44e77..00000000000 --- a/board/apollon/lowlevel_init.S +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include "mem.h" - -#define APOLLON_CS0_BASE 0x00000000 - -#ifdef PRCM_CONFIG_I -#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 -#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 -#define SDRC_RFR_CTRL_0_VAL 0x00044C01 -#elif defined(PRCM_CONFIG_II) -#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 -#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C -#define SDRC_RFR_CTRL_0_VAL 0x00030001 -#endif - -#define SDRAM_BASE_ADDRESS 0x80008000 - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - -#ifdef CONFIG_SYS_NOR_BOOT - /* Check running in SDRAM */ - mov r0, pc, lsr #28 - cmp r0, #8 - beq prcm_setup - -flash_setup: - /* In Flash */ - ldr r0, =WD2_BASE - ldr r1, =WD_UNLOCK1 - str r1, [r0, #WSPR] - - ldr r1, =WD_UNLOCK2 - str r1, [r0, #WSPR] - - /* Pin muxing for SDRC */ - mov r1, #0x00 - ldr r0, =0x480000A1 /* ball C12, mode 0 */ - strb r1, [r0] - - ldr r0, =0x48000032 /* ball D11, mode 0 */ - strb r1, [r0] - - ldr r0, =0x480000A3 /* ball B13, mode 0 */ - strb r1, [r0] - - /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE - ldr r1, =0x00000010 - str r1, [r0, #0x10] - - ldr r1, =0x00000100 - str r1, [r0, #0x44] - - /* SDRC CS0 configuration */ - ldr r1, =0x00d04011 - str r1, [r0, #0x80] - - ldr r1, =SDRC_ACTIM_CTRLA_0_VAL - str r1, [r0, #0x9C] - - ldr r1, =SDRC_ACTIM_CTRLB_0_VAL - str r1, [r0, #0xA0] - - ldr r1, =SDRC_RFR_CTRL_0_VAL - str r1, [r0, #0xA4] - - ldr r1, =0x00000041 - str r1, [r0, #0x70] - - /* Manual command sequence */ - ldr r1, =0x00000007 - str r1, [r0, #0xA8] - - ldr r1, =0x00000000 - str r1, [r0, #0xA8] - - ldr r1, =0x00000001 - str r1, [r0, #0xA8] - - ldr r1, =0x00000002 - str r1, [r0, #0xA8] - str r1, [r0, #0xA8] - - /* - * CS0 SDRC Mode register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - ldr r1, =0x00000032 - str r1, [r0, #0x84] - - /* Note: You MUST set EMR values */ - /* EMR1 & EMR2 */ - ldr r1, =0x00000000 - str r1, [r0, #0x88] - str r1, [r0, #0x8C] - -#ifdef OLD_SDRC_DLLA_CTRL - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00007306 - str r1, [r0, #0x60] - - ldr r1, =0x00007303 - str r1, [r0, #0x60] -#else - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x60] - - ldr r1, =0x00000503 - str r1, [r0, #0x60] -#endif - -#ifdef __BROKEN_FEATURE__ - /* SDRC_DLLB_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x68] - - ldr r1, =0x00000503 - str r1, [r0, #0x68] -#endif - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b - - /* Setup base address */ - ldr r0, =0x00000000 /* NOR address */ - ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */ - ldr r2, =0x20000 /* Size: 128KB */ - -copy_loop: - ldmia r0!, {r3-r10} - stmia r1!, {r3-r10} - cmp r0, r2 - ble copy_loop - - ldr r1, =SDRAM_BASE_ADDRESS - mov lr, pc - mov pc, r1 -#endif - -prcm_setup: - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ - bic r1, r1, #0x03 - orr r1, r1, #0x02 - str r1, [r0, #0x544] - - ldr r1, [r0, #0x500] - bic r1, r1, #0x03 - orr r1, r1, #0x01 - str r1, [r0, #0x500] - - ldr r1, [r0, #0x140] - bic r1, r1, #0x1f - orr r1, r1, #0x02 - str r1, [r0, #0x140] - -#ifdef PRCM_CONFIG_I - ldr r1, =0x000003C3 -#else - ldr r1, =0x00000343 -#endif - str r1, [r0, #0x840] - - ldr r1, =0x00000002 - str r1, [r0, #0x340] - - ldr r1, =CM_CLKSEL1_CORE -#ifdef PRCM_CONFIG_I - ldr r2, =0x08300C44 -#else - ldr r2, =0x04600C26 -#endif - str r2, [r1] - - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x01 - bne clkvalid - - b . - -clkvalid: - mov r1, #0x01 - str r1, [r0, #0x080] - -waitvalid: - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x00 - bne waitvalid - - ldr r0, =CM_CLKSEL1_PLL -#ifdef PRCM_CONFIG_I - ldr r1, =0x01837100 -#else - ldr r1, =0x01832100 -#endif - str r1, [r0] - - ldr r0, =PRCM_CLKCFG_CTRL - mov r1, #0x01 - str r1, [r0] - mov r6, #0x50 -loop1: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop1 - - ldr r0, =CM_CLKEN_PLL - mov r1, #0x0f - str r1, [r0] - - mov r6, #0x100 -loop2: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop2 - - ldr r0, =0x48008200 - ldr r1, =0xbfffffff - str r1, [r0] - - ldr r0, =0x48008210 - ldr r1, =0xfffffff9 - str r1, [r0] - - ldr r0, =0x4806a004 - ldr r1, =0x00 - strb r1, [r0] - - ldr r0, =0x4806a020 - ldr r1, =0x07 - strb r1, [r0] - - ldr r0, =0x4806a00c - ldr r1, =0x83 - strb r1, [r0] - - ldr r0, =0x4806a000 - ldr r1, =0x1a - strb r1, [r0] - - ldr r0, =0x4806a004 - ldr r1, =0x00 - strb r1, [r0] - - ldr r0, =0x4806a00c - ldr r1, =0x03 - strb r1, [r0] - - ldr r0, =0x4806a010 - ldr r1, =0x03 - strb r1, [r0] - - ldr r0, =0x4806a008 - ldr r1, =0x04 - strb r1, [r0] - - ldr r0, =0x4806a020 - ldr r1, =0x00 - strb r1, [r0] - -#if 0 - ldr r0, =0x4806a000 - mov r1, #'u' - strb r1, [r0] -#endif - -#if 0 - /* LED0 OFF */ - ldr r3, =0x480000E5 - mov r4, #0x0b - strb r4, [r3] -#endif - - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK diff --git a/board/apollon/mem.c b/board/apollon/mem.c deleted file mode 100644 index 36bf6e92239..00000000000 --- a/board/apollon/mem.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mux.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> - -#include "mem.h" - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in 12MHz bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/******************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * (config II default). - * -- called from SRAM, or Flash (using temp SRAM stack). - ********************************************************************/ -void prcm_init(void) { } - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontigious support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(SDRC_CS0_OSET); - size /= SZ_32M; /* find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); - -} - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in gussing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(void) -{ - u32 val1, val2; - u32 pattern = 0x12345678; - - /* clear pos A */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); - /* pattern to pos B */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); - /* remove pattern off the bus */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); - /* get pos A value */ - val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ - - /* see if pos A value changed */ - if ((val1 != 0) || (val2 != pattern)) - return (0); - else - return (1); -} - -/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ -#define EARLY_INIT 1 - /* only init up first bank here */ - do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -called from low level code with stack only. - * -code sets up SDRAM timing and muxing for 2422 or 2420. - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * This is a bit ugly, but should handle all memory moduels - * used with the APOLLON. The first time though this code from s_init() - * we configure the first chip select. Later on we come back and - * will configure the 2nd chip select if it exists. - * - **************************************************************************/ -void do_sdrc_init(u32 offset, u32 early) -{ -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - u32 mux = 0, mtype, mwidth, rev, tval; - - rev = get_cpu_rev(); - if (rev == CPU_2420_2422_ES1) - tval = 1; - else - tval = 0; /* disable bit switched meaning */ - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */ -#ifdef CONFIG_SYS_NAND_BOOT - /* set nWP, disable limited addr */ - __raw_writel(0x001, GPMC_CONFIG); -#else - /* set nWP, disable limited addr */ - __raw_writel(0x111, GPMC_CONFIG); -#endif - - /* discover bus connection from sysboot */ - if (is_gpmc_muxed() == GPMC_MUXED) - mux = BIT9; - mtype = get_gpmc0_type(); - mwidth = get_gpmc0_width(); - - /* setup cs0 */ - __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ - sdelay(1000); - -#ifdef CONFIG_SYS_NOR_BOOT - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0); -#else - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, - GPMC_CONFIG1_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0); -#endif - sdelay(2000); - - /* setup cs1 */ - __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ - sdelay(1000); - - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); - sdelay(2000); - - /* setup cs2 */ - __raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */ - sdelay(1000); - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth, - GPMC_CONFIG1_2); - /* It's same as cs 0 */ - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2); -#ifdef CONFIG_SYS_NOR_BOOT - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2); -#else - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2); -#endif - -#ifndef CONFIG_SYS_NOR_BOOT - /* setup cs3 */ - __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */ - sdelay(1000); - - __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3); - __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3); -#endif - -#ifndef ASYNC_NOR - __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa)); - __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554)); - __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE)); -#endif - sdelay(2000); -} diff --git a/board/apollon/mem.h b/board/apollon/mem.h deleted file mode 100644 index 09c4ea43c8b..00000000000 --- a/board/apollon/mem.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _APOLLON_OMAP24XX_MEM_H_ -#define _APOLLON_OMAP24XX_MEM_H_ - -/* Slower full frequency range default timings for x32 operation*/ -#define APOLLON_2420_SDRC_SHARING 0x00000100 -#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011 -#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032 - -/* optimized timings good for current shipping parts */ -#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485 -#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C - -#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907 -#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013 - -#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001 -#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01 - -#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306 -#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506 - -#ifdef PRCM_CONFIG_I -#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz -#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz -#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz -#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz -#elif PRCM_CONFIG_II -#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz -#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz -#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz -#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz -#endif - -/* GPMC settings */ -#ifdef PRCM_CONFIG_I /* L3 at 165MHz */ -/* CS0: OneNAND */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24)) - -/* CS1: Ethernet */ -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011203 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) - -/* CS2: OneNAND */ -/* It's same as CS0 */ -# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) - -/* CS3: NOR */ -#ifdef ASYNC_NOR -# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 -#else -# define SYNC_NOR_VALUE 0x24aaa -# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c -#endif /* ASYNC_NOR */ -# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24)) -#endif /* endif PRCM_CONFIG_I */ - -#ifdef PRCM_CONFIG_II /* L3 at 100MHz */ -/* CS0: OneNAND */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) - -/* CS1: ethernet */ -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) - -/* CS2: OneNAND */ -/* It's same as CS0 */ -# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24)) - -/* CS3: NOR */ -#define ASYNC_NOR -#ifdef ASYNC_NOR -# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317 -#else -# define SYNC_NOR_VALUE 0x24aaa -# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202 -# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501 -# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501 -# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07 -# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F -#endif /* ASYNC_NOR */ -# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000 -# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24)) -#endif /* endif PRCM_CONFIG_II */ - -#ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CONFIG_SYS_NAND_BOOT -# define APOLLON_24XX_GPMC_CONFIG1_0 0x0 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414 -# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80 -# else /* NOR boot */ -# define APOLLON_24XX_GPMC_CONFIG1_0 0x3 -# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501 -# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602 -# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008 -# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F -# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CONFIG_SYS_NAND_BOOT */ -# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) -# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000 -# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01 -# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803 -# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09 -# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F -# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 -# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) -#endif /* endif CONFIG_SYS_PRCM_III */ - -#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */ diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c deleted file mode 100644 index 4f950aef653..00000000000 --- a/board/apollon/sys_info.c +++ /dev/null @@ -1,396 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from omap2420 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/omap2420.h> -#include <asm/io.h> -#include <asm/arch/bits.h> -#include <asm/arch/mem.h> /* get mem tables */ -#include <asm/arch/sys_proto.h> -#include <asm/arch/sys_info.h> -#include <i2c.h> - -/************************************************************************** - * get_prod_id() - get id info from chips - ***************************************************************************/ -static u32 get_prod_id(void) -{ - u32 p; - p = __raw_readl(PRODUCTION_ID); /* get production ID */ - return ((p & CPU_242X_PID_MASK) >> 16); -} - -/************************************************************************** - * get_cpu_type() - low level get cpu type - * - no C globals yet. - * - just looking to say if this is a 2422 or 2420 or ... - * - to start with we will look at switch settings.. - * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics - * (mux for 2420, non-mux for 2422). - ***************************************************************************/ -u32 get_cpu_type(void) -{ - u32 v; - - switch (get_prod_id()) { - case 1:; /* 2420 */ - case 2: - return (CPU_2420); - break; /* 2420 pop */ - case 4: - return (CPU_2422); - break; - case 8: - return (CPU_2423); - break; - default: - break; /* early 2420/2422's unmarked */ - } - - v = __raw_readl(TAP_IDCODE_REG); - v &= CPU_24XX_ID_MASK; - /* currently 2420 and 2422 have same id */ - if (v == CPU_2420_CHIPID) { - if (is_gpmc_muxed() == GPMC_MUXED) /* if mux'ed */ - return (CPU_2420); - else - return (CPU_2422); - } else - return (CPU_2420); /* don't know, say 2420 */ -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return (v + 1); /* currently 2422 and 2420 match up */ -} - -/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); - if (*burst == H4_2420_SDRC_MR_0_SDR) - return (1); - return (0); -} - -/*********************************************************** - * get_mem_type() - identify type of mDDR part used. - * 2422 uses stacked DDR, 2 parts CS0/CS1. - * 2420 may have 1 or 2, no good way to know...only init 1... - * when eeprom data is up we can select 1 more. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 cpu, sdr = is_mem_sdr(); - - cpu = get_cpu_type(); - if (cpu == CPU_2422 || cpu == CPU_2423) - return (DDR_STACKED); - - if (get_prod_id() == 0x2) - return (XDR_POP); - - if (get_board_type() == BOARD_H4_MENELAUS) - if (sdr) - return (SDR_DISCRETE); - else - return (DDR_COMBO); - else if (sdr) /* SDP + SDR kit */ - return (SDR_DISCRETE); - else - return (DDR_DISCRETE); /* origional SDP */ -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 offset) -{ - u32 size; - size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; /* get ram size field */ - size &= 0x2FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ - return (size); -} - -/*********************************************************************** - * get_board_type() - get board type based on current production stats. - * --- NOTE: 2 I2C EEPROMs will someday be populated with proper info. - * when they are available we can get info from there. This should - * be correct of all known boards up until today. - ************************************************************************/ -u32 get_board_type(void) -{ - return (BOARD_H4_SDP); -} - -/****************************************************************** - * get_sysboot_value() - get init word settings (dip switch on h4) - ******************************************************************/ -inline u32 get_sysboot_value(void) -{ - return (0x00000FFF & __raw_readl(CONTROL_STATUS)); -} - -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = __raw_readl(GPMC_CONFIG7_0); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return (b); -} - -/***************************************************************** - * is_gpmc_muxed() - tells if address/data lines are multiplexed - *****************************************************************/ -u32 is_gpmc_muxed(void) -{ - u32 mux; - mux = get_sysboot_value(); - if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) - return (GPMC_MUXED); /* NAND Boot mode */ - if (mux & BIT1) /* if mux'ed */ - return (GPMC_MUXED); - else - return (GPMC_NONMUXED); -} - -/************************************************************************ - * get_gpmc0_type() - read sysboot lines to see type of memory attached - ************************************************************************/ -u32 get_gpmc0_type(void) -{ - u32 type; - type = get_sysboot_value(); - if ((type & (BIT3 | BIT2)) == (BIT3 | BIT2)) - return (TYPE_NAND); - else - return (TYPE_NOR); -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - u32 width; - width = get_sysboot_value(); - if ((width & 0xF) == (BIT3 | BIT2)) - return (WIDTH_8BIT); - else - return (WIDTH_16BIT); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -/********************************************************************* - * display_board_info() - print banner with board info. - *********************************************************************/ -void display_board_info(u32 btype) -{ - char cpu_2420[] = "2420"; /* cpu type */ - char cpu_2422[] = "2422"; - char cpu_2423[] = "2423"; - char mem_sdr[] = "mSDR"; /* memory type */ - char mem_ddr[] = "mDDR"; - char t_tst[] = "TST"; /* security level */ - char t_emu[] = "EMU"; - char t_hs[] = "HS"; - char t_gp[] = "GP"; - char unk[] = "?"; - - char *cpu_s, *mem_s, *sec_s; - u32 cpu, rev, sec; - - rev = get_cpu_rev(); - cpu = get_cpu_type(); - sec = get_device_type(); - - if (is_mem_sdr()) - mem_s = mem_sdr; - else - mem_s = mem_ddr; - - if (cpu == CPU_2423) - cpu_s = cpu_2423; - else if (cpu == CPU_2422) - cpu_s = cpu_2422; - else - cpu_s = cpu_2420; - - switch (sec) { - case TST_DEVICE: - sec_s = t_tst; - break; - case EMU_DEVICE: - sec_s = t_emu; - break; - case HS_DEVICE: - sec_s = t_hs; - break; - case GP_DEVICE: - sec_s = t_gp; - break; - default: - sec_s = unk; - } - - printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev - 1); - printf("Samsung Apollon SDP Base Board + %s \n", mem_s); -} - -/************************************************************************* - * get_board_rev() - setup to pass kernel board revision information - * 0 = 242x IP platform (first 2xx boards) - * 1 = 242x Menelaus platfrom. - *************************************************************************/ -u32 get_board_rev(void) -{ - u32 rev = 0; - u32 btype = get_board_type(); - - if (btype == BOARD_H4_MENELAUS) - rev = 1; - return (rev); -} - -/******************************************************** - * get_base(); get upper addr of current execution - *******************************************************/ -u32 get_base(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); - val &= 0xF0000000; - val >>= 28; - return (val); -} - -/******************************************************** - * get_base2(); get 2upper addr of current execution - *******************************************************/ -u32 get_base2(void) -{ - u32 val; - __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); - val &= 0xFF000000; - val >>= 24; - return (val); -} - -/******************************************************** - * running_in_flash() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_flash(void) -{ - if (get_base() < 4) - return (1); /* in flash */ - return (0); /* running in SRAM or SDRAM */ -} - -/******************************************************** - * running_in_sram() - tell if currently running in - * sram. - *******************************************************/ -u32 running_in_sram(void) -{ - if (get_base() == 4) - return (1); /* in SRAM */ - return (0); /* running in FLASH or SDRAM */ -} - -/******************************************************** - * running_in_sdram() - tell if currently running in - * flash. - *******************************************************/ -u32 running_in_sdram(void) -{ - if (get_base() > 4) - return (1); /* in sdram */ - return (0); /* running in SRAM or FLASH */ -} - -/************************************************************* - * running_from_internal_boot() - am I a signed NOR image. - *************************************************************/ -u32 running_from_internal_boot(void) -{ - u32 v, base; - - v = get_sysboot_value() & BIT3; - base = get_base2(); - /* if running at mask rom flash address and - * sysboot3 says this was an internal boot - */ - if ((base == 0x08) && v) - return (1); - else - return (0); -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (BIT10 | BIT9 | BIT8); - return (mode >>= 8); -} diff --git a/board/apollon/Makefile b/board/atmel/atngw100mkii/Makefile index 1bf1a326fc1..7fbd20d002e 100644 --- a/board/apollon/Makefile +++ b/board/atmel/atngw100mkii/Makefile @@ -1,9 +1,7 @@ # -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (C) 2005-2006 Atmel Corporation # -# See file CREDITS for list of people who contributed to this -# project. +# See file CREDITS for list of people who contributed to this project. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -19,25 +17,24 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -# include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o +LIB := $(obj)lib$(BOARD).o -COBJS-y := apollon.o mem.o sys_info.o -SOBJS := lowlevel_init.o +COBJS := $(BOARD).o -COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### +# defines $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend + +######################################################################### diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c new file mode 100644 index 00000000000..f4023b3eefd --- /dev/null +++ b/board/atmel/atngw100mkii/atngw100mkii.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2010 Atmel Corporation + * + * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <spi.h> +#include <netdev.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/mmu.h> +#include <asm/arch/portmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { + { + /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ + .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ + .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT, + .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_NONE, + }, { + /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + | MMU_VMR_CACHE_WRBACK, + }, +}; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_32BIT, + .row_bits = 13, + .col_bits = 10, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 6, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE) + | HMATRIX_BIT(EBI_NAND_ENABLE)); + + portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND, + PORTMUX_DRIVE_HIGH); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 23, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH + | PORTMUX_DRIVE_MIN); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif +#if defined(CONFIG_ATMEL_SPI) + portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = uncached(EBI_SDRAM_BASE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + gd->bd->bi_phy_id[1] = 0x03; + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); + return 0; +} +#endif + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); +} +#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index a0a4d1d07dd..93f12ea4f19 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0, SD slot, with 4-bit bus */ - tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); + tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); return 0; } diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index 9faebd8bc66..bb3851b57d1 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -55,4 +55,15 @@ usb@c5004000 { status = "disabled"; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index fe155112c9e..b3f31d6b697 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -158,7 +158,7 @@ static void set_led(int state) { switch (state) { case LED_OFF: - __set_led(0, 0, 0, 0, 0, 0); + __set_led(0, 0, 0, 1, 1, 1); break; case LED_ALARM_ON: __set_led(0, 0, 0, 0, 1, 1); @@ -192,6 +192,25 @@ int board_init(void) } #ifdef CONFIG_MISC_INIT_R +static void check_power_switch(void) +{ + if (kw_gpio_get_value(GPIO_POWER_SWITCH)) { + /* turn off HDD and USB power */ + kw_gpio_set_value(GPIO_HDD_POWER, 0); + kw_gpio_set_value(GPIO_USB_VBUS, 0); + set_led(LED_OFF); + + /* loop until released */ + while (kw_gpio_get_value(GPIO_POWER_SWITCH)) + ; + + /* turn power on again */ + kw_gpio_set_value(GPIO_HDD_POWER, 1); + kw_gpio_set_value(GPIO_USB_VBUS, 1); + set_led(LED_POWER_BLINKING); + } +} + void check_enetaddr(void) { uchar enetaddr[6]; @@ -261,6 +280,7 @@ static void check_push_button(void) int misc_init_r(void) { + check_power_switch(); check_enetaddr(); check_push_button(); diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index cd684f29263..0f8f1670172 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra20_mmc_init(0, 4, -1, -1); + tegra_mmc_init(0, 4, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ - tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); + tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; } diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c index 5dae15b962f..893cca8c19b 100644 --- a/board/compulab/trimslice/trimslice.c +++ b/board/compulab/trimslice/trimslice.c @@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ - tegra20_mmc_init(0, 4, -1, GPIO_PP1); + tegra_mmc_init(0, 4, -1, GPIO_PP1); /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ - tegra20_mmc_init(3, 4, -1, -1); + tegra_mmc_init(3, 4, -1, -1); return 0; } diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 0b40dc7bf72..54cb098a915 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -51,14 +51,12 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o -COBJS-$(CONFIG_P3060QDS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o -SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 6ddf8162012..3ef49369a47 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -25,6 +25,9 @@ #include <libfdt_env.h> #include <fdt_support.h> +#include <fm_eth.h> +#include <asm/fsl_serdes.h> + /* * Given the following ... * @@ -67,3 +70,31 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); } + +/* + * Return the SerDes device enum for a given Fman port + * + * This function just maps the fm_port namespace to the srds_prtcl namespace. + */ +enum srds_prtcl serdes_device_from_fm_port(enum fm_port port) +{ + static const enum srds_prtcl srds_table[] = { + [FM1_DTSEC1] = SGMII_FM1_DTSEC1, + [FM1_DTSEC2] = SGMII_FM1_DTSEC2, + [FM1_DTSEC3] = SGMII_FM1_DTSEC3, + [FM1_DTSEC4] = SGMII_FM1_DTSEC4, + [FM1_DTSEC5] = SGMII_FM1_DTSEC5, + [FM1_10GEC1] = XAUI_FM1, + [FM2_DTSEC1] = SGMII_FM2_DTSEC1, + [FM2_DTSEC2] = SGMII_FM2_DTSEC2, + [FM2_DTSEC3] = SGMII_FM2_DTSEC3, + [FM2_DTSEC4] = SGMII_FM2_DTSEC4, + [FM2_DTSEC5] = SGMII_FM2_DTSEC5, + [FM2_10GEC1] = XAUI_FM2, + }; + + if ((port < FM1_DTSEC1) || (port > FM2_10GEC1)) + return NONE; + else + return srds_table[port]; +} diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h index d39ef080c1f..734b1da1d67 100644 --- a/board/freescale/common/fman.h +++ b/board/freescale/common/fman.h @@ -23,4 +23,6 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, const char *alias); +enum srds_prtcl serdes_device_from_fm_port(enum fm_port port); + #endif diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index c4566ddd4f7..09ef5615d26 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,19 +48,6 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif -#ifdef CONFIG_SRIOBOOT_SLAVE -#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) - SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, - LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), - SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, - LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), -#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) - SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, - LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), - SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, - LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), -#endif -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index da2162728fd..e5cf208a905 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIOBOOT_SLAVE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* - * SRIOBOOT-SLAVE. When slave boot, the address of the + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, - CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SRIOBOOT_SLAVE +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* - * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode - * and ENV from master + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index b87b0922acf..2c69c516dd2 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -68,6 +68,15 @@ static char *mdio_names[16] = { NULL, NULL, NULL, }; +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot. + */ +static u8 lane_to_slot[] = { + 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 +}; + static char *p4080ds_mdio_name_for_muxval(u32 muxval) { return mdio_names[(muxval & EMI_MASK) >> 28]; @@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt) } } -enum board_slots { - SLOT1 = 1, - SLOT2, - SLOT3, - SLOT4, - SLOT5, - SLOT6, -}; - int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET @@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis) struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; - u8 lane_to_slot[] = { - SLOT1, /* 0 - Bank 1:A */ - SLOT1, /* 1 - Bank 1:B */ - SLOT2, /* 2 - Bank 1:C */ - SLOT2, /* 3 - Bank 1:D */ - SLOT3, /* 4 - Bank 1:E */ - SLOT3, /* 5 - Bank 1:F */ - SLOT3, /* 6 - Bank 1:G */ - SLOT3, /* 7 - Bank 1:H */ - SLOT6, /* 8 - Bank 1:I */ - SLOT6, /* 9 - Bank 1:J */ - SLOT4, /* 10 - Bank 2:A */ - SLOT4, /* 11 - Bank 2:B */ - SLOT4, /* 12 - Bank 2:C */ - SLOT4, /* 13 - Bank 2:D */ - SLOT5, /* 14 - Bank 3:A */ - SLOT5, /* 15 - Bank 3:B */ - SLOT5, /* 16 - Bank 3:C */ - SLOT5, /* 17 - Bank 3:D */ - }; - /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; @@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis) break; slot = lane_to_slot[lane]; switch (slot) { - case SLOT3: + case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT4: + case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT5: + case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); @@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis) break; slot = lane_to_slot[lane]; switch (slot) { - case SLOT4: + case 4: mdio_mux[i] = EMI2_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT5: + case 5: mdio_mux[i] = EMI2_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); @@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis) break; slot = lane_to_slot[lane]; switch (slot) { - case SLOT3: + case 3: mdio_mux[i] = EMI1_SLOT3; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT4: + case 4: mdio_mux[i] = EMI1_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT5: + case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); @@ -481,12 +460,12 @@ int board_eth_init(bd_t *bis) break; slot = lane_to_slot[lane]; switch (slot) { - case SLOT4: + case 4: mdio_mux[i] = EMI2_SLOT4; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; - case SLOT5: + case 5: mdio_mux[i] = EMI2_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg new file mode 100644 index 00000000000..50806ca8a00 --- /dev/null +++ b/board/freescale/corenet_ds/pbi.cfg @@ -0,0 +1,51 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg new file mode 100644 index 00000000000..8813156219f --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p3041ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P3041DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +D8984A01 03002000 58000000 41000000 +00000000 00000000 00000000 10070000 +00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg new file mode 100644 index 00000000000..6a263395998 --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p4080ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P4080DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +105a0000 00000000 1e1e181e 0000cccc +58400000 3c3c2000 58000000 e1000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg new file mode 100644 index 00000000000..b09e409bbff --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p5020ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P5020DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0C540000 00000000 1E120000 00000000 +D8984A01 03002000 58000000 41000000 +00000000 00000000 00000000 10070000 +00000000 00000000 00000000 00000000 diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 5f99e2f2442..355cfedfbed 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,34 +51,35 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_SDRAM_BASE1 - sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); asm("nop"); - sdram->mode = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); asm("nop"); udelay(100); diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index 9109edb3710..a9bec584fa6 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,8 +48,8 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -59,36 +60,37 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD); __asm__("nop"); udelay(1000); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); #endif diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index b9e61269c74..e9a568efb38 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,8 +40,8 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 dramsize, i, dramclk; /* @@ -48,14 +49,15 @@ phys_size_t initdram(int board_type) * the port-size of SDRAM. In this case it is necessary to enable * Data[15:0] on Port Address/Data. */ - gpio->par_ad = - GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | - GPIO_PAR_AD_DATAL; + out_8(&gpio->par_ad, + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL); /* Initialize PAR to enable SDRAM signals */ - gpio->par_sdram = - GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | - GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); + out_8(&gpio->par_sdram, + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | + GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | + GPIO_PAR_SDRAM_SDCS(3)); dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -64,25 +66,28 @@ phys_size_t initdram(int board_type) } i--; - if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { + if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); /* Initialize DRAM Control Register: DCR */ - sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | - SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4); + out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | + SDRAMC_DCR_RC((15 * dramclk) >> 4)); /* Initialize DACR0 */ - sdram->dacr0 = - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | - SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; + out_be32(&sdram->dacr0, + SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | + SDRAMC_DARCn_PS_32); asm("nop"); /* Initialize DMR0 */ - sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V; + out_be32(&sdram->dmr0, + ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V); asm("nop"); /* Set IP (bit 3) in DACR */ - sdram->dacr0 |= SDRAMC_DARCn_IP; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); /* Wait 30ns to allow banks to precharge */ for (i = 0; i < 5; i++) { @@ -93,7 +98,7 @@ phys_size_t initdram(int board_type) *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ - sdram->dacr0 |= SDRAMC_DARCn_RE; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); /* Wait for at least 8 auto refresh cycles to occur */ for (i = 0; i < 0x2000; i++) { @@ -101,7 +106,7 @@ phys_size_t initdram(int board_type) } /* Finish the configuration by issuing the MRS. */ - sdram->dacr0 |= SDRAMC_DARCn_IMRS; + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); asm("nop"); /* Write to the SDRAM Mode Register */ diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 8ffb2cc0447..052993da660 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -109,7 +109,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -120,7 +120,8 @@ void ide_set_reset(int idereset) }; if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(100); } else { mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); @@ -129,17 +130,19 @@ void ide_set_reset(int idereset) period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(2000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index ae69f67b482..658748b0dcf 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int checkboard(void) { @@ -101,7 +102,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -112,7 +113,8 @@ void ide_set_reset(int idereset) }; if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(100); } else { mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); @@ -121,17 +123,19 @@ void ide_set_reset(int idereset) period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(2000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif /* CONFIG_CMD_IDE */ diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 902ca3aac67..c3160cef209 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -2,6 +2,8 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,6 +25,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int checkboard (void) { @@ -32,10 +35,10 @@ int checkboard (void) { }; phys_size_t initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); + sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); - sdp->sdram_sdtr = 0xf539; - sdp->sdram_sdcr = 0x4211; + out_be16(&sdp->sdram_sdtr, 0xf539); + out_be16(&sdp->sdram_sdcr, 0x4211); /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0; diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 35c9b2018c1..1bbe5a33071 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -4,6 +4,8 @@ * * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,6 +27,7 @@ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> #define PERIOD 13 /* system bus period in ns */ #define SDRAM_TREFI 7800 /* in ns */ @@ -38,67 +41,68 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); - volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); + sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); + gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); - gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ + /* Enable SDRAM */ + out_be16(&gpio_reg->par_sdram, 0x3FF); /* Set up chip select */ - sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE; - sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; + out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); /* Set up timing */ - sdp->sdcfg1 = 0x83711630; - sdp->sdcfg2 = 0x46770000; + out_be32(&sdp->sdcfg1, 0x83711630); + out_be32(&sdp->sdcfg2, 0x46770000); /* Enable clock */ - sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE; + out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE); /* Set precharge */ - sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); /* Dummy write to start SDRAM */ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LEMR */ - sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR - | MCF_SDRAMC_SDMR_AD(0x0) - | MCF_SDRAMC_SDMR_CMD; + setbits_be32(&sdp->sdmr, + MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | + MCF_SDRAMC_SDMR_CMD); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LMR */ - sdp->sdmr = 0x058d0000; + out_be32(&sdp->sdmr, 0x058d0000); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ - sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); /* Set precharge */ - sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop manual precharge, send 2 IREF */ - sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); - sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; - /* Write mode register, clear reset DLL */ - sdp->sdmr = 0x018d0000; + + out_be32(&sdp->sdmr, 0x018d0000); *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ - sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); - sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN); + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN); /* Turn on auto refresh, lock SDMR */ - sdp->sdcr = + out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_CKE | MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_MUX(1) /* 1 added to round up */ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) - | MCF_SDRAMC_SDCR_DQS_OE(0x3); + | MCF_SDRAMC_SDCR_DQS_OE(0x3)); return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index f331786bf7d..142485f0eda 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,34 +51,35 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_SDRAM_BASE1 - sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); asm("nop"); - sdram->mode = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); asm("nop"); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); asm("nop"); udelay(100); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index b4df22f1f23..1c14b83a9d9 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,29 +51,30 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 16025f91e2e..c70c98c8a14 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* * set up pin configuration - enabled 2nd output buffer's signals * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) * to use nCE signal */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index 376de4b9522..8eb3512daec 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <config.h> #include <common.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,7 +40,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; @@ -50,29 +51,30 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index df8c03b8a27..ed79e395c1d 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) int board_nand_init(struct nand_chip *nand) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - fbcs->csmr2 &= ~FBCS_CSMR_WP; + clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); /* * set up pin configuration - enabled 2nd output buffer's signals * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) * to use nCE signal */ - gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; - gpio->pddr_timer |= 0x08; - gpio->ppd_timer |= 0x08; - gpio->pclrr_timer = 0; - gpio->podr_timer = 0; + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); nand->chip_delay = 60; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c index 088c8c4d1ac..32a9374cf9a 100644 --- a/board/freescale/m54451evb/m54451evb.c +++ b/board/freescale/m54451evb/m54451evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <spi.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,14 +52,14 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) && - (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2)) + if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) && + (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2)) return dramsize; for (i = 0x13; i < 0x20; i++) { @@ -67,32 +68,33 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); udelay(200); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); __asm__("nop"); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE); __asm__("nop"); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000); udelay(100); #endif diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 2a84514a3dc..0ca268ee168 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,8 +48,8 @@ phys_size_t initdram(int board_type) */ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; #else - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); u32 i; dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; @@ -59,33 +60,34 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH); - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i); + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i); - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408; - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408); + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300); udelay(500); /* Issue PALL */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200; + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200); - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + out_be32(&sdram->sdcr, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); #endif @@ -105,26 +107,29 @@ int testdram(void) int ide_preinit(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; - gpio->par_feci2c |= - (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | - GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); - gpio->par_ata |= - (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | - GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 - | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | - GPIO_PAR_ATA_IORDY_IORDY); - gpio->par_pci |= - (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u32 tmp; + + tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; + setbits_8(&gpio->par_fec, tmp); + tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) | + (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW)); + setbits_be16(&gpio->par_feci2c, tmp); + + setbits_be16(&gpio->par_ata, + GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 | + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 | + GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ | + GPIO_PAR_ATA_IORDY_IORDY); + setbits_be16(&gpio->par_pci, + GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ); return (0); } void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) MMAP_ATA; + atac_t *ata = (atac_t *) MMAP_ATA; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { @@ -136,24 +141,27 @@ void ide_set_reset(int idereset) }; /* PIO 4 */ if (idereset) { - ata->cr = 0; /* control reset */ + /* control reset */ + out_8(&ata->cr, 0); udelay(10000); } else { #define CALC_TIMING(t) (t + period - 1) / period period = 1000000000 / gd->bus_clk; /* period in ns */ /*ata->ton = CALC_TIMING (180); */ - ata->t1 = CALC_TIMING(piotms[2][0]); - ata->t2w = CALC_TIMING(piotms[2][1]); - ata->t2r = CALC_TIMING(piotms[2][1]); - ata->ta = CALC_TIMING(piotms[2][8]); - ata->trd = CALC_TIMING(piotms[2][7]); - ata->t4 = CALC_TIMING(piotms[2][3]); - ata->t9 = CALC_TIMING(piotms[2][6]); - - ata->cr = 0x40; /* IORDY enable */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); udelay(200000); - ata->cr |= 0x01; /* IORDY enable */ + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); } } #endif diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 9f1ec3854c0..fd9bddd22fc 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,14 +41,14 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); udelay(100); diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index fbc08883201..fb216d8d1c4 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,14 +41,14 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH); dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i); #ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); /* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); udelay(100); diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index 5c543573a81..7e3fa1a621e 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -24,18 +24,56 @@ #include <common.h> #include <hwconfig.h> #include <i2c.h> +#include <spi.h> #include <libfdt.h> #include <fdt_support.h> #include <pci.h> #include <mpc83xx.h> #include <vsc7385.h> #include <netdev.h> +#include <fsl_esdhc.h> #include <asm/io.h> #include <asm/fsl_serdes.h> #include <asm/fsl_mpc83xx_serdes.h> DECLARE_GLOBAL_DATA_PTR; +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_MPC8XXX_SPI + +#define SPI_CS_MASK 0x00400000 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* active low */ + clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + /* inactive high */ + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +} +#endif /* CONFIG_MPC8XXX_SPI */ + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + return fsl_esdhc_mmc_init(bd); +} +#endif + static u8 read_board_info(void) { u8 val8; @@ -109,6 +147,25 @@ void pci_init_board(void) */ int misc_init_r(void) { +#ifdef CONFIG_MPC8XXX_SPI + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + + /* + * Set proper bits in SICRH to allow SPI on header J8 + * + * NOTE: this breaks the TSEC2 interface, attached to the Vitesse + * switch. The pinmux configuration does not have a fine enough + * granularity to support both simultaneously. + */ + clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); + puts("WARNING: SPI enabled, TSEC2 support is broken\n"); + + /* Set header J8 SPI chip select output, disabled */ + setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); + setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); +#endif + #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { @@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); } #endif diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index c75585e28c0..a275d3a074d 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -87,10 +87,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -105,7 +105,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 532d32ac7cb..13ca84b6523 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -269,13 +269,13 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ + lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 3361614de5f..4cfd61cdd95 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -267,13 +267,13 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr |= 0x80000000; /* DLL Bypass */ + lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1a165bff869..285edbce6b4 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -292,10 +292,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -310,7 +310,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 16a6d8ad230..ae6eda343ed 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -173,7 +173,7 @@ const iomux_cfg_t iomux_setup[] = { #define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ ADDR_PINS << 8 | APREBIT) -void mx28_adjust_memory_params(uint32_t *dram_vals) +void mxs_adjust_memory_params(uint32_t *dram_vals) { dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; } diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 867d3c8518f..d782aea61b8 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -49,8 +49,8 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 96MHz */ - mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + /* SSP2 clock at 160MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 160000, 0); #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README index 3d69ed5839c..7232b533574 100644 --- a/board/freescale/mx35pdk/README +++ b/board/freescale/mx35pdk/README @@ -71,91 +71,17 @@ exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nf Flashing U-Boot -------------------------------- -There are two options: the original bootloader in NAND can be replaced with -u-boot, or u-boot can be stored on the NOR flash without erasing -the delivered bootloader. +U-boot should be stored on the NOR flash. + The boot storage can be select using the switches on the personality board (SW1-SW2) and on the DEBUG board (SW4-SW10). -The second option is to be preferred if you have not a JTAG debugger. If something goes wrong flashing the bootloader, it is always possible to recover the board booting from the other device. -Replacing the bootloader on the NAND --------------------------------------- -To replace RedBoot with U-Boot, the easy way is to do this in linux. -Start the kernel with the suggested options. Make sure to have set the -mtdparts exactly as described, because this matches the layout on the -mx35pdk. - -You should see in your boot log the following entries for the NAND -flash: - -5 cmdlinepart partitions found on MTD device mxc_nand -Creating 5 MTD partitions on "mxc_nand": -0x000000000000-0x000000100000 : "boot" -0x000000100000-0x000000600000 : "linux" -0x000000600000-0x000006600000 : "root" -0x000006600000-0x000006e00000 : "cfg" -0x000006e00000-0x000080000000 : "user" - -You can use the utilities flash_eraseall and nandwrite to put -u-boot on the NAND. The bootloader is marked as "boot", and 1MB is -reserved. If everything is correct, this partition is accessed as -/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and -get the device node from the partition name: - -$ cat /proc/mtd | grep boot - -I suggest you try the utilities on a different partition to be sure -if everything works correctly. If not, and you remove RedBoot, you have to -reinstall it using the ATK tool as suggested by Freescale, or using a -JTAG debugger. - -I report the versions of the utilities I used (they are provided with ELDK): - --bash-3.2# nandwrite --version -nandwrite $Revision: 1.32 $ - -flash_eraseall --version -flash_eraseall $Revision: 1.22 $ - -nandwrite reports a warning if the file to be saved is not sector aligned. -This should have no consequences, but I preferred to pad u-boot.bin -to get no problem at all. -$ dd if=/dev/zero of=zeros bs=1 count=74800 -$ cat u-boot.bin zeros > u-boot-padded.bin - -To erase the partition: -$ flash_eraseall /dev/mtd4 - -Writing u-boot: - -$ nandwrite /dev/mtd4 u-boot-padded.bin - -Now U-Boot is stored on the booting partition. - -To boot from NAND, you have to select the switches as follows: - -Personality board - SW2 1, 4, 5 on - 2, 3, 6, 7, 8 off - SW1 all off - -Debug Board: - SW5 0 - SW6 0 - SW7 0 - SW8 1 - SW9 1 - SW10 0 - - Saving U-Boot in the NOR flash --------------------------------- -The procedure to save in the NOR flash is quite the same as to write into the NAND. - Check the partition for boot in the NOR flash. Setting the mtdparts as reported, the boot partition should be /dev/mtd0. diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 787c9232d25..7cb6b3086f1 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -32,6 +32,8 @@ #include <i2c.h> #include <pmic.h> #include <fsl_pmic.h> +#include <mmc.h> +#include <fsl_esdhc.h> #include <mc9sdz60.h> #include <mc13892.h> #include <linux/types.h> @@ -275,3 +277,26 @@ int board_eth_init(bd_t *bis) return rc; } + +#if defined(CONFIG_FSL_ESDHC) + +struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; + +int board_mmc_init(bd_t *bis) +{ + /* configure pins for SDHC1 only */ + mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4); +} +#endif diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 909ccca11e9..4b4e89b0e22 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -197,18 +197,18 @@ static iomux_v3_cfg_t button_pads[] = { static void setup_iomux_enet(void) { - gpio_direction_output(87, 0); /* GPIO 3-23 */ - gpio_direction_output(190, 1); /* GPIO 6-30 */ - gpio_direction_output(185, 1); /* GPIO 6-25 */ - gpio_direction_output(187, 1); /* GPIO 6-27 */ - gpio_direction_output(188, 1); /* GPIO 6-28*/ - gpio_direction_output(189, 1); /* GPIO 6-29 */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); - gpio_direction_output(184, 1); /* GPIO 6-24 */ + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); - gpio_set_value(87, 1); /* GPIO 3-23 */ + gpio_set_value(IMX_GPIO_NR(3, 23), 1); imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } @@ -249,11 +249,11 @@ int board_mmc_getcd(struct mmc *mmc) int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { - gpio_direction_input(192); /*GPIO7_0*/ - ret = !gpio_get_value(192); + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); } else { - gpio_direction_input(38); /*GPIO2_6*/ - ret = !gpio_get_value(38); + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); } return ret; diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 10c5a42d1ea..6d00caffa37 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ if (cpu->soc_ver == SVR_P1014) { + ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; - ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; - ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; + /* divide SA and EA by two and then mask the rest so we don't + * write to reserved fields */ + ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 79689199c12..0da8300c6f5 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -25,13 +25,11 @@ #include <asm/mmu.h> struct law_entry law_table[] = { -#ifndef CONFIG_NAND_SPL SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif -#endif SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p3060qds/README b/board/freescale/p3060qds/README deleted file mode 100644 index ec627980c11..00000000000 --- a/board/freescale/p3060qds/README +++ /dev/null @@ -1,110 +0,0 @@ -Overview -========= -The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC. - -The P3060 Processor combines six e500mc Power Architecture processor -cores(1.2GHz) with high-performance datapath acceleration -architecture(DPAA), CoreNet fabric infrastructure, as well as network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and military/aerospace applications. - - -P3060QDS Board Specifications: -============================== -Memory subsystem: - * 2G Bytes UDIMM DDR3(64bit bus) with ECC on - * 128M Bytes NOR flash single-chip memory - * 16M Bytes SPI flash - * 8K Bytes AT24C64 I2C EEPROM for RCW - -Ethernet(Default SERDES 0x19): - * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45) - * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45) - * FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1) - * FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1) - * FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2) - * FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2) - * FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1) - * FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1) - -PCIe: - * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4 - * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3 - -RapidIO: - * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3) - * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4) - -USB: - * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface - * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface - -I2C: - * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD, - AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68) - * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon - ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D) - * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40) - * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56) - * I2C1_CH4: PCIe SLOT1 - * I2C1_CH5: PCIe SLOT2 - * I2C1_CH6: PCIe SLOT3 - * I2C1_CH7: PCIe SLOT4 - * I2C2: NULL - * I2C3: NULL - -UART: - * Supports two UARTs up to 115200 bps for console - - -Boot from NOR flash -=================== -1. Build image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu- - make P3060QDS_config - make - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff80000 efffffff - => cp.b 1000000 eff80000 80000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase ef000000 ef0fffff - => cp.b 1000000 ef000000 2000 - -5. Change DIP-switch - RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash) - Note: 1 stands for 'on', 0 stands for 'off' - - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb - -Or use the following command: - {linux-2.6}/make p3060qds.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p3060qds.dtb - - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p3060rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c deleted file mode 100644 index 9affbf09f78..00000000000 --- a/board/freescale/p3060qds/ddr.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <asm/mmu.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> - -#include "p3060qds.h" - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - unsigned int lawbar1_target_id; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); - - /* - * setup laws for DDR. If not interleaving, presuming half memory on - * DDR1 and the other half on DDR2 - */ - if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - LAW_TRGT_IF_DDR_INTRLV) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } else { - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } - return ddr_size; -} - -struct board_specific_params { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2T; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_params udimm[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 950, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -static const struct board_specific_params rdimm[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_params *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimm; - else - pbsp = udimm; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twoT_en = pbsp_highest->force_2T; - } else { - panic("DIMM is not supported by this board"); - } - - -found: - - /* - * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered. - * However SPD still claims CL=7 is supported. Extensive tests - * confirmed this board cannot work stably with CL=7 with this - * particular DIMM. - */ - if (ddr_freq >= 800 && ddr_freq < 1066 && \ - !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) { - popts->cas_latency_override = 1; - popts->cas_latency_override_value = 8; - debug("Override CL to 8\n"); - } - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("using fixed parameters\n"); - dram_size = fixed_sdram(); - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - return dram_size; -} diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c deleted file mode 100644 index 3f812dbd3c9..00000000000 --- a/board/freescale/p3060qds/eth.c +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <asm/fsl_dtsec.h> - -#include "../common/qixis.h" -#include "../common/fman.h" - -#include "p3060qds_qixis.h" - -#define EMI_NONE 0xffffffff -#define EMI1_RGMII1 0 -#define EMI1_SLOT1 1 -#define EMI1_SLOT2 2 -#define EMI1_SLOT3 3 -#define EMI1_RGMII2 4 - -static int mdio_mux[NUM_FM_PORTS]; - -static char *mdio_names[5] = { - "P3060QDS_MDIO0", - "P3060QDS_MDIO1", - "P3060QDS_MDIO2", - "P3060QDS_MDIO3", - "P3060QDS_MDIO4", -}; - -/* - * Mapping of all 18 SERDES lanes to board slots. - * A value of '0' here means that the mapping must be determined - * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug - */ -static u8 lane_to_slot[] = { - 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 -}; - -static char *p3060qds_mdio_name_for_muxval(u32 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u32 muxval) -{ - struct mii_dev *bus; - char *name = p3060qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct p3060qds_mdio { - u32 muxval; - struct mii_dev *realbus; -}; - -static void p3060qds_mux_mdio(u32 muxval) -{ - u8 brdcfg4; - - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << 4); - QIXIS_WRITE(brdcfg[4], brdcfg4); -} - -static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct p3060qds_mdio *priv = bus->priv; - - p3060qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct p3060qds_mdio *priv = bus->priv; - - p3060qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int p3060qds_mdio_reset(struct mii_dev *bus) -{ - struct p3060qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int p3060qds_mdio_init(char *realbusname, u32 muxval) -{ - struct p3060qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate P3060QDS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate P3060QDS private data\n"); - free(bus); - return -1; - } - - bus->read = p3060qds_mdio_read; - bus->write = p3060qds_mdio_write; - bus->reset = p3060qds_mdio_reset; - sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - if (mdio_mux[port] == EMI1_RGMII1) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1"); - - if (mdio_mux[port] == EMI1_RGMII2) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2"); - - if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3) - || (srds_prtcl == 0x6))) { - switch (port) { - case FM2_DTSEC4: - fdt_set_phy_handle(blob, prop, pa, "phy2_slot1"); - break; - case FM1_DTSEC4: - fdt_set_phy_handle(blob, prop, pa, "phy3_slot1"); - break; - default: - break; - } - } - - if (mdio_mux[port] == EMI1_SLOT3) { - switch (port) { - case FM2_DTSEC3: - fdt_set_phy_handle(blob, prop, pa, "phy0_slot3"); - break; - case FM1_DTSEC3: - fdt_set_phy_handle(blob, prop, pa, "phy1_slot3"); - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i, lane, idx; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - - switch (mdio_mux[i]) { - case EMI1_SLOT1: - if (lane >= 14) { - fdt_status_okay_by_alias(fdt, - "emi1_slot1"); - fdt_status_disabled_by_alias(fdt, - "emi1_slot1_bk1"); - } else { - fdt_status_disabled_by_alias(fdt, - "emi1_slot1"); - fdt_status_okay_by_alias(fdt, - "emi1_slot1_bk1"); - } - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - if (i == FM1_DTSEC1) - fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); - - if (i == FM1_DTSEC2) - fdt_status_okay_by_alias(fdt, "emi1_rgmii2"); - break; - default: - break; - } - } -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - idx = i - FM2_DTSEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane >= 0) { - switch (mdio_mux[i]) { - case EMI1_SLOT1: - if (lane >= 14) - fdt_status_okay_by_alias(fdt, - "emi1_slot1"); - else - fdt_status_okay_by_alias(fdt, - "emi1_slot1_bk1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, - "emi1_slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, - "emi1_slot3"); - break; - } - } - break; - default: - break; - } - } -#endif -} - -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int sdprtl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - switch (sdprtl) { - case 0x03: - case 0x06: - lane_to_slot[8] = 1; - lane_to_slot[9] = lane_to_slot[8]; - lane_to_slot[16] = 5; - lane_to_slot[17] = lane_to_slot[16]; - break; - case 0x16: - case 0x19: - case 0x1C: - lane_to_slot[8] = 5; - lane_to_slot[9] = lane_to_slot[8]; - lane_to_slot[16] = 1; - lane_to_slot[17] = lane_to_slot[16]; - break; - default: - puts("Invalid SerDes protocol for P3060QDS\n"); - break; - } -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; - int i; - struct fsl_pq_mdio_info dtsec_mdio_info; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_cfg = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - initialize_lane_to_slot(); - - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - /* Register the 5 muxing front-ends to the MDIO buses */ - if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) - p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - - if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) - p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - - if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) - fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */ - else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR); - - if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) - fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */ - else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII) - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - - fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR); - - switch (srds_cfg) { - case 0x03: - case 0x06: - fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x16: - case 0x19: - case 0x1C: - fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - puts("Invalid SerDes protocol for P3060QDS\n"); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (QIXIS_READ(present) & (1 << (slot - 1))) - fm_disable_port(i); - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - if (i == FM1_DTSEC1) { - mdio_mux[i] = EMI1_RGMII1; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - } else if (i == FM1_DTSEC2) { - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - } - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (QIXIS_READ(present) & (1 << (slot - 1))) - fm_disable_port(i); - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } -#endif /* CONFIG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c deleted file mode 100644 index 125988da829..00000000000 --- a/board/freescale/p3060qds/fixed_ddr.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> - -#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 -#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 -#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 -#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 -#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 -#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 -#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 -#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF -#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 -#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 -#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 -#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce -#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 -#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 -#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 -#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 -#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {850, 950, &ddr_cfg_regs_900}, - {950, 1050, &ddr_cfg_regs_1000}, - {1050, 1250, &ddr_cfg_regs_1200}, - {0, 0, NULL} -}; diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c deleted file mode 100644 index 43e7f2888a5..00000000000 --- a/board/freescale/p3060qds/p3060qds.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> -#include <configs/P3060QDS.h> -#include <libfdt.h> -#include <fdt_support.h> - -#include "../common/qixis.h" -#include "p3060qds.h" -#include "p3060qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - u8 sw; - struct cpu_type *cpu = gd->cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; - - printf("Board: %s", cpu->name); - puts("QDS, "); - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - - puts("SERDES Reference Clocks: "); - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < 3; i++) { - static const char * const freq[] = {"100", "125", "Reserved", - "156.25"}; - unsigned int clock = (sw >> (2 * i)) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[clock]); - } - puts("\n"); - - return 0; -} - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */ - setbits_be32(&gur->ddrclkdr, 0x00030000); - - return 0; -} - -void board_config_serdes_mux(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int cfg = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - switch (cfg) { - case 0x03: - case 0x06: - /* set Lane I,J as SGMII */ - QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A | - BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A); - break; - case 0x16: - case 0x19: - case 0x1c: - /* set Lane I,J as Aurora Debug */ - QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B | - BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B); - break; - default: - puts("Invalid SerDes protocol for P3060QDS\n"); - break; - } -} - -void board_config_usb_mux(void) -{ - u8 brdcfg4, brdcfg5, brdcfg7; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr11 = in_be32(&gur->rcwsr[11]); - u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1; - u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2; - - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EC_MODE_MASK; - if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && - (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { - brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB; - - } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && - ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || - (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { - brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB; - - } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && - (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { - brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII; - - } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && - ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || - (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { - brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII; - } else { - brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII; - } - QIXIS_WRITE(brdcfg[4], brdcfg4); - - brdcfg5 = QIXIS_READ(brdcfg[5]); - brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK); - brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL); - QIXIS_WRITE(brdcfg[5], brdcfg5); - - brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT | - BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1; - QIXIS_WRITE(brdcfg[7], brdcfg7); -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - board_config_serdes_mux(); - board_config_usb_mux(); - - return 0; -} - -static const char *serdes_clock_to_string(u32 clock) -{ - switch (clock) { - case SRDS_PLLCR0_RFCK_SEL_100: - return "100"; - case SRDS_PLLCR0_RFCK_SEL_125: - return "125"; - case SRDS_PLLCR0_RFCK_SEL_156_25: - return "156.25"; - default: - return "150"; - } -} - -#define NUM_SRDS_BANKS 3 - -int misc_init_r(void) -{ - serdes_corenet_t *srds_regs; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (2 * i)) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 3: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - default: - printf("Warning: SDREFCLK%u switch setting of '10' is " - "unsupported\n", i + 1); - break; - } - } - - srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0); - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -/* - * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v, - * 18 means CVDD is 1.8v. - */ -static u8 IO_VSEL[] = { - 33, 33, 33, 25, 25, 25, 18, 18, 18, - 33, 33, 33, 25, 25, 25, 18, 18, 18, - 33, 33, 33, 25, 25, 25, 18, 18, 18, - 33, 33, 33, 33, 33 -}; - -#define IO_VSEL_MASK 0x1f - -/* - * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD, - * then set status of spi flash nodes to 'disabled' according to CVDD. - * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi - * flash2, CVDD '18' will select spi flash3. - */ -void fdt_fixup_board_spi(void *blob) -{ - u8 sw5 = QIXIS_READ(dutcfg[3]); - - switch (IO_VSEL[sw5 & IO_VSEL_MASK]) { - /* 3.3v */ - case 33: - do_fixup_by_compat(blob, "atmel,at45db081d", "status", - "disabled", strlen("disabled") + 1, 1); - do_fixup_by_compat(blob, "spansion,sst25wf040", "status", - "disabled", strlen("disabled") + 1, 1); - break; - /* 2.5v */ - case 25: - do_fixup_by_compat(blob, "spansion,s25sl12801", "status", - "disabled", strlen("disabled") + 1, 1); - do_fixup_by_compat(blob, "spansion,en25q32", "status", - "disabled", strlen("disabled") + 1, 1); - do_fixup_by_compat(blob, "spansion,sst25wf040", "status", - "disabled", strlen("disabled") + 1, 1); - break; - /* 1.8v */ - case 18: - do_fixup_by_compat(blob, "spansion,s25sl12801", "status", - "disabled", strlen("disabled") + 1, 1); - do_fixup_by_compat(blob, "spansion,en25q32", "status", - "disabled", strlen("disabled") + 1, 1); - do_fixup_by_compat(blob, "atmel,at45db081d", "status", - "disabled", strlen("disabled") + 1, 1); - break; - } -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) - fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fdt_fixup_dr_usb(blob, bd); - fdt_fixup_board_spi(blob); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_board_enet(blob); -#endif -} diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h deleted file mode 100644 index 4d5d6a25ebe..00000000000 --- a/board/freescale/p3060qds/p3060qds_qixis.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __P3060QDS_QIXIS_H__ -#define __P3060QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for P3060QDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EC_MODE_MASK 0x0F -#define BRDCFG4_EC2_MII_EC1_MII 0x00 -#define BRDCFG4_EC2_MII_EC1_USB 0x03 -#define BRDCFG4_EC2_USB_EC1_MII 0x0C -#define BRDCFG4_EC2_USB_EC1_USB 0x0F -#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E -#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B -#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A -#define BRDCFG4_EMISEL_MASK 0xF0 - -#define BRDCFG5_ECLKS_MASK 0x80 -#define BRDCFG5_USB1ID_MASK 0x40 -#define BRDCFG5_USB2ID_MASK 0x20 -#define BRDCFG5_GC2MX_MASK 0x0C -#define BRDCFG5_T15MX_MASK 0x03 -#define BRDCFG5_ECLKS_IEEE1588_CM 0x80 -#define BRDCFG5_USB1ID_CTRL 0x40 -#define BRDCFG5_USB2ID_CTRL 0x20 - -#define BRDCFG6_SD1MX_A 0x01 -#define BRDCFG6_SD1MX_B 0x00 -#define BRDCFG6_SD2MX_A 0x02 -#define BRDCFG6_SD2MX_B 0x00 -#define BRDCFG6_SD3MX_A 0x04 -#define BRDCFG6_SD3MX_B 0x00 -#define BRDCFG6_SD4MX_A 0x08 -#define BRDCFG6_SD4MX_B 0x00 - -#define BRDCFG7_JTAGMX_MASK 0xC0 -#define BRDCFG7_IQ1MX_MASK 0x20 -#define BRDCFG7_G1MX_MASK 0x10 -#define BRDCFG7_D1MX_MASK 0x0C -#define BRDCFG7_I3MX_MASK 0x03 -#define BRDCFG7_JTAGMX_AURORA 0x00 -#define BRDCFG7_JTAGMX_FPGA 0x80 -#define BRDCFG7_JTAGMX_COP_JTAG 0xC0 -#define BRDCFG7_IQ1MX_IRQ_EVT 0x00 -#define BRDCFG7_IQ1MX_USB2 0x20 -#define BRDCFG7_G1MX_USB1 0x00 -#define BRDCFG7_G1MX_TSEC3 0x10 -#define BRDCFG7_D1MX_DMA 0x00 -#define BRDCFG7_D1MX_TSEC3USB 0x04 -#define BRDCFG7_D1MX_HDLC2 0x08 -#define BRDCFG7_I3MX_UART2_I2C34 0x00 -#define BRDCFG7_I3MX_GPIO_EVT 0x01 -#define BRDCFG7_I3MX_USB1 0x02 -#define BRDCFG7_I3MX_TSEC3 0x03 - -#endif diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile index bd2174fec32..f95356f16d2 100644 --- a/board/genesi/mx51_efikamx/Makefile +++ b/board/genesi/mx51_efikamx/Makefile @@ -27,11 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := efikamx.o - -ifdef CONFIG_CMD_USB -COBJS += efikamx-usb.o -endif +COBJS := efikamx.o efikamx-usb.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index e9273d027a0..cf020c35cb6 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -214,3 +214,15 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) if (port) mdelay(10); } + +/* + * Ethernet on the Smarttop is on the USB bus. Rather than give an error about + * "CPU Net Initialization Failed", just pass this test since no other settings + * are required. Smartbook doesn't have built-in Ethernet but we will let it + * pass anyway considering someone may have plugged in a USB stick and all + * they need to do is run "usb start". + */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 6d98c94db91..cfd2e938b94 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -492,9 +492,6 @@ int board_late_init(void) ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb(); - if (machine_is_efikasb()) - setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); - return 0; } diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index 9bc3c21c9c6..eaa924f0e6a 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -163,7 +163,7 @@ static int ivm_findinventorystring(int type, if (addr == INVENTORYDATASIZE) { xcode = -1; printf("Error end of string not found\n"); - } else if ((size >= (maxlen - 1)) && + } else if ((size > (maxlen - 1)) && (buf[addr] != '\r')) { xcode = -1; printf("string too long till next CR\n"); diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 930c80e7c2a..be8f51c2fc4 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -331,26 +331,6 @@ void board_spi_release_bus(struct spi_slave *slave) kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); } -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - /* Fix this */ - gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), - kw_sdram_bs(0)); - return 0; -} - -void dram_init_banksize(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), - kw_sdram_bs(i)); - } -} - #if (defined(CONFIG_KM_PIGGY4_88E6061)) #define PHY_LED_SEL_REG 0x18 diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 7ab20408e86..afe832a5295 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -45,8 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; -const struct tegra20_sysinfo sysinfo = { - CONFIG_TEGRA20_BOARD_STRING +const struct tegra_sysinfo sysinfo = { + CONFIG_TEGRA_BOARD_STRING }; #ifndef CONFIG_SPL_BUILD @@ -79,7 +79,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); static void power_det_init(void) { #if defined(CONFIG_TEGRA20) - struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE; + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; /* turn off power detects */ writel(0, &pmc->pmc_pwr_det_latch); @@ -132,7 +132,7 @@ int board_init(void) board_usb_init(gd->fdt_blob); #endif -#ifdef CONFIG_TEGRA20_LP0 +#ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ warmboot_save_sdram_params(); diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index c3519543011..ca5facb7fe7 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -54,4 +54,14 @@ usb@c5004000 { status = "disabled"; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 335253953b2..25a63a05d0c 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -153,4 +153,14 @@ 0x1f04008a>; linux,fn-keymap = <0x05040002>; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index b6efa1c29a0..88b9dcf0305 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 44977c78d1d..b4a811dc5f9 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init SD slot J26\n"); /* init dev 0, SD slot J26, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); + tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); debug("board_mmc_init: init SD slot J5\n"); /* init dev 2, SD slot J5, with 4-bit bus */ - tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); + tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); return 0; } diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index b6efa1c29a0..88b9dcf0305 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 3298a6b3a88..667f60a9bb9 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ - tegra20_mmc_init(0, 4, -1, -1); + tegra_mmc_init(0, 4, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 1, SD slot, with 4-bit bus */ - tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); + tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); return 0; } diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile index e3b7435530b..147d0bcf950 100644 --- a/board/nvidia/ventana/Makefile +++ b/board/nvidia/ventana/Makefile @@ -24,9 +24,7 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common $(obj)../seaboard) -endif +$(shell mkdir -p $(obj)../seaboard) LIB = $(obj)lib$(BOARD).o diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile index a910577f21a..913f1cea4a9 100644 --- a/board/nvidia/whistler/Makefile +++ b/board/nvidia/whistler/Makefile @@ -24,10 +24,6 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index c0a114d6677..598b2e5ce25 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd) pin_mux_mmc(); /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ - tegra20_mmc_init(0, 8, -1, -1); + tegra_mmc_init(0, 8, -1, -1); /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ - tegra20_mmc_init(1, 8, -1, -1); + tegra_mmc_init(1, 8, -1, -1); return 0; } diff --git a/board/qi/qi_lb60/qi_lb60.c b/board/qi/qi_lb60/qi_lb60.c index 3583d01c761..d9752096c18 100644 --- a/board/qi/qi_lb60/qi_lb60.c +++ b/board/qi/qi_lb60/qi_lb60.c @@ -69,7 +69,7 @@ static void gpio_init(void) static void cpm_init(void) { struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - uint32_t reg = readw(&cpm->clkgr); + uint32_t reg = readl(&cpm->clkgr); reg |= CPM_CLKGR_IPU | CPM_CLKGR_CIM | @@ -81,7 +81,7 @@ static void cpm_init(void) CPM_CLKGR_UDC | CPM_CLKGR_AIC1; - writew(reg, &cpm->clkgr); + writel(reg, &cpm->clkgr); } int board_early_init_f(void) diff --git a/board/freescale/p3060qds/Makefile b/board/samsung/common/Makefile index ae136f4626d..0bcd5949ad0 100644 --- a/board/freescale/p3060qds/Makefile +++ b/board/samsung/common/Makefile @@ -1,7 +1,6 @@ # -# Copyright 2011 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (C) 2012 Samsung Electronics +# Lukasz Majewski <l.majewski@samsung.com> # # See file CREDITS for list of people who contributed to this # project. @@ -24,26 +23,16 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o +LIB = $(obj)libsamsung.o -COBJS-y += $(BOARD).o -COBJS-y += ddr.o -COBJS-y += eth.o -COBJS-y += fixed_ddr.o +COBJS-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +SRCS := $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - ######################################################################### # defines $(obj).depend target diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c new file mode 100644 index 00000000000..d6c3d37bb79 --- /dev/null +++ b/board/samsung/common/multi_i2c.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Lukasz Majewski <l.majewski@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> + +/* Handle multiple I2C buses instances */ +int get_multi_scl_pin(void) +{ + unsigned int bus = I2C_GET_BUS(); + + switch (bus) { + case I2C_0: /* I2C_0 definition - compatibility layer */ + case I2C_5: + return CONFIG_SOFT_I2C_I2C5_SCL; + case I2C_9: + return CONFIG_SOFT_I2C_I2C9_SCL; + default: + printf("I2C_%d not supported!\n", bus); + }; + + return 0; +} + +int get_multi_sda_pin(void) +{ + unsigned int bus = I2C_GET_BUS(); + + switch (bus) { + case I2C_0: /* I2C_0 definition - compatibility layer */ + case I2C_5: + return CONFIG_SOFT_I2C_I2C5_SDA; + case I2C_9: + return CONFIG_SOFT_I2C_I2C9_SDA; + default: + printf("I2C_%d not supported!\n", bus); + }; + + return 0; +} + +int multi_i2c_init(void) +{ + return 0; +} diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 30a5835abb1..1effc9cdf5f 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -79,11 +79,7 @@ skip_check_didle: str r1, [r0, #0x0] @ GPIO_CON_OFFSET ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET -#ifdef CONFIG_ONENAND_IPL - orr r1, r1, #(1 << 1) @ 1 * 1-bit -#else bic r1, r1, #(1 << 1) -#endif str r1, [r0, #0x4] @ GPIO_DAT_OFFSET /* Don't setup at s5pc100 */ @@ -182,7 +178,6 @@ skip_check_didle: /* Do not release retention here for S5PC110 */ streq r1, [r0] -#ifndef CONFIG_ONENAND_IPL /* Disable Watchdog */ ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 @@ -193,7 +188,6 @@ skip_check_didle: ldrne r0, =S5PC110_SROMC_BASE ldr r1, =0x9 str r1, [r0] -#endif /* S5PC100 has 3 groups of interrupt sources */ ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 @@ -207,7 +201,6 @@ skip_check_didle: str r3, [r1, #0x14] @ INTENCLEAR str r3, [r2, #0x14] @ INTENCLEAR -#ifndef CONFIG_ONENAND_IPL /* Set all interrupts as IRQ */ str r5, [r0, #0xc] @ INTSELECT str r5, [r1, #0xc] @ INTSELECT @@ -217,120 +210,12 @@ skip_check_didle: str r5, [r0, #0xf00] @ INTADDRESS str r5, [r1, #0xf00] @ INTADDRESS str r5, [r2, #0xf00] @ INTADDRESS -#endif -#ifndef CONFIG_ONENAND_IPL /* for UART */ bl uart_asm_init bl internal_ram_init -#endif - -#ifdef CONFIG_ONENAND_IPL - /* init system clock */ - bl system_clock_init - - /* OneNAND Sync Read Support at S5PC110 only - * RM[15] : Sync Read - * BRWL[14:12] : 7 CLK - * BL[11:9] : Continuous - * VHF[3] : Very High Frequency Enable (Over 83MHz) - * HF[2] : High Frequency Enable (Over 66MHz) - * WM[1] : Sync Write - */ - cmp r7, r8 - ldrne r1, =0xE006 - ldrne r0, =0xB001E442 - strneh r1, [r0] - - /* - * GCE[26] : Gated Clock Enable - * RPE[17] : Enables Read Prefetch - */ - ldrne r1, =((1 << 26) | (1 << 17) | 0xE006) - ldrne r0, =0xB0600000 - strne r1, [r0, #0x100] @ ONENAND_IF_CTRL - ldrne r1, =0x1212 - strne r1, [r0, #0x108] - - /* Board detection to set proper memory configuration */ - cmp r7, r8 - moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ - movne r9, #2 /* r9 has 2Gib default at s5pc110 */ - - ldr r2, =0xE0200200 - ldr r4, [r2, #0x48] - - bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */ - bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */ - bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */ - str r1, [r2, #0x48] - /* For write completion */ - nop - nop - - ldr r3, [r2, #0x44] - and r1, r3, #(0x7 << 2) - mov r1, r1, lsr #2 - cmp r1, #0x5 - moveq r9, #3 - cmp r1, #0x6 - moveq r9, #1 - cmp r1, #0x7 - moveq r9, #2 - and r0, r3, #(0x1 << 1) - mov r0, r0, lsr #1 - orr r1, r1, r0, lsl #3 - cmp r1, #0x8 - moveq r9, #3 - and r1, r3, #(0x7 << 2) - mov r1, r1, lsr #2 - and r0, r3, #(0x1 << 7) - mov r0, r0, lsr #7 - orr r1, r1, r0, lsl #3 - cmp r1, #0x9 - moveq r9, #3 - str r4, [r2, #0x48] /* Restore PULLUP configuration */ - - bl mem_ctrl_asm_init - - /* Wakeup support. Don't know if it's going to be used, untested. */ - ldreq r0, =S5PC100_RST_STAT - ldrne r0, =S5PC110_RST_STAT - ldr r1, [r0] - biceq r1, r1, #0xfffffff7 - moveq r2, #(1 << 3) - bicne r1, r1, #0xfffeffff - movne r2, #(1 << 16) - cmp r1, r2 - bne 1f -wakeup: - /* turn off L2 cache */ - bl l2_cache_disable - - cmp r7, r8 - ldreq r0, =0xC100 - ldrne r0, =0xC110 - - /* invalidate L2 cache also */ - bl invalidate_dcache - - /* turn on L2 cache */ - bl l2_cache_enable - - cmp r7, r8 - /* Load return address and jump to kernel */ - ldreq r0, =S5PC100_INFORM0 - ldrne r0, =S5PC110_INFORM0 - - /* r1 = physical address of s5pc1xx_cpu_resume function */ - ldr r1, [r0] - /* Jump to kernel (sleep-s5pc1xx.S) */ - mov pc, r1 - nop - nop -#else cmp r7, r8 /* Clear wakeup status register */ ldreq r0, =S5PC100_WAKEUP_STAT @@ -347,7 +232,6 @@ wakeup: orr r1, r1, r2 str r1, [r0] -#endif b 1f didle_wakeup: @@ -517,7 +401,6 @@ system_clock_init: mov pc, lr -#ifndef CONFIG_ONENAND_IPL internal_ram_init: ldreq r0, =0xE3800000 ldrne r0, =0xF1500000 @@ -525,9 +408,7 @@ internal_ram_init: str r1, [r0] mov pc, lr -#endif -#ifndef CONFIG_ONENAND_IPL /* * uart_asm_init: Initialize UART's pins */ @@ -582,4 +463,3 @@ uart_asm_init: str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET 200: mov pc, lr -#endif diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 6d18835acc3..6f9a554d99c 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -50,12 +50,10 @@ lowlevel_init: orr r0, r0, #0x0 str r5, [r0] -#ifndef CONFIG_ONENAND_IPL /* setting SRAM */ ldr r0, =S5PC100_SROMC_BASE ldr r1, =0x9 str r1, [r0] -#endif /* S5PC100 has 3 groups of interrupt sources */ ldr r0, =S5PC100_VIC0_BASE @0xE4000000 @@ -68,7 +66,6 @@ lowlevel_init: str r3, [r1, #0x14] @INTENCLEAR str r3, [r2, #0x14] @INTENCLEAR -#ifndef CONFIG_ONENAND_IPL /* Set all interrupts as IRQ */ str r5, [r0, #0xc] @INTSELECT str r5, [r1, #0xc] @INTSELECT @@ -78,54 +75,17 @@ lowlevel_init: str r5, [r0, #0xf00] @INTADDRESS str r5, [r1, #0xf00] @INTADDRESS str r5, [r2, #0xf00] @INTADDRESS -#endif -#ifndef CONFIG_ONENAND_IPL /* for UART */ bl uart_asm_init /* for TZPC */ bl tzpc_asm_init -#endif - -#ifdef CONFIG_ONENAND_IPL - /* init system clock */ - bl system_clock_init - - bl mem_ctrl_asm_init - - /* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =S5PC100_RST_STAT - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset -#endif 1: mov lr, r9 mov pc, lr -#ifdef CONFIG_ONENAND_IPL -wakeup_reset: - - /* Clear wakeup status register */ - ldr r0, =S5PC100_WAKEUP_STAT - ldr r1, [r0] - str r1, [r0] - - /* Load return address and jump to kernel */ - ldr r0, =S5PC100_INFORM0 - - /* r1 = physical address of s5pc100_cpu_resume function */ - ldr r1, [r0] - - /* Jump to kernel (sleep.S) */ - mov pc, r1 - nop - nop -#endif - /* * system_clock_init: Initialize core clock and bus clock. * void system_clock_init(void) @@ -178,7 +138,6 @@ system_clock_init: mov pc, lr -#ifndef CONFIG_ONENAND_IPL /* * uart_asm_init: Initialize UART's pins */ @@ -212,4 +171,3 @@ tzpc_asm_init: str r1, [r0, #0x810] mov pc, lr -#endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 4f9cb5a7e5b..e11a8922fca 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -75,6 +75,21 @@ int board_init(void) return 0; } +void i2c_init_board(void) +{ + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + + /* I2C_5 -> PMIC */ + s5p_gpio_direction_output(&gpio1->b, 7, 1); + s5p_gpio_direction_output(&gpio1->b, 6, 1); + /* I2C_9 -> FG */ + s5p_gpio_direction_output(&gpio2->y4, 0, 1); + s5p_gpio_direction_output(&gpio2->y4, 1, 1); +} + int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c index 5e07bf8d4e2..06df0af06f3 100644 --- a/board/taskit/stamp9g20/stamp9g20.c +++ b/board/taskit/stamp9g20/stamp9g20.c @@ -159,15 +159,28 @@ int board_early_init_f(void) return 0; } -int board_init(void) +int board_postclk_init(void) { - /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* + * Initialize the serial interface here, because be need a running + * timer to set PC9 to high and wait for some time to enable the + * level converter of the RS232 interface on the PortuxG20 board. + */ - /* Enable the serial interface */ +#ifdef CONFIG_PORTUXG20 at91_set_gpio_output(AT91_PIN_PC9, 1); + mdelay(1); +#endif at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + stamp9G20_nand_hw_init(); #ifdef CONFIG_MACB stamp9G20_macb_hw_init(); diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index c2b10ac1eaa..7429e934fde 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -100,8 +100,18 @@ int board_init(void) int misc_init_r(void) { + char *eth_addr; + dieid_num_r(); + eth_addr = getenv("ethaddr"); + if (eth_addr) + return 0; + +#ifndef CONFIG_SPL_BUILD + TAM3517_READ_MAC_FROM_EEPROM; +#endif + return 0; } diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 9fbaedd7920..b8ad4471f52 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -21,13 +21,17 @@ #include <common.h> #include <netdev.h> +#include <malloc.h> #include <fpga.h> +#include <video_fb.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/omap_gpio.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/dss.h> +#include <asm/arch/clocks.h> #include <i2c.h> #include <spartan3.h> #include <asm/gpio.h> @@ -39,6 +43,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BUZZER 140 +#define SPEAKER 141 + #ifndef CONFIG_FPGA #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" #endif @@ -50,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_INIT 119 #define FPGA_DONE 154 +#define LCD_PWR 138 +#define LCD_PON_PIN 139 + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct { + u32 xres; + u32 yres; +} panel_resolution[] = { + { 480, 272 }, + { 800, 480 } +}; + +static struct panel_config lcd_cfg[] = { + { + .timing_h = PANEL_TIMING_H(4, 8, 41), + .timing_v = PANEL_TIMING_V(2, 4, 10), + .pol_freq = 0x00000000, /* Pol Freq */ + .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + }, + { + .timing_h = PANEL_TIMING_H(20, 192, 4), + .timing_v = PANEL_TIMING_V(2, 20, 10), + .pol_freq = 0x00004000, /* Pol Freq */ + .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + } +}; +#endif + /* Timing definitions for FPGA */ static const u32 gpmc_fpga[] = { FPGA_GPMC_CONFIG1, @@ -193,6 +236,33 @@ int board_init(void) mt_ventoux_init_fpga(); + /* GPIO_140: speaker #mute */ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) + /* GPIO_141: Buzz Hi */ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) + + /* Turning off the buzzer */ + gpio_request(BUZZER, "BUZZER_MUTE"); + gpio_request(SPEAKER, "SPEAKER"); + gpio_direction_output(BUZZER, 0); + gpio_direction_output(SPEAKER, 0); + + return 0; +} + +int misc_init_r(void) +{ + char *eth_addr; + + dieid_num_r(); + + eth_addr = getenv("ethaddr"); + if (eth_addr) + return 0; + +#ifndef CONFIG_SPL_BUILD + TAM3517_READ_MAC_FROM_EEPROM; +#endif return 0; } @@ -224,3 +294,46 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0); } #endif + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +int board_video_init(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct panel_config *panel = &lcd_cfg[0]; + char *s; + u32 index = 0; + + void *fb; + + fb = (void *)0x88000000; + + s = getenv("panel"); + if (s) { + index = simple_strtoul(s, NULL, 10); + if (index < ARRAY_SIZE(lcd_cfg)) + panel = &lcd_cfg[index]; + else + return 0; + } + + panel->frame_buffer = fb; + printf("Panel: %dx%d\n", panel_resolution[index].xres, + panel_resolution[index].yres); + panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | + (panel_resolution[index].xres - 1); + + gpio_request(LCD_PWR, "LCD Power"); + gpio_request(LCD_PON_PIN, "LCD Pon"); + gpio_direction_output(LCD_PWR, 0); + gpio_direction_output(LCD_PON_PIN, 1); + + + setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); + + omap3_dss_panel_config(panel); + omap3_dss_enable(); + + return 0; +} +#endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h index 9b2e43ec6f0..1cd7ec2ab29 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.h +++ b/board/teejet/mt_ventoux/mt_ventoux.h @@ -142,7 +142,8 @@ const omap3_sysinfo sysinfo = { /*GPIO_62: FPGA_RESET */ \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/ \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ + /* GPIO_64*/ \ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ /* DSS */\ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ @@ -174,26 +175,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ @@ -209,6 +190,7 @@ const omap3_sysinfo sysinfo = { /* GPIO_126: CardDetect */\ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + /*GPIO_128 */ \ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ \ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ @@ -221,7 +203,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ /* GPIO_138: LCD_ENVD */\ - MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \ /* GPIO_139: LCD_PON */\ /* McBSP */\ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ @@ -241,16 +223,12 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ /* GPIO_119: FPGA_INIT */ \ \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ - /* GPIO_140: speaker #mute */\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ - /* GPIO_141: Buzz Hi */\ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ \ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ /*GPIO_152: Ignition Sense */ \ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) \ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ /*GPIO_153: Power Button Sense */ \ MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ /* GPIO_154: FPGA_DONE */ \ @@ -264,10 +242,14 @@ const omap3_sysinfo sysinfo = { /* GPIO_150: USB status 1 */\ \ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ + /* gpt9_pwm */\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ + /* gpt10_pwm */\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ + /* gpt8_pwm */\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ + /* gpt11_pwm */\ \ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ /*GPIO_163 : TS_PENIRQ*/ \ @@ -299,22 +281,24 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ + /* GPIO94 */\ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ /* GPIO95: #Enable Output */\ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ /* GPIO 99: #SOM_PWR_OFF */\ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ /* GPIO_100: #power out */\ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ + /* GPIO_102 */\ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ /* RMII */\ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ @@ -363,7 +347,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ \ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ + /* gpio_10 */\ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ /* JTAG */\ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ @@ -387,12 +372,15 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ + /* gpio_24 */\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + /* gpio_26 */\ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) \ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* gpio_29 */\ /* Die to Die */\ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index a1e2bfee872..b75e62c715d 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -28,6 +28,7 @@ #include <common.h> #include <config.h> #include <netdev.h> +#include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -69,6 +70,14 @@ int fsl_init2 (void) { } #endif +void board_init(void) +{ + gpio_init(); +#ifdef CONFIG_SYS_FSL_2 + fsl_init2(); +#endif +} + int board_eth_init(bd_t *bis) { int ret = 0; diff --git a/boards.cfg b/boards.cfg index 72e78034425..f789539e858 100644 --- a/boards.cfg +++ b/boards.cfg @@ -50,7 +50,6 @@ tt01 arm arm1136 - hale imx31_litekit arm arm1136 - logicpd mx31 flea3 arm arm1136 - CarMediaLab mx35 mx35pdk arm arm1136 - freescale mx35 -apollon arm arm1136 apollon - omap24xx omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x rpi_b arm arm1176 rpi_b raspberrypi bcm2835 @@ -60,7 +59,8 @@ integratorcp_cm920t arm arm920t integrator armltd a320evb arm arm920t - faraday a320 at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT -eb_cpux9k2 arm arm920t - BuS at91 +eb_cpux9k2 arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2 +eb_cpux9k2_ram arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2:RAMBOOT cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91 cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT mx1ads arm arm920t - - imx @@ -302,6 +302,7 @@ tec arm armv7:arm720t tec avionic paz00 arm armv7:arm720t paz00 compal tegra20 trimslice arm armv7:arm720t trimslice compulab tegra20 atngw100 avr32 at32ap - atmel at32ap700x +atngw100mkii avr32 at32ap - atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x atstk1004 avr32 at32ap atstk1000 atmel at32ap700x @@ -389,7 +390,8 @@ M5485FFE m68k mcf547x_8x m548xevb freescale - M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx -qemu_mips mips mips32 qemu-mips - - qemu-mips +qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN +qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND @@ -807,29 +809,24 @@ P2041RDB_NAND powerpc mpc85xx p2041rdb freescale P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P3041DS powerpc mpc85xx corenet_ds freescale P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER -P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -P3060QDS powerpc mpc85xx p3060qds freescale -P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT +P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER -P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER -P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/common/Makefile b/common/Makefile index 57da76f9089..b56df1d588b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o COBJS-y += s_record.o COBJS-$(CONFIG_SERIAL_MULTI) += serial.o COBJS-y += xyzModem.o +COBJS-y += cmd_disk.o # core command COBJS-y += cmd_boot.o @@ -86,7 +87,13 @@ COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += cmd_eeprom.o COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o +COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o +ifdef CONFIG_CMD_EXT4 +COBJS-y += cmd_ext_common.o +else +COBJS-$(CONFIG_CMD_EXT2) += cmd_ext_common.o +endif COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o @@ -129,6 +136,7 @@ COBJS-$(CONFIG_CMD_NAND) += cmd_nand.o COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o +COBJS-$(CONFIG_CMD_PART) += cmd_part.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 42f08fdd0d9..23bd8a5098a 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -216,15 +216,15 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) print_num("flashstart ", bd->bi_flashstart); print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE); print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR); - printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE, + printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN); - printf("CONFIG_SYS_MALLOC_BASE = 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE, + printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); - printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET, + printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET, CONFIG_SYS_STACK_SIZE); - printf("CONFIG_SYS_PROM_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET, + printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET, CONFIG_SYS_PROM_SIZE); - printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET, + printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET, GENERATED_GBL_DATA_SIZE); #if defined(CONFIG_CMD_NET) diff --git a/common/cmd_disk.c b/common/cmd_disk.c new file mode 100644 index 00000000000..ee4e21551b1 --- /dev/null +++ b/common/cmd_disk.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2011 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <command.h> +#include <part.h> + +#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_SCSI) || \ + defined(CONFIG_USB_STORAGE) +int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, + char *const argv[]) +{ + int dev, part; + ulong addr = CONFIG_SYS_LOAD_ADDR; + ulong cnt; + disk_partition_t info; + image_header_t *hdr; + block_dev_desc_t *dev_desc; + +#if defined(CONFIG_FIT) + const void *fit_hdr = NULL; +#endif + + bootstage_mark(BOOTSTAGE_ID_IDE_START); + if (argc > 3) { + bootstage_error(BOOTSTAGE_ID_IDE_ADDR); + return CMD_RET_USAGE; + } + bootstage_mark(BOOTSTAGE_ID_IDE_ADDR); + + if (argc > 1) + addr = simple_strtoul(argv[1], NULL, 16); + + bootstage_mark(BOOTSTAGE_ID_IDE_BOOT_DEVICE); + + part = get_device_and_partition(intf, (argc == 3) ? argv[2] : NULL, + &dev_desc, &info, 1); + if (part < 0) { + bootstage_error(BOOTSTAGE_ID_IDE_TYPE); + return 1; + } + + dev = dev_desc->dev; + bootstage_mark(BOOTSTAGE_ID_IDE_TYPE); + + printf("\nLoading from %s device %d, partition %d: " + "Name: %.32s Type: %.32s\n", intf, dev, part, info.name, + info.type); + + debug("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", + info.start, info.size, info.blksz); + + if (dev_desc->block_read(dev, info.start, 1, (ulong *) addr) != 1) { + printf("** Read error on %d:%d\n", dev, part); + bootstage_error(BOOTSTAGE_ID_IDE_PART_READ); + return 1; + } + bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ); + + switch (genimg_get_format((void *) addr)) { + case IMAGE_FORMAT_LEGACY: + hdr = (image_header_t *) addr; + + bootstage_mark(BOOTSTAGE_ID_IDE_FORMAT); + + if (!image_check_hcrc(hdr)) { + puts("\n** Bad Header Checksum **\n"); + bootstage_error(BOOTSTAGE_ID_IDE_CHECKSUM); + return 1; + } + bootstage_mark(BOOTSTAGE_ID_IDE_CHECKSUM); + + image_print_contents(hdr); + + cnt = image_get_image_size(hdr); + break; +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + fit_hdr = (const void *) addr; + puts("Fit image detected...\n"); + + cnt = fit_get_size(fit_hdr); + break; +#endif + default: + bootstage_error(BOOTSTAGE_ID_IDE_FORMAT); + puts("** Unknown image type\n"); + return 1; + } + + cnt += info.blksz - 1; + cnt /= info.blksz; + cnt -= 1; + + if (dev_desc->block_read(dev, info.start + 1, cnt, + (ulong *)(addr + info.blksz)) != cnt) { + printf("** Read error on %d:%d\n", dev, part); + bootstage_error(BOOTSTAGE_ID_IDE_READ); + return 1; + } + bootstage_mark(BOOTSTAGE_ID_IDE_READ); + +#if defined(CONFIG_FIT) + /* This cannot be done earlier, + * we need complete FIT image in RAM first */ + if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format(fit_hdr)) { + bootstage_error(BOOTSTAGE_ID_IDE_FIT_READ); + puts("** Bad FIT image format\n"); + return 1; + } + bootstage_mark(BOOTSTAGE_ID_IDE_FIT_READ_OK); + fit_print_contents(fit_hdr); + } +#endif + + flush_cache(addr, (cnt+1)*info.blksz); + + /* Loading ok, update default load address */ + load_addr = addr; + + return bootm_maybe_autostart(cmdtp, argv[0]); +} +#endif diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 79b1e2fb62f..c27d9c7edeb 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -1,4 +1,9 @@ /* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * (C) Copyright 2004 * esd gmbh <www.esd-electronics.com> * Reinhard Arlt <reinhard.arlt@esd-electronics.com> @@ -33,225 +38,35 @@ * Ext2fs support */ #include <common.h> -#include <part.h> -#include <config.h> -#include <command.h> -#include <image.h> -#include <linux/ctype.h> -#include <asm/byteorder.h> -#include <ext2fs.h> -#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) -#include <usb.h> -#endif - -#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION) -#error DOS or EFI partition support must be selected -#endif - -/* #define EXT2_DEBUG */ - -#ifdef EXT2_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif +#include <ext_common.h> int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *filename = "/"; - int dev=0; - int part=1; - char *ep; - block_dev_desc_t *dev_desc=NULL; - int part_length; - - if (argc < 3) - return CMD_RET_USAGE; - - dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - - if (dev_desc == NULL) { - printf ("\n** Block device %s %d not supported\n", argv[1], dev); - return 1; - } - - if (*ep) { - if (*ep != ':') { - puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } - - if (argc == 4) - filename = argv[3]; - - PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename); - - if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) { - printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); - ext2fs_close(); - return 1; - } - - if (!ext2fs_mount(part_length)) { - printf ("** Bad ext2 partition or disk - %s %d:%d **\n", argv[1], dev, part); - ext2fs_close(); - return 1; - } - - if (ext2fs_ls (filename)) { - printf ("** Error ext2fs_ls() **\n"); - ext2fs_close(); - return 1; - }; - - ext2fs_close(); + if (do_ext_ls(cmdtp, flag, argc, argv)) + return -1; return 0; } -U_BOOT_CMD( - ext2ls, 4, 1, do_ext2ls, - "list files in a directory (default /)", - "<interface> <dev[:part]> [directory]\n" - " - list files from 'dev' on 'interface' in a 'directory'" -); - /****************************************************************************** * Ext2fs boot command intepreter. Derived from diskboot */ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *filename = NULL; - char *ep; - int dev, part = 1; - ulong addr = 0, part_length; - int filelen; - disk_partition_t info; - block_dev_desc_t *dev_desc = NULL; - char buf [12]; - unsigned long count; - char *addr_str; - - switch (argc) { - case 3: - addr_str = getenv("loadaddr"); - if (addr_str != NULL) - addr = simple_strtoul (addr_str, NULL, 16); - else - addr = CONFIG_SYS_LOAD_ADDR; - - filename = getenv ("bootfile"); - count = 0; - break; - case 4: - addr = simple_strtoul (argv[3], NULL, 16); - filename = getenv ("bootfile"); - count = 0; - break; - case 5: - addr = simple_strtoul (argv[3], NULL, 16); - filename = argv[4]; - count = 0; - break; - case 6: - addr = simple_strtoul (argv[3], NULL, 16); - filename = argv[4]; - count = simple_strtoul (argv[5], NULL, 16); - break; - - default: - return CMD_RET_USAGE; - } - - if (!filename) { - puts ("** No boot file defined **\n"); - return 1; - } - - dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - if (dev_desc==NULL) { - printf ("** Block device %s %d not supported\n", argv[1], dev); - return 1; - } - if (*ep) { - if (*ep != ':') { - puts ("** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } - - PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part); - - if (part != 0) { - if (get_partition_info (dev_desc, part, &info)) { - printf ("** Bad partition %d **\n", part); - return 1; - } - - if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { - printf ("** Invalid partition type \"%.32s\"" - " (expect \"" BOOT_PART_TYPE "\")\n", - info.type); - return 1; - } - printf ("Loading file \"%s\" " - "from %s device %d:%d (%.32s)\n", - filename, - argv[1], dev, part, info.name); - } else { - printf ("Loading file \"%s\" from %s device %d\n", - filename, argv[1], dev); - } - - - if ((part_length = ext2fs_set_blk_dev(dev_desc, part)) == 0) { - printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); - ext2fs_close(); - return 1; - } - - if (!ext2fs_mount(part_length)) { - printf ("** Bad ext2 partition or disk - %s %d:%d **\n", - argv[1], dev, part); - ext2fs_close(); - return 1; - } - - filelen = ext2fs_open(filename); - if (filelen < 0) { - printf("** File not found %s\n", filename); - ext2fs_close(); - return 1; - } - if ((count < filelen) && (count != 0)) { - filelen = count; - } - - if (ext2fs_read((char *)addr, filelen) != filelen) { - printf("** Unable to read \"%s\" from %s %d:%d **\n", - filename, argv[1], dev, part); - ext2fs_close(); - return 1; - } - - ext2fs_close(); - - /* Loading ok, update default load address */ - load_addr = addr; - - printf ("%d bytes read\n", filelen); - sprintf(buf, "%X", filelen); - setenv("filesize", buf); + if (do_ext_load(cmdtp, flag, argc, argv)) + return -1; return 0; } U_BOOT_CMD( + ext2ls, 4, 1, do_ext2ls, + "list files in a directory (default /)", + "<interface> <dev[:part]> [directory]\n" + " - list files from 'dev' on 'interface' in a 'directory'" +); + +U_BOOT_CMD( ext2load, 6, 0, do_ext2load, "load binary file from a Ext2 filesystem", "<interface> <dev[:part]> [addr] [filename] [bytes]\n" diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c new file mode 100644 index 00000000000..ca4656184cb --- /dev/null +++ b/common/cmd_ext4.c @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Ext4fs support + * made from existing cmd_ext2.c file of Uboot + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * made from cmd_reiserfs by + * + * (C) Copyright 2003 - 2004 + * Sysgo Real-Time Solutions, AG <www.elinos.com> + * Pavel Bartusek <pba@sysgo.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Changelog: + * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c + * file in uboot. Added ext4fs ls load and write support. + */ + +#include <common.h> +#include <part.h> +#include <config.h> +#include <command.h> +#include <image.h> +#include <linux/ctype.h> +#include <asm/byteorder.h> +#include <ext_common.h> +#include <ext4fs.h> +#include <linux/stat.h> +#include <malloc.h> + +#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) +#include <usb.h> +#endif + +int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (do_ext_load(cmdtp, flag, argc, argv)) + return -1; + + return 0; +} + +int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if (do_ext_ls(cmdtp, flag, argc, argv)) + return -1; + + return 0; +} + +#if defined(CONFIG_CMD_EXT4_WRITE) +int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + const char *filename = "/"; + int dev, part; + unsigned long ram_address; + unsigned long file_size; + disk_partition_t info; + block_dev_desc_t *dev_desc; + + if (argc < 6) + return cmd_usage(cmdtp); + + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) + return 1; + + dev = dev_desc->dev; + + /* get the filename */ + filename = argv[3]; + + /* get the address in hexadecimal format (string to int) */ + ram_address = simple_strtoul(argv[4], NULL, 16); + + /* get the filesize in base 10 format */ + file_size = simple_strtoul(argv[5], NULL, 10); + + /* set the device as block device */ + ext4fs_set_blk_dev(dev_desc, &info); + + /* mount the filesystem */ + if (!ext4fs_mount(info.size)) { + printf("Bad ext4 partition %s %d:%lu\n", argv[1], dev, part); + goto fail; + } + + /* start write */ + if (ext4fs_write(filename, (unsigned char *)ram_address, file_size)) { + printf("** Error ext4fs_write() **\n"); + goto fail; + } + ext4fs_close(); + + return 0; + +fail: + ext4fs_close(); + + return 1; +} + +U_BOOT_CMD(ext4write, 6, 1, do_ext4_write, + "create a file in the root directory", + "<interface> <dev[:part]> [Absolute filename path] [Address] [sizebytes]\n" + " - create a file in / directory"); + +#endif + +U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls, + "list files in a directory (default /)", + "<interface> <dev[:part]> [directory]\n" + " - list files from 'dev' on 'interface' in a 'directory'"); + +U_BOOT_CMD(ext4load, 6, 0, do_ext4_load, + "load binary file from a Ext4 filesystem", + "<interface> <dev[:part]> [addr] [filename] [bytes]\n" + " - load binary file 'filename' from 'dev' on 'interface'\n" + " to address 'addr' from ext4 filesystem"); diff --git a/common/cmd_ext_common.c b/common/cmd_ext_common.c new file mode 100644 index 00000000000..1952f4d1e14 --- /dev/null +++ b/common/cmd_ext_common.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT2/4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Ext4fs support + * made from existing cmd_ext2.c file of Uboot + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * made from cmd_reiserfs by + * + * (C) Copyright 2003 - 2004 + * Sysgo Real-Time Solutions, AG <www.elinos.com> + * Pavel Bartusek <pba@sysgo.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Changelog: + * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c + * file in uboot. Added ext4fs ls load and write support. + */ + +#include <common.h> +#include <part.h> +#include <config.h> +#include <command.h> +#include <image.h> +#include <linux/ctype.h> +#include <asm/byteorder.h> +#include <ext_common.h> +#include <ext4fs.h> +#include <linux/stat.h> +#include <malloc.h> + +#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) +#include <usb.h> +#endif + +#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION) +#error DOS or EFI partition support must be selected +#endif + +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_FS_TYPE_OFFSET 0x36 +#define DOS_FS32_TYPE_OFFSET 0x52 + +int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + char *filename = NULL; + int dev, part; + ulong addr = 0; + int filelen; + disk_partition_t info; + block_dev_desc_t *dev_desc; + char buf[12]; + unsigned long count; + const char *addr_str; + + count = 0; + addr = simple_strtoul(argv[3], NULL, 16); + filename = getenv("bootfile"); + switch (argc) { + case 3: + addr_str = getenv("loadaddr"); + if (addr_str != NULL) + addr = simple_strtoul(addr_str, NULL, 16); + else + addr = CONFIG_SYS_LOAD_ADDR; + + break; + case 4: + break; + case 5: + filename = argv[4]; + break; + case 6: + filename = argv[4]; + count = simple_strtoul(argv[5], NULL, 16); + break; + + default: + return cmd_usage(cmdtp); + } + + if (!filename) { + puts("** No boot file defined **\n"); + return 1; + } + + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) + return 1; + + dev = dev_desc->dev; + printf("Loading file \"%s\" from %s device %d%c%c\n", + filename, argv[1], dev, + part ? ':' : ' ', part ? part + '0' : ' '); + + ext4fs_set_blk_dev(dev_desc, &info); + + if (!ext4fs_mount(info.size)) { + printf("** Bad ext2 partition or disk - %s %d:%d **\n", + argv[1], dev, part); + ext4fs_close(); + goto fail; + } + + filelen = ext4fs_open(filename); + if (filelen < 0) { + printf("** File not found %s\n", filename); + ext4fs_close(); + goto fail; + } + if ((count < filelen) && (count != 0)) + filelen = count; + + if (ext4fs_read((char *)addr, filelen) != filelen) { + printf("** Unable to read \"%s\" from %s %d:%d **\n", + filename, argv[1], dev, part); + ext4fs_close(); + goto fail; + } + + ext4fs_close(); + /* Loading ok, update default load address */ + load_addr = addr; + + printf("%d bytes read\n", filelen); + sprintf(buf, "%X", filelen); + setenv("filesize", buf); + + return 0; +fail: + return 1; +} + +int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const char *filename = "/"; + int dev; + int part; + block_dev_desc_t *dev_desc; + disk_partition_t info; + + if (argc < 2) + return cmd_usage(cmdtp); + + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) + return 1; + + if (argc == 4) + filename = argv[3]; + + dev = dev_desc->dev; + ext4fs_set_blk_dev(dev_desc, &info); + + if (!ext4fs_mount(info.size)) { + printf("** Bad ext2 partition or disk - %s %d:%d **\n", + argv[1], dev, part); + ext4fs_close(); + goto fail; + } + + if (ext4fs_ls(filename)) { + printf("** Error extfs_ls() **\n"); + ext4fs_close(); + goto fail; + }; + + ext4fs_close(); + return 0; + +fail: + return 1; +} diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 559a16d6195..01e02f5b2bb 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -40,29 +40,20 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned long count; char buf [12]; block_dev_desc_t *dev_desc=NULL; - int dev=0; - int part=1; - char *ep; + disk_partition_t info; + int part, dev; if (argc < 5) { - printf( "usage: fatload <interface> <dev[:part]> " + printf("usage: fatload <interface> [<dev[:part]>] " "<addr> <filename> [bytes]\n"); return 1; } - dev = (int)simple_strtoul(argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - if (dev_desc == NULL) { - puts("\n** Invalid boot device **\n"); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } + + dev = dev_desc->dev; if (fat_register_device(dev_desc,part)!=0) { printf("\n** Unable to use %s %d:%d for fatload **\n", argv[1], dev, part); @@ -93,7 +84,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( fatload, 6, 0, do_fat_fsload, "load binary file from a dos filesystem", - "<interface> <dev[:part]> <addr> <filename> [bytes]\n" + "<interface> [<dev[:part]>] <addr> <filename> [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from dos filesystem" ); @@ -101,29 +92,20 @@ U_BOOT_CMD( int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *filename = "/"; - int ret; - int dev=0; - int part=1; - char *ep; + int ret, dev, part; block_dev_desc_t *dev_desc=NULL; + disk_partition_t info; - if (argc < 3) { - printf("usage: fatls <interface> <dev[:part]> [directory]\n"); + if (argc < 2) { + printf("usage: fatls <interface> [<dev[:part]>] [directory]\n"); return 0; } - dev = (int)simple_strtoul(argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - if (dev_desc == NULL) { - puts("\n** Invalid boot device **\n"); + + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } + + dev = dev_desc->dev; if (fat_register_device(dev_desc,part)!=0) { printf("\n** Unable to use %s %d:%d for fatls **\n", argv[1], dev, part); @@ -142,34 +124,26 @@ int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( fatls, 4, 1, do_fat_ls, "list files in a directory (default /)", - "<interface> <dev[:part]> [directory]\n" + "<interface> [<dev[:part]>] [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'" ); int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int dev=0; - int part=1; - char *ep; - block_dev_desc_t *dev_desc=NULL; + int dev, part; + block_dev_desc_t *dev_desc; + disk_partition_t info; if (argc < 2) { - printf("usage: fatinfo <interface> <dev[:part]>\n"); + printf("usage: fatinfo <interface> [<dev[:part]>]\n"); return 0; } - dev = (int)simple_strtoul(argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - if (dev_desc == NULL) { - puts("\n** Invalid boot device **\n"); + + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } + + dev = dev_desc->dev; if (fat_register_device(dev_desc,part)!=0) { printf("\n** Unable to use %s %d:%d for fatinfo **\n", argv[1], dev, part); @@ -181,7 +155,7 @@ int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( fatinfo, 3, 1, do_fat_fsinfo, "print information about filesystem", - "<interface> <dev[:part]>\n" + "<interface> [<dev[:part]>]\n" " - print information about filesystem from 'dev' on 'interface'" ); @@ -193,6 +167,7 @@ static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, unsigned long addr; unsigned long count; block_dev_desc_t *dev_desc = NULL; + disk_partition_t info; int dev = 0; int part = 1; char *ep; @@ -200,19 +175,12 @@ static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, if (argc < 5) return cmd_usage(cmdtp); - dev = (int)simple_strtoul(argv[2], &ep, 16); - dev_desc = get_dev(argv[1], dev); - if (dev_desc == NULL) { - puts("\n** Invalid boot device **\n"); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } + + dev = dev_desc->dev; + if (fat_register_device(dev_desc, part) != 0) { printf("\n** Unable to use %s %d:%d for fatwrite **\n", argv[1], dev, part); diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 9a5c53ec06c..e2225c4d5c6 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -114,10 +114,21 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } } + return CMD_RET_SUCCESS; + } + + if (!working_fdt) { + puts( + "No FDT memory address configured. Please configure\n" + "the FDT address via \"fdt addr <address>\" command.\n" + "Aborting!\n"); + return CMD_RET_FAILURE; + } + /* * Move the working_fdt */ - } else if (strncmp(argv[1], "mo", 2) == 0) { + if (strncmp(argv[1], "mo", 2) == 0) { struct fdt_header *newaddr; int len; int err; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index f5b6c7b1ec6..6e1e5680a2c 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -334,156 +334,7 @@ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - char *boot_device = NULL; - char *ep; - int dev, part = 0; - ulong addr, cnt; - disk_partition_t info; - image_header_t *hdr; - -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - - bootstage_mark(BOOTSTAGE_ID_IDE_START); - switch (argc) { - case 1: - addr = CONFIG_SYS_LOAD_ADDR; - boot_device = getenv("bootdevice"); - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = getenv("bootdevice"); - break; - case 3: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = argv[2]; - break; - default: - bootstage_error(BOOTSTAGE_ID_IDE_ADDR); - return CMD_RET_USAGE; - } - bootstage_mark(BOOTSTAGE_ID_IDE_ADDR); - - if (!boot_device) { - puts("\n** No boot device **\n"); - bootstage_error(BOOTSTAGE_ID_IDE_BOOT_DEVICE); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_BOOT_DEVICE); - - dev = simple_strtoul(boot_device, &ep, 16); - - if (ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { - printf("\n** Device %d not available\n", dev); - bootstage_error(BOOTSTAGE_ID_IDE_TYPE); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_TYPE); - - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - bootstage_error(BOOTSTAGE_ID_IDE_PART); - return 1; - } - part = simple_strtoul(++ep, NULL, 16); - } - bootstage_mark(BOOTSTAGE_ID_IDE_PART); - - if (get_partition_info(&ide_dev_desc[dev], part, &info)) { - bootstage_error(BOOTSTAGE_ID_IDE_PART_INFO); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_PART_INFO); - - if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) - && - (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0) - ) { - printf("\n** Invalid partition type \"%.32s\"" " (expect \"" - BOOT_PART_TYPE "\")\n", - info.type); - bootstage_error(BOOTSTAGE_ID_IDE_PART_TYPE); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_PART_TYPE); - - printf("\nLoading from IDE device %d, partition %d: " - "Name: %.32s Type: %.32s\n", dev, part, info.name, info.type); - - debug("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", - info.start, info.size, info.blksz); - - if (ide_dev_desc[dev]. - block_read(dev, info.start, 1, (ulong *) addr) != 1) { - printf("** Read error on %d:%d\n", dev, part); - bootstage_error(BOOTSTAGE_ID_IDE_PART_READ); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ); - - switch (genimg_get_format((void *) addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *) addr; - - bootstage_mark(BOOTSTAGE_ID_IDE_FORMAT); - - if (!image_check_hcrc(hdr)) { - puts("\n** Bad Header Checksum **\n"); - bootstage_error(BOOTSTAGE_ID_IDE_CHECKSUM); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_CHECKSUM); - - image_print_contents(hdr); - - cnt = image_get_image_size(hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *) addr; - puts("Fit image detected...\n"); - - cnt = fit_get_size(fit_hdr); - break; -#endif - default: - bootstage_error(BOOTSTAGE_ID_IDE_FORMAT); - puts("** Unknown image type\n"); - return 1; - } - - cnt += info.blksz - 1; - cnt /= info.blksz; - cnt -= 1; - - if (ide_dev_desc[dev].block_read(dev, info.start + 1, cnt, - (ulong *)(addr + info.blksz)) != cnt) { - printf("** Read error on %d:%d\n", dev, part); - bootstage_error(BOOTSTAGE_ID_IDE_READ); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_READ); - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format(fit_hdr)) { - bootstage_error(BOOTSTAGE_ID_IDE_FIT_READ); - puts("** Bad FIT image format\n"); - return 1; - } - bootstage_mark(BOOTSTAGE_ID_IDE_FIT_READ_OK); - fit_print_contents(fit_hdr); - } -#endif - - /* Loading ok, update default load address */ - - load_addr = addr; - - return bootm_maybe_autostart(cmdtp, argv[0]); + return common_diskboot(cmdtp, "ide", argc, argv); } /* ------------------------------------------------------------------------- */ diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 750509da5e2..79a1088f3bb 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -144,8 +144,7 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( mmcinfo, 1, 0, do_mmcinfo, "display MMC info", - " - device number of the device to dislay info of\n" - "" + "- dislay info of the current MMC device" ); int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4df37..e24ed7f9c4a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat) last = off; - datbuf = malloc(nand->writesize); - oobbuf = malloc(nand->oobsize); + datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize); + oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1; @@ -231,12 +231,18 @@ print: #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK static void print_status(ulong start, ulong end, ulong erasesize, int status) { + /* + * Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is + * not the same as others. Instead of bit 1 being lock, it is + * #lock_tight. To make the driver support either format, ignore bit 1 + * and use only bit 0 and bit 2. + */ printf("%08lx - %08lx: %08lx blocks %s%s%s\n", start, end - 1, (end - start) / erasesize, ((status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""), - ((status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""), + (!(status & NAND_LOCK_STATUS_UNLOCK) ? "LOCK " : ""), ((status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); } @@ -749,11 +755,18 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 0; } - if (strcmp(cmd, "unlock") == 0) { + if (strncmp(cmd, "unlock", 5) == 0) { + int allexcept = 0; + + s = strchr(cmd, '.'); + + if (s && !strcmp(s, ".allexcept")) + allexcept = 1; + if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0) return 1; - if (!nand_unlock(&nand_info[dev], off, size)) { + if (!nand_unlock(&nand_info[dev], off, size, allexcept)) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " @@ -807,7 +820,7 @@ U_BOOT_CMD( "\n" "nand lock [tight] [status]\n" " bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section" + "nand unlock[.allexcept] [offset] [size] - unlock section" #endif #ifdef CONFIG_ENV_OFFSET_OOB "\n" diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index fd05e725d76..3474bc60940 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -198,31 +198,20 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag, #endif /* - * Set a new environment variable, - * or replace or delete an existing one. + * Perform consistency checking before setting, replacing, or deleting an + * environment variable, then (if successful) apply the changes to internals so + * to make them effective. Code for this function was taken out of + * _do_env_set(), which now calls it instead. + * Also called as a callback function by himport_r(). + * Returns 0 in case of success, 1 in case of failure. + * When (flag & H_FORCE) is set, do not print out any error message and force + * overwriting of write-once variables. */ -int _do_env_set(int flag, int argc, char * const argv[]) + +int env_check_apply(const char *name, const char *oldval, + const char *newval, int flag) { - int i, len; int console = -1; - char *name, *value, *s; - ENTRY e, *ep; - - name = argv[1]; - - if (strchr(name, '=')) { - printf("## Error: illegal character '=' in variable name" - "\"%s\"\n", name); - return 1; - } - - env_id++; - /* - * search if variable with this name already exists - */ - e.key = name; - e.data = NULL; - hsearch_r(e, FIND, &ep, &env_htab); /* Check for console redirection */ if (strcmp(name, "stdin") == 0) @@ -233,60 +222,75 @@ int _do_env_set(int flag, int argc, char * const argv[]) console = stderr; if (console != -1) { - if (argc < 3) { /* Cannot delete it! */ - printf("Can't delete \"%s\"\n", name); + if ((newval == NULL) || (*newval == '\0')) { + /* We cannot delete stdin/stdout/stderr */ + if ((flag & H_FORCE) == 0) + printf("Can't delete \"%s\"\n", name); return 1; } #ifdef CONFIG_CONSOLE_MUX - i = iomux_doenv(console, argv[2]); - if (i) - return i; + if (iomux_doenv(console, newval)) + return 1; #else /* Try assigning specified device */ - if (console_assign(console, argv[2]) < 0) + if (console_assign(console, newval) < 0) return 1; #ifdef CONFIG_SERIAL_MULTI - if (serial_assign(argv[2]) < 0) + if (serial_assign(newval) < 0) return 1; #endif #endif /* CONFIG_CONSOLE_MUX */ } /* - * Some variables like "ethaddr" and "serial#" can be set only - * once and cannot be deleted; also, "ver" is readonly. + * Some variables like "ethaddr" and "serial#" can be set only once and + * cannot be deleted, unless CONFIG_ENV_OVERWRITE is defined. */ - if (ep) { /* variable exists */ #ifndef CONFIG_ENV_OVERWRITE + if (oldval != NULL && /* variable exists */ + (flag & H_FORCE) == 0) { /* and we are not forced */ if (strcmp(name, "serial#") == 0 || (strcmp(name, "ethaddr") == 0 #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) - && strcmp(ep->data, MK_STR(CONFIG_ETHADDR)) != 0 + && strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0 #endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */ )) { printf("Can't overwrite \"%s\"\n", name); return 1; } + } #endif + /* + * When we change baudrate, or we are doing an env default -a + * (which will erase all variables prior to calling this), + * we want the baudrate to actually change - for real. + */ + if (oldval != NULL || /* variable exists */ + (flag & H_NOCLEAR) == 0) { /* or env is clear */ /* * Switch to new baudrate if new baudrate is supported */ if (strcmp(name, "baudrate") == 0) { - int baudrate = simple_strtoul(argv[2], NULL, 10); + int baudrate = simple_strtoul(newval, NULL, 10); int i; for (i = 0; i < N_BAUDRATES; ++i) { if (baudrate == baudrate_table[i]) break; } if (i == N_BAUDRATES) { - printf("## Baudrate %d bps not supported\n", - baudrate); + if ((flag & H_FORCE) == 0) + printf("## Baudrate %d bps not " + "supported\n", baudrate); return 1; } + if (gd->baudrate == baudrate) { + /* If unchanged, we just say it's OK */ + return 0; + } printf("## Switch baudrate to %d bps and" - "press ENTER ...\n", baudrate); + "press ENTER ...\n", baudrate); udelay(50000); gd->baudrate = baudrate; #if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) @@ -300,9 +304,62 @@ int _do_env_set(int flag, int argc, char * const argv[]) } } + /* + * Some variables should be updated when the corresponding + * entry in the environment is changed + */ + if (strcmp(name, "loadaddr") == 0) { + load_addr = simple_strtoul(newval, NULL, 16); + return 0; + } +#if defined(CONFIG_CMD_NET) + else if (strcmp(name, "bootfile") == 0) { + copy_filename(BootFile, newval, sizeof(BootFile)); + return 0; + } +#endif + return 0; +} + +/* + * Set a new environment variable, + * or replace or delete an existing one. +*/ +int _do_env_set(int flag, int argc, char * const argv[]) +{ + int i, len; + char *name, *value, *s; + ENTRY e, *ep; + + name = argv[1]; + value = argv[2]; + + if (strchr(name, '=')) { + printf("## Error: illegal character '='" + "in variable name \"%s\"\n", name); + return 1; + } + + env_id++; + /* + * search if variable with this name already exists + */ + e.key = name; + e.data = NULL; + hsearch_r(e, FIND, &ep, &env_htab); + + /* + * Perform requested checks. Notice how since we are overwriting + * a single variable, we need to set H_NOCLEAR + */ + if (env_check_apply(name, ep ? ep->data : NULL, value, H_NOCLEAR)) { + debug("check function did not approve, refusing\n"); + return 1; + } + /* Delete only ? */ if (argc < 3 || argv[2] == NULL) { - int rc = hdelete_r(name, &env_htab); + int rc = hdelete_r(name, &env_htab, 0); return !rc; } @@ -337,20 +394,6 @@ int _do_env_set(int flag, int argc, char * const argv[]) return 1; } - /* - * Some variables should be updated when the corresponding - * entry in the environment is changed - */ - if (strcmp(argv[1], "loadaddr") == 0) { - load_addr = simple_strtoul(argv[2], NULL, 16); - return 0; - } -#if defined(CONFIG_CMD_NET) - else if (strcmp(argv[1], "bootfile") == 0) { - copy_filename(BootFile, argv[2], sizeof(BootFile)); - return 0; - } -#endif return 0; } @@ -613,14 +656,41 @@ int envmatch(uchar *s1, int i2) return -1; } -static int do_env_default(cmd_tbl_t *cmdtp, int flag, +static int do_env_default(cmd_tbl_t *cmdtp, int __flag, int argc, char * const argv[]) { - if (argc != 2 || strcmp(argv[1], "-f") != 0) - return CMD_RET_USAGE; + int all = 0, flag = 0; - set_default_env("## Resetting to default environment\n"); - return 0; + debug("Initial value for argc=%d\n", argc); + while (--argc > 0 && **++argv == '-') { + char *arg = *argv; + + while (*++arg) { + switch (*arg) { + case 'a': /* default all */ + all = 1; + break; + case 'f': /* force */ + flag |= H_FORCE; + break; + default: + return cmd_usage(cmdtp); + } + } + } + debug("Final value for argc=%d\n", argc); + if (all && (argc == 0)) { + /* Reset the whole environment */ + set_default_env("## Resetting to default environment\n"); + return 0; + } + if (!all && (argc > 0)) { + /* Reset individual variables */ + set_default_vars(argc, argv); + return 0; + } + + return cmd_usage(cmdtp); } static int do_env_delete(cmd_tbl_t *cmdtp, int flag, @@ -872,7 +942,8 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, addr = (char *)ep->data; } - if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR) == 0) { + if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR, + 0, NULL, 0 /* do_apply */) == 0) { error("Environment import failed: errno = %d\n", errno); return 1; } @@ -950,15 +1021,20 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_ASKENV) "ask name [message] [size] - ask for environment variable\nenv " #endif - "default -f - reset default environment\n" + "default [-f] -a - [forcibly] reset default environment\n" + "env default [-f] var [...] - [forcibly] reset variable(s) to their default values\n" #if defined(CONFIG_CMD_EDITENV) "env edit name - edit environment variable\n" #endif +#if defined(CONFIG_CMD_EXPORTENV) "env export [-t | -b | -c] [-s size] addr [var ...] - export environment\n" +#endif #if defined(CONFIG_CMD_GREPENV) "env grep string [...] - search environment\n" #endif +#if defined(CONFIG_CMD_IMPORTENV) "env import [-d] [-t | -b | -c] addr [size] - import environment\n" +#endif "env print [name ...] - print environment\n" #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" diff --git a/common/cmd_part.c b/common/cmd_part.c new file mode 100644 index 00000000000..d997597c1e1 --- /dev/null +++ b/common/cmd_part.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * made from cmd_ext2, which was: + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * made from cmd_reiserfs by + * + * (C) Copyright 2003 - 2004 + * Sysgo Real-Time Solutions, AG <www.elinos.com> + * Pavel Bartusek <pba@sysgo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <part.h> +#include <vsprintf.h> + +#ifndef CONFIG_PARTITION_UUIDS +#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled +#endif + +int do_part_uuid(int argc, char * const argv[]) +{ + int part; + block_dev_desc_t *dev_desc; + disk_partition_t info; + + if (argc < 2) + return CMD_RET_USAGE; + if (argc > 3) + return CMD_RET_USAGE; + + part = get_device_and_partition(argv[0], argv[1], &dev_desc, &info, 0); + if (part < 0) + return 1; + + if (argc > 2) + setenv(argv[2], info.uuid); + else + printf("%s\n", info.uuid); + + return 0; +} + +int do_part_list(int argc, char * const argv[]) +{ + int ret; + block_dev_desc_t *desc; + + if (argc != 2) + return CMD_RET_USAGE; + + ret = get_device(argv[0], argv[1], &desc); + if (ret < 0) + return 1; + + print_part(desc); + + return 0; +} + +int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "uuid")) + return do_part_uuid(argc - 2, argv + 2); + else if (!strcmp(argv[1], "list")) + return do_part_list(argc - 2, argv + 2); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + part, 5, 1, do_part, + "disk partition related commands", + "part uuid <interface> <dev>:<part>\n" + " - print partition UUID\n" + "part uuid <interface> <dev>:<part> <varname>\n" + " - set environment variable to partition UUID\n" + "part list <interface> <dev>\n" + " - print a device's partition table" +); diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c index fbb9484d0ae..e658618c6d0 100644 --- a/common/cmd_reiser.c +++ b/common/cmd_reiser.c @@ -50,43 +50,27 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *filename = "/"; - int dev=0; - int part=1; - char *ep; + int dev, part; block_dev_desc_t *dev_desc=NULL; - int part_length; + disk_partition_t info; if (argc < 3) return CMD_RET_USAGE; - dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - - if (dev_desc == NULL) { - printf ("\n** Block device %s %d not supported\n", argv[1], dev); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - - if (*ep) { - if (*ep != ':') { - puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } if (argc == 4) { filename = argv[3]; } + dev = dev_desc->dev; PRINTF("Using device %s %d:%d, directory: %s\n", argv[1], dev, part, filename); - if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) { - printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); - return 1; - } + reiserfs_set_blk_dev(dev_desc, &info); - if (!reiserfs_mount(part_length)) { + if (!reiserfs_mount(info.size)) { printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } @@ -112,9 +96,8 @@ U_BOOT_CMD( int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *filename = NULL; - char *ep; - int dev, part = 0; - ulong addr = 0, part_length, filelen; + int dev, part; + ulong addr = 0, filelen; disk_partition_t info; block_dev_desc_t *dev_desc = NULL; char buf [12]; @@ -157,49 +140,19 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } - dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); - if (dev_desc==NULL) { - printf ("\n** Block device %s %d not supported\n", argv[1], dev); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = (int)simple_strtoul(++ep, NULL, 16); - } - PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part); + dev = dev_desc->dev; - if (part != 0) { - if (get_partition_info (dev_desc, part, &info)) { - printf ("** Bad partition %d **\n", part); - return 1; - } + printf("Loading file \"%s\" from %s device %d%c%c\n", + filename, argv[1], dev, + part ? ':' : ' ', part ? part + '0' : ' '); - if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { - printf ("\n** Invalid partition type \"%.32s\"" - " (expect \"" BOOT_PART_TYPE "\")\n", - info.type); - return 1; - } - PRINTF ("\nLoading from block device %s device %d, partition %d: " - "Name: %.32s Type: %.32s File:%s\n", - argv[1], dev, part, info.name, info.type, filename); - } else { - PRINTF ("\nLoading from block device %s device %d, File:%s\n", - argv[1], dev, filename); - } - - - if ((part_length = reiserfs_set_blk_dev(dev_desc, part)) == 0) { - printf ("** Bad partition - %s %d:%d **\n", argv[1], dev, part); - return 1; - } + reiserfs_set_blk_dev(dev_desc, &info); - if (!reiserfs_mount(part_length)) { + if (!reiserfs_mount(info.size)) { printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index d15b567dbb2..22d0119814f 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -206,128 +206,7 @@ block_dev_desc_t * scsi_get_dev(int dev) */ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *boot_device = NULL; - char *ep; - int dev, part = 0; - ulong addr, cnt; - disk_partition_t info; - image_header_t *hdr; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - - switch (argc) { - case 1: - addr = CONFIG_SYS_LOAD_ADDR; - boot_device = getenv ("bootdevice"); - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = getenv ("bootdevice"); - break; - case 3: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = argv[2]; - break; - default: - return CMD_RET_USAGE; - } - - if (!boot_device) { - puts ("\n** No boot device **\n"); - return 1; - } - - dev = simple_strtoul(boot_device, &ep, 16); - printf("booting from dev %d\n",dev); - if (scsi_dev_desc[dev].type == DEV_TYPE_UNKNOWN) { - printf ("\n** Device %d not available\n", dev); - return 1; - } - - if (*ep) { - if (*ep != ':') { - puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = simple_strtoul(++ep, NULL, 16); - } - if (get_partition_info (&scsi_dev_desc[dev], part, &info)) { - printf("error reading partinfo\n"); - return 1; - } - if ((strncmp((char *)(info.type), BOOT_PART_TYPE, sizeof(info.type)) != 0) && - (strncmp((char *)(info.type), BOOT_PART_COMP, sizeof(info.type)) != 0)) { - printf ("\n** Invalid partition type \"%.32s\"" - " (expect \"" BOOT_PART_TYPE "\")\n", - info.type); - return 1; - } - - printf ("\nLoading from SCSI device %d, partition %d: " - "Name: %.32s Type: %.32s\n", - dev, part, info.name, info.type); - - debug ("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", - info.start, info.size, info.blksz); - - if (scsi_read (dev, info.start, 1, (ulong *)addr) != 1) { - printf ("** Read error on %d:%d\n", dev, part); - return 1; - } - - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - - if (!image_check_hcrc (hdr)) { - puts ("\n** Bad Header Checksum **\n"); - return 1; - } - - image_print_contents (hdr); - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - puts ("** Unknown image type\n"); - return 1; - } - - cnt += info.blksz - 1; - cnt /= info.blksz; - cnt -= 1; - - if (scsi_read (dev, info.start+1, cnt, - (ulong *)(addr+info.blksz)) != cnt) { - printf ("** Read error on %d:%d\n", dev, part); - return 1; - } - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } - fit_print_contents (fit_hdr); - } -#endif - - /* Loading ok, update default load address */ - load_addr = addr; - - flush_cache (addr, (cnt+1)*info.blksz); - - return bootm_maybe_autostart(cmdtp, argv[0]); + return common_diskboot(cmdtp, "scsi", argc, argv); } /********************************************************************************* diff --git a/common/cmd_usb.c b/common/cmd_usb.c index a8e3ae5b67f..181e727f00a 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -355,143 +355,7 @@ void usb_show_tree(struct usb_device *dev) #ifdef CONFIG_USB_STORAGE int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *boot_device = NULL; - char *ep; - int dev, part = 1; - ulong addr, cnt; - disk_partition_t info; - image_header_t *hdr; - block_dev_desc_t *stor_dev; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - - switch (argc) { - case 1: - addr = CONFIG_SYS_LOAD_ADDR; - boot_device = getenv("bootdevice"); - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = getenv("bootdevice"); - break; - case 3: - addr = simple_strtoul(argv[1], NULL, 16); - boot_device = argv[2]; - break; - default: - return CMD_RET_USAGE; - } - - if (!boot_device) { - puts("\n** No boot device **\n"); - return 1; - } - - dev = simple_strtoul(boot_device, &ep, 16); - stor_dev = usb_stor_get_dev(dev); - if (stor_dev == NULL || stor_dev->type == DEV_TYPE_UNKNOWN) { - printf("\n** Device %d not available\n", dev); - return 1; - } - if (stor_dev->block_read == NULL) { - printf("storage device not initialized. Use usb scan\n"); - return 1; - } - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = simple_strtoul(++ep, NULL, 16); - } - - if (get_partition_info(stor_dev, part, &info)) { - /* try to boot raw .... */ - strncpy((char *)&info.type[0], BOOT_PART_TYPE, - sizeof(BOOT_PART_TYPE)); - strncpy((char *)&info.name[0], "Raw", 4); - info.start = 0; - info.blksz = 0x200; - info.size = 2880; - printf("error reading partinfo...try to boot raw\n"); - } - if ((strncmp((char *)info.type, BOOT_PART_TYPE, - sizeof(info.type)) != 0) && - (strncmp((char *)info.type, BOOT_PART_COMP, - sizeof(info.type)) != 0)) { - printf("\n** Invalid partition type \"%.32s\"" - " (expect \"" BOOT_PART_TYPE "\")\n", - info.type); - return 1; - } - printf("\nLoading from USB device %d, partition %d: " - "Name: %.32s Type: %.32s\n", - dev, part, info.name, info.type); - - debug("First Block: %ld, # of blocks: %ld, Block Size: %ld\n", - info.start, info.size, info.blksz); - - if (stor_dev->block_read(dev, info.start, 1, (ulong *)addr) != 1) { - printf("** Read error on %d:%d\n", dev, part); - return 1; - } - - switch (genimg_get_format((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - - if (!image_check_hcrc(hdr)) { - puts("\n** Bad Header Checksum **\n"); - return 1; - } - - image_print_contents(hdr); - - cnt = image_get_image_size(hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts("Fit image detected...\n"); - - cnt = fit_get_size(fit_hdr); - break; -#endif - default: - puts("** Unknown image type\n"); - return 1; - } - - cnt += info.blksz - 1; - cnt /= info.blksz; - cnt -= 1; - - if (stor_dev->block_read(dev, info.start+1, cnt, - (ulong *)(addr+info.blksz)) != cnt) { - printf("\n** Read error on %d:%d\n", dev, part); - return 1; - } - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM - * first - */ - if (genimg_get_format((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format(fit_hdr)) { - puts("** Bad FIT image format\n"); - return 1; - } - fit_print_contents(fit_hdr); - } -#endif - - /* Loading ok, update default load address */ - load_addr = addr; - - flush_cache(addr, (cnt+1)*info.blksz); - - return bootm_maybe_autostart(cmdtp, argv[0]); + return common_diskboot(cmdtp, "usb", argc, argv); } #endif /* CONFIG_USB_STORAGE */ diff --git a/common/cmd_zfs.c b/common/cmd_zfs.c index a6ea2c07cdd..d580f7bca06 100644 --- a/common/cmd_zfs.c +++ b/common/cmd_zfs.c @@ -49,12 +49,11 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *filename = NULL; - char *ep; int dev; - unsigned long part = 1; + int part; ulong addr = 0; - ulong part_length; disk_partition_t info; + block_dev_desc_t *dev_desc; char buf[12]; unsigned long count; const char *addr_str; @@ -95,48 +94,17 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - dev = (int)simple_strtoul(argv[2], &ep, 16); - zfs_dev_desc = get_dev(argv[1], dev); - if (zfs_dev_desc == NULL) { - printf("** Block device %s %d not supported\n", argv[1], dev); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - if (*ep) { - if (*ep != ':') { - puts("** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = simple_strtoul(++ep, NULL, 16); - } + dev = dev_desc->dev; + printf("Loading file \"%s\" from %s device %d%c%c\n", + filename, argv[1], dev, + part ? ':' : ' ', part ? part + '0' : ' '); - if (part != 0) { - if (get_partition_info(zfs_dev_desc, part, &info)) { - printf("** Bad partition %lu **\n", part); - return 1; - } - - if (strncmp((char *)info.type, BOOT_PART_TYPE, - strlen(BOOT_PART_TYPE)) != 0) { - printf("** Invalid partition type \"%s\" (expect \"" BOOT_PART_TYPE "\")\n", - info.type); - return 1; - } - printf("Loading file \"%s\" " - "from %s device %d:%lu %s\n", - filename, argv[1], dev, part, info.name); - } else { - printf("Loading file \"%s\" from %s device %d\n", - filename, argv[1], dev); - } - - part_length = zfs_set_blk_dev(zfs_dev_desc, part); - if (part_length == 0) { - printf("**Bad partition - %s %d:%lu **\n", argv[1], dev, part); - return 1; - } - - vdev.part_length = part_length; + zfs_set_blk_dev(dev_desc, &info); + vdev.part_length = info.size; memset(&zfile, 0, sizeof(zfile)); zfile.device = &vdev; @@ -149,7 +117,7 @@ static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) zfile.size = (uint64_t)count; if (zfs_read(&zfile, (char *)addr, zfile.size) != zfile.size) { - printf("** Unable to read \"%s\" from %s %d:%lu **\n", + printf("** Unable to read \"%s\" from %s %d:%d **\n", filename, argv[1], dev, part); zfs_close(&zfile); return 1; @@ -181,41 +149,23 @@ int zfs_print(const char *entry, const struct zfs_dirhook_info *data) static int do_zfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { const char *filename = "/"; - int dev; - unsigned long part = 1; - char *ep; - int part_length; + int part; + block_dev_desc_t *dev_desc; + disk_partition_t info; struct device_s vdev; - if (argc < 3) + if (argc < 2) return cmd_usage(cmdtp); - dev = (int)simple_strtoul(argv[2], &ep, 16); - zfs_dev_desc = get_dev(argv[1], dev); - - if (zfs_dev_desc == NULL) { - printf("\n** Block device %s %d not supported\n", argv[1], dev); - return 1; - } - - if (*ep) { - if (*ep != ':') { - puts("\n** Invalid boot device, use `dev[:part]' **\n"); - return 1; - } - part = simple_strtoul(++ep, NULL, 16); - } - if (argc == 4) filename = argv[3]; - part_length = zfs_set_blk_dev(zfs_dev_desc, part); - if (part_length == 0) { - printf("** Bad partition - %s %d:%lu **\n", argv[1], dev, part); + part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); + if (part < 0) return 1; - } - vdev.part_length = part_length; + zfs_set_blk_dev(dev_desc, &info); + vdev.part_length = info.size; zfs_ls(&vdev, filename, zfs_print); diff --git a/common/dlmalloc.c b/common/dlmalloc.c index c645d7314bf..1d7e527b9df 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1487,11 +1487,11 @@ static mbinptr av_[NAV * 2 + 2] = { #ifdef CONFIG_NEEDS_MANUAL_RELOC void malloc_bin_reloc (void) { - unsigned long *p = (unsigned long *)(&av_[2]); - int i; - for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) { - *p++ += gd->reloc_off; - } + mbinptr *p = &av_[2]; + size_t i; + + for (i = 2; i < ARRAY_SIZE(av_); ++i, ++p) + *p = (mbinptr)((ulong)*p + gd->reloc_off); } #endif diff --git a/common/env_common.c b/common/env_common.c index d9e990dbbec..3e46c260df8 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -80,6 +80,9 @@ const uchar default_environment[] = { #ifdef CONFIG_ETH5ADDR "eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0" #endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif #ifdef CONFIG_IPADDR "ipaddr=" MK_STR(CONFIG_IPADDR) "\0" #endif @@ -133,7 +136,9 @@ const uchar default_environment[] = { "\0" }; -struct hsearch_data env_htab; +struct hsearch_data env_htab = { + .apply = env_check_apply, +}; static uchar __env_get_char_spec(int index) { @@ -175,6 +180,11 @@ const uchar *env_get_addr(int index) void set_default_env(const char *s) { + /* + * By default, do not apply changes as they will eventually + * be applied by someone else + */ + int do_apply = 0; if (sizeof(default_environment) > ENV_SIZE) { puts("*** Error - default environment is too large\n\n"); return; @@ -186,6 +196,14 @@ void set_default_env(const char *s) "using default environment\n\n", s + 1); } else { + /* + * This set_to_default was explicitly asked for + * by the user, as opposed to being a recovery + * mechanism. Therefore we check every single + * variable and apply changes to the system + * right away (e.g. baudrate, console). + */ + do_apply = 1; puts(s); } } else { @@ -193,12 +211,26 @@ void set_default_env(const char *s) } if (himport_r(&env_htab, (char *)default_environment, - sizeof(default_environment), '\0', 0) == 0) + sizeof(default_environment), '\0', 0, + 0, NULL, do_apply) == 0) error("Environment import failed: errno = %d\n", errno); gd->flags |= GD_FLG_ENV_READY; } + +/* [re]set individual variables to their value in the default environment */ +int set_default_vars(int nvars, char * const vars[]) +{ + /* + * Special use-case: import from default environment + * (and use \0 as a separator) + */ + return himport_r(&env_htab, (const char *)default_environment, + sizeof(default_environment), '\0', H_NOCLEAR, + nvars, vars, 1 /* do_apply */); +} + /* * Check if CRC is valid and (if yes) import the environment. * Note that "buf" may or may not be aligned. @@ -218,7 +250,8 @@ int env_import(const char *buf, int check) } } - if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) { + if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, + 0, NULL, 0 /* do_apply */)) { gd->flags |= GD_FLG_ENV_READY; return 1; } diff --git a/common/env_mmc.c b/common/env_mmc.c index be2f2be205a..a2ff90bf485 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -75,9 +75,28 @@ static int init_mmc_for_env(struct mmc *mmc) return -1; } +#ifdef CONFIG_SYS_MMC_ENV_PART + if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) { + if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV, + CONFIG_SYS_MMC_ENV_PART)) { + puts("MMC partition switch failed\n"); + return -1; + } + } +#endif + return 0; } +static void fini_mmc_for_env(struct mmc *mmc) +{ +#ifdef CONFIG_SYS_MMC_ENV_PART + if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) + mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV, + mmc->part_num); +#endif +} + #ifdef CONFIG_CMD_SAVEENV static inline int write_env(struct mmc *mmc, unsigned long size, unsigned long offset, const void *buffer) @@ -100,26 +119,38 @@ int saveenv(void) char *res; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); u32 offset; + int ret; - if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset)) + if (init_mmc_for_env(mmc)) return 1; + if (mmc_get_env_addr(mmc, &offset)) { + ret = 1; + goto fini; + } + res = (char *)&env_new->data; len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); - return 1; + ret = 1; + goto fini; } env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE); printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV); if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) { puts("failed\n"); - return 1; + ret = 1; + goto fini; } puts("done\n"); - return 0; + ret = 0; + +fini: + fini_mmc_for_env(mmc); + return ret; } #endif /* CONFIG_CMD_SAVEENV */ @@ -143,13 +174,30 @@ void env_relocate_spec(void) ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); u32 offset; + int ret; - if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset)) - return set_default_env(NULL); + if (init_mmc_for_env(mmc)) { + ret = 1; + goto err; + } - if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) - return set_default_env(NULL); + if (mmc_get_env_addr(mmc, &offset)) { + ret = 1; + goto fini; + } + + if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) { + ret = 1; + goto fini; + } env_import(buf, 1); + ret = 0; + +fini: + fini_mmc_for_env(mmc); +err: + if (ret) + set_default_env(NULL); #endif } diff --git a/common/env_nand.c b/common/env_nand.c index e6354728fbc..79e80337050 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -226,7 +226,7 @@ int saveenv(void) int saveenv(void) { int ret = 0; - ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, sizeof(env_t)); + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); ssize_t len; char *res; nand_erase_options_t nand_erase_options; diff --git a/common/env_remote.c b/common/env_remote.c index 3bf0f957b3a..a7b147b20db 100644 --- a/common/env_remote.c +++ b/common/env_remote.c @@ -62,8 +62,8 @@ int env_init(void) #ifdef CONFIG_CMD_SAVEENV int saveenv(void) { -#ifdef CONFIG_SRIOBOOT_SLAVE - printf("Can not support the 'saveenv' when boot from SRIO!\n"); +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + printf("Can not support the 'saveenv' when boot from SRIO or PCIE!\n"); return 1; #else return 0; diff --git a/common/image.c b/common/image.c index 70a112d36f0..f084d2baed3 100644 --- a/common/image.c +++ b/common/image.c @@ -143,6 +143,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_INVALID, NULL, "Invalid Image", }, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, + { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, diff --git a/common/usb_hub.c b/common/usb_hub.c index f35ad95324a..32750e8d050 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -43,6 +43,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/unaligned.h> #include <linux/ctype.h> #include <asm/byteorder.h> #include <asm/unaligned.h> @@ -269,6 +270,7 @@ static int usb_hub_configure(struct usb_device *dev) int i; ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ); unsigned char *bitmap; + short hubCharacteristics; struct usb_hub_descriptor *descriptor; struct usb_hub_device *hub; #ifdef USB_HUB_DEBUG @@ -304,8 +306,9 @@ static int usb_hub_configure(struct usb_device *dev) } memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength); /* adjust 16bit values */ - hub->desc.wHubCharacteristics = - le16_to_cpu(descriptor->wHubCharacteristics); + put_unaligned(le16_to_cpu(get_unaligned( + &descriptor->wHubCharacteristics)), + &hub->desc.wHubCharacteristics); /* set the bitmap */ bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0]; /* devices not removable by default */ @@ -322,7 +325,8 @@ static int usb_hub_configure(struct usb_device *dev) dev->maxchild = descriptor->bNbrPorts; USB_HUB_PRINTF("%d ports detected\n", dev->maxchild); - switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) { + hubCharacteristics = get_unaligned(&hub->desc.wHubCharacteristics); + switch (hubCharacteristics & HUB_CHAR_LPSM) { case 0x00: USB_HUB_PRINTF("ganged power switching\n"); break; @@ -335,12 +339,12 @@ static int usb_hub_configure(struct usb_device *dev) break; } - if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) + if (hubCharacteristics & HUB_CHAR_COMPOUND) USB_HUB_PRINTF("part of a compound device\n"); else USB_HUB_PRINTF("standalone hub\n"); - switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) { + switch (hubCharacteristics & HUB_CHAR_OCPM) { case 0x00: USB_HUB_PRINTF("global over-current protection\n"); break; diff --git a/disk/part.c b/disk/part.c index 76f393900a5..64d76e83806 100644 --- a/disk/part.c +++ b/disk/part.c @@ -24,6 +24,7 @@ #include <common.h> #include <command.h> #include <ide.h> +#include <malloc.h> #include <part.h> #undef PART_DEBUG @@ -70,7 +71,7 @@ static const struct block_drvr block_drvr[] = { DECLARE_GLOBAL_DATA_PTR; -block_dev_desc_t *get_dev(char* ifname, int dev) +block_dev_desc_t *get_dev(const char *ifname, int dev) { const struct block_drvr *drvr = block_drvr; block_dev_desc_t* (*reloc_get_dev)(int dev); @@ -97,7 +98,7 @@ block_dev_desc_t *get_dev(char* ifname, int dev) return NULL; } #else -block_dev_desc_t *get_dev(char* ifname, int dev) +block_dev_desc_t *get_dev(const char *ifname, int dev) { return NULL; } @@ -288,64 +289,10 @@ void init_part (block_dev_desc_t * dev_desc) return; } #endif + dev_desc->part_type = PART_TYPE_UNKNOWN; } -int get_partition_info (block_dev_desc_t *dev_desc, int part - , disk_partition_t *info) -{ - switch (dev_desc->part_type) { -#ifdef CONFIG_MAC_PARTITION - case PART_TYPE_MAC: - if (get_partition_info_mac(dev_desc,part,info) == 0) { - PRINTF ("## Valid MAC partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_DOS_PARTITION - case PART_TYPE_DOS: - if (get_partition_info_dos(dev_desc,part,info) == 0) { - PRINTF ("## Valid DOS partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_ISO_PARTITION - case PART_TYPE_ISO: - if (get_partition_info_iso(dev_desc,part,info) == 0) { - PRINTF ("## Valid ISO boot partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_AMIGA_PARTITION - case PART_TYPE_AMIGA: - if (get_partition_info_amiga(dev_desc, part, info) == 0) - { - PRINTF ("## Valid Amiga partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_EFI_PARTITION - case PART_TYPE_EFI: - if (get_partition_info_efi(dev_desc,part,info) == 0) { - PRINTF ("## Valid EFI partition found ##\n"); - return (0); - } - break; -#endif - default: - break; - } - return (-1); -} - static void print_part_header (const char *type, block_dev_desc_t * dev_desc) { puts ("\nPartition Map for "); @@ -433,3 +380,267 @@ void print_part (block_dev_desc_t * dev_desc) #endif #endif + +int get_partition_info(block_dev_desc_t *dev_desc, int part + , disk_partition_t *info) +{ +#if defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_SATA) || \ + defined(CONFIG_CMD_SCSI) || \ + defined(CONFIG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) + +#ifdef CONFIG_PARTITION_UUIDS + /* The common case is no UUID support */ + info->uuid[0] = 0; +#endif + + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + if (get_partition_info_mac(dev_desc, part, info) == 0) { + PRINTF("## Valid MAC partition found ##\n"); + return 0; + } + break; +#endif + +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + if (get_partition_info_dos(dev_desc, part, info) == 0) { + PRINTF("## Valid DOS partition found ##\n"); + return 0; + } + break; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + if (get_partition_info_iso(dev_desc, part, info) == 0) { + PRINTF("## Valid ISO boot partition found ##\n"); + return 0; + } + break; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + if (get_partition_info_amiga(dev_desc, part, info) == 0) { + PRINTF("## Valid Amiga partition found ##\n"); + return 0; + } + break; +#endif + +#ifdef CONFIG_EFI_PARTITION + case PART_TYPE_EFI: + if (get_partition_info_efi(dev_desc, part, info) == 0) { + PRINTF("## Valid EFI partition found ##\n"); + return 0; + } + break; +#endif + default: + break; + } +#endif + + return -1; +} + +int get_device(const char *ifname, const char *dev_str, + block_dev_desc_t **dev_desc) +{ + char *ep; + int dev; + + dev = simple_strtoul(dev_str, &ep, 16); + if (*ep) { + printf("** Bad device specification %s %s **\n", + ifname, dev_str); + return -1; + } + + *dev_desc = get_dev(ifname, dev); + if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) { + printf("** Bad device %s %s **\n", ifname, dev_str); + return -1; + } + + return dev; +} + +#define PART_UNSPECIFIED -2 +#define PART_AUTO -1 +#define MAX_SEARCH_PARTITIONS 16 +int get_device_and_partition(const char *ifname, const char *dev_part_str, + block_dev_desc_t **dev_desc, + disk_partition_t *info, int allow_whole_dev) +{ + int ret = -1; + const char *part_str; + char *dup_str = NULL; + const char *dev_str; + int dev; + char *ep; + int p; + int part; + disk_partition_t tmpinfo; + + /* If no dev_part_str, use bootdevice environment variable */ + if (!dev_part_str) + dev_part_str = getenv("bootdevice"); + + /* If still no dev_part_str, it's an error */ + if (!dev_part_str) { + printf("** No device specified **\n"); + goto cleanup; + } + + /* Separate device and partition ID specification */ + part_str = strchr(dev_part_str, ':'); + if (part_str) { + dup_str = strdup(dev_part_str); + dup_str[part_str - dev_part_str] = 0; + dev_str = dup_str; + part_str++; + } else { + dev_str = dev_part_str; + } + + /* Look up the device */ + dev = get_device(ifname, dev_str, dev_desc); + if (dev < 0) + goto cleanup; + + /* Convert partition ID string to number */ + if (!part_str || !*part_str) { + part = PART_UNSPECIFIED; + } else if (!strcmp(part_str, "auto")) { + part = PART_AUTO; + } else { + /* Something specified -> use exactly that */ + part = (int)simple_strtoul(part_str, &ep, 16); + /* + * Less than whole string converted, + * or request for whole device, but caller requires partition. + */ + if (*ep || (part == 0 && !allow_whole_dev)) { + printf("** Bad partition specification %s %s **\n", + ifname, dev_part_str); + goto cleanup; + } + } + + /* + * No partition table on device, + * or user requested partition 0 (entire device). + */ + if (((*dev_desc)->part_type == PART_TYPE_UNKNOWN) || + (part == 0)) { + if (!(*dev_desc)->lba) { + printf("** Bad device size - %s %s **\n", ifname, + dev_str); + goto cleanup; + } + + /* + * If user specified a partition ID other than 0, + * or the calling command only accepts partitions, + * it's an error. + */ + if ((part > 0) || (!allow_whole_dev)) { + printf("** No partition table - %s %s **\n", ifname, + dev_str); + goto cleanup; + } + + info->start = 0; + info->size = (*dev_desc)->lba; + info->blksz = (*dev_desc)->blksz; + info->bootable = 0; +#ifdef CONFIG_PARTITION_UUIDS + info->uuid[0] = 0; +#endif + + ret = 0; + goto cleanup; + } + + /* + * Now there's known to be a partition table, + * not specifying a partition means to pick partition 1. + */ + if (part == PART_UNSPECIFIED) + part = 1; + + /* + * If user didn't specify a partition number, or did specify something + * other than "auto", use that partition number directly. + */ + if (part != PART_AUTO) { + ret = get_partition_info(*dev_desc, part, info); + if (ret) { + printf("** Invalid partition %d **\n", part); + goto cleanup; + } + } else { + /* + * Find the first bootable partition. + * If none are bootable, fall back to the first valid partition. + */ + part = 0; + for (p = 1; p <= MAX_SEARCH_PARTITIONS; p++) { + ret = get_partition_info(*dev_desc, p, info); + if (ret) + continue; + + /* + * First valid partition, or new better partition? + * If so, save partition ID. + */ + if (!part || info->bootable) + part = p; + + /* Best possible partition? Stop searching. */ + if (info->bootable) + break; + + /* + * We now need to search further for best possible. + * If we what we just queried was the best so far, + * save the info since we over-write it next loop. + */ + if (part == p) + tmpinfo = *info; + } + /* If we found any acceptable partition */ + if (part) { + /* + * If we searched all possible partition IDs, + * return the first valid partition we found. + */ + if (p == MAX_SEARCH_PARTITIONS + 1) + *info = tmpinfo; + ret = 0; + } else { + printf("** No valid partitions found **\n"); + goto cleanup; + } + } + if (strncmp((char *)info->type, BOOT_PART_TYPE, sizeof(info->type)) != 0) { + printf("** Invalid partition type \"%.32s\"" + " (expect \"" BOOT_PART_TYPE "\")\n", + info->type); + ret = -1; + goto cleanup; + } + + ret = part; + goto cleanup; + +cleanup: + free(dup_str); + return ret; +} diff --git a/disk/part_dos.c b/disk/part_dos.c index a43dd9c0229..c9a3e2bf02e 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -60,14 +60,20 @@ static inline int is_extended(int part_type) part_type == 0x85); } +static inline int is_bootable(dos_partition_t *p) +{ + return p->boot_ind == 0x80; +} + static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_num) { int lba_start = ext_part_sector + le32_to_int (p->start4); int lba_size = le32_to_int (p->size4); - printf ("%5d\t\t%10d\t%10d\t%2x%s\n", + printf("%5d\t\t%10d\t%10d\t%2x%s%s\n", part_num, lba_start, lba_size, p->sys_ind, - (is_extended (p->sys_ind) ? " Extd" : "")); + (is_extended(p->sys_ind) ? " Extd" : ""), + (is_bootable(p) ? " Boot" : "")); } static int test_block_type(unsigned char *buffer) @@ -163,7 +169,8 @@ static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_s */ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num, - int which_part, disk_partition_t *info) + int which_part, disk_partition_t *info, + unsigned int disksig) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; @@ -182,6 +189,11 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part return -1; } +#ifdef CONFIG_PARTITION_UUIDS + if (!ext_part_sector) + disksig = le32_to_int(&buffer[DOS_PART_DISKSIG_OFFSET]); +#endif + /* Print all primary/logical partitions */ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); for (i = 0; i < 4; i++, pt++) { @@ -222,6 +234,10 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part } /* sprintf(info->type, "%d, pt->sys_ind); */ sprintf ((char *)info->type, "U-Boot"); + info->bootable = is_bootable(pt); +#ifdef CONFIG_PARTITION_UUIDS + sprintf(info->uuid, "%08x-%02x", disksig, part_num); +#endif return 0; } @@ -240,7 +256,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part return get_partition_info_extended (dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, - part_num, which_part, info); + part_num, which_part, info, disksig); } } return -1; @@ -254,7 +270,7 @@ void print_part_dos (block_dev_desc_t *dev_desc) int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info) { - return get_partition_info_extended (dev_desc, 0, 0, 1, part, info); + return get_partition_info_extended(dev_desc, 0, 0, 1, part, info, 0); } diff --git a/disk/part_dos.h b/disk/part_dos.h index de755425e0e..7b77c1d4477 100644 --- a/disk/part_dos.h +++ b/disk/part_dos.h @@ -24,7 +24,7 @@ #ifndef _DISK_PART_DOS_H #define _DISK_PART_DOS_H - +#define DOS_PART_DISKSIG_OFFSET 0x1b8 #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe #define DOS_PBR_FSTYPE_OFFSET 0x36 diff --git a/disk/part_efi.c b/disk/part_efi.c index 02927a0d9da..264ea9c77f6 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -154,6 +154,28 @@ void print_part_efi(block_dev_desc_t * dev_desc) return; } +#ifdef CONFIG_PARTITION_UUIDS +static void uuid_string(unsigned char *uuid, char *str) +{ + static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, + 12, 13, 14, 15}; + int i; + + for (i = 0; i < 16; i++) { + sprintf(str, "%02x", uuid[le[i]]); + str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *str++ = '-'; + break; + } + } +} +#endif + int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, disk_partition_t * info) { @@ -173,6 +195,13 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, return -1; } + if (part > le32_to_int(gpt_head->num_partition_entries) || + !is_pte_valid(&gpt_pte[part - 1])) { + printf("%s: *** ERROR: Invalid partition number %d ***\n", + __func__, part); + return -1; + } + /* The ulong casting limits the maximum disk size to 2 TB */ info->start = (ulong) le64_to_int(gpt_pte[part - 1].starting_lba); /* The ending LBA is inclusive, to calculate size, add 1 to it */ @@ -183,6 +212,9 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->name, "%s", print_efiname(&gpt_pte[part - 1])); sprintf((char *)info->type, "U-Boot"); +#ifdef CONFIG_PARTITION_UUIDS + uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); +#endif debug("%s: start 0x%lX, size 0x%lX, name %s", __func__, info->start, info->size, info->name); diff --git a/doc/README.ext4 b/doc/README.ext4 new file mode 100644 index 00000000000..b3ea8b776d4 --- /dev/null +++ b/doc/README.ext4 @@ -0,0 +1,46 @@ +This patch series adds support for ext4 ls,load and write features in uboot +Journaling is supported for write feature. + +To Enable ext2 ls and load commands, modify the board specific config file with +#define CONFIG_CMD_EXT2 + +To Enable ext4 ls and load commands, modify the board specific config file with +#define CONFIG_CMD_EXT4 + +To enable ext4 write command, modify the board specific config file with +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +Steps to test: + +1. After applying the patch, ext4 specific commands can be seen + in the boot loader prompt using + UBOOT #help + + ext4load- load binary file from a Ext4 file system + ext4ls - list files in a directory (default /) + ext4write- create a file in ext4 formatted partition + +2. To list the files in ext4 formatted partition, execute + ext4ls <interface> <dev[:part]> [directory] + For example: + UBOOT #ext4ls mmc 0:5 /usr/lib + +3. To read and load a file from an ext4 formatted partition to RAM, execute + ext4load <interface> <dev[:part]> [addr] [filename] [bytes] + For example: + UBOOT #ext4load mmc 2:2 0x30007fc0 uImage + +4. To write a file to a ext4 formatted partition. + a) First load a file to RAM at a particular address for example 0x30007fc0. + Now execute ext4write command + ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes] + For example: + UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120 + (here 6183120 is the size of the file to be written) + Note: Absolute path is required for the file to be written + +References : + -- ext4 implementation in Linux Kernel + -- Uboot existing ext2 load and ls implementation + -- Journaling block device JBD2 implementation in linux Kernel diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 5e216587659..f94b56f628c 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -1,5 +1,28 @@ - -Table of interleaving modes supported in cpu/8xxx/ddr/ +Table of interleaving 2-4 controllers +===================================== + +--------------+-----------------------------------------------------------+ + |Configuration | Memory Controller | + | | 1 2 3 4 | + |--------------+--------------+--------------+-----------------------------+ + | Two memory | Not Intlv'ed | Not Intlv'ed | | + | complexes +--------------+--------------+ | + | | 2-way Intlv'ed | | + |--------------+--------------+--------------+--------------+ | + | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | | + | Three memory +--------------+--------------+--------------+ | + | complexes | 2-way Intlv'ed | Not Intlv'ed | | + | +-----------------------------+--------------+ | + | | 3-way Intlv'ed | | + +--------------+--------------+--------------+--------------+--------------+ + | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | + | Four memory +--------------+--------------+--------------+--------------+ + | complexes | 2-way Intlv'ed | 2-way Intlv'ed | + | +-----------------------------+-----------------------------+ + | | 4-way Intlv'ed | + +--------------+-----------------------------------------------------------+ + + +Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ ====================================================== +-------------+---------------------------------------------------------+ | | Rank Interleaving | @@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode # superbank setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" + # 1KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB" + + # 4KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB" + + # 8KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB" + # disable bank (chip-select) interleaving setenv hwconfig "fsl_ddr:bank_intlv=null" diff --git a/doc/README.kwbimage b/doc/README.kwbimage index 6dd942f1097..e91c387b51e 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -25,13 +25,24 @@ for ex. -T kwbimage -a 0x00600000 -e 0x00600000 \ -d u-boot.bin u-boot.kwb -kwimage support available with mkimage utility will generate kirkwood boot -image that can be flashed on the board NAND/SPI flash + +kwbimage support available with mkimage utility will generate kirkwood boot +image that can be flashed on the board NAND/SPI flash. The make target +which uses mkimage to produce such an image is "u-boot.kwb". For example: + + export BUILD_DIR=/tmp/build + make distclean + make yourboard_config + make $BUILD_DIR/u-boot.kwb + Board specific configuration file specifications: ------------------------------------------------ -1. This file must present in the $(BOARDDIR) and the name should be - kwbimage.cfg (since this is used in Makefile) +1. This file must present in the $(BOARDDIR). The default name is + kwbimage.cfg. The name can be set as part of the full path + to the file using CONFIG_SYS_KWD_CONFIG (probably in + include/configs/<yourboard>.h). The path should look like: + $(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg 2. This file can have empty lines and lines starting with "#" as first character to put comments 3. This file can have configuration command lines as mentioned below, diff --git a/doc/README.nand b/doc/README.nand index 1602b5eee96..c130189587b 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -228,6 +228,8 @@ NAND locking command (for chips with active LOCKPRE pin) "nand unlock [offset] [size]" unlock consecutive area (can be called multiple times for different areas) + "nand unlock.allexcept [offset] [size]" + unlock all except specified consecutive area I have tested the code with board containing 128MiB NAND large page chips and 32MiB small page chips. diff --git a/doc/README.pblimage b/doc/README.pblimage new file mode 100644 index 00000000000..2b9bb5c5f5b --- /dev/null +++ b/doc/README.pblimage @@ -0,0 +1,114 @@ +------------------------------------------------------------------ +Freescale PBL(pre-boot loader) Boot Image generation using mkimage +------------------------------------------------------------------ + +The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and +NAND, etc. These SoCs use PBL to load RCW and/or pre-initialization +instructions. For more details refer section 5 Pre-boot loader +specifications of reference manual P3041RM/P4080RM/P5020RM at link: +http://www.freescale.com/webapp/search/Serp.jsp?Reference+Manuals + +Building PBL Boot Image and boot steps +-------------------------------------- + +1. Building PBL Boot Image. + The default Image is u-boot.pbl. + + For eSPI boot(available on P3041/P4080/P5020): + To build the eSPI boot image: + make <board_name>_SPIFLASH_config + make u-boot.pbl + + For SD boot(available on P3041/P4080/P5020): + To build the SD boot image: + make <board_name>_SDCARD_config + make u-boot.pbl + + For Nand boot(available on P3041/P5020): + To build the NAND boot image: + make <board_name>_NAND_config + make u-boot.pbl + + +2. pblimage support available with mkimage utility will generate Freescale PBL +boot image that can be flashed on the board eSPI flash, SD/MMC and NAND. +Following steps describe it in detail. + + 1). Boot from eSPI flash + Write u-boot.pbl to eSPI flash from offset 0x0. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>sf probe 0 + =>sf erase 0 100000 + =>sf write 100000 0 $filesize + Change SW1[1:5] = off off on off on. + + 2). Boot from SD/MMC + Write u-boot.pbl to SD/MMC from offset 0x1000. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>mmcinfo + =>mmc write 100000 8 441 + Change SW1[1:5] = off off on on off. + + 3). Boot from Nand + Write u-boot.pbl to Nand from offset 0x0. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>nand info + =>nand erase 0 100000 + =>nand write 100000 0 $filesize + Change SW1[1:5] = off on off off on + Change SW7[1:4] = on off off on + +Board specific configuration file specifications: +------------------------------------------------ +1. Configuration files rcw.cfg and pbi.cfg must present in the +board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for +PBI instructions. File name must not be changed since they are used +in Makefile. +2. These files can have empty lines and lines starting with "#" as first +character to put comments + +Typical example of rcw.cfg file: +----------------------------------- + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +Typical example of pbi.cfg file: +----------------------------------- + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 + +------------------------------------------------ +Author: Shaohui Xie<Shaohui.Xie@freescale.com> diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 4b5558d5c04..5929a8e0a08 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +apollon arm omap24xx - 2012-09-06 Kyungmin Park <kyungmin.park@samsung.com> tb0229 mips mips32 - 2011-12-12 rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk <wd@denx.de> OXC powerpc MPC8240 309a292 2011-12-07 diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet deleted file mode 100644 index 56b094c9a27..00000000000 --- a/doc/README.srio-boot-corenet +++ /dev/null @@ -1,103 +0,0 @@ ------------------------------- -SRIO Boot on Corenet Platforms ------------------------------- - -For some PowerPC processors with SRIO interface, boot location can be configured -to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot -image, ucode and ENV. All the images can be fetched from another processor's -memory space by SRIO link connected between them. - -This document describes the processes based on an example implemented on P4080DS -platforms and a RCW example with boot from SRIO configuration. - -Environment of the SRIO boot: - a) Master and slave can be SOCs in one board or SOCs in separate boards. - b) They are connected with SRIO links, whether 1x or 4x, and directly or - through switch system. - c) Only Master has NorFlash for booting, and all the Master's and Slave's - U-Boot images, UCodes will be stored in this flash. - d) Slave has its own EEPROM for RCW and PBI. - e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot - location to SRIO, and holdoff all the cores if needed. - - ---------- ----------- ----------- - | | | | | | - | | | | | | - | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM] - | | | |<===========>| | - | | | | | | - ---------- ----------- ----------- - -The example based on P4080DS platform: - Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO - ports 0 will be connected directly and will be used for the boot from SRIO. - - 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. - 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 - 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 - 00000020: f400 0000 0100 0000 0000 0000 0000 0000 - 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 - 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe - - 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. - 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 - 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 - 00000020: f440 0000 0100 0000 0000 0000 0000 0000 - 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 - 00000040: 0000 0000 0000 0000 0813 8040 063c 778f - - 3. Sequence in Step by Step. - a) Update RCW for slave with boot from SRIO port 0 configuration. - b) Program slave's U-Boot image, UCode, and ENV parameters into master's - NorFlash. - c) Start up master and it will boot up normally from its NorFlash. - Then, it will finish necessary configurations for slave's boot from - SRIO port 0. - d) Master will set inbound SRIO windows covered slave's U-Boot image stored - in master's NorFlash. - e) Master will set an inbound SRIO window covered slave's UCode stored in - master's NorFlash. - f) Master will set an inbound SRIO window covered slave's ENV stored in - master's NorFlash. - g) If need to release slave's core, master will set outbound SRIO windows - in order to configure slave's registers for the core's releasing. - h) If all cores of slave in holdoff, slave should be powered on before all - the above master's steps, and wait to be released by master. If not all - cores in holdoff, that means core 0 will start up normally, slave should - be powered on after all the above master's steps. In the startup phase - of the slave from SRIO, it will finish some necessary configurations. - i) Slave will set a specific TLB entry for the boot process. - j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. - k) Slave will set a specific TLB entry in order to fetch UCode and ENV - from master. - l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV. - -How to use this feature: - To use this feature, you need to focus three points. - - 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff - configurations if needed. - Please refer to the examples given above. - - 2. U-Boot image's compilation. - For master, U-Boot image should be generated specifically by - - make xxxx_SRIOBOOT_MASTER_config. - - For example, master U-Boot image used on P4080DS should be compiled with - - make P4080DS_SRIOBOOT_MASTER_config. - - For slave, U-Boot image should be generated specifically by - - make xxxx_SRIOBOOT_SLAVE_config. - - For example, slave U-Boot image used on P4080DS should be compiled with - - make P4080DS_SRIOBOOT_SLAVE_config. - - 3. Necessary modifications based on a specific environment. - For a specific environment, the SRIO port for boot, the addresses of the - slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other - configurations can be modified in the file: - include/configs/corenet_ds.h. diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet new file mode 100644 index 00000000000..cd7e7ee9b34 --- /dev/null +++ b/doc/README.srio-pcie-boot-corenet @@ -0,0 +1,112 @@ +--------------------------------------- +SRIO and PCIE Boot on Corenet Platforms +--------------------------------------- + +For some PowerPC processors with SRIO or PCIE interface, boot location can be +configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can +do without flash for u-boot image, ucode and ENV. All the images can be fetched +from another processor's memory space by SRIO or PCIE link connected between +them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO or PCIE configuration. + +Environment of the SRIO or PCIE boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and + directly or through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set + the boot location to SRIO or PCIE, and holdoff all the cores. + + ---------- ----------- ----------- + | | | | | | + | | | | | | + | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM] + | | | |<===========>| | + | | | | | | + ---------- ----------- ----------- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO or PCIE. + Their SRIO or PCIE ports 1 will be connected directly and will be used for + the boot from SRIO or PCIE. + + 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 + 00000020: f440 0000 0100 0000 0000 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 063c 778f + + 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 1440 4000 0000 2000 + 00000020: f040 0000 0100 0000 0020 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 547e ffc9 + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save + environment for master. + setenv bootmaster SRIO1 + or + setenv bootmaster PCIE1 + saveenv + d) Restart up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO or PCIE port 1. + e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot + image stored in master's NorFlash. + f) Master will set an inbound SRIO or PCIE window covered slave's UCode + and ENV stored in master's NorFlash. + g) Master will set outbound SRIO or PCIE windows in order to configure + slave's registers for the core's releasing. + h) Since all cores of slave in holdoff, slave should be powered on before + all the above master's steps, and wait to be released by master. In the + startup phase of the slave from SRIO or PCIE, it will finish some + necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for + the boot. + k) Slave will set a specific TLB entry in order to fetch UCode and ENV + from master. + l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for + UCode and ENV. + +How to use this feature: + To use this feature, you need to focus those points. + + 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff + configurations. + Please refer to the examples given above. + + 2. U-Boot image's compilation. + For master, U-Boot image should be generated normally. + + For example, master U-Boot image used on P4080DS should be compiled with + + make P4080DS_config. + + For slave, U-Boot image should be generated specifically by + + make xxxx_SRIO_PCIE_BOOT_config. + + For example, slave U-Boot image used on P4080DS should be compiled with + + make P4080DS_SRIO_PCIE_BOOT_config. + + 3. Necessary modifications based on a specific environment. + For a specific environment, the addresses of the slave's U-Boot image, + UCode, ENV stored in master's NorFlash, and any other configurations + can be modified in the file: + include/configs/corenet_ds.h. + + 4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2" + or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to + perform the role as a master for boot from SRIO or PCIE. diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file mode 100644 index 00000000000..86ae4082de9 --- /dev/null +++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt @@ -0,0 +1,53 @@ +NAND Flash +---------- + +(there isn't yet a generic binding in Linux, so this describes what is in +U-Boot. There should not be Linux-specific or U-Boot specific binding, just +a binding that describes this hardware. But agreeing a binding in Linux in +the absence of a driver may be beyond my powers.) + +The device node for a NAND flash device is as follows: + +Required properties : + - compatible : Should be "manufacturer,device", "nand-flash" + +This node should sit inside its controller. + + +Nvidia NAND Controller +---------------------- + +The device node for a NAND flash controller is as follows: + +Optional properties: + +nvidia,wp-gpios : GPIO of write-protect line, three cells in the format: + phandle, parameter, flags +nvidia,nand-width : bus width of the NAND device in bits + + - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns. + Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH), + TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL + + MAX_TRP_TREA is: + non-EDO mode: Max(tRP, tREA) + 6ns + EDO mode: tRP timing + +The 'reg' property should provide the chip select used by the flash chip. + + +Example +------- + +nand-controller@0x70008000 { + compatible = "nvidia,tegra20-nand"; + #address-cells = <1>; + #size-cells = <0>; + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,nand-width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; +}; diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c index 58402b9289c..247cf060e43 100644 --- a/drivers/block/systemace.c +++ b/drivers/block/systemace.c @@ -51,24 +51,36 @@ * to be the base address for the chip, usually in the local * peripheral bus. */ -#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8) + +static u32 base = CONFIG_SYS_SYSTEMACE_BASE; +static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; + +static void ace_writew(u16 val, unsigned off) +{ + if (width == 8) { #if !defined(__BIG_ENDIAN) -#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \ - (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1))) -#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \ - writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);} + writeb(val >> 8, base + off); + writeb(val, base + off + 1); #else -#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \ - (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8)) -#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \ - writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);} + writeb(val, base + off); + writeb(val >> 8, base + off + 1); #endif + } + out16(base + off, val); +} + +static u16 ace_readw(unsigned off) +{ + if (width == 8) { +#if !defined(__BIG_ENDIAN) + return (readb(base + off) << 8) | readb(base + off + 1); #else -#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off)) -#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val)) + return readb(base + off) | (readb(base + off + 1) << 8); #endif + } -/* */ + return in16(base + off); +} static unsigned long systemace_read(int dev, unsigned long start, unsigned long blkcnt, void *buffer); @@ -121,7 +133,7 @@ block_dev_desc_t *systemace_get_dev(int dev) /* * Ensure the correct bus mode (8/16 bits) gets enabled */ - ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); + ace_writew(width == 8 ? 0 : 0x0001, 0); init_part(&systemace_dev); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 060145bbeec..5d504dffd11 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -63,10 +63,23 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, char *str_env; int ret; - sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s %lx", - op == DFU_OP_READ ? "load" : "write", - dfu->data.mmc.dev, dfu->data.mmc.part, - (unsigned int) buf, dfu->name, *len); + switch (dfu->layout) { + case DFU_FS_FAT: + sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s %lx", + op == DFU_OP_READ ? "load" : "write", + dfu->data.mmc.dev, dfu->data.mmc.part, + (unsigned int) buf, dfu->name, *len); + break; + case DFU_FS_EXT4: + sprintf(cmd_buf, "ext4%s mmc %d:%d /%s 0x%x %ld", + op == DFU_OP_READ ? "load" : "write", + dfu->data.mmc.dev, dfu->data.mmc.part, + dfu->name, (unsigned int) buf, *len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); @@ -76,7 +89,7 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return ret; } - if (dfu->layout != DFU_RAW_ADDR) { + if (dfu->layout != DFU_RAW_ADDR && op == DFU_OP_READ) { str_env = getenv("filesize"); if (str_env == NULL) { puts("dfu: Wrong file size!\n"); @@ -107,6 +120,7 @@ int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) ret = mmc_block_write(dfu, buf, len); break; case DFU_FS_FAT: + case DFU_FS_EXT4: ret = mmc_file_write(dfu, buf, len); break; default: @@ -126,6 +140,7 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) ret = mmc_block_read(dfu, buf, len); break; case DFU_FS_FAT: + case DFU_FS_EXT4: ret = mmc_file_read(dfu, buf, len); break; default: @@ -149,12 +164,17 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) dfu->data.mmc.lba_blk_size = get_mmc_blk_size(dfu->dev_num); } else if (!strcmp(st, "fat")) { dfu->layout = DFU_FS_FAT; - dfu->data.mmc.dev = simple_strtoul(s, &s, 10); - dfu->data.mmc.part = simple_strtoul(++s, &s, 10); + } else if (!strcmp(st, "ext4")) { + dfu->layout = DFU_FS_EXT4; } else { printf("%s: Memory layout (%s) not supported!\n", __func__, st); } + if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) { + dfu->data.mmc.dev = simple_strtoul(s, &s, 10); + dfu->data.mmc.part = simple_strtoul(++s, &s, 10); + } + dfu->read_medium = dfu_read_medium_mmc; dfu->write_medium = dfu_write_medium_mmc; diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 8cfcf8283b3..747f4cf9212 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -34,10 +34,10 @@ #include <asm/gpio.h> enum { - TEGRA20_CMD_INFO, - TEGRA20_CMD_PORT, - TEGRA20_CMD_OUTPUT, - TEGRA20_CMD_INPUT, + TEGRA_CMD_INFO, + TEGRA_CMD_PORT, + TEGRA_CMD_OUTPUT, + TEGRA_CMD_INPUT, }; static struct gpio_names { diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 978507ba298..094305fdf93 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -442,6 +442,14 @@ int i2c_set_bus_num(unsigned int bus) return -1; } +#if I2C_BUS_MAX == 4 + if (bus == 3) + i2c_base = (struct i2c *)I2C_BASE4; + else + if (bus == 2) + i2c_base = (struct i2c *)I2C_BASE3; + else +#endif #if I2C_BUS_MAX == 3 if (bus == 2) i2c_base = (struct i2c *)I2C_BASE3; diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index b4eb49127eb..e3be14e3cf3 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -262,7 +262,7 @@ exit: return error; } -static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len) +static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len) { int error; struct i2c_trans_info trans_info; @@ -275,12 +275,12 @@ static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len) error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); if (error) - debug("tegra20_i2c_write_data: Error (%d) !!!\n", error); + debug("tegra_i2c_write_data: Error (%d) !!!\n", error); return error; } -static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len) +static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len) { int error; struct i2c_trans_info trans_info; @@ -293,7 +293,7 @@ static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len) error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); if (error) - debug("tegra20_i2c_read_data: Error (%d) !!!\n", error); + debug("tegra_i2c_read_data: Error (%d) !!!\n", error); return error; } @@ -438,7 +438,7 @@ int i2c_write_data(uchar chip, uchar *buffer, int len) debug("\n"); /* Shift 7-bit address over for lower-level i2c functions */ - rc = tegra20_i2c_write_data(chip << 1, buffer, len); + rc = tegra_i2c_write_data(chip << 1, buffer, len); if (rc) debug("i2c_write_data(): rc=%d\n", rc); @@ -452,7 +452,7 @@ int i2c_read_data(uchar chip, uchar *buffer, int len) debug("inside i2c_read_data():\n"); /* Shift 7-bit address over for lower-level i2c functions */ - rc = tegra20_i2c_read_data(chip << 1, buffer, len); + rc = tegra_i2c_read_data(chip << 1, buffer, len); if (rc) { debug("i2c_read_data(): rc=%d\n", rc); return rc; diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 68c6a16bcc2..0805e866787 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libinput.o COBJS-$(CONFIG_I8042_KBD) += i8042.o -COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o +COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o ifdef CONFIG_PS2KBD COBJS-y += keyboard.o pc_keyb.o COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index a7d04b7ea39..223cd5d65c8 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -275,5 +275,59 @@ void init_laws(void) law_table[i].size, law_table[i].trgt_id); } +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* check RCW to get which port is used for boot */ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 bootloc = in_be32(&gur->rcwsr[6]); + /* + * in SRIO or PCIE boot we need to set specail LAWs for + * SRIO or PCIE interfaces. + */ + switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { + case 0x0: /* boot from PCIE1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_1); + break; + case 0x1: /* boot from PCIE2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_2); + break; + case 0x2: /* boot from PCIE3 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_PCIE_3); + break; + case 0x8: /* boot from SRIO1 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_1); + break; + case 0x9: /* boot from SRIO2 */ + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, + LAW_TRGT_IF_RIO_2); + break; + default: + break; + } +#endif + return ; } diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index db2c7ab75ce..af1380a4550 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -52,7 +52,7 @@ static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd) debug("CMD%d time out\n", cmd->cmdidx); return TIMEOUT; } else if ((hoststatus & SDI_STA_CCRCFAIL) && - (cmd->flags & MMC_RSP_CRC)) { + (cmd->resp_type & MMC_RSP_CRC)) { printf("CMD%d CRC error\n", cmd->cmdidx); return -EILSEQ; } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index fa673cf2c68..a60cfe1cb0d 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -236,7 +236,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; printf("CURR STATE:%d\n", status); #endif - if (!timeout) { + if (timeout <= 0) { printf("Timeout waiting card ready\n"); return TIMEOUT; } @@ -658,7 +658,7 @@ int mmc_send_op_cond(struct mmc *mmc) } -int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd) +int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) { struct mmc_cmd cmd; struct mmc_data data; @@ -669,7 +669,7 @@ int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd) cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = 0; - data.dest = ext_csd; + data.dest = (char *)ext_csd; data.blocks = 1; data.blocksize = 512; data.flags = MMC_DATA_READ; @@ -704,7 +704,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) int mmc_change_freq(struct mmc *mmc) { - ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512); + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512); char cardtype; int err; @@ -963,8 +963,8 @@ int mmc_startup(struct mmc *mmc) uint mult, freq; u64 cmult, csize, capacity; struct mmc_cmd cmd; - ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512); - ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512); + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512); + ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512); int timeout = 1000; #ifdef CONFIG_MMC_SPI_CRC_ON @@ -1137,7 +1137,8 @@ int mmc_startup(struct mmc *mmc) } /* store the partition info of emmc */ - if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || + ext_csd[EXT_CSD_BOOT_MULT]) mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; } @@ -1232,7 +1233,9 @@ int mmc_startup(struct mmc *mmc) (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28, (mmc->cid[2] >> 24) & 0xf); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(&mmc->block_dev); +#endif return 0; } @@ -1283,10 +1286,9 @@ int mmc_register(struct mmc *mmc) block_dev_desc_t *mmc_get_dev(int dev) { struct mmc *mmc = find_mmc_device(dev); - if (!mmc) + if (!mmc || mmc_init(mmc)) return NULL; - mmc_init(mmc); return &mmc->block_dev; } #endif diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 9a98c6b85be..c80b41b1925 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -119,6 +119,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) (uint32_t)(priv->desc->cmd.address + cache_data_count)); } + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range((uint32_t)priv->desc->cmd.address, + (uint32_t)(priv->desc->cmd.address + cache_data_count)); + priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | (data_count << MXS_DMA_DESC_BYTES_OFFSET); diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 2c5bf17bb3c..b3ec441b66a 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -118,7 +118,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, int ret; /* The card can send a "busy" response */ - if (cmd->flags & MMC_RSP_BUSY) + if (cmd->resp_type & MMC_RSP_BUSY) cmdat |= MMC_CMDAT_BUSY; /* Inform the controller about response type */ @@ -181,9 +181,11 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) /* The command response didn't arrive */ if (stat & MMC_STAT_TIME_OUT_RESPONSE) return -ETIMEDOUT; - else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) { + else if (stat & MMC_STAT_RES_CRC_ERROR + && cmd->resp_type & MMC_RSP_CRC) { #ifdef PXAMMC_CRC_SKIP - if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31)) + if (cmd->resp_type & MMC_RSP_136 + && cmd->response[0] & (1 << 31)) printf("Ignoring CRC, this may be dangerous!\n"); else #endif diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 1d4481b974a..b9782367e2a 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -21,6 +21,7 @@ #include <malloc.h> #include <sdhci.h> #include <asm/arch/mmc.h> +#include <asm/arch/clk.h> static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -54,7 +55,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) * 00 = Delay3 (inverter delay) * 10 = Delay4 (inverter delay + 2ns) */ - val = SDHCI_CTRL3_FCSEL3 | SDHCI_CTRL3_FCSEL1; + val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; sdhci_writel(host, val, SDHCI_CONTROL3); /* @@ -69,7 +70,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) +int s5p_sdhci_init(u32 regbase, int index, int bus_width) { struct sdhci_host *host = NULL; host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); @@ -80,19 +81,18 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->name = S5P_NAME; host->ioaddr = (void *)regbase; - host->quirks = quirks; - host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - if (quirks & SDHCI_QUIRK_REG32_RW) - host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; - else - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->set_control_reg = &s5p_sdhci_set_control_reg; + host->set_clock = set_mmc_clk; + host->index = index; host->host_caps = MMC_MODE_HC; - add_sdhci(host, max_clk, min_clk); + add_sdhci(host, 52000000, 400000); return 0; } diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1709643da83..2e3c408bc55 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -260,7 +260,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (clock == 0) return 0; - if (host->version >= SDHCI_SPEC_300) { + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { /* Version 3.00 divisors must be a multiple of 2. */ if (mmc->f_max <= clock) div = 1; @@ -279,6 +279,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } div >>= 1; + if (host->set_clock) + host->set_clock(host->index, div); + clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; @@ -347,10 +350,10 @@ void sdhci_set_ios(struct mmc *mmc) ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); if (mmc->bus_width == 8) { ctrl &= ~SDHCI_CTRL_4BITBUS; - if (host->version >= SDHCI_SPEC_300) + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) ctrl |= SDHCI_CTRL_8BITBUS; } else { - if (host->version >= SDHCI_SPEC_300) + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) ctrl &= ~SDHCI_CTRL_8BITBUS; if (mmc->bus_width == 4) ctrl |= SDHCI_CTRL_4BITBUS; @@ -381,12 +384,25 @@ int sdhci_init(struct mmc *mmc) } } + sdhci_set_power(host, fls(mmc->voltages) - 1); + + if (host->quirks & SDHCI_QUIRK_NO_CD) { + unsigned int status; + + sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, + SDHCI_HOST_CONTROL); + + status = sdhci_readl(host, SDHCI_PRESENT_STATE); + while ((!(status & SDHCI_CARD_PRESENT)) || + (!(status & SDHCI_CARD_STATE_STABLE)) || + (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) + status = sdhci_readl(host, SDHCI_PRESENT_STATE); + } + /* Eable all state */ sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE); sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE); - sdhci_set_power(host, fls(mmc->voltages) - 1); - return 0; } @@ -421,7 +437,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (max_clk) mmc->f_max = max_clk; else { - if (host->version >= SDHCI_SPEC_300) + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else @@ -436,7 +452,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) if (min_clk) mmc->f_min = min_clk; else { - if (host->version >= SDHCI_SPEC_300) + if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; else mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 2835e242f89..4588568a6db 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -593,7 +593,7 @@ int mmcif_mmc_init(void) mmc->f_max = CLKDEV_EMMC_DATA; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | - MMC_MODE_8BIT; + MMC_MODE_8BIT | MMC_MODE_HC; memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); mmc->send_cmd = sh_mmcif_request; mmc->set_ios = sh_mmcif_set_ios; diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index ddfa7279c22..ca8fad86572 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -25,7 +25,7 @@ #include <asm/io.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> -#include "tegra_mmc.h" +#include <asm/arch/tegra_mmc.h> /* support 4 mmc hosts */ struct mmc mmc_dev[4]; @@ -39,31 +39,31 @@ struct mmc_host mmc_host[4]; * @param host Structure to fill in (base, reg, mmc_id) * @param dev_index Device index (0-3) */ -static void tegra20_get_setup(struct mmc_host *host, int dev_index) +static void tegra_get_setup(struct mmc_host *host, int dev_index) { - debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index); + debug("tegra_get_setup: dev_index = %d\n", dev_index); switch (dev_index) { case 1: - host->base = TEGRA20_SDMMC3_BASE; + host->base = TEGRA_SDMMC3_BASE; host->mmc_id = PERIPH_ID_SDMMC3; break; case 2: - host->base = TEGRA20_SDMMC2_BASE; + host->base = TEGRA_SDMMC2_BASE; host->mmc_id = PERIPH_ID_SDMMC2; break; case 3: - host->base = TEGRA20_SDMMC1_BASE; + host->base = TEGRA_SDMMC1_BASE; host->mmc_id = PERIPH_ID_SDMMC1; break; case 0: default: - host->base = TEGRA20_SDMMC4_BASE; + host->base = TEGRA_SDMMC4_BASE; host->mmc_id = PERIPH_ID_SDMMC4; break; } - host->reg = (struct tegra20_mmc *)host->base; + host->reg = (struct tegra_mmc *)host->base; } static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) @@ -345,7 +345,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) debug(" mmc_change_clock called\n"); /* - * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz, + * Change Tegra SDMMCx clock divisor here. Source is 216MHz, * PLLP_OUT0 */ if (clock == 0) @@ -494,11 +494,11 @@ static int mmc_core_init(struct mmc *mmc) return 0; } -int tegra20_mmc_getcd(struct mmc *mmc) +int tegra_mmc_getcd(struct mmc *mmc) { struct mmc_host *host = (struct mmc_host *)mmc->priv; - debug("tegra20_mmc_getcd called\n"); + debug("tegra_mmc_getcd called\n"); if (host->cd_gpio >= 0) return !gpio_get_value(host->cd_gpio); @@ -506,13 +506,13 @@ int tegra20_mmc_getcd(struct mmc *mmc) return 1; } -int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) +int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) { struct mmc_host *host; char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ struct mmc *mmc; - debug(" tegra20_mmc_init: index %d, bus width %d " + debug(" tegra_mmc_init: index %d, bus width %d " "pwr_gpio %d cd_gpio %d\n", dev_index, bus_width, pwr_gpio, cd_gpio); @@ -521,7 +521,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) host->clock = 0; host->pwr_gpio = pwr_gpio; host->cd_gpio = cd_gpio; - tegra20_get_setup(host, dev_index); + tegra_get_setup(host, dev_index); clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); @@ -539,12 +539,12 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) mmc = &mmc_dev[dev_index]; - sprintf(mmc->name, "Tegra20 SD/MMC"); + sprintf(mmc->name, "Tegra SD/MMC"); mmc->priv = host; mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_core_init; - mmc->getcd = tegra20_mmc_getcd; + mmc->getcd = tegra_mmc_getcd; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; if (bus_width == 8) @@ -559,7 +559,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) * Both of these are the closest equivalents w/216MHz source - * clock and Tegra20 SDMMC divisors. + * clock and Tegra SDMMC divisors. */ mmc->f_min = 375000; mmc->f_max = 48000000; diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 29dc20ef5e2..beb99cacb66 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -62,6 +62,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o +COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 936186f75e6..d0ded483e2a 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -25,168 +25,23 @@ #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) #include <asm/arch/imx-regs.h> #endif +#include <fsl_nfc.h> #define DRIVER_NAME "mxc_nand" -/* - * TODO: Use same register defs here as nand_spl mxc nand driver. - */ -/* - * Register map and bit definitions for the Freescale NAND Flash Controller - * present in various i.MX devices. - * - * MX31 and MX27 have version 1 which has - * 4 512 byte main buffers and - * 4 16 byte spare buffers - * to support up to 2K byte pagesize nand. - * Reading or writing a 2K page requires 4 FDI/FDO cycles. - * - * MX25 has version 1.1 which has - * 8 512 byte main buffers and - * 8 64 byte spare buffers - * to support up to 4K byte pagesize nand. - * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. - * Also some of registers are moved and/or changed meaning as seen below. - */ -#if defined(CONFIG_MX31) || defined(CONFIG_MX27) -#define MXC_NFC_V1 -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) -#define MXC_NFC_V1_1 -#else -#warning "MXC NFC version not defined" -#endif - -#if defined(MXC_NFC_V1) -#define NAND_MXC_NR_BUFS 4 -#define NAND_MXC_SPARE_BUF_SIZE 16 -#define NAND_MXC_REG_OFFSET 0xe00 -#define is_mxc_nfc_11() 0 -#elif defined(MXC_NFC_V1_1) -#define NAND_MXC_NR_BUFS 8 -#define NAND_MXC_SPARE_BUF_SIZE 64 -#define NAND_MXC_REG_OFFSET 0x1e00 -#define is_mxc_nfc_11() 1 -#else -#error "define CONFIG_NAND_MXC_VXXX to use mtd mxc nand driver" -#endif -struct nfc_regs { - uint8_t main_area[NAND_MXC_NR_BUFS][0x200]; - uint8_t spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; - /* - * reserved size is offset of nfc registers - * minus total main and spare sizes - */ - uint8_t reserved1[NAND_MXC_REG_OFFSET - - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; -#if defined(MXC_NFC_V1) - uint16_t nfc_buf_size; - uint16_t reserved2; - uint16_t nfc_buf_addr; - uint16_t nfc_flash_addr; - uint16_t nfc_flash_cmd; - uint16_t nfc_config; - uint16_t nfc_ecc_status_result; - uint16_t nfc_rsltmain_area; - uint16_t nfc_rsltspare_area; - uint16_t nfc_wrprot; - uint16_t nfc_unlockstart_blkaddr; - uint16_t nfc_unlockend_blkaddr; - uint16_t nfc_nf_wrprst; - uint16_t nfc_config1; - uint16_t nfc_config2; -#elif defined(MXC_NFC_V1_1) - uint16_t reserved2[2]; - uint16_t nfc_buf_addr; - uint16_t nfc_flash_addr; - uint16_t nfc_flash_cmd; - uint16_t nfc_config; - uint16_t nfc_ecc_status_result; - uint16_t nfc_ecc_status_result2; - uint16_t nfc_spare_area_size; - uint16_t nfc_wrprot; - uint16_t reserved3[2]; - uint16_t nfc_nf_wrprst; - uint16_t nfc_config1; - uint16_t nfc_config2; - uint16_t reserved4; - uint16_t nfc_unlockstart_blkaddr; - uint16_t nfc_unlockend_blkaddr; - uint16_t nfc_unlockstart_blkaddr1; - uint16_t nfc_unlockend_blkaddr1; - uint16_t nfc_unlockstart_blkaddr2; - uint16_t nfc_unlockend_blkaddr2; - uint16_t nfc_unlockstart_blkaddr3; - uint16_t nfc_unlockend_blkaddr3; -#endif -}; - -/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register - * for Command operation - */ -#define NFC_CMD 0x1 - -/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register - * for Address operation - */ -#define NFC_ADDR 0x2 - -/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register - * for Input operation - */ -#define NFC_INPUT 0x4 - -/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register - * for Data Output operation - */ -#define NFC_OUTPUT 0x8 - -/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register - * for Read ID operation - */ -#define NFC_ID 0x10 - -/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register - * for Read Status operation - */ -#define NFC_STATUS 0x20 - -/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read - * Status operation - */ -#define NFC_INT 0x8000 - -#ifdef MXC_NFC_V1_1 -#define NFC_4_8N_ECC (1 << 0) -#else -#define NFC_4_8N_ECC 0 -#endif -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) - typedef enum {false, true} bool; struct mxc_nand_host { - struct mtd_info mtd; - struct nand_chip *nand; - - struct nfc_regs __iomem *regs; - int spare_only; - int status_request; - int pagesize_2k; - int clk_act; - uint16_t col_addr; - unsigned int page_addr; + struct mtd_info mtd; + struct nand_chip *nand; + + struct fsl_nfc_regs __iomem *regs; + int spare_only; + int status_request; + int pagesize_2k; + int clk_act; + uint16_t col_addr; + unsigned int page_addr; }; static struct mxc_nand_host mxc_host; @@ -222,7 +77,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = { .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, }; #endif -#elif defined(MXC_NFC_V1_1) +#elif defined(MXC_NFC_V2_1) #ifndef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 9, @@ -268,8 +123,7 @@ static int is_16bit_nand(void) #elif defined(CONFIG_MX25) || defined(CONFIG_MX35) static int is_16bit_nand(void) { - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; + struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL) return 1; @@ -304,10 +158,10 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp; while (max_retries-- > 0) { - if (readw(&host->regs->nfc_config2) & NFC_INT) { - tmp = readw(&host->regs->nfc_config2); + if (readw(&host->regs->config2) & NFC_INT) { + tmp = readw(&host->regs->config2); tmp &= ~NFC_INT; - writew(tmp, &host->regs->nfc_config2); + writew(tmp, &host->regs->config2); break; } udelay(1); @@ -326,8 +180,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); - writew(cmd, &host->regs->nfc_flash_cmd); - writew(NFC_CMD, &host->regs->nfc_config2); + writew(cmd, &host->regs->flash_cmd); + writew(NFC_CMD, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, cmd); @@ -342,8 +196,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); - writew(addr, &host->regs->nfc_flash_addr); - writew(NFC_ADDR, &host->regs->nfc_config2); + writew(addr, &host->regs->flash_addr); + writew(NFC_ADDR, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, addr); @@ -359,7 +213,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, if (spare_only) MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only); - if (is_mxc_nfc_11()) { + if (is_mxc_nfc_21()) { int i; /* * The controller copies the 64 bytes of spare data from @@ -375,19 +229,19 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } } - writew(buf_id, &host->regs->nfc_buf_addr); + writew(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readw(&host->regs->nfc_config1); + uint16_t config1 = readw(&host->regs->config1); if (spare_only) config1 |= NFC_SP_EN; else - config1 &= ~(NFC_SP_EN); - writew(config1, &host->regs->nfc_config1); + config1 &= ~NFC_SP_EN; + writew(config1, &host->regs->config1); } - writew(NFC_INPUT, &host->regs->nfc_config2); + writew(NFC_INPUT, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -402,24 +256,24 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); - writew(buf_id, &host->regs->nfc_buf_addr); + writew(buf_id, &host->regs->buf_addr); /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint32_t config1 = readw(&host->regs->nfc_config1); + uint32_t config1 = readw(&host->regs->config1); if (spare_only) config1 |= NFC_SP_EN; else config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->nfc_config1); + writew(config1, &host->regs->config1); } - writew(NFC_OUTPUT, &host->regs->nfc_config2); + writew(NFC_OUTPUT, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); - if (is_mxc_nfc_11()) { + if (is_mxc_nfc_21()) { int i; /* @@ -442,14 +296,14 @@ static void send_read_id(struct mxc_nand_host *host) uint16_t tmp; /* NANDFC buffer 0 is used for device ID output */ - writew(0x0, &host->regs->nfc_buf_addr); + writew(0x0, &host->regs->buf_addr); /* Read ID into main buffer */ - tmp = readw(&host->regs->nfc_config1); + tmp = readw(&host->regs->config1); tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->nfc_config1); + writew(tmp, &host->regs->config1); - writew(NFC_ID, &host->regs->nfc_config2); + writew(NFC_ID, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -469,14 +323,14 @@ static uint16_t get_dev_status(struct mxc_nand_host *host) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ - writew(1, &host->regs->nfc_buf_addr); + writew(1, &host->regs->buf_addr); /* Read status into main buffer */ - tmp = readw(&host->regs->nfc_config1); + tmp = readw(&host->regs->config1); tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->nfc_config1); + writew(tmp, &host->regs->config1); - writew(NFC_STATUS, &host->regs->nfc_config2); + writew(NFC_STATUS, &host->regs->config2); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -501,29 +355,29 @@ static int mxc_nand_dev_ready(struct mtd_info *mtd) return 1; } -#ifdef CONFIG_MXC_NAND_HWECC -static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) -{ - /* - * If HW ECC is enabled, we turn it on during init. There is - * no need to enable again here. - */ -} - -#ifdef MXC_NFC_V1_1 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t tmp = readw(&host->regs->nfc_config1); + uint16_t tmp = readw(&host->regs->config1); if (on) tmp |= NFC_ECC_EN; else tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->nfc_config1); + writew(tmp, &host->regs->config1); +} + +#ifdef CONFIG_MXC_NAND_HWECC +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + /* + * If HW ECC is enabled, we turn it on during init. There is + * no need to enable again here. + */ } +#ifdef MXC_NFC_V2_1 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd) @@ -616,7 +470,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, size = mtd->oobsize - (oob - chip->oob_poi); if (size) chip->read_buf(mtd, oob, size); - _mxc_nand_enable_hwecc(mtd, 0); + _mxc_nand_enable_hwecc(mtd, 1); return 0; } @@ -799,7 +653,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result); + uint32_t ecc_status = readl(&host->regs->ecc_status_result); int subpages = mtd->writesize / nand_chip->subpagesize; int pg2blk_shift = nand_chip->phys_erase_shift - nand_chip->page_shift; @@ -832,7 +686,6 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, #define mxc_nand_write_page_syndrome NULL #define mxc_nand_write_page_raw_syndrome NULL #define mxc_nand_write_oob_syndrome NULL -#define mxc_nfc_11_nand_correct_data NULL static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) @@ -845,7 +698,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result); + uint16_t ecc_status = readw(&host->regs->ecc_status_result); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, @@ -1208,7 +1061,7 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_PAGEPROG: send_prog_page(host, 0, host->spare_only); - if (host->pagesize_2k && !is_mxc_nfc_11()) { + if (host->pagesize_2k && is_mxc_nfc_1()) { /* data in 4 areas */ send_prog_page(host, 1, host->spare_only); send_prog_page(host, 2, host->spare_only); @@ -1258,7 +1111,7 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command, send_cmd(host, NAND_CMD_READSTART); /* read for each AREA */ send_read_page(host, 0, host->spare_only); - if (!is_mxc_nfc_11()) { + if (is_mxc_nfc_1()) { send_read_page(host, 1, host->spare_only); send_read_page(host, 2, host->spare_only); send_read_page(host, 3, host->spare_only); @@ -1284,24 +1137,6 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command, } } -#ifdef MXC_NFC_V1_1 -static void mxc_setup_config1(void) -{ - uint16_t tmp; - - tmp = readw(&host->regs->nfc_config1); - tmp |= NFC_ONE_CYCLE; - tmp |= NFC_4_8N_ECC; - writew(tmp, &host->regs->nfc_config1); - if (host->pagesize_2k) - writew(64/2, &host->regs->nfc_spare_area_size); - else - writew(16/2, &host->regs->nfc_spare_area_size); -} -#else -#define mxc_setup_config1() -#endif - #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; @@ -1332,8 +1167,9 @@ static struct nand_bbt_descr bbt_mirror_descr = { int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; +#ifdef MXC_NFC_V2_1 uint16_t tmp; - int err = 0; +#endif #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT this->options |= NAND_USE_FLASH_BBT; @@ -1359,14 +1195,14 @@ int board_nand_init(struct nand_chip *this) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf; - host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; host->clk_act = 1; #ifdef CONFIG_MXC_NAND_HWECC this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; this->ecc.correct = mxc_nand_correct_data; - if (is_mxc_nfc_11()) { + if (is_mxc_nfc_21()) { this->ecc.mode = NAND_ECC_HW_SYNDROME; this->ecc.read_page = mxc_nand_read_page_syndrome; this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; @@ -1383,27 +1219,46 @@ int board_nand_init(struct nand_chip *this) host->pagesize_2k = 0; this->ecc.size = 512; - tmp = readw(&host->regs->nfc_config1); - tmp |= NFC_ECC_EN; - writew(tmp, &host->regs->nfc_config1); + _mxc_nand_enable_hwecc(mtd, 1); #else this->ecc.layout = &nand_soft_eccoob; this->ecc.mode = NAND_ECC_SOFT; - tmp = readw(&host->regs->nfc_config1); - tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->nfc_config1); + _mxc_nand_enable_hwecc(mtd, 0); #endif /* Reset NAND */ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + /* NAND bus width determines access functions used by upper layer */ + if (is_16bit_nand()) + this->options |= NAND_BUSWIDTH_16; + +#ifdef CONFIG_SYS_NAND_LARGEPAGE + host->pagesize_2k = 1; + this->ecc.layout = &nand_hw_eccoob2k; +#else + host->pagesize_2k = 0; + this->ecc.layout = &nand_hw_eccoob; +#endif + +#ifdef MXC_NFC_V2_1 + tmp = readw(&host->regs->config1); + tmp |= NFC_ONE_CYCLE; + tmp |= NFC_4_8N_ECC; + writew(tmp, &host->regs->config1); + if (host->pagesize_2k) + writew(64/2, &host->regs->spare_area_size); + else + writew(16/2, &host->regs->spare_area_size); +#endif + /* * preset operation * Unlock the internal RAM Buffer */ - writew(0x2, &host->regs->nfc_config); + writew(0x2, &host->regs->config); /* Blocks to be unlocked */ - writew(0x0, &host->regs->nfc_unlockstart_blkaddr); + writew(0x0, &host->regs->unlockstart_blkaddr); /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the * unlockend_blkaddr, but the magic 0x4000 does not always work * when writing more than some 32 megabytes (on 2k page nands) @@ -1415,22 +1270,10 @@ int board_nand_init(struct nand_chip *this) * This might be NAND chip specific and the i.MX31 datasheet is * extremely vague about the semantics of this register. */ - writew(0xFFFF, &host->regs->nfc_unlockend_blkaddr); + writew(0xFFFF, &host->regs->unlockend_blkaddr); /* Unlock Block Command for given address range */ - writew(0x4, &host->regs->nfc_wrprot); + writew(0x4, &host->regs->wrprot); - /* NAND bus width determines access functions used by upper layer */ - if (is_16bit_nand()) - this->options |= NAND_BUSWIDTH_16; - -#ifdef CONFIG_SYS_NAND_LARGEPAGE - host->pagesize_2k = 1; - this->ecc.layout = &nand_hw_eccoob2k; -#else - host->pagesize_2k = 0; - this->ecc.layout = &nand_hw_eccoob; -#endif - mxc_setup_config1(); - return err; + return 0; } diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index bf9414fef1e..4701be846c6 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -25,10 +25,10 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ +#include <common.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/types.h> -#include <common.h> #include <malloc.h> #include <asm/errno.h> #include <asm/io.h> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index bfd668fa0ac..71f5027889f 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2573,14 +2573,13 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, mtd->writesize = le32_to_cpu(p->byte_per_page); mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); - chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize; + chip->chipsize = le32_to_cpu(p->blocks_per_lun); + chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; *busw = 0; if (le16_to_cpu(p->features) & 1) *busw = NAND_BUSWIDTH_16; - chip->options &= ~NAND_CHIPOPTIONS_MSK; - chip->options |= (NAND_NO_READRDY | - NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK; + chip->options |= NAND_NO_READRDY | NAND_NO_AUTOINCR; return 1; } @@ -2752,8 +2751,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } } /* Get chip options, preserve non chip based options */ - chip->options &= ~NAND_CHIPOPTIONS_MSK; - chip->options |= type->options & NAND_CHIPOPTIONS_MSK; + chip->options |= type->options; /* Check if chip is a not a samsung device. Do not clear the * options for chips which are not having an extended id. @@ -2936,7 +2934,8 @@ int nand_scan_tail(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_OWN_BUFFERS)) - chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); + chip->buffers = memalign(ARCH_DMA_MINALIGN, + sizeof(*chip->buffers)); if (!chip->buffers) return -ENOMEM; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 7ed8b1891ce..c4752a7cbf8 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -207,12 +207,6 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) * Support for locking / unlocking operations of some NAND devices *****************************************************************************/ -#define NAND_CMD_LOCK 0x2a -#define NAND_CMD_LOCK_TIGHT 0x2c -#define NAND_CMD_UNLOCK1 0x23 -#define NAND_CMD_UNLOCK2 0x24 -#define NAND_CMD_LOCK_STATUS 0x7a - /** * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT * state @@ -271,7 +265,6 @@ int nand_lock(struct mtd_info *mtd, int tight) * >0 lock status: * bitfield with the following combinations: * NAND_LOCK_STATUS_TIGHT: page in tight state - * NAND_LOCK_STATUS_LOCK: page locked * NAND_LOCK_STATUS_UNLOCK: page unlocked * */ @@ -300,7 +293,6 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset) chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask); ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT - | NAND_LOCK_STATUS_LOCK | NAND_LOCK_STATUS_UNLOCK); out: @@ -317,18 +309,21 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset) * @param start start byte address * @param length number of bytes to unlock (must be a multiple of * page size nand->writesize) + * @param allexcept if set, unlock everything not selected * * @return 0 on success, -1 in case of error */ -int nand_unlock(struct mtd_info *mtd, ulong start, ulong length) +int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, + int allexcept) { int ret = 0; int chipnr; int status; int page; struct nand_chip *chip = mtd->priv; - printf ("nand_unlock: start: %08x, length: %d!\n", - (int)start, (int)length); + + debug("nand_unlock%s: start: %08llx, length: %d!\n", + allexcept ? " (allexcept)" : "", start, length); /* select the NAND device */ chipnr = (int)(start >> chip->chip_shift); @@ -368,6 +363,15 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length) /* submit ADDRESS of LAST page to unlock */ page += (int)(length >> chip->page_shift); + + /* + * Page addresses for unlocking are supposed to be block-aligned. + * At least some NAND chips use the low bit to indicate that the + * page range should be inverted. + */ + if (allexcept) + page |= 1; + chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask); /* call wait ready function */ diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c new file mode 100644 index 00000000000..8c1de34455e --- /dev/null +++ b/drivers/mtd/nand/tegra_nand.c @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/gpio.h> +#include <asm/errno.h> +#include <asm-generic/gpio.h> +#include <fdtdec.h> +#include "tegra_nand.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define NAND_CMD_TIMEOUT_MS 10 + +#define SKIPPED_SPARE_BYTES 4 + +/* ECC bytes to be generated for tag data */ +#define TAG_ECC_BYTES 4 + +/* 64 byte oob block info for large page (== 2KB) device + * + * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC: + * Skipped bytes(4) + * Main area Ecc(36) + * Tag data(20) + * Tag data Ecc(4) + * + * Yaffs2 will use 16 tag bytes. + */ +static struct nand_ecclayout eccoob = { + .eccbytes = 36, + .eccpos = { + 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 33, 34, 35, 36, 37, 38, 39, + }, + .oobavail = 20, + .oobfree = { + { + .offset = 40, + .length = 20, + }, + } +}; + +enum { + ECC_OK, + ECC_TAG_ERROR = 1 << 0, + ECC_DATA_ERROR = 1 << 1 +}; + +/* Timing parameters */ +enum { + FDT_NAND_MAX_TRP_TREA, + FDT_NAND_TWB, + FDT_NAND_MAX_TCR_TAR_TRR, + FDT_NAND_TWHR, + FDT_NAND_MAX_TCS_TCH_TALS_TALH, + FDT_NAND_TWH, + FDT_NAND_TWP, + FDT_NAND_TRH, + FDT_NAND_TADL, + + FDT_NAND_TIMING_COUNT +}; + +/* Information about an attached NAND chip */ +struct fdt_nand { + struct nand_ctlr *reg; + int enabled; /* 1 to enable, 0 to disable */ + struct fdt_gpio_state wp_gpio; /* write-protect GPIO */ + s32 width; /* bit width, normally 8 */ + u32 timing[FDT_NAND_TIMING_COUNT]; +}; + +struct nand_drv { + struct nand_ctlr *reg; + + /* + * When running in PIO mode to get READ ID bytes from register + * RESP_0, we need this variable as an index to know which byte in + * register RESP_0 should be read. + * Because common code in nand_base.c invokes read_byte function two + * times for NAND_CMD_READID. + * And our controller returns 4 bytes at once in register RESP_0. + */ + int pio_byte_index; + struct fdt_nand config; +}; + +static struct nand_drv nand_ctrl; +static struct mtd_info *our_mtd; +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +#ifdef CONFIG_SYS_DCACHE_OFF +static inline void dma_prepare(void *start, unsigned long length, + int is_writing) +{ +} +#else +/** + * Prepare for a DMA transaction + * + * For a write we flush out our data. For a read we invalidate, since we + * need to do this before we read from the buffer after the DMA has + * completed, so may as well do it now. + * + * @param start Start address for DMA buffer (should be cache-aligned) + * @param length Length of DMA buffer in bytes + * @param is_writing 0 if reading, non-zero if writing + */ +static void dma_prepare(void *start, unsigned long length, int is_writing) +{ + unsigned long addr = (unsigned long)start; + + length = ALIGN(length, ARCH_DMA_MINALIGN); + if (is_writing) + flush_dcache_range(addr, addr + length); + else + invalidate_dcache_range(addr, addr + length); +} +#endif + +/** + * Wait for command completion + * + * @param reg nand_ctlr structure + * @return + * 1 - Command completed + * 0 - Timeout + */ +static int nand_waitfor_cmd_completion(struct nand_ctlr *reg) +{ + u32 reg_val; + int running; + int i; + + for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) { + if ((readl(®->command) & CMD_GO) || + !(readl(®->status) & STATUS_RBSY0) || + !(readl(®->isr) & ISR_IS_CMD_DONE)) { + udelay(1); + continue; + } + reg_val = readl(®->dma_mst_ctrl); + /* + * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE + * is set, that means DMA engine is running. + * + * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE + * is cleared, indicating DMA transfer completion. + */ + running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE | + DMA_MST_CTRL_EN_B_ENABLE); + if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE)) + return 1; + udelay(1); + } + return 0; +} + +/** + * Read one byte from the chip + * + * @param mtd MTD device structure + * @return data byte + * + * Read function for 8bit bus-width + */ +static uint8_t read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + u32 dword_read; + struct nand_drv *info; + + info = (struct nand_drv *)chip->priv; + + /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */ + if (info->pio_byte_index > 3) { + info->pio_byte_index = 0; + writel(CMD_GO | CMD_PIO + | CMD_RX | CMD_CE0, + &info->reg->command); + if (!nand_waitfor_cmd_completion(info->reg)) + printf("Command timeout\n"); + } + + dword_read = readl(&info->reg->resp); + dword_read = dword_read >> (8 * info->pio_byte_index); + info->pio_byte_index++; + return (uint8_t)dword_read; +} + +/** + * Check NAND status to see if it is ready or not + * + * @param mtd MTD device structure + * @return + * 1 - ready + * 0 - not ready + */ +static int nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + int reg_val; + struct nand_drv *info; + + info = (struct nand_drv *)chip->priv; + + reg_val = readl(&info->reg->status); + if (reg_val & STATUS_RBSY0) + return 1; + else + return 0; +} + +/* Dummy implementation: we don't support multiple chips */ +static void nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + switch (chipnr) { + case -1: + case 0: + break; + + default: + BUG(); + } +} + +/** + * Clear all interrupt status bits + * + * @param reg nand_ctlr structure + */ +static void nand_clear_interrupt_status(struct nand_ctlr *reg) +{ + u32 reg_val; + + /* Clear interrupt status */ + reg_val = readl(®->isr); + writel(reg_val, ®->isr); +} + +/** + * Send command to NAND device + * + * @param mtd MTD device structure + * @param command the command to be sent + * @param column the column address for this command, -1 if none + * @param page_addr the page address for this command, -1 if none + */ +static void nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct nand_drv *info; + + info = (struct nand_drv *)chip->priv; + + /* + * Write out the command to the device. + * + * Only command NAND_CMD_RESET or NAND_CMD_READID will come + * here before mtd->writesize is initialized. + */ + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + assert(mtd->writesize != 0); + column += mtd->writesize; + command = NAND_CMD_READ0; + } + + /* Adjust columns for 16 bit bus-width */ + if (column != -1 && (chip->options & NAND_BUSWIDTH_16)) + column >>= 1; + + nand_clear_interrupt_status(info->reg); + + /* Stop DMA engine, clear DMA completion status */ + writel(DMA_MST_CTRL_EN_A_DISABLE + | DMA_MST_CTRL_EN_B_DISABLE + | DMA_MST_CTRL_IS_DMA_DONE, + &info->reg->dma_mst_ctrl); + + /* + * Program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + case NAND_CMD_READID: + writel(NAND_CMD_READID, &info->reg->cmd_reg1); + writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO + | CMD_RX | + ((4 - 1) << CMD_TRANS_SIZE_SHIFT) + | CMD_CE0, + &info->reg->command); + info->pio_byte_index = 0; + break; + case NAND_CMD_READ0: + writel(NAND_CMD_READ0, &info->reg->cmd_reg1); + writel(NAND_CMD_READSTART, &info->reg->cmd_reg2); + writel((page_addr << 16) | (column & 0xFFFF), + &info->reg->addr_reg1); + writel(page_addr >> 16, &info->reg->addr_reg2); + return; + case NAND_CMD_SEQIN: + writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1); + writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2); + writel((page_addr << 16) | (column & 0xFFFF), + &info->reg->addr_reg1); + writel(page_addr >> 16, + &info->reg->addr_reg2); + return; + case NAND_CMD_PAGEPROG: + return; + case NAND_CMD_ERASE1: + writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1); + writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2); + writel(page_addr, &info->reg->addr_reg1); + writel(CMD_GO | CMD_CLE | CMD_ALE | + CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3, + &info->reg->command); + break; + case NAND_CMD_ERASE2: + return; + case NAND_CMD_STATUS: + writel(NAND_CMD_STATUS, &info->reg->cmd_reg1); + writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX + | ((1 - 0) << CMD_TRANS_SIZE_SHIFT) + | CMD_CE0, + &info->reg->command); + info->pio_byte_index = 0; + break; + case NAND_CMD_RESET: + writel(NAND_CMD_RESET, &info->reg->cmd_reg1); + writel(CMD_GO | CMD_CLE | CMD_CE0, + &info->reg->command); + break; + case NAND_CMD_RNDOUT: + default: + printf("%s: Unsupported command %d\n", __func__, command); + return; + } + if (!nand_waitfor_cmd_completion(info->reg)) + printf("Command 0x%02X timeout\n", command); +} + +/** + * Check whether the pointed buffer are all 0xff (blank). + * + * @param buf data buffer for blank check + * @param len length of the buffer in byte + * @return + * 1 - blank + * 0 - non-blank + */ +static int blank_check(u8 *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (buf[i] != 0xFF) + return 0; + return 1; +} + +/** + * After a DMA transfer for read, we call this function to see whether there + * is any uncorrectable error on the pointed data buffer or oob buffer. + * + * @param reg nand_ctlr structure + * @param databuf data buffer + * @param a_len data buffer length + * @param oobbuf oob buffer + * @param b_len oob buffer length + * @return + * ECC_OK - no ECC error or correctable ECC error + * ECC_TAG_ERROR - uncorrectable tag ECC error + * ECC_DATA_ERROR - uncorrectable data ECC error + * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error + */ +static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf, + int a_len, u8 *oobbuf, int b_len) +{ + int return_val = ECC_OK; + u32 reg_val; + + if (!(readl(®->isr) & ISR_IS_ECC_ERR)) + return ECC_OK; + + /* + * Area A is used for the data block (databuf). Area B is used for + * the spare block (oobbuf) + */ + reg_val = readl(®->dec_status); + if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) { + reg_val = readl(®->bch_dec_status_buf); + /* + * If uncorrectable error occurs on data area, then see whether + * they are all FF. If all are FF, it's a blank page. + * Not error. + */ + if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) && + !blank_check(databuf, a_len)) + return_val |= ECC_DATA_ERROR; + } + + if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) { + reg_val = readl(®->bch_dec_status_buf); + /* + * If uncorrectable error occurs on tag area, then see whether + * they are all FF. If all are FF, it's a blank page. + * Not error. + */ + if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) && + !blank_check(oobbuf, b_len)) + return_val |= ECC_TAG_ERROR; + } + + return return_val; +} + +/** + * Set GO bit to send command to device + * + * @param reg nand_ctlr structure + */ +static void start_command(struct nand_ctlr *reg) +{ + u32 reg_val; + + reg_val = readl(®->command); + reg_val |= CMD_GO; + writel(reg_val, ®->command); +} + +/** + * Clear command GO bit, DMA GO bit, and DMA completion status + * + * @param reg nand_ctlr structure + */ +static void stop_command(struct nand_ctlr *reg) +{ + /* Stop command */ + writel(0, ®->command); + + /* Stop DMA engine and clear DMA completion status */ + writel(DMA_MST_CTRL_GO_DISABLE + | DMA_MST_CTRL_IS_DMA_DONE, + ®->dma_mst_ctrl); +} + +/** + * Set up NAND bus width and page size + * + * @param info nand_info structure + * @param *reg_val address of reg_val + * @return 0 if ok, -1 on error + */ +static int set_bus_width_page_size(struct fdt_nand *config, + u32 *reg_val) +{ + if (config->width == 8) + *reg_val = CFG_BUS_WIDTH_8BIT; + else if (config->width == 16) + *reg_val = CFG_BUS_WIDTH_16BIT; + else { + debug("%s: Unsupported bus width %d\n", __func__, + config->width); + return -1; + } + + if (our_mtd->writesize == 512) + *reg_val |= CFG_PAGE_SIZE_512; + else if (our_mtd->writesize == 2048) + *reg_val |= CFG_PAGE_SIZE_2048; + else if (our_mtd->writesize == 4096) + *reg_val |= CFG_PAGE_SIZE_4096; + else { + debug("%s: Unsupported page size %d\n", __func__, + our_mtd->writesize); + return -1; + } + + return 0; +} + +/** + * Page read/write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + * @param page page number + * @param with_ecc 1 to enable ECC, 0 to disable ECC + * @param is_writing 0 for read, 1 for write + * @return 0 when successfully completed + * -EIO when command timeout + */ +static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page, int with_ecc, int is_writing) +{ + u32 reg_val; + int tag_size; + struct nand_oobfree *free = chip->ecc.layout->oobfree; + /* 4*128=512 (byte) is the value that our HW can support. */ + ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128); + char *tag_ptr; + struct nand_drv *info; + struct fdt_nand *config; + + if ((uintptr_t)buf & 0x03) { + printf("buf %p has to be 4-byte aligned\n", buf); + return -EINVAL; + } + + info = (struct nand_drv *)chip->priv; + config = &info->config; + if (set_bus_width_page_size(config, ®_val)) + return -EINVAL; + + /* Need to be 4-byte aligned */ + tag_ptr = (char *)tag_buf; + + stop_command(info->reg); + + writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a); + writel(virt_to_phys(buf), &info->reg->data_block_ptr); + + if (with_ecc) { + writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr); + if (is_writing) + memcpy(tag_ptr, chip->oob_poi + free->offset, + chip->ecc.layout->oobavail + + TAG_ECC_BYTES); + } else { + writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr); + } + + /* Set ECC selection, configure ECC settings */ + if (with_ecc) { + tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES; + reg_val |= (CFG_SKIP_SPARE_SEL_4 + | CFG_SKIP_SPARE_ENABLE + | CFG_HW_ECC_CORRECTION_ENABLE + | CFG_ECC_EN_TAG_DISABLE + | CFG_HW_ECC_SEL_RS + | CFG_HW_ECC_ENABLE + | CFG_TVAL4 + | (tag_size - 1)); + + if (!is_writing) + tag_size += SKIPPED_SPARE_BYTES; + dma_prepare(tag_ptr, tag_size, is_writing); + } else { + tag_size = mtd->oobsize; + reg_val |= (CFG_SKIP_SPARE_DISABLE + | CFG_HW_ECC_CORRECTION_DISABLE + | CFG_ECC_EN_TAG_DISABLE + | CFG_HW_ECC_DISABLE + | (tag_size - 1)); + dma_prepare(chip->oob_poi, tag_size, is_writing); + } + writel(reg_val, &info->reg->config); + + dma_prepare(buf, 1 << chip->page_shift, is_writing); + + writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); + + writel(tag_size - 1, &info->reg->dma_cfg_b); + + nand_clear_interrupt_status(info->reg); + + reg_val = CMD_CLE | CMD_ALE + | CMD_SEC_CMD + | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) + | CMD_A_VALID + | CMD_B_VALID + | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT) + | CMD_CE0; + if (!is_writing) + reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); + else + reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); + writel(reg_val, &info->reg->command); + + /* Setup DMA engine */ + reg_val = DMA_MST_CTRL_GO_ENABLE + | DMA_MST_CTRL_BURST_8WORDS + | DMA_MST_CTRL_EN_A_ENABLE + | DMA_MST_CTRL_EN_B_ENABLE; + + if (!is_writing) + reg_val |= DMA_MST_CTRL_DIR_READ; + else + reg_val |= DMA_MST_CTRL_DIR_WRITE; + + writel(reg_val, &info->reg->dma_mst_ctrl); + + start_command(info->reg); + + if (!nand_waitfor_cmd_completion(info->reg)) { + if (!is_writing) + printf("Read Page 0x%X timeout ", page); + else + printf("Write Page 0x%X timeout ", page); + if (with_ecc) + printf("with ECC"); + else + printf("without ECC"); + printf("\n"); + return -EIO; + } + + if (with_ecc && !is_writing) { + memcpy(chip->oob_poi, tag_ptr, + SKIPPED_SPARE_BYTES); + memcpy(chip->oob_poi + free->offset, + tag_ptr + SKIPPED_SPARE_BYTES, + chip->ecc.layout->oobavail); + reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf, + 1 << chip->page_shift, + (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES), + chip->ecc.layout->oobavail); + if (reg_val & ECC_TAG_ERROR) + printf("Read Page 0x%X tag ECC error\n", page); + if (reg_val & ECC_DATA_ERROR) + printf("Read Page 0x%X data ECC error\n", + page); + if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR)) + return -EIO; + } + return 0; +} + +/** + * Hardware ecc based page read function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf buffer to store read data + * @param page page number to read + * @return 0 when successfully completed + * -EIO when command timeout + */ +static int nand_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int page) +{ + return nand_rw_page(mtd, chip, buf, page, 1, 0); +} + +/** + * Hardware ecc based page write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + */ +static void nand_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + int page; + struct nand_drv *info; + + info = (struct nand_drv *)chip->priv; + + page = (readl(&info->reg->addr_reg1) >> 16) | + (readl(&info->reg->addr_reg2) << 16); + + nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1); +} + + +/** + * Read raw page data without ecc + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf buffer to store read data + * @param page page number to read + * @return 0 when successfully completed + * -EINVAL when chip->oob_poi is not double-word aligned + * -EIO when command timeout + */ +static int nand_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int page) +{ + return nand_rw_page(mtd, chip, buf, page, 0, 0); +} + +/** + * Raw page write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param buf data buffer + */ +static void nand_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + int page; + struct nand_drv *info; + + info = (struct nand_drv *)chip->priv; + page = (readl(&info->reg->addr_reg1) >> 16) | + (readl(&info->reg->addr_reg2) << 16); + + nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1); +} + +/** + * OOB data read/write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to read + * @param with_ecc 1 to enable ECC, 0 to disable ECC + * @param is_writing 0 for read, 1 for write + * @return 0 when successfully completed + * -EINVAL when chip->oob_poi is not double-word aligned + * -EIO when command timeout + */ +static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int with_ecc, int is_writing) +{ + u32 reg_val; + int tag_size; + struct nand_oobfree *free = chip->ecc.layout->oobfree; + struct nand_drv *info; + + if (((int)chip->oob_poi) & 0x03) + return -EINVAL; + info = (struct nand_drv *)chip->priv; + if (set_bus_width_page_size(&info->config, ®_val)) + return -EINVAL; + + stop_command(info->reg); + + writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr); + + /* Set ECC selection */ + tag_size = mtd->oobsize; + if (with_ecc) + reg_val |= CFG_ECC_EN_TAG_ENABLE; + else + reg_val |= (CFG_ECC_EN_TAG_DISABLE); + + reg_val |= ((tag_size - 1) | + CFG_SKIP_SPARE_DISABLE | + CFG_HW_ECC_CORRECTION_DISABLE | + CFG_HW_ECC_DISABLE); + writel(reg_val, &info->reg->config); + + dma_prepare(chip->oob_poi, tag_size, is_writing); + + writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config); + + if (is_writing && with_ecc) + tag_size -= TAG_ECC_BYTES; + + writel(tag_size - 1, &info->reg->dma_cfg_b); + + nand_clear_interrupt_status(info->reg); + + reg_val = CMD_CLE | CMD_ALE + | CMD_SEC_CMD + | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT) + | CMD_B_VALID + | CMD_CE0; + if (!is_writing) + reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX); + else + reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX); + writel(reg_val, &info->reg->command); + + /* Setup DMA engine */ + reg_val = DMA_MST_CTRL_GO_ENABLE + | DMA_MST_CTRL_BURST_8WORDS + | DMA_MST_CTRL_EN_B_ENABLE; + if (!is_writing) + reg_val |= DMA_MST_CTRL_DIR_READ; + else + reg_val |= DMA_MST_CTRL_DIR_WRITE; + + writel(reg_val, &info->reg->dma_mst_ctrl); + + start_command(info->reg); + + if (!nand_waitfor_cmd_completion(info->reg)) { + if (!is_writing) + printf("Read OOB of Page 0x%X timeout\n", page); + else + printf("Write OOB of Page 0x%X timeout\n", page); + return -EIO; + } + + if (with_ecc && !is_writing) { + reg_val = (u32)check_ecc_error(info->reg, 0, 0, + (u8 *)(chip->oob_poi + free->offset), + chip->ecc.layout->oobavail); + if (reg_val & ECC_TAG_ERROR) + printf("Read OOB of Page 0x%X tag ECC error\n", page); + } + return 0; +} + +/** + * OOB data read function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to read + * @param sndcmd flag whether to issue read command or not + * @return 1 - issue read command next time + * 0 - not to issue + */ +static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + if (sndcmd) { + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + sndcmd = 0; + } + nand_rw_oob(mtd, chip, page, 0, 0); + return sndcmd; +} + +/** + * OOB data write function + * + * @param mtd mtd info structure + * @param chip nand chip info structure + * @param page page number to write + * @return 0 when successfully completed + * -EINVAL when chip->oob_poi is not double-word aligned + * -EIO when command timeout + */ +static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); + + return nand_rw_oob(mtd, chip, page, 0, 1); +} + +/** + * Set up NAND memory timings according to the provided parameters + * + * @param timing Timing parameters + * @param reg NAND controller register address + */ +static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT], + struct nand_ctlr *reg) +{ + u32 reg_val, clk_rate, clk_period, time_val; + + clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH, + CLOCK_ID_PERIPH) / 1000000; + clk_period = 1000 / clk_rate; + reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << + TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK; + reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << + TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK; + time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; + if (time_val > 2) + reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) & + TIMING_TCR_TAR_TRR_CNT_MASK; + reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << + TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK; + time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period; + if (time_val > 1) + reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) & + TIMING_TCS_CNT_MASK; + reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << + TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK; + reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << + TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK; + reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << + TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK; + reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << + TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK; + writel(reg_val, ®->timing); + + reg_val = 0; + time_val = timing[FDT_NAND_TADL] / clk_period; + if (time_val > 2) + reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK; + writel(reg_val, ®->timing2); +} + +/** + * Decode NAND parameters from the device tree + * + * @param blob Device tree blob + * @param node Node containing "nand-flash" compatble node + * @return 0 if ok, -ve on error (FDT_ERR_...) + */ +static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) +{ + int err; + + config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg"); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8); + err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios", + &config->wp_gpio); + if (err) + return err; + err = fdtdec_get_int_array(blob, node, "nvidia,timing", + config->timing, FDT_NAND_TIMING_COUNT); + if (err < 0) + return err; + + /* Now look up the controller and decode that */ + node = fdt_next_node(blob, node, NULL); + if (node < 0) + return node; + + return 0; +} + +/** + * Board-specific NAND initialization + * + * @param nand nand chip info structure + * @return 0, after initialized, -1 on error + */ +int tegra_nand_init(struct nand_chip *nand, int devnum) +{ + struct nand_drv *info = &nand_ctrl; + struct fdt_nand *config = &info->config; + int node, ret; + + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_NVIDIA_TEGRA20_NAND); + if (node < 0) + return -1; + if (fdt_decode_nand(gd->fdt_blob, node, config)) { + printf("Could not decode nand-flash in device tree\n"); + return -1; + } + if (!config->enabled) + return -1; + info->reg = config->reg; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &eccoob; + + nand->options = LP_OPTIONS; + nand->cmdfunc = nand_command; + nand->read_byte = read_byte; + nand->ecc.read_page = nand_read_page_hwecc; + nand->ecc.write_page = nand_write_page_hwecc; + nand->ecc.read_page_raw = nand_read_page_raw; + nand->ecc.write_page_raw = nand_write_page_raw; + nand->ecc.read_oob = nand_read_oob; + nand->ecc.write_oob = nand_write_oob; + nand->select_chip = nand_select_chip; + nand->dev_ready = nand_dev_ready; + nand->priv = &nand_ctrl; + + /* Adjust controller clock rate */ + clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000); + + /* Adjust timing for NAND device */ + setup_timing(config->timing, info->reg); + + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); + fdtdec_setup_gpio(&config->wp_gpio); + gpio_direction_output(config->wp_gpio.gpio, 1); + + our_mtd = &nand_info[devnum]; + our_mtd->priv = nand; + ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); + if (ret) + return ret; + + nand->ecc.size = our_mtd->writesize; + nand->ecc.bytes = our_mtd->oobsize; + + ret = nand_scan_tail(our_mtd); + if (ret) + return ret; + + ret = nand_register(devnum); + if (ret) + return ret; + + return 0; +} + +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (tegra_nand_init(nand, 0)) + puts("Tegra NAND init failed\n"); +} diff --git a/drivers/mtd/nand/tegra_nand.h b/drivers/mtd/nand/tegra_nand.h new file mode 100644 index 00000000000..7e74be75f81 --- /dev/null +++ b/drivers/mtd/nand/tegra_nand.h @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* register offset */ +#define COMMAND_0 0x00 +#define CMD_GO (1 << 31) +#define CMD_CLE (1 << 30) +#define CMD_ALE (1 << 29) +#define CMD_PIO (1 << 28) +#define CMD_TX (1 << 27) +#define CMD_RX (1 << 26) +#define CMD_SEC_CMD (1 << 25) +#define CMD_AFT_DAT_MASK (1 << 24) +#define CMD_AFT_DAT_DISABLE 0 +#define CMD_AFT_DAT_ENABLE (1 << 24) +#define CMD_TRANS_SIZE_SHIFT 20 +#define CMD_TRANS_SIZE_PAGE 8 +#define CMD_A_VALID (1 << 19) +#define CMD_B_VALID (1 << 18) +#define CMD_RD_STATUS_CHK (1 << 17) +#define CMD_R_BSY_CHK (1 << 16) +#define CMD_CE7 (1 << 15) +#define CMD_CE6 (1 << 14) +#define CMD_CE5 (1 << 13) +#define CMD_CE4 (1 << 12) +#define CMD_CE3 (1 << 11) +#define CMD_CE2 (1 << 10) +#define CMD_CE1 (1 << 9) +#define CMD_CE0 (1 << 8) +#define CMD_CLE_BYTE_SIZE_SHIFT 4 +enum { + CMD_CLE_BYTES1 = 0, + CMD_CLE_BYTES2, + CMD_CLE_BYTES3, + CMD_CLE_BYTES4, +}; +#define CMD_ALE_BYTE_SIZE_SHIFT 0 +enum { + CMD_ALE_BYTES1 = 0, + CMD_ALE_BYTES2, + CMD_ALE_BYTES3, + CMD_ALE_BYTES4, + CMD_ALE_BYTES5, + CMD_ALE_BYTES6, + CMD_ALE_BYTES7, + CMD_ALE_BYTES8 +}; + +#define STATUS_0 0x04 +#define STATUS_RBSY0 (1 << 8) + +#define ISR_0 0x08 +#define ISR_IS_CMD_DONE (1 << 5) +#define ISR_IS_ECC_ERR (1 << 4) + +#define IER_0 0x0C + +#define CFG_0 0x10 +#define CFG_HW_ECC_MASK (1 << 31) +#define CFG_HW_ECC_DISABLE 0 +#define CFG_HW_ECC_ENABLE (1 << 31) +#define CFG_HW_ECC_SEL_MASK (1 << 30) +#define CFG_HW_ECC_SEL_HAMMING 0 +#define CFG_HW_ECC_SEL_RS (1 << 30) +#define CFG_HW_ECC_CORRECTION_MASK (1 << 29) +#define CFG_HW_ECC_CORRECTION_DISABLE 0 +#define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29) +#define CFG_PIPELINE_EN_MASK (1 << 28) +#define CFG_PIPELINE_EN_DISABLE 0 +#define CFG_PIPELINE_EN_ENABLE (1 << 28) +#define CFG_ECC_EN_TAG_MASK (1 << 27) +#define CFG_ECC_EN_TAG_DISABLE 0 +#define CFG_ECC_EN_TAG_ENABLE (1 << 27) +#define CFG_TVALUE_MASK (3 << 24) +enum { + CFG_TVAL4 = 0 << 24, + CFG_TVAL6 = 1 << 24, + CFG_TVAL8 = 2 << 24 +}; +#define CFG_SKIP_SPARE_MASK (1 << 23) +#define CFG_SKIP_SPARE_DISABLE 0 +#define CFG_SKIP_SPARE_ENABLE (1 << 23) +#define CFG_COM_BSY_MASK (1 << 22) +#define CFG_COM_BSY_DISABLE 0 +#define CFG_COM_BSY_ENABLE (1 << 22) +#define CFG_BUS_WIDTH_MASK (1 << 21) +#define CFG_BUS_WIDTH_8BIT 0 +#define CFG_BUS_WIDTH_16BIT (1 << 21) +#define CFG_LPDDR1_MODE_MASK (1 << 20) +#define CFG_LPDDR1_MODE_DISABLE 0 +#define CFG_LPDDR1_MODE_ENABLE (1 << 20) +#define CFG_EDO_MODE_MASK (1 << 19) +#define CFG_EDO_MODE_DISABLE 0 +#define CFG_EDO_MODE_ENABLE (1 << 19) +#define CFG_PAGE_SIZE_SEL_MASK (7 << 16) +enum { + CFG_PAGE_SIZE_256 = 0 << 16, + CFG_PAGE_SIZE_512 = 1 << 16, + CFG_PAGE_SIZE_1024 = 2 << 16, + CFG_PAGE_SIZE_2048 = 3 << 16, + CFG_PAGE_SIZE_4096 = 4 << 16 +}; +#define CFG_SKIP_SPARE_SEL_MASK (3 << 14) +enum { + CFG_SKIP_SPARE_SEL_4 = 0 << 14, + CFG_SKIP_SPARE_SEL_8 = 1 << 14, + CFG_SKIP_SPARE_SEL_12 = 2 << 14, + CFG_SKIP_SPARE_SEL_16 = 3 << 14 +}; +#define CFG_TAG_BYTE_SIZE_MASK 0x1FF + +#define TIMING_0 0x14 +#define TIMING_TRP_RESP_CNT_SHIFT 28 +#define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT) +#define TIMING_TWB_CNT_SHIFT 24 +#define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT) +#define TIMING_TCR_TAR_TRR_CNT_SHIFT 20 +#define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT) +#define TIMING_TWHR_CNT_SHIFT 16 +#define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT) +#define TIMING_TCS_CNT_SHIFT 14 +#define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT) +#define TIMING_TWH_CNT_SHIFT 12 +#define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT) +#define TIMING_TWP_CNT_SHIFT 8 +#define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT) +#define TIMING_TRH_CNT_SHIFT 4 +#define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT) +#define TIMING_TRP_CNT_SHIFT 0 +#define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT) + +#define RESP_0 0x18 + +#define TIMING2_0 0x1C +#define TIMING2_TADL_CNT_SHIFT 0 +#define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT) + +#define CMD_REG1_0 0x20 +#define CMD_REG2_0 0x24 +#define ADDR_REG1_0 0x28 +#define ADDR_REG2_0 0x2C + +#define DMA_MST_CTRL_0 0x30 +#define DMA_MST_CTRL_GO_MASK (1 << 31) +#define DMA_MST_CTRL_GO_DISABLE 0 +#define DMA_MST_CTRL_GO_ENABLE (1 << 31) +#define DMA_MST_CTRL_DIR_MASK (1 << 30) +#define DMA_MST_CTRL_DIR_READ 0 +#define DMA_MST_CTRL_DIR_WRITE (1 << 30) +#define DMA_MST_CTRL_PERF_EN_MASK (1 << 29) +#define DMA_MST_CTRL_PERF_EN_DISABLE 0 +#define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29) +#define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27) +#define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0 +#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27) +#define DMA_MST_CTRL_BURST_SIZE_SHIFT 24 +#define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT) +enum { + DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT, + DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT, + DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT, + DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT +}; +#define DMA_MST_CTRL_IS_DMA_DONE (1 << 20) +#define DMA_MST_CTRL_EN_A_MASK (1 << 2) +#define DMA_MST_CTRL_EN_A_DISABLE 0 +#define DMA_MST_CTRL_EN_A_ENABLE (1 << 2) +#define DMA_MST_CTRL_EN_B_MASK (1 << 1) +#define DMA_MST_CTRL_EN_B_DISABLE 0 +#define DMA_MST_CTRL_EN_B_ENABLE (1 << 1) + +#define DMA_CFG_A_0 0x34 +#define DMA_CFG_B_0 0x38 +#define FIFO_CTRL_0 0x3C +#define DATA_BLOCK_PTR_0 0x40 +#define TAG_PTR_0 0x44 +#define ECC_PTR_0 0x48 + +#define DEC_STATUS_0 0x4C +#define DEC_STATUS_A_ECC_FAIL (1 << 1) +#define DEC_STATUS_B_ECC_FAIL (1 << 0) + +#define BCH_CONFIG_0 0xCC +#define BCH_CONFIG_BCH_TVALUE_SHIFT 4 +#define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT) +enum { + BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT, + BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT, + BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT, + BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT +}; +#define BCH_CONFIG_BCH_ECC_MASK (1 << 0) +#define BCH_CONFIG_BCH_ECC_DISABLE 0 +#define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0) + +#define BCH_DEC_RESULT_0 0xD0 +#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8) +#define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF + +#define BCH_DEC_STATUS_BUF_0 0xD4 +#define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000 +#define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000 +#define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14) +#define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13) +#define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8) +#define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF + +#define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR) + +struct nand_ctlr { + u32 command; /* offset 00h */ + u32 status; /* offset 04h */ + u32 isr; /* offset 08h */ + u32 ier; /* offset 0Ch */ + u32 config; /* offset 10h */ + u32 timing; /* offset 14h */ + u32 resp; /* offset 18h */ + u32 timing2; /* offset 1Ch */ + u32 cmd_reg1; /* offset 20h */ + u32 cmd_reg2; /* offset 24h */ + u32 addr_reg1; /* offset 28h */ + u32 addr_reg2; /* offset 2Ch */ + u32 dma_mst_ctrl; /* offset 30h */ + u32 dma_cfg_a; /* offset 34h */ + u32 dma_cfg_b; /* offset 38h */ + u32 fifo_ctrl; /* offset 3Ch */ + u32 data_block_ptr; /* offset 40h */ + u32 tag_ptr; /* offset 44h */ + u32 resv1; /* offset 48h */ + u32 dec_status; /* offset 4Ch */ + u32 hwstatus_cmd; /* offset 50h */ + u32 hwstatus_mask; /* offset 54h */ + u32 resv2[29]; + u32 bch_config; /* offset CCh */ + u32 bch_dec_result; /* offset D0h */ + u32 bch_dec_status_buf; + /* offset D4h */ +}; diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 072b178a04a..cc573547557 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -36,10 +36,8 @@ COBJS-y += tgec_phy.o COBJS-$(CONFIG_P1017) += p1023.o COBJS-$(CONFIG_P1023) += p1023.o # The P204x, P304x, and P5020 are the same -COBJS-$(CONFIG_PPC_P2040) += p5020.o COBJS-$(CONFIG_PPC_P2041) += p5020.o COBJS-$(CONFIG_PPC_P3041) += p5020.o -COBJS-$(CONFIG_PPC_P3060) += p3060.o COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o endif diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 953c359e6e4..736b8b95829 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(2, 4), #endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) + FM_DTSEC_INFO_INITIALIZER(2, 5), +#endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif @@ -152,6 +155,22 @@ void fm_info_set_phy_address(enum fm_port port, int address) } /* + * Returns the PHY address for a given Fman port + * + * The port must be set via a prior call to fm_info_set_phy_address(). + * A negative error code is returned if the port is invalid. + */ +int fm_info_get_phy_address(enum fm_port port) +{ + int i = fm_port_to_index(port); + + if (i == -1) + return -1; + + return fm_info[i].phy_addr; +} + +/* * Returns the type of the data interface between the given MAC and its PHY. * This is typically determined by the RCW. */ @@ -181,7 +200,8 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { - int off, ph; + int off; + uint32_t ph; phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; @@ -198,12 +218,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) off = fdt_node_offset_by_compat_reg(blob, prop, paddr); /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ - if (paddr != dtsec1_addr) { - /* disable the mac node */ - fdt_setprop_string(blob, off, "status", "disabled"); - } + if (paddr != dtsec1_addr) + fdt_status_disabled(blob, off); /* disable the MAC node */ - /* disable the node point to the mac */ + /* disable the fsl,dpa-ethernet node that points to the MAC */ ph = fdt_get_phandle(blob, off); do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), "status", "disabled", strlen("disabled") + 1, 1); diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c deleted file mode 100644 index c9748a954cc..00000000000 --- a/drivers/net/fm/p3060.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <phy.h> -#include <fm_eth.h> -#include <asm/io.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> - -u32 port_to_devdisr[] = { - [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, - [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, - [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, - [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, - [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, - [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, - [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, - [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, -}; - -static int is_device_disabled(enum fm_port port) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 devdisr2 = in_be32(&gur->devdisr2); - - return port_to_devdisr[port] & devdisr2; -} - -void fman_disable_port(enum fm_port port) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* don't allow disabling of DTSEC1 as its needed for MDIO */ - if (port == FM1_DTSEC1) - return; - - setbits_be32(&gur->devdisr2, port_to_devdisr[port]); -} - -phy_interface_t fman_port_enet_if(enum fm_port port) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr11 = in_be32(&gur->rcwsr[11]); - - if (is_device_disabled(port)) - return PHY_INTERFACE_MODE_NONE; - - /* handle RGMII/MII first */ - if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == - FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) - return PHY_INTERFACE_MODE_RGMII; - - if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == - FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) - return PHY_INTERFACE_MODE_RGMII; - - if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == - FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) - return PHY_INTERFACE_MODE_RGMII; - - switch (port) { - case FM1_DTSEC1: - case FM1_DTSEC2: - case FM1_DTSEC3: - case FM1_DTSEC4: - if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) - return PHY_INTERFACE_MODE_SGMII; - break; - case FM2_DTSEC1: - case FM2_DTSEC2: - case FM2_DTSEC3: - case FM2_DTSEC4: - if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) - return PHY_INTERFACE_MODE_SGMII; - break; - default: - return PHY_INTERFACE_MODE_NONE; - } - - return PHY_INTERFACE_MODE_NONE; -} diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 08206c87119..3103a741a19 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c @@ -483,7 +483,7 @@ int greth_recv(struct eth_device *dev) greth_regs *regs = greth->regs; greth_bd *rxbd; unsigned int status, len = 0, bad; - unsigned char *d; + char *d; int enable = 0; int i; @@ -504,7 +504,7 @@ int greth_recv(struct eth_device *dev) goto done; } - debug("greth_recv: packet 0x%lx, 0x%lx, len: %d\n", + debug("greth_recv: packet 0x%x, 0x%x, len: %d\n", (unsigned int)rxbd, status, status & GRETH_BD_LEN); /* Check status for errors. @@ -620,7 +620,7 @@ int greth_initialize(bd_t * bis) greth->regs = (greth_regs *) apbdev.address; greth->irq = apbdev.irq; - debug("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq); + debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq); dev->priv = (void *)greth; dev->iobase = (unsigned int)greth->regs; dev->init = greth_init; @@ -652,7 +652,7 @@ int greth_initialize(bd_t * bis) /* initiate PHY, select speed/duplex depending on connected PHY */ if (greth_init_phy(greth, bis)) { /* Failed to init PHY (timedout) */ - debug("GRETH[0x%08x]: Failed to init PHY\n", greth->regs); + debug("GRETH[%p]: Failed to init PHY\n", greth->regs); return -1; } @@ -681,6 +681,6 @@ int greth_initialize(bd_t * bis) /* set and remember MAC address */ greth_set_hwaddr(greth, addr); - debug("GRETH[0x%08x]: Initialized successfully\n", greth->regs); + debug("GRETH[%p]: Initialized successfully\n", greth->regs); return 0; } diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 1d75a82bc3d..0d46c963128 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -211,6 +211,95 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } +#ifdef CONFIG_FSL_CORENET +static void fsl_pcie_boot_master(pit_t *pi) +{ + /* configure inbound window for slave's u-boot image */ + debug("PCIEBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + struct pci_region r_inbound; + u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE) + - 1; + pci_set_region(&r_inbound, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + sz_inbound, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + set_inbound_window(pi--, &r_inbound, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + + /* configure inbound window for slave's u-boot image */ + debug("PCIEBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + pci_set_region(&r_inbound, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + sz_inbound, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + set_inbound_window(pi--, &r_inbound, + CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + + /* configure inbound window for slave's ucode and ENV */ + debug("PCIEBOOT - MASTER: Inbound window for slave's " + "ucode and ENV; " + "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE) + - 1; + pci_set_region(&r_inbound, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + sz_inbound, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + set_inbound_window(pi--, &r_inbound, + CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); +} + +static void fsl_pcie_boot_master_release_slave(int port) +{ + unsigned long release_addr; + + /* now release slave's core 0 */ + switch (port) { + case 1: + release_addr = CONFIG_SYS_PCIE1_MEM_VIRT + + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; + break; + case 2: + release_addr = CONFIG_SYS_PCIE2_MEM_VIRT + + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; + break; + case 3: + release_addr = CONFIG_SYS_PCIE3_MEM_VIRT + + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; + break; + default: + release_addr = 0; + break; + } + if (release_addr != 0) { + out_be32((void *)release_addr, + CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + debug("PCIEBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } else { + debug("PCIEBOOT - MASTER: " + "Release slave failed!\n"); + } +} +#endif + void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; @@ -295,8 +384,25 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); +#ifdef CONFIG_FSL_CORENET + /* boot from PCIE --master */ + char *s = getenv("bootmaster"); + char pcie[6]; + sprintf(pcie, "PCIE%d", pci_info->pci_num); + + if (s && (strcmp(s, pcie) == 0)) { + debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n", + pci_info->pci_num); + fsl_pcie_boot_master((pit_t *)pi); + } else { + /* inbound */ + inbound = fsl_pci_setup_inbound_windows(hose, + out_lo, pcie_cap, pi); + } +#else /* inbound */ inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi); +#endif for (r = 0; r < hose->region_count; r++) debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r, @@ -488,6 +594,16 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; +#ifdef CONFIG_FSL_CORENET + } else { + /* boot from PCIE --master releases slave's core 0 */ + char *s = getenv("bootmaster"); + char pcie[6]; + sprintf(pcie, "PCIE%d", pci_info->pci_num); + + if (s && (strcmp(s, pcie) == 0)) + fsl_pcie_boot_master_release_slave(pci_info->pci_num); +#endif } pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 2a6d0a7593c..d864f137f54 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -118,11 +118,11 @@ PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) void *pci_map_bar(pci_dev_t pdev, int bar, int flags) { pci_addr_t pci_bus_addr; - pci_addr_t bar_response; + u32 bar_response; /* read BAR address */ pci_read_config_dword(pdev, bar, &bar_response); - pci_bus_addr = bar_response & ~0xf; + pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); /* * Pass "0" as the length argument to pci_bus_to_virt. The arg @@ -389,7 +389,7 @@ int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command) { - pci_addr_t bar_response; + u32 bar_response; unsigned int old_command; pci_addr_t bar_value; pci_size_t bar_size; diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ae61e24907a..cd78030cd63 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -89,7 +89,7 @@ void pciauto_setup_device(struct pci_controller *hose, struct pci_region *prefetch, struct pci_region *io) { - pci_addr_t bar_response; + u32 bar_response; pci_size_t bar_size; u16 cmdstat = 0; int bar, bar_nr = 0; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 216c8982be2..e6ae709db78 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -580,8 +580,7 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* QE9 and QE12 need to be set for enabling QE MII managment signals */ @@ -592,8 +591,7 @@ static void phy_change(struct eth_device *dev) /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. @@ -1208,16 +1206,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); @@ -1249,8 +1245,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); -#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 3a38f9e327f..2bdb68ba4aa 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -89,11 +89,17 @@ int uartlite_serial_tstc(const int port) return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA; } +static int uartlite_serial_init(const int port) +{ + if (userial_ports[port]) + return 0; + return -1; +} + #if !defined(CONFIG_SERIAL_MULTI) int serial_init(void) { - /* FIXME: Nothing for now. We should initialize fifo, etc */ - return 0; + return uartlite_serial_init(0); } void serial_setbrg(void) @@ -126,7 +132,7 @@ int serial_tstc(void) /* Multi serial device functions */ #define DECLARE_ESERIAL_FUNCTIONS(port) \ int userial##port##_init(void) \ - { return(0); } \ + { return uartlite_serial_init(port); } \ void userial##port##_setbrg(void) {} \ int userial##port##_getc(void) \ { return uartlite_serial_getc(port); } \ @@ -163,17 +169,15 @@ struct serial_device uartlite_serial3_device = __weak struct serial_device *default_serial_console(void) { -# ifdef XILINX_UARTLITE_BASEADDR - return &uartlite_serial0_device; -# endif /* XILINX_UARTLITE_BASEADDR */ -# ifdef XILINX_UARTLITE_BASEADDR1 - return &uartlite_serial1_device; -# endif /* XILINX_UARTLITE_BASEADDR1 */ -# ifdef XILINX_UARTLITE_BASEADDR2 - return &uartlite_serial2_device; -# endif /* XILINX_UARTLITE_BASEADDR2 */ -# ifdef XILINX_UARTLITE_BASEADDR3 - return &uartlite_serial3_device; -# endif /* XILINX_UARTLITE_BASEADDR3 */ + if (userial_ports[0]) + return &uartlite_serial0_device; + if (userial_ports[1]) + return &uartlite_serial1_device; + if (userial_ports[2]) + return &uartlite_serial2_device; + if (userial_ports[3]) + return &uartlite_serial3_device; + + return NULL; } #endif /* CONFIG_SERIAL_MULTI */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 80b981f10fc..f0b82c67f5b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o +COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c new file mode 100644 index 00000000000..72dd1a520db --- /dev/null +++ b/drivers/spi/cf_qspi.c @@ -0,0 +1,373 @@ +/* + * Freescale Coldfire Queued SPI driver + * + * NOTE: + * This driver is written to transfer 8 bit at-a-time and uses the dedicated + * SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem. + * + * + * Copyright (C) 2011 Ruggedcom, Inc. + * Richard Retanubun (richardretanubun@freescale.com) + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/immap.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define clamp(x, low, high) (min(max(low, x), high)) +#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s) + +struct cf_qspi_slave { + struct spi_slave slave; /* Specific bus:cs ID for each device */ + qspi_t *regs; /* Pointer to SPI controller registers */ + u16 qmr; /* QMR: Queued Mode Register */ + u16 qwr; /* QWR: Queued Wrap Register */ + u16 qcr; /* QCR: Queued Command Ram */ +}; + +/* Register write wrapper functions */ +static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; } +static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; } +static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; } +static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; } +static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; } +static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; } +/* Register read wrapper functions */ +static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; } +static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; } +static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; } +static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; } + +/* These call points may be different for each ColdFire CPU */ +extern void cfspi_port_conf(void); +static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high); +static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high); + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} +void spi_release_bus(struct spi_slave *slave) +{ +} + +__attribute__((weak)) +void spi_init(void) +{ + cfspi_port_conf(); +} + +__attribute__((weak)) +void spi_cs_activate(struct spi_slave *slave) +{ + struct cf_qspi_slave *dev = to_cf_qspi_slave(slave); + + cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV)); +} + +__attribute__((weak)) +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct cf_qspi_slave *dev = to_cf_qspi_slave(slave); + + cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV)); +} + +__attribute__((weak)) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Only 1 bus and 4 chipselect per controller */ + if (bus == 0 && (cs >= 0 && cs < 4)) + return 1; + else + return 0; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct cf_qspi_slave *dev = to_cf_qspi_slave(slave); + + free(dev); +} + +/* Translate information given by spi_setup_slave to members of cf_qspi_slave */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct cf_qspi_slave *dev = NULL; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + dev = malloc(sizeof(struct cf_qspi_slave)); + if (!dev) + return NULL; + + /* Initialize to known value */ + dev->slave.bus = bus; + dev->slave.cs = cs; + dev->regs = (qspi_t *)MMAP_QSPI; + dev->qmr = 0; + dev->qwr = 0; + dev->qcr = 0; + + + /* Map max_hz to QMR[BAUD] */ + if (max_hz == 0) /* Go as fast as possible */ + dev->qmr = 2u; + else /* Get the closest baud rate */ + dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz, + 2u, 255u); + + /* Map mode to QMR[CPOL] and QMR[CPHA] */ + if (mode & SPI_CPOL) + dev->qmr |= QSPI_QMR_CPOL; + + if (mode & SPI_CPHA) + dev->qmr |= QSPI_QMR_CPHA; + + /* Hardcode bit length to 8 bit per transter */ + dev->qmr |= QSPI_QMR_BITS_8; + + /* Set QMR[MSTR] to enable QSPI as master */ + dev->qmr |= QSPI_QMR_MSTR; + + /* + * Set QCR and QWR to default values for spi flash operation. + * If more custom QCR and QRW are needed, overload mode variable + */ + dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE); + + if (!(mode & SPI_CS_HIGH)) + dev->qwr |= QSPI_QWR_CSIV; + + return &dev->slave; +} + +/* Transfer 8 bit at a time */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct cf_qspi_slave *dev = to_cf_qspi_slave(slave); + volatile qspi_t *qspi = dev->regs; + u8 *txbuf = (u8 *)dout; + u8 *rxbuf = (u8 *)din; + u32 count = ((bitlen / 8) + (bitlen % 8 ? 1 : 0)); + u32 n, i = 0; + + /* Sanitize arguments */ + if (slave == NULL) { + printf("%s: NULL slave ptr\n", __func__); + return -1; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* There is something to send, lets process it. spi_xfer is also called + * just to toggle chip select, so bitlen of 0 is valid */ + if (count > 0) { + /* + * NOTE: Since chip select is driven as a bit-bang-ed GPIO + * using spi_cs_activate() and spi_cs_deactivate(), + * the chip select settings inside the controller + * (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to + * keep the controller settings consistent with the actual + * operation of the bus. + */ + + /* Write the slave device's settings for the controller.*/ + write_qmr(qspi, dev->qmr); + write_qwr(qspi, dev->qwr); + + /* Limit transfer to 16 at a time */ + n = min(count, 16u); + do { + /* Setup queue end point */ + write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK) + | QSPI_QWR_ENDQP((n-1)))); + + /* Write Command RAM */ + write_qar(qspi, QSPI_QAR_CMD); + for (i = 0; i < n; ++i) + write_qdr(qspi, dev->qcr); + + /* Write TxBuf, if none given, fill with ZEROes */ + write_qar(qspi, QSPI_QAR_TRANS); + if (txbuf) { + for (i = 0; i < n; ++i) + write_qdr(qspi, *txbuf++); + } else { + for (i = 0; i < n; ++i) + write_qdr(qspi, 0); + } + + /* Clear QIR[SPIF] by writing a 1 to it */ + write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF); + /* Set QDLYR[SPE] to start sending */ + write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE); + + /* Poll QIR[SPIF] for transfer completion */ + while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1) + udelay(1); + + /* If given read RxBuf, load data to it */ + if (rxbuf) { + write_qar(qspi, QSPI_QAR_RECV); + for (i = 0; i < n; ++i) + *rxbuf++ = read_qdr(qspi); + } + + /* Decrement count */ + count -= n; + } while (count); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} + +/* Each MCF CPU may have different pin assignments for chip selects. */ +#if defined(CONFIG_M5271) +/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */ +void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high) +{ + debug("%s: bus %d cs %d cs_active_high %d\n", + __func__, bus, cs, cs_active_high); + + switch (cs) { + case 0: /* QSPI_CS[0] = PQSPI[3] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08); + else + mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7); + + mbar_writeByte(MCF_GPIO_PDDR_QSPI, + mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08); + + mbar_writeByte(MCF_GPIO_PAR_QSPI, + mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF); + break; + case 1: /* QSPI_CS[1] = PQSPI[4] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10); + else + mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF); + + mbar_writeByte(MCF_GPIO_PDDR_QSPI, + mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10); + + mbar_writeByte(MCF_GPIO_PAR_QSPI, + mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F); + break; + case 2: /* QSPI_CS[2] = PTIMER[7] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80); + else + mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F); + + mbar_writeByte(MCF_GPIO_PDDR_TIMER, + mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80); + + mbar_writeShort(MCF_GPIO_PAR_TIMER, + mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF); + break; + case 3: /* QSPI_CS[3] = PTIMER[3] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08); + else + mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7); + + mbar_writeByte(MCF_GPIO_PDDR_TIMER, + mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08); + + mbar_writeShort(MCF_GPIO_PAR_TIMER, + mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F); + break; + } +} + +/* Deassert chip select, val = [1|0], dir = in, mode = GPIO + * direction set as IN to undrive the pin, external pullup/pulldown will bring + * bus to deassert state. + */ +void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high) +{ + debug("%s: bus %d cs %d cs_active_high %d\n", + __func__, bus, cs, cs_active_high); + + switch (cs) { + case 0: /* QSPI_CS[0] = PQSPI[3] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7); + else + mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08); + + mbar_writeByte(MCF_GPIO_PDDR_QSPI, + mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7); + + mbar_writeByte(MCF_GPIO_PAR_QSPI, + mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF); + break; + case 1: /* QSPI_CS[1] = PQSPI[4] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF); + else + mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10); + + mbar_writeByte(MCF_GPIO_PDDR_QSPI, + mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF); + + mbar_writeByte(MCF_GPIO_PAR_QSPI, + mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F); + break; + case 2: /* QSPI_CS[2] = PTIMER[7] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F); + else + mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80); + + mbar_writeByte(MCF_GPIO_PDDR_TIMER, + mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F); + + mbar_writeShort(MCF_GPIO_PAR_TIMER, + mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF); + break; + case 3: /* QSPI_CS[3] = PTIMER[3] */ + if (cs_active_high) + mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7); + else + mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08); + + mbar_writeByte(MCF_GPIO_PDDR_TIMER, + mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7); + + mbar_writeShort(MCF_GPIO_PAR_TIMER, + mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F); + break; + } +} +#endif /* CONFIG_M5271 */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index f4523a39291..a7cda751bd0 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -56,8 +56,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); /* calculate spi clock prescaller using max_hz */ - data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK; - data |= 0x10; + data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10; + data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data; + data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data; /* program spi clock prescaller using max_hz */ writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 44ab39dd3ff..4e46041dfff 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -124,6 +124,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * len > 16 0 */ + spi->mode &= ~SPI_MODE_EN; + if (bitlen <= 16) { if (bitlen <= 4) spi->mode = (spi->mode & 0xff0fffff) | @@ -138,6 +140,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, dout += 4; } + spi->mode |= SPI_MODE_EN; + spi->tx = tmpdout; /* Write the data out */ debug("*** spi_xfer: ... %08x written\n", tmpdout); diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 168dbe497e6..42e4c9952ed 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -224,8 +224,10 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, struct mxs_dma_desc *dp; uint32_t ctrl0; uint32_t cache_data_count; + const uint32_t dstart = (uint32_t)data; int dmach; int tl; + int ret = 0; ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count); @@ -239,17 +241,17 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, if (!write) ctrl0 |= SSP_CTRL0_READ; - writel(length, &ssp_regs->hw_ssp_xfer_size); - if (length % ARCH_DMA_MINALIGN) cache_data_count = roundup(length, ARCH_DMA_MINALIGN); else cache_data_count = length; + /* Flush data to DRAM so DMA can pick them up */ if (write) - /* Flush data to DRAM so DMA can pick them up */ - flush_dcache_range((uint32_t)data, - (uint32_t)(data + cache_data_count)); + flush_dcache_range(dstart, dstart + cache_data_count); + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range(dstart, dstart + cache_data_count); dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; @@ -281,41 +283,47 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, tl = min(length, xfer_max_sz); dp->cmd.data |= - (tl << MXS_DMA_DESC_BYTES_OFFSET) | - (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | + ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) | + (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | MXS_DMA_DESC_HALT_ON_TERMINATE | MXS_DMA_DESC_TERMINATE_FLUSH; - dp->cmd.pio_words[0] = ctrl0; data += tl; length -= tl; + if (!length) { + dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; + + if (flags & SPI_XFER_END) { + ctrl0 &= ~SSP_CTRL0_LOCK_CS; + ctrl0 |= SSP_CTRL0_IGNORE_CRC; + } + } + + /* + * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is + * essential that the XFER_SIZE register is written on + * a per-descriptor basis with the same size as is the + * descriptor! + */ + dp->cmd.pio_words[0] = ctrl0; + dp->cmd.pio_words[1] = 0; + dp->cmd.pio_words[2] = 0; + dp->cmd.pio_words[3] = tl; + mxs_dma_desc_append(dmach, dp); dp++; } - dp->address = (dma_addr_t)dp; - dp->cmd.address = (dma_addr_t)0; - dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | - (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | - MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM; - if (flags & SPI_XFER_END) { - ctrl0 &= ~SSP_CTRL0_LOCK_CS; - dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC; - } - mxs_dma_desc_append(dmach, dp); - if (mxs_dma_go(dmach)) - return -EINVAL; + ret = -EINVAL; /* The data arrived into DRAM, invalidate cache over them */ - if (!write) { - invalidate_dcache_range((uint32_t)data, - (uint32_t)(data + cache_data_count)); - } + if (!write) + invalidate_dcache_range(dstart, dstart + cache_data_count); - return 0; + return ret; } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra_spi.c index 2355e022b02..18b00b2cae9 100644 --- a/drivers/spi/tegra_spi.c +++ b/drivers/spi/tegra_spi.c @@ -72,9 +72,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - if (max_hz > TEGRA20_SPI_MAX_FREQ) { + if (max_hz > TEGRA_SPI_MAX_FREQ) { printf("SPI error: unsupported frequency %d Hz. Max frequency" - " is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ); + " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); return NULL; } @@ -86,7 +86,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, spi->slave.bus = bus; spi->slave.cs = cs; spi->freq = max_hz; - spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE; + spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE; spi->mode = mode; return &spi->slave; diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index e563c19051a..52a4134f18b 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -78,7 +78,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct xilinx_spi_slave *xilspi; - struct xilinx_spi_reg *regs; if (!spi_cs_is_valid(bus, cs)) { printf("XILSPI error: %s: unsupported bus %d / cs %d\n", diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 18b4bc65470..392e2862245 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -22,6 +22,7 @@ */ #include <common.h> #include <asm/byteorder.h> +#include <asm/unaligned.h> #include <usb.h> #include <asm/io.h> #include <malloc.h> @@ -866,10 +867,12 @@ int usb_lowlevel_init(void) printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); /* Port Indicators */ if (HCS_INDICATOR(reg)) - descriptor.hub.wHubCharacteristics |= 0x80; + put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) + | 0x80, &descriptor.hub.wHubCharacteristics); /* Port Power Control */ if (HCS_PPC(reg)) - descriptor.hub.wHubCharacteristics |= 0x01; + put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) + | 0x01, &descriptor.hub.wHubCharacteristics); /* Start the host controller. */ cmd = ehci_readl(&hcor->or_usbcmd); diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c index 6686718b0a7..b1424bfd038 100644 --- a/drivers/video/omap3_dss.c +++ b/drivers/video/omap3_dss.c @@ -112,7 +112,7 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg) writel(panel_cfg->pol_freq, &dispc->pol_freq); writel(panel_cfg->divisor, &dispc->divisor); writel(panel_cfg->lcd_size, &dispc->size_lcd); - writel(panel_cfg->load_mode << FRAME_MODE_SHIFT, &dispc->config); + writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config); writel(panel_cfg->panel_type << TFTSTN_SHIFT | panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control); writel(panel_cfg->panel_color, &dispc->default_color0); @@ -121,7 +121,6 @@ void omap3_dss_panel_config(const struct panel_config *panel_cfg) if (!panel_cfg->frame_buffer) return; - writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config); writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes); writel(1, &dispc->gfx_row_inc); writel(1, &dispc->gfx_pixel_inc); diff --git a/fs/Makefile b/fs/Makefile index 28da76e9591..901e1894b6a 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -23,7 +23,10 @@ # subdirs-$(CONFIG_CMD_CRAMFS) := cramfs -subdirs-$(CONFIG_CMD_EXT2) += ext2 +subdirs-$(CONFIG_CMD_EXT4) += ext4 +ifndef CONFIG_CMD_EXT4 +subdirs-$(CONFIG_CMD_EXT2) += ext4 +endif subdirs-$(CONFIG_CMD_FAT) += fat subdirs-$(CONFIG_CMD_FDOS) += fdos subdirs-$(CONFIG_CMD_JFFS2) += jffs2 diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c deleted file mode 100644 index 874e21161e6..00000000000 --- a/fs/ext2/dev.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2004 - * esd gmbh <www.esd-electronics.com> - * Reinhard Arlt <reinhard.arlt@esd-electronics.com> - * - * based on code of fs/reiserfs/dev.c by - * - * (C) Copyright 2003 - 2004 - * Sysgo AG, <www.elinos.com>, Pavel Bartusek <pba@sysgo.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - -#include <common.h> -#include <config.h> -#include <ext2fs.h> - -static block_dev_desc_t *ext2fs_block_dev_desc; -static disk_partition_t part_info; - -int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part) -{ - ext2fs_block_dev_desc = rbdd; - - if (part == 0) { - /* disk doesn't use partition table */ - part_info.start = 0; - part_info.size = rbdd->lba; - part_info.blksz = rbdd->blksz; - } else { - if (get_partition_info - (ext2fs_block_dev_desc, part, &part_info)) { - return 0; - } - } - return part_info.size; -} - - -int ext2fs_devread(int sector, int byte_offset, int byte_len, char *buf) -{ - ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE); - unsigned sectors; - - /* - * Check partition boundaries - */ - if ((sector < 0) || - ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= - part_info.size)) { - /* errnum = ERR_OUTSIDE_PART; */ - printf(" ** %s read outside partition sector %d\n", - __func__, - sector); - return 0; - } - - /* - * Get the read to the beginning of a partition. - */ - sector += byte_offset >> SECTOR_BITS; - byte_offset &= SECTOR_SIZE - 1; - - debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len); - - if (ext2fs_block_dev_desc == NULL) { - printf(" ** %s Invalid Block Device Descriptor (NULL)\n", - __func__); - return 0; - } - - if (byte_offset != 0) { - /* read first part which isn't aligned with start of sector */ - if (ext2fs_block_dev_desc-> - block_read(ext2fs_block_dev_desc->dev, - part_info.start + sector, 1, - (unsigned long *) sec_buf) != 1) { - printf(" ** %s read error **\n", __func__); - return 0; - } - memcpy(buf, sec_buf + byte_offset, - min(SECTOR_SIZE - byte_offset, byte_len)); - buf += min(SECTOR_SIZE - byte_offset, byte_len); - byte_len -= min(SECTOR_SIZE - byte_offset, byte_len); - sector++; - } - - /* read sector aligned part */ - sectors = byte_len / SECTOR_SIZE; - - if (sectors > 0) { - if (ext2fs_block_dev_desc->block_read( - ext2fs_block_dev_desc->dev, - part_info.start + sector, - sectors, - (unsigned long *) buf) != sectors) { - printf(" ** %s read error - block\n", __func__); - return 0; - } - - buf += sectors * SECTOR_SIZE; - byte_len -= sectors * SECTOR_SIZE; - sector += sectors; - } - - if (byte_len != 0) { - /* read rest of data which are not in whole sector */ - if (ext2fs_block_dev_desc-> - block_read(ext2fs_block_dev_desc->dev, - part_info.start + sector, 1, - (unsigned long *) sec_buf) != 1) { - printf(" ** %s read error - last part\n", __func__); - return 0; - } - memcpy(buf, sec_buf, byte_len); - } - return 1; -} diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c deleted file mode 100644 index 418404e6062..00000000000 --- a/fs/ext2/ext2fs.c +++ /dev/null @@ -1,919 +0,0 @@ -/* - * (C) Copyright 2004 - * esd gmbh <www.esd-electronics.com> - * Reinhard Arlt <reinhard.arlt@esd-electronics.com> - * - * based on code from grub2 fs/ext2.c and fs/fshelp.c by - * - * GRUB -- GRand Unified Bootloader - * Copyright (C) 2003, 2004 Free Software Foundation, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <common.h> -#include <ext2fs.h> -#include <malloc.h> -#include <asm/byteorder.h> - -extern int ext2fs_devread (int sector, int byte_offset, int byte_len, - char *buf); - -/* Magic value used to identify an ext2 filesystem. */ -#define EXT2_MAGIC 0xEF53 -/* Amount of indirect blocks in an inode. */ -#define INDIRECT_BLOCKS 12 -/* Maximum lenght of a pathname. */ -#define EXT2_PATH_MAX 4096 -/* Maximum nesting of symlinks, used to prevent a loop. */ -#define EXT2_MAX_SYMLINKCNT 8 - -/* Filetype used in directory entry. */ -#define FILETYPE_UNKNOWN 0 -#define FILETYPE_REG 1 -#define FILETYPE_DIRECTORY 2 -#define FILETYPE_SYMLINK 7 - -/* Filetype information as used in inodes. */ -#define FILETYPE_INO_MASK 0170000 -#define FILETYPE_INO_REG 0100000 -#define FILETYPE_INO_DIRECTORY 0040000 -#define FILETYPE_INO_SYMLINK 0120000 - -/* Bits used as offset in sector */ -#define DISK_SECTOR_BITS 9 - -/* Log2 size of ext2 block in 512 blocks. */ -#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 1) - -/* Log2 size of ext2 block in bytes. */ -#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu (data->sblock.log2_block_size) + 10) - -/* The size of an ext2 block in bytes. */ -#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) - -/* The ext2 superblock. */ -struct ext2_sblock { - uint32_t total_inodes; - uint32_t total_blocks; - uint32_t reserved_blocks; - uint32_t free_blocks; - uint32_t free_inodes; - uint32_t first_data_block; - uint32_t log2_block_size; - uint32_t log2_fragment_size; - uint32_t blocks_per_group; - uint32_t fragments_per_group; - uint32_t inodes_per_group; - uint32_t mtime; - uint32_t utime; - uint16_t mnt_count; - uint16_t max_mnt_count; - uint16_t magic; - uint16_t fs_state; - uint16_t error_handling; - uint16_t minor_revision_level; - uint32_t lastcheck; - uint32_t checkinterval; - uint32_t creator_os; - uint32_t revision_level; - uint16_t uid_reserved; - uint16_t gid_reserved; - uint32_t first_inode; - uint16_t inode_size; - uint16_t block_group_number; - uint32_t feature_compatibility; - uint32_t feature_incompat; - uint32_t feature_ro_compat; - uint32_t unique_id[4]; - char volume_name[16]; - char last_mounted_on[64]; - uint32_t compression_info; -}; - -/* The ext2 blockgroup. */ -struct ext2_block_group { - uint32_t block_id; - uint32_t inode_id; - uint32_t inode_table_id; - uint16_t free_blocks; - uint16_t free_inodes; - uint16_t used_dir_cnt; - uint32_t reserved[3]; -}; - -/* The ext2 inode. */ -struct ext2_inode { - uint16_t mode; - uint16_t uid; - uint32_t size; - uint32_t atime; - uint32_t ctime; - uint32_t mtime; - uint32_t dtime; - uint16_t gid; - uint16_t nlinks; - uint32_t blockcnt; /* Blocks of 512 bytes!! */ - uint32_t flags; - uint32_t osd1; - union { - struct datablocks { - uint32_t dir_blocks[INDIRECT_BLOCKS]; - uint32_t indir_block; - uint32_t double_indir_block; - uint32_t tripple_indir_block; - } blocks; - char symlink[60]; - } b; - uint32_t version; - uint32_t acl; - uint32_t dir_acl; - uint32_t fragment_addr; - uint32_t osd2[3]; -}; - -/* The header of an ext2 directory entry. */ -struct ext2_dirent { - uint32_t inode; - uint16_t direntlen; - uint8_t namelen; - uint8_t filetype; -}; - -struct ext2fs_node { - struct ext2_data *data; - struct ext2_inode inode; - int ino; - int inode_read; -}; - -/* Information about a "mounted" ext2 filesystem. */ -struct ext2_data { - struct ext2_sblock sblock; - struct ext2_inode *inode; - struct ext2fs_node diropen; -}; - - -typedef struct ext2fs_node *ext2fs_node_t; - -struct ext2_data *ext2fs_root = NULL; -ext2fs_node_t ext2fs_file = NULL; -int symlinknest = 0; -uint32_t *indir1_block = NULL; -int indir1_size = 0; -int indir1_blkno = -1; -uint32_t *indir2_block = NULL; -int indir2_size = 0; -int indir2_blkno = -1; -static unsigned int inode_size; - - -static int ext2fs_blockgroup - (struct ext2_data *data, int group, struct ext2_block_group *blkgrp) { - unsigned int blkno; - unsigned int blkoff; - unsigned int desc_per_blk; - - desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group); - - blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 + - group / desc_per_blk; - blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group); -#ifdef DEBUG - printf ("ext2fs read %d group descriptor (blkno %d blkoff %d)\n", - group, blkno, blkoff); -#endif - return (ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE(data), - blkoff, sizeof(struct ext2_block_group), (char *)blkgrp)); - -} - - -static int ext2fs_read_inode - (struct ext2_data *data, int ino, struct ext2_inode *inode) { - struct ext2_block_group blkgrp; - struct ext2_sblock *sblock = &data->sblock; - int inodes_per_block; - int status; - - unsigned int blkno; - unsigned int blkoff; - -#ifdef DEBUG - printf ("ext2fs read inode %d, inode_size %d\n", ino, inode_size); -#endif - /* It is easier to calculate if the first inode is 0. */ - ino--; - status = ext2fs_blockgroup (data, ino / __le32_to_cpu - (sblock->inodes_per_group), &blkgrp); - if (status == 0) { - return (0); - } - - inodes_per_block = EXT2_BLOCK_SIZE(data) / inode_size; - - blkno = __le32_to_cpu (blkgrp.inode_table_id) + - (ino % __le32_to_cpu (sblock->inodes_per_group)) - / inodes_per_block; - blkoff = (ino % inodes_per_block) * inode_size; -#ifdef DEBUG - printf ("ext2fs read inode blkno %d blkoff %d\n", blkno, blkoff); -#endif - /* Read the inode. */ - status = ext2fs_devread (blkno << LOG2_EXT2_BLOCK_SIZE (data), blkoff, - sizeof (struct ext2_inode), (char *) inode); - if (status == 0) { - return (0); - } - - return (1); -} - - -void ext2fs_free_node (ext2fs_node_t node, ext2fs_node_t currroot) { - if ((node != &ext2fs_root->diropen) && (node != currroot)) { - free (node); - } -} - - -static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { - struct ext2_data *data = node->data; - struct ext2_inode *inode = &node->inode; - int blknr; - int blksz = EXT2_BLOCK_SIZE (data); - int log2_blksz = LOG2_EXT2_BLOCK_SIZE (data); - int status; - - /* Direct blocks. */ - if (fileblock < INDIRECT_BLOCKS) { - blknr = __le32_to_cpu (inode->b.blocks.dir_blocks[fileblock]); - } - /* Indirect. */ - else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { - if (indir1_block == NULL) { - indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir1_block == NULL) { - printf ("** ext2fs read block (indir 1) malloc failed. **\n"); - return (-1); - } - indir1_size = blksz; - indir1_blkno = -1; - } - if (blksz != indir1_size) { - free (indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir1_block == NULL) { - printf ("** ext2fs read block (indir 1) malloc failed. **\n"); - return (-1); - } - indir1_size = blksz; - } - if ((__le32_to_cpu (inode->b.blocks.indir_block) << - log2_blksz) != indir1_blkno) { - status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.indir_block) << log2_blksz, - 0, blksz, - (char *) indir1_block); - if (status == 0) { - printf ("** ext2fs read block (indir 1) failed. **\n"); - return (0); - } - indir1_blkno = - __le32_to_cpu (inode->b.blocks. - indir_block) << log2_blksz; - } - blknr = __le32_to_cpu (indir1_block - [fileblock - INDIRECT_BLOCKS]); - } - /* Double indirect. */ - else if (fileblock < - (INDIRECT_BLOCKS + (blksz / 4 * (blksz / 4 + 1)))) { - unsigned int perblock = blksz / 4; - unsigned int rblock = fileblock - (INDIRECT_BLOCKS - + blksz / 4); - - if (indir1_block == NULL) { - indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir1_block == NULL) { - printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); - return (-1); - } - indir1_size = blksz; - indir1_blkno = -1; - } - if (blksz != indir1_size) { - free (indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir1_block == NULL) { - printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); - return (-1); - } - indir1_size = blksz; - } - if ((__le32_to_cpu (inode->b.blocks.double_indir_block) << - log2_blksz) != indir1_blkno) { - status = ext2fs_devread (__le32_to_cpu(inode->b.blocks.double_indir_block) << log2_blksz, - 0, blksz, - (char *) indir1_block); - if (status == 0) { - printf ("** ext2fs read block (indir 2 1) failed. **\n"); - return (-1); - } - indir1_blkno = - __le32_to_cpu (inode->b.blocks.double_indir_block) << log2_blksz; - } - - if (indir2_block == NULL) { - indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir2_block == NULL) { - printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); - return (-1); - } - indir2_size = blksz; - indir2_blkno = -1; - } - if (blksz != indir2_size) { - free (indir2_block); - indir2_block = NULL; - indir2_size = 0; - indir2_blkno = -1; - indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, - blksz); - if (indir2_block == NULL) { - printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); - return (-1); - } - indir2_size = blksz; - } - if ((__le32_to_cpu (indir1_block[rblock / perblock]) << - log2_blksz) != indir2_blkno) { - status = ext2fs_devread (__le32_to_cpu(indir1_block[rblock / perblock]) << log2_blksz, - 0, blksz, - (char *) indir2_block); - if (status == 0) { - printf ("** ext2fs read block (indir 2 2) failed. **\n"); - return (-1); - } - indir2_blkno = - __le32_to_cpu (indir1_block[rblock / perblock]) << log2_blksz; - } - blknr = __le32_to_cpu (indir2_block[rblock % perblock]); - } - /* Tripple indirect. */ - else { - printf ("** ext2fs doesn't support tripple indirect blocks. **\n"); - return (-1); - } -#ifdef DEBUG - printf ("ext2fs_read_block %08x\n", blknr); -#endif - return (blknr); -} - - -int ext2fs_read_file - (ext2fs_node_t node, int pos, unsigned int len, char *buf) { - int i; - int blockcnt; - int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data); - int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS); - unsigned int filesize = __le32_to_cpu(node->inode.size); - - /* Adjust len so it we can't read past the end of the file. */ - if (len > filesize) { - len = filesize; - } - blockcnt = ((len + pos) + blocksize - 1) / blocksize; - - for (i = pos / blocksize; i < blockcnt; i++) { - int blknr; - int blockoff = pos % blocksize; - int blockend = blocksize; - - int skipfirst = 0; - - blknr = ext2fs_read_block (node, i); - if (blknr < 0) { - return (-1); - } - - /* Last block. */ - if (i == blockcnt - 1) { - blockend = (len + pos) % blocksize; - - /* The last portion is exactly blocksize. */ - if (!blockend) { - blockend = blocksize; - } - } - - /* First block. */ - if (i == pos / blocksize) { - skipfirst = blockoff; - blockend -= skipfirst; - } - - /* grab middle blocks in one go */ - if (i != pos / blocksize && i < blockcnt - 1 && blockcnt > 3) { - int oldblk = blknr; - int blocknxt = ext2fs_read_block(node, i + 1); - while (i < blockcnt - 1) { - if (blocknxt == (oldblk + 1)) { - oldblk = blocknxt; - i++; - } else { - blocknxt = ext2fs_read_block(node, i); - break; - } - blocknxt = ext2fs_read_block(node, i); - } - - if (oldblk == blknr) - blockend = blocksize; - else - blockend = (1 + blocknxt - blknr) * blocksize; - } - - blknr = blknr << log2blocksize; - - /* If the block number is 0 this block is not stored on disk but - is zero filled instead. */ - if (blknr) { - int status; - - status = ext2fs_devread (blknr, skipfirst, blockend, buf); - if (status == 0) { - return (-1); - } - } else { - memset (buf, 0, blocksize - skipfirst); - } - buf += blockend - skipfirst; - } - return (len); -} - - -static int ext2fs_iterate_dir (ext2fs_node_t dir, char *name, ext2fs_node_t * fnode, int *ftype) -{ - unsigned int fpos = 0; - int status; - struct ext2fs_node *diro = (struct ext2fs_node *) dir; - -#ifdef DEBUG - if (name != NULL) - printf ("Iterate dir %s\n", name); -#endif /* of DEBUG */ - if (!diro->inode_read) { - status = ext2fs_read_inode (diro->data, diro->ino, - &diro->inode); - if (status == 0) { - return (0); - } - } - /* Search the file. */ - while (fpos < __le32_to_cpu (diro->inode.size)) { - struct ext2_dirent dirent; - - status = ext2fs_read_file (diro, fpos, - sizeof (struct ext2_dirent), - (char *) &dirent); - if (status < 1) { - return (0); - } - if (dirent.namelen != 0) { - char filename[dirent.namelen + 1]; - ext2fs_node_t fdiro; - int type = FILETYPE_UNKNOWN; - - status = ext2fs_read_file (diro, - fpos + sizeof (struct ext2_dirent), - dirent.namelen, filename); - if (status < 1) { - return (0); - } - fdiro = malloc (sizeof (struct ext2fs_node)); - if (!fdiro) { - return (0); - } - - fdiro->data = diro->data; - fdiro->ino = __le32_to_cpu (dirent.inode); - - filename[dirent.namelen] = '\0'; - - if (dirent.filetype != FILETYPE_UNKNOWN) { - fdiro->inode_read = 0; - - if (dirent.filetype == FILETYPE_DIRECTORY) { - type = FILETYPE_DIRECTORY; - } else if (dirent.filetype == - FILETYPE_SYMLINK) { - type = FILETYPE_SYMLINK; - } else if (dirent.filetype == FILETYPE_REG) { - type = FILETYPE_REG; - } - } else { - /* The filetype can not be read from the dirent, get it from inode */ - - status = ext2fs_read_inode (diro->data, - __le32_to_cpu(dirent.inode), - &fdiro->inode); - if (status == 0) { - free (fdiro); - return (0); - } - fdiro->inode_read = 1; - - if ((__le16_to_cpu (fdiro->inode.mode) & - FILETYPE_INO_MASK) == - FILETYPE_INO_DIRECTORY) { - type = FILETYPE_DIRECTORY; - } else if ((__le16_to_cpu (fdiro->inode.mode) - & FILETYPE_INO_MASK) == - FILETYPE_INO_SYMLINK) { - type = FILETYPE_SYMLINK; - } else if ((__le16_to_cpu (fdiro->inode.mode) - & FILETYPE_INO_MASK) == - FILETYPE_INO_REG) { - type = FILETYPE_REG; - } - } -#ifdef DEBUG - printf ("iterate >%s<\n", filename); -#endif /* of DEBUG */ - if ((name != NULL) && (fnode != NULL) - && (ftype != NULL)) { - if (strcmp (filename, name) == 0) { - *ftype = type; - *fnode = fdiro; - return (1); - } - } else { - if (fdiro->inode_read == 0) { - status = ext2fs_read_inode (diro->data, - __le32_to_cpu (dirent.inode), - &fdiro->inode); - if (status == 0) { - free (fdiro); - return (0); - } - fdiro->inode_read = 1; - } - switch (type) { - case FILETYPE_DIRECTORY: - printf ("<DIR> "); - break; - case FILETYPE_SYMLINK: - printf ("<SYM> "); - break; - case FILETYPE_REG: - printf (" "); - break; - default: - printf ("< ? > "); - break; - } - printf ("%10d %s\n", - __le32_to_cpu (fdiro->inode.size), - filename); - } - free (fdiro); - } - fpos += __le16_to_cpu (dirent.direntlen); - } - return (0); -} - - -static char *ext2fs_read_symlink (ext2fs_node_t node) { - char *symlink; - struct ext2fs_node *diro = node; - int status; - - if (!diro->inode_read) { - status = ext2fs_read_inode (diro->data, diro->ino, - &diro->inode); - if (status == 0) { - return (0); - } - } - symlink = malloc (__le32_to_cpu (diro->inode.size) + 1); - if (!symlink) { - return (0); - } - /* If the filesize of the symlink is bigger than - 60 the symlink is stored in a separate block, - otherwise it is stored in the inode. */ - if (__le32_to_cpu (diro->inode.size) <= 60) { - strncpy (symlink, diro->inode.b.symlink, - __le32_to_cpu (diro->inode.size)); - } else { - status = ext2fs_read_file (diro, 0, - __le32_to_cpu (diro->inode.size), - symlink); - if (status == 0) { - free (symlink); - return (0); - } - } - symlink[__le32_to_cpu (diro->inode.size)] = '\0'; - return (symlink); -} - - -int ext2fs_find_file1 - (const char *currpath, - ext2fs_node_t currroot, ext2fs_node_t * currfound, int *foundtype) { - char fpath[strlen (currpath) + 1]; - char *name = fpath; - char *next; - int status; - int type = FILETYPE_DIRECTORY; - ext2fs_node_t currnode = currroot; - ext2fs_node_t oldnode = currroot; - - strncpy (fpath, currpath, strlen (currpath) + 1); - - /* Remove all leading slashes. */ - while (*name == '/') { - name++; - } - if (!*name) { - *currfound = currnode; - return (1); - } - - for (;;) { - int found; - - /* Extract the actual part from the pathname. */ - next = strchr (name, '/'); - if (next) { - /* Remove all leading slashes. */ - while (*next == '/') { - *(next++) = '\0'; - } - } - - /* At this point it is expected that the current node is a directory, check if this is true. */ - if (type != FILETYPE_DIRECTORY) { - ext2fs_free_node (currnode, currroot); - return (0); - } - - oldnode = currnode; - - /* Iterate over the directory. */ - found = ext2fs_iterate_dir (currnode, name, &currnode, &type); - if (found == 0) { - return (0); - } - if (found == -1) { - break; - } - - /* Read in the symlink and follow it. */ - if (type == FILETYPE_SYMLINK) { - char *symlink; - - /* Test if the symlink does not loop. */ - if (++symlinknest == 8) { - ext2fs_free_node (currnode, currroot); - ext2fs_free_node (oldnode, currroot); - return (0); - } - - symlink = ext2fs_read_symlink (currnode); - ext2fs_free_node (currnode, currroot); - - if (!symlink) { - ext2fs_free_node (oldnode, currroot); - return (0); - } -#ifdef DEBUG - printf ("Got symlink >%s<\n", symlink); -#endif /* of DEBUG */ - /* The symlink is an absolute path, go back to the root inode. */ - if (symlink[0] == '/') { - ext2fs_free_node (oldnode, currroot); - oldnode = &ext2fs_root->diropen; - } - - /* Lookup the node the symlink points to. */ - status = ext2fs_find_file1 (symlink, oldnode, - &currnode, &type); - - free (symlink); - - if (status == 0) { - ext2fs_free_node (oldnode, currroot); - return (0); - } - } - - ext2fs_free_node (oldnode, currroot); - - /* Found the node! */ - if (!next || *next == '\0') { - *currfound = currnode; - *foundtype = type; - return (1); - } - name = next; - } - return (-1); -} - - -int ext2fs_find_file - (const char *path, - ext2fs_node_t rootnode, ext2fs_node_t * foundnode, int expecttype) { - int status; - int foundtype = FILETYPE_DIRECTORY; - - - symlinknest = 0; - if (!path) { - return (0); - } - - status = ext2fs_find_file1 (path, rootnode, foundnode, &foundtype); - if (status == 0) { - return (0); - } - /* Check if the node that was found was of the expected type. */ - if ((expecttype == FILETYPE_REG) && (foundtype != expecttype)) { - return (0); - } else if ((expecttype == FILETYPE_DIRECTORY) - && (foundtype != expecttype)) { - return (0); - } - return (1); -} - - -int ext2fs_ls (const char *dirname) { - ext2fs_node_t dirnode; - int status; - - if (ext2fs_root == NULL) { - return (0); - } - - status = ext2fs_find_file (dirname, &ext2fs_root->diropen, &dirnode, - FILETYPE_DIRECTORY); - if (status != 1) { - printf ("** Can not find directory. **\n"); - return (1); - } - ext2fs_iterate_dir (dirnode, NULL, NULL, NULL); - ext2fs_free_node (dirnode, &ext2fs_root->diropen); - return (0); -} - - -int ext2fs_open (const char *filename) { - ext2fs_node_t fdiro = NULL; - int status; - int len; - - if (ext2fs_root == NULL) { - return (-1); - } - ext2fs_file = NULL; - status = ext2fs_find_file (filename, &ext2fs_root->diropen, &fdiro, - FILETYPE_REG); - if (status == 0) { - goto fail; - } - if (!fdiro->inode_read) { - status = ext2fs_read_inode (fdiro->data, fdiro->ino, - &fdiro->inode); - if (status == 0) { - goto fail; - } - } - len = __le32_to_cpu (fdiro->inode.size); - ext2fs_file = fdiro; - return (len); - -fail: - ext2fs_free_node (fdiro, &ext2fs_root->diropen); - return (-1); -} - - -int ext2fs_close (void - ) { - if ((ext2fs_file != NULL) && (ext2fs_root != NULL)) { - ext2fs_free_node (ext2fs_file, &ext2fs_root->diropen); - ext2fs_file = NULL; - } - if (ext2fs_root != NULL) { - free (ext2fs_root); - ext2fs_root = NULL; - } - if (indir1_block != NULL) { - free (indir1_block); - indir1_block = NULL; - indir1_size = 0; - indir1_blkno = -1; - } - if (indir2_block != NULL) { - free (indir2_block); - indir2_block = NULL; - indir2_size = 0; - indir2_blkno = -1; - } - return (0); -} - - -int ext2fs_read (char *buf, unsigned len) { - int status; - - if (ext2fs_root == NULL) { - return (0); - } - - if (ext2fs_file == NULL) { - return (0); - } - - status = ext2fs_read_file (ext2fs_file, 0, len, buf); - return (status); -} - - -int ext2fs_mount (unsigned part_length) { - struct ext2_data *data; - int status; - - data = malloc (sizeof (struct ext2_data)); - if (!data) { - return (0); - } - /* Read the superblock. */ - status = ext2fs_devread (1 * 2, 0, sizeof (struct ext2_sblock), - (char *) &data->sblock); - if (status == 0) { - goto fail; - } - /* Make sure this is an ext2 filesystem. */ - if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) { - goto fail; - } - if (__le32_to_cpu(data->sblock.revision_level == 0)) { - inode_size = 128; - } else { - inode_size = __le16_to_cpu(data->sblock.inode_size); - } -#ifdef DEBUG - printf("EXT2 rev %d, inode_size %d\n", - __le32_to_cpu(data->sblock.revision_level), inode_size); -#endif - data->diropen.data = data; - data->diropen.ino = 2; - data->diropen.inode_read = 1; - data->inode = &data->diropen.inode; - - status = ext2fs_read_inode (data, 2, data->inode); - if (status == 0) { - goto fail; - } - - ext2fs_root = data; - - return (1); - -fail: - printf ("Failed to mount ext2 filesystem...\n"); - free (data); - ext2fs_root = NULL; - return (0); -} diff --git a/fs/ext2/Makefile b/fs/ext4/Makefile index 3c65d252f58..82cd9ae16a5 100644 --- a/fs/ext2/Makefile +++ b/fs/ext4/Makefile @@ -27,15 +27,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libext2fs.o +LIB = $(obj)libext4fs.o AOBJS = -COBJS-$(CONFIG_CMD_EXT2) := ext2fs.o dev.o +COBJS-$(CONFIG_CMD_EXT4) := ext4fs.o ext4_common.o dev.o +ifndef CONFIG_CMD_EXT4 +COBJS-$(CONFIG_CMD_EXT2) := ext4fs.o ext4_common.o dev.o +endif +COBJS-$(CONFIG_CMD_EXT4_WRITE) += ext4_journal.o crc16.o SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) -#CPPFLAGS += all: $(LIB) $(AOBJS) diff --git a/fs/ext4/crc16.c b/fs/ext4/crc16.c new file mode 100644 index 00000000000..3afb34daefa --- /dev/null +++ b/fs/ext4/crc16.c @@ -0,0 +1,62 @@ +/* + * crc16.c + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include <common.h> +#include <asm/byteorder.h> +#include <linux/stat.h> +#include "crc16.h" + +/** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */ +static __u16 const crc16_table[256] = { + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 +}; + +/** + * Compute the CRC-16 for the data buffer +*/ + +unsigned int ext2fs_crc16(unsigned int crc, + const void *buffer, unsigned int len) +{ + const unsigned char *cp = buffer; + + while (len--) + crc = (((crc >> 8) & 0xffU) ^ + crc16_table[(crc ^ *cp++) & 0xffU]) & 0x0000ffffU; + return crc; +} diff --git a/fs/ext4/crc16.h b/fs/ext4/crc16.h new file mode 100644 index 00000000000..5fd113a56c0 --- /dev/null +++ b/fs/ext4/crc16.h @@ -0,0 +1,16 @@ +/* + * crc16.h - CRC-16 routine + * Implements the standard CRC-16: + * Width 16 + * Poly 0x8005 (x16 + x15 + x2 + 1) + * Init 0 + * + * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com> + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ +#ifndef __CRC16_H +#define __CRC16_H +extern unsigned int ext2fs_crc16(unsigned int crc, + const void *buffer, unsigned int len); +#endif diff --git a/fs/ext4/dev.c b/fs/ext4/dev.c new file mode 100644 index 00000000000..1596a92b9ad --- /dev/null +++ b/fs/ext4/dev.c @@ -0,0 +1,139 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * made from existing ext2/dev.c file of Uboot + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code of fs/reiserfs/dev.c by + * + * (C) Copyright 2003 - 2004 + * Sysgo AG, <www.elinos.com>, Pavel Bartusek <pba@sysgo.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * Changelog: + * 0.1 - Newly created file for ext4fs support. Taken from + * fs/ext2/dev.c file in uboot. + */ + +#include <common.h> +#include <config.h> +#include <ext4fs.h> +#include <ext_common.h> + +unsigned long part_offset; + +static block_dev_desc_t *ext4fs_block_dev_desc; +static disk_partition_t *part_info; + +void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) +{ + ext4fs_block_dev_desc = rbdd; + part_info = info; + part_offset = info->start; + get_fs()->total_sect = (info->size * info->blksz) / SECTOR_SIZE; +} + +int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, SECTOR_SIZE); + unsigned block_len; + + /* Check partition boundaries */ + if ((sector < 0) + || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= + part_info->size)) { + printf("%s read outside partition %d\n", __func__, sector); + return 0; + } + + /* Get the read to the beginning of a partition */ + sector += byte_offset >> SECTOR_BITS; + byte_offset &= SECTOR_SIZE - 1; + + debug(" <%d, %d, %d>\n", sector, byte_offset, byte_len); + + if (ext4fs_block_dev_desc == NULL) { + printf("** Invalid Block Device Descriptor (NULL)\n"); + return 0; + } + + if (byte_offset != 0) { + /* read first part which isn't aligned with start of sector */ + if (ext4fs_block_dev_desc-> + block_read(ext4fs_block_dev_desc->dev, + part_info->start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf(" ** ext2fs_devread() read error **\n"); + return 0; + } + memcpy(buf, sec_buf + byte_offset, + min(SECTOR_SIZE - byte_offset, byte_len)); + buf += min(SECTOR_SIZE - byte_offset, byte_len); + byte_len -= min(SECTOR_SIZE - byte_offset, byte_len); + sector++; + } + + if (byte_len == 0) + return 1; + + /* read sector aligned part */ + block_len = byte_len & ~(SECTOR_SIZE - 1); + + if (block_len == 0) { + ALLOC_CACHE_ALIGN_BUFFER(u8, p, SECTOR_SIZE); + + block_len = SECTOR_SIZE; + ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev, + part_info->start + sector, + 1, (unsigned long *)p); + memcpy(buf, p, byte_len); + return 1; + } + + if (ext4fs_block_dev_desc->block_read(ext4fs_block_dev_desc->dev, + part_info->start + sector, + block_len / SECTOR_SIZE, + (unsigned long *) buf) != + block_len / SECTOR_SIZE) { + printf(" ** %s read error - block\n", __func__); + return 0; + } + block_len = byte_len & ~(SECTOR_SIZE - 1); + buf += block_len; + byte_len -= block_len; + sector += block_len / SECTOR_SIZE; + + if (byte_len != 0) { + /* read rest of data which are not in whole sector */ + if (ext4fs_block_dev_desc-> + block_read(ext4fs_block_dev_desc->dev, + part_info->start + sector, 1, + (unsigned long *) sec_buf) != 1) { + printf("* %s read error - last part\n", __func__); + return 0; + } + memcpy(buf, sec_buf, byte_len); + } + return 1; +} diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c new file mode 100644 index 00000000000..3deffd523e0 --- /dev/null +++ b/fs/ext4/ext4_common.c @@ -0,0 +1,2228 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * ext4ls and ext4load : Based on ext2 ls load support in Uboot. + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * ext4write : Based on generic ext4 protocol. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <ext_common.h> +#include <ext4fs.h> +#include <malloc.h> +#include <stddef.h> +#include <linux/stat.h> +#include <linux/time.h> +#include <asm/byteorder.h> +#include "ext4_common.h" + +struct ext2_data *ext4fs_root; +struct ext2fs_node *ext4fs_file; +uint32_t *ext4fs_indir1_block; +int ext4fs_indir1_size; +int ext4fs_indir1_blkno = -1; +uint32_t *ext4fs_indir2_block; +int ext4fs_indir2_size; +int ext4fs_indir2_blkno = -1; + +uint32_t *ext4fs_indir3_block; +int ext4fs_indir3_size; +int ext4fs_indir3_blkno = -1; +struct ext2_inode *g_parent_inode; +static int symlinknest; + +#if defined(CONFIG_CMD_EXT4_WRITE) +uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n) +{ + uint32_t res = size / n; + if (res * n != size) + res++; + + return res; +} + +void put_ext4(uint64_t off, void *buf, uint32_t size) +{ + uint64_t startblock; + uint64_t remainder; + unsigned char *temp_ptr = NULL; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, SECTOR_SIZE); + struct ext_filesystem *fs = get_fs(); + + startblock = off / (uint64_t)SECTOR_SIZE; + startblock += part_offset; + remainder = off % (uint64_t)SECTOR_SIZE; + remainder &= SECTOR_SIZE - 1; + + if (fs->dev_desc == NULL) + return; + + if ((startblock + (size / SECTOR_SIZE)) > + (part_offset + fs->total_sect)) { + printf("part_offset is %lu\n", part_offset); + printf("total_sector is %llu\n", fs->total_sect); + printf("error: overflow occurs\n"); + return; + } + + if (remainder) { + if (fs->dev_desc->block_read) { + fs->dev_desc->block_read(fs->dev_desc->dev, + startblock, 1, sec_buf); + temp_ptr = sec_buf; + memcpy((temp_ptr + remainder), + (unsigned char *)buf, size); + fs->dev_desc->block_write(fs->dev_desc->dev, + startblock, 1, sec_buf); + } + } else { + if (size / SECTOR_SIZE != 0) { + fs->dev_desc->block_write(fs->dev_desc->dev, + startblock, + size / SECTOR_SIZE, + (unsigned long *)buf); + } else { + fs->dev_desc->block_read(fs->dev_desc->dev, + startblock, 1, sec_buf); + temp_ptr = sec_buf; + memcpy(temp_ptr, buf, size); + fs->dev_desc->block_write(fs->dev_desc->dev, + startblock, 1, + (unsigned long *)sec_buf); + } + } +} + +static int _get_new_inode_no(unsigned char *buffer) +{ + struct ext_filesystem *fs = get_fs(); + unsigned char input; + int operand, status; + int count = 1; + int j = 0; + + /* get the blocksize of the filesystem */ + unsigned char *ptr = buffer; + while (*ptr == 255) { + ptr++; + count += 8; + if (count > ext4fs_root->sblock.inodes_per_group) + return -1; + } + + for (j = 0; j < fs->blksz; j++) { + input = *ptr; + int i = 0; + while (i <= 7) { + operand = 1 << i; + status = input & operand; + if (status) { + i++; + count++; + } else { + *ptr |= operand; + return count; + } + } + ptr = ptr + 1; + } + + return -1; +} + +static int _get_new_blk_no(unsigned char *buffer) +{ + unsigned char input; + int operand, status; + int count = 0; + int j = 0; + unsigned char *ptr = buffer; + struct ext_filesystem *fs = get_fs(); + + if (fs->blksz != 1024) + count = 0; + else + count = 1; + + while (*ptr == 255) { + ptr++; + count += 8; + if (count == (fs->blksz * 8)) + return -1; + } + + for (j = 0; j < fs->blksz; j++) { + input = *ptr; + int i = 0; + while (i <= 7) { + operand = 1 << i; + status = input & operand; + if (status) { + i++; + count++; + } else { + *ptr |= operand; + return count; + } + } + ptr = ptr + 1; + } + + return -1; +} + +int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index) +{ + int i, remainder, status; + unsigned char *ptr = buffer; + unsigned char operand; + i = blockno / 8; + remainder = blockno % 8; + int blocksize = EXT2_BLOCK_SIZE(ext4fs_root); + + i = i - (index * blocksize); + if (blocksize != 1024) { + ptr = ptr + i; + operand = 1 << remainder; + status = *ptr & operand; + if (status) + return -1; + + *ptr = *ptr | operand; + return 0; + } else { + if (remainder == 0) { + ptr = ptr + i - 1; + operand = (1 << 7); + } else { + ptr = ptr + i; + operand = (1 << (remainder - 1)); + } + status = *ptr & operand; + if (status) + return -1; + + *ptr = *ptr | operand; + return 0; + } +} + +void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, int index) +{ + int i, remainder, status; + unsigned char *ptr = buffer; + unsigned char operand; + i = blockno / 8; + remainder = blockno % 8; + int blocksize = EXT2_BLOCK_SIZE(ext4fs_root); + + i = i - (index * blocksize); + if (blocksize != 1024) { + ptr = ptr + i; + operand = (1 << remainder); + status = *ptr & operand; + if (status) + *ptr = *ptr & ~(operand); + } else { + if (remainder == 0) { + ptr = ptr + i - 1; + operand = (1 << 7); + } else { + ptr = ptr + i; + operand = (1 << (remainder - 1)); + } + status = *ptr & operand; + if (status) + *ptr = *ptr & ~(operand); + } +} + +int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index) +{ + int i, remainder, status; + unsigned char *ptr = buffer; + unsigned char operand; + + inode_no -= (index * ext4fs_root->sblock.inodes_per_group); + i = inode_no / 8; + remainder = inode_no % 8; + if (remainder == 0) { + ptr = ptr + i - 1; + operand = (1 << 7); + } else { + ptr = ptr + i; + operand = (1 << (remainder - 1)); + } + status = *ptr & operand; + if (status) + return -1; + + *ptr = *ptr | operand; + + return 0; +} + +void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index) +{ + int i, remainder, status; + unsigned char *ptr = buffer; + unsigned char operand; + + inode_no -= (index * ext4fs_root->sblock.inodes_per_group); + i = inode_no / 8; + remainder = inode_no % 8; + if (remainder == 0) { + ptr = ptr + i - 1; + operand = (1 << 7); + } else { + ptr = ptr + i; + operand = (1 << (remainder - 1)); + } + status = *ptr & operand; + if (status) + *ptr = *ptr & ~(operand); +} + +int ext4fs_checksum_update(unsigned int i) +{ + struct ext2_block_group *desc; + struct ext_filesystem *fs = get_fs(); + __u16 crc = 0; + + desc = (struct ext2_block_group *)&fs->gd[i]; + if (fs->sb->feature_ro_compat & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) { + int offset = offsetof(struct ext2_block_group, bg_checksum); + + crc = ext2fs_crc16(~0, fs->sb->unique_id, + sizeof(fs->sb->unique_id)); + crc = ext2fs_crc16(crc, &i, sizeof(i)); + crc = ext2fs_crc16(crc, desc, offset); + offset += sizeof(desc->bg_checksum); /* skip checksum */ + assert(offset == sizeof(*desc)); + } + + return crc; +} + +static int check_void_in_dentry(struct ext2_dirent *dir, char *filename) +{ + int dentry_length; + int sizeof_void_space; + int new_entry_byte_reqd; + short padding_factor = 0; + + if (dir->namelen % 4 != 0) + padding_factor = 4 - (dir->namelen % 4); + + dentry_length = sizeof(struct ext2_dirent) + + dir->namelen + padding_factor; + sizeof_void_space = dir->direntlen - dentry_length; + if (sizeof_void_space == 0) + return 0; + + padding_factor = 0; + if (strlen(filename) % 4 != 0) + padding_factor = 4 - (strlen(filename) % 4); + + new_entry_byte_reqd = strlen(filename) + + sizeof(struct ext2_dirent) + padding_factor; + if (sizeof_void_space >= new_entry_byte_reqd) { + dir->direntlen = dentry_length; + return sizeof_void_space; + } + + return 0; +} + +void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type) +{ + unsigned int *zero_buffer = NULL; + char *root_first_block_buffer = NULL; + int direct_blk_idx; + long int root_blknr; + long int first_block_no_of_root = 0; + long int previous_blknr = -1; + int totalbytes = 0; + short int padding_factor = 0; + unsigned int new_entry_byte_reqd; + unsigned int last_entry_dirlen; + int sizeof_void_space = 0; + int templength = 0; + int inodeno; + int status; + struct ext_filesystem *fs = get_fs(); + /* directory entry */ + struct ext2_dirent *dir; + char *ptr = NULL; + char *temp_dir = NULL; + + zero_buffer = zalloc(fs->blksz); + if (!zero_buffer) { + printf("No Memory\n"); + return; + } + root_first_block_buffer = zalloc(fs->blksz); + if (!root_first_block_buffer) { + free(zero_buffer); + printf("No Memory\n"); + return; + } +restart: + + /* read the block no allocated to a file */ + for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; + direct_blk_idx++) { + root_blknr = read_allocated_block(g_parent_inode, + direct_blk_idx); + if (root_blknr == 0) { + first_block_no_of_root = previous_blknr; + break; + } + previous_blknr = root_blknr; + } + + status = ext4fs_devread(first_block_no_of_root + * fs->sect_perblk, + 0, fs->blksz, root_first_block_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root)) + goto fail; + dir = (struct ext2_dirent *)root_first_block_buffer; + ptr = (char *)dir; + totalbytes = 0; + while (dir->direntlen > 0) { + /* + * blocksize-totalbytes because last directory length + * i.e. dir->direntlen is free availble space in the + * block that means it is a last entry of directory + * entry + */ + + /* traversing the each directory entry */ + if (fs->blksz - totalbytes == dir->direntlen) { + if (strlen(filename) % 4 != 0) + padding_factor = 4 - (strlen(filename) % 4); + + new_entry_byte_reqd = strlen(filename) + + sizeof(struct ext2_dirent) + padding_factor; + padding_factor = 0; + /* + * update last directory entry length to its + * length because we are creating new directory + * entry + */ + if (dir->namelen % 4 != 0) + padding_factor = 4 - (dir->namelen % 4); + + last_entry_dirlen = dir->namelen + + sizeof(struct ext2_dirent) + padding_factor; + if ((fs->blksz - totalbytes - last_entry_dirlen) < + new_entry_byte_reqd) { + printf("1st Block Full:Allocate new block\n"); + + if (direct_blk_idx == INDIRECT_BLOCKS - 1) { + printf("Directory exceeds limit\n"); + goto fail; + } + g_parent_inode->b.blocks.dir_blocks + [direct_blk_idx] = ext4fs_get_new_blk_no(); + if (g_parent_inode->b.blocks.dir_blocks + [direct_blk_idx] == -1) { + printf("no block left to assign\n"); + goto fail; + } + put_ext4(((uint64_t) + (g_parent_inode->b. + blocks.dir_blocks[direct_blk_idx] * + fs->blksz)), zero_buffer, fs->blksz); + g_parent_inode->size = + g_parent_inode->size + fs->blksz; + g_parent_inode->blockcnt = + g_parent_inode->blockcnt + fs->sect_perblk; + if (ext4fs_put_metadata + (root_first_block_buffer, + first_block_no_of_root)) + goto fail; + goto restart; + } + dir->direntlen = last_entry_dirlen; + break; + } + + templength = dir->direntlen; + totalbytes = totalbytes + templength; + sizeof_void_space = check_void_in_dentry(dir, filename); + if (sizeof_void_space) + break; + + dir = (struct ext2_dirent *)((char *)dir + templength); + ptr = (char *)dir; + } + + /* make a pointer ready for creating next directory entry */ + templength = dir->direntlen; + totalbytes = totalbytes + templength; + dir = (struct ext2_dirent *)((char *)dir + templength); + ptr = (char *)dir; + + /* get the next available inode number */ + inodeno = ext4fs_get_new_inode_no(); + if (inodeno == -1) { + printf("no inode left to assign\n"); + goto fail; + } + dir->inode = inodeno; + if (sizeof_void_space) + dir->direntlen = sizeof_void_space; + else + dir->direntlen = fs->blksz - totalbytes; + + dir->namelen = strlen(filename); + dir->filetype = FILETYPE_REG; /* regular file */ + temp_dir = (char *)dir; + temp_dir = temp_dir + sizeof(struct ext2_dirent); + memcpy(temp_dir, filename, strlen(filename)); + + *p_ino = inodeno; + + /* update or write the 1st block of root inode */ + if (ext4fs_put_metadata(root_first_block_buffer, + first_block_no_of_root)) + goto fail; + +fail: + free(zero_buffer); + free(root_first_block_buffer); +} + +static int search_dir(struct ext2_inode *parent_inode, char *dirname) +{ + int status; + int inodeno; + int totalbytes; + int templength; + int direct_blk_idx; + long int blknr; + int found = 0; + char *ptr = NULL; + unsigned char *block_buffer = NULL; + struct ext2_dirent *dir = NULL; + struct ext2_dirent *previous_dir = NULL; + struct ext_filesystem *fs = get_fs(); + + /* read the block no allocated to a file */ + for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; + direct_blk_idx++) { + blknr = read_allocated_block(parent_inode, direct_blk_idx); + if (blknr == 0) + goto fail; + + /* read the blocks of parenet inode */ + block_buffer = zalloc(fs->blksz); + if (!block_buffer) + goto fail; + + status = ext4fs_devread(blknr * fs->sect_perblk, + 0, fs->blksz, (char *)block_buffer); + if (status == 0) + goto fail; + + dir = (struct ext2_dirent *)block_buffer; + ptr = (char *)dir; + totalbytes = 0; + while (dir->direntlen >= 0) { + /* + * blocksize-totalbytes because last directory + * length i.e.,*dir->direntlen is free availble + * space in the block that means + * it is a last entry of directory entry + */ + if (strlen(dirname) == dir->namelen) { + if (strncmp(dirname, ptr + + sizeof(struct ext2_dirent), + dir->namelen) == 0) { + previous_dir->direntlen += + dir->direntlen; + inodeno = dir->inode; + dir->inode = 0; + found = 1; + break; + } + } + + if (fs->blksz - totalbytes == dir->direntlen) + break; + + /* traversing the each directory entry */ + templength = dir->direntlen; + totalbytes = totalbytes + templength; + previous_dir = dir; + dir = (struct ext2_dirent *)((char *)dir + templength); + ptr = (char *)dir; + } + + if (found == 1) { + free(block_buffer); + block_buffer = NULL; + return inodeno; + } + + free(block_buffer); + block_buffer = NULL; + } + +fail: + free(block_buffer); + + return -1; +} + +static int find_dir_depth(char *dirname) +{ + char *token = strtok(dirname, "/"); + int count = 0; + while (token != NULL) { + token = strtok(NULL, "/"); + count++; + } + return count + 1 + 1; + /* + * for example for string /home/temp + * depth=home(1)+temp(1)+1 extra for NULL; + * so count is 4; + */ +} + +static int parse_path(char **arr, char *dirname) +{ + char *token = strtok(dirname, "/"); + int i = 0; + + /* add root */ + arr[i] = zalloc(strlen("/") + 1); + if (!arr[i]) + return -ENOMEM; + + arr[i++] = "/"; + + /* add each path entry after root */ + while (token != NULL) { + arr[i] = zalloc(strlen(token) + 1); + if (!arr[i]) + return -ENOMEM; + memcpy(arr[i++], token, strlen(token)); + token = strtok(NULL, "/"); + } + arr[i] = NULL; + + return 0; +} + +int ext4fs_iget(int inode_no, struct ext2_inode *inode) +{ + if (ext4fs_read_inode(ext4fs_root, inode_no, inode) == 0) + return -1; + + return 0; +} + +/* + * Function: ext4fs_get_parent_inode_num + * Return Value: inode Number of the parent directory of file/Directory to be + * created + * dirname : Input parmater, input path name of the file/directory to be created + * dname : Output parameter, to be filled with the name of the directory + * extracted from dirname + */ +int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags) +{ + int i; + int depth = 0; + int matched_inode_no; + int result_inode_no = -1; + char **ptr = NULL; + char *depth_dirname = NULL; + char *parse_dirname = NULL; + struct ext2_inode *parent_inode = NULL; + struct ext2_inode *first_inode = NULL; + struct ext2_inode temp_inode; + + if (*dirname != '/') { + printf("Please supply Absolute path\n"); + return -1; + } + + /* TODO: input validation make equivalent to linux */ + depth_dirname = zalloc(strlen(dirname) + 1); + if (!depth_dirname) + return -ENOMEM; + + memcpy(depth_dirname, dirname, strlen(dirname)); + depth = find_dir_depth(depth_dirname); + parse_dirname = zalloc(strlen(dirname) + 1); + if (!parse_dirname) + goto fail; + memcpy(parse_dirname, dirname, strlen(dirname)); + + /* allocate memory for each directory level */ + ptr = zalloc((depth) * sizeof(char *)); + if (!ptr) + goto fail; + if (parse_path(ptr, parse_dirname)) + goto fail; + parent_inode = zalloc(sizeof(struct ext2_inode)); + if (!parent_inode) + goto fail; + first_inode = zalloc(sizeof(struct ext2_inode)); + if (!first_inode) + goto fail; + memcpy(parent_inode, ext4fs_root->inode, sizeof(struct ext2_inode)); + memcpy(first_inode, parent_inode, sizeof(struct ext2_inode)); + if (flags & F_FILE) + result_inode_no = EXT2_ROOT_INO; + for (i = 1; i < depth; i++) { + matched_inode_no = search_dir(parent_inode, ptr[i]); + if (matched_inode_no == -1) { + if (ptr[i + 1] == NULL && i == 1) { + result_inode_no = EXT2_ROOT_INO; + goto end; + } else { + if (ptr[i + 1] == NULL) + break; + printf("Invalid path\n"); + result_inode_no = -1; + goto fail; + } + } else { + if (ptr[i + 1] != NULL) { + memset(parent_inode, '\0', + sizeof(struct ext2_inode)); + if (ext4fs_iget(matched_inode_no, + parent_inode)) { + result_inode_no = -1; + goto fail; + } + result_inode_no = matched_inode_no; + } else { + break; + } + } + } + +end: + if (i == 1) + matched_inode_no = search_dir(first_inode, ptr[i]); + else + matched_inode_no = search_dir(parent_inode, ptr[i]); + + if (matched_inode_no != -1) { + ext4fs_iget(matched_inode_no, &temp_inode); + if (temp_inode.mode & S_IFDIR) { + printf("It is a Directory\n"); + result_inode_no = -1; + goto fail; + } + } + + if (strlen(ptr[i]) > 256) { + result_inode_no = -1; + goto fail; + } + memcpy(dname, ptr[i], strlen(ptr[i])); + +fail: + free(depth_dirname); + free(parse_dirname); + free(ptr); + free(parent_inode); + free(first_inode); + + return result_inode_no; +} + +static int check_filename(char *filename, unsigned int blknr) +{ + unsigned int first_block_no_of_root; + int totalbytes = 0; + int templength = 0; + int status, inodeno; + int found = 0; + char *root_first_block_buffer = NULL; + char *root_first_block_addr = NULL; + struct ext2_dirent *dir = NULL; + struct ext2_dirent *previous_dir = NULL; + char *ptr = NULL; + struct ext_filesystem *fs = get_fs(); + + /* get the first block of root */ + first_block_no_of_root = blknr; + root_first_block_buffer = zalloc(fs->blksz); + if (!root_first_block_buffer) + return -ENOMEM; + root_first_block_addr = root_first_block_buffer; + status = ext4fs_devread(first_block_no_of_root * + fs->sect_perblk, 0, + fs->blksz, root_first_block_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root)) + goto fail; + dir = (struct ext2_dirent *)root_first_block_buffer; + ptr = (char *)dir; + totalbytes = 0; + while (dir->direntlen >= 0) { + /* + * blocksize-totalbytes because last + * directory length i.e., *dir->direntlen + * is free availble space in the block that + * means it is a last entry of directory entry + */ + if (strlen(filename) == dir->namelen) { + if (strncmp(filename, ptr + sizeof(struct ext2_dirent), + dir->namelen) == 0) { + printf("file found deleting\n"); + previous_dir->direntlen += dir->direntlen; + inodeno = dir->inode; + dir->inode = 0; + found = 1; + break; + } + } + + if (fs->blksz - totalbytes == dir->direntlen) + break; + + /* traversing the each directory entry */ + templength = dir->direntlen; + totalbytes = totalbytes + templength; + previous_dir = dir; + dir = (struct ext2_dirent *)((char *)dir + templength); + ptr = (char *)dir; + } + + + if (found == 1) { + if (ext4fs_put_metadata(root_first_block_addr, + first_block_no_of_root)) + goto fail; + return inodeno; + } +fail: + free(root_first_block_buffer); + + return -1; +} + +int ext4fs_filename_check(char *filename) +{ + short direct_blk_idx = 0; + long int blknr = -1; + int inodeno = -1; + + /* read the block no allocated to a file */ + for (direct_blk_idx = 0; direct_blk_idx < INDIRECT_BLOCKS; + direct_blk_idx++) { + blknr = read_allocated_block(g_parent_inode, direct_blk_idx); + if (blknr == 0) + break; + inodeno = check_filename(filename, blknr); + if (inodeno != -1) + return inodeno; + } + + return -1; +} + +long int ext4fs_get_new_blk_no(void) +{ + short i; + short status; + int remainder; + unsigned int bg_idx; + static int prev_bg_bitmap_index = -1; + unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + char *zero_buffer = zalloc(fs->blksz); + if (!journal_buffer || !zero_buffer) + goto fail; + struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable; + + if (fs->first_pass_bbmap == 0) { + for (i = 0; i < fs->no_blkgrp; i++) { + if (gd[i].free_blocks) { + if (gd[i].bg_flags & EXT4_BG_BLOCK_UNINIT) { + put_ext4(((uint64_t) (gd[i].block_id * + fs->blksz)), + zero_buffer, fs->blksz); + gd[i].bg_flags = + gd[i]. + bg_flags & ~EXT4_BG_BLOCK_UNINIT; + memcpy(fs->blk_bmaps[i], zero_buffer, + fs->blksz); + } + fs->curr_blkno = + _get_new_blk_no(fs->blk_bmaps[i]); + if (fs->curr_blkno == -1) + /* if block bitmap is completely fill */ + continue; + fs->curr_blkno = fs->curr_blkno + + (i * fs->blksz * 8); + fs->first_pass_bbmap++; + gd[i].free_blocks--; + fs->sb->free_blocks--; + status = ext4fs_devread(gd[i].block_id * + fs->sect_perblk, 0, + fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[i].block_id)) + goto fail; + goto success; + } else { + debug("no space left on block group %d\n", i); + } + } + + goto fail; + } else { +restart: + fs->curr_blkno++; + /* get the blockbitmap index respective to blockno */ + if (fs->blksz != 1024) { + bg_idx = fs->curr_blkno / blk_per_grp; + } else { + bg_idx = fs->curr_blkno / blk_per_grp; + remainder = fs->curr_blkno % blk_per_grp; + if (!remainder) + bg_idx--; + } + + /* + * To skip completely filled block group bitmaps + * Optimize the block allocation + */ + if (bg_idx >= fs->no_blkgrp) + goto fail; + + if (gd[bg_idx].free_blocks == 0) { + debug("block group %u is full. Skipping\n", bg_idx); + fs->curr_blkno = fs->curr_blkno + blk_per_grp; + fs->curr_blkno--; + goto restart; + } + + if (gd[bg_idx].bg_flags & EXT4_BG_BLOCK_UNINIT) { + memset(zero_buffer, '\0', fs->blksz); + put_ext4(((uint64_t) (gd[bg_idx].block_id * fs->blksz)), + zero_buffer, fs->blksz); + memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz); + gd[bg_idx].bg_flags = gd[bg_idx].bg_flags & + ~EXT4_BG_BLOCK_UNINIT; + } + + if (ext4fs_set_block_bmap(fs->curr_blkno, fs->blk_bmaps[bg_idx], + bg_idx) != 0) { + debug("going for restart for the block no %ld %u\n", + fs->curr_blkno, bg_idx); + goto restart; + } + + /* journal backup */ + if (prev_bg_bitmap_index != bg_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[bg_idx].block_id + * fs->sect_perblk, + 0, fs->blksz, journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + + prev_bg_bitmap_index = bg_idx; + } + gd[bg_idx].free_blocks--; + fs->sb->free_blocks--; + goto success; + } +success: + free(journal_buffer); + free(zero_buffer); + + return fs->curr_blkno; +fail: + free(journal_buffer); + free(zero_buffer); + + return -1; +} + +int ext4fs_get_new_inode_no(void) +{ + short i; + short status; + unsigned int ibmap_idx; + static int prev_inode_bitmap_index = -1; + unsigned int inodes_per_grp = ext4fs_root->sblock.inodes_per_group; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + char *zero_buffer = zalloc(fs->blksz); + if (!journal_buffer || !zero_buffer) + goto fail; + struct ext2_block_group *gd = (struct ext2_block_group *)fs->gdtable; + + if (fs->first_pass_ibmap == 0) { + for (i = 0; i < fs->no_blkgrp; i++) { + if (gd[i].free_inodes) { + if (gd[i].bg_itable_unused != gd[i].free_inodes) + gd[i].bg_itable_unused = + gd[i].free_inodes; + if (gd[i].bg_flags & EXT4_BG_INODE_UNINIT) { + put_ext4(((uint64_t) + (gd[i].inode_id * fs->blksz)), + zero_buffer, fs->blksz); + gd[i].bg_flags = gd[i].bg_flags & + ~EXT4_BG_INODE_UNINIT; + memcpy(fs->inode_bmaps[i], + zero_buffer, fs->blksz); + } + fs->curr_inode_no = + _get_new_inode_no(fs->inode_bmaps[i]); + if (fs->curr_inode_no == -1) + /* if block bitmap is completely fill */ + continue; + fs->curr_inode_no = fs->curr_inode_no + + (i * inodes_per_grp); + fs->first_pass_ibmap++; + gd[i].free_inodes--; + gd[i].bg_itable_unused--; + fs->sb->free_inodes--; + status = ext4fs_devread(gd[i].inode_id * + fs->sect_perblk, 0, + fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[i].inode_id)) + goto fail; + goto success; + } else + debug("no inode left on block group %d\n", i); + } + goto fail; + } else { +restart: + fs->curr_inode_no++; + /* get the blockbitmap index respective to blockno */ + ibmap_idx = fs->curr_inode_no / inodes_per_grp; + if (gd[ibmap_idx].bg_flags & EXT4_BG_INODE_UNINIT) { + memset(zero_buffer, '\0', fs->blksz); + put_ext4(((uint64_t) (gd[ibmap_idx].inode_id * + fs->blksz)), zero_buffer, + fs->blksz); + gd[ibmap_idx].bg_flags = + gd[ibmap_idx].bg_flags & ~EXT4_BG_INODE_UNINIT; + memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer, + fs->blksz); + } + + if (ext4fs_set_inode_bmap(fs->curr_inode_no, + fs->inode_bmaps[ibmap_idx], + ibmap_idx) != 0) { + debug("going for restart for the block no %d %u\n", + fs->curr_inode_no, ibmap_idx); + goto restart; + } + + /* journal backup */ + if (prev_inode_bitmap_index != ibmap_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[ibmap_idx].inode_id + * fs->sect_perblk, + 0, fs->blksz, journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[ibmap_idx].inode_id)) + goto fail; + prev_inode_bitmap_index = ibmap_idx; + } + if (gd[ibmap_idx].bg_itable_unused != gd[ibmap_idx].free_inodes) + gd[ibmap_idx].bg_itable_unused = + gd[ibmap_idx].free_inodes; + gd[ibmap_idx].free_inodes--; + gd[ibmap_idx].bg_itable_unused--; + fs->sb->free_inodes--; + goto success; + } + +success: + free(journal_buffer); + free(zero_buffer); + + return fs->curr_inode_no; +fail: + free(journal_buffer); + free(zero_buffer); + + return -1; + +} + + +static void alloc_single_indirect_block(struct ext2_inode *file_inode, + unsigned int *total_remaining_blocks, + unsigned int *no_blks_reqd) +{ + short i; + short status; + long int actual_block_no; + long int si_blockno; + /* si :single indirect */ + unsigned int *si_buffer = NULL; + unsigned int *si_start_addr = NULL; + struct ext_filesystem *fs = get_fs(); + + if (*total_remaining_blocks != 0) { + si_buffer = zalloc(fs->blksz); + if (!si_buffer) { + printf("No Memory\n"); + return; + } + si_start_addr = si_buffer; + si_blockno = ext4fs_get_new_blk_no(); + if (si_blockno == -1) { + printf("no block left to assign\n"); + goto fail; + } + (*no_blks_reqd)++; + debug("SIPB %ld: %u\n", si_blockno, *total_remaining_blocks); + + status = ext4fs_devread(si_blockno * fs->sect_perblk, + 0, fs->blksz, (char *)si_buffer); + memset(si_buffer, '\0', fs->blksz); + if (status == 0) + goto fail; + + for (i = 0; i < (fs->blksz / sizeof(int)); i++) { + actual_block_no = ext4fs_get_new_blk_no(); + if (actual_block_no == -1) { + printf("no block left to assign\n"); + goto fail; + } + *si_buffer = actual_block_no; + debug("SIAB %u: %u\n", *si_buffer, + *total_remaining_blocks); + + si_buffer++; + (*total_remaining_blocks)--; + if (*total_remaining_blocks == 0) + break; + } + + /* write the block to disk */ + put_ext4(((uint64_t) (si_blockno * fs->blksz)), + si_start_addr, fs->blksz); + file_inode->b.blocks.indir_block = si_blockno; + } +fail: + free(si_start_addr); +} + +static void alloc_double_indirect_block(struct ext2_inode *file_inode, + unsigned int *total_remaining_blocks, + unsigned int *no_blks_reqd) +{ + short i; + short j; + short status; + long int actual_block_no; + /* di:double indirect */ + long int di_blockno_parent; + long int di_blockno_child; + unsigned int *di_parent_buffer = NULL; + unsigned int *di_child_buff = NULL; + unsigned int *di_block_start_addr = NULL; + unsigned int *di_child_buff_start = NULL; + struct ext_filesystem *fs = get_fs(); + + if (*total_remaining_blocks != 0) { + /* double indirect parent block connecting to inode */ + di_blockno_parent = ext4fs_get_new_blk_no(); + if (di_blockno_parent == -1) { + printf("no block left to assign\n"); + goto fail; + } + di_parent_buffer = zalloc(fs->blksz); + if (!di_parent_buffer) + goto fail; + + di_block_start_addr = di_parent_buffer; + (*no_blks_reqd)++; + debug("DIPB %ld: %u\n", di_blockno_parent, + *total_remaining_blocks); + + status = ext4fs_devread(di_blockno_parent * + fs->sect_perblk, 0, + fs->blksz, (char *)di_parent_buffer); + memset(di_parent_buffer, '\0', fs->blksz); + + /* + * start:for each double indirect parent + * block create one more block + */ + for (i = 0; i < (fs->blksz / sizeof(int)); i++) { + di_blockno_child = ext4fs_get_new_blk_no(); + if (di_blockno_child == -1) { + printf("no block left to assign\n"); + goto fail; + } + di_child_buff = zalloc(fs->blksz); + if (!di_child_buff) + goto fail; + + di_child_buff_start = di_child_buff; + *di_parent_buffer = di_blockno_child; + di_parent_buffer++; + (*no_blks_reqd)++; + debug("DICB %ld: %u\n", di_blockno_child, + *total_remaining_blocks); + + status = ext4fs_devread(di_blockno_child * + fs->sect_perblk, 0, + fs->blksz, + (char *)di_child_buff); + memset(di_child_buff, '\0', fs->blksz); + /* filling of actual datablocks for each child */ + for (j = 0; j < (fs->blksz / sizeof(int)); j++) { + actual_block_no = ext4fs_get_new_blk_no(); + if (actual_block_no == -1) { + printf("no block left to assign\n"); + goto fail; + } + *di_child_buff = actual_block_no; + debug("DIAB %ld: %u\n", actual_block_no, + *total_remaining_blocks); + + di_child_buff++; + (*total_remaining_blocks)--; + if (*total_remaining_blocks == 0) + break; + } + /* write the block table */ + put_ext4(((uint64_t) (di_blockno_child * fs->blksz)), + di_child_buff_start, fs->blksz); + free(di_child_buff_start); + di_child_buff_start = NULL; + + if (*total_remaining_blocks == 0) + break; + } + put_ext4(((uint64_t) (di_blockno_parent * fs->blksz)), + di_block_start_addr, fs->blksz); + file_inode->b.blocks.double_indir_block = di_blockno_parent; + } +fail: + free(di_block_start_addr); +} + +static void alloc_triple_indirect_block(struct ext2_inode *file_inode, + unsigned int *total_remaining_blocks, + unsigned int *no_blks_reqd) +{ + short i; + short j; + short k; + long int actual_block_no; + /* ti: Triple Indirect */ + long int ti_gp_blockno; + long int ti_parent_blockno; + long int ti_child_blockno; + unsigned int *ti_gp_buff = NULL; + unsigned int *ti_parent_buff = NULL; + unsigned int *ti_child_buff = NULL; + unsigned int *ti_gp_buff_start_addr = NULL; + unsigned int *ti_pbuff_start_addr = NULL; + unsigned int *ti_cbuff_start_addr = NULL; + struct ext_filesystem *fs = get_fs(); + if (*total_remaining_blocks != 0) { + /* triple indirect grand parent block connecting to inode */ + ti_gp_blockno = ext4fs_get_new_blk_no(); + if (ti_gp_blockno == -1) { + printf("no block left to assign\n"); + goto fail; + } + ti_gp_buff = zalloc(fs->blksz); + if (!ti_gp_buff) + goto fail; + + ti_gp_buff_start_addr = ti_gp_buff; + (*no_blks_reqd)++; + debug("TIGPB %ld: %u\n", ti_gp_blockno, + *total_remaining_blocks); + + /* for each 4 byte grand parent entry create one more block */ + for (i = 0; i < (fs->blksz / sizeof(int)); i++) { + ti_parent_blockno = ext4fs_get_new_blk_no(); + if (ti_parent_blockno == -1) { + printf("no block left to assign\n"); + goto fail; + } + ti_parent_buff = zalloc(fs->blksz); + if (!ti_parent_buff) + goto fail; + + ti_pbuff_start_addr = ti_parent_buff; + *ti_gp_buff = ti_parent_blockno; + ti_gp_buff++; + (*no_blks_reqd)++; + debug("TIPB %ld: %u\n", ti_parent_blockno, + *total_remaining_blocks); + + /* for each 4 byte entry parent create one more block */ + for (j = 0; j < (fs->blksz / sizeof(int)); j++) { + ti_child_blockno = ext4fs_get_new_blk_no(); + if (ti_child_blockno == -1) { + printf("no block left assign\n"); + goto fail; + } + ti_child_buff = zalloc(fs->blksz); + if (!ti_child_buff) + goto fail; + + ti_cbuff_start_addr = ti_child_buff; + *ti_parent_buff = ti_child_blockno; + ti_parent_buff++; + (*no_blks_reqd)++; + debug("TICB %ld: %u\n", ti_parent_blockno, + *total_remaining_blocks); + + /* fill actual datablocks for each child */ + for (k = 0; k < (fs->blksz / sizeof(int)); + k++) { + actual_block_no = + ext4fs_get_new_blk_no(); + if (actual_block_no == -1) { + printf("no block left\n"); + goto fail; + } + *ti_child_buff = actual_block_no; + debug("TIAB %ld: %u\n", actual_block_no, + *total_remaining_blocks); + + ti_child_buff++; + (*total_remaining_blocks)--; + if (*total_remaining_blocks == 0) + break; + } + /* write the child block */ + put_ext4(((uint64_t) (ti_child_blockno * + fs->blksz)), + ti_cbuff_start_addr, fs->blksz); + free(ti_cbuff_start_addr); + + if (*total_remaining_blocks == 0) + break; + } + /* write the parent block */ + put_ext4(((uint64_t) (ti_parent_blockno * fs->blksz)), + ti_pbuff_start_addr, fs->blksz); + free(ti_pbuff_start_addr); + + if (*total_remaining_blocks == 0) + break; + } + /* write the grand parent block */ + put_ext4(((uint64_t) (ti_gp_blockno * fs->blksz)), + ti_gp_buff_start_addr, fs->blksz); + file_inode->b.blocks.triple_indir_block = ti_gp_blockno; + } +fail: + free(ti_gp_buff_start_addr); +} + +void ext4fs_allocate_blocks(struct ext2_inode *file_inode, + unsigned int total_remaining_blocks, + unsigned int *total_no_of_block) +{ + short i; + long int direct_blockno; + unsigned int no_blks_reqd = 0; + + /* allocation of direct blocks */ + for (i = 0; i < INDIRECT_BLOCKS; i++) { + direct_blockno = ext4fs_get_new_blk_no(); + if (direct_blockno == -1) { + printf("no block left to assign\n"); + return; + } + file_inode->b.blocks.dir_blocks[i] = direct_blockno; + debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks); + + total_remaining_blocks--; + if (total_remaining_blocks == 0) + break; + } + + alloc_single_indirect_block(file_inode, &total_remaining_blocks, + &no_blks_reqd); + alloc_double_indirect_block(file_inode, &total_remaining_blocks, + &no_blks_reqd); + alloc_triple_indirect_block(file_inode, &total_remaining_blocks, + &no_blks_reqd); + *total_no_of_block += no_blks_reqd; +} + +#endif + +static struct ext4_extent_header *ext4fs_get_extent_block + (struct ext2_data *data, char *buf, + struct ext4_extent_header *ext_block, + uint32_t fileblock, int log2_blksz) +{ + struct ext4_extent_idx *index; + unsigned long long block; + struct ext_filesystem *fs = get_fs(); + int i; + + while (1) { + index = (struct ext4_extent_idx *)(ext_block + 1); + + if (le32_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC) + return 0; + + if (ext_block->eh_depth == 0) + return ext_block; + i = -1; + do { + i++; + if (i >= le32_to_cpu(ext_block->eh_entries)) + break; + } while (fileblock > le32_to_cpu(index[i].ei_block)); + + if (--i < 0) + return 0; + + block = le32_to_cpu(index[i].ei_leaf_hi); + block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo); + + if (ext4fs_devread(block << log2_blksz, 0, fs->blksz, buf)) + ext_block = (struct ext4_extent_header *)buf; + else + return 0; + } +} + +static int ext4fs_blockgroup + (struct ext2_data *data, int group, struct ext2_block_group *blkgrp) +{ + long int blkno; + unsigned int blkoff, desc_per_blk; + + desc_per_blk = EXT2_BLOCK_SIZE(data) / sizeof(struct ext2_block_group); + + blkno = __le32_to_cpu(data->sblock.first_data_block) + 1 + + group / desc_per_blk; + blkoff = (group % desc_per_blk) * sizeof(struct ext2_block_group); + + debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n", + group, blkno, blkoff); + + return ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data), + blkoff, sizeof(struct ext2_block_group), + (char *)blkgrp); +} + +int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode) +{ + struct ext2_block_group blkgrp; + struct ext2_sblock *sblock = &data->sblock; + struct ext_filesystem *fs = get_fs(); + int inodes_per_block, status; + long int blkno; + unsigned int blkoff; + + /* It is easier to calculate if the first inode is 0. */ + ino--; + status = ext4fs_blockgroup(data, ino / __le32_to_cpu + (sblock->inodes_per_group), &blkgrp); + if (status == 0) + return 0; + + inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz; + blkno = __le32_to_cpu(blkgrp.inode_table_id) + + (ino % __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; + blkoff = (ino % inodes_per_block) * fs->inodesz; + /* Read the inode. */ + status = ext4fs_devread(blkno << LOG2_EXT2_BLOCK_SIZE(data), blkoff, + sizeof(struct ext2_inode), (char *)inode); + if (status == 0) + return 0; + + return 1; +} + +long int read_allocated_block(struct ext2_inode *inode, int fileblock) +{ + long int blknr; + int blksz; + int log2_blksz; + int status; + long int rblock; + long int perblock_parent; + long int perblock_child; + unsigned long long start; + /* get the blocksize of the filesystem */ + blksz = EXT2_BLOCK_SIZE(ext4fs_root); + log2_blksz = LOG2_EXT2_BLOCK_SIZE(ext4fs_root); + if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) { + char *buf = zalloc(blksz); + if (!buf) + return -ENOMEM; + struct ext4_extent_header *ext_block; + struct ext4_extent *extent; + int i = -1; + ext_block = ext4fs_get_extent_block(ext4fs_root, buf, + (struct ext4_extent_header + *)inode->b. + blocks.dir_blocks, + fileblock, log2_blksz); + if (!ext_block) { + printf("invalid extent block\n"); + free(buf); + return -EINVAL; + } + + extent = (struct ext4_extent *)(ext_block + 1); + + do { + i++; + if (i >= le32_to_cpu(ext_block->eh_entries)) + break; + } while (fileblock >= le32_to_cpu(extent[i].ee_block)); + if (--i >= 0) { + fileblock -= le32_to_cpu(extent[i].ee_block); + if (fileblock >= le32_to_cpu(extent[i].ee_len)) { + free(buf); + return 0; + } + + start = le32_to_cpu(extent[i].ee_start_hi); + start = (start << 32) + + le32_to_cpu(extent[i].ee_start_lo); + free(buf); + return fileblock + start; + } + + printf("Extent Error\n"); + free(buf); + return -1; + } + + /* Direct blocks. */ + if (fileblock < INDIRECT_BLOCKS) + blknr = __le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]); + + /* Indirect. */ + else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { + if (ext4fs_indir1_block == NULL) { + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** SI ext2fs read block (indir 1)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + ext4fs_indir1_blkno = -1; + } + if (blksz != ext4fs_indir1_size) { + free(ext4fs_indir1_block); + ext4fs_indir1_block = NULL; + ext4fs_indir1_size = 0; + ext4fs_indir1_blkno = -1; + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** SI ext2fs read block (indir 1):" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + } + if ((__le32_to_cpu(inode->b.blocks.indir_block) << + log2_blksz) != ext4fs_indir1_blkno) { + status = + ext4fs_devread(__le32_to_cpu + (inode->b.blocks. + indir_block) << log2_blksz, 0, + blksz, (char *)ext4fs_indir1_block); + if (status == 0) { + printf("** SI ext2fs read block (indir 1)" + "failed. **\n"); + return 0; + } + ext4fs_indir1_blkno = + __le32_to_cpu(inode->b.blocks. + indir_block) << log2_blksz; + } + blknr = __le32_to_cpu(ext4fs_indir1_block + [fileblock - INDIRECT_BLOCKS]); + } + /* Double indirect. */ + else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4 * + (blksz / 4 + 1)))) { + + long int perblock = blksz / 4; + long int rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4); + + if (ext4fs_indir1_block == NULL) { + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** DI ext2fs read block (indir 2 1)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + ext4fs_indir1_blkno = -1; + } + if (blksz != ext4fs_indir1_size) { + free(ext4fs_indir1_block); + ext4fs_indir1_block = NULL; + ext4fs_indir1_size = 0; + ext4fs_indir1_blkno = -1; + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** DI ext2fs read block (indir 2 1)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + } + if ((__le32_to_cpu(inode->b.blocks.double_indir_block) << + log2_blksz) != ext4fs_indir1_blkno) { + status = + ext4fs_devread(__le32_to_cpu + (inode->b.blocks. + double_indir_block) << log2_blksz, + 0, blksz, + (char *)ext4fs_indir1_block); + if (status == 0) { + printf("** DI ext2fs read block (indir 2 1)" + "failed. **\n"); + return -1; + } + ext4fs_indir1_blkno = + __le32_to_cpu(inode->b.blocks.double_indir_block) << + log2_blksz; + } + + if (ext4fs_indir2_block == NULL) { + ext4fs_indir2_block = zalloc(blksz); + if (ext4fs_indir2_block == NULL) { + printf("** DI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir2_size = blksz; + ext4fs_indir2_blkno = -1; + } + if (blksz != ext4fs_indir2_size) { + free(ext4fs_indir2_block); + ext4fs_indir2_block = NULL; + ext4fs_indir2_size = 0; + ext4fs_indir2_blkno = -1; + ext4fs_indir2_block = zalloc(blksz); + if (ext4fs_indir2_block == NULL) { + printf("** DI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir2_size = blksz; + } + if ((__le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) << + log2_blksz) != ext4fs_indir2_blkno) { + status = ext4fs_devread(__le32_to_cpu + (ext4fs_indir1_block + [rblock / + perblock]) << log2_blksz, 0, + blksz, + (char *)ext4fs_indir2_block); + if (status == 0) { + printf("** DI ext2fs read block (indir 2 2)" + "failed. **\n"); + return -1; + } + ext4fs_indir2_blkno = + __le32_to_cpu(ext4fs_indir1_block[rblock + / + perblock]) << + log2_blksz; + } + blknr = __le32_to_cpu(ext4fs_indir2_block[rblock % perblock]); + } + /* Tripple indirect. */ + else { + rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4 + + (blksz / 4 * blksz / 4)); + perblock_child = blksz / 4; + perblock_parent = ((blksz / 4) * (blksz / 4)); + + if (ext4fs_indir1_block == NULL) { + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** TI ext2fs read block (indir 2 1)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + ext4fs_indir1_blkno = -1; + } + if (blksz != ext4fs_indir1_size) { + free(ext4fs_indir1_block); + ext4fs_indir1_block = NULL; + ext4fs_indir1_size = 0; + ext4fs_indir1_blkno = -1; + ext4fs_indir1_block = zalloc(blksz); + if (ext4fs_indir1_block == NULL) { + printf("** TI ext2fs read block (indir 2 1)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir1_size = blksz; + } + if ((__le32_to_cpu(inode->b.blocks.triple_indir_block) << + log2_blksz) != ext4fs_indir1_blkno) { + status = ext4fs_devread + (__le32_to_cpu(inode->b.blocks.triple_indir_block) + << log2_blksz, 0, blksz, + (char *)ext4fs_indir1_block); + if (status == 0) { + printf("** TI ext2fs read block (indir 2 1)" + "failed. **\n"); + return -1; + } + ext4fs_indir1_blkno = + __le32_to_cpu(inode->b.blocks.triple_indir_block) << + log2_blksz; + } + + if (ext4fs_indir2_block == NULL) { + ext4fs_indir2_block = zalloc(blksz); + if (ext4fs_indir2_block == NULL) { + printf("** TI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir2_size = blksz; + ext4fs_indir2_blkno = -1; + } + if (blksz != ext4fs_indir2_size) { + free(ext4fs_indir2_block); + ext4fs_indir2_block = NULL; + ext4fs_indir2_size = 0; + ext4fs_indir2_blkno = -1; + ext4fs_indir2_block = zalloc(blksz); + if (ext4fs_indir2_block == NULL) { + printf("** TI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir2_size = blksz; + } + if ((__le32_to_cpu(ext4fs_indir1_block[rblock / + perblock_parent]) << + log2_blksz) + != ext4fs_indir2_blkno) { + status = ext4fs_devread(__le32_to_cpu + (ext4fs_indir1_block + [rblock / + perblock_parent]) << + log2_blksz, 0, blksz, + (char *)ext4fs_indir2_block); + if (status == 0) { + printf("** TI ext2fs read block (indir 2 2)" + "failed. **\n"); + return -1; + } + ext4fs_indir2_blkno = + __le32_to_cpu(ext4fs_indir1_block[rblock / + perblock_parent]) + << log2_blksz; + } + + if (ext4fs_indir3_block == NULL) { + ext4fs_indir3_block = zalloc(blksz); + if (ext4fs_indir3_block == NULL) { + printf("** TI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir3_size = blksz; + ext4fs_indir3_blkno = -1; + } + if (blksz != ext4fs_indir3_size) { + free(ext4fs_indir3_block); + ext4fs_indir3_block = NULL; + ext4fs_indir3_size = 0; + ext4fs_indir3_blkno = -1; + ext4fs_indir3_block = zalloc(blksz); + if (ext4fs_indir3_block == NULL) { + printf("** TI ext2fs read block (indir 2 2)" + "malloc failed. **\n"); + return -1; + } + ext4fs_indir3_size = blksz; + } + if ((__le32_to_cpu(ext4fs_indir2_block[rblock + / + perblock_child]) << + log2_blksz) != ext4fs_indir3_blkno) { + status = + ext4fs_devread(__le32_to_cpu + (ext4fs_indir2_block + [(rblock / perblock_child) + % (blksz / 4)]) << log2_blksz, 0, + blksz, (char *)ext4fs_indir3_block); + if (status == 0) { + printf("** TI ext2fs read block (indir 2 2)" + "failed. **\n"); + return -1; + } + ext4fs_indir3_blkno = + __le32_to_cpu(ext4fs_indir2_block[(rblock / + perblock_child) % + (blksz / + 4)]) << + log2_blksz; + } + + blknr = __le32_to_cpu(ext4fs_indir3_block + [rblock % perblock_child]); + } + debug("ext4fs_read_block %ld\n", blknr); + + return blknr; +} + +void ext4fs_close(void) +{ + if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) { + ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen); + ext4fs_file = NULL; + } + if (ext4fs_root != NULL) { + free(ext4fs_root); + ext4fs_root = NULL; + } + if (ext4fs_indir1_block != NULL) { + free(ext4fs_indir1_block); + ext4fs_indir1_block = NULL; + ext4fs_indir1_size = 0; + ext4fs_indir1_blkno = -1; + } + if (ext4fs_indir2_block != NULL) { + free(ext4fs_indir2_block); + ext4fs_indir2_block = NULL; + ext4fs_indir2_size = 0; + ext4fs_indir2_blkno = -1; + } + if (ext4fs_indir3_block != NULL) { + free(ext4fs_indir3_block); + ext4fs_indir3_block = NULL; + ext4fs_indir3_size = 0; + ext4fs_indir3_blkno = -1; + } +} + +int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, + struct ext2fs_node **fnode, int *ftype) +{ + unsigned int fpos = 0; + int status; + struct ext2fs_node *diro = (struct ext2fs_node *) dir; + +#ifdef DEBUG + if (name != NULL) + printf("Iterate dir %s\n", name); +#endif /* of DEBUG */ + if (!diro->inode_read) { + status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); + if (status == 0) + return 0; + } + /* Search the file. */ + while (fpos < __le32_to_cpu(diro->inode.size)) { + struct ext2_dirent dirent; + + status = ext4fs_read_file(diro, fpos, + sizeof(struct ext2_dirent), + (char *) &dirent); + if (status < 1) + return 0; + + if (dirent.namelen != 0) { + char filename[dirent.namelen + 1]; + struct ext2fs_node *fdiro; + int type = FILETYPE_UNKNOWN; + + status = ext4fs_read_file(diro, + fpos + + sizeof(struct ext2_dirent), + dirent.namelen, filename); + if (status < 1) + return 0; + + fdiro = zalloc(sizeof(struct ext2fs_node)); + if (!fdiro) + return 0; + + fdiro->data = diro->data; + fdiro->ino = __le32_to_cpu(dirent.inode); + + filename[dirent.namelen] = '\0'; + + if (dirent.filetype != FILETYPE_UNKNOWN) { + fdiro->inode_read = 0; + + if (dirent.filetype == FILETYPE_DIRECTORY) + type = FILETYPE_DIRECTORY; + else if (dirent.filetype == FILETYPE_SYMLINK) + type = FILETYPE_SYMLINK; + else if (dirent.filetype == FILETYPE_REG) + type = FILETYPE_REG; + } else { + status = ext4fs_read_inode(diro->data, + __le32_to_cpu + (dirent.inode), + &fdiro->inode); + if (status == 0) { + free(fdiro); + return 0; + } + fdiro->inode_read = 1; + + if ((__le16_to_cpu(fdiro->inode.mode) & + FILETYPE_INO_MASK) == + FILETYPE_INO_DIRECTORY) { + type = FILETYPE_DIRECTORY; + } else if ((__le16_to_cpu(fdiro->inode.mode) + & FILETYPE_INO_MASK) == + FILETYPE_INO_SYMLINK) { + type = FILETYPE_SYMLINK; + } else if ((__le16_to_cpu(fdiro->inode.mode) + & FILETYPE_INO_MASK) == + FILETYPE_INO_REG) { + type = FILETYPE_REG; + } + } +#ifdef DEBUG + printf("iterate >%s<\n", filename); +#endif /* of DEBUG */ + if ((name != NULL) && (fnode != NULL) + && (ftype != NULL)) { + if (strcmp(filename, name) == 0) { + *ftype = type; + *fnode = fdiro; + return 1; + } + } else { + if (fdiro->inode_read == 0) { + status = ext4fs_read_inode(diro->data, + __le32_to_cpu( + dirent.inode), + &fdiro->inode); + if (status == 0) { + free(fdiro); + return 0; + } + fdiro->inode_read = 1; + } + switch (type) { + case FILETYPE_DIRECTORY: + printf("<DIR> "); + break; + case FILETYPE_SYMLINK: + printf("<SYM> "); + break; + case FILETYPE_REG: + printf(" "); + break; + default: + printf("< ? > "); + break; + } + printf("%10d %s\n", + __le32_to_cpu(fdiro->inode.size), + filename); + } + free(fdiro); + } + fpos += __le16_to_cpu(dirent.direntlen); + } + return 0; +} + +static char *ext4fs_read_symlink(struct ext2fs_node *node) +{ + char *symlink; + struct ext2fs_node *diro = node; + int status; + + if (!diro->inode_read) { + status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); + if (status == 0) + return 0; + } + symlink = zalloc(__le32_to_cpu(diro->inode.size) + 1); + if (!symlink) + return 0; + + if (__le32_to_cpu(diro->inode.size) <= 60) { + strncpy(symlink, diro->inode.b.symlink, + __le32_to_cpu(diro->inode.size)); + } else { + status = ext4fs_read_file(diro, 0, + __le32_to_cpu(diro->inode.size), + symlink); + if (status == 0) { + free(symlink); + return 0; + } + } + symlink[__le32_to_cpu(diro->inode.size)] = '\0'; + return symlink; +} + +static int ext4fs_find_file1(const char *currpath, + struct ext2fs_node *currroot, + struct ext2fs_node **currfound, int *foundtype) +{ + char fpath[strlen(currpath) + 1]; + char *name = fpath; + char *next; + int status; + int type = FILETYPE_DIRECTORY; + struct ext2fs_node *currnode = currroot; + struct ext2fs_node *oldnode = currroot; + + strncpy(fpath, currpath, strlen(currpath) + 1); + + /* Remove all leading slashes. */ + while (*name == '/') + name++; + + if (!*name) { + *currfound = currnode; + return 1; + } + + for (;;) { + int found; + + /* Extract the actual part from the pathname. */ + next = strchr(name, '/'); + if (next) { + /* Remove all leading slashes. */ + while (*next == '/') + *(next++) = '\0'; + } + + if (type != FILETYPE_DIRECTORY) { + ext4fs_free_node(currnode, currroot); + return 0; + } + + oldnode = currnode; + + /* Iterate over the directory. */ + found = ext4fs_iterate_dir(currnode, name, &currnode, &type); + if (found == 0) + return 0; + + if (found == -1) + break; + + /* Read in the symlink and follow it. */ + if (type == FILETYPE_SYMLINK) { + char *symlink; + + /* Test if the symlink does not loop. */ + if (++symlinknest == 8) { + ext4fs_free_node(currnode, currroot); + ext4fs_free_node(oldnode, currroot); + return 0; + } + + symlink = ext4fs_read_symlink(currnode); + ext4fs_free_node(currnode, currroot); + + if (!symlink) { + ext4fs_free_node(oldnode, currroot); + return 0; + } + + debug("Got symlink >%s<\n", symlink); + + if (symlink[0] == '/') { + ext4fs_free_node(oldnode, currroot); + oldnode = &ext4fs_root->diropen; + } + + /* Lookup the node the symlink points to. */ + status = ext4fs_find_file1(symlink, oldnode, + &currnode, &type); + + free(symlink); + + if (status == 0) { + ext4fs_free_node(oldnode, currroot); + return 0; + } + } + + ext4fs_free_node(oldnode, currroot); + + /* Found the node! */ + if (!next || *next == '\0') { + *currfound = currnode; + *foundtype = type; + return 1; + } + name = next; + } + return -1; +} + +int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, + struct ext2fs_node **foundnode, int expecttype) +{ + int status; + int foundtype = FILETYPE_DIRECTORY; + + symlinknest = 0; + if (!path) + return 0; + + status = ext4fs_find_file1(path, rootnode, foundnode, &foundtype); + if (status == 0) + return 0; + + /* Check if the node that was found was of the expected type. */ + if ((expecttype == FILETYPE_REG) && (foundtype != expecttype)) + return 0; + else if ((expecttype == FILETYPE_DIRECTORY) + && (foundtype != expecttype)) + return 0; + + return 1; +} + +int ext4fs_open(const char *filename) +{ + struct ext2fs_node *fdiro = NULL; + int status; + int len; + + if (ext4fs_root == NULL) + return -1; + + ext4fs_file = NULL; + status = ext4fs_find_file(filename, &ext4fs_root->diropen, &fdiro, + FILETYPE_REG); + if (status == 0) + goto fail; + + if (!fdiro->inode_read) { + status = ext4fs_read_inode(fdiro->data, fdiro->ino, + &fdiro->inode); + if (status == 0) + goto fail; + } + len = __le32_to_cpu(fdiro->inode.size); + ext4fs_file = fdiro; + + return len; +fail: + ext4fs_free_node(fdiro, &ext4fs_root->diropen); + + return -1; +} + +int ext4fs_mount(unsigned part_length) +{ + struct ext2_data *data; + int status; + struct ext_filesystem *fs = get_fs(); + data = zalloc(sizeof(struct ext2_data)); + if (!data) + return 0; + + /* Read the superblock. */ + status = ext4fs_devread(1 * 2, 0, sizeof(struct ext2_sblock), + (char *)&data->sblock); + + if (status == 0) + goto fail; + + /* Make sure this is an ext2 filesystem. */ + if (__le16_to_cpu(data->sblock.magic) != EXT2_MAGIC) + goto fail; + + if (__le32_to_cpu(data->sblock.revision_level == 0)) + fs->inodesz = 128; + else + fs->inodesz = __le16_to_cpu(data->sblock.inode_size); + + debug("EXT2 rev %d, inode_size %d\n", + __le32_to_cpu(data->sblock.revision_level), fs->inodesz); + + data->diropen.data = data; + data->diropen.ino = 2; + data->diropen.inode_read = 1; + data->inode = &data->diropen.inode; + + status = ext4fs_read_inode(data, 2, data->inode); + if (status == 0) + goto fail; + + ext4fs_root = data; + + return 1; +fail: + printf("Failed to mount ext2 filesystem...\n"); + free(data); + ext4fs_root = NULL; + + return 0; +} diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h new file mode 100644 index 00000000000..f7281341869 --- /dev/null +++ b/fs/ext4/ext4_common.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * ext4ls and ext4load : based on ext2 ls load support in Uboot. + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * ext4write : Based on generic ext4 protocol. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT4_COMMON__ +#define __EXT4_COMMON__ +#include <ext_common.h> +#include <ext4fs.h> +#include <malloc.h> +#include <asm/errno.h> +#if defined(CONFIG_CMD_EXT4_WRITE) +#include "ext4_journal.h" +#include "crc16.h" +#endif + +#define YES 1 +#define NO 0 +#define TRUE 1 +#define FALSE 0 +#define RECOVER 1 +#define SCAN 0 + +#define S_IFLNK 0120000 /* symbolic link */ +#define BLOCK_NO_ONE 1 +#define SUPERBLOCK_SECTOR 2 +#define SUPERBLOCK_SIZE 1024 +#define F_FILE 1 + +static inline void *zalloc(size_t size) +{ + void *p = memalign(ARCH_DMA_MINALIGN, size); + memset(p, 0, size); + return p; +} + +int ext4fs_read_inode(struct ext2_data *data, int ino, + struct ext2_inode *inode); +int ext4fs_read_file(struct ext2fs_node *node, int pos, + unsigned int len, char *buf); +int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, + struct ext2fs_node **foundnode, int expecttype); +int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, + struct ext2fs_node **fnode, int *ftype); + +#if defined(CONFIG_CMD_EXT4_WRITE) +uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n); +int ext4fs_checksum_update(unsigned int i); +int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags); +void ext4fs_update_parent_dentry(char *filename, int *p_ino, int file_type); +long int ext4fs_get_new_blk_no(void); +int ext4fs_get_new_inode_no(void); +void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, + int index); +int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index); +int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index); +void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index); +int ext4fs_iget(int inode_no, struct ext2_inode *inode); +void ext4fs_allocate_blocks(struct ext2_inode *file_inode, + unsigned int total_remaining_blocks, + unsigned int *total_no_of_block); +void put_ext4(uint64_t off, void *buf, uint32_t size); +#endif +#endif diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c new file mode 100644 index 00000000000..8a252d66c33 --- /dev/null +++ b/fs/ext4/ext4_journal.c @@ -0,0 +1,667 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Journal data structures and headers for Journaling feature of ext4 + * have been referred from JBD2 (Journaling Block device 2) + * implementation in Linux Kernel. + * Written by Stephen C. Tweedie <sct@redhat.com> + * + * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved + * This file is part of the Linux kernel and is made available under + * the terms of the GNU General Public License, version 2, or at your + * option, any later version, incorporated herein by reference. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <ext4fs.h> +#include <malloc.h> +#include <ext_common.h> +#include "ext4_common.h" + +static struct revoke_blk_list *revk_blk_list; +static struct revoke_blk_list *prev_node; +static int first_node = TRUE; + +int gindex; +int gd_index; +int jrnl_blk_idx; +struct journal_log *journal_ptr[MAX_JOURNAL_ENTRIES]; +struct dirty_blocks *dirty_block_ptr[MAX_JOURNAL_ENTRIES]; + +int ext4fs_init_journal(void) +{ + int i; + char *temp = NULL; + struct ext_filesystem *fs = get_fs(); + + /* init globals */ + revk_blk_list = NULL; + prev_node = NULL; + gindex = 0; + gd_index = 0; + jrnl_blk_idx = 1; + + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + journal_ptr[i] = zalloc(sizeof(struct journal_log)); + if (!journal_ptr[i]) + goto fail; + dirty_block_ptr[i] = zalloc(sizeof(struct dirty_blocks)); + if (!dirty_block_ptr[i]) + goto fail; + journal_ptr[i]->buf = NULL; + journal_ptr[i]->blknr = -1; + + dirty_block_ptr[i]->buf = NULL; + dirty_block_ptr[i]->blknr = -1; + } + + if (fs->blksz == 4096) { + temp = zalloc(fs->blksz); + if (!temp) + goto fail; + journal_ptr[gindex]->buf = zalloc(fs->blksz); + if (!journal_ptr[gindex]->buf) + goto fail; + ext4fs_devread(0, 0, fs->blksz, temp); + memcpy(temp + SUPERBLOCK_SIZE, fs->sb, SUPERBLOCK_SIZE); + memcpy(journal_ptr[gindex]->buf, temp, fs->blksz); + journal_ptr[gindex++]->blknr = 0; + free(temp); + } else { + journal_ptr[gindex]->buf = zalloc(fs->blksz); + if (!journal_ptr[gindex]->buf) + goto fail; + memcpy(journal_ptr[gindex]->buf, fs->sb, SUPERBLOCK_SIZE); + journal_ptr[gindex++]->blknr = 1; + } + + /* Check the file system state using journal super block */ + if (ext4fs_check_journal_state(SCAN)) + goto fail; + /* Check the file system state using journal super block */ + if (ext4fs_check_journal_state(RECOVER)) + goto fail; + + return 0; +fail: + return -1; +} + +void ext4fs_dump_metadata(void) +{ + struct ext_filesystem *fs = get_fs(); + int i; + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (dirty_block_ptr[i]->blknr == -1) + break; + put_ext4((uint64_t) ((uint64_t)dirty_block_ptr[i]->blknr * + (uint64_t)fs->blksz), dirty_block_ptr[i]->buf, + fs->blksz); + } +} + +void ext4fs_free_journal(void) +{ + int i; + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (dirty_block_ptr[i]->blknr == -1) + break; + if (dirty_block_ptr[i]->buf) + free(dirty_block_ptr[i]->buf); + } + + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (journal_ptr[i]->blknr == -1) + break; + if (journal_ptr[i]->buf) + free(journal_ptr[i]->buf); + } + + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (journal_ptr[i]) + free(journal_ptr[i]); + if (dirty_block_ptr[i]) + free(dirty_block_ptr[i]); + } + gindex = 0; + gd_index = 0; + jrnl_blk_idx = 1; +} + +int ext4fs_log_gdt(char *gd_table) +{ + struct ext_filesystem *fs = get_fs(); + short i; + long int var = fs->gdtable_blkno; + for (i = 0; i < fs->no_blk_pergdt; i++) { + journal_ptr[gindex]->buf = zalloc(fs->blksz); + if (!journal_ptr[gindex]->buf) + return -ENOMEM; + memcpy(journal_ptr[gindex]->buf, gd_table, fs->blksz); + gd_table += fs->blksz; + journal_ptr[gindex++]->blknr = var++; + } + + return 0; +} + +/* + * This function stores the backup copy of meta data in RAM + * journal_buffer -- Buffer containing meta data + * blknr -- Block number on disk of the meta data buffer + */ +int ext4fs_log_journal(char *journal_buffer, long int blknr) +{ + struct ext_filesystem *fs = get_fs(); + short i; + + if (!journal_buffer) { + printf("Invalid input arguments %s\n", __func__); + return -EINVAL; + } + + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (journal_ptr[i]->blknr == -1) + break; + if (journal_ptr[i]->blknr == blknr) + return 0; + } + + journal_ptr[gindex]->buf = zalloc(fs->blksz); + if (!journal_ptr[gindex]->buf) + return -ENOMEM; + + memcpy(journal_ptr[gindex]->buf, journal_buffer, fs->blksz); + journal_ptr[gindex++]->blknr = blknr; + + return 0; +} + +/* + * This function stores the modified meta data in RAM + * metadata_buffer -- Buffer containing meta data + * blknr -- Block number on disk of the meta data buffer + */ +int ext4fs_put_metadata(char *metadata_buffer, long int blknr) +{ + struct ext_filesystem *fs = get_fs(); + if (!metadata_buffer) { + printf("Invalid input arguments %s\n", __func__); + return -EINVAL; + } + dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz); + if (!dirty_block_ptr[gd_index]->buf) + return -ENOMEM; + memcpy(dirty_block_ptr[gd_index]->buf, metadata_buffer, fs->blksz); + dirty_block_ptr[gd_index++]->blknr = blknr; + + return 0; +} + +void print_revoke_blks(char *revk_blk) +{ + int offset; + int max; + long int blocknr; + struct journal_revoke_header_t *header; + + if (revk_blk == NULL) + return; + + header = (struct journal_revoke_header_t *) revk_blk; + offset = sizeof(struct journal_revoke_header_t); + max = be32_to_cpu(header->r_count); + printf("total bytes %d\n", max); + + while (offset < max) { + blocknr = be32_to_cpu(*((long int *)(revk_blk + offset))); + printf("revoke blknr is %ld\n", blocknr); + offset += 4; + } +} + +static struct revoke_blk_list *_get_node(void) +{ + struct revoke_blk_list *tmp_node; + tmp_node = zalloc(sizeof(struct revoke_blk_list)); + if (tmp_node == NULL) + return NULL; + tmp_node->content = NULL; + tmp_node->next = NULL; + + return tmp_node; +} + +void ext4fs_push_revoke_blk(char *buffer) +{ + struct revoke_blk_list *node = NULL; + struct ext_filesystem *fs = get_fs(); + if (buffer == NULL) { + printf("buffer ptr is NULL\n"); + return; + } + node = _get_node(); + if (!node) { + printf("_get_node: malloc failed\n"); + return; + } + + node->content = zalloc(fs->blksz); + if (node->content == NULL) + return; + memcpy(node->content, buffer, fs->blksz); + + if (first_node == TRUE) { + revk_blk_list = node; + prev_node = node; + first_node = FALSE; + } else { + prev_node->next = node; + prev_node = node; + } +} + +void ext4fs_free_revoke_blks(void) +{ + struct revoke_blk_list *tmp_node = revk_blk_list; + struct revoke_blk_list *next_node = NULL; + + while (tmp_node != NULL) { + if (tmp_node->content) + free(tmp_node->content); + tmp_node = tmp_node->next; + } + + tmp_node = revk_blk_list; + while (tmp_node != NULL) { + next_node = tmp_node->next; + free(tmp_node); + tmp_node = next_node; + } + + revk_blk_list = NULL; + prev_node = NULL; + first_node = TRUE; +} + +int check_blknr_for_revoke(long int blknr, int sequence_no) +{ + struct journal_revoke_header_t *header; + int offset; + int max; + long int blocknr; + char *revk_blk; + struct revoke_blk_list *tmp_revk_node = revk_blk_list; + while (tmp_revk_node != NULL) { + revk_blk = tmp_revk_node->content; + + header = (struct journal_revoke_header_t *) revk_blk; + if (sequence_no < be32_to_cpu(header->r_header.h_sequence)) { + offset = sizeof(struct journal_revoke_header_t); + max = be32_to_cpu(header->r_count); + + while (offset < max) { + blocknr = be32_to_cpu(*((long int *) + (revk_blk + offset))); + if (blocknr == blknr) + goto found; + offset += 4; + } + } + tmp_revk_node = tmp_revk_node->next; + } + + return -1; + +found: + return 0; +} + +/* + * This function parses the journal blocks and replays the + * suceessful transactions. A transaction is successfull + * if commit block is found for a descriptor block + * The tags in descriptor block contain the disk block + * numbers of the metadata to be replayed + */ +void recover_transaction(int prev_desc_logical_no) +{ + struct ext2_inode inode_journal; + struct ext_filesystem *fs = get_fs(); + struct journal_header_t *jdb; + long int blknr; + char *p_jdb; + int ofs, flags; + int i; + struct ext3_journal_block_tag *tag; + char *temp_buff = zalloc(fs->blksz); + char *metadata_buff = zalloc(fs->blksz); + if (!temp_buff || !metadata_buff) + goto fail; + i = prev_desc_logical_no; + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, + (struct ext2_inode *)&inode_journal); + blknr = read_allocated_block((struct ext2_inode *) + &inode_journal, i); + ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); + p_jdb = (char *)temp_buff; + jdb = (struct journal_header_t *) temp_buff; + ofs = sizeof(struct journal_header_t); + + do { + tag = (struct ext3_journal_block_tag *)&p_jdb[ofs]; + ofs += sizeof(struct ext3_journal_block_tag); + + if (ofs > fs->blksz) + break; + + flags = be32_to_cpu(tag->flags); + if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID)) + ofs += 16; + + i++; + debug("\t\ttag %u\n", be32_to_cpu(tag->block)); + if (revk_blk_list != NULL) { + if (check_blknr_for_revoke(be32_to_cpu(tag->block), + be32_to_cpu(jdb->h_sequence)) == 0) + continue; + } + blknr = read_allocated_block(&inode_journal, i); + ext4fs_devread(blknr * fs->sect_perblk, 0, + fs->blksz, metadata_buff); + put_ext4((uint64_t)(be32_to_cpu(tag->block) * fs->blksz), + metadata_buff, (uint32_t) fs->blksz); + } while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG)); +fail: + free(temp_buff); + free(metadata_buff); +} + +void print_jrnl_status(int recovery_flag) +{ + if (recovery_flag == RECOVER) + printf("Journal Recovery Completed\n"); + else + printf("Journal Scan Completed\n"); +} + +int ext4fs_check_journal_state(int recovery_flag) +{ + int i; + int DB_FOUND = NO; + long int blknr; + int transaction_state = TRANSACTION_COMPLETE; + int prev_desc_logical_no = 0; + int curr_desc_logical_no = 0; + int ofs, flags, block; + struct ext2_inode inode_journal; + struct journal_superblock_t *jsb = NULL; + struct journal_header_t *jdb = NULL; + char *p_jdb = NULL; + struct ext3_journal_block_tag *tag = NULL; + char *temp_buff = NULL; + char *temp_buff1 = NULL; + struct ext_filesystem *fs = get_fs(); + + temp_buff = zalloc(fs->blksz); + if (!temp_buff) + return -ENOMEM; + temp_buff1 = zalloc(fs->blksz); + if (!temp_buff1) { + free(temp_buff); + return -ENOMEM; + } + + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); + blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK); + ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); + jsb = (struct journal_superblock_t *) temp_buff; + + if (fs->sb->feature_incompat & EXT3_FEATURE_INCOMPAT_RECOVER) { + if (recovery_flag == RECOVER) + printf("Recovery required\n"); + } else { + if (recovery_flag == RECOVER) + printf("File System is consistent\n"); + goto end; + } + + if (be32_to_cpu(jsb->s_start) == 0) + goto end; + + if (!(jsb->s_feature_compat & + cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM))) + jsb->s_feature_compat |= + cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM); + + i = be32_to_cpu(jsb->s_first); + while (1) { + block = be32_to_cpu(jsb->s_first); + blknr = read_allocated_block(&inode_journal, i); + memset(temp_buff1, '\0', fs->blksz); + ext4fs_devread(blknr * fs->sect_perblk, + 0, fs->blksz, temp_buff1); + jdb = (struct journal_header_t *) temp_buff1; + + if (be32_to_cpu(jdb->h_blocktype) == + EXT3_JOURNAL_DESCRIPTOR_BLOCK) { + if (be32_to_cpu(jdb->h_sequence) != + be32_to_cpu(jsb->s_sequence)) { + print_jrnl_status(recovery_flag); + break; + } + + curr_desc_logical_no = i; + if (transaction_state == TRANSACTION_COMPLETE) + transaction_state = TRANSACTION_RUNNING; + else + return -1; + p_jdb = (char *)temp_buff1; + ofs = sizeof(struct journal_header_t); + do { + tag = (struct ext3_journal_block_tag *) + &p_jdb[ofs]; + ofs += sizeof(struct ext3_journal_block_tag); + if (ofs > fs->blksz) + break; + flags = be32_to_cpu(tag->flags); + if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID)) + ofs += 16; + i++; + debug("\t\ttag %u\n", be32_to_cpu(tag->block)); + } while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG)); + i++; + DB_FOUND = YES; + } else if (be32_to_cpu(jdb->h_blocktype) == + EXT3_JOURNAL_COMMIT_BLOCK) { + if (be32_to_cpu(jdb->h_sequence) != + be32_to_cpu(jsb->s_sequence)) { + print_jrnl_status(recovery_flag); + break; + } + + if (transaction_state == TRANSACTION_RUNNING || + (DB_FOUND == NO)) { + transaction_state = TRANSACTION_COMPLETE; + i++; + jsb->s_sequence = + cpu_to_be32(be32_to_cpu( + jsb->s_sequence) + 1); + } + prev_desc_logical_no = curr_desc_logical_no; + if ((recovery_flag == RECOVER) && (DB_FOUND == YES)) + recover_transaction(prev_desc_logical_no); + + DB_FOUND = NO; + } else if (be32_to_cpu(jdb->h_blocktype) == + EXT3_JOURNAL_REVOKE_BLOCK) { + if (be32_to_cpu(jdb->h_sequence) != + be32_to_cpu(jsb->s_sequence)) { + print_jrnl_status(recovery_flag); + break; + } + if (recovery_flag == SCAN) + ext4fs_push_revoke_blk((char *)jdb); + i++; + } else { + debug("Else Case\n"); + if (be32_to_cpu(jdb->h_sequence) != + be32_to_cpu(jsb->s_sequence)) { + print_jrnl_status(recovery_flag); + break; + } + } + } + +end: + if (recovery_flag == RECOVER) { + jsb->s_start = cpu_to_be32(1); + jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1); + /* get the superblock */ + ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, + (char *)fs->sb); + fs->sb->feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER; + + /* Update the super block */ + put_ext4((uint64_t) (SUPERBLOCK_SIZE), + (struct ext2_sblock *)fs->sb, + (uint32_t) SUPERBLOCK_SIZE); + ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, + (char *)fs->sb); + + blknr = read_allocated_block(&inode_journal, + EXT2_JOURNAL_SUPERBLOCK); + put_ext4((uint64_t) (blknr * fs->blksz), + (struct journal_superblock_t *)temp_buff, + (uint32_t) fs->blksz); + ext4fs_free_revoke_blks(); + } + free(temp_buff); + free(temp_buff1); + + return 0; +} + +static void update_descriptor_block(long int blknr) +{ + int i; + long int jsb_blknr; + struct journal_header_t jdb; + struct ext3_journal_block_tag tag; + struct ext2_inode inode_journal; + struct journal_superblock_t *jsb = NULL; + char *buf = NULL; + char *temp = NULL; + struct ext_filesystem *fs = get_fs(); + char *temp_buff = zalloc(fs->blksz); + if (!temp_buff) + return; + + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); + jsb_blknr = read_allocated_block(&inode_journal, + EXT2_JOURNAL_SUPERBLOCK); + ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); + jsb = (struct journal_superblock_t *) temp_buff; + + jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_DESCRIPTOR_BLOCK); + jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER); + jdb.h_sequence = jsb->s_sequence; + buf = zalloc(fs->blksz); + if (!buf) { + free(temp_buff); + return; + } + temp = buf; + memcpy(buf, &jdb, sizeof(struct journal_header_t)); + temp += sizeof(struct journal_header_t); + + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (journal_ptr[i]->blknr == -1) + break; + + tag.block = cpu_to_be32(journal_ptr[i]->blknr); + tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_SAME_UUID); + memcpy(temp, &tag, sizeof(struct ext3_journal_block_tag)); + temp = temp + sizeof(struct ext3_journal_block_tag); + } + + tag.block = cpu_to_be32(journal_ptr[--i]->blknr); + tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG); + memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag, + sizeof(struct ext3_journal_block_tag)); + put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz); + + free(temp_buff); + free(buf); +} + +static void update_commit_block(long int blknr) +{ + struct journal_header_t jdb; + struct ext_filesystem *fs = get_fs(); + char *buf = NULL; + struct ext2_inode inode_journal; + struct journal_superblock_t *jsb; + long int jsb_blknr; + char *temp_buff = zalloc(fs->blksz); + if (!temp_buff) + return; + + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); + jsb_blknr = read_allocated_block(&inode_journal, + EXT2_JOURNAL_SUPERBLOCK); + ext4fs_devread(jsb_blknr * fs->sect_perblk, 0, fs->blksz, temp_buff); + jsb = (struct journal_superblock_t *) temp_buff; + + jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_COMMIT_BLOCK); + jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER); + jdb.h_sequence = jsb->s_sequence; + buf = zalloc(fs->blksz); + if (!buf) { + free(temp_buff); + return; + } + memcpy(buf, &jdb, sizeof(struct journal_header_t)); + put_ext4((uint64_t) (blknr * fs->blksz), buf, (uint32_t) fs->blksz); + + free(temp_buff); + free(buf); +} + +void ext4fs_update_journal(void) +{ + struct ext2_inode inode_journal; + struct ext_filesystem *fs = get_fs(); + long int blknr; + int i; + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal); + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + update_descriptor_block(blknr); + for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) { + if (journal_ptr[i]->blknr == -1) + break; + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), + journal_ptr[i]->buf, fs->blksz); + } + blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++); + update_commit_block(blknr); + printf("update journal finished\n"); +} diff --git a/fs/ext4/ext4_journal.h b/fs/ext4/ext4_journal.h new file mode 100644 index 00000000000..acc1c51635b --- /dev/null +++ b/fs/ext4/ext4_journal.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Journal data structures and headers for Journaling feature of ext4 + * have been referred from JBD2 (Journaling Block device 2) + * implementation in Linux Kernel. + * + * Written by Stephen C. Tweedie <sct@redhat.com> + * + * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved + * This file is part of the Linux kernel and is made available under + * the terms of the GNU General Public License, version 2, or at your + * option, any later version, incorporated herein by reference. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT4_JRNL__ +#define __EXT4_JRNL__ + +#define EXT2_JOURNAL_INO 8 /* Journal inode */ +#define EXT2_JOURNAL_SUPERBLOCK 0 /* Journal Superblock number */ + +#define JBD2_FEATURE_COMPAT_CHECKSUM 0x00000001 +#define EXT3_JOURNAL_MAGIC_NUMBER 0xc03b3998U +#define TRANSACTION_RUNNING 1 +#define TRANSACTION_COMPLETE 0 +#define EXT3_FEATURE_INCOMPAT_RECOVER 0x0004 /* Needs recovery */ +#define EXT3_JOURNAL_DESCRIPTOR_BLOCK 1 +#define EXT3_JOURNAL_COMMIT_BLOCK 2 +#define EXT3_JOURNAL_SUPERBLOCK_V1 3 +#define EXT3_JOURNAL_SUPERBLOCK_V2 4 +#define EXT3_JOURNAL_REVOKE_BLOCK 5 +#define EXT3_JOURNAL_FLAG_ESCAPE 1 +#define EXT3_JOURNAL_FLAG_SAME_UUID 2 +#define EXT3_JOURNAL_FLAG_DELETED 4 +#define EXT3_JOURNAL_FLAG_LAST_TAG 8 + +/* Maximum entries in 1 journal transaction */ +#define MAX_JOURNAL_ENTRIES 100 +struct journal_log { + char *buf; + int blknr; +}; + +struct dirty_blocks { + char *buf; + int blknr; +}; + +/* Standard header for all descriptor blocks: */ +struct journal_header_t { + __u32 h_magic; + __u32 h_blocktype; + __u32 h_sequence; +}; + +/* The journal superblock. All fields are in big-endian byte order. */ +struct journal_superblock_t { + /* 0x0000 */ + struct journal_header_t s_header; + + /* Static information describing the journal */ + __u32 s_blocksize; /* journal device blocksize */ + __u32 s_maxlen; /* total blocks in journal file */ + __u32 s_first; /* first block of log information */ + + /* Dynamic information describing the current state of the log */ + __u32 s_sequence; /* first commit ID expected in log */ + __u32 s_start; /* blocknr of start of log */ + + /* Error value, as set by journal_abort(). */ + __s32 s_errno; + + /* Remaining fields are only valid in a version-2 superblock */ + __u32 s_feature_compat; /* compatible feature set */ + __u32 s_feature_incompat; /* incompatible feature set */ + __u32 s_feature_ro_compat; /* readonly-compatible feature set */ + /* 0x0030 */ + __u8 s_uuid[16]; /* 128-bit uuid for journal */ + + /* 0x0040 */ + __u32 s_nr_users; /* Nr of filesystems sharing log */ + + __u32 s_dynsuper; /* Blocknr of dynamic superblock copy */ + + /* 0x0048 */ + __u32 s_max_transaction; /* Limit of journal blocks per trans. */ + __u32 s_max_trans_data; /* Limit of data blocks per trans. */ + + /* 0x0050 */ + __u32 s_padding[44]; + + /* 0x0100 */ + __u8 s_users[16 * 48]; /* ids of all fs'es sharing the log */ + /* 0x0400 */ +} ; + +struct ext3_journal_block_tag { + uint32_t block; + uint32_t flags; +}; + +struct journal_revoke_header_t { + struct journal_header_t r_header; + int r_count; /* Count of bytes used in the block */ +}; + +struct revoke_blk_list { + char *content; /* revoke block itself */ + struct revoke_blk_list *next; +}; + +extern struct ext2_data *ext4fs_root; + +int ext4fs_init_journal(void); +int ext4fs_log_gdt(char *gd_table); +int ext4fs_check_journal_state(int recovery_flag); +int ext4fs_log_journal(char *journal_buffer, long int blknr); +int ext4fs_put_metadata(char *metadata_buffer, long int blknr); +void ext4fs_update_journal(void); +void ext4fs_dump_metadata(void); +void ext4fs_push_revoke_blk(char *buffer); +void ext4fs_free_journal(void); +void ext4fs_free_revoke_blks(void); +#endif diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c new file mode 100644 index 00000000000..93dcb7e8fac --- /dev/null +++ b/fs/ext4/ext4fs.c @@ -0,0 +1,1156 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * ext4ls and ext4load : Based on ext2 ls and load support in Uboot. + * Ext4 read optimization taken from Open-Moko + * Qi bootloader + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * ext4write : Based on generic ext4 protocol. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <malloc.h> +#include <ext_common.h> +#include <ext4fs.h> +#include <linux/stat.h> +#include <linux/time.h> +#include <asm/byteorder.h> +#include "ext4_common.h" + +int ext4fs_symlinknest; +struct ext_filesystem ext_fs; + +struct ext_filesystem *get_fs(void) +{ + return &ext_fs; +} + +void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot) +{ + if ((node != &ext4fs_root->diropen) && (node != currroot)) + free(node); +} + +/* + * Taken from openmoko-kernel mailing list: By Andy green + * Optimized read file API : collects and defers contiguous sector + * reads into one potentially more efficient larger sequential read action + */ +int ext4fs_read_file(struct ext2fs_node *node, int pos, + unsigned int len, char *buf) +{ + int i; + int blockcnt; + int log2blocksize = LOG2_EXT2_BLOCK_SIZE(node->data); + int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS); + unsigned int filesize = __le32_to_cpu(node->inode.size); + int previous_block_number = -1; + int delayed_start = 0; + int delayed_extent = 0; + int delayed_skipfirst = 0; + int delayed_next = 0; + char *delayed_buf = NULL; + short status; + + /* Adjust len so it we can't read past the end of the file. */ + if (len > filesize) + len = filesize; + + blockcnt = ((len + pos) + blocksize - 1) / blocksize; + + for (i = pos / blocksize; i < blockcnt; i++) { + int blknr; + int blockoff = pos % blocksize; + int blockend = blocksize; + int skipfirst = 0; + blknr = read_allocated_block(&(node->inode), i); + if (blknr < 0) + return -1; + + blknr = blknr << log2blocksize; + + /* Last block. */ + if (i == blockcnt - 1) { + blockend = (len + pos) % blocksize; + + /* The last portion is exactly blocksize. */ + if (!blockend) + blockend = blocksize; + } + + /* First block. */ + if (i == pos / blocksize) { + skipfirst = blockoff; + blockend -= skipfirst; + } + if (blknr) { + int status; + + if (previous_block_number != -1) { + if (delayed_next == blknr) { + delayed_extent += blockend; + delayed_next += blockend >> SECTOR_BITS; + } else { /* spill */ + status = ext4fs_devread(delayed_start, + delayed_skipfirst, + delayed_extent, + delayed_buf); + if (status == 0) + return -1; + previous_block_number = blknr; + delayed_start = blknr; + delayed_extent = blockend; + delayed_skipfirst = skipfirst; + delayed_buf = buf; + delayed_next = blknr + + (blockend >> SECTOR_BITS); + } + } else { + previous_block_number = blknr; + delayed_start = blknr; + delayed_extent = blockend; + delayed_skipfirst = skipfirst; + delayed_buf = buf; + delayed_next = blknr + + (blockend >> SECTOR_BITS); + } + } else { + if (previous_block_number != -1) { + /* spill */ + status = ext4fs_devread(delayed_start, + delayed_skipfirst, + delayed_extent, + delayed_buf); + if (status == 0) + return -1; + previous_block_number = -1; + } + memset(buf, 0, blocksize - skipfirst); + } + buf += blocksize - skipfirst; + } + if (previous_block_number != -1) { + /* spill */ + status = ext4fs_devread(delayed_start, + delayed_skipfirst, delayed_extent, + delayed_buf); + if (status == 0) + return -1; + previous_block_number = -1; + } + + return len; +} + +int ext4fs_ls(const char *dirname) +{ + struct ext2fs_node *dirnode; + int status; + + if (dirname == NULL) + return 0; + + status = ext4fs_find_file(dirname, &ext4fs_root->diropen, &dirnode, + FILETYPE_DIRECTORY); + if (status != 1) { + printf("** Can not find directory. **\n"); + return 1; + } + + ext4fs_iterate_dir(dirnode, NULL, NULL, NULL); + ext4fs_free_node(dirnode, &ext4fs_root->diropen); + + return 0; +} + +int ext4fs_read(char *buf, unsigned len) +{ + if (ext4fs_root == NULL || ext4fs_file == NULL) + return 0; + + return ext4fs_read_file(ext4fs_file, 0, len, buf); +} + +#if defined(CONFIG_CMD_EXT4_WRITE) +static void ext4fs_update(void) +{ + short i; + ext4fs_update_journal(); + struct ext_filesystem *fs = get_fs(); + + /* update super block */ + put_ext4((uint64_t)(SUPERBLOCK_SIZE), + (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE); + + /* update block groups */ + for (i = 0; i < fs->no_blkgrp; i++) { + fs->gd[i].bg_checksum = ext4fs_checksum_update(i); + put_ext4((uint64_t)(fs->gd[i].block_id * fs->blksz), + fs->blk_bmaps[i], fs->blksz); + } + + /* update inode table groups */ + for (i = 0; i < fs->no_blkgrp; i++) { + put_ext4((uint64_t) (fs->gd[i].inode_id * fs->blksz), + fs->inode_bmaps[i], fs->blksz); + } + + /* update the block group descriptor table */ + put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz), + (struct ext2_block_group *)fs->gdtable, + (fs->blksz * fs->no_blk_pergdt)); + + ext4fs_dump_metadata(); + + gindex = 0; + gd_index = 0; +} + +int ext4fs_get_bgdtable(void) +{ + int status; + int grp_desc_size; + struct ext_filesystem *fs = get_fs(); + grp_desc_size = sizeof(struct ext2_block_group); + fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz; + if ((fs->no_blkgrp * grp_desc_size) % fs->blksz) + fs->no_blk_pergdt++; + + /* allocate memory for gdtable */ + fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt); + if (!fs->gdtable) + return -ENOMEM; + /* read the group descriptor table */ + status = ext4fs_devread(fs->gdtable_blkno * fs->sect_perblk, 0, + fs->blksz * fs->no_blk_pergdt, fs->gdtable); + if (status == 0) + goto fail; + + if (ext4fs_log_gdt(fs->gdtable)) { + printf("Error in ext4fs_log_gdt\n"); + return -1; + } + + return 0; +fail: + free(fs->gdtable); + fs->gdtable = NULL; + + return -1; +} + +static void delete_single_indirect_block(struct ext2_inode *inode) +{ + struct ext2_block_group *gd = NULL; + static int prev_bg_bmap_idx = -1; + long int blknr; + int remainder; + int bg_idx; + int status; + unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + if (!journal_buffer) { + printf("No memory\n"); + return; + } + /* get block group descriptor table */ + gd = (struct ext2_block_group *)fs->gdtable; + + /* deleting the single indirect block associated with inode */ + if (inode->b.blocks.indir_block != 0) { + debug("SIPB releasing %u\n", inode->b.blocks.indir_block); + blknr = inode->b.blocks.indir_block; + if (fs->blksz != 1024) { + bg_idx = blknr / blk_per_grp; + } else { + bg_idx = blknr / blk_per_grp; + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + status = + ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal + (journal_buffer, gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } +fail: + free(journal_buffer); +} + +static void delete_double_indirect_block(struct ext2_inode *inode) +{ + int i; + short status; + static int prev_bg_bmap_idx = -1; + long int blknr; + int remainder; + int bg_idx; + unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + unsigned int *di_buffer = NULL; + unsigned int *DIB_start_addr = NULL; + struct ext2_block_group *gd = NULL; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + if (!journal_buffer) { + printf("No memory\n"); + return; + } + /* get the block group descriptor table */ + gd = (struct ext2_block_group *)fs->gdtable; + + if (inode->b.blocks.double_indir_block != 0) { + di_buffer = zalloc(fs->blksz); + if (!di_buffer) { + printf("No memory\n"); + return; + } + DIB_start_addr = (unsigned int *)di_buffer; + blknr = inode->b.blocks.double_indir_block; + status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, + (char *)di_buffer); + for (i = 0; i < fs->blksz / sizeof(int); i++) { + if (*di_buffer == 0) + break; + + debug("DICB releasing %u\n", *di_buffer); + if (fs->blksz != 1024) { + bg_idx = (*di_buffer) / blk_per_grp; + } else { + bg_idx = (*di_buffer) / blk_per_grp; + remainder = (*di_buffer) % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(*di_buffer, + fs->blk_bmaps[bg_idx], bg_idx); + di_buffer++; + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + status = ext4fs_devread(gd[bg_idx].block_id + * fs->sect_perblk, 0, + fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } + + /* removing the parent double indirect block */ + blknr = inode->b.blocks.double_indir_block; + if (fs->blksz != 1024) { + bg_idx = blknr / blk_per_grp; + } else { + bg_idx = blknr / blk_per_grp; + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + debug("DIPB releasing %ld\n", blknr); + } +fail: + free(DIB_start_addr); + free(journal_buffer); +} + +static void delete_triple_indirect_block(struct ext2_inode *inode) +{ + int i, j; + short status; + static int prev_bg_bmap_idx = -1; + long int blknr; + int remainder; + int bg_idx; + unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + unsigned int *tigp_buffer = NULL; + unsigned int *tib_start_addr = NULL; + unsigned int *tip_buffer = NULL; + unsigned int *tipb_start_addr = NULL; + struct ext2_block_group *gd = NULL; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + if (!journal_buffer) { + printf("No memory\n"); + return; + } + /* get block group descriptor table */ + gd = (struct ext2_block_group *)fs->gdtable; + + if (inode->b.blocks.triple_indir_block != 0) { + tigp_buffer = zalloc(fs->blksz); + if (!tigp_buffer) { + printf("No memory\n"); + return; + } + tib_start_addr = (unsigned int *)tigp_buffer; + blknr = inode->b.blocks.triple_indir_block; + status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, + (char *)tigp_buffer); + for (i = 0; i < fs->blksz / sizeof(int); i++) { + if (*tigp_buffer == 0) + break; + debug("tigp buffer releasing %u\n", *tigp_buffer); + + tip_buffer = zalloc(fs->blksz); + if (!tip_buffer) + goto fail; + tipb_start_addr = (unsigned int *)tip_buffer; + status = ext4fs_devread((*tigp_buffer) * + fs->sect_perblk, 0, fs->blksz, + (char *)tip_buffer); + for (j = 0; j < fs->blksz / sizeof(int); j++) { + if (*tip_buffer == 0) + break; + if (fs->blksz != 1024) { + bg_idx = (*tip_buffer) / blk_per_grp; + } else { + bg_idx = (*tip_buffer) / blk_per_grp; + + remainder = (*tip_buffer) % blk_per_grp; + if (!remainder) + bg_idx--; + } + + ext4fs_reset_block_bmap(*tip_buffer, + fs->blk_bmaps[bg_idx], + bg_idx); + + tip_buffer++; + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + status = + ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, + fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx]. + block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } + free(tipb_start_addr); + tipb_start_addr = NULL; + + /* + * removing the grand parent blocks + * which is connected to inode + */ + if (fs->blksz != 1024) { + bg_idx = (*tigp_buffer) / blk_per_grp; + } else { + bg_idx = (*tigp_buffer) / blk_per_grp; + + remainder = (*tigp_buffer) % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(*tigp_buffer, + fs->blk_bmaps[bg_idx], bg_idx); + + tigp_buffer++; + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = + ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, + fs->blksz, journal_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } + + /* removing the grand parent triple indirect block */ + blknr = inode->b.blocks.triple_indir_block; + if (fs->blksz != 1024) { + bg_idx = blknr / blk_per_grp; + } else { + bg_idx = blknr / blk_per_grp; + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx); + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + debug("tigp buffer itself releasing %ld\n", blknr); + } +fail: + free(tib_start_addr); + free(tipb_start_addr); + free(journal_buffer); +} + +static int ext4fs_delete_file(int inodeno) +{ + struct ext2_inode inode; + short status; + int i; + int remainder; + long int blknr; + int bg_idx; + int ibmap_idx; + char *read_buffer = NULL; + char *start_block_address = NULL; + unsigned int no_blocks; + + static int prev_bg_bmap_idx = -1; + unsigned int inodes_per_block; + long int blkno; + unsigned int blkoff; + unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group; + unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group; + struct ext2_inode *inode_buffer = NULL; + struct ext2_block_group *gd = NULL; + struct ext_filesystem *fs = get_fs(); + char *journal_buffer = zalloc(fs->blksz); + if (!journal_buffer) + return -ENOMEM; + /* get the block group descriptor table */ + gd = (struct ext2_block_group *)fs->gdtable; + status = ext4fs_read_inode(ext4fs_root, inodeno, &inode); + if (status == 0) + goto fail; + + /* read the block no allocated to a file */ + no_blocks = inode.size / fs->blksz; + if (inode.size % fs->blksz) + no_blocks++; + + if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) { + struct ext2fs_node *node_inode = + zalloc(sizeof(struct ext2fs_node)); + if (!node_inode) + goto fail; + node_inode->data = ext4fs_root; + node_inode->ino = inodeno; + node_inode->inode_read = 0; + memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode)); + + for (i = 0; i < no_blocks; i++) { + blknr = read_allocated_block(&(node_inode->inode), i); + if (fs->blksz != 1024) { + bg_idx = blknr / blk_per_grp; + } else { + bg_idx = blknr / blk_per_grp; + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], + bg_idx); + debug("EXT4_EXTENTS Block releasing %ld: %d\n", + blknr, bg_idx); + + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + status = + ext4fs_devread(gd[bg_idx].block_id * + fs->sect_perblk, 0, + fs->blksz, journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } + if (node_inode) { + free(node_inode); + node_inode = NULL; + } + } else { + + delete_single_indirect_block(&inode); + delete_double_indirect_block(&inode); + delete_triple_indirect_block(&inode); + + /* read the block no allocated to a file */ + no_blocks = inode.size / fs->blksz; + if (inode.size % fs->blksz) + no_blocks++; + for (i = 0; i < no_blocks; i++) { + blknr = read_allocated_block(&inode, i); + if (fs->blksz != 1024) { + bg_idx = blknr / blk_per_grp; + } else { + bg_idx = blknr / blk_per_grp; + remainder = blknr % blk_per_grp; + if (!remainder) + bg_idx--; + } + ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], + bg_idx); + debug("ActualB releasing %ld: %d\n", blknr, bg_idx); + + gd[bg_idx].free_blocks++; + fs->sb->free_blocks++; + /* journal backup */ + if (prev_bg_bmap_idx != bg_idx) { + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[bg_idx].block_id + * fs->sect_perblk, + 0, fs->blksz, + journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, + gd[bg_idx].block_id)) + goto fail; + prev_bg_bmap_idx = bg_idx; + } + } + } + + /* from the inode no to blockno */ + inodes_per_block = fs->blksz / fs->inodesz; + ibmap_idx = inodeno / inode_per_grp; + + /* get the block no */ + inodeno--; + blkno = __le32_to_cpu(gd[ibmap_idx].inode_table_id) + + (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block; + + /* get the offset of the inode */ + blkoff = ((inodeno) % inodes_per_block) * fs->inodesz; + + /* read the block no containing the inode */ + read_buffer = zalloc(fs->blksz); + if (!read_buffer) + goto fail; + start_block_address = read_buffer; + status = ext4fs_devread(blkno * fs->sect_perblk, + 0, fs->blksz, read_buffer); + if (status == 0) + goto fail; + + if (ext4fs_log_journal(read_buffer, blkno)) + goto fail; + + read_buffer = read_buffer + blkoff; + inode_buffer = (struct ext2_inode *)read_buffer; + memset(inode_buffer, '\0', sizeof(struct ext2_inode)); + + /* write the inode to original position in inode table */ + if (ext4fs_put_metadata(start_block_address, blkno)) + goto fail; + + /* update the respective inode bitmaps */ + inodeno++; + ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx); + gd[ibmap_idx].free_inodes++; + fs->sb->free_inodes++; + /* journal backup */ + memset(journal_buffer, '\0', fs->blksz); + status = ext4fs_devread(gd[ibmap_idx].inode_id * + fs->sect_perblk, 0, fs->blksz, journal_buffer); + if (status == 0) + goto fail; + if (ext4fs_log_journal(journal_buffer, gd[ibmap_idx].inode_id)) + goto fail; + + ext4fs_update(); + ext4fs_deinit(); + + if (ext4fs_init() != 0) { + printf("error in File System init\n"); + goto fail; + } + + free(start_block_address); + free(journal_buffer); + + return 0; +fail: + free(start_block_address); + free(journal_buffer); + + return -1; +} + +int ext4fs_init(void) +{ + short status; + int i; + unsigned int real_free_blocks = 0; + struct ext_filesystem *fs = get_fs(); + + /* populate fs */ + fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root); + fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root); + fs->sect_perblk = fs->blksz / SECTOR_SIZE; + + /* get the superblock */ + fs->sb = zalloc(SUPERBLOCK_SIZE); + if (!fs->sb) + return -ENOMEM; + if (!ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, + (char *)fs->sb)) + goto fail; + + /* init journal */ + if (ext4fs_init_journal()) + goto fail; + + /* get total no of blockgroups */ + fs->no_blkgrp = (uint32_t)ext4fs_div_roundup( + (ext4fs_root->sblock.total_blocks - + ext4fs_root->sblock.first_data_block), + ext4fs_root->sblock.blocks_per_group); + + /* get the block group descriptor table */ + fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1); + if (ext4fs_get_bgdtable() == -1) { + printf("Error in getting the block group descriptor table\n"); + goto fail; + } + fs->gd = (struct ext2_block_group *)fs->gdtable; + + /* load all the available bitmap block of the partition */ + fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *)); + if (!fs->blk_bmaps) + goto fail; + for (i = 0; i < fs->no_blkgrp; i++) { + fs->blk_bmaps[i] = zalloc(fs->blksz); + if (!fs->blk_bmaps[i]) + goto fail; + } + + for (i = 0; i < fs->no_blkgrp; i++) { + status = + ext4fs_devread(fs->gd[i].block_id * fs->sect_perblk, 0, + fs->blksz, (char *)fs->blk_bmaps[i]); + if (status == 0) + goto fail; + } + + /* load all the available inode bitmap of the partition */ + fs->inode_bmaps = zalloc(fs->no_blkgrp * sizeof(unsigned char *)); + if (!fs->inode_bmaps) + goto fail; + for (i = 0; i < fs->no_blkgrp; i++) { + fs->inode_bmaps[i] = zalloc(fs->blksz); + if (!fs->inode_bmaps[i]) + goto fail; + } + + for (i = 0; i < fs->no_blkgrp; i++) { + status = ext4fs_devread(fs->gd[i].inode_id * fs->sect_perblk, + 0, fs->blksz, + (char *)fs->inode_bmaps[i]); + if (status == 0) + goto fail; + } + + /* + * check filesystem consistency with free blocks of file system + * some time we observed that superblock freeblocks does not match + * with the blockgroups freeblocks when improper + * reboot of a linux kernel + */ + for (i = 0; i < fs->no_blkgrp; i++) + real_free_blocks = real_free_blocks + fs->gd[i].free_blocks; + if (real_free_blocks != fs->sb->free_blocks) + fs->sb->free_blocks = real_free_blocks; + + return 0; +fail: + ext4fs_deinit(); + + return -1; +} + +void ext4fs_deinit(void) +{ + int i; + struct ext2_inode inode_journal; + struct journal_superblock_t *jsb; + long int blknr; + struct ext_filesystem *fs = get_fs(); + + /* free journal */ + char *temp_buff = zalloc(fs->blksz); + if (temp_buff) { + ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, + &inode_journal); + blknr = read_allocated_block(&inode_journal, + EXT2_JOURNAL_SUPERBLOCK); + ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz, + temp_buff); + jsb = (struct journal_superblock_t *)temp_buff; + jsb->s_start = cpu_to_be32(0); + put_ext4((uint64_t) (blknr * fs->blksz), + (struct journal_superblock_t *)temp_buff, fs->blksz); + free(temp_buff); + } + ext4fs_free_journal(); + + /* get the superblock */ + ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, (char *)fs->sb); + fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER; + put_ext4((uint64_t)(SUPERBLOCK_SIZE), + (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE); + free(fs->sb); + fs->sb = NULL; + + if (fs->blk_bmaps) { + for (i = 0; i < fs->no_blkgrp; i++) { + free(fs->blk_bmaps[i]); + fs->blk_bmaps[i] = NULL; + } + free(fs->blk_bmaps); + fs->blk_bmaps = NULL; + } + + if (fs->inode_bmaps) { + for (i = 0; i < fs->no_blkgrp; i++) { + free(fs->inode_bmaps[i]); + fs->inode_bmaps[i] = NULL; + } + free(fs->inode_bmaps); + fs->inode_bmaps = NULL; + } + + + free(fs->gdtable); + fs->gdtable = NULL; + fs->gd = NULL; + /* + * reinitiliazed the global inode and + * block bitmap first execution check variables + */ + fs->first_pass_ibmap = 0; + fs->first_pass_bbmap = 0; + fs->curr_inode_no = 0; + fs->curr_blkno = 0; +} + +static int ext4fs_write_file(struct ext2_inode *file_inode, + int pos, unsigned int len, char *buf) +{ + int i; + int blockcnt; + int log2blocksize = LOG2_EXT2_BLOCK_SIZE(ext4fs_root); + unsigned int filesize = __le32_to_cpu(file_inode->size); + struct ext_filesystem *fs = get_fs(); + int previous_block_number = -1; + int delayed_start = 0; + int delayed_extent = 0; + int delayed_skipfirst = 0; + int delayed_next = 0; + char *delayed_buf = NULL; + + /* Adjust len so it we can't read past the end of the file. */ + if (len > filesize) + len = filesize; + + blockcnt = ((len + pos) + fs->blksz - 1) / fs->blksz; + + for (i = pos / fs->blksz; i < blockcnt; i++) { + long int blknr; + int blockend = fs->blksz; + int skipfirst = 0; + blknr = read_allocated_block(file_inode, i); + if (blknr < 0) + return -1; + + blknr = blknr << log2blocksize; + + if (blknr) { + if (previous_block_number != -1) { + if (delayed_next == blknr) { + delayed_extent += blockend; + delayed_next += blockend >> SECTOR_BITS; + } else { /* spill */ + put_ext4((uint64_t) (delayed_start * + SECTOR_SIZE), + delayed_buf, + (uint32_t) delayed_extent); + previous_block_number = blknr; + delayed_start = blknr; + delayed_extent = blockend; + delayed_skipfirst = skipfirst; + delayed_buf = buf; + delayed_next = blknr + + (blockend >> SECTOR_BITS); + } + } else { + previous_block_number = blknr; + delayed_start = blknr; + delayed_extent = blockend; + delayed_skipfirst = skipfirst; + delayed_buf = buf; + delayed_next = blknr + + (blockend >> SECTOR_BITS); + } + } else { + if (previous_block_number != -1) { + /* spill */ + put_ext4((uint64_t) (delayed_start * + SECTOR_SIZE), delayed_buf, + (uint32_t) delayed_extent); + previous_block_number = -1; + } + memset(buf, 0, fs->blksz - skipfirst); + } + buf += fs->blksz - skipfirst; + } + if (previous_block_number != -1) { + /* spill */ + put_ext4((uint64_t) (delayed_start * SECTOR_SIZE), + delayed_buf, (uint32_t) delayed_extent); + previous_block_number = -1; + } + + return len; +} + +int ext4fs_write(const char *fname, unsigned char *buffer, + unsigned long sizebytes) +{ + int ret = 0; + struct ext2_inode *file_inode = NULL; + unsigned char *inode_buffer = NULL; + int parent_inodeno; + int inodeno; + time_t timestamp = 0; + + uint64_t bytes_reqd_for_file; + unsigned int blks_reqd_for_file; + unsigned int blocks_remaining; + int existing_file_inodeno; + char filename[256]; + + char *temp_ptr = NULL; + long int itable_blkno; + long int parent_itable_blkno; + long int blkoff; + struct ext2_sblock *sblock = &(ext4fs_root->sblock); + unsigned int inodes_per_block; + unsigned int ibmap_idx; + struct ext_filesystem *fs = get_fs(); + g_parent_inode = zalloc(sizeof(struct ext2_inode)); + if (!g_parent_inode) + goto fail; + + if (ext4fs_init() != 0) { + printf("error in File System init\n"); + return -1; + } + inodes_per_block = fs->blksz / fs->inodesz; + parent_inodeno = ext4fs_get_parent_inode_num(fname, filename, F_FILE); + if (parent_inodeno == -1) + goto fail; + if (ext4fs_iget(parent_inodeno, g_parent_inode)) + goto fail; + /* check if the filename is already present in root */ + existing_file_inodeno = ext4fs_filename_check(filename); + if (existing_file_inodeno != -1) { + ret = ext4fs_delete_file(existing_file_inodeno); + fs->first_pass_bbmap = 0; + fs->curr_blkno = 0; + + fs->first_pass_ibmap = 0; + fs->curr_inode_no = 0; + if (ret) + goto fail; + } + /* calucalate how many blocks required */ + bytes_reqd_for_file = sizebytes; + blks_reqd_for_file = bytes_reqd_for_file / fs->blksz; + if (bytes_reqd_for_file % fs->blksz != 0) { + blks_reqd_for_file++; + debug("total bytes for a file %u\n", blks_reqd_for_file); + } + blocks_remaining = blks_reqd_for_file; + /* test for available space in partition */ + if (fs->sb->free_blocks < blks_reqd_for_file) { + printf("Not enough space on partition !!!\n"); + goto fail; + } + + ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG); + /* prepare file inode */ + inode_buffer = zalloc(fs->inodesz); + if (!inode_buffer) + goto fail; + file_inode = (struct ext2_inode *)inode_buffer; + file_inode->mode = S_IFREG | S_IRWXU | + S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH; + /* ToDo: Update correct time */ + file_inode->mtime = timestamp; + file_inode->atime = timestamp; + file_inode->ctime = timestamp; + file_inode->nlinks = 1; + file_inode->size = sizebytes; + + /* Allocate data blocks */ + ext4fs_allocate_blocks(file_inode, blocks_remaining, + &blks_reqd_for_file); + file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) / SECTOR_SIZE; + + temp_ptr = zalloc(fs->blksz); + if (!temp_ptr) + goto fail; + ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group; + inodeno--; + itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) + + (inodeno % __le32_to_cpu(sblock->inodes_per_group)) / + inodes_per_block; + blkoff = (inodeno % inodes_per_block) * fs->inodesz; + ext4fs_devread(itable_blkno * fs->sect_perblk, 0, fs->blksz, temp_ptr); + if (ext4fs_log_journal(temp_ptr, itable_blkno)) + goto fail; + + memcpy(temp_ptr + blkoff, inode_buffer, fs->inodesz); + if (ext4fs_put_metadata(temp_ptr, itable_blkno)) + goto fail; + /* copy the file content into data blocks */ + if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) { + printf("Error in copying content\n"); + goto fail; + } + ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group; + parent_inodeno--; + parent_itable_blkno = __le32_to_cpu(fs->gd[ibmap_idx].inode_table_id) + + (parent_inodeno % + __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block; + blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz; + if (parent_itable_blkno != itable_blkno) { + memset(temp_ptr, '\0', fs->blksz); + ext4fs_devread(parent_itable_blkno * fs->sect_perblk, + 0, fs->blksz, temp_ptr); + if (ext4fs_log_journal(temp_ptr, parent_itable_blkno)) + goto fail; + + memcpy(temp_ptr + blkoff, g_parent_inode, + sizeof(struct ext2_inode)); + if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno)) + goto fail; + free(temp_ptr); + } else { + /* + * If parent and child fall in same inode table block + * both should be kept in 1 buffer + */ + memcpy(temp_ptr + blkoff, g_parent_inode, + sizeof(struct ext2_inode)); + gd_index--; + if (ext4fs_put_metadata(temp_ptr, itable_blkno)) + goto fail; + free(temp_ptr); + } + ext4fs_update(); + ext4fs_deinit(); + + fs->first_pass_bbmap = 0; + fs->curr_blkno = 0; + fs->first_pass_ibmap = 0; + fs->curr_inode_no = 0; + free(inode_buffer); + free(g_parent_inode); + g_parent_inode = NULL; + + return 0; +fail: + ext4fs_deinit(); + free(inode_buffer); + free(g_parent_inode); + g_parent_inode = NULL; + + return -1; +} +#endif diff --git a/fs/fat/fat.c b/fs/fat/fat.c index f7bb1dadff3..19f6a8c0af6 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1109,11 +1109,11 @@ rootdir_done: goto exit; } - if (idx >= 0) { - if (!(dentptr->attr & ATTR_DIR)) - goto exit; + if (isdir && !(dentptr->attr & ATTR_DIR)) + goto exit; + + if (idx >= 0) subname = nextname; - } } ret = get_contents(mydata, dentptr, buffer, maxsize); diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c index 1facfaf182d..cb288d60f56 100644 --- a/fs/reiserfs/dev.c +++ b/fs/reiserfs/dev.c @@ -25,24 +25,13 @@ #include "reiserfs_private.h" static block_dev_desc_t *reiserfs_block_dev_desc; -static disk_partition_t part_info; +static disk_partition_t *part_info; -int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part) +void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) { reiserfs_block_dev_desc = rbdd; - - if (part == 0) { - /* disk doesn't use partition table */ - part_info.start = 0; - part_info.size = rbdd->lba; - part_info.blksz = rbdd->blksz; - } else { - if (get_partition_info (reiserfs_block_dev_desc, part, &part_info)) { - return 0; - } - } - return (part_info.size); + part_info = info; } @@ -59,7 +48,7 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) */ if (sector < 0 || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) - >= part_info.size)) { + >= part_info->size)) { /* errnum = ERR_OUTSIDE_PART; */ printf (" ** reiserfs_devread() read outside partition\n"); return 0; @@ -83,7 +72,8 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) if (byte_offset != 0) { /* read first part which isn't aligned with start of sector */ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info.start+sector, 1, (unsigned long *)sec_buf) != 1) { + part_info->start + sector, 1, + (unsigned long *)sec_buf) != 1) { printf (" ** reiserfs_devread() read error\n"); return 0; } @@ -96,8 +86,8 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) /* read sector aligned part */ block_len = byte_len & ~(SECTOR_SIZE-1); if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info.start+sector, block_len/SECTOR_SIZE, (unsigned long *)buf) != - block_len/SECTOR_SIZE) { + part_info->start + sector, block_len/SECTOR_SIZE, + (unsigned long *)buf) != block_len/SECTOR_SIZE) { printf (" ** reiserfs_devread() read error - block\n"); return 0; } @@ -108,7 +98,8 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) if ( byte_len != 0 ) { /* read rest of data which are not in whole sector */ if (reiserfs_block_dev_desc->block_read(reiserfs_block_dev_desc->dev, - part_info.start+sector, 1, (unsigned long *)sec_buf) != 1) { + part_info->start + sector, 1, + (unsigned long *)sec_buf) != 1) { printf (" ** reiserfs_devread() read error - last part\n"); return 0; } diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index c68802bc8d1..44be3f53e07 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -37,8 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; static int gzip_decompress(const unsigned char *in, size_t in_len, unsigned char *out, size_t *out_len) { - unsigned long len = in_len; - return zunzip(out, *out_len, (unsigned char *)in, &len, 0, 0); + return zunzip(out, *out_len, (unsigned char *)in, + (unsigned long *)out_len, 0, 0); } /* Fake description object for the "none" compressor */ diff --git a/fs/zfs/dev.c b/fs/zfs/dev.c index d68372c8089..36be8f5c807 100644 --- a/fs/zfs/dev.c +++ b/fs/zfs/dev.c @@ -26,23 +26,12 @@ #include <zfs_common.h> static block_dev_desc_t *zfs_block_dev_desc; -static disk_partition_t part_info; +static disk_partition_t *part_info; -int zfs_set_blk_dev(block_dev_desc_t *rbdd, int part) +void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info) { zfs_block_dev_desc = rbdd; - - if (part == 0) { - /* disk doesn't use partition table */ - part_info.start = 0; - part_info.size = rbdd->lba; - part_info.blksz = rbdd->blksz; - } else { - if (get_partition_info(zfs_block_dev_desc, part, &part_info)) - return 0; - } - - return part_info.size; + part_info = info; } /* err */ @@ -57,7 +46,7 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) */ if ((sector < 0) || ((sector + ((byte_offset + byte_len - 1) >> SECTOR_BITS)) >= - part_info.size)) { + part_info->size)) { /* errnum = ERR_OUTSIDE_PART; */ printf(" ** zfs_devread() read outside partition sector %d\n", sector); return 1; @@ -79,8 +68,8 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) if (byte_offset != 0) { /* read first part which isn't aligned with start of sector */ if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info.start + sector, 1, - (unsigned long *) sec_buf) != 1) { + part_info->start + sector, 1, + (unsigned long *)sec_buf) != 1) { printf(" ** zfs_devread() read error **\n"); return 1; } @@ -102,17 +91,15 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) block_len = SECTOR_SIZE; zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info.start + sector, - 1, (unsigned long *)p); + part_info->start + sector, + 1, (unsigned long *)p); memcpy(buf, p, byte_len); return 0; } if (zfs_block_dev_desc->block_read(zfs_block_dev_desc->dev, - part_info.start + sector, - block_len / SECTOR_SIZE, - (unsigned long *) buf) != - block_len / SECTOR_SIZE) { + part_info->start + sector, block_len / SECTOR_SIZE, + (unsigned long *) buf) != block_len / SECTOR_SIZE) { printf(" ** zfs_devread() read error - block\n"); return 1; } @@ -126,7 +113,7 @@ int zfs_devread(int sector, int byte_offset, int byte_len, char *buf) /* read rest of data which are not in whole sector */ if (zfs_block_dev_desc-> block_read(zfs_block_dev_desc->dev, - part_info.start + sector, 1, + part_info->start + sector, 1, (unsigned long *) sec_buf) != 1) { printf(" ** zfs_devread() read error - last part\n"); return 1; diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index c19e16cd21d..23c96494031 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -94,4 +94,13 @@ int gpio_get_value(unsigned gpio); */ int gpio_set_value(unsigned gpio, int value); +/** + * Request a gpio. This should be called before any of the other functions + * are used on this gpio. + * + * @param gp GPIO number + * @param label User label for this GPIO + * @return 0 if ok, -1 on error + */ +int gpio_request(unsigned gpio, const char *label); #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/command.h b/include/command.h index 6e1bdc2ab27..1f06aa18190 100644 --- a/include/command.h +++ b/include/command.h @@ -110,6 +110,10 @@ static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd) return 0; } #endif + +extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc, + char *const argv[]); + extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); /* diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 0d09f0ec614..45d10645578 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Freescale MCF5373 FireEngine board. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -59,7 +59,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_CMD_NAND #endif @@ -208,7 +208,7 @@ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 @@ -264,9 +264,9 @@ #define CONFIG_SYS_CS1_MASK 0x001f0001 #define CONFIG_SYS_CS1_CTRL 0x002A3780 -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE #define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) #define CONFIG_SYS_CS2_CTRL 0x00001f60 #endif diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 7f2761c5391..2d48dde8084 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -37,6 +37,24 @@ #define CONFIG_MISC_INIT_R +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 + +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ESDHC_USE_PIO + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * On-board devices * @@ -340,6 +358,19 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 +/* + * SPI on header J8 + * + * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) + * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. + */ +#ifdef CONFIG_MPC8XXX_SPI +#define CONFIG_CMD_SPI +#define CONFIG_USE_SPIFLASH +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#endif /* * Board info - revision and where boot from diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1c0eb740175..31696655bbe 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -22,7 +22,7 @@ /* * P2041 RDB board configuration file - * + * Also supports P2040 RDB */ #ifndef __CONFIG_H #define __CONFIG_H @@ -36,6 +36,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -73,7 +82,7 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -#ifndef CONFIG_RAMBOOT_PBL +#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_NOWHERE #endif #else @@ -104,8 +113,12 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) - #define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ @@ -374,6 +387,35 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI @@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy); #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h deleted file mode 100644 index 8006547000d..00000000000 --- a/include/configs/P3060QDS.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * P3060 QDS board configuration file - */ -#define CONFIG_P3060QDS -#define CONFIG_PHYS_64BIT -#define CONFIG_PPC_P3060 -#define CONFIG_FSL_QIXIS - -#define CONFIG_NAND_FSL_ELBC - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_EON -#define CONFIG_SPI_FLASH_SST - -#include "corenet_ds.h" - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - -/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */ -#define CONFIG_I2C_MUX -#define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 4a2e47513d6..d6f2f5ceb89 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -22,6 +22,7 @@ /* * P4080 DS board configuration file + * Also supports P4040 DS */ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 4afc4f16ed1..8625f762902 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -22,7 +22,7 @@ /* * P5020 DS board configuration file - * + * Also supports P5010 DS */ #define CONFIG_P5020DS #define CONFIG_PHYS_64BIT diff --git a/include/configs/apollon.h b/include/configs/apollon.h deleted file mode 100644 index b8ca8a849fa..00000000000 --- a/include/configs/apollon.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Samsung Electronics, - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Configuration settings for the 2420 Samsung Apollon board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420_APOLLON 1 -#define CONFIG_APOLLON 1 -#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */ - -#define CONFIG_ONENAND_U_BOOT y - -/* Clock config to target*/ -#define PRCM_CONFIG_I 1 -/* #define PRCM_CONFIG_II 1 */ - -/* Boot method */ -/* uncomment if you use NOR boot */ -/* #define CONFIG_SYS_NOR_BOOT 1 */ - -/* uncomment if you use NOR on CS3 */ -/* #define CONFIG_SYS_USE_NOR 1 */ - -#ifdef CONFIG_SYS_NOR_BOOT -#undef CONFIG_SYS_USE_NOR -#define CONFIG_SYS_USE_NOR 1 -#endif - -/* uncommnet if you want to use UBI */ -#define CONFIG_SYS_USE_UBI - -#include <asm/arch/omap2420.h> /* get chip and board defs */ - -#define V_SCLK 12000000 - -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE_FLEX SZ_256K -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M) - -/* - * Hardware drivers - */ - -/* - * SMC91c96 Etherent - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300) -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ONENAND - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_UBI -#define CONFIG_RBTREE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS -#endif - -#undef CONFIG_CMD_SOURCE - -#ifndef CONFIG_SYS_USE_NOR -# undef CONFIG_CMD_FLASH -# undef CONFIG_CMD_IMLS -#endif - -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.116.25 -#define CONFIG_SERVERIP 192.168.116.1 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_ETHADDR 00:0E:99:00:24:20 - -#ifdef CONFIG_APOLLON_PLUS -#define CONFIG_SYS_MEM "mem=64M" -#else -#define CONFIG_SYS_MEM "mem=128" -#endif - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_SYS_UBI "ubi.mtd=4" -#else -#define CONFIG_SYS_UBI "" -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \ - " console=ttyS0,115200n8" \ - " ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \ - "apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \ - CONFIG_SYS_UBI - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "Image=tftp 0x80008000 Image; go 0x80008000\0" \ - "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \ - "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \ - "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \ - "xloader=tftp 0x80180000 x-load.bin; " \ - " cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \ - "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \ - "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \ - "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \ - "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \ - "onesyncboot=run syncmode oneboot\0" \ - "updateb=tftp 0x80180000 u-boot-onenand.bin; " \ - " onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \ - "ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \ - "bootcmd=run uboot\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Apollon # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) - -/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) - * or by 32KHz clk, or from external sig. This rate is divided by a local - * divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_128M -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_SYS_USE_NOR -/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */ -# define CONFIG_SYS_FLASH_BASE 0x18000000 -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_MAX_FLASH_SECT 1024 -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* Flash memory is CFI compliant */ -# define CONFIG_SYS_FLASH_CFI 1 -# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -/* Use buffered writes (~10x faster) */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ -/* Use h/w sector protection*/ -# define CONFIG_SYS_FLASH_PROTECTION 1 - -#else /* !CONFIG_SYS_USE_NOR */ -# define CONFIG_SYS_NO_FLASH 1 -#endif /* CONFIG_SYS_USE_NOR */ - -/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */ -#define CONFIG_SYS_ONENAND_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */ -#define CONFIG_ENV_IS_IN_ONENAND 1 -#define CONFIG_ENV_ADDR 0x00020000 -#define CONFIG_ENV_ADDR_FLEX 0x00040000 - -#ifdef CONFIG_SYS_USE_UBI -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "onenand0=onenand" -#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \ - "128k(params)," \ - "2m(kernel)," \ - "16m(rootfs)," \ - "32m(fs)," \ - "-(ubifs)" -#endif - -#define PHYS_SRAM 0x4020F800 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h new file mode 100644 index 00000000000..f85374f8820 --- /dev/null +++ b/include/configs/atngw100mkii.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/hardware.h> + +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_ATNGW100MKII + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER +#define CONFIG_SYS_OSC0_HZ 20000000 +#define CONFIG_SYS_PLL0_DIV 1 +#define CONFIG_SYS_PLL0_MUL 7 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz + */ +#define CONFIG_SYS_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz + */ +#define CONFIG_SYS_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz + */ +#define CONFIG_SYS_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz + */ +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* Reserve VM regions for NOR flash, NAND flash and SDRAM */ +#define CONFIG_SYS_NR_VM_REGIONS 3 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x04 + +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "root=mtd:main rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload 0x10400000 /uImage; bootm" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_MII + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 +#define CONFIG_ATMEL_SPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x800000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 65536 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f8f7a82aa96..f4f9bd12a4c 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -31,13 +31,21 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#if defined(CONFIG_P3041DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg +#elif defined(CONFIG_P4080DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg +#elif defined(CONFIG_P5020DS) +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg +#endif #endif -#ifdef CONFIG_SRIOBOOT_SLAVE +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_NO_FLASH #endif @@ -77,7 +85,7 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) #define CONFIG_ENV_IS_NOWHERE #endif #else @@ -108,7 +116,7 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIOBOOT_SLAVE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 #define CONFIG_ENV_SIZE 0x2000 @@ -186,11 +194,7 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#ifdef CONFIG_P3060QDS -#define CONFIG_SYS_SPD_BUS_NUM 0 -#else #define CONFIG_SYS_SPD_BUS_NUM 1 -#endif #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -389,51 +393,32 @@ #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* - * SRIOBOOT - MASTER - */ -#ifdef CONFIG_SRIOBOOT_MASTER -/* master port for srioboot*/ -#define CONFIG_SRIOBOOT_MASTER_PORT 0 -/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ -/* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull -#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull /* - * for slave UCODE instored in master memory space, + * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull -#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull -#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ -/* - * for slave ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull -#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull -#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + /* slave core release by master*/ -#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF -#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ -#endif +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* - * SRIOBOOT - SLAVE + * SRIO_PCIE_BOOT - SLAVE */ -#ifdef CONFIG_SRIOBOOT_SLAVE -/* slave port for srioboot */ -#define CONFIG_SRIOBOOT_SLAVE_PORT0 -/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ -#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* @@ -556,13 +541,13 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIOBOOT_SLAVE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing * in two corenet boards, slave's ucode could be stored in master's memory * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO outbound window->master inbound window->master LAW-> - * the ucode address in master's NOR flash. + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 @@ -724,7 +709,7 @@ #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) +#ifdef CONFIG_P4080DS #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index d4104de5f25..9371ec31f33 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -44,7 +44,12 @@ #define MACH_TYPE_EB_CPUX9K2 1977 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 /*--------------------------------------------------------------------------*/ -#define CONFIG_SYS_TEXT_BASE 0x00000000 +#ifndef CONFIG_RAMBOOT +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x21f00000 +#endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index f0fb48828ae..f2cfaf8350e 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -69,13 +69,18 @@ * - GPIO16 is Power LED control (0 = on, 1 = off) * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - Last GPIO is 26, further bits are supposed to be 0. + * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) + * - GPIO22 is SATA disk power status () + * - GPIO23 is supply status for SATA disk () + * - GPIO24 is supply control for board (write 1 to power off) + * Last GPIO is 25, further bits are supposed to be 0. * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON. + * Default is LED ON, board ON :) */ -#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff -#define ORION5X_GPIO_OUT_VALUE 0x03fcffff +#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca +#define ORION5X_GPIO_OUT_VALUE 0x00000000 +#define ORION5X_GPIO_IN_POLARITY 0x000000d0 /* * NS16550 Configuration diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 4350518939c..46171b98f01 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -213,7 +212,6 @@ * NAND FLASH driver setup */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d0555c16300..e407ff4ca53 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -34,15 +34,15 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Harmony) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Harmony" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA20_ENABLE_UARTA +#ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ #define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif @@ -62,8 +62,15 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE + +/* Environment in NAND (which is 512M), aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ #define CONFIG_USB_EHCI @@ -80,6 +87,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h index 567061aee30..dbc59b91e98 100644 --- a/include/configs/ima3-mx53.h +++ b/include/configs/ima3-mx53.h @@ -64,7 +64,6 @@ /* Ethernet on FEC */ #define CONFIG_NET_MULTI #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_MXC #define IMX_FEC_BASE FEC_BASE_ADDR @@ -72,7 +71,7 @@ #define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR #define CONFIG_RESET_PHY_R #define CONFIG_FEC_MXC_NO_ANEG -#define CONFIG_PRIME "FEC0" +#define CONFIG_ETHPRIME "FEC0" /* SPI */ #define CONFIG_HARD_SPI diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 8cca4785780..6ae764a2d4a 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index b21621ca9e2..f36ceea57f6 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -33,7 +33,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h new file mode 100644 index 00000000000..564b418fa75 --- /dev/null +++ b/include/configs/integrator-common.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2012 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Common ARM Integrator configuration settings + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define CONFIG_INTEGRATOR + +#define CONFIG_SYS_TEXT_BASE 0x01000000 +#define CONFIG_SYS_MEMTEST_START 0x100000 +#define CONFIG_SYS_MEMTEST_END 0x10000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ + +/* + * There are various dependencies on the core module (CM) fitted + * Users should refer to their CM user guide + */ +#include "armcoremodule.h" + +/* + * Initialize and remap the core module, use SPD to detect memory size + * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & + * the core module has a CM_INIT register + * then the U-Boot initialisation code will + * e.g. ARM Boot Monitor or pre-loader is repeated once + * (to re-initialise any existing CM_INIT settings to safe values). + * + * This is usually not the desired behaviour since the platform + * will either reboot into the ARM monitor (or pre-loader) + * or continuously cycle thru it without U-Boot running, + * depending upon the setting of Integrator/CP switch S2-4. + * + * However it may be needed if Integrator/CP switch S2-1 + * is set OFF to boot direct into U-Boot. + * In that case comment out the line below. + */ +#define CONFIG_CM_INIT +#define CONFIG_CM_REMAP +#define CONFIG_CM_SPD_DETECT + +/* + * The ARM boot monitor initializes the board. + * However, the default U-Boot code also performs the initialization. + * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT + * - see documentation supplied with board for details of how to choose the + * image to run at reset/power up + * e.g. whether the ARM Boot Monitor runs before U-Boot + */ +/* #define CONFIG_SKIP_LOWLEVEL_INIT */ + +/* + * The ARM boot monitor does not relocate U-Boot. + * However, the default U-Boot code performs the relocation check, + * and may relocate the code if the memory map is changed. + * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT + */ +/* #define SKIP_CONFIG_RELOCATE_UBOOT */ + + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2770c82b599..c6907b51284 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -31,32 +31,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_INTEGRATOR +#include "integrator-common.h" + +/* Integrator/AP-specific configuration */ #define CONFIG_ARCH_INTEGRATOR -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_TEXT_BASE 0x01000000 -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_CM_INIT 1 -#define CONFIG_CM_REMAP 1 -#define CONFIG_CM_SPD_DETECT - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * PL010 Configuration @@ -90,29 +69,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_FLASH_BASE 0x24000000 diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index d5043df6f03..ca02a6f1d6b 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -31,32 +31,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Integrator-specific configuration */ -#define CONFIG_INTEGRATOR -#define CONFIG_ARCH_CINTEGRATOR -#define CONFIG_CM_INIT -#define CONFIG_CM_REMAP -#define CONFIG_CM_SPD_DETECT +#include "integrator-common.h" -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_TEXT_BASE 0x01000000 -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ 1000 +/* Integrator CP-specific configuration */ +#define CONFIG_ARCH_CINTEGRATOR #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ -#define CONFIG_SYS_TIMERBASE 0x13000100 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * Hardware drivers @@ -66,9 +45,7 @@ #define CONFIG_SMC91111_BASE 0xC8000000 #undef CONFIG_SMC91111_EXT_PHY -/* - * NS16550 Configuration - */ +/* PL011 configuration */ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 14745600 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 } @@ -77,16 +54,6 @@ #define CONFIG_SYS_SERIAL0 0x16000000 #define CONFIG_SYS_SERIAL1 0x17000000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* * Command line configuration. */ @@ -102,32 +69,10 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- +/* * FLASH and environment organization - * Top varies according to amount fitted * Reserve top 4 blocks of flash * - ARM Boot Monitor @@ -136,7 +81,6 @@ * - U-Boot environment * * Base is always 0x24000000 - */ #define CONFIG_SYS_FLASH_BASE 0x24000000 #define CONFIG_SYS_FLASH_CFI 1 @@ -178,53 +122,4 @@ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #define CONFIG_ENV_SIZE 8192 /* 8KB */ -/* - * The ARM boot monitor initializes the board. - * However, the default U-Boot code also performs the initialization. - * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT - * - see documentation supplied with board for details of how to choose the - * image to run at reset/power up - * e.g. whether the ARM Boot Monitor runs before U-Boot - -#define CONFIG_SKIP_LOWLEVEL_INIT - - */ - -/* - * The ARM boot monitor does not relocate U-Boot. - * However, the default U-Boot code performs the relocation check, - * and may relocate the code if the memory map is changed. - * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT - -#define SKIP_CONFIG_RELOCATE_UBOOT - - */ -/*----------------------------------------------------------------------- - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - * - when porting adjust u-boot/Makefile accordingly - * to define the necessary CONFIG_ s for the CM involved - * see e.g. cp_926ejs_config - */ - -#include "armcoremodule.h" - -/* - * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & - * the core module has a CM_INIT register - * then the U-Boot initialisation code will - * e.g. ARM Boot Monitor or pre-loader is repeated once - * (to re-initialise any existing CM_INIT settings to safe values). - * - * This is usually not the desired behaviour since the platform - * will either reboot into the ARM monitor (or pre-loader) - * or continuously cycle thru it without U-Boot running, - * depending upon the setting of Integrator/CP switch S2-4. - * - * However it may be needed if Integrator/CP switch S2-1 - * is set OFF to boot direct into U-Boot. - * In that case comment out the line below. -#undef CONFIG_CM_INIT - */ - #endif /* __CONFIG_H */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 7ed99587a24..99831047327 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -81,7 +81,6 @@ #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE -#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 27b77d3dabe..44d5373968c 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,10 +57,14 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */ +/* SPI NOR Flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 8100000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MAX_HZ 8100000 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index d0f2b481d51..9eb2a547fc4 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -171,9 +171,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=gpmi-nand.0" +#define MTDIDS_DEFAULT "nand0=gpmi-nand" #define MTDPARTS_DEFAULT \ - "mtdparts=gpmi-nand.0:" \ + "mtdparts=gpmi-nand:" \ "3m(bootloader)ro," \ "512k(environment)," \ "512k(redundant-environment)," \ diff --git a/include/configs/medcom.h b/include/configs/medcom.h index bce03a49fab..678b36b6cff 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -35,11 +35,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Medcom) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Medcom" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F @@ -78,6 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 1266cf72faf..721cd906adb 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -115,19 +115,11 @@ #endif /* timer */ -#ifdef XILINX_TIMER_BASEADDR -# if (XILINX_TIMER_IRQ != -1) -# define CONFIG_SYS_TIMER_0 1 +#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -# define FREQUENCE XILINX_CLOCK_FREQ -# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -# endif -#elif XILINX_CLOCK_FREQ -# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -# error BAD CLOCK FREQ #endif + /* FSL */ /* #define CONFIG_SYS_FSL_2 */ /* #define FSL_INTR_2 1 */ diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 5db6d576664..8d35943fa0f 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -2,6 +2,9 @@ * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * + * + * Configuration settings for the Teejet mt_ventoux board. + * * Copyright (C) 2009 TechNexion Ltd. * * This program is free software; you can redistribute it and/or modify @@ -24,6 +27,10 @@ #include "tam3517-common.h" +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ + 6 * 1024 * 1024) + #define MACH_TYPE_AM3517_MT_VENTOUX 3832 #define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX @@ -31,6 +38,7 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_AUTO_COMPLETE +#define CONFIG_OMAP3_GPIO_4 #define CONFIG_HOSTNAME mt_ventoux /* @@ -62,6 +70,15 @@ #define CONFIG_FPGA_DELAY() udelay(1) #define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_OMAP3 /* DSS Support */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ "bootcmd=run net_nfs\0" diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 359a3083054..96c143efb97 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -17,7 +17,6 @@ /* High Level Configuration Options */ -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x81200000 diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 4e1e6bc0a85..dffb744c3dc 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -184,6 +184,9 @@ #define CONFIG_EHCI_MXS_PORT 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX #endif /* I2C */ @@ -199,6 +202,7 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI #define CONFIG_MXS_SPI +#define CONFIG_MXS_SPI_DMA_ENABLE #define CONFIG_SPI_HALF_DUPLEX #define CONFIG_DEFAULT_SPI_BUS 2 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 @@ -235,7 +239,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_net" #define CONFIG_LOADADDR 0x42000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_OF_LIBFDT @@ -244,13 +247,80 @@ * Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "console_fsl=console=ttyAM0" \ - "console_mainline=console=ttyAMA0" \ - "netargs=setenv bootargs console=${console_mainline}" \ + "update_nand_full_filename=u-boot.nand\0" \ + "update_nand_firmware_filename=u-boot.sb\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_nand_firmware_maxsz=0x100000\0" \ + "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ + "nand device 0 ; " \ + "nand info ; " \ + "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ + "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ + "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "if tftp ${update_nand_full_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "nand scrub -y 0x0 ${filesize} ; " \ + "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \ + "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ + "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ + "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ + "fi\0" \ + "update_nand_firmware=" /* Update only firmware */ \ + "if tftp ${update_nand_firmware_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ + "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ + "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ + "nand erase ${fcb_sz} ${fw_sz} ; " \ + "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ + "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console_fsl=ttyAM0\0" \ + "console_mainline=ttyAMA0\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \ - "bootcmd_net=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" #endif /* __MX28EVK_CONFIG_H__ */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 081fbf69058..9d9f4a78229 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -27,8 +27,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 17d3143eba8..b272674f820 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -35,8 +35,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 9bc6bd44705..69bd654b9f5 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -31,7 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_DISPLAY_CPUINFO @@ -111,6 +110,12 @@ #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_CMD_DATE +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ @@ -231,13 +236,19 @@ * NAND FLASH driver setup */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE +/* mmc driver */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + /* * Default environment and default scripts * to update uboot and load kernel @@ -279,8 +290,8 @@ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +40000;" \ - "erase ${uboot_addr} +40000;" \ + "update=protect off ${uboot_addr} +80000;" \ + "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ "upd=if run load;then echo Updating u-boot;if run update;" \ "then echo U-Boot updated;" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a8882d49da4..b18f4a0ec55 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -31,7 +31,7 @@ #endif #if defined(CONFIG_P1020MBG) -#define CONFIG_BOARDNAME "P1020MBG" +#define CONFIG_BOARDNAME "P1020MBG-PC" #define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC @@ -41,7 +41,7 @@ #endif #if defined(CONFIG_P1020UTM) -#define CONFIG_BOARDNAME "P1020UTM" +#define CONFIG_BOARDNAME "P1020UTM-PC" #define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 @@ -49,7 +49,7 @@ #endif #if defined(CONFIG_P1020RDB) -#define CONFIG_BOARDNAME "P1020RDB" +#define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 #define CONFIG_SPI_FLASH @@ -64,7 +64,7 @@ #endif #if defined(CONFIG_P1021RDB) -#define CONFIG_BOARDNAME "P1021RDB" +#define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1021 #define CONFIG_QE @@ -111,7 +111,7 @@ #endif #if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB" +#define CONFIG_BOARDNAME "P2020RDB-PCA" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P2020 #define CONFIG_SPI_FLASH diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 0eb9f3b6045..24cda4839ee 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -27,11 +27,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Paz00) MOD # " -#define CONFIG_TEGRA20_BOARD_STRING "Compal Paz00" +#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA +#define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 @@ -51,8 +51,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -68,6 +69,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 42291d4e28b..65b42edc270 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -35,11 +35,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Plutux) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Plutux" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F @@ -78,6 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 306c17336e6..b8b970504f5 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -100,7 +100,12 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "qemu-mips # " /* Monitor Command Prompt */ +/* Monitor Command Prompt */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "qemu-mipsel # " +#else +#define CONFIG_SYS_PROMPT "qemu-mips # " +#endif #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h index a3fc465e709..4bb5bbc6979 100644 --- a/include/configs/qi_lb60.h +++ b/include/configs/qi_lb60.h @@ -11,6 +11,7 @@ #define __CONFIG_QI_LB60_H #define CONFIG_MIPS32 /* MIPS32 CPU core */ +#define CONFIG_SYS_LITTLE_ENDIAN #define CONFIG_JZSOC /* Jz SoC */ #define CONFIG_JZ4740 /* Jz4740 SoC */ #define CONFIG_NAND_JZ4740 diff --git a/include/configs/qong.h b/include/configs/qong.h index 485e1b1f043..c2bd09729da 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -28,8 +28,6 @@ #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ #define CONFIG_MX31 /* in a mx31 */ #define CONFIG_QONG -#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */ -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 0ebdfb8217d..f5dc3930209 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -39,8 +39,6 @@ #include <asm/arch/regs-base.h> #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index afc4a855bf0..de19e38deb4 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,7 +27,7 @@ #include <asm/sizes.h> /* LP0 suspend / resume */ -#define CONFIG_TEGRA20_LP0 +#define CONFIG_TEGRA_LP0 #define CONFIG_AES #define CONFIG_TEGRA_PMU #define CONFIG_TPS6586X_POWER @@ -42,11 +42,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (SeaBoard) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ @@ -77,8 +77,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -95,14 +96,23 @@ #define CONFIG_CMD_DHCP /* Enable keyboard */ -#define CONFIG_TEGRA20_KEYBOARD +#define CONFIG_TEGRA_KEYBOARD #define CONFIG_KEYBOARD -#undef TEGRA20_DEVICE_SETTINGS -#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#undef TEGRA_DEVICE_SETTINGS +#define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ + "stdout=serial\0" \ + "stderr=serial\0" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Somewhat oddly, the NAND base address must be a config option */ +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index a2a0156a652..a881eef300e 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -59,6 +59,7 @@ #define CONFIG_INITRD_TAG /* pass initrd param to kernel */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */ +#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */ #define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ /* setting board specific options */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 375265d475b..a13fd937621 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -124,6 +124,7 @@ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_PING #define CONFIG_CMD_USB +#define CONFIG_CMD_EEPROM #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ #undef CONFIG_CMD_IMLS @@ -134,6 +135,9 @@ #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 #define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CONFIG_DRIVER_OMAP34XX_I2C @@ -347,4 +351,66 @@ "fi;" \ "else echo U-Boot not downloaded..exiting;fi\0" \ + +/* + * this is common code for all TAM3517 boards. + * MAC address is stored from manufacturer in + * I2C EEPROM + */ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) + +/* + * The I2C EEPROM on the TAM3517 contains + * mac address and production data + */ +struct tam3517_module_info { + char customer[48]; + char product[48]; + + /* + * bit 0~47 : sequence number + * bit 48~55 : week of year, from 0. + * bit 56~63 : year + */ + unsigned long long sequence_number; + + /* + * bit 0~7 : revision fixed + * bit 8~15 : revision major + * bit 16~31 : TNxxx + */ + unsigned int revision; + unsigned char eth_addr[4][8]; + unsigned char _rev[100]; +}; + +#define TAM3517_READ_MAC_FROM_EEPROM \ +do { \ + struct tam3517_module_info info;\ + char buf[80], ethname[20]; \ + int i; \ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ + (void *)&info, sizeof(info))) \ + break; \ + memset(buf, 0, sizeof(buf)); \ + for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) { \ + sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ + info.eth_addr[i][5], \ + info.eth_addr[i][4], \ + info.eth_addr[i][3], \ + info.eth_addr[i][2], \ + info.eth_addr[i][1], \ + info.eth_addr[i][0]); \ + \ + if (i) \ + sprintf(ethname, "eth%daddr", i); \ + else \ + sprintf(ethname, "ethaddr"); \ + printf("Setting %s from EEPROM with %s\n", ethname, buf);\ + setenv(ethname, buf); \ + } \ +} while (0) +#endif + #endif /* __TAM3517_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 9b3f88dff86..d5da3c7a88c 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -35,24 +35,32 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (TEC) # " -#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" +#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" #define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ENV_IS_NOWHERE - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE + +/* Environment in NAND, aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ + /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA @@ -79,6 +87,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra20-common-post.h b/include/configs/tegra-common-post.h index 42f270f7bcd..168b64be52f 100644 --- a/include/configs/tegra20-common-post.h +++ b/include/configs/tegra-common-post.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __TEGRA20_COMMON_POST_H -#define __TEGRA20_COMMON_POST_H +#ifndef __TEGRA_COMMON_POST_H +#define __TEGRA_COMMON_POST_H #ifdef CONFIG_BOOTCOMMAND @@ -141,7 +141,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - TEGRA20_DEVICE_SETTINGS \ + TEGRA_DEVICE_SETTINGS \ "fdt_load=0x01000000\0" \ "fdt_high=01100000\0" \ BOOTCMDS_COMMON @@ -174,8 +174,8 @@ #ifdef CONFIG_GENERIC_MMC #undef CONFIG_GENERIC_MMC #endif -#ifdef CONFIG_TEGRA20_MMC -#undef CONFIG_TEGRA20_MMC +#ifdef CONFIG_TEGRA_MMC +#undef CONFIG_TEGRA_MMC #endif #ifdef CONFIG_CMD_MMC #undef CONFIG_CMD_MMC @@ -211,4 +211,4 @@ #endif /* CONFIG_SPL_BUILD */ -#endif /* __TEGRA20_COMMON_POST_H */ +#endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 4c02f205437..098cdb4460d 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -54,7 +54,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ -#ifdef CONFIG_TEGRA20_LP0 +#ifdef CONFIG_TEGRA_LP0 #define TEGRA_LP0_ADDR 0x1C406000 #define TEGRA_LP0_SIZE 0x2000 #define TEGRA_LP0_VEC \ @@ -132,9 +132,9 @@ /* Environment information, boards can override if required */ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" +#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ @@ -157,7 +157,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ @@ -169,7 +169,7 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0 +#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 @@ -201,4 +201,6 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" +#define CONFIG_SYS_NAND_SELF_INIT + #endif /* __TEGRA20_COMMON_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index f8da9c01c2e..b3b5a3d5e31 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -78,6 +78,7 @@ #define CONFIG_MMC #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI +#define CONFIG_MMC_SDMA /* PWM */ #define CONFIG_PWM @@ -211,18 +212,28 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_CACHELINE_SIZE 32 -#include <asm/arch/gpio.h> -/* - * I2C Settings - */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) #define CONFIG_SOFT_I2C #define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C_SPEED 50000 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS 7 +#define CONFIG_SOFT_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 15 + +#include <asm/arch/gpio.h> + +/* I2C PMIC */ +#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7) +#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6) + +/* I2C FG */ +#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1) +#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0) + +#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin() +#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin() +#define I2C_INIT multi_i2c_init() #define CONFIG_PMIC #define CONFIG_PMIC_I2C diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b3c524981f5..a46890c0947 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -34,12 +34,12 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (TrimSlice) # " -#define CONFIG_TEGRA20_BOARD_STRING "Compulab Trimslice" +#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA -#define CONFIG_TEGRA20_UARTA_GPU +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_GPU #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE @@ -94,6 +94,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tt01.h b/include/configs/tt01.h index cc68a42e86a..f46efa55f16 100644 --- a/include/configs/tt01.h +++ b/include/configs/tt01.h @@ -31,8 +31,6 @@ /* High Level Configuration Options */ #define CONFIG_ARM1136 #define CONFIG_MX31 -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c8a49bba145..71b1d326de5 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -107,7 +107,6 @@ /* NAND */ #define CONFIG_NAND_MXC -#define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (0xBB000000) diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 25ec2ebfec7..7d3a54f7432 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -34,11 +34,11 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Ventana) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Ventana" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTD +#define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA @@ -58,8 +58,9 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -75,6 +76,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h index b747d0e2b2c..6c565bae14d 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -34,12 +34,12 @@ /* High-level configuration options */ #define V_PROMPT "Tegra20 (Whistler) # " -#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Whistler" +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler" /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA20_ENABLE_UARTA -#define CONFIG_TEGRA20_UARTA_UAA_UAB +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_UAA_UAB #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER @@ -72,8 +72,9 @@ * particular card is standard practice as far as I know. */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE) #define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ #define CONFIG_USB_EHCI @@ -89,6 +90,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#include "tegra20-common-post.h" +#include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 072945ad4ab..447683a4905 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -28,7 +28,6 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_MX25 -#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0xA0000000 diff --git a/include/ddr_spd.h b/include/ddr_spd.h index a9230b9108e..9e74d8729e2 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -221,7 +221,12 @@ typedef struct ddr3_spd_eeprom_s { unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ unsigned char therm_sensor; /* 32 Module Thermal Sensor */ unsigned char device_type; /* 33 SDRAM device type */ - unsigned char res_34_59[26]; /* 34-59 Reserved, General Section */ + int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */ + int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */ + int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */ + int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */ + int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */ + unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ /* Module-Specific Section: Bytes 60-116 */ union { diff --git a/include/environment.h b/include/environment.h index ae3f7b6aedf..e8ab7033bf7 100644 --- a/include/environment.h +++ b/include/environment.h @@ -181,9 +181,21 @@ void env_crc_update(void); /* [re]set to the default environment */ void set_default_env(const char *s); +/* [re]set individual variables to their value in the default environment */ +int set_default_vars(int nvars, char * const vars[]); + /* Import from binary representation into hash table */ int env_import(const char *buf, int check); +/* + * Check if variable "name" can be changed from oldval to newval, + * and if so, apply the changes (e.g. baudrate). + * When (flag & H_FORCE) is set, it does not print out any error + * message and forces overwriting of write-once variables. + */ +int env_check_apply(const char *name, const char *oldval, + const char *newval, int flag); + #endif /* DO_DEPS_ONLY */ #endif /* _ENVIRONMENT_H_ */ diff --git a/include/ext2fs.h b/include/ext2fs.h deleted file mode 100644 index 163a9bbc0e0..00000000000 --- a/include/ext2fs.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * GRUB -- GRand Unified Bootloader - * Copyright (C) 2000, 2001 Free Software Foundation, Inc. - * - * (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com> - * Pavel Bartusek <pba@sysgo.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* An implementation for the Ext2FS filesystem ported from GRUB. - * Some parts of this code (mainly the structures and defines) are - * from the original ext2 fs code, as found in the linux kernel. - */ - - -#define SECTOR_SIZE 0x200 -#define SECTOR_BITS 9 - -/* Error codes */ -typedef enum -{ - ERR_NONE = 0, - ERR_BAD_FILENAME, - ERR_BAD_FILETYPE, - ERR_BAD_GZIP_DATA, - ERR_BAD_GZIP_HEADER, - ERR_BAD_PART_TABLE, - ERR_BAD_VERSION, - ERR_BELOW_1MB, - ERR_BOOT_COMMAND, - ERR_BOOT_FAILURE, - ERR_BOOT_FEATURES, - ERR_DEV_FORMAT, - ERR_DEV_VALUES, - ERR_EXEC_FORMAT, - ERR_FILELENGTH, - ERR_FILE_NOT_FOUND, - ERR_FSYS_CORRUPT, - ERR_FSYS_MOUNT, - ERR_GEOM, - ERR_NEED_LX_KERNEL, - ERR_NEED_MB_KERNEL, - ERR_NO_DISK, - ERR_NO_PART, - ERR_NUMBER_PARSING, - ERR_OUTSIDE_PART, - ERR_READ, - ERR_SYMLINK_LOOP, - ERR_UNRECOGNIZED, - ERR_WONT_FIT, - ERR_WRITE, - ERR_BAD_ARGUMENT, - ERR_UNALIGNED, - ERR_PRIVILEGED, - ERR_DEV_NEED_INIT, - ERR_NO_DISK_SPACE, - ERR_NUMBER_OVERFLOW, - - MAX_ERR_NUM -} ext2fs_error_t; - - -extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part); -extern int ext2fs_ls (const char *dirname); -extern int ext2fs_open (const char *filename); -extern int ext2fs_read (char *buf, unsigned len); -extern int ext2fs_mount (unsigned part_length); -extern int ext2fs_close(void); diff --git a/include/ext4fs.h b/include/ext4fs.h new file mode 100644 index 00000000000..b6eedde3180 --- /dev/null +++ b/include/ext4fs.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Ext4 Extent data structures are taken from original ext4 fs code + * as found in the linux kernel. + * + * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com + * Written by Alex Tomas <alex@clusterfs.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT4__ +#define __EXT4__ +#include <ext_common.h> + +#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ +#define EXT4_EXT_MAGIC 0xf30a +#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 +#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 +#define EXT4_INDIRECT_BLOCKS 12 + +#define EXT4_BG_INODE_UNINIT 0x0001 +#define EXT4_BG_BLOCK_UNINIT 0x0002 +#define EXT4_BG_INODE_ZEROED 0x0004 + +/* + * ext4_inode has i_block array (60 bytes total). + * The first 12 bytes store ext4_extent_header; + * the remainder stores an array of ext4_extent. + */ + +/* + * This is the extent on-disk structure. + * It's used at the bottom of the tree. + */ +struct ext4_extent { + __le32 ee_block; /* first logical block extent covers */ + __le16 ee_len; /* number of blocks covered by extent */ + __le16 ee_start_hi; /* high 16 bits of physical block */ + __le32 ee_start_lo; /* low 32 bits of physical block */ +}; + +/* + * This is index on-disk structure. + * It's used at all the levels except the bottom. + */ +struct ext4_extent_idx { + __le32 ei_block; /* index covers logical blocks from 'block' */ + __le32 ei_leaf_lo; /* pointer to the physical block of the next * + * level. leaf or next index could be there */ + __le16 ei_leaf_hi; /* high 16 bits of physical block */ + __u16 ei_unused; +}; + +/* Each block (leaves and indexes), even inode-stored has header. */ +struct ext4_extent_header { + __le16 eh_magic; /* probably will support different formats */ + __le16 eh_entries; /* number of valid entries */ + __le16 eh_max; /* capacity of store in entries */ + __le16 eh_depth; /* has tree real underlying blocks? */ + __le32 eh_generation; /* generation of the tree */ +}; + +struct ext_filesystem { + /* Total Sector of partition */ + uint64_t total_sect; + /* Block size of partition */ + uint32_t blksz; + /* Inode size of partition */ + uint32_t inodesz; + /* Sectors per Block */ + uint32_t sect_perblk; + /* Group Descriptor Block Number */ + uint32_t gdtable_blkno; + /* Total block groups of partition */ + uint32_t no_blkgrp; + /* No of blocks required for bgdtable */ + uint32_t no_blk_pergdt; + /* Superblock */ + struct ext2_sblock *sb; + /* Block group descritpor table */ + struct ext2_block_group *gd; + char *gdtable; + + /* Block Bitmap Related */ + unsigned char **blk_bmaps; + long int curr_blkno; + uint16_t first_pass_bbmap; + + /* Inode Bitmap Related */ + unsigned char **inode_bmaps; + int curr_inode_no; + uint16_t first_pass_ibmap; + + /* Journal Related */ + + /* Block Device Descriptor */ + block_dev_desc_t *dev_desc; +}; + +extern struct ext2_data *ext4fs_root; +extern struct ext2fs_node *ext4fs_file; + +#if defined(CONFIG_CMD_EXT4_WRITE) +extern struct ext2_inode *g_parent_inode; +extern int gd_index; +extern int gindex; + +int ext4fs_init(void); +void ext4fs_deinit(void); +int ext4fs_filename_check(char *filename); +int ext4fs_write(const char *fname, unsigned char *buffer, + unsigned long sizebytes); +#endif + +struct ext_filesystem *get_fs(void); +int ext4fs_open(const char *filename); +int ext4fs_read(char *buf, unsigned len); +int ext4fs_mount(unsigned part_length); +void ext4fs_close(void); +int ext4fs_ls(const char *dirname); +void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); +int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf); +void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); +long int read_allocated_block(struct ext2_inode *inode, int fileblock); +#endif diff --git a/include/ext_common.h b/include/ext_common.h new file mode 100644 index 00000000000..ce73857f8d8 --- /dev/null +++ b/include/ext_common.h @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2011 - 2012 Samsung Electronics + * EXT4 filesystem implementation in Uboot by + * Uma Shankar <uma.shankar@samsung.com> + * Manjunatha C Achar <a.manjunatha@samsung.com> + * + * Data structures and headers for ext4 support have been taken from + * ext2 ls load support in Uboot + * + * (C) Copyright 2004 + * esd gmbh <www.esd-electronics.com> + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * based on code from grub2 fs/ext2.c and fs/fshelp.c by + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2003, 2004 Free Software Foundation, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __EXT_COMMON__ +#define __EXT_COMMON__ +#include <command.h> +#define SECTOR_SIZE 0x200 +#define SECTOR_BITS 9 + +/* Magic value used to identify an ext2 filesystem. */ +#define EXT2_MAGIC 0xEF53 +/* Amount of indirect blocks in an inode. */ +#define INDIRECT_BLOCKS 12 +/* Maximum lenght of a pathname. */ +#define EXT2_PATH_MAX 4096 +/* Maximum nesting of symlinks, used to prevent a loop. */ +#define EXT2_MAX_SYMLINKCNT 8 + +/* Filetype used in directory entry. */ +#define FILETYPE_UNKNOWN 0 +#define FILETYPE_REG 1 +#define FILETYPE_DIRECTORY 2 +#define FILETYPE_SYMLINK 7 + +/* Filetype information as used in inodes. */ +#define FILETYPE_INO_MASK 0170000 +#define FILETYPE_INO_REG 0100000 +#define FILETYPE_INO_DIRECTORY 0040000 +#define FILETYPE_INO_SYMLINK 0120000 +#define EXT2_ROOT_INO 2 /* Root inode */ + +/* Bits used as offset in sector */ +#define DISK_SECTOR_BITS 9 +/* The size of an ext2 block in bytes. */ +#define EXT2_BLOCK_SIZE(data) (1 << LOG2_BLOCK_SIZE(data)) + +/* Log2 size of ext2 block in 512 blocks. */ +#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \ + (data->sblock.log2_block_size) + 1) + +/* Log2 size of ext2 block in bytes. */ +#define LOG2_BLOCK_SIZE(data) (__le32_to_cpu \ + (data->sblock.log2_block_size) + 10) +#define INODE_SIZE_FILESYSTEM(data) (__le32_to_cpu \ + (data->sblock.inode_size)) + +#define EXT2_FT_DIR 2 +#define SUCCESS 1 + +/* Macro-instructions used to manage several block sizes */ +#define EXT2_MIN_BLOCK_LOG_SIZE 10 /* 1024 */ +#define EXT2_MAX_BLOCK_LOG_SIZE 16 /* 65536 */ +#define EXT2_MIN_BLOCK_SIZE (1 << EXT2_MIN_BLOCK_LOG_SIZE) +#define EXT2_MAX_BLOCK_SIZE (1 << EXT2_MAX_BLOCK_LOG_SIZE) + +/* The ext2 superblock. */ +struct ext2_sblock { + uint32_t total_inodes; + uint32_t total_blocks; + uint32_t reserved_blocks; + uint32_t free_blocks; + uint32_t free_inodes; + uint32_t first_data_block; + uint32_t log2_block_size; + uint32_t log2_fragment_size; + uint32_t blocks_per_group; + uint32_t fragments_per_group; + uint32_t inodes_per_group; + uint32_t mtime; + uint32_t utime; + uint16_t mnt_count; + uint16_t max_mnt_count; + uint16_t magic; + uint16_t fs_state; + uint16_t error_handling; + uint16_t minor_revision_level; + uint32_t lastcheck; + uint32_t checkinterval; + uint32_t creator_os; + uint32_t revision_level; + uint16_t uid_reserved; + uint16_t gid_reserved; + uint32_t first_inode; + uint16_t inode_size; + uint16_t block_group_number; + uint32_t feature_compatibility; + uint32_t feature_incompat; + uint32_t feature_ro_compat; + uint32_t unique_id[4]; + char volume_name[16]; + char last_mounted_on[64]; + uint32_t compression_info; +}; + +struct ext2_block_group { + __u32 block_id; /* Blocks bitmap block */ + __u32 inode_id; /* Inodes bitmap block */ + __u32 inode_table_id; /* Inodes table block */ + __u16 free_blocks; /* Free blocks count */ + __u16 free_inodes; /* Free inodes count */ + __u16 used_dir_cnt; /* Directories count */ + __u16 bg_flags; + __u32 bg_reserved[2]; + __u16 bg_itable_unused; /* Unused inodes count */ + __u16 bg_checksum; /* crc16(s_uuid+grouo_num+group_desc)*/ +}; + +/* The ext2 inode. */ +struct ext2_inode { + uint16_t mode; + uint16_t uid; + uint32_t size; + uint32_t atime; + uint32_t ctime; + uint32_t mtime; + uint32_t dtime; + uint16_t gid; + uint16_t nlinks; + uint32_t blockcnt; /* Blocks of 512 bytes!! */ + uint32_t flags; + uint32_t osd1; + union { + struct datablocks { + uint32_t dir_blocks[INDIRECT_BLOCKS]; + uint32_t indir_block; + uint32_t double_indir_block; + uint32_t triple_indir_block; + } blocks; + char symlink[60]; + } b; + uint32_t version; + uint32_t acl; + uint32_t dir_acl; + uint32_t fragment_addr; + uint32_t osd2[3]; +}; + +/* The header of an ext2 directory entry. */ +struct ext2_dirent { + uint32_t inode; + uint16_t direntlen; + uint8_t namelen; + uint8_t filetype; +}; + +struct ext2fs_node { + struct ext2_data *data; + struct ext2_inode inode; + int ino; + int inode_read; +}; + +/* Information about a "mounted" ext2 filesystem. */ +struct ext2_data { + struct ext2_sblock sblock; + struct ext2_inode *inode; + struct ext2fs_node diropen; +}; + +extern unsigned long part_offset; + +int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); +int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]); +int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index a8f783ffd50..0b140752ffb 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -19,6 +19,8 @@ * MA 02111-1307 USA */ +#ifndef __fdtdec_h +#define __fdtdec_h /* * This file contains convenience functions for decoding useful and @@ -63,6 +65,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ + COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_COUNT, }; @@ -382,3 +385,4 @@ int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name, */ const u8 *fdtdec_locate_byte_array(const void *blob, int node, const char *prop_name, int count); +#endif diff --git a/include/fm_eth.h b/include/fm_eth.h index c7c68820d57..e56541df1b7 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -35,6 +35,7 @@ enum fm_port { FM2_DTSEC2, FM2_DTSEC3, FM2_DTSEC4, + FM2_DTSEC5, FM2_10GEC1, NUM_FM_PORTS, }; @@ -109,6 +110,7 @@ void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); phy_interface_t fm_info_get_enet_if(enum fm_port port); void fm_info_set_phy_address(enum fm_port port, int address); +int fm_info_get_phy_address(enum fm_port port); void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); void fm_disable_port(enum fm_port port); diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index 279aaa55de0..ff537b49a9c 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -24,49 +24,48 @@ #define __FSL_NFC_H /* - * TODO: Use same register defs for nand_spl mxc nand driver - * and mtd mxc nand driver. + * Register map and bit definitions for the Freescale NAND Flash Controller + * present in various i.MX devices. * - * Register map and bit definitions for the Freescale NAND Flash - * Controller present in various i.MX devices. + * MX31 and MX27 have version 1, which has: + * 4 512-byte main buffers and + * 4 16-byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. * - * MX31 and MX27 have version 1 which has - * 4 512 byte main buffers and - * 4 16 byte spare buffers - * to support up to 2K byte pagesize nand. - * Reading or writing a 2K page requires 4 FDI/FDO cycles. - * - * MX25 has version 1.1 which has - * 8 512 byte main buffers and - * 8 64 byte spare buffers - * to support up to 4K byte pagesize nand. - * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. - * Also some of registers are moved and/or changed meaning as seen below. + * MX25 and MX35 have version 2.1, which has: + * 8 512-byte main buffers and + * 8 64-byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. */ -#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#if defined(CONFIG_MX27) || defined(CONFIG_MX31) #define MXC_NFC_V1 -#elif defined(CONFIG_MX25) -#define MXC_NFC_V1_1 +#define is_mxc_nfc_1() 1 +#define is_mxc_nfc_21() 0 +#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#define MXC_NFC_V2_1 +#define is_mxc_nfc_1() 0 +#define is_mxc_nfc_21() 1 #else -#warning "MXC NFC version not defined" +#error "MXC NFC implementation not supported" #endif #if defined(MXC_NFC_V1) #define NAND_MXC_NR_BUFS 4 #define NAND_MXC_SPARE_BUF_SIZE 16 #define NAND_MXC_REG_OFFSET 0xe00 -#define NAND_MXC_2K_MULTI_CYCLE 1 -#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_2K_MULTI_CYCLE +#elif defined(MXC_NFC_V2_1) #define NAND_MXC_NR_BUFS 8 #define NAND_MXC_SPARE_BUF_SIZE 64 #define NAND_MXC_REG_OFFSET 0x1e00 -#else -#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver" #endif struct fsl_nfc_regs { - u32 main_area[NAND_MXC_NR_BUFS][512/4]; - u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4]; + u8 main_area[NAND_MXC_NR_BUFS][0x200]; + u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; /* * reserved size is offset of nfc registers * minus total main and spare sizes @@ -74,44 +73,43 @@ struct fsl_nfc_regs { u8 reserved1[NAND_MXC_REG_OFFSET - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; #if defined(MXC_NFC_V1) - u16 bufsiz; + u16 buf_size; u16 reserved2; - u16 buffer_address; - u16 flash_add; + u16 buf_addr; + u16 flash_addr; u16 flash_cmd; - u16 configuration; + u16 config; u16 ecc_status_result; - u16 ecc_rslt_main_area; - u16 ecc_rslt_spare_area; - u16 nf_wr_prot; - u16 unlock_start_blk_add; - u16 unlock_end_blk_add; - u16 nand_flash_wr_pr_st; - u16 nand_flash_config1; - u16 nand_flash_config2; -#elif defined(MXC_NFC_V1_1) + u16 rsltmain_area; + u16 rsltspare_area; + u16 wrprot; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 nf_wrprst; + u16 config1; + u16 config2; +#elif defined(MXC_NFC_V2_1) u16 reserved2[2]; - u16 buffer_address; - u16 flash_add; + u16 buf_addr; + u16 flash_addr; u16 flash_cmd; - u16 configuration; - u16 ecc_status_result; - u16 ecc_status_result2; + u16 config; + u32 ecc_status_result; u16 spare_area_size; - u16 nf_wr_prot; + u16 wrprot; u16 reserved3[2]; - u16 nand_flash_wr_pr_st; - u16 nand_flash_config1; - u16 nand_flash_config2; + u16 nf_wrprst; + u16 config1; + u16 config2; u16 reserved4; - u16 unlock_start_blk_add0; - u16 unlock_end_blk_add0; - u16 unlock_start_blk_add1; - u16 unlock_end_blk_add1; - u16 unlock_start_blk_add2; - u16 unlock_end_blk_add2; - u16 unlock_start_blk_add3; - u16 unlock_end_blk_add3; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 unlockstart_blkaddr1; + u16 unlockend_blkaddr1; + u16 unlockstart_blkaddr2; + u16 unlockend_blkaddr2; + u16 unlockstart_blkaddr3; + u16 unlockend_blkaddr3; #endif }; @@ -157,7 +155,7 @@ struct fsl_nfc_regs { */ #define NFC_INT 0x8000 -#ifdef MXC_NFC_V1_1 +#ifdef MXC_NFC_V2_1 #define NFC_4_8N_ECC (1 << 0) #endif #define NFC_SP_EN (1 << 2) @@ -167,5 +165,6 @@ struct fsl_nfc_regs { #define NFC_RST (1 << 6) #define NFC_CE (1 << 7) #define NFC_ONE_CYCLE (1 << 8) +#define NFC_FP_INT (1 << 11) #endif /* __FSL_NFC_H */ diff --git a/include/i2c.h b/include/i2c.h index 1f35acf6759..16f099d2eeb 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -250,4 +250,16 @@ static inline void I2C_SET_BUS(unsigned int bus) i2c_set_bus_num(bus); } +/* Multi I2C definitions */ +enum { + I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, + I2C_8, I2C_9, I2C_10, +}; + +/* Multi I2C busses handling */ +#ifdef CONFIG_SOFT_I2C_MULTI_BUS +extern int get_multi_scl_pin(void); +extern int get_multi_sda_pin(void); +extern int multi_i2c_init(void); +#endif #endif /* _I2C_H_ */ diff --git a/include/image.h b/include/image.h index aa9daa2debd..e5f6649291e 100644 --- a/include/image.h +++ b/include/image.h @@ -164,6 +164,7 @@ #define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ +#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ /* * Compression Types diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 82704de0835..f63e04b634d 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -85,8 +85,10 @@ extern void nand_wait_ready(struct mtd_info *mtd); #define NAND_CMD_RESET 0xff #define NAND_CMD_LOCK 0x2a +#define NAND_CMD_LOCK_TIGHT 0x2c #define NAND_CMD_UNLOCK1 0x23 #define NAND_CMD_UNLOCK2 0x24 +#define NAND_CMD_LOCK_STATUS 0x7a /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 @@ -205,9 +207,6 @@ typedef enum { #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ && (chip->page_shift > 9)) -/* Mask to zero out the chip options, which come from the id table */ -#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) - /* Non chip related options */ /* * Use a flash based bad block table. OOB identifier is saved in OOB area. @@ -391,9 +390,10 @@ struct nand_ecc_ctrl { * consecutive order. */ struct nand_buffers { - uint8_t ecccalc[NAND_MAX_OOBSIZE]; - uint8_t ecccode[NAND_MAX_OOBSIZE]; - uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)]; + uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, + ARCH_DMA_MINALIGN)]; }; /** diff --git a/include/mmc.h b/include/mmc.h index 7b094a4146e..a13e2bdcf16 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -160,6 +160,7 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ /* * EXT_CSD field definitions diff --git a/include/nand.h b/include/nand.h index c554c552f59..bbe28b20bbc 100644 --- a/include/nand.h +++ b/include/nand.h @@ -141,11 +141,11 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); #define NAND_LOCK_STATUS_TIGHT 0x01 -#define NAND_LOCK_STATUS_LOCK 0x02 #define NAND_LOCK_STATUS_UNLOCK 0x04 -int nand_lock( nand_info_t *meminfo, int tight ); -int nand_unlock( nand_info_t *meminfo, ulong start, ulong length ); +int nand_lock(nand_info_t *meminfo, int tight); +int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length, + int allexcept); int nand_get_lock_status(nand_info_t *meminfo, loff_t offset); int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst); diff --git a/include/part.h b/include/part.h index e1478f4ebf4..27ea283f1ed 100644 --- a/include/part.h +++ b/include/part.h @@ -93,11 +93,15 @@ typedef struct disk_partition { ulong blksz; /* block size in bytes */ uchar name[32]; /* partition name */ uchar type[32]; /* string type description */ + int bootable; /* Active/Bootable flag is set */ +#ifdef CONFIG_PARTITION_UUIDS + char uuid[37]; /* filesystem UUID as string, if exists */ +#endif } disk_partition_t; /* Misc _get_dev functions */ #ifdef CONFIG_PARTITIONS -block_dev_desc_t* get_dev(char* ifname, int dev); +block_dev_desc_t *get_dev(const char *ifname, int dev); block_dev_desc_t* ide_get_dev(int dev); block_dev_desc_t* sata_get_dev(int dev); block_dev_desc_t* scsi_get_dev(int dev); @@ -111,8 +115,14 @@ int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t void print_part (block_dev_desc_t *dev_desc); void init_part (block_dev_desc_t *dev_desc); void dev_print(block_dev_desc_t *dev_desc); +int get_device(const char *ifname, const char *dev_str, + block_dev_desc_t **dev_desc); +int get_device_and_partition(const char *ifname, const char *dev_part_str, + block_dev_desc_t **dev_desc, + disk_partition_t *info, int allow_whole_dev); #else -static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; } +static inline block_dev_desc_t *get_dev(const char *ifname, int dev) +{ return NULL; } static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; } static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; } @@ -126,6 +136,15 @@ static inline int get_partition_info (block_dev_desc_t * dev_desc, int part, static inline void print_part (block_dev_desc_t *dev_desc) {} static inline void init_part (block_dev_desc_t *dev_desc) {} static inline void dev_print(block_dev_desc_t *dev_desc) {} +static inline int get_device(const char *ifname, const char *dev_str, + block_dev_desc_t **dev_desc) +{ return -1; } +static inline int get_device_and_partition(const char *ifname, + const char *dev_part_str, + block_dev_desc_t **dev_desc, + disk_partition_t *info, + int allow_whole_dev) +{ *dev_desc = NULL; return -1; } #endif #ifdef CONFIG_MAC_PARTITION diff --git a/include/reiserfs.h b/include/reiserfs.h index c465b3cdaf8..dc893425a53 100644 --- a/include/reiserfs.h +++ b/include/reiserfs.h @@ -75,7 +75,7 @@ typedef enum } reiserfs_error_t; -extern int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part); +extern void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); extern int reiserfs_ls (char *dirname); extern int reiserfs_open (char *filename); extern int reiserfs_read (char *buf, unsigned len); diff --git a/include/sdhci.h b/include/sdhci.h index 9d371832436..c0345ed86ef 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -76,6 +76,8 @@ #define SDHCI_SPACE_AVAILABLE 0x00000400 #define SDHCI_DATA_AVAILABLE 0x00000800 #define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_STATE_STABLE 0x00020000 +#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000 #define SDHCI_WRITE_PROTECT 0x00080000 #define SDHCI_HOST_CONTROL 0x28 @@ -87,7 +89,9 @@ #define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA64 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CD_TEST_INS 0x40 +#define SDHCI_CTRL_CD_TEST 0x80 #define SDHCI_POWER_CONTROL 0x29 #define SDHCI_POWER_ON 0x01 @@ -219,6 +223,7 @@ #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) +#define SDHCI_QUIRK_NO_CD (1 << 5) /* to make gcc happy */ struct sdhci_host; @@ -248,8 +253,10 @@ struct sdhci_host { unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; + int index; void (*set_control_reg)(struct sdhci_host *host); + void (*set_clock)(int dev_index, unsigned int div); uint voltages; }; diff --git a/include/search.h b/include/search.h index ef53edb9fef..93e1cbc6d0b 100644 --- a/include/search.h +++ b/include/search.h @@ -57,13 +57,23 @@ struct hsearch_data { struct _ENTRY *table; unsigned int size; unsigned int filled; +/* + * Callback function which will check whether the given change for variable + * "name" from "oldval" to "newval" may be applied or not, and possibly apply + * such change. + * When (flag & H_FORCE) is set, it shall not print out any error message and + * shall force overwriting of write-once variables. +.* Must return 0 for approval, 1 for denial. + */ + int (*apply)(const char *name, const char *oldval, + const char *newval, int flag); }; /* Create a new hashing table which will at most contain NEL elements. */ extern int hcreate_r(size_t __nel, struct hsearch_data *__htab); /* Destroy current internal hashing table. */ -extern void hdestroy_r(struct hsearch_data *__htab); +extern void hdestroy_r(struct hsearch_data *__htab, int do_apply); /* * Search for entry matching ITEM.key in internal hash table. If @@ -88,17 +98,25 @@ extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval, struct hsearch_data *__htab); /* Search and delete entry matching ITEM.key in internal hash table. */ -extern int hdelete_r(const char *__key, struct hsearch_data *__htab); +extern int hdelete_r(const char *__key, struct hsearch_data *__htab, + int do_apply); extern ssize_t hexport_r(struct hsearch_data *__htab, const char __sep, char **__resp, size_t __size, int argc, char * const argv[]); +/* + * nvars: length of vars array + * vars: array of strings (variable names) to import (nvars == 0 means all) + * do_apply: whether to call callback function to check the new argument, + * and possibly apply changes (false means accept everything) + */ extern int himport_r(struct hsearch_data *__htab, const char *__env, size_t __size, const char __sep, - int __flag); + int __flag, int nvars, char * const vars[], int do_apply); /* Flags for himport_r() */ -#define H_NOCLEAR 1 /* do not clear hash table before importing */ +#define H_NOCLEAR (1 << 0) /* do not clear hash table before importing */ +#define H_FORCE (1 << 1) /* overwrite read-only/write-once variables */ #endif /* search.h */ diff --git a/include/serial.h b/include/serial.h index cbdf8a9bf7e..d76d6dfb6d4 100644 --- a/include/serial.h +++ b/include/serial.h @@ -31,7 +31,8 @@ extern struct serial_device *default_serial_console(void); defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ - defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) + defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \ + defined(CONFIG_MICROBLAZE) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) diff --git a/include/zfs_common.h b/include/zfs_common.h index 04e73d0cd2a..3bd575ef5f9 100644 --- a/include/zfs_common.h +++ b/include/zfs_common.h @@ -66,9 +66,6 @@ struct zfs_filesystem { block_dev_desc_t *dev_desc; }; - -extern block_dev_desc_t *zfs_dev_desc; - struct device_s { uint64_t part_length; }; @@ -94,8 +91,6 @@ struct zfs_dirhook_info { struct zfs_filesystem *zfsget_fs(void); -int init_fs(block_dev_desc_t *dev_desc); -void deinit_fs(block_dev_desc_t *dev_desc); int zfs_open(zfs_file_t, const char *filename); uint64_t zfs_read(zfs_file_t, char *buf, uint64_t len); struct zfs_data *zfs_mount(device_t); @@ -103,7 +98,7 @@ int zfs_close(zfs_file_t); int zfs_ls(device_t dev, const char *path, int (*hook) (const char *, const struct zfs_dirhook_info *)); int zfs_devread(int sector, int byte_offset, int byte_len, char *buf); -int zfs_set_blk_dev(block_dev_desc_t *rbdd, int part); +void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); void zfs_unmount(struct zfs_data *data); int lzjb_decompress(void *, void *, uint32_t, uint32_t); #endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index af17ac1b7a1..4c23f458f0f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -42,6 +42,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"), + COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -79,11 +80,16 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, const fdt_addr_t *cell; int len; - debug("get_addr: %s\n", prop_name); + debug("%s: %s: ", __func__, prop_name); cell = fdt_getprop(blob, node, prop_name, &len); if (cell && (len == sizeof(fdt_addr_t) || - len == sizeof(fdt_addr_t) * 2)) - return fdt_addr_to_cpu(*cell); + len == sizeof(fdt_addr_t) * 2)) { + fdt_addr_t addr = fdt_addr_to_cpu(*cell); + + debug("%p\n", (void *)addr); + return addr; + } + debug("(not found)\n"); return FDT_ADDR_T_NONE; } @@ -93,10 +99,15 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, const s32 *cell; int len; - debug("get_size: %s\n", prop_name); + debug("%s: %s: ", __func__, prop_name); cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && len >= sizeof(s32)) - return fdt32_to_cpu(cell[0]); + if (cell && len >= sizeof(s32)) { + s32 val = fdt32_to_cpu(cell[0]); + + debug("%#x (%d)\n", val, val); + return val; + } + debug("(not found)\n"); return default_val; } @@ -328,6 +339,7 @@ int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name) const u32 *phandle; int lookup; + debug("%s: %s\n", __func__, prop_name); phandle = fdt_getprop(blob, node, prop_name, NULL); if (!phandle) return -FDT_ERR_NOTFOUND; @@ -427,7 +439,7 @@ static int fdtdec_decode_gpios(const void *blob, int node, assert(max_count > 0); prop = fdt_get_property(blob, node, prop_name, &len); if (!prop) { - debug("FDT: %s: property '%s' missing\n", __func__, prop_name); + debug("%s: property '%s' missing\n", __func__, prop_name); return -FDT_ERR_NOTFOUND; } @@ -436,7 +448,7 @@ static int fdtdec_decode_gpios(const void *blob, int node, cell = (u32 *)prop->data; len /= sizeof(u32) * 3; /* 3 cells per GPIO record */ if (len > max_count) { - debug("FDT: %s: too many GPIOs / cells for " + debug(" %s: too many GPIOs / cells for " "property '%s'\n", __func__, prop_name); return -FDT_ERR_BADLAYOUT; } diff --git a/lib/hashtable.c b/lib/hashtable.c index abd61c89186..670a704a418 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -142,7 +142,7 @@ int hcreate_r(size_t nel, struct hsearch_data *htab) * be freed and the local static variable can be marked as not used. */ -void hdestroy_r(struct hsearch_data *htab) +void hdestroy_r(struct hsearch_data *htab, int do_apply) { int i; @@ -156,7 +156,10 @@ void hdestroy_r(struct hsearch_data *htab) for (i = 1; i <= htab->size; ++i) { if (htab->table[i].used > 0) { ENTRY *ep = &htab->table[i].entry; - + if (do_apply && htab->apply != NULL) { + /* deletion is always forced */ + htab->apply(ep->key, ep->data, NULL, H_FORCE); + } free((void *)ep->key); free(ep->data); } @@ -401,7 +404,7 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, * do that. */ -int hdelete_r(const char *key, struct hsearch_data *htab) +int hdelete_r(const char *key, struct hsearch_data *htab, int do_apply) { ENTRY e, *ep; int idx; @@ -417,7 +420,8 @@ int hdelete_r(const char *key, struct hsearch_data *htab) /* free used ENTRY */ debug("hdelete: DELETING key \"%s\"\n", key); - + if (do_apply && htab->apply != NULL) + htab->apply(ep->key, ep->data, NULL, H_FORCE); free((void *)ep->key); free(ep->data); htab->table[idx].used = -1; @@ -604,6 +608,34 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, */ /* + * Check whether variable 'name' is amongst vars[], + * and remove all instances by setting the pointer to NULL + */ +static int drop_var_from_set(const char *name, int nvars, char * vars[]) +{ + int i = 0; + int res = 0; + + /* No variables specified means process all of them */ + if (nvars == 0) + return 1; + + for (i = 0; i < nvars; i++) { + if (vars[i] == NULL) + continue; + /* If we found it, delete all of them */ + if (!strcmp(name, vars[i])) { + vars[i] = NULL; + res = 1; + } + } + if (!res) + debug("Skipping non-listed variable %s\n", name); + + return res; +} + +/* * Import linearized data into hash table. * * This is the inverse function to hexport(): it takes a linear list @@ -639,9 +671,12 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, */ int himport_r(struct hsearch_data *htab, - const char *env, size_t size, const char sep, int flag) + const char *env, size_t size, const char sep, int flag, + int nvars, char * const vars[], int do_apply) { char *data, *sp, *dp, *name, *value; + char *localvars[nvars]; + int i; /* Test for correct arguments. */ if (htab == NULL) { @@ -658,12 +693,16 @@ int himport_r(struct hsearch_data *htab, memcpy(data, env, size); dp = data; + /* make a local copy of the list of variables */ + if (nvars) + memcpy(localvars, vars, sizeof(vars[0]) * nvars); + if ((flag & H_NOCLEAR) == 0) { /* Destroy old hash table if one exists */ debug("Destroy Hash Table: %p table = %p\n", htab, htab->table); if (htab->table) - hdestroy_r(htab); + hdestroy_r(htab, do_apply); } /* @@ -726,8 +765,10 @@ int himport_r(struct hsearch_data *htab, *dp++ = '\0'; /* terminate name */ debug("DELETE CANDIDATE: \"%s\"\n", name); + if (!drop_var_from_set(name, nvars, localvars)) + continue; - if (hdelete_r(name, htab) == 0) + if (hdelete_r(name, htab, do_apply) == 0) debug("DELETE ERROR ##############################\n"); continue; @@ -743,10 +784,32 @@ int himport_r(struct hsearch_data *htab, *sp++ = '\0'; /* terminate value */ ++dp; + /* Skip variables which are not supposed to be processed */ + if (!drop_var_from_set(name, nvars, localvars)) + continue; + /* enter into hash table */ e.key = name; e.data = value; + /* if there is an apply function, check what it has to say */ + if (do_apply && htab->apply != NULL) { + debug("searching before calling cb function" + " for %s\n", name); + /* + * Search for variable in existing env, so to pass + * its previous value to the apply callback + */ + hsearch_r(e, FIND, &rv, htab); + debug("previous value was %s\n", rv ? rv->data : ""); + if (htab->apply(name, rv ? rv->data : NULL, + value, flag)) { + debug("callback function refused to set" + " variable %s, skipping it!\n", name); + continue; + } + } + hsearch_r(e, ENTER, &rv, htab); if (rv == NULL) { printf("himport_r: can't insert \"%s=%s\" into hash table\n", @@ -762,6 +825,24 @@ int himport_r(struct hsearch_data *htab, debug("INSERT: free(data = %p)\n", data); free(data); + /* process variables which were not considered */ + for (i = 0; i < nvars; i++) { + if (localvars[i] == NULL) + continue; + /* + * All variables which were not deleted from the variable list + * were not present in the imported env + * This could mean two things: + * a) if the variable was present in current env, we delete it + * b) if the variable was not present in current env, we notify + * it might be a typo + */ + if (hdelete_r(localvars[i], htab, do_apply) == 0) + printf("WARNING: '%s' neither in running nor in imported env!\n", localvars[i]); + else + printf("WARNING: '%s' not in imported env, deleting it!\n", localvars[i]); + } + debug("INSERT: done\n"); return 1; /* everything OK */ } diff --git a/onenand_ipl/onenand_boot.c b/nand_spl/board/freescale/common.c index 22baebb314c..0e099bc7c67 100644 --- a/onenand_ipl/onenand_boot.c +++ b/nand_spl/board/freescale/common.c @@ -1,11 +1,6 @@ /* - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from x-loader - * - * See file CREDITS for list of people who contributed to this - * project. + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Matthew McClintock <msm@freescale.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,35 +9,32 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ #include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> -#include "onenand_ipl.h" +DECLARE_GLOBAL_DATA_PTR; -typedef int (init_fnc_t)(void); +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif -void start_oneboot(void) +void udelay(unsigned long usec) { - uchar *buf; - - buf = (uchar *) CONFIG_SYS_LOAD_ADDR; + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); - onenand_read_block(buf); - - ((init_fnc_t *)CONFIG_SYS_LOAD_ADDR)(); - - /* should never come here */ -} - -void hang(void) -{ - for (;;); + while ((mfspr(SPRN_TBRL) - s) < ticks); } diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 8d240eadd97..cdbd49292cb 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 16eeb61d85b..9c356901b13 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -27,51 +27,61 @@ #include <asm/immap_85xx.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_law.h> +#include <asm/global_data.h> -#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); } +DECLARE_GLOBAL_DATA_PTR; unsigned long ddr_freq_mhz; void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + /* mask off E bit */ + u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); if (ddr_freq_mhz < 700) { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_667); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); } else { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_800); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); } - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + + /* P1014 and it's derivatives support max 16bit DDR width */ + if (svr == SVR_P1014) { + __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg); + __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg); + /* For CS0_BNDS we divide the start and end address by 2, so we can just + * shift the entire register to achieve the desired result and the mask + * the value so we don't write reserved fields */ + __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds); + } - /* mimic 500us delay, with busy isync() loop */ - udelay(100); + udelay(500); /* Let the controller go */ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); @@ -82,20 +92,19 @@ void sdram_init(void) void board_init_f(ulong bootflag) { u32 plat_ratio, ddr_ratio; - unsigned long bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 168e8686413..da435213fcf 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 0065c876ded..89e339d5120 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -25,6 +25,10 @@ #include <asm/io.h> #include <nand.h> #include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; /* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) @@ -33,40 +37,47 @@ void sdram_init(void) set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl); + __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1); + __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2); + /* Set, but do not enable the memory */ + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); } void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); /* Initialize the DDR3 */ diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 475cc496b3d..46cf7099b6e 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ - nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \ + ../common.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +$(obj)../common.c: + @rm -f $(obj)../common.c + ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c endif ######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c index b9796ea6c94..4c140c1572f 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c @@ -25,11 +25,9 @@ #include <nand.h> #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> -#define udelay(x) {int i, j; \ - for (i = 0; i < x; i++) \ - for (j = 0; j < 10000; j++) \ - ; } +DECLARE_GLOBAL_DATA_PTR; /* * Fixed sdram init -- doesn't use serial presence detect. @@ -38,32 +36,32 @@ void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); #endif - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); /* Set, but do not enable the memory */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN); + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); asm volatile("sync;isync"); udelay(500); @@ -76,7 +74,7 @@ void sdram_init(void) void board_init_f(ulong bootflag) { - u32 plat_ratio, bus_clk; + u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; #ifndef CONFIG_QE ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); @@ -85,22 +83,22 @@ void board_init_f(ulong bootflag) /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); + gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); #ifndef CONFIG_QE /* init DDR3 reset signal */ - out_be32(&pgpio->gpdir, 0x02000000); - out_be32(&pgpio->gpodr, 0x00200000); - out_be32(&pgpio->gpdat, 0x00000000); + __raw_writel(0x02000000, &pgpio->gpdir); + __raw_writel(0x00200000, &pgpio->gpodr); + __raw_writel(0x00000000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdat, 0x00200000); + __raw_writel(0x00200000, &pgpio->gpdat); udelay(1000); - out_be32(&pgpio->gpdir, 0x00000000); + __raw_writel(0x00000000, &pgpio->gpdir); #endif /* Initialize the DDR3 */ diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index 502605b1d5c..e9d649743ee 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -66,39 +66,42 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) if (large) { fmr |= FMR_ECCM; - out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | - (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); - out_be32(®s->fir, - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_CW1 << FIR_OP3_SHIFT) | - (FIR_OP_RBW << FIR_OP4_SHIFT)); + __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT), + ®s->fcr); + __raw_writel( + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT), + ®s->fir); } else { - out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); - out_be32(®s->fir, - (FIR_OP_CW0 << FIR_OP0_SHIFT) | - (FIR_OP_CA << FIR_OP1_SHIFT) | - (FIR_OP_PA << FIR_OP2_SHIFT) | - (FIR_OP_RBW << FIR_OP3_SHIFT)); + __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, ®s->fcr); + __raw_writel( + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT), + ®s->fir); } - out_be32(®s->fbcr, 0); - clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN); + __raw_writel(0, ®s->fbcr); while (pos < uboot_size) { int i = 0; - out_be32(®s->fbar, offs >> block_shift); + __raw_writel(offs >> block_shift, ®s->fbar); do { int j; unsigned int page_offs = (offs & (block_size - 1)) << 1; - out_be32(®s->ltesr, ~0); - out_be32(®s->lteatr, 0); - out_be32(®s->fpar, page_offs); - out_be32(®s->fmr, fmr); - out_be32(®s->lsor, 0); + __raw_writel(~0, ®s->ltesr); + __raw_writel(0, ®s->lteatr); + __raw_writel(page_offs, ®s->fpar); + __raw_writel(fmr, ®s->fmr); + sync(); + __raw_writel(0, ®s->lsor); nand_wait(); page_offs %= WINDOW_SIZE; diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index d6b0d9b6d10..a40c99877c0 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -36,50 +36,58 @@ static void nfc_wait_ready(void) { uint32_t tmp; - while (!(readw(&nfc->nand_flash_config2) & NFC_INT)) + while (!(readw(&nfc->config2) & NFC_INT)) ; /* Reset interrupt flag */ - tmp = readw(&nfc->nand_flash_config2); + tmp = readw(&nfc->config2); tmp &= ~NFC_INT; - writew(tmp, &nfc->nand_flash_config2); + writew(tmp, &nfc->config2); } -void nfc_nand_init(void) +static void nfc_nand_init(void) { -#if defined(MXC_NFC_V1_1) - int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; +#if defined(MXC_NFC_V2_1) + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1; writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); /* unlocking RAM Buff */ - writew(0x2, &nfc->configuration); + writew(0x2, &nfc->config); /* hardware ECC checking and correct */ - config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800; + config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | + NFC_ONE_CYCLE | NFC_FP_INT; /* * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ - if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16) + if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) config1 &= ~NFC_4_8N_ECC; else config1 |= NFC_4_8N_ECC; - writew(config1, &nfc->nand_flash_config1); + writew(config1, &nfc->config1); #elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ - writew(0x2, &nfc->configuration); + writew(0x2, &nfc->config); /* hardware ECC checking and correct */ - writew(NFC_ECC_EN, &nfc->nand_flash_config1); + writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1); #endif } static void nfc_nand_command(unsigned short command) { writew(command, &nfc->flash_cmd); - writew(NFC_CMD, &nfc->nand_flash_config2); + writew(NFC_CMD, &nfc->config2); + nfc_wait_ready(); +} + +static void nfc_nand_address(unsigned short address) +{ + writew(address, &nfc->flash_addr); + writew(NFC_ADDR, &nfc->config2); nfc_wait_ready(); } @@ -87,58 +95,43 @@ static void nfc_nand_page_address(unsigned int page_address) { unsigned int page_count; - writew(0x00, &nfc->flash_add); - writew(NFC_ADDR, &nfc->nand_flash_config2); - nfc_wait_ready(); + nfc_nand_address(0x00); /* code only for large page flash */ - if (CONFIG_SYS_NAND_PAGE_SIZE > 512) { - writew(0x00, &nfc->flash_add); - writew(NFC_ADDR, &nfc->nand_flash_config2); - nfc_wait_ready(); - } + if (CONFIG_SYS_NAND_PAGE_SIZE > 512) + nfc_nand_address(0x00); page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; if (page_address <= page_count) { page_count--; /* transform 0x01000000 to 0x00ffffff */ do { - writew(page_address & 0xff, &nfc->flash_add); - writew(NFC_ADDR, &nfc->nand_flash_config2); - nfc_wait_ready(); + nfc_nand_address(page_address & 0xff); page_address = page_address >> 8; page_count = page_count >> 8; } while (page_count); } - writew(0x00, &nfc->flash_add); - writew(NFC_ADDR, &nfc->nand_flash_config2); - nfc_wait_ready(); + nfc_nand_address(0x00); } static void nfc_nand_data_output(void) { - int config1 = readw(&nfc->nand_flash_config1); #ifdef NAND_MXC_2K_MULTI_CYCLE int i; #endif - config1 |= NFC_ECC_EN | NFC_INT_MSK; - writew(config1, &nfc->nand_flash_config1); - writew(0, &nfc->buffer_address); - writew(NFC_OUTPUT, &nfc->nand_flash_config2); + writew(0, &nfc->buf_addr); + writew(NFC_OUTPUT, &nfc->config2); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE /* * This NAND controller requires multiple input commands * for pages larger than 512 bytes. */ - for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { - config1 = readw(&nfc->nand_flash_config1); - config1 |= NFC_ECC_EN | NFC_INT_MSK; - writew(config1, &nfc->nand_flash_config1); - writew(i, &nfc->buffer_address); - writew(NFC_OUTPUT, &nfc->nand_flash_config2); + for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) { + writew(i, &nfc->buf_addr); + writew(NFC_OUTPUT, &nfc->config2); nfc_wait_ready(); } #endif @@ -146,16 +139,28 @@ static void nfc_nand_data_output(void) static int nfc_nand_check_ecc(void) { - return readw(&nfc->ecc_status_result); +#if defined(MXC_NFC_V1) + u16 ecc_status = readw(&nfc->ecc_status_result); + return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2; +#elif defined(MXC_NFC_V2_1) + u32 ecc_status = readl(&nfc->ecc_status_result); + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; + int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4; + int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512; + + do { + if ((ecc_status & 0xf) > err_limit) + return 1; + ecc_status >>= 4; + } while (--subpages); + + return 0; +#endif } -static int nfc_read_page(unsigned int page_address, unsigned char *buf) +static void nfc_nand_read_page(unsigned int page_address) { - int i; - u32 *src; - u32 *dst; - - writew(0, &nfc->buffer_address); /* read in first 0 buffer */ + writew(0, &nfc->buf_addr); /* read in first 0 buffer */ nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); @@ -163,15 +168,24 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf) nfc_nand_command(NAND_CMD_READSTART); nfc_nand_data_output(); /* fill the main buffer 0 */ +} + +static int nfc_read_page(unsigned int page_address, unsigned char *buf) +{ + int i; + u32 *src; + u32 *dst; + + nfc_nand_read_page(page_address); if (nfc_nand_check_ecc()) return -1; - src = &nfc->main_area[0][0]; + src = (u32 *)&nfc->main_area[0][0]; dst = (u32 *)buf; /* main copy loop from NAND-buffer to SDRAM memory */ - for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) { + for (i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE / 4; i++) { writel(readl(src), dst); src++; dst++; @@ -188,16 +202,9 @@ static int is_badblock(int pagenumber) /* Check the first two pages for bad block markers */ for (page = pagenumber; page < pagenumber + 2; page++) { - writew(0, &nfc->buffer_address); /* read in first 0 buffer */ - nfc_nand_command(NAND_CMD_READ0); - nfc_nand_page_address(page); - - if (CONFIG_SYS_NAND_PAGE_SIZE > 512) - nfc_nand_command(NAND_CMD_READSTART); - - nfc_nand_data_output(); /* fill the main buffer 0 */ + nfc_nand_read_page(page); - src = &nfc->spare_area[0][0]; + src = (u32 *)&nfc->spare_area[0][0]; /* * IMPORTANT NOTE: The nand flash controller uses a non- @@ -230,7 +237,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) page = from / CONFIG_SYS_NAND_PAGE_SIZE; i = 0; - while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) { + while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) { if (nfc_read_page(page, buf) < 0) return -1; diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile deleted file mode 100644 index 3bc992049af..00000000000 --- a/onenand_ipl/board/apollon/Makefile +++ /dev/null @@ -1,87 +0,0 @@ - -include $(TOPDIR)/config.mk -include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk - -LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds -LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL -OBJCFLAGS += --gap-fill=0x00 - -SOBJS := low_levelinit.o -SOBJS += start.o -COBJS := apollon.o -COBJS += onenand_read.o -COBJS += onenand_boot.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) - -onenandobj := $(OBJTREE)/onenand_ipl/ - -ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin - -all: $(obj).depend $(ALL) - -$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@ - -$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@ - -$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - -Map $@.map -o $@ - -$(onenandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links from common files - -# from cpu directory -$(obj)start.S: - @rm -f $@ - ln -s $(SRCTREE)/$(CPUDIR)/start.S $@ - -# from onenand_ipl directory -$(obj)onenand_ipl.h: - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@ - -$(obj)onenand_boot.c: $(obj)onenand_ipl.h - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@ - -$(obj)onenand_read.c: $(obj)onenand_ipl.h - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)apollon.c: - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/apollon.c $@ - -$(obj)low_levelinit.S: - @rm -f $@ - ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)$.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/onenand_ipl/board/apollon/apollon.c b/onenand_ipl/board/apollon/apollon.c deleted file mode 100644 index 4936e00f17a..00000000000 --- a/onenand_ipl/board/apollon/apollon.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/arch/mux.h> - -#define write_config_reg(reg, value) \ -do { \ - writeb(value, reg); \ -} while (0) - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -#ifdef CONFIG_SYS_PRINTF -/* Pin Muxing registers used for UART1 */ -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -static void muxSetupUART1(void) -{ - /* UART1_CTS pin configuration, PIN = D21 */ - write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); - /* UART1_RTS pin configuration, PIN = H21 */ - write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); - /* UART1_TX pin configuration, PIN = L20 */ - write_config_reg(CONTROL_PADCONF_UART1_TX, 0); - /* UART1_RX pin configuration, PIN = T21 */ - write_config_reg(CONTROL_PADCONF_UART1_RX, 0); -} -#endif - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ -int s_init(int skip) -{ -#ifdef CONFIG_SYS_PRINTF - muxSetupUART1(); -#endif - return 0; -} diff --git a/onenand_ipl/board/apollon/config.mk b/onenand_ipl/board/apollon/config.mk deleted file mode 100644 index 62956e866ef..00000000000 --- a/onenand_ipl/board/apollon/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2005-2008 Samsung Electronics -# Kyungmin Park <kyungmin.park@samsung.com> -# -# Samsung Apollon board with OMAP2420 (ARM1136) cpu -# -# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) -# 8800'0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x00000000 diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S deleted file mode 100644 index cab422717db..00000000000 --- a/onenand_ipl/board/apollon/low_levelinit.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from board/omap2420h4/platform.S - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/omap2420.h> -#include <asm/arch/mem.h> -#include <asm/arch/clocks.h> - -#define APOLLON_CS0_BASE 0x00000000 - -#ifdef PRCM_CONFIG_I -#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 -#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 -#define SDRC_RFR_CTRL_0_VAL 0x00044C01 - -/* GPMC */ -#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 -#define APOLLON_GPMC_CONFIG2_0 0x000c1000 -#define APOLLON_GPMC_CONFIG3_0 0x00030400 -#define APOLLON_GPMC_CONFIG4_0 0x0B841006 -#define APOLLON_GPMC_CONFIG5_0 0x020F0C11 -#define APOLLON_GPMC_CONFIG6_0 0x00000000 -#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) - -#elif defined(PRCM_CONFIG_II) -#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 -#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C -#define SDRC_RFR_CTRL_0_VAL 0x00030001 - -/* GPMC */ -#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 -#define APOLLON_GPMC_CONFIG2_0 0x00080E81 -#define APOLLON_GPMC_CONFIG3_0 0x00030400 -#define APOLLON_GPMC_CONFIG4_0 0x08041586 -#define APOLLON_GPMC_CONFIG5_0 0x020C090E -#define APOLLON_GPMC_CONFIG6_0 0x00000000 -#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) - -#else -#error "Please configure PRCM schecm" -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - mov r3, r0 /* save skip information */ - - /* Disable watchdog */ - ldr r0, =WD2_BASE - ldr r1, =WD_UNLOCK1 - str r1, [r0, #WSPR] - - ldr r1, =WD_UNLOCK2 - str r1, [r0, #WSPR] - -#ifdef DEBUG_LED - /* LED0 OFF */ - ldr r0, =0x480000E5 /* ball AA10, mode 3 */ - mov r1, #0x0b - strb r1, [r0] -#endif - - /* Pin muxing for SDRC */ - mov r1, #0x00 - ldr r0, =0x480000A1 /* ball C12, mode 0 */ - strb r1, [r0] - - ldr r0, =0x48000032 /* ball D11, mode 0 */ - strb r1, [r0] - - ldr r0, =0x480000A3 /* ball B13, mode 0 */ - strb r1, [r0] - - /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE - ldr r1, =0x00000010 - str r1, [r0, #0x10] - - ldr r1, =0x00000100 - str r1, [r0, #0x44] - - /* SDRC CS0 configuration */ -#ifdef CONFIG_APOLLON_PLUS - ldr r1, =0x01702011 -#else - ldr r1, =0x00d04011 -#endif - str r1, [r0, #0x80] - - ldr r1, =SDRC_ACTIM_CTRLA_0_VAL - str r1, [r0, #0x9C] - - ldr r1, =SDRC_ACTIM_CTRLB_0_VAL - str r1, [r0, #0xA0] - - ldr r1, =SDRC_RFR_CTRL_0_VAL - str r1, [r0, #0xA4] - - ldr r1, =0x00000041 - str r1, [r0, #0x70] - - /* Manual command sequence */ - ldr r1, =0x00000007 - str r1, [r0, #0xA8] - - ldr r1, =0x00000000 - str r1, [r0, #0xA8] - - ldr r1, =0x00000001 - str r1, [r0, #0xA8] - - ldr r1, =0x00000002 - str r1, [r0, #0xA8] - str r1, [r0, #0xA8] - - /* - * CS0 SDRC Mode register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - ldr r1, =0x00000032 - str r1, [r0, #0x84] - - /* Note: You MUST set EMR values */ - /* EMR1 & EMR2 */ - ldr r1, =0x00000000 - str r1, [r0, #0x88] - str r1, [r0, #0x8C] - -#ifdef OLD_SDRC_DLLA_CTRL - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00007306 - str r1, [r0, #0x60] - - ldr r1, =0x00007303 - str r1, [r0, #0x60] -#else - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x60] - - ldr r1, =0x00000503 - str r1, [r0, #0x60] -#endif - -#ifdef __BROKEN_FEATURE__ - /* SDRC_DLLB_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x68] - - ldr r1, =0x00000503 - str r1, [r0, #0x68] -#endif - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b - - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ - - bl s_init /* go setup pll,mux,memory */ - - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK diff --git a/onenand_ipl/board/apollon/u-boot.onenand.lds b/onenand_ipl/board/apollon/u-boot.onenand.lds deleted file mode 100644 index 721d2f5949b..00000000000 --- a/onenand_ipl/board/apollon/u-boot.onenand.lds +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * Derived from X-loader - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) . = ALIGN(4); } - __bss_end__ = .; -} diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h deleted file mode 100644 index 7ebb3e32ddb..00000000000 --- a/onenand_ipl/onenand_ipl.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ONENAND_IPL_H -#define _ONENAND_IPL_H - -#include <linux/mtd/onenand_regs.h> - -#define onenand_readw(a) readw(THIS_ONENAND(a)) -#define onenand_writew(v, a) writew(v, THIS_ONENAND(a)) - -#define THIS_ONENAND(a) (CONFIG_SYS_ONENAND_BASE + (a)) - -#define READ_INTERRUPT() onenand_readw(ONENAND_REG_INTERRUPT) - -extern int (*onenand_read_page)(ulong block, ulong page, - u_char *buf, int pagesize); -extern int onenand_read_block(unsigned char *buf); -#endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c deleted file mode 100644 index 8d0df81af63..00000000000 --- a/onenand_ipl/onenand_read.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * (C) Copyright 2005-2009 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#include <asm/io.h> -#include <asm/string.h> - -#include "onenand_ipl.h" - -#define onenand_block_address(block) (block) -#define onenand_sector_address(page) (page << 2) -#define onenand_buffer_address() ((1 << 3) << 8) -#define onenand_bufferram_address(block) (0) - -#ifdef __HAVE_ARCH_MEMCPY32 -extern void *memcpy32(void *dest, void *src, int size); -#endif - -int (*onenand_read_page)(ulong block, ulong page, u_char *buf, int pagesize); - -/* read a page with ECC */ -static int generic_onenand_read_page(ulong block, ulong page, - u_char * buf, int pagesize) -{ - unsigned long *base; - -#ifndef __HAVE_ARCH_MEMCPY32 - unsigned int offset, value; - unsigned long *p; -#endif - - onenand_writew(onenand_block_address(block), - ONENAND_REG_START_ADDRESS1); - - onenand_writew(onenand_bufferram_address(block), - ONENAND_REG_START_ADDRESS2); - - onenand_writew(onenand_sector_address(page), - ONENAND_REG_START_ADDRESS8); - - onenand_writew(onenand_buffer_address(), - ONENAND_REG_START_BUFFER); - - onenand_writew(ONENAND_INT_CLEAR, ONENAND_REG_INTERRUPT); - - onenand_writew(ONENAND_CMD_READ, ONENAND_REG_COMMAND); - -#ifndef __HAVE_ARCH_MEMCPY32 - p = (unsigned long *) buf; -#endif - base = (unsigned long *) (CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM); - - while (!(READ_INTERRUPT() & ONENAND_INT_READ)) - continue; - - /* Check for invalid block mark */ - if (page < 2 && (onenand_readw(ONENAND_SPARERAM) != 0xffff)) - return 1; - -#ifdef __HAVE_ARCH_MEMCPY32 - /* 32 bytes boundary memory copy */ - memcpy32(buf, base, pagesize); -#else - for (offset = 0; offset < (pagesize >> 2); offset++) { - value = *(base + offset); - *p++ = value; - } -#endif - - return 0; -} - -#ifndef CONFIG_ONENAND_START_PAGE -#define CONFIG_ONENAND_START_PAGE 1 -#endif -#define ONENAND_PAGES_PER_BLOCK 64 - -static void onenand_generic_init(int *page_is_4KiB, int *page) -{ - int dev_id, density; - - if (onenand_readw(ONENAND_REG_TECHNOLOGY)) - *page_is_4KiB = 1; - dev_id = onenand_readw(ONENAND_REG_DEVICE_ID); - density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; - density &= ONENAND_DEVICE_DENSITY_MASK; - if (density >= ONENAND_DEVICE_DENSITY_4Gb && - !(dev_id & ONENAND_DEVICE_IS_DDP)) - *page_is_4KiB = 1; -} - -/** - * onenand_read_block - Read CONFIG_SYS_MONITOR_LEN from begining - * of OneNAND, skipping bad blocks - * @return 0 on success - */ -int onenand_read_block(unsigned char *buf) -{ - int block, nblocks; - int page = CONFIG_ONENAND_START_PAGE, offset = 0; - int pagesize, erasesize, erase_shift; - int page_is_4KiB = 0; - - onenand_read_page = generic_onenand_read_page; - - onenand_generic_init(&page_is_4KiB, &page); - - if (page_is_4KiB) { - pagesize = 4096; /* OneNAND has 4KiB pagesize */ - erase_shift = 18; - } else { - pagesize = 2048; /* OneNAND has 2KiB pagesize */ - erase_shift = 17; - } - - erasesize = (1 << erase_shift); - nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize - 1) >> erase_shift; - - /* NOTE: you must read page from page 1 of block 0 */ - /* read the block page by page */ - for (block = 0; block < nblocks; block++) { - for (; page < ONENAND_PAGES_PER_BLOCK; page++) { - if (onenand_read_page(block, page, buf + offset, - pagesize)) { - /* This block is bad. Skip it - * and read next block */ - offset -= page * pagesize; - nblocks++; - break; - } - offset += pagesize; - } - page = 0; - } - - return 0; -} diff --git a/spl/Makefile b/spl/Makefile index 476a5e65d15..d4cb6685d47 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -135,9 +135,7 @@ $(obj)u-boot-spl.bin: $(obj)u-boot-spl $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ GEN_UBOOT = \ - UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) | \ - sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ - cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__START) \ + cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot-spl.map -o u-boot-spl diff --git a/tools/Makefile b/tools/Makefile index a7d1e18fe2a..c31437e6a20 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -92,6 +92,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o NOPED_OBJ_FILES-y += aisimage.o NOPED_OBJ_FILES-y += kwbimage.o +NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o @@ -208,6 +209,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \ $(obj)image.o \ $(obj)imximage.o \ $(obj)kwbimage.o \ + $(obj)pblimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index e292d2ba1db..1a2c22756ee 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -203,6 +203,17 @@ static char default_environment[] = { #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" MK_STR (CONFIG_PCI_BOOTDELAY) "\0" #endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" + "cpu=" CONFIG_SYS_CPU "\0" + "board=" CONFIG_SYS_BOARD "\0" +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#endif #ifdef CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS #endif diff --git a/tools/mkimage.c b/tools/mkimage.c index eeb1b106682..e43b09f7661 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -39,6 +39,7 @@ struct mkimage_params params = { .comp = IH_COMP_GZIP, .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, .imagename = "", + .imagename2 = "", }; /* @@ -150,6 +151,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Freescale PBL Boot image generation/list support */ + init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ init_kwb_image_type (); /* Init Freescale imx Boot image generation/list support */ @@ -250,6 +253,15 @@ main (int argc, char **argv) usage (); params.imagename = *++argv; goto NXTARG; + case 'R': + if (--argc <= 0) + usage(); + /* + * This entry is for the second configuration + * file, if only one is not enough. + */ + params.imagename2 = *++argv; + goto NXTARG; case 's': params.skipcpy = 1; break; @@ -440,6 +452,9 @@ NXTARG: ; break; } } + } else if (params.type == IH_TYPE_PBLIMAGE) { + /* PBL has special Image format, implements its' own */ + pbl_load_uboot(ifd, ¶ms); } else { copy_file (ifd, params.datafile, 0); } diff --git a/tools/mkimage.h b/tools/mkimage.h index 5fe1a48ccfe..ea45f5c8349 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -69,6 +69,7 @@ struct mkimage_params { unsigned int addr; unsigned int ep; char *imagename; + char *imagename2; char *datafile; char *imagefile; char *cmdname; @@ -147,6 +148,8 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void pbl_load_uboot(int fd, struct mkimage_params *mparams); +void init_pbl_image_type(void); void init_ais_image_type(void); void init_kwb_image_type (void); void init_imx_image_type (void); diff --git a/tools/pblimage.c b/tools/pblimage.c new file mode 100644 index 00000000000..508a747a3f6 --- /dev/null +++ b/tools/pblimage.c @@ -0,0 +1,331 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "pblimage.h" + +/* + * The PBL can load up to 64 bytes at a time, so we split the U-Boot + * image into 64 byte chunks. PBL needs a command for each piece, of + * the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE + * is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit, + * so it starts from 0x81F80000. + */ +static uint32_t next_pbl_cmd = 0x81F80000; +/* + * need to store all bytes in memory for calculating crc32, then write the + * bytes to image file for PBL boot. + */ +static unsigned char mem_buf[600000]; +static unsigned char *pmem_buf = mem_buf; +static int pbl_size; +static char *fname = "Unknown"; +static int lineno = -1; +static struct pbl_header pblimage_header; + +static union +{ + char c[4]; + unsigned char l; +} endian_test = { {'l', '?', '?', 'b'} }; + +#define ENDIANNESS ((char)endian_test.l) + +static void generate_pbl_cmd(void) +{ + uint32_t val = next_pbl_cmd; + next_pbl_cmd += 0x40; + int i; + + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (val >> (i * 8)) & 0xff; + pbl_size++; + } +} + +static void pbl_fget(size_t size, FILE *stream) +{ + unsigned char c; + int c_temp; + + while (size && (c_temp = fgetc(stream)) != EOF) { + c = (unsigned char)c_temp; + *pmem_buf++ = c; + pbl_size++; + size--; + } +} + +/* load split u-boot with PBI command 81xxxxxx. */ +static void load_uboot(FILE *fp_uboot) +{ + while (next_pbl_cmd < 0x82000000) { + generate_pbl_cmd(); + pbl_fget(64, fp_uboot); + } +} + +static void check_get_hexval(char *token) +{ + uint32_t hexval; + int i; + + if (!sscanf(token, "%x", &hexval)) { + printf("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit(EXIT_FAILURE); + } + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (hexval >> (i * 8)) & 0xff; + pbl_size++; + } +} + +static void pbl_parser(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + size_t len = 0; + + fname = name; + fd = fopen(name, "r"); + if (fd == NULL) { + printf("Error:%s - Can't open\n", fname); + exit(EXIT_FAILURE); + } + + while ((getline(&line, &len, fd)) > 0) { + lineno++; + token = strtok_r(line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + for (line = token;; line = NULL) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + check_get_hexval(token); + } + } + if (line) + free(line); + fclose(fd); +} + +static uint32_t crc_table[256]; + +static void make_crc_table(void) +{ + uint32_t mask; + int i, j; + uint32_t poly; /* polynomial exclusive-or pattern */ + + /* + * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + * + x11 + x12 + x16 + x22 + x23 + x26 + x32. + */ + poly = 0x04c11db7; + + for (i = 0; i < 256; i++) { + mask = i << 24; + for (j = 0; j < 8; j++) { + if (mask & 0x80000000) + mask = (mask << 1) ^ poly; + else + mask <<= 1; + } + crc_table[i] = mask; + } +} + +unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len) +{ + uint32_t crc32_val = 0xffffffff; + uint32_t xor = 0x0; + int i; + + make_crc_table(); + + for (i = 0; i < len; i++) + crc32_val = (crc32_val << 8) ^ + crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; + + crc32_val = crc32_val ^ xor; + if (crc32_val < 0) { + crc32_val += 0xffffffff; + crc32_val += 1; + } + return crc32_val; +} + +static uint32_t reverse_byte(uint32_t val) +{ + uint32_t temp; + unsigned char *p1; + int j; + + temp = val; + p1 = (unsigned char *)&temp; + for (j = 3; j >= 0; j--) + *p1++ = (val >> (j * 8)) & 0xff; + return temp; +} + +/* write end command and crc command to memory. */ +static void add_end_cmd(void) +{ + uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, + 0x091380c0, 0x00000000}; + uint32_t crc32_pbl; + int i; + unsigned char *p = (unsigned char *)&pbl_end_cmd; + + if (ENDIANNESS == 'l') { + for (i = 0; i < 4; i++) + pbl_end_cmd[i] = reverse_byte(pbl_end_cmd[i]); + } + + for (i = 0; i < 16; i++) { + *pmem_buf++ = *p++; + pbl_size++; + } + + /* Add PBI CRC command. */ + *pmem_buf++ = 0x08; + *pmem_buf++ = 0x13; + *pmem_buf++ = 0x80; + *pmem_buf++ = 0x40; + pbl_size += 4; + + /* calculated CRC32 and write it to memory. */ + crc32_pbl = pbl_crc32(0, (const char *)mem_buf, pbl_size); + *pmem_buf++ = (crc32_pbl >> 24) & 0xff; + *pmem_buf++ = (crc32_pbl >> 16) & 0xff; + *pmem_buf++ = (crc32_pbl >> 8) & 0xff; + *pmem_buf++ = (crc32_pbl) & 0xff; + pbl_size += 4; + + if ((pbl_size % 16) != 0) { + for (i = 0; i < 8; i++) { + *pmem_buf++ = 0x0; + pbl_size++; + } + } + if ((pbl_size % 16 != 0)) { + printf("Error: Bad size of image file\n"); + exit(EXIT_FAILURE); + } +} + +void pbl_load_uboot(int ifd, struct mkimage_params *params) +{ + FILE *fp_uboot; + int size; + + /* parse the rcw.cfg file. */ + pbl_parser(params->imagename); + + /* parse the pbi.cfg file. */ + pbl_parser(params->imagename2); + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + + load_uboot(fp_uboot); + add_end_cmd(); + fclose(fp_uboot); + lseek(ifd, 0, SEEK_SET); + + size = pbl_size; + if (write(ifd, (const void *)&mem_buf, size) != size) { + fprintf(stderr, "Write error on %s: %s\n", + params->imagefile, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +static int pblimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_PBLIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int pblimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct pbl_header *pbl_hdr = (struct pbl_header *) ptr; + + /* Only a few checks can be done: search for magic numbers */ + if (ENDIANNESS == 'l') { + if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE)) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER)) + return -FDT_ERR_BADSTRUCTURE; + } else { + if (pbl_hdr->preamble != RCW_PREAMBLE) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != RCW_HEADER) + return -FDT_ERR_BADSTRUCTURE; + } + return 0; +} + +static void pblimage_print_header(const void *ptr) +{ + printf("Image Type: Freescale PBL Boot Image\n"); +} + +static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + /*nothing need to do, pbl_load_uboot takes care of whole file. */ +} + +/* pblimage parameters */ +static struct image_type_params pblimage_params = { + .name = "Freescale PBL Boot Image support", + .header_size = sizeof(struct pbl_header), + .hdr = (void *)&pblimage_header, + .check_image_type = pblimage_check_image_types, + .verify_header = pblimage_verify_header, + .print_header = pblimage_print_header, + .set_header = pblimage_set_header, +}; + +void init_pbl_image_type(void) +{ + pbl_size = 0; + mkimage_register(&pblimage_params); +} diff --git a/board/freescale/p3060qds/p3060qds.h b/tools/pblimage.h index 3da6815f0ff..514a477ca45 100644 --- a/board/freescale/p3060qds/p3060qds.h +++ b/tools/pblimage.h @@ -1,5 +1,8 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -8,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -17,14 +20,17 @@ * MA 02111-1307 USA */ -#ifndef __P3060QDS_H__ -#define __P3060QDS_H__ +#ifndef PBLIMAGE_H +#define PBLIMAGE_H -#include <asm/fsl_ddr_sdram.h> -#include <asm/u-boot.h> +#define RCW_BYTES 64 +#define RCW_PREAMBLE 0xaa55aa55 +#define RCW_HEADER 0x010e0100 -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); -extern fixed_ddr_parm_t fixed_ddr_parm_0[]; +struct pbl_header { + uint32_t preamble; + uint32_t rcwheader; + uint8_t rcw_data[RCW_BYTES]; +}; -#endif +#endif /* PBLIMAGE_H */ |